merge

1 files changed, 1 insertions, 0 deletions

diff --git a/TODO b/TODO
index d5ff2955..44d194b8 100644
--- a/TODO
+++ b/TODO
@@ -102,6 +102,7 @@ Fast C++ where wires/register/instances are predicated
 Verilog backend - put stuff in posedge clock, not assign statements, for speedup
 Annotate mems with location stuff
 Coverage tests, such as statespace or specific instances (like asserts, sort of)
+   check all predicates of whens
 
 ======== FIRRTL++ =========
 Variable size FIFOs