Updated tests for previous change that removed RemoveScope test from the StandardVerilogCompiler

1 files changed, 0 insertions, 1 deletions

diff --git a/TODO b/TODO
index b8086632..1c85c5f1 100644
--- a/TODO
+++ b/TODO
@@ -3,7 +3,6 @@ Support ASIC backend
      Mem of vec, should just work?
    ASIC rams (pass to replace smem with black box)
    Readwrite Port
-Move WorkingIR->RealIR right after width inference, update other passes accordingly
 
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 ========== ADAM's BIG ARSE TODO LIST ============