From 4726d8b6ca56435d861cb74f52f1237e3b43ae38 Mon Sep 17 00:00:00 2001
From: azidar
Date: Thu, 1 Oct 2015 09:59:38 -0700
Subject: Updated tests for previous change that removed RemoveScope test from
 the StandardVerilogCompiler

---
 TODO | 1 -
 1 file changed, 1 deletion(-)

(limited to 'TODO')

diff --git a/TODO b/TODO
index b8086632..1c85c5f1 100644
--- a/TODO
+++ b/TODO
@@ -3,7 +3,6 @@ Support ASIC backend
      Mem of vec, should just work?
    ASIC rams (pass to replace smem with black box)
    Readwrite Port
-Move WorkingIR->RealIR right after width inference, update other passes accordingly
 
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 ========== ADAM's BIG ARSE TODO LIST ============
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