diff options
| author | Andrew Waterman | 2016-01-28 22:48:55 -0800 |
|---|---|---|
| committer | Andrew Waterman | 2016-01-28 22:48:55 -0800 |
| commit | f9d329b91ba5a57dfaca7367fbe14d6f85de672f (patch) | |
| tree | 69d62d9c84ff62b97d594b9350cef73336192f81 | |
| parent | 8530eeae4ca34acf2cb40b46e6676951733b3ab7 (diff) | |
Update rocket regression
| -rw-r--r-- | regress/rocket.fir | 58454 |
1 files changed, 24835 insertions, 33619 deletions
diff --git a/regress/rocket.fir b/regress/rocket.fir index b6a765e5..0089cd03 100644 --- a/regress/rocket.fir +++ b/regress/rocket.fir @@ -4,438 +4,381 @@ circuit Top : input reset : UInt<1> output io : {host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_csr : UInt<1>}, flip cpu : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}[1], mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, scr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io.scr.resp.ready <= UInt<1>("h00") - io.scr.req.bits.data <= UInt<1>("h00") - io.scr.req.bits.addr <= UInt<1>("h00") - io.scr.req.bits.rw <= UInt<1>("h00") - io.scr.req.valid <= UInt<1>("h00") - io.mem.grant.ready <= UInt<1>("h00") - io.mem.acquire.bits.data <= UInt<1>("h00") - io.mem.acquire.bits.union <= UInt<1>("h00") - io.mem.acquire.bits.a_type <= UInt<1>("h00") - io.mem.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.mem.acquire.bits.addr_beat <= UInt<1>("h00") - io.mem.acquire.bits.client_xact_id <= UInt<1>("h00") - io.mem.acquire.bits.addr_block <= UInt<1>("h00") - io.mem.acquire.valid <= UInt<1>("h00") - io.cpu[0].csr.resp.ready <= UInt<1>("h00") - io.cpu[0].csr.req.bits.data <= UInt<1>("h00") - io.cpu[0].csr.req.bits.addr <= UInt<1>("h00") - io.cpu[0].csr.req.bits.rw <= UInt<1>("h00") - io.cpu[0].csr.req.valid <= UInt<1>("h00") - io.cpu[0].id <= UInt<1>("h00") - io.cpu[0].reset <= UInt<1>("h00") - io.host.debug_stats_csr <= UInt<1>("h00") - io.host.out.bits <= UInt<1>("h00") - io.host.out.valid <= UInt<1>("h00") - io.host.in.ready <= UInt<1>("h00") - io.host.clk_edge <= UInt<1>("h00") - io.host.clk <= UInt<1>("h00") + io is invalid io.host.debug_stats_csr <= io.cpu[0].debug_stats_csr - reg rx_count : UInt<15>, clk, reset, UInt<15>("h00") - reg rx_shifter : UInt<64>, clk, UInt<1>("h00"), rx_shifter + reg rx_count : UInt<15>, clk with : (reset => (reset, UInt<15>("h00"))) + reg rx_shifter : UInt<64>, clk node T_1212 = bits(rx_shifter, 63, 16) node rx_shifter_in = cat(io.host.in.bits, T_1212) node next_cmd = bits(rx_shifter_in, 3, 0) - reg cmd : UInt<?>, clk, UInt<1>("h00"), cmd - reg size : UInt<?>, clk, UInt<1>("h00"), size - reg pos : UInt<?>, clk, UInt<1>("h00"), pos - reg seqno : UInt<?>, clk, UInt<1>("h00"), seqno - reg addr : UInt<?>, clk, UInt<1>("h00"), addr + reg cmd : UInt<?>, clk + reg size : UInt<?>, clk + reg pos : UInt<?>, clk + reg seqno : UInt<?>, clk + reg addr : UInt<?>, clk node T_1225 = and(io.host.in.valid, io.host.in.ready) when T_1225 : rx_shifter <= rx_shifter_in - node T_1227 = addw(rx_count, UInt<1>("h01")) - rx_count <= T_1227 - node T_1229 = eq(rx_count, UInt<2>("h03")) - when T_1229 : + node T_1227 = add(rx_count, UInt<1>("h01")) + node T_1228 = tail(T_1227, 1) + rx_count <= T_1228 + node T_1230 = eq(rx_count, UInt<2>("h03")) + when T_1230 : cmd <= next_cmd - node T_1230 = bits(rx_shifter_in, 15, 4) - size <= T_1230 - node T_1231 = bits(rx_shifter_in, 15, 7) - pos <= T_1231 - node T_1232 = bits(rx_shifter_in, 23, 16) - seqno <= T_1232 - node T_1233 = bits(rx_shifter_in, 63, 24) - addr <= T_1233 + node T_1231 = bits(rx_shifter_in, 15, 4) + size <= T_1231 + node T_1232 = bits(rx_shifter_in, 15, 7) + pos <= T_1232 + node T_1233 = bits(rx_shifter_in, 23, 16) + seqno <= T_1233 + node T_1234 = bits(rx_shifter_in, 63, 24) + addr <= T_1234 skip skip node rx_word_count = shr(rx_count, 2) - node T_1235 = bits(rx_count, 1, 0) - node T_1236 = not(T_1235) - node T_1238 = eq(T_1236, UInt<1>("h00")) - node rx_word_done = and(io.host.in.valid, T_1238) + node T_1236 = bits(rx_count, 1, 0) + node T_1237 = not(T_1236) + node T_1239 = eq(T_1237, UInt<1>("h00")) + node rx_word_done = and(io.host.in.valid, T_1239) cmem packet_ram : UInt<64>[8] - node T_1243 = and(rx_word_done, io.host.in.ready) - when T_1243 : - node T_1244 = bits(rx_word_count, 2, 0) - node T_1246 = subw(T_1244, UInt<1>("h01")) - infer mport T_1247 = packet_ram[T_1246], clk - T_1247 <= rx_shifter_in + node T_1244 = and(rx_word_done, io.host.in.ready) + when T_1244 : + node T_1245 = bits(rx_word_count, 2, 0) + node T_1247 = sub(T_1245, UInt<1>("h01")) + node T_1248 = tail(T_1247, 1) + infer mport T_1249 = packet_ram[T_1248], clk + T_1249 <= rx_shifter_in skip node csr_addr = bits(addr, 11, 0) node csr_coreid = bits(addr, 21, 20) infer mport csr_wdata = packet_ram[UInt<1>("h00")], clk - node T_1259 = bits(size, 2, 0) - node T_1261 = neq(T_1259, UInt<1>("h00")) - node T_1262 = bits(addr, 2, 0) - node T_1264 = neq(T_1262, UInt<1>("h00")) - node bad_mem_packet = or(T_1261, T_1264) - node T_1266 = eq(cmd, UInt<1>("h00")) - node T_1267 = eq(cmd, UInt<1>("h01")) - node T_1268 = or(T_1266, T_1267) - node T_1269 = eq(cmd, UInt<2>("h02")) - node T_1270 = eq(cmd, UInt<2>("h03")) - node T_1271 = or(T_1269, T_1270) - node T_1273 = neq(size, UInt<1>("h01")) - node T_1275 = mux(T_1271, T_1273, UInt<1>("h01")) - node nack = mux(T_1268, bad_mem_packet, T_1275) - reg tx_count : UInt<15>, clk, reset, UInt<15>("h00") + node T_1261 = bits(size, 2, 0) + node T_1263 = neq(T_1261, UInt<1>("h00")) + node T_1264 = bits(addr, 2, 0) + node T_1266 = neq(T_1264, UInt<1>("h00")) + node bad_mem_packet = or(T_1263, T_1266) + node T_1268 = eq(cmd, UInt<1>("h00")) + node T_1269 = eq(cmd, UInt<1>("h01")) + node T_1270 = or(T_1268, T_1269) + node T_1271 = eq(cmd, UInt<2>("h02")) + node T_1272 = eq(cmd, UInt<2>("h03")) + node T_1273 = or(T_1271, T_1272) + node T_1275 = neq(size, UInt<1>("h01")) + node T_1277 = mux(T_1273, T_1275, UInt<1>("h01")) + node nack = mux(T_1270, bad_mem_packet, T_1277) + reg tx_count : UInt<15>, clk with : (reset => (reset, UInt<15>("h00"))) node tx_subword_count = bits(tx_count, 1, 0) node tx_word_count = bits(tx_count, 14, 2) - node T_1281 = bits(tx_word_count, 2, 0) - node packet_ram_raddr = subw(T_1281, UInt<1>("h01")) - node T_1284 = and(io.host.out.valid, io.host.out.ready) - when T_1284 : - node T_1286 = addw(tx_count, UInt<1>("h01")) - tx_count <= T_1286 - skip - node T_1288 = eq(rx_word_count, UInt<1>("h00")) - node T_1289 = neq(next_cmd, UInt<1>("h01")) - node T_1290 = neq(next_cmd, UInt<2>("h03")) - node T_1291 = and(T_1289, T_1290) - node T_1292 = eq(rx_word_count, size) - node T_1293 = bits(rx_word_count, 2, 0) - node T_1295 = eq(T_1293, UInt<1>("h00")) - node T_1296 = or(T_1292, T_1295) - node T_1297 = mux(T_1288, T_1291, T_1296) - node rx_done = and(rx_word_done, T_1297) - node T_1300 = eq(nack, UInt<1>("h00")) - node T_1301 = eq(cmd, UInt<1>("h00")) - node T_1302 = eq(cmd, UInt<2>("h02")) - node T_1303 = or(T_1301, T_1302) - node T_1304 = eq(cmd, UInt<2>("h03")) - node T_1305 = or(T_1303, T_1304) - node T_1306 = and(T_1300, T_1305) - node tx_size = mux(T_1306, size, UInt<1>("h00")) - node T_1309 = not(tx_subword_count) - node T_1311 = eq(T_1309, UInt<1>("h00")) - node T_1312 = and(io.host.out.ready, T_1311) - node T_1313 = eq(tx_word_count, tx_size) - node T_1315 = gt(tx_word_count, UInt<1>("h00")) - node T_1316 = not(packet_ram_raddr) - node T_1318 = eq(T_1316, UInt<1>("h00")) - node T_1319 = and(T_1315, T_1318) - node T_1320 = or(T_1313, T_1319) - node tx_done = and(T_1312, T_1320) - reg state : UInt<?>, clk, reset, UInt<1>("h00") - node T_1332 = eq(state, UInt<3>("h04")) - node T_1333 = and(T_1332, io.mem.acquire.ready) - node T_1334 = eq(state, UInt<3>("h05")) - node T_1335 = and(T_1334, io.mem.grant.valid) - node T_1336 = or(T_1333, T_1335) - reg cnt : UInt<2>, clk, reset, UInt<2>("h00") - when T_1336 : - node T_1340 = eq(cnt, UInt<2>("h03")) - node T_1342 = and(UInt<1>("h00"), T_1340) - node T_1345 = addw(cnt, UInt<1>("h01")) - node T_1346 = mux(T_1342, UInt<1>("h00"), T_1345) - cnt <= T_1346 - skip - node cnt_done = and(T_1336, T_1340) - node T_1349 = eq(rx_word_count, UInt<1>("h00")) - node rx_cmd = mux(T_1349, next_cmd, cmd) - node T_1351 = eq(state, UInt<1>("h00")) - node T_1352 = and(T_1351, rx_done) - when T_1352 : - node T_1353 = eq(rx_cmd, UInt<1>("h00")) - node T_1354 = eq(rx_cmd, UInt<1>("h01")) - node T_1355 = eq(rx_cmd, UInt<2>("h02")) - node T_1356 = eq(rx_cmd, UInt<2>("h03")) - node T_1357 = or(T_1355, T_1356) - node T_1358 = mux(T_1357, UInt<1>("h01"), UInt<3>("h07")) - node T_1359 = mux(T_1354, UInt<3>("h04"), T_1358) - node T_1360 = mux(T_1353, UInt<2>("h03"), T_1359) - state <= T_1360 - skip - node T_1361 = eq(state, UInt<3>("h04")) - when T_1361 : + node T_1283 = bits(tx_word_count, 2, 0) + node T_1285 = sub(T_1283, UInt<1>("h01")) + node packet_ram_raddr = tail(T_1285, 1) + node T_1287 = and(io.host.out.valid, io.host.out.ready) + when T_1287 : + node T_1289 = add(tx_count, UInt<1>("h01")) + node T_1290 = tail(T_1289, 1) + tx_count <= T_1290 + skip + node T_1292 = eq(rx_word_count, UInt<1>("h00")) + node T_1293 = neq(next_cmd, UInt<1>("h01")) + node T_1294 = neq(next_cmd, UInt<2>("h03")) + node T_1295 = and(T_1293, T_1294) + node T_1296 = eq(rx_word_count, size) + node T_1297 = bits(rx_word_count, 2, 0) + node T_1299 = eq(T_1297, UInt<1>("h00")) + node T_1300 = or(T_1296, T_1299) + node T_1301 = mux(T_1292, T_1295, T_1300) + node rx_done = and(rx_word_done, T_1301) + node T_1304 = eq(nack, UInt<1>("h00")) + node T_1305 = eq(cmd, UInt<1>("h00")) + node T_1306 = eq(cmd, UInt<2>("h02")) + node T_1307 = or(T_1305, T_1306) + node T_1308 = eq(cmd, UInt<2>("h03")) + node T_1309 = or(T_1307, T_1308) + node T_1310 = and(T_1304, T_1309) + node tx_size = mux(T_1310, size, UInt<1>("h00")) + node T_1313 = not(tx_subword_count) + node T_1315 = eq(T_1313, UInt<1>("h00")) + node T_1316 = and(io.host.out.ready, T_1315) + node T_1317 = eq(tx_word_count, tx_size) + node T_1319 = gt(tx_word_count, UInt<1>("h00")) + node T_1320 = not(packet_ram_raddr) + node T_1322 = eq(T_1320, UInt<1>("h00")) + node T_1323 = and(T_1319, T_1322) + node T_1324 = or(T_1317, T_1323) + node tx_done = and(T_1316, T_1324) + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_1336 = eq(state, UInt<3>("h04")) + node T_1337 = and(T_1336, io.mem.acquire.ready) + node T_1338 = eq(state, UInt<3>("h05")) + node T_1339 = and(T_1338, io.mem.grant.valid) + node T_1340 = or(T_1337, T_1339) + reg cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_1340 : + node T_1344 = eq(cnt, UInt<2>("h03")) + node T_1346 = and(UInt<1>("h00"), T_1344) + node T_1349 = add(cnt, UInt<1>("h01")) + node T_1350 = tail(T_1349, 1) + node T_1351 = mux(T_1346, UInt<1>("h00"), T_1350) + cnt <= T_1351 + skip + node cnt_done = and(T_1340, T_1344) + node T_1354 = eq(rx_word_count, UInt<1>("h00")) + node rx_cmd = mux(T_1354, next_cmd, cmd) + node T_1356 = eq(state, UInt<1>("h00")) + node T_1357 = and(T_1356, rx_done) + when T_1357 : + node T_1358 = eq(rx_cmd, UInt<1>("h00")) + node T_1359 = eq(rx_cmd, UInt<1>("h01")) + node T_1360 = eq(rx_cmd, UInt<2>("h02")) + node T_1361 = eq(rx_cmd, UInt<2>("h03")) + node T_1362 = or(T_1360, T_1361) + node T_1363 = mux(T_1362, UInt<1>("h01"), UInt<3>("h07")) + node T_1364 = mux(T_1359, UInt<3>("h04"), T_1363) + node T_1365 = mux(T_1358, UInt<2>("h03"), T_1364) + state <= T_1365 + skip + node T_1366 = eq(state, UInt<3>("h04")) + when T_1366 : when cnt_done : state <= UInt<3>("h06") skip skip - node T_1362 = eq(state, UInt<2>("h03")) - when T_1362 : + node T_1367 = eq(state, UInt<2>("h03")) + when T_1367 : when io.mem.acquire.ready : state <= UInt<3>("h05") skip skip - node T_1363 = eq(state, UInt<3>("h06")) - node T_1364 = and(T_1363, io.mem.grant.valid) - when T_1364 : - node T_1365 = eq(cmd, UInt<1>("h00")) - node T_1367 = eq(pos, UInt<1>("h01")) - node T_1368 = or(T_1365, T_1367) - node T_1369 = mux(T_1368, UInt<3>("h07"), UInt<1>("h00")) - state <= T_1369 - node T_1371 = subw(pos, UInt<1>("h01")) - pos <= T_1371 - node T_1373 = addw(addr, UInt<4>("h08")) - addr <= T_1373 - skip - node T_1374 = eq(state, UInt<3>("h05")) - node T_1375 = and(T_1374, cnt_done) - when T_1375 : - node T_1376 = eq(cmd, UInt<1>("h00")) - node T_1378 = eq(pos, UInt<1>("h01")) - node T_1379 = or(T_1376, T_1378) - node T_1380 = mux(T_1379, UInt<3>("h07"), UInt<1>("h00")) - state <= T_1380 - node T_1382 = subw(pos, UInt<1>("h01")) - pos <= T_1382 - node T_1384 = addw(addr, UInt<4>("h08")) - addr <= T_1384 - skip - node T_1385 = eq(state, UInt<3>("h07")) - node T_1386 = and(T_1385, tx_done) - when T_1386 : - node T_1387 = eq(tx_word_count, tx_size) - when T_1387 : + node T_1368 = eq(state, UInt<3>("h06")) + node T_1369 = and(T_1368, io.mem.grant.valid) + when T_1369 : + node T_1370 = eq(cmd, UInt<1>("h00")) + node T_1372 = eq(pos, UInt<1>("h01")) + node T_1373 = or(T_1370, T_1372) + node T_1374 = mux(T_1373, UInt<3>("h07"), UInt<1>("h00")) + state <= T_1374 + node T_1376 = sub(pos, UInt<1>("h01")) + node T_1377 = tail(T_1376, 1) + pos <= T_1377 + node T_1379 = add(addr, UInt<4>("h08")) + node T_1380 = tail(T_1379, 1) + addr <= T_1380 + skip + node T_1381 = eq(state, UInt<3>("h05")) + node T_1382 = and(T_1381, cnt_done) + when T_1382 : + node T_1383 = eq(cmd, UInt<1>("h00")) + node T_1385 = eq(pos, UInt<1>("h01")) + node T_1386 = or(T_1383, T_1385) + node T_1387 = mux(T_1386, UInt<3>("h07"), UInt<1>("h00")) + state <= T_1387 + node T_1389 = sub(pos, UInt<1>("h01")) + node T_1390 = tail(T_1389, 1) + pos <= T_1390 + node T_1392 = add(addr, UInt<4>("h08")) + node T_1393 = tail(T_1392, 1) + addr <= T_1393 + skip + node T_1394 = eq(state, UInt<3>("h07")) + node T_1395 = and(T_1394, tx_done) + when T_1395 : + node T_1396 = eq(tx_word_count, tx_size) + when T_1396 : rx_count <= UInt<1>("h00") tx_count <= UInt<1>("h00") skip - node T_1390 = eq(cmd, UInt<1>("h00")) - node T_1392 = neq(pos, UInt<1>("h00")) - node T_1393 = and(T_1390, T_1392) - node T_1394 = mux(T_1393, UInt<2>("h03"), UInt<1>("h00")) - state <= T_1394 - skip - node T_1396 = eq(state, UInt<3>("h05")) - node T_1397 = and(T_1396, io.mem.grant.valid) - when T_1397 : - node T_1398 = cat(io.mem.grant.bits.addr_beat, UInt<1>("h00")) - infer mport T_1399 = packet_ram[T_1398], clk - node T_1400 = bits(io.mem.grant.bits.data, 63, 0) - T_1399 <= T_1400 - skip - node T_1401 = cat(cnt, UInt<1>("h00")) - infer mport T_1402 = packet_ram[T_1401], clk - node T_1404 = eq(state, UInt<3>("h05")) - node T_1405 = and(T_1404, io.mem.grant.valid) - when T_1405 : - node T_1406 = cat(io.mem.grant.bits.addr_beat, UInt<1>("h01")) - infer mport T_1407 = packet_ram[T_1406], clk - node T_1408 = bits(io.mem.grant.bits.data, 127, 64) - T_1407 <= T_1408 - skip - node T_1409 = cat(cnt, UInt<1>("h01")) - infer mport T_1410 = packet_ram[T_1409], clk - node mem_req_data = cat(T_1410, T_1402) + node T_1399 = eq(cmd, UInt<1>("h00")) + node T_1401 = neq(pos, UInt<1>("h00")) + node T_1402 = and(T_1399, T_1401) + node T_1403 = mux(T_1402, UInt<2>("h03"), UInt<1>("h00")) + state <= T_1403 + skip + node T_1405 = eq(state, UInt<3>("h05")) + node T_1406 = and(T_1405, io.mem.grant.valid) + when T_1406 : + node T_1407 = cat(io.mem.grant.bits.addr_beat, UInt<1>("h00")) + infer mport T_1408 = packet_ram[T_1407], clk + node T_1409 = bits(io.mem.grant.bits.data, 63, 0) + T_1408 <= T_1409 + skip + node T_1410 = cat(cnt, UInt<1>("h00")) + infer mport T_1411 = packet_ram[T_1410], clk + node T_1413 = eq(state, UInt<3>("h05")) + node T_1414 = and(T_1413, io.mem.grant.valid) + when T_1414 : + node T_1415 = cat(io.mem.grant.bits.addr_beat, UInt<1>("h01")) + infer mport T_1416 = packet_ram[T_1415], clk + node T_1417 = bits(io.mem.grant.bits.data, 127, 64) + T_1416 <= T_1417 + skip + node T_1418 = cat(cnt, UInt<1>("h01")) + infer mport T_1419 = packet_ram[T_1418], clk + node mem_req_data = cat(T_1419, T_1411) node init_addr = shr(addr, 3) - node T_1413 = eq(state, UInt<2>("h03")) - node T_1414 = eq(state, UInt<3>("h04")) - node T_1415 = or(T_1413, T_1414) - io.mem.acquire.valid <= T_1415 - node T_1416 = eq(cmd, UInt<1>("h01")) - node T_1444 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_1450 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1451 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1452 = cat(T_1450, T_1451) - node T_1454 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1455 = cat(UInt<3>("h07"), T_1454) - node T_1457 = cat(T_1444, UInt<1>("h01")) - node T_1459 = cat(T_1444, UInt<1>("h01")) - node T_1461 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1462 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1463 = cat(T_1461, T_1462) - node T_1465 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1467 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1468 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_1469 = mux(T_1468, T_1467, UInt<1>("h00")) - node T_1470 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_1471 = mux(T_1470, T_1465, T_1469) - node T_1472 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_1473 = mux(T_1472, T_1463, T_1471) - node T_1474 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_1475 = mux(T_1474, T_1459, T_1473) - node T_1476 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_1477 = mux(T_1476, T_1457, T_1475) - node T_1478 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_1479 = mux(T_1478, T_1455, T_1477) - node T_1480 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_1481 = mux(T_1480, T_1452, T_1479) - wire T_1513 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1513.data <= UInt<1>("h00") - T_1513.union <= UInt<1>("h00") - T_1513.a_type <= UInt<1>("h00") - T_1513.is_builtin_type <= UInt<1>("h00") - T_1513.addr_beat <= UInt<1>("h00") - T_1513.client_xact_id <= UInt<1>("h00") - T_1513.addr_block <= UInt<1>("h00") - T_1513.is_builtin_type <= UInt<1>("h01") - T_1513.a_type <= UInt<3>("h03") - T_1513.client_xact_id <= UInt<1>("h00") - T_1513.addr_block <= init_addr - T_1513.addr_beat <= cnt - T_1513.data <= mem_req_data - T_1513.union <= T_1481 - node T_1561 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1562 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1563 = cat(T_1561, T_1562) - node T_1565 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1566 = cat(UInt<3>("h07"), T_1565) - node T_1568 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_1422 = eq(state, UInt<2>("h03")) + node T_1423 = eq(state, UInt<3>("h04")) + node T_1424 = or(T_1422, T_1423) + io.mem.acquire.valid <= T_1424 + node T_1425 = eq(cmd, UInt<1>("h01")) + node T_1453 = asUInt(asSInt(UInt<16>("h0ffff"))) + node T_1459 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_1460 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_1461 = cat(T_1459, T_1460) + node T_1463 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_1464 = cat(UInt<3>("h07"), T_1463) + node T_1466 = cat(T_1453, UInt<1>("h01")) + node T_1468 = cat(T_1453, UInt<1>("h01")) + node T_1470 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_1471 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_1472 = cat(T_1470, T_1471) + node T_1474 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1476 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_1477 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_1478 = mux(T_1477, T_1476, UInt<1>("h00")) + node T_1479 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_1480 = mux(T_1479, T_1474, T_1478) + node T_1481 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_1482 = mux(T_1481, T_1472, T_1480) + node T_1483 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_1484 = mux(T_1483, T_1468, T_1482) + node T_1485 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_1486 = mux(T_1485, T_1466, T_1484) + node T_1487 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_1488 = mux(T_1487, T_1464, T_1486) + node T_1489 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_1490 = mux(T_1489, T_1461, T_1488) + wire T_1522 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} + T_1522 is invalid + T_1522.is_builtin_type <= UInt<1>("h01") + T_1522.a_type <= UInt<3>("h03") + T_1522.client_xact_id <= UInt<1>("h00") + T_1522.addr_block <= init_addr + T_1522.addr_beat <= cnt + T_1522.data <= mem_req_data + T_1522.union <= T_1490 + node T_1563 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_1564 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1565 = cat(T_1563, T_1564) + node T_1567 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1568 = cat(UInt<3>("h07"), T_1567) node T_1570 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1572 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1573 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1574 = cat(T_1572, T_1573) - node T_1576 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1578 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1579 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_1580 = mux(T_1579, T_1578, UInt<1>("h00")) - node T_1581 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_1582 = mux(T_1581, T_1576, T_1580) - node T_1583 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_1584 = mux(T_1583, T_1574, T_1582) - node T_1585 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_1586 = mux(T_1585, T_1570, T_1584) - node T_1587 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_1588 = mux(T_1587, T_1568, T_1586) - node T_1589 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_1590 = mux(T_1589, T_1566, T_1588) - node T_1591 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_1592 = mux(T_1591, T_1563, T_1590) - wire T_1624 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1624.data <= UInt<1>("h00") - T_1624.union <= UInt<1>("h00") - T_1624.a_type <= UInt<1>("h00") - T_1624.is_builtin_type <= UInt<1>("h00") - T_1624.addr_beat <= UInt<1>("h00") - T_1624.client_xact_id <= UInt<1>("h00") - T_1624.addr_block <= UInt<1>("h00") - T_1624.is_builtin_type <= UInt<1>("h01") - T_1624.a_type <= UInt<3>("h01") - T_1624.client_xact_id <= UInt<1>("h00") - T_1624.addr_block <= init_addr - T_1624.addr_beat <= UInt<1>("h00") - T_1624.data <= UInt<1>("h00") - T_1624.union <= T_1592 - wire T_1693 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1693 <- T_1624 - when T_1416 : - T_1693 <- T_1513 - skip - io.mem.acquire.bits <- T_1693 + node T_1572 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_1574 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_1575 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1576 = cat(T_1574, T_1575) + node T_1578 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1580 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_1581 = eq(UInt<3>("h06"), UInt<3>("h01")) + node T_1582 = mux(T_1581, T_1580, UInt<1>("h00")) + node T_1583 = eq(UInt<3>("h05"), UInt<3>("h01")) + node T_1584 = mux(T_1583, T_1578, T_1582) + node T_1585 = eq(UInt<3>("h04"), UInt<3>("h01")) + node T_1586 = mux(T_1585, T_1576, T_1584) + node T_1587 = eq(UInt<3>("h03"), UInt<3>("h01")) + node T_1588 = mux(T_1587, T_1572, T_1586) + node T_1589 = eq(UInt<3>("h02"), UInt<3>("h01")) + node T_1590 = mux(T_1589, T_1570, T_1588) + node T_1591 = eq(UInt<3>("h01"), UInt<3>("h01")) + node T_1592 = mux(T_1591, T_1568, T_1590) + node T_1593 = eq(UInt<3>("h00"), UInt<3>("h01")) + node T_1594 = mux(T_1593, T_1565, T_1592) + wire T_1626 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} + T_1626 is invalid + T_1626.is_builtin_type <= UInt<1>("h01") + T_1626.a_type <= UInt<3>("h01") + T_1626.client_xact_id <= UInt<1>("h00") + T_1626.addr_block <= init_addr + T_1626.addr_beat <= UInt<1>("h00") + T_1626.data <= UInt<1>("h00") + T_1626.union <= T_1594 + node T_1657 = mux(T_1425, T_1522, T_1626) + io.mem.acquire.bits <- T_1657 io.mem.grant.ready <= UInt<1>("h01") - reg csrReadData : UInt<64>, clk, UInt<1>("h00"), csrReadData - reg T_1728 : UInt<1>, clk, reset, UInt<1>("h01") - node T_1730 = eq(csr_coreid, UInt<1>("h00")) - node T_1731 = eq(state, UInt<1>("h01")) - node T_1732 = and(T_1731, T_1730) - node T_1734 = neq(csr_addr, UInt<11>("h0782")) - node T_1735 = and(T_1732, T_1734) - io.cpu[0].csr.req.valid <= T_1735 - node T_1736 = eq(cmd, UInt<2>("h03")) - io.cpu[0].csr.req.bits.rw <= T_1736 + reg csrReadData : UInt<64>, clk + reg T_1692 : UInt<1>, clk with : (reset => (reset, UInt<1>("h01"))) + node T_1694 = eq(csr_coreid, UInt<1>("h00")) + node T_1695 = eq(state, UInt<1>("h01")) + node T_1696 = and(T_1695, T_1694) + node T_1698 = neq(csr_addr, UInt<11>("h0782")) + node T_1699 = and(T_1696, T_1698) + io.cpu[0].csr.req.valid <= T_1699 + node T_1700 = eq(cmd, UInt<2>("h03")) + io.cpu[0].csr.req.bits.rw <= T_1700 io.cpu[0].csr.req.bits.addr <= csr_addr io.cpu[0].csr.req.bits.data <= csr_wdata - io.cpu[0].reset <= T_1728 - node T_1737 = and(io.cpu[0].csr.req.ready, io.cpu[0].csr.req.valid) - when T_1737 : + io.cpu[0].reset <= T_1692 + node T_1701 = and(io.cpu[0].csr.req.ready, io.cpu[0].csr.req.valid) + when T_1701 : state <= UInt<2>("h02") skip - node T_1738 = eq(state, UInt<1>("h01")) - node T_1739 = and(T_1738, T_1730) - node T_1741 = eq(csr_addr, UInt<11>("h0782")) - node T_1742 = and(T_1739, T_1741) - when T_1742 : - node T_1743 = eq(cmd, UInt<2>("h03")) - when T_1743 : - node T_1744 = bit(csr_wdata, 0) - T_1728 <= T_1744 - skip - csrReadData <= T_1728 + node T_1702 = eq(state, UInt<1>("h01")) + node T_1703 = and(T_1702, T_1694) + node T_1705 = eq(csr_addr, UInt<11>("h0782")) + node T_1706 = and(T_1703, T_1705) + when T_1706 : + node T_1707 = eq(cmd, UInt<2>("h03")) + when T_1707 : + node T_1708 = bits(csr_wdata, 0, 0) + T_1692 <= T_1708 + skip + csrReadData <= T_1692 state <= UInt<3>("h07") skip io.cpu[0].csr.resp.ready <= UInt<1>("h01") - node T_1746 = eq(state, UInt<2>("h02")) - node T_1747 = and(T_1746, io.cpu[0].csr.resp.valid) - when T_1747 : + node T_1710 = eq(state, UInt<2>("h02")) + node T_1711 = and(T_1710, io.cpu[0].csr.resp.valid) + when T_1711 : csrReadData <= io.cpu[0].csr.resp.bits state <= UInt<3>("h07") skip - node T_1748 = eq(state, UInt<1>("h01")) - node T_1749 = not(csr_coreid) - node T_1751 = eq(T_1749, UInt<1>("h00")) - node T_1752 = and(T_1748, T_1751) - io.scr.req.valid <= T_1752 - node T_1753 = bits(addr, 5, 0) - io.scr.req.bits.addr <= T_1753 + node T_1712 = eq(state, UInt<1>("h01")) + node T_1713 = not(csr_coreid) + node T_1715 = eq(T_1713, UInt<1>("h00")) + node T_1716 = and(T_1712, T_1715) + io.scr.req.valid <= T_1716 + node T_1717 = bits(addr, 5, 0) + io.scr.req.bits.addr <= T_1717 io.scr.req.bits.data <= csr_wdata - node T_1754 = eq(cmd, UInt<2>("h03")) - io.scr.req.bits.rw <= T_1754 + node T_1718 = eq(cmd, UInt<2>("h03")) + io.scr.req.bits.rw <= T_1718 io.scr.resp.ready <= UInt<1>("h01") - node T_1756 = and(io.scr.req.ready, io.scr.req.valid) - when T_1756 : + node T_1720 = and(io.scr.req.ready, io.scr.req.valid) + when T_1720 : state <= UInt<2>("h02") skip - node T_1757 = eq(state, UInt<2>("h02")) - node T_1758 = and(T_1757, io.scr.resp.valid) - when T_1758 : + node T_1721 = eq(state, UInt<2>("h02")) + node T_1722 = and(T_1721, io.scr.resp.valid) + when T_1722 : csrReadData <= io.scr.resp.bits state <= UInt<3>("h07") skip node tx_cmd = mux(nack, UInt<3>("h05"), UInt<3>("h04")) node tx_cmd_ext = cat(UInt<1>("h00"), tx_cmd) - node T_1762 = cat(addr, seqno) - node T_1763 = cat(tx_size, tx_cmd_ext) - node tx_header = cat(T_1762, T_1763) - node T_1766 = eq(tx_word_count, UInt<1>("h00")) - node T_1767 = eq(cmd, UInt<2>("h02")) - node T_1768 = eq(cmd, UInt<2>("h03")) - node T_1769 = or(T_1767, T_1768) - infer mport T_1770 = packet_ram[packet_ram_raddr], clk - node T_1771 = mux(T_1769, csrReadData, T_1770) - node tx_data = mux(T_1766, tx_header, T_1771) - node T_1773 = eq(state, UInt<1>("h00")) - io.host.in.ready <= T_1773 - node T_1774 = eq(state, UInt<3>("h07")) - io.host.out.valid <= T_1774 - node T_1775 = bits(tx_count, 1, 0) - node T_1777 = cat(T_1775, UInt<4>("h00")) - node T_1778 = dshr(tx_data, T_1777) - io.host.out.bits <= T_1778 + node T_1726 = cat(addr, seqno) + node T_1727 = cat(tx_size, tx_cmd_ext) + node tx_header = cat(T_1726, T_1727) + node T_1730 = eq(tx_word_count, UInt<1>("h00")) + node T_1731 = eq(cmd, UInt<2>("h02")) + node T_1732 = eq(cmd, UInt<2>("h03")) + node T_1733 = or(T_1731, T_1732) + infer mport T_1734 = packet_ram[packet_ram_raddr], clk + node T_1735 = mux(T_1733, csrReadData, T_1734) + node tx_data = mux(T_1730, tx_header, T_1735) + node T_1737 = eq(state, UInt<1>("h00")) + io.host.in.ready <= T_1737 + node T_1738 = eq(state, UInt<3>("h07")) + io.host.out.valid <= T_1738 + node T_1739 = bits(tx_count, 1, 0) + node T_1741 = cat(T_1739, UInt<4>("h00")) + node T_1742 = dshr(tx_data, T_1741) + io.host.out.bits <= T_1742 module ClientTileLinkIOWrapper : input clk : Clock input reset : UInt<1> output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}} - io.out.release.bits.data <= UInt<1>("h00") - io.out.release.bits.r_type <= UInt<1>("h00") - io.out.release.bits.voluntary <= UInt<1>("h00") - io.out.release.bits.client_xact_id <= UInt<1>("h00") - io.out.release.bits.addr_block <= UInt<1>("h00") - io.out.release.bits.addr_beat <= UInt<1>("h00") - io.out.release.valid <= UInt<1>("h00") - io.out.probe.ready <= UInt<1>("h00") - io.out.grant.ready <= UInt<1>("h00") - io.out.acquire.bits.data <= UInt<1>("h00") - io.out.acquire.bits.union <= UInt<1>("h00") - io.out.acquire.bits.a_type <= UInt<1>("h00") - io.out.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.out.acquire.bits.addr_beat <= UInt<1>("h00") - io.out.acquire.bits.client_xact_id <= UInt<1>("h00") - io.out.acquire.bits.addr_block <= UInt<1>("h00") - io.out.acquire.valid <= UInt<1>("h00") - io.in.grant.bits.data <= UInt<1>("h00") - io.in.grant.bits.g_type <= UInt<1>("h00") - io.in.grant.bits.is_builtin_type <= UInt<1>("h00") - io.in.grant.bits.manager_xact_id <= UInt<1>("h00") - io.in.grant.bits.client_xact_id <= UInt<1>("h00") - io.in.grant.bits.addr_beat <= UInt<1>("h00") - io.in.grant.valid <= UInt<1>("h00") - io.in.acquire.ready <= UInt<1>("h00") + io is invalid io.out.acquire <- io.in.acquire io.in.grant <- io.out.grant io.out.probe.ready <= UInt<1>("h01") @@ -446,15 +389,11 @@ circuit Top : input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}}, count : UInt<2>} - io.count <= UInt<1>("h00") - io.deq.bits.dst <= UInt<1>("h00") - io.deq.bits.fin.manager_xact_id <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem T_877 : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>}[2] - reg T_879 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_881 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_883 : UInt<1>, clk, reset, UInt<1>("h00") + reg T_879 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_881 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_883 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node T_884 = eq(T_879, T_881) node T_886 = eq(T_883, UInt<1>("h00")) node T_887 = and(T_884, T_886) @@ -472,59 +411,46 @@ circuit Top : T_900 <- io.enq.bits node T_997 = eq(T_879, UInt<1>("h01")) node T_999 = and(UInt<1>("h00"), T_997) - node T_1002 = addw(T_879, UInt<1>("h01")) - node T_1003 = mux(T_999, UInt<1>("h00"), T_1002) - T_879 <= T_1003 + node T_1002 = add(T_879, UInt<1>("h01")) + node T_1003 = tail(T_1002, 1) + node T_1004 = mux(T_999, UInt<1>("h00"), T_1003) + T_879 <= T_1004 skip when T_899 : - node T_1005 = eq(T_881, UInt<1>("h01")) - node T_1007 = and(UInt<1>("h00"), T_1005) - node T_1010 = addw(T_881, UInt<1>("h01")) - node T_1011 = mux(T_1007, UInt<1>("h00"), T_1010) - T_881 <= T_1011 - skip - node T_1012 = neq(T_895, T_899) - when T_1012 : + node T_1006 = eq(T_881, UInt<1>("h01")) + node T_1008 = and(UInt<1>("h00"), T_1006) + node T_1011 = add(T_881, UInt<1>("h01")) + node T_1012 = tail(T_1011, 1) + node T_1013 = mux(T_1008, UInt<1>("h00"), T_1012) + T_881 <= T_1013 + skip + node T_1014 = neq(T_895, T_899) + when T_1014 : T_883 <= T_895 skip - node T_1014 = eq(T_887, UInt<1>("h00")) - node T_1016 = and(UInt<1>("h00"), io.enq.valid) - node T_1017 = or(T_1014, T_1016) - io.deq.valid <= T_1017 - node T_1019 = eq(T_888, UInt<1>("h00")) - node T_1021 = and(UInt<1>("h00"), io.deq.ready) - node T_1022 = or(T_1019, T_1021) - io.enq.ready <= T_1022 - infer mport T_1023 = T_877[T_881], clk - wire T_1215 : {fin : {manager_xact_id : UInt<4>}, dst : UInt<2>} - T_1215 <- T_1023 - when T_890 : - T_1215 <- io.enq.bits - skip - io.deq.bits <- T_1215 - node T_1311 = subw(T_879, T_881) - node T_1312 = and(T_883, T_884) - node T_1313 = cat(T_1312, T_1311) - io.count <= T_1313 + node T_1016 = eq(T_887, UInt<1>("h00")) + node T_1018 = and(UInt<1>("h00"), io.enq.valid) + node T_1019 = or(T_1016, T_1018) + io.deq.valid <= T_1019 + node T_1021 = eq(T_888, UInt<1>("h00")) + node T_1023 = and(UInt<1>("h00"), io.deq.ready) + node T_1024 = or(T_1021, T_1023) + io.enq.ready <= T_1024 + infer mport T_1025 = T_877[T_881], clk + node T_1121 = mux(T_890, io.enq.bits, T_1025) + io.deq.bits <- T_1121 + node T_1217 = sub(T_879, T_881) + node T_1218 = tail(T_1217, 1) + node T_1219 = and(T_883, T_884) + node T_1220 = cat(T_1219, T_1218) + io.count <= T_1220 module FinishUnit : input clk : Clock input reset : UInt<1> output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, ready : UInt<1>} - io.ready <= UInt<1>("h00") - io.finish.bits.payload.manager_xact_id <= UInt<1>("h00") - io.finish.bits.header.dst <= UInt<1>("h00") - io.finish.bits.header.src <= UInt<1>("h00") - io.finish.valid <= UInt<1>("h00") - io.refill.bits.data <= UInt<1>("h00") - io.refill.bits.g_type <= UInt<1>("h00") - io.refill.bits.is_builtin_type <= UInt<1>("h00") - io.refill.bits.manager_xact_id <= UInt<1>("h00") - io.refill.bits.client_xact_id <= UInt<1>("h00") - io.refill.bits.addr_beat <= UInt<1>("h00") - io.refill.valid <= UInt<1>("h00") - io.grant.ready <= UInt<1>("h00") + io is invalid node T_1178 = and(io.grant.ready, io.grant.valid) wire T_1183 : UInt<3>[1] T_1183[0] <= UInt<3>("h05") @@ -540,183 +466,113 @@ circuit Top : node T_1199 = mux(io.grant.bits.payload.is_builtin_type, T_1188, T_1198) node T_1200 = and(UInt<1>("h01"), T_1199) node T_1201 = and(T_1178, T_1200) - reg T_1203 : UInt<2>, clk, reset, UInt<2>("h00") + reg T_1203 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) when T_1201 : node T_1205 = eq(T_1203, UInt<2>("h03")) node T_1207 = and(UInt<1>("h00"), T_1205) - node T_1210 = addw(T_1203, UInt<1>("h01")) - node T_1211 = mux(T_1207, UInt<1>("h00"), T_1210) - T_1203 <= T_1211 - skip - node T_1212 = and(T_1201, T_1205) - node T_1213 = mux(T_1200, T_1203, UInt<1>("h00")) - node T_1214 = mux(T_1200, T_1212, T_1178) - inst T_1311 of FinishQueue - T_1311.io.deq.ready <= UInt<1>("h00") - T_1311.io.enq.bits.dst <= UInt<1>("h00") - T_1311.io.enq.bits.fin.manager_xact_id <= UInt<1>("h00") - T_1311.io.enq.valid <= UInt<1>("h00") - T_1311.clk <= clk - T_1311.reset <= reset - node T_1316 = and(io.grant.ready, io.grant.valid) - node T_1319 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1321 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1322 = and(io.grant.bits.payload.is_builtin_type, T_1321) - node T_1324 = eq(T_1322, UInt<1>("h00")) - node T_1325 = and(T_1319, T_1324) - node T_1326 = and(T_1316, T_1325) - wire T_1330 : UInt<3>[1] - T_1330[0] <= UInt<3>("h05") - node T_1333 = eq(T_1330[0], io.grant.bits.payload.g_type) - node T_1335 = or(UInt<1>("h00"), T_1333) - wire T_1337 : UInt<1>[2] - T_1337[0] <= UInt<1>("h00") - T_1337[1] <= UInt<1>("h01") - node T_1341 = eq(T_1337[0], io.grant.bits.payload.g_type) - node T_1342 = eq(T_1337[1], io.grant.bits.payload.g_type) - node T_1344 = or(UInt<1>("h00"), T_1341) - node T_1345 = or(T_1344, T_1342) - node T_1346 = mux(io.grant.bits.payload.is_builtin_type, T_1335, T_1345) - node T_1347 = and(UInt<1>("h01"), T_1346) - node T_1349 = eq(T_1347, UInt<1>("h00")) - node T_1350 = or(T_1349, T_1214) - node T_1351 = and(T_1326, T_1350) - T_1311.io.enq.valid <= T_1351 - wire T_1377 : {manager_xact_id : UInt<4>} - T_1377.manager_xact_id <= UInt<1>("h00") - T_1377.manager_xact_id <= io.grant.bits.payload.manager_xact_id - T_1311.io.enq.bits.fin <- T_1377 - T_1311.io.enq.bits.dst <= io.grant.bits.header.src + node T_1210 = add(T_1203, UInt<1>("h01")) + node T_1211 = tail(T_1210, 1) + node T_1212 = mux(T_1207, UInt<1>("h00"), T_1211) + T_1203 <= T_1212 + skip + node T_1213 = and(T_1201, T_1205) + node T_1214 = mux(T_1200, T_1203, UInt<1>("h00")) + node T_1215 = mux(T_1200, T_1213, T_1178) + inst T_1312 of FinishQueue + T_1312.io is invalid + T_1312.clk <= clk + T_1312.reset <= reset + node T_1313 = and(io.grant.ready, io.grant.valid) + node T_1316 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1318 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) + node T_1319 = and(io.grant.bits.payload.is_builtin_type, T_1318) + node T_1321 = eq(T_1319, UInt<1>("h00")) + node T_1322 = and(T_1316, T_1321) + node T_1323 = and(T_1313, T_1322) + wire T_1327 : UInt<3>[1] + T_1327[0] <= UInt<3>("h05") + node T_1330 = eq(T_1327[0], io.grant.bits.payload.g_type) + node T_1332 = or(UInt<1>("h00"), T_1330) + wire T_1334 : UInt<1>[2] + T_1334[0] <= UInt<1>("h00") + T_1334[1] <= UInt<1>("h01") + node T_1338 = eq(T_1334[0], io.grant.bits.payload.g_type) + node T_1339 = eq(T_1334[1], io.grant.bits.payload.g_type) + node T_1341 = or(UInt<1>("h00"), T_1338) + node T_1342 = or(T_1341, T_1339) + node T_1343 = mux(io.grant.bits.payload.is_builtin_type, T_1332, T_1342) + node T_1344 = and(UInt<1>("h01"), T_1343) + node T_1346 = eq(T_1344, UInt<1>("h00")) + node T_1347 = or(T_1346, T_1215) + node T_1348 = and(T_1323, T_1347) + T_1312.io.enq.valid <= T_1348 + wire T_1374 : {manager_xact_id : UInt<4>} + T_1374 is invalid + T_1374.manager_xact_id <= io.grant.bits.payload.manager_xact_id + T_1312.io.enq.bits.fin <- T_1374 + T_1312.io.enq.bits.dst <= io.grant.bits.header.src io.finish.bits.header.src <= UInt<1>("h00") - io.finish.bits.header.dst <= T_1311.io.deq.bits.dst - io.finish.bits.payload <- T_1311.io.deq.bits.fin - io.finish.valid <= T_1311.io.deq.valid - T_1311.io.deq.ready <= io.finish.ready - node T_1406 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1408 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1409 = and(io.grant.bits.payload.is_builtin_type, T_1408) - node T_1411 = eq(T_1409, UInt<1>("h00")) - node T_1412 = and(T_1406, T_1411) - node T_1414 = eq(T_1412, UInt<1>("h00")) - node T_1415 = or(T_1311.io.enq.ready, T_1414) - node T_1416 = and(T_1415, io.grant.valid) - io.refill.valid <= T_1416 + io.finish.bits.header.dst <= T_1312.io.deq.bits.dst + io.finish.bits.payload <- T_1312.io.deq.bits.fin + io.finish.valid <= T_1312.io.deq.valid + T_1312.io.deq.ready <= io.finish.ready + node T_1402 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1404 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) + node T_1405 = and(io.grant.bits.payload.is_builtin_type, T_1404) + node T_1407 = eq(T_1405, UInt<1>("h00")) + node T_1408 = and(T_1402, T_1407) + node T_1410 = eq(T_1408, UInt<1>("h00")) + node T_1411 = or(T_1312.io.enq.ready, T_1410) + node T_1412 = and(T_1411, io.grant.valid) + io.refill.valid <= T_1412 io.refill.bits <- io.grant.bits.payload - node T_1419 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1421 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1422 = and(io.grant.bits.payload.is_builtin_type, T_1421) - node T_1424 = eq(T_1422, UInt<1>("h00")) - node T_1425 = and(T_1419, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h00")) - node T_1428 = or(T_1311.io.enq.ready, T_1427) - node T_1429 = and(T_1428, io.refill.ready) - io.grant.ready <= T_1429 - io.ready <= T_1311.io.enq.ready + node T_1415 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1417 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) + node T_1418 = and(io.grant.bits.payload.is_builtin_type, T_1417) + node T_1420 = eq(T_1418, UInt<1>("h00")) + node T_1421 = and(T_1415, T_1420) + node T_1423 = eq(T_1421, UInt<1>("h00")) + node T_1424 = or(T_1312.io.enq.ready, T_1423) + node T_1425 = and(T_1424, io.refill.ready) + io.grant.ready <= T_1425 + io.ready <= T_1312.io.enq.ready module ClientTileLinkNetworkPort : input clk : Clock input reset : UInt<1> output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - io.network.release.bits.payload.data <= UInt<1>("h00") - io.network.release.bits.payload.r_type <= UInt<1>("h00") - io.network.release.bits.payload.voluntary <= UInt<1>("h00") - io.network.release.bits.payload.client_xact_id <= UInt<1>("h00") - io.network.release.bits.payload.addr_block <= UInt<1>("h00") - io.network.release.bits.payload.addr_beat <= UInt<1>("h00") - io.network.release.bits.header.dst <= UInt<1>("h00") - io.network.release.bits.header.src <= UInt<1>("h00") - io.network.release.valid <= UInt<1>("h00") - io.network.probe.ready <= UInt<1>("h00") - io.network.finish.bits.payload.manager_xact_id <= UInt<1>("h00") - io.network.finish.bits.header.dst <= UInt<1>("h00") - io.network.finish.bits.header.src <= UInt<1>("h00") - io.network.finish.valid <= UInt<1>("h00") - io.network.grant.ready <= UInt<1>("h00") - io.network.acquire.bits.payload.data <= UInt<1>("h00") - io.network.acquire.bits.payload.union <= UInt<1>("h00") - io.network.acquire.bits.payload.a_type <= UInt<1>("h00") - io.network.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") - io.network.acquire.bits.payload.addr_beat <= UInt<1>("h00") - io.network.acquire.bits.payload.client_xact_id <= UInt<1>("h00") - io.network.acquire.bits.payload.addr_block <= UInt<1>("h00") - io.network.acquire.bits.header.dst <= UInt<1>("h00") - io.network.acquire.bits.header.src <= UInt<1>("h00") - io.network.acquire.valid <= UInt<1>("h00") - io.client.release.ready <= UInt<1>("h00") - io.client.probe.bits.p_type <= UInt<1>("h00") - io.client.probe.bits.addr_block <= UInt<1>("h00") - io.client.probe.valid <= UInt<1>("h00") - io.client.grant.bits.data <= UInt<1>("h00") - io.client.grant.bits.g_type <= UInt<1>("h00") - io.client.grant.bits.is_builtin_type <= UInt<1>("h00") - io.client.grant.bits.manager_xact_id <= UInt<1>("h00") - io.client.grant.bits.client_xact_id <= UInt<1>("h00") - io.client.grant.bits.addr_beat <= UInt<1>("h00") - io.client.grant.valid <= UInt<1>("h00") - io.client.acquire.ready <= UInt<1>("h00") + io is invalid inst finisher of FinishUnit - finisher.io.finish.ready <= UInt<1>("h00") - finisher.io.refill.ready <= UInt<1>("h00") - finisher.io.grant.bits.payload.data <= UInt<1>("h00") - finisher.io.grant.bits.payload.g_type <= UInt<1>("h00") - finisher.io.grant.bits.payload.is_builtin_type <= UInt<1>("h00") - finisher.io.grant.bits.payload.manager_xact_id <= UInt<1>("h00") - finisher.io.grant.bits.payload.client_xact_id <= UInt<1>("h00") - finisher.io.grant.bits.payload.addr_beat <= UInt<1>("h00") - finisher.io.grant.bits.header.dst <= UInt<1>("h00") - finisher.io.grant.bits.header.src <= UInt<1>("h00") - finisher.io.grant.valid <= UInt<1>("h00") + finisher.io is invalid finisher.clk <= clk finisher.reset <= reset finisher.io.grant <- io.network.grant io.network.finish <- finisher.io.finish wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}} - acq_with_header.bits.payload.data <= UInt<1>("h00") - acq_with_header.bits.payload.union <= UInt<1>("h00") - acq_with_header.bits.payload.a_type <= UInt<1>("h00") - acq_with_header.bits.payload.is_builtin_type <= UInt<1>("h00") - acq_with_header.bits.payload.addr_beat <= UInt<1>("h00") - acq_with_header.bits.payload.client_xact_id <= UInt<1>("h00") - acq_with_header.bits.payload.addr_block <= UInt<1>("h00") - acq_with_header.bits.header.dst <= UInt<1>("h00") - acq_with_header.bits.header.src <= UInt<1>("h00") - acq_with_header.valid <= UInt<1>("h00") - acq_with_header.ready <= UInt<1>("h00") + acq_with_header is invalid acq_with_header.bits.payload <- io.client.acquire.bits acq_with_header.bits.header.src <= UInt<1>("h00") acq_with_header.bits.header.dst <= UInt<1>("h00") acq_with_header.valid <= io.client.acquire.valid io.client.acquire.ready <= acq_with_header.ready wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}} - rel_with_header.bits.payload.data <= UInt<1>("h00") - rel_with_header.bits.payload.r_type <= UInt<1>("h00") - rel_with_header.bits.payload.voluntary <= UInt<1>("h00") - rel_with_header.bits.payload.client_xact_id <= UInt<1>("h00") - rel_with_header.bits.payload.addr_block <= UInt<1>("h00") - rel_with_header.bits.payload.addr_beat <= UInt<1>("h00") - rel_with_header.bits.header.dst <= UInt<1>("h00") - rel_with_header.bits.header.src <= UInt<1>("h00") - rel_with_header.valid <= UInt<1>("h00") - rel_with_header.ready <= UInt<1>("h00") + rel_with_header is invalid rel_with_header.bits.payload <- io.client.release.bits rel_with_header.bits.header.src <= UInt<1>("h00") rel_with_header.bits.header.dst <= UInt<1>("h00") rel_with_header.valid <= io.client.release.valid io.client.release.ready <= rel_with_header.ready wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} - prb_without_header.bits.p_type <= UInt<1>("h00") - prb_without_header.bits.addr_block <= UInt<1>("h00") - prb_without_header.valid <= UInt<1>("h00") - prb_without_header.ready <= UInt<1>("h00") + prb_without_header is invalid prb_without_header.valid <= io.network.probe.valid prb_without_header.bits <- io.network.probe.bits.payload io.network.probe.ready <= prb_without_header.ready io.network.acquire.bits <- acq_with_header.bits - node T_5014 = and(acq_with_header.valid, finisher.io.ready) - io.network.acquire.valid <= T_5014 - node T_5015 = and(io.network.acquire.ready, finisher.io.ready) - acq_with_header.ready <= T_5015 + node T_4978 = and(acq_with_header.valid, finisher.io.ready) + io.network.acquire.valid <= T_4978 + node T_4979 = and(io.network.acquire.ready, finisher.io.ready) + acq_with_header.ready <= T_4979 io.network.release <- rel_with_header io.client.probe <- prb_without_header io.client.grant <- finisher.io.refill @@ -726,22 +582,11 @@ circuit Top : input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, count : UInt<2>} - io.count <= UInt<1>("h00") - io.deq.bits.payload.data <= UInt<1>("h00") - io.deq.bits.payload.union <= UInt<1>("h00") - io.deq.bits.payload.a_type <= UInt<1>("h00") - io.deq.bits.payload.is_builtin_type <= UInt<1>("h00") - io.deq.bits.payload.addr_beat <= UInt<1>("h00") - io.deq.bits.payload.client_xact_id <= UInt<1>("h00") - io.deq.bits.payload.addr_block <= UInt<1>("h00") - io.deq.bits.header.dst <= UInt<1>("h00") - io.deq.bits.header.src <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}[2] - reg T_1160 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_1162 : UInt<1>, clk, reset, UInt<1>("h00") - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1160 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_1162 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(T_1160, T_1162) node T_1167 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_1167) @@ -759,57 +604,50 @@ circuit Top : T_1181 <- io.enq.bits node T_1309 = eq(T_1160, UInt<1>("h01")) node T_1311 = and(UInt<1>("h00"), T_1309) - node T_1314 = addw(T_1160, UInt<1>("h01")) - node T_1315 = mux(T_1311, UInt<1>("h00"), T_1314) - T_1160 <= T_1315 + node T_1314 = add(T_1160, UInt<1>("h01")) + node T_1315 = tail(T_1314, 1) + node T_1316 = mux(T_1311, UInt<1>("h00"), T_1315) + T_1160 <= T_1316 skip when do_deq : - node T_1317 = eq(T_1162, UInt<1>("h01")) - node T_1319 = and(UInt<1>("h00"), T_1317) - node T_1322 = addw(T_1162, UInt<1>("h01")) - node T_1323 = mux(T_1319, UInt<1>("h00"), T_1322) - T_1162 <= T_1323 - skip - node T_1324 = neq(do_enq, do_deq) - when T_1324 : + node T_1318 = eq(T_1162, UInt<1>("h01")) + node T_1320 = and(UInt<1>("h00"), T_1318) + node T_1323 = add(T_1162, UInt<1>("h01")) + node T_1324 = tail(T_1323, 1) + node T_1325 = mux(T_1320, UInt<1>("h00"), T_1324) + T_1162 <= T_1325 + skip + node T_1326 = neq(do_enq, do_deq) + when T_1326 : maybe_full <= do_enq skip - node T_1326 = eq(empty, UInt<1>("h00")) - node T_1328 = and(UInt<1>("h00"), io.enq.valid) - node T_1329 = or(T_1326, T_1328) - io.deq.valid <= T_1329 - node T_1331 = eq(full, UInt<1>("h00")) - node T_1333 = and(UInt<1>("h00"), io.deq.ready) - node T_1334 = or(T_1331, T_1333) - io.enq.ready <= T_1334 - infer mport T_1335 = ram[T_1162], clk - wire T_1589 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}} - T_1589 <- T_1335 - when maybe_flow : - T_1589 <- io.enq.bits - skip - io.deq.bits <- T_1589 - node ptr_diff = subw(T_1160, T_1162) - node T_1717 = and(maybe_full, ptr_match) - node T_1718 = cat(T_1717, ptr_diff) - io.count <= T_1718 + node T_1328 = eq(empty, UInt<1>("h00")) + node T_1330 = and(UInt<1>("h00"), io.enq.valid) + node T_1331 = or(T_1328, T_1330) + io.deq.valid <= T_1331 + node T_1333 = eq(full, UInt<1>("h00")) + node T_1335 = and(UInt<1>("h00"), io.deq.ready) + node T_1336 = or(T_1333, T_1335) + io.enq.ready <= T_1336 + infer mport T_1337 = ram[T_1162], clk + node T_1464 = mux(maybe_flow, io.enq.bits, T_1337) + io.deq.bits <- T_1464 + node T_1591 = sub(T_1160, T_1162) + node ptr_diff = tail(T_1591, 1) + node T_1593 = and(maybe_full, ptr_match) + node T_1594 = cat(T_1593, ptr_diff) + io.count <= T_1594 module Queue_2 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, count : UInt<2>} - io.count <= UInt<1>("h00") - io.deq.bits.payload.p_type <= UInt<1>("h00") - io.deq.bits.payload.addr_block <= UInt<1>("h00") - io.deq.bits.header.dst <= UInt<1>("h00") - io.deq.bits.header.src <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}[2] - reg T_1115 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_1117 : UInt<1>, clk, reset, UInt<1>("h00") - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1115 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_1117 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(T_1115, T_1117) node T_1122 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_1122) @@ -827,61 +665,50 @@ circuit Top : T_1136 <- io.enq.bits node T_1259 = eq(T_1115, UInt<1>("h01")) node T_1261 = and(UInt<1>("h00"), T_1259) - node T_1264 = addw(T_1115, UInt<1>("h01")) - node T_1265 = mux(T_1261, UInt<1>("h00"), T_1264) - T_1115 <= T_1265 + node T_1264 = add(T_1115, UInt<1>("h01")) + node T_1265 = tail(T_1264, 1) + node T_1266 = mux(T_1261, UInt<1>("h00"), T_1265) + T_1115 <= T_1266 skip when do_deq : - node T_1267 = eq(T_1117, UInt<1>("h01")) - node T_1269 = and(UInt<1>("h00"), T_1267) - node T_1272 = addw(T_1117, UInt<1>("h01")) - node T_1273 = mux(T_1269, UInt<1>("h00"), T_1272) - T_1117 <= T_1273 - skip - node T_1274 = neq(do_enq, do_deq) - when T_1274 : + node T_1268 = eq(T_1117, UInt<1>("h01")) + node T_1270 = and(UInt<1>("h00"), T_1268) + node T_1273 = add(T_1117, UInt<1>("h01")) + node T_1274 = tail(T_1273, 1) + node T_1275 = mux(T_1270, UInt<1>("h00"), T_1274) + T_1117 <= T_1275 + skip + node T_1276 = neq(do_enq, do_deq) + when T_1276 : maybe_full <= do_enq skip - node T_1276 = eq(empty, UInt<1>("h00")) - node T_1278 = and(UInt<1>("h00"), io.enq.valid) - node T_1279 = or(T_1276, T_1278) - io.deq.valid <= T_1279 - node T_1281 = eq(full, UInt<1>("h00")) - node T_1283 = and(UInt<1>("h00"), io.deq.ready) - node T_1284 = or(T_1281, T_1283) - io.enq.ready <= T_1284 - infer mport T_1285 = ram[T_1117], clk - wire T_1529 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}} - T_1529 <- T_1285 - when maybe_flow : - T_1529 <- io.enq.bits - skip - io.deq.bits <- T_1529 - node ptr_diff = subw(T_1115, T_1117) - node T_1652 = and(maybe_full, ptr_match) - node T_1653 = cat(T_1652, ptr_diff) - io.count <= T_1653 + node T_1278 = eq(empty, UInt<1>("h00")) + node T_1280 = and(UInt<1>("h00"), io.enq.valid) + node T_1281 = or(T_1278, T_1280) + io.deq.valid <= T_1281 + node T_1283 = eq(full, UInt<1>("h00")) + node T_1285 = and(UInt<1>("h00"), io.deq.ready) + node T_1286 = or(T_1283, T_1285) + io.enq.ready <= T_1286 + infer mport T_1287 = ram[T_1117], clk + node T_1409 = mux(maybe_flow, io.enq.bits, T_1287) + io.deq.bits <- T_1409 + node T_1531 = sub(T_1115, T_1117) + node ptr_diff = tail(T_1531, 1) + node T_1533 = and(maybe_full, ptr_match) + node T_1534 = cat(T_1533, ptr_diff) + io.count <= T_1534 module Queue_3 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, count : UInt<2>} - io.count <= UInt<1>("h00") - io.deq.bits.payload.data <= UInt<1>("h00") - io.deq.bits.payload.r_type <= UInt<1>("h00") - io.deq.bits.payload.voluntary <= UInt<1>("h00") - io.deq.bits.payload.client_xact_id <= UInt<1>("h00") - io.deq.bits.payload.addr_block <= UInt<1>("h00") - io.deq.bits.payload.addr_beat <= UInt<1>("h00") - io.deq.bits.header.dst <= UInt<1>("h00") - io.deq.bits.header.src <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}[2] - reg T_1151 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_1153 : UInt<1>, clk, reset, UInt<1>("h00") - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1151 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_1153 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(T_1151, T_1153) node T_1158 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_1158) @@ -899,61 +726,50 @@ circuit Top : T_1172 <- io.enq.bits node T_1299 = eq(T_1151, UInt<1>("h01")) node T_1301 = and(UInt<1>("h00"), T_1299) - node T_1304 = addw(T_1151, UInt<1>("h01")) - node T_1305 = mux(T_1301, UInt<1>("h00"), T_1304) - T_1151 <= T_1305 + node T_1304 = add(T_1151, UInt<1>("h01")) + node T_1305 = tail(T_1304, 1) + node T_1306 = mux(T_1301, UInt<1>("h00"), T_1305) + T_1151 <= T_1306 skip when do_deq : - node T_1307 = eq(T_1153, UInt<1>("h01")) - node T_1309 = and(UInt<1>("h00"), T_1307) - node T_1312 = addw(T_1153, UInt<1>("h01")) - node T_1313 = mux(T_1309, UInt<1>("h00"), T_1312) - T_1153 <= T_1313 - skip - node T_1314 = neq(do_enq, do_deq) - when T_1314 : + node T_1308 = eq(T_1153, UInt<1>("h01")) + node T_1310 = and(UInt<1>("h00"), T_1308) + node T_1313 = add(T_1153, UInt<1>("h01")) + node T_1314 = tail(T_1313, 1) + node T_1315 = mux(T_1310, UInt<1>("h00"), T_1314) + T_1153 <= T_1315 + skip + node T_1316 = neq(do_enq, do_deq) + when T_1316 : maybe_full <= do_enq skip - node T_1316 = eq(empty, UInt<1>("h00")) - node T_1318 = and(UInt<1>("h00"), io.enq.valid) - node T_1319 = or(T_1316, T_1318) - io.deq.valid <= T_1319 - node T_1321 = eq(full, UInt<1>("h00")) - node T_1323 = and(UInt<1>("h00"), io.deq.ready) - node T_1324 = or(T_1321, T_1323) - io.enq.ready <= T_1324 - infer mport T_1325 = ram[T_1153], clk - wire T_1577 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}} - T_1577 <- T_1325 - when maybe_flow : - T_1577 <- io.enq.bits - skip - io.deq.bits <- T_1577 - node ptr_diff = subw(T_1151, T_1153) - node T_1704 = and(maybe_full, ptr_match) - node T_1705 = cat(T_1704, ptr_diff) - io.count <= T_1705 + node T_1318 = eq(empty, UInt<1>("h00")) + node T_1320 = and(UInt<1>("h00"), io.enq.valid) + node T_1321 = or(T_1318, T_1320) + io.deq.valid <= T_1321 + node T_1323 = eq(full, UInt<1>("h00")) + node T_1325 = and(UInt<1>("h00"), io.deq.ready) + node T_1326 = or(T_1323, T_1325) + io.enq.ready <= T_1326 + infer mport T_1327 = ram[T_1153], clk + node T_1453 = mux(maybe_flow, io.enq.bits, T_1327) + io.deq.bits <- T_1453 + node T_1579 = sub(T_1151, T_1153) + node ptr_diff = tail(T_1579, 1) + node T_1581 = and(maybe_full, ptr_match) + node T_1582 = cat(T_1581, ptr_diff) + io.count <= T_1582 module Queue_4 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, count : UInt<2>} - io.count <= UInt<1>("h00") - io.deq.bits.payload.data <= UInt<1>("h00") - io.deq.bits.payload.g_type <= UInt<1>("h00") - io.deq.bits.payload.is_builtin_type <= UInt<1>("h00") - io.deq.bits.payload.manager_xact_id <= UInt<1>("h00") - io.deq.bits.payload.client_xact_id <= UInt<1>("h00") - io.deq.bits.payload.addr_beat <= UInt<1>("h00") - io.deq.bits.header.dst <= UInt<1>("h00") - io.deq.bits.header.src <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}[2] - reg T_1151 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_1153 : UInt<1>, clk, reset, UInt<1>("h00") - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1151 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_1153 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(T_1151, T_1153) node T_1158 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_1158) @@ -971,56 +787,50 @@ circuit Top : T_1172 <- io.enq.bits node T_1299 = eq(T_1151, UInt<1>("h01")) node T_1301 = and(UInt<1>("h00"), T_1299) - node T_1304 = addw(T_1151, UInt<1>("h01")) - node T_1305 = mux(T_1301, UInt<1>("h00"), T_1304) - T_1151 <= T_1305 + node T_1304 = add(T_1151, UInt<1>("h01")) + node T_1305 = tail(T_1304, 1) + node T_1306 = mux(T_1301, UInt<1>("h00"), T_1305) + T_1151 <= T_1306 skip when do_deq : - node T_1307 = eq(T_1153, UInt<1>("h01")) - node T_1309 = and(UInt<1>("h00"), T_1307) - node T_1312 = addw(T_1153, UInt<1>("h01")) - node T_1313 = mux(T_1309, UInt<1>("h00"), T_1312) - T_1153 <= T_1313 - skip - node T_1314 = neq(do_enq, do_deq) - when T_1314 : + node T_1308 = eq(T_1153, UInt<1>("h01")) + node T_1310 = and(UInt<1>("h00"), T_1308) + node T_1313 = add(T_1153, UInt<1>("h01")) + node T_1314 = tail(T_1313, 1) + node T_1315 = mux(T_1310, UInt<1>("h00"), T_1314) + T_1153 <= T_1315 + skip + node T_1316 = neq(do_enq, do_deq) + when T_1316 : maybe_full <= do_enq skip - node T_1316 = eq(empty, UInt<1>("h00")) - node T_1318 = and(UInt<1>("h00"), io.enq.valid) - node T_1319 = or(T_1316, T_1318) - io.deq.valid <= T_1319 - node T_1321 = eq(full, UInt<1>("h00")) - node T_1323 = and(UInt<1>("h00"), io.deq.ready) - node T_1324 = or(T_1321, T_1323) - io.enq.ready <= T_1324 - infer mport T_1325 = ram[T_1153], clk - wire T_1577 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}} - T_1577 <- T_1325 - when maybe_flow : - T_1577 <- io.enq.bits - skip - io.deq.bits <- T_1577 - node ptr_diff = subw(T_1151, T_1153) - node T_1704 = and(maybe_full, ptr_match) - node T_1705 = cat(T_1704, ptr_diff) - io.count <= T_1705 + node T_1318 = eq(empty, UInt<1>("h00")) + node T_1320 = and(UInt<1>("h00"), io.enq.valid) + node T_1321 = or(T_1318, T_1320) + io.deq.valid <= T_1321 + node T_1323 = eq(full, UInt<1>("h00")) + node T_1325 = and(UInt<1>("h00"), io.deq.ready) + node T_1326 = or(T_1323, T_1325) + io.enq.ready <= T_1326 + infer mport T_1327 = ram[T_1153], clk + node T_1453 = mux(maybe_flow, io.enq.bits, T_1327) + io.deq.bits <- T_1453 + node T_1579 = sub(T_1151, T_1153) + node ptr_diff = tail(T_1579, 1) + node T_1581 = and(maybe_full, ptr_match) + node T_1582 = cat(T_1581, ptr_diff) + io.count <= T_1582 module Queue_5 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, count : UInt<2>} - io.count <= UInt<1>("h00") - io.deq.bits.payload.manager_xact_id <= UInt<1>("h00") - io.deq.bits.header.dst <= UInt<1>("h00") - io.deq.bits.header.src <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}[2] - reg T_1106 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_1108 : UInt<1>, clk, reset, UInt<1>("h00") - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1106 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_1108 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(T_1106, T_1108) node T_1113 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_1113) @@ -1038,184 +848,93 @@ circuit Top : T_1127 <- io.enq.bits node T_1249 = eq(T_1106, UInt<1>("h01")) node T_1251 = and(UInt<1>("h00"), T_1249) - node T_1254 = addw(T_1106, UInt<1>("h01")) - node T_1255 = mux(T_1251, UInt<1>("h00"), T_1254) - T_1106 <= T_1255 + node T_1254 = add(T_1106, UInt<1>("h01")) + node T_1255 = tail(T_1254, 1) + node T_1256 = mux(T_1251, UInt<1>("h00"), T_1255) + T_1106 <= T_1256 skip when do_deq : - node T_1257 = eq(T_1108, UInt<1>("h01")) - node T_1259 = and(UInt<1>("h00"), T_1257) - node T_1262 = addw(T_1108, UInt<1>("h01")) - node T_1263 = mux(T_1259, UInt<1>("h00"), T_1262) - T_1108 <= T_1263 - skip - node T_1264 = neq(do_enq, do_deq) - when T_1264 : + node T_1258 = eq(T_1108, UInt<1>("h01")) + node T_1260 = and(UInt<1>("h00"), T_1258) + node T_1263 = add(T_1108, UInt<1>("h01")) + node T_1264 = tail(T_1263, 1) + node T_1265 = mux(T_1260, UInt<1>("h00"), T_1264) + T_1108 <= T_1265 + skip + node T_1266 = neq(do_enq, do_deq) + when T_1266 : maybe_full <= do_enq skip - node T_1266 = eq(empty, UInt<1>("h00")) - node T_1268 = and(UInt<1>("h00"), io.enq.valid) - node T_1269 = or(T_1266, T_1268) - io.deq.valid <= T_1269 - node T_1271 = eq(full, UInt<1>("h00")) - node T_1273 = and(UInt<1>("h00"), io.deq.ready) - node T_1274 = or(T_1271, T_1273) - io.enq.ready <= T_1274 - infer mport T_1275 = ram[T_1108], clk - wire T_1517 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}} - T_1517 <- T_1275 - when maybe_flow : - T_1517 <- io.enq.bits - skip - io.deq.bits <- T_1517 - node ptr_diff = subw(T_1106, T_1108) - node T_1639 = and(maybe_full, ptr_match) - node T_1640 = cat(T_1639, ptr_diff) - io.count <= T_1640 + node T_1268 = eq(empty, UInt<1>("h00")) + node T_1270 = and(UInt<1>("h00"), io.enq.valid) + node T_1271 = or(T_1268, T_1270) + io.deq.valid <= T_1271 + node T_1273 = eq(full, UInt<1>("h00")) + node T_1275 = and(UInt<1>("h00"), io.deq.ready) + node T_1276 = or(T_1273, T_1275) + io.enq.ready <= T_1276 + infer mport T_1277 = ram[T_1108], clk + node T_1398 = mux(maybe_flow, io.enq.bits, T_1277) + io.deq.bits <- T_1398 + node T_1519 = sub(T_1106, T_1108) + node ptr_diff = tail(T_1519, 1) + node T_1521 = and(maybe_full, ptr_match) + node T_1522 = cat(T_1521, ptr_diff) + io.count <= T_1522 module TileLinkEnqueuer : input clk : Clock input reset : UInt<1> output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}, manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - io.manager.release.bits.payload.data <= UInt<1>("h00") - io.manager.release.bits.payload.r_type <= UInt<1>("h00") - io.manager.release.bits.payload.voluntary <= UInt<1>("h00") - io.manager.release.bits.payload.client_xact_id <= UInt<1>("h00") - io.manager.release.bits.payload.addr_block <= UInt<1>("h00") - io.manager.release.bits.payload.addr_beat <= UInt<1>("h00") - io.manager.release.bits.header.dst <= UInt<1>("h00") - io.manager.release.bits.header.src <= UInt<1>("h00") - io.manager.release.valid <= UInt<1>("h00") - io.manager.probe.ready <= UInt<1>("h00") - io.manager.finish.bits.payload.manager_xact_id <= UInt<1>("h00") - io.manager.finish.bits.header.dst <= UInt<1>("h00") - io.manager.finish.bits.header.src <= UInt<1>("h00") - io.manager.finish.valid <= UInt<1>("h00") - io.manager.grant.ready <= UInt<1>("h00") - io.manager.acquire.bits.payload.data <= UInt<1>("h00") - io.manager.acquire.bits.payload.union <= UInt<1>("h00") - io.manager.acquire.bits.payload.a_type <= UInt<1>("h00") - io.manager.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") - io.manager.acquire.bits.payload.addr_beat <= UInt<1>("h00") - io.manager.acquire.bits.payload.client_xact_id <= UInt<1>("h00") - io.manager.acquire.bits.payload.addr_block <= UInt<1>("h00") - io.manager.acquire.bits.header.dst <= UInt<1>("h00") - io.manager.acquire.bits.header.src <= UInt<1>("h00") - io.manager.acquire.valid <= UInt<1>("h00") - io.client.release.ready <= UInt<1>("h00") - io.client.probe.bits.payload.p_type <= UInt<1>("h00") - io.client.probe.bits.payload.addr_block <= UInt<1>("h00") - io.client.probe.bits.header.dst <= UInt<1>("h00") - io.client.probe.bits.header.src <= UInt<1>("h00") - io.client.probe.valid <= UInt<1>("h00") - io.client.finish.ready <= UInt<1>("h00") - io.client.grant.bits.payload.data <= UInt<1>("h00") - io.client.grant.bits.payload.g_type <= UInt<1>("h00") - io.client.grant.bits.payload.is_builtin_type <= UInt<1>("h00") - io.client.grant.bits.payload.manager_xact_id <= UInt<1>("h00") - io.client.grant.bits.payload.client_xact_id <= UInt<1>("h00") - io.client.grant.bits.payload.addr_beat <= UInt<1>("h00") - io.client.grant.bits.header.dst <= UInt<1>("h00") - io.client.grant.bits.header.src <= UInt<1>("h00") - io.client.grant.valid <= UInt<1>("h00") - io.client.acquire.ready <= UInt<1>("h00") + io is invalid inst T_7778 of Queue - T_7778.io.deq.ready <= UInt<1>("h00") - T_7778.io.enq.bits.payload.data <= UInt<1>("h00") - T_7778.io.enq.bits.payload.union <= UInt<1>("h00") - T_7778.io.enq.bits.payload.a_type <= UInt<1>("h00") - T_7778.io.enq.bits.payload.is_builtin_type <= UInt<1>("h00") - T_7778.io.enq.bits.payload.addr_beat <= UInt<1>("h00") - T_7778.io.enq.bits.payload.client_xact_id <= UInt<1>("h00") - T_7778.io.enq.bits.payload.addr_block <= UInt<1>("h00") - T_7778.io.enq.bits.header.dst <= UInt<1>("h00") - T_7778.io.enq.bits.header.src <= UInt<1>("h00") - T_7778.io.enq.valid <= UInt<1>("h00") + T_7778.io is invalid T_7778.clk <= clk T_7778.reset <= reset T_7778.io.enq.valid <= io.client.acquire.valid T_7778.io.enq.bits <- io.client.acquire.bits io.client.acquire.ready <= T_7778.io.enq.ready io.manager.acquire <- T_7778.io.deq - inst T_7912 of Queue_2 - T_7912.io.deq.ready <= UInt<1>("h00") - T_7912.io.enq.bits.payload.p_type <= UInt<1>("h00") - T_7912.io.enq.bits.payload.addr_block <= UInt<1>("h00") - T_7912.io.enq.bits.header.dst <= UInt<1>("h00") - T_7912.io.enq.bits.header.src <= UInt<1>("h00") - T_7912.io.enq.valid <= UInt<1>("h00") - T_7912.clk <= clk - T_7912.reset <= reset - T_7912.io.enq.valid <= io.manager.probe.valid - T_7912.io.enq.bits <- io.manager.probe.bits - io.manager.probe.ready <= T_7912.io.enq.ready - io.client.probe <- T_7912.io.deq - inst T_8045 of Queue_3 - T_8045.io.deq.ready <= UInt<1>("h00") - T_8045.io.enq.bits.payload.data <= UInt<1>("h00") - T_8045.io.enq.bits.payload.r_type <= UInt<1>("h00") - T_8045.io.enq.bits.payload.voluntary <= UInt<1>("h00") - T_8045.io.enq.bits.payload.client_xact_id <= UInt<1>("h00") - T_8045.io.enq.bits.payload.addr_block <= UInt<1>("h00") - T_8045.io.enq.bits.payload.addr_beat <= UInt<1>("h00") - T_8045.io.enq.bits.header.dst <= UInt<1>("h00") - T_8045.io.enq.bits.header.src <= UInt<1>("h00") - T_8045.io.enq.valid <= UInt<1>("h00") - T_8045.clk <= clk - T_8045.reset <= reset - T_8045.io.enq.valid <= io.client.release.valid - T_8045.io.enq.bits <- io.client.release.bits - io.client.release.ready <= T_8045.io.enq.ready - io.manager.release <- T_8045.io.deq - inst T_8182 of Queue_4 - T_8182.io.deq.ready <= UInt<1>("h00") - T_8182.io.enq.bits.payload.data <= UInt<1>("h00") - T_8182.io.enq.bits.payload.g_type <= UInt<1>("h00") - T_8182.io.enq.bits.payload.is_builtin_type <= UInt<1>("h00") - T_8182.io.enq.bits.payload.manager_xact_id <= UInt<1>("h00") - T_8182.io.enq.bits.payload.client_xact_id <= UInt<1>("h00") - T_8182.io.enq.bits.payload.addr_beat <= UInt<1>("h00") - T_8182.io.enq.bits.header.dst <= UInt<1>("h00") - T_8182.io.enq.bits.header.src <= UInt<1>("h00") - T_8182.io.enq.valid <= UInt<1>("h00") - T_8182.clk <= clk - T_8182.reset <= reset - T_8182.io.enq.valid <= io.manager.grant.valid - T_8182.io.enq.bits <- io.manager.grant.bits - io.manager.grant.ready <= T_8182.io.enq.ready - io.client.grant <- T_8182.io.deq - inst T_8314 of Queue_5 - T_8314.io.deq.ready <= UInt<1>("h00") - T_8314.io.enq.bits.payload.manager_xact_id <= UInt<1>("h00") - T_8314.io.enq.bits.header.dst <= UInt<1>("h00") - T_8314.io.enq.bits.header.src <= UInt<1>("h00") - T_8314.io.enq.valid <= UInt<1>("h00") - T_8314.clk <= clk - T_8314.reset <= reset - T_8314.io.enq.valid <= io.client.finish.valid - T_8314.io.enq.bits <- io.client.finish.bits - io.client.finish.ready <= T_8314.io.enq.ready - io.manager.finish <- T_8314.io.deq + inst T_7901 of Queue_2 + T_7901.io is invalid + T_7901.clk <= clk + T_7901.reset <= reset + T_7901.io.enq.valid <= io.manager.probe.valid + T_7901.io.enq.bits <- io.manager.probe.bits + io.manager.probe.ready <= T_7901.io.enq.ready + io.client.probe <- T_7901.io.deq + inst T_8028 of Queue_3 + T_8028.io is invalid + T_8028.clk <= clk + T_8028.reset <= reset + T_8028.io.enq.valid <= io.client.release.valid + T_8028.io.enq.bits <- io.client.release.bits + io.client.release.ready <= T_8028.io.enq.ready + io.manager.release <- T_8028.io.deq + inst T_8155 of Queue_4 + T_8155.io is invalid + T_8155.clk <= clk + T_8155.reset <= reset + T_8155.io.enq.valid <= io.manager.grant.valid + T_8155.io.enq.bits <- io.manager.grant.bits + io.manager.grant.ready <= T_8155.io.enq.ready + io.client.grant <- T_8155.io.deq + inst T_8277 of Queue_5 + T_8277.io is invalid + T_8277.clk <= clk + T_8277.reset <= reset + T_8277.io.enq.valid <= io.client.finish.valid + T_8277.io.enq.bits <- io.client.finish.bits + io.client.finish.ready <= T_8277.io.enq.ready + io.manager.finish <- T_8277.io.deq module FinishUnit_7 : input clk : Clock input reset : UInt<1> output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, ready : UInt<1>} - io.ready <= UInt<1>("h00") - io.finish.bits.payload.manager_xact_id <= UInt<1>("h00") - io.finish.bits.header.dst <= UInt<1>("h00") - io.finish.bits.header.src <= UInt<1>("h00") - io.finish.valid <= UInt<1>("h00") - io.refill.bits.data <= UInt<1>("h00") - io.refill.bits.g_type <= UInt<1>("h00") - io.refill.bits.is_builtin_type <= UInt<1>("h00") - io.refill.bits.manager_xact_id <= UInt<1>("h00") - io.refill.bits.client_xact_id <= UInt<1>("h00") - io.refill.bits.addr_beat <= UInt<1>("h00") - io.refill.valid <= UInt<1>("h00") - io.grant.ready <= UInt<1>("h00") + io is invalid node T_1178 = and(io.grant.ready, io.grant.valid) wire T_1183 : UInt<3>[1] T_1183[0] <= UInt<3>("h05") @@ -1231,183 +950,113 @@ circuit Top : node T_1199 = mux(io.grant.bits.payload.is_builtin_type, T_1188, T_1198) node T_1200 = and(UInt<1>("h01"), T_1199) node T_1201 = and(T_1178, T_1200) - reg T_1203 : UInt<2>, clk, reset, UInt<2>("h00") + reg T_1203 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) when T_1201 : node T_1205 = eq(T_1203, UInt<2>("h03")) node T_1207 = and(UInt<1>("h00"), T_1205) - node T_1210 = addw(T_1203, UInt<1>("h01")) - node T_1211 = mux(T_1207, UInt<1>("h00"), T_1210) - T_1203 <= T_1211 - skip - node T_1212 = and(T_1201, T_1205) - node T_1213 = mux(T_1200, T_1203, UInt<1>("h00")) - node T_1214 = mux(T_1200, T_1212, T_1178) - inst T_1311 of FinishQueue - T_1311.io.deq.ready <= UInt<1>("h00") - T_1311.io.enq.bits.dst <= UInt<1>("h00") - T_1311.io.enq.bits.fin.manager_xact_id <= UInt<1>("h00") - T_1311.io.enq.valid <= UInt<1>("h00") - T_1311.clk <= clk - T_1311.reset <= reset - node T_1316 = and(io.grant.ready, io.grant.valid) - node T_1319 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1321 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1322 = and(io.grant.bits.payload.is_builtin_type, T_1321) - node T_1324 = eq(T_1322, UInt<1>("h00")) - node T_1325 = and(T_1319, T_1324) - node T_1326 = and(T_1316, T_1325) - wire T_1330 : UInt<3>[1] - T_1330[0] <= UInt<3>("h05") - node T_1333 = eq(T_1330[0], io.grant.bits.payload.g_type) - node T_1335 = or(UInt<1>("h00"), T_1333) - wire T_1337 : UInt<1>[2] - T_1337[0] <= UInt<1>("h00") - T_1337[1] <= UInt<1>("h01") - node T_1341 = eq(T_1337[0], io.grant.bits.payload.g_type) - node T_1342 = eq(T_1337[1], io.grant.bits.payload.g_type) - node T_1344 = or(UInt<1>("h00"), T_1341) - node T_1345 = or(T_1344, T_1342) - node T_1346 = mux(io.grant.bits.payload.is_builtin_type, T_1335, T_1345) - node T_1347 = and(UInt<1>("h01"), T_1346) - node T_1349 = eq(T_1347, UInt<1>("h00")) - node T_1350 = or(T_1349, T_1214) - node T_1351 = and(T_1326, T_1350) - T_1311.io.enq.valid <= T_1351 - wire T_1377 : {manager_xact_id : UInt<4>} - T_1377.manager_xact_id <= UInt<1>("h00") - T_1377.manager_xact_id <= io.grant.bits.payload.manager_xact_id - T_1311.io.enq.bits.fin <- T_1377 - T_1311.io.enq.bits.dst <= io.grant.bits.header.src + node T_1210 = add(T_1203, UInt<1>("h01")) + node T_1211 = tail(T_1210, 1) + node T_1212 = mux(T_1207, UInt<1>("h00"), T_1211) + T_1203 <= T_1212 + skip + node T_1213 = and(T_1201, T_1205) + node T_1214 = mux(T_1200, T_1203, UInt<1>("h00")) + node T_1215 = mux(T_1200, T_1213, T_1178) + inst T_1312 of FinishQueue + T_1312.io is invalid + T_1312.clk <= clk + T_1312.reset <= reset + node T_1313 = and(io.grant.ready, io.grant.valid) + node T_1316 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1318 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) + node T_1319 = and(io.grant.bits.payload.is_builtin_type, T_1318) + node T_1321 = eq(T_1319, UInt<1>("h00")) + node T_1322 = and(T_1316, T_1321) + node T_1323 = and(T_1313, T_1322) + wire T_1327 : UInt<3>[1] + T_1327[0] <= UInt<3>("h05") + node T_1330 = eq(T_1327[0], io.grant.bits.payload.g_type) + node T_1332 = or(UInt<1>("h00"), T_1330) + wire T_1334 : UInt<1>[2] + T_1334[0] <= UInt<1>("h00") + T_1334[1] <= UInt<1>("h01") + node T_1338 = eq(T_1334[0], io.grant.bits.payload.g_type) + node T_1339 = eq(T_1334[1], io.grant.bits.payload.g_type) + node T_1341 = or(UInt<1>("h00"), T_1338) + node T_1342 = or(T_1341, T_1339) + node T_1343 = mux(io.grant.bits.payload.is_builtin_type, T_1332, T_1342) + node T_1344 = and(UInt<1>("h01"), T_1343) + node T_1346 = eq(T_1344, UInt<1>("h00")) + node T_1347 = or(T_1346, T_1215) + node T_1348 = and(T_1323, T_1347) + T_1312.io.enq.valid <= T_1348 + wire T_1374 : {manager_xact_id : UInt<4>} + T_1374 is invalid + T_1374.manager_xact_id <= io.grant.bits.payload.manager_xact_id + T_1312.io.enq.bits.fin <- T_1374 + T_1312.io.enq.bits.dst <= io.grant.bits.header.src io.finish.bits.header.src <= UInt<1>("h01") - io.finish.bits.header.dst <= T_1311.io.deq.bits.dst - io.finish.bits.payload <- T_1311.io.deq.bits.fin - io.finish.valid <= T_1311.io.deq.valid - T_1311.io.deq.ready <= io.finish.ready - node T_1406 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1408 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1409 = and(io.grant.bits.payload.is_builtin_type, T_1408) - node T_1411 = eq(T_1409, UInt<1>("h00")) - node T_1412 = and(T_1406, T_1411) - node T_1414 = eq(T_1412, UInt<1>("h00")) - node T_1415 = or(T_1311.io.enq.ready, T_1414) - node T_1416 = and(T_1415, io.grant.valid) - io.refill.valid <= T_1416 + io.finish.bits.header.dst <= T_1312.io.deq.bits.dst + io.finish.bits.payload <- T_1312.io.deq.bits.fin + io.finish.valid <= T_1312.io.deq.valid + T_1312.io.deq.ready <= io.finish.ready + node T_1402 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1404 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) + node T_1405 = and(io.grant.bits.payload.is_builtin_type, T_1404) + node T_1407 = eq(T_1405, UInt<1>("h00")) + node T_1408 = and(T_1402, T_1407) + node T_1410 = eq(T_1408, UInt<1>("h00")) + node T_1411 = or(T_1312.io.enq.ready, T_1410) + node T_1412 = and(T_1411, io.grant.valid) + io.refill.valid <= T_1412 io.refill.bits <- io.grant.bits.payload - node T_1419 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1421 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1422 = and(io.grant.bits.payload.is_builtin_type, T_1421) - node T_1424 = eq(T_1422, UInt<1>("h00")) - node T_1425 = and(T_1419, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h00")) - node T_1428 = or(T_1311.io.enq.ready, T_1427) - node T_1429 = and(T_1428, io.refill.ready) - io.grant.ready <= T_1429 - io.ready <= T_1311.io.enq.ready + node T_1415 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1417 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) + node T_1418 = and(io.grant.bits.payload.is_builtin_type, T_1417) + node T_1420 = eq(T_1418, UInt<1>("h00")) + node T_1421 = and(T_1415, T_1420) + node T_1423 = eq(T_1421, UInt<1>("h00")) + node T_1424 = or(T_1312.io.enq.ready, T_1423) + node T_1425 = and(T_1424, io.refill.ready) + io.grant.ready <= T_1425 + io.ready <= T_1312.io.enq.ready module ClientTileLinkNetworkPort_6 : input clk : Clock input reset : UInt<1> output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - io.network.release.bits.payload.data <= UInt<1>("h00") - io.network.release.bits.payload.r_type <= UInt<1>("h00") - io.network.release.bits.payload.voluntary <= UInt<1>("h00") - io.network.release.bits.payload.client_xact_id <= UInt<1>("h00") - io.network.release.bits.payload.addr_block <= UInt<1>("h00") - io.network.release.bits.payload.addr_beat <= UInt<1>("h00") - io.network.release.bits.header.dst <= UInt<1>("h00") - io.network.release.bits.header.src <= UInt<1>("h00") - io.network.release.valid <= UInt<1>("h00") - io.network.probe.ready <= UInt<1>("h00") - io.network.finish.bits.payload.manager_xact_id <= UInt<1>("h00") - io.network.finish.bits.header.dst <= UInt<1>("h00") - io.network.finish.bits.header.src <= UInt<1>("h00") - io.network.finish.valid <= UInt<1>("h00") - io.network.grant.ready <= UInt<1>("h00") - io.network.acquire.bits.payload.data <= UInt<1>("h00") - io.network.acquire.bits.payload.union <= UInt<1>("h00") - io.network.acquire.bits.payload.a_type <= UInt<1>("h00") - io.network.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") - io.network.acquire.bits.payload.addr_beat <= UInt<1>("h00") - io.network.acquire.bits.payload.client_xact_id <= UInt<1>("h00") - io.network.acquire.bits.payload.addr_block <= UInt<1>("h00") - io.network.acquire.bits.header.dst <= UInt<1>("h00") - io.network.acquire.bits.header.src <= UInt<1>("h00") - io.network.acquire.valid <= UInt<1>("h00") - io.client.release.ready <= UInt<1>("h00") - io.client.probe.bits.p_type <= UInt<1>("h00") - io.client.probe.bits.addr_block <= UInt<1>("h00") - io.client.probe.valid <= UInt<1>("h00") - io.client.grant.bits.data <= UInt<1>("h00") - io.client.grant.bits.g_type <= UInt<1>("h00") - io.client.grant.bits.is_builtin_type <= UInt<1>("h00") - io.client.grant.bits.manager_xact_id <= UInt<1>("h00") - io.client.grant.bits.client_xact_id <= UInt<1>("h00") - io.client.grant.bits.addr_beat <= UInt<1>("h00") - io.client.grant.valid <= UInt<1>("h00") - io.client.acquire.ready <= UInt<1>("h00") + io is invalid inst finisher of FinishUnit_7 - finisher.io.finish.ready <= UInt<1>("h00") - finisher.io.refill.ready <= UInt<1>("h00") - finisher.io.grant.bits.payload.data <= UInt<1>("h00") - finisher.io.grant.bits.payload.g_type <= UInt<1>("h00") - finisher.io.grant.bits.payload.is_builtin_type <= UInt<1>("h00") - finisher.io.grant.bits.payload.manager_xact_id <= UInt<1>("h00") - finisher.io.grant.bits.payload.client_xact_id <= UInt<1>("h00") - finisher.io.grant.bits.payload.addr_beat <= UInt<1>("h00") - finisher.io.grant.bits.header.dst <= UInt<1>("h00") - finisher.io.grant.bits.header.src <= UInt<1>("h00") - finisher.io.grant.valid <= UInt<1>("h00") + finisher.io is invalid finisher.clk <= clk finisher.reset <= reset finisher.io.grant <- io.network.grant io.network.finish <- finisher.io.finish wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}} - acq_with_header.bits.payload.data <= UInt<1>("h00") - acq_with_header.bits.payload.union <= UInt<1>("h00") - acq_with_header.bits.payload.a_type <= UInt<1>("h00") - acq_with_header.bits.payload.is_builtin_type <= UInt<1>("h00") - acq_with_header.bits.payload.addr_beat <= UInt<1>("h00") - acq_with_header.bits.payload.client_xact_id <= UInt<1>("h00") - acq_with_header.bits.payload.addr_block <= UInt<1>("h00") - acq_with_header.bits.header.dst <= UInt<1>("h00") - acq_with_header.bits.header.src <= UInt<1>("h00") - acq_with_header.valid <= UInt<1>("h00") - acq_with_header.ready <= UInt<1>("h00") + acq_with_header is invalid acq_with_header.bits.payload <- io.client.acquire.bits acq_with_header.bits.header.src <= UInt<1>("h01") acq_with_header.bits.header.dst <= UInt<1>("h00") acq_with_header.valid <= io.client.acquire.valid io.client.acquire.ready <= acq_with_header.ready wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}} - rel_with_header.bits.payload.data <= UInt<1>("h00") - rel_with_header.bits.payload.r_type <= UInt<1>("h00") - rel_with_header.bits.payload.voluntary <= UInt<1>("h00") - rel_with_header.bits.payload.client_xact_id <= UInt<1>("h00") - rel_with_header.bits.payload.addr_block <= UInt<1>("h00") - rel_with_header.bits.payload.addr_beat <= UInt<1>("h00") - rel_with_header.bits.header.dst <= UInt<1>("h00") - rel_with_header.bits.header.src <= UInt<1>("h00") - rel_with_header.valid <= UInt<1>("h00") - rel_with_header.ready <= UInt<1>("h00") + rel_with_header is invalid rel_with_header.bits.payload <- io.client.release.bits rel_with_header.bits.header.src <= UInt<1>("h01") rel_with_header.bits.header.dst <= UInt<1>("h00") rel_with_header.valid <= io.client.release.valid io.client.release.ready <= rel_with_header.ready wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} - prb_without_header.bits.p_type <= UInt<1>("h00") - prb_without_header.bits.addr_block <= UInt<1>("h00") - prb_without_header.valid <= UInt<1>("h00") - prb_without_header.ready <= UInt<1>("h00") + prb_without_header is invalid prb_without_header.valid <= io.network.probe.valid prb_without_header.bits <- io.network.probe.bits.payload io.network.probe.ready <= prb_without_header.ready io.network.acquire.bits <- acq_with_header.bits - node T_5014 = and(acq_with_header.valid, finisher.io.ready) - io.network.acquire.valid <= T_5014 - node T_5015 = and(io.network.acquire.ready, finisher.io.ready) - acq_with_header.ready <= T_5015 + node T_4978 = and(acq_with_header.valid, finisher.io.ready) + io.network.acquire.valid <= T_4978 + node T_4979 = and(io.network.acquire.ready, finisher.io.ready) + acq_with_header.ready <= T_4979 io.network.release <- rel_with_header io.client.probe <- prb_without_header io.client.grant <- finisher.io.refill @@ -1417,19 +1066,7 @@ circuit Top : input reset : UInt<1> output io : {flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, refill : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, ready : UInt<1>} - io.ready <= UInt<1>("h00") - io.finish.bits.payload.manager_xact_id <= UInt<1>("h00") - io.finish.bits.header.dst <= UInt<1>("h00") - io.finish.bits.header.src <= UInt<1>("h00") - io.finish.valid <= UInt<1>("h00") - io.refill.bits.data <= UInt<1>("h00") - io.refill.bits.g_type <= UInt<1>("h00") - io.refill.bits.is_builtin_type <= UInt<1>("h00") - io.refill.bits.manager_xact_id <= UInt<1>("h00") - io.refill.bits.client_xact_id <= UInt<1>("h00") - io.refill.bits.addr_beat <= UInt<1>("h00") - io.refill.valid <= UInt<1>("h00") - io.grant.ready <= UInt<1>("h00") + io is invalid node T_1178 = and(io.grant.ready, io.grant.valid) wire T_1183 : UInt<3>[1] T_1183[0] <= UInt<3>("h05") @@ -1445,183 +1082,113 @@ circuit Top : node T_1199 = mux(io.grant.bits.payload.is_builtin_type, T_1188, T_1198) node T_1200 = and(UInt<1>("h01"), T_1199) node T_1201 = and(T_1178, T_1200) - reg T_1203 : UInt<2>, clk, reset, UInt<2>("h00") + reg T_1203 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) when T_1201 : node T_1205 = eq(T_1203, UInt<2>("h03")) node T_1207 = and(UInt<1>("h00"), T_1205) - node T_1210 = addw(T_1203, UInt<1>("h01")) - node T_1211 = mux(T_1207, UInt<1>("h00"), T_1210) - T_1203 <= T_1211 - skip - node T_1212 = and(T_1201, T_1205) - node T_1213 = mux(T_1200, T_1203, UInt<1>("h00")) - node T_1214 = mux(T_1200, T_1212, T_1178) - inst T_1311 of FinishQueue - T_1311.io.deq.ready <= UInt<1>("h00") - T_1311.io.enq.bits.dst <= UInt<1>("h00") - T_1311.io.enq.bits.fin.manager_xact_id <= UInt<1>("h00") - T_1311.io.enq.valid <= UInt<1>("h00") - T_1311.clk <= clk - T_1311.reset <= reset - node T_1316 = and(io.grant.ready, io.grant.valid) - node T_1319 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1321 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1322 = and(io.grant.bits.payload.is_builtin_type, T_1321) - node T_1324 = eq(T_1322, UInt<1>("h00")) - node T_1325 = and(T_1319, T_1324) - node T_1326 = and(T_1316, T_1325) - wire T_1330 : UInt<3>[1] - T_1330[0] <= UInt<3>("h05") - node T_1333 = eq(T_1330[0], io.grant.bits.payload.g_type) - node T_1335 = or(UInt<1>("h00"), T_1333) - wire T_1337 : UInt<1>[2] - T_1337[0] <= UInt<1>("h00") - T_1337[1] <= UInt<1>("h01") - node T_1341 = eq(T_1337[0], io.grant.bits.payload.g_type) - node T_1342 = eq(T_1337[1], io.grant.bits.payload.g_type) - node T_1344 = or(UInt<1>("h00"), T_1341) - node T_1345 = or(T_1344, T_1342) - node T_1346 = mux(io.grant.bits.payload.is_builtin_type, T_1335, T_1345) - node T_1347 = and(UInt<1>("h01"), T_1346) - node T_1349 = eq(T_1347, UInt<1>("h00")) - node T_1350 = or(T_1349, T_1214) - node T_1351 = and(T_1326, T_1350) - T_1311.io.enq.valid <= T_1351 - wire T_1377 : {manager_xact_id : UInt<4>} - T_1377.manager_xact_id <= UInt<1>("h00") - T_1377.manager_xact_id <= io.grant.bits.payload.manager_xact_id - T_1311.io.enq.bits.fin <- T_1377 - T_1311.io.enq.bits.dst <= io.grant.bits.header.src + node T_1210 = add(T_1203, UInt<1>("h01")) + node T_1211 = tail(T_1210, 1) + node T_1212 = mux(T_1207, UInt<1>("h00"), T_1211) + T_1203 <= T_1212 + skip + node T_1213 = and(T_1201, T_1205) + node T_1214 = mux(T_1200, T_1203, UInt<1>("h00")) + node T_1215 = mux(T_1200, T_1213, T_1178) + inst T_1312 of FinishQueue + T_1312.io is invalid + T_1312.clk <= clk + T_1312.reset <= reset + node T_1313 = and(io.grant.ready, io.grant.valid) + node T_1316 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1318 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) + node T_1319 = and(io.grant.bits.payload.is_builtin_type, T_1318) + node T_1321 = eq(T_1319, UInt<1>("h00")) + node T_1322 = and(T_1316, T_1321) + node T_1323 = and(T_1313, T_1322) + wire T_1327 : UInt<3>[1] + T_1327[0] <= UInt<3>("h05") + node T_1330 = eq(T_1327[0], io.grant.bits.payload.g_type) + node T_1332 = or(UInt<1>("h00"), T_1330) + wire T_1334 : UInt<1>[2] + T_1334[0] <= UInt<1>("h00") + T_1334[1] <= UInt<1>("h01") + node T_1338 = eq(T_1334[0], io.grant.bits.payload.g_type) + node T_1339 = eq(T_1334[1], io.grant.bits.payload.g_type) + node T_1341 = or(UInt<1>("h00"), T_1338) + node T_1342 = or(T_1341, T_1339) + node T_1343 = mux(io.grant.bits.payload.is_builtin_type, T_1332, T_1342) + node T_1344 = and(UInt<1>("h01"), T_1343) + node T_1346 = eq(T_1344, UInt<1>("h00")) + node T_1347 = or(T_1346, T_1215) + node T_1348 = and(T_1323, T_1347) + T_1312.io.enq.valid <= T_1348 + wire T_1374 : {manager_xact_id : UInt<4>} + T_1374 is invalid + T_1374.manager_xact_id <= io.grant.bits.payload.manager_xact_id + T_1312.io.enq.bits.fin <- T_1374 + T_1312.io.enq.bits.dst <= io.grant.bits.header.src io.finish.bits.header.src <= UInt<2>("h02") - io.finish.bits.header.dst <= T_1311.io.deq.bits.dst - io.finish.bits.payload <- T_1311.io.deq.bits.fin - io.finish.valid <= T_1311.io.deq.valid - T_1311.io.deq.ready <= io.finish.ready - node T_1406 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1408 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1409 = and(io.grant.bits.payload.is_builtin_type, T_1408) - node T_1411 = eq(T_1409, UInt<1>("h00")) - node T_1412 = and(T_1406, T_1411) - node T_1414 = eq(T_1412, UInt<1>("h00")) - node T_1415 = or(T_1311.io.enq.ready, T_1414) - node T_1416 = and(T_1415, io.grant.valid) - io.refill.valid <= T_1416 + io.finish.bits.header.dst <= T_1312.io.deq.bits.dst + io.finish.bits.payload <- T_1312.io.deq.bits.fin + io.finish.valid <= T_1312.io.deq.valid + T_1312.io.deq.ready <= io.finish.ready + node T_1402 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1404 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) + node T_1405 = and(io.grant.bits.payload.is_builtin_type, T_1404) + node T_1407 = eq(T_1405, UInt<1>("h00")) + node T_1408 = and(T_1402, T_1407) + node T_1410 = eq(T_1408, UInt<1>("h00")) + node T_1411 = or(T_1312.io.enq.ready, T_1410) + node T_1412 = and(T_1411, io.grant.valid) + io.refill.valid <= T_1412 io.refill.bits <- io.grant.bits.payload - node T_1419 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1421 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) - node T_1422 = and(io.grant.bits.payload.is_builtin_type, T_1421) - node T_1424 = eq(T_1422, UInt<1>("h00")) - node T_1425 = and(T_1419, T_1424) - node T_1427 = eq(T_1425, UInt<1>("h00")) - node T_1428 = or(T_1311.io.enq.ready, T_1427) - node T_1429 = and(T_1428, io.refill.ready) - io.grant.ready <= T_1429 - io.ready <= T_1311.io.enq.ready + node T_1415 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1417 = eq(io.grant.bits.payload.g_type, UInt<3>("h00")) + node T_1418 = and(io.grant.bits.payload.is_builtin_type, T_1417) + node T_1420 = eq(T_1418, UInt<1>("h00")) + node T_1421 = and(T_1415, T_1420) + node T_1423 = eq(T_1421, UInt<1>("h00")) + node T_1424 = or(T_1312.io.enq.ready, T_1423) + node T_1425 = and(T_1424, io.refill.ready) + io.grant.ready <= T_1425 + io.ready <= T_1312.io.enq.ready module ClientTileLinkNetworkPort_15 : input clk : Clock input reset : UInt<1> output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - io.network.release.bits.payload.data <= UInt<1>("h00") - io.network.release.bits.payload.r_type <= UInt<1>("h00") - io.network.release.bits.payload.voluntary <= UInt<1>("h00") - io.network.release.bits.payload.client_xact_id <= UInt<1>("h00") - io.network.release.bits.payload.addr_block <= UInt<1>("h00") - io.network.release.bits.payload.addr_beat <= UInt<1>("h00") - io.network.release.bits.header.dst <= UInt<1>("h00") - io.network.release.bits.header.src <= UInt<1>("h00") - io.network.release.valid <= UInt<1>("h00") - io.network.probe.ready <= UInt<1>("h00") - io.network.finish.bits.payload.manager_xact_id <= UInt<1>("h00") - io.network.finish.bits.header.dst <= UInt<1>("h00") - io.network.finish.bits.header.src <= UInt<1>("h00") - io.network.finish.valid <= UInt<1>("h00") - io.network.grant.ready <= UInt<1>("h00") - io.network.acquire.bits.payload.data <= UInt<1>("h00") - io.network.acquire.bits.payload.union <= UInt<1>("h00") - io.network.acquire.bits.payload.a_type <= UInt<1>("h00") - io.network.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") - io.network.acquire.bits.payload.addr_beat <= UInt<1>("h00") - io.network.acquire.bits.payload.client_xact_id <= UInt<1>("h00") - io.network.acquire.bits.payload.addr_block <= UInt<1>("h00") - io.network.acquire.bits.header.dst <= UInt<1>("h00") - io.network.acquire.bits.header.src <= UInt<1>("h00") - io.network.acquire.valid <= UInt<1>("h00") - io.client.release.ready <= UInt<1>("h00") - io.client.probe.bits.p_type <= UInt<1>("h00") - io.client.probe.bits.addr_block <= UInt<1>("h00") - io.client.probe.valid <= UInt<1>("h00") - io.client.grant.bits.data <= UInt<1>("h00") - io.client.grant.bits.g_type <= UInt<1>("h00") - io.client.grant.bits.is_builtin_type <= UInt<1>("h00") - io.client.grant.bits.manager_xact_id <= UInt<1>("h00") - io.client.grant.bits.client_xact_id <= UInt<1>("h00") - io.client.grant.bits.addr_beat <= UInt<1>("h00") - io.client.grant.valid <= UInt<1>("h00") - io.client.acquire.ready <= UInt<1>("h00") + io is invalid inst finisher of FinishUnit_16 - finisher.io.finish.ready <= UInt<1>("h00") - finisher.io.refill.ready <= UInt<1>("h00") - finisher.io.grant.bits.payload.data <= UInt<1>("h00") - finisher.io.grant.bits.payload.g_type <= UInt<1>("h00") - finisher.io.grant.bits.payload.is_builtin_type <= UInt<1>("h00") - finisher.io.grant.bits.payload.manager_xact_id <= UInt<1>("h00") - finisher.io.grant.bits.payload.client_xact_id <= UInt<1>("h00") - finisher.io.grant.bits.payload.addr_beat <= UInt<1>("h00") - finisher.io.grant.bits.header.dst <= UInt<1>("h00") - finisher.io.grant.bits.header.src <= UInt<1>("h00") - finisher.io.grant.valid <= UInt<1>("h00") + finisher.io is invalid finisher.clk <= clk finisher.reset <= reset finisher.io.grant <- io.network.grant io.network.finish <- finisher.io.finish wire acq_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}} - acq_with_header.bits.payload.data <= UInt<1>("h00") - acq_with_header.bits.payload.union <= UInt<1>("h00") - acq_with_header.bits.payload.a_type <= UInt<1>("h00") - acq_with_header.bits.payload.is_builtin_type <= UInt<1>("h00") - acq_with_header.bits.payload.addr_beat <= UInt<1>("h00") - acq_with_header.bits.payload.client_xact_id <= UInt<1>("h00") - acq_with_header.bits.payload.addr_block <= UInt<1>("h00") - acq_with_header.bits.header.dst <= UInt<1>("h00") - acq_with_header.bits.header.src <= UInt<1>("h00") - acq_with_header.valid <= UInt<1>("h00") - acq_with_header.ready <= UInt<1>("h00") + acq_with_header is invalid acq_with_header.bits.payload <- io.client.acquire.bits acq_with_header.bits.header.src <= UInt<2>("h02") acq_with_header.bits.header.dst <= UInt<1>("h00") acq_with_header.valid <= io.client.acquire.valid io.client.acquire.ready <= acq_with_header.ready wire rel_with_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}} - rel_with_header.bits.payload.data <= UInt<1>("h00") - rel_with_header.bits.payload.r_type <= UInt<1>("h00") - rel_with_header.bits.payload.voluntary <= UInt<1>("h00") - rel_with_header.bits.payload.client_xact_id <= UInt<1>("h00") - rel_with_header.bits.payload.addr_block <= UInt<1>("h00") - rel_with_header.bits.payload.addr_beat <= UInt<1>("h00") - rel_with_header.bits.header.dst <= UInt<1>("h00") - rel_with_header.bits.header.src <= UInt<1>("h00") - rel_with_header.valid <= UInt<1>("h00") - rel_with_header.ready <= UInt<1>("h00") + rel_with_header is invalid rel_with_header.bits.payload <- io.client.release.bits rel_with_header.bits.header.src <= UInt<2>("h02") rel_with_header.bits.header.dst <= UInt<1>("h00") rel_with_header.valid <= io.client.release.valid io.client.release.ready <= rel_with_header.ready wire prb_without_header : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}} - prb_without_header.bits.p_type <= UInt<1>("h00") - prb_without_header.bits.addr_block <= UInt<1>("h00") - prb_without_header.valid <= UInt<1>("h00") - prb_without_header.ready <= UInt<1>("h00") + prb_without_header is invalid prb_without_header.valid <= io.network.probe.valid prb_without_header.bits <- io.network.probe.bits.payload io.network.probe.ready <= prb_without_header.ready io.network.acquire.bits <- acq_with_header.bits - node T_5014 = and(acq_with_header.valid, finisher.io.ready) - io.network.acquire.valid <= T_5014 - node T_5015 = and(io.network.acquire.ready, finisher.io.ready) - acq_with_header.ready <= T_5015 + node T_4978 = and(acq_with_header.valid, finisher.io.ready) + io.network.acquire.valid <= T_4978 + node T_4979 = and(io.network.acquire.ready, finisher.io.ready) + acq_with_header.ready <= T_4979 io.network.release <- rel_with_header io.client.probe <- prb_without_header io.client.grant <- finisher.io.refill @@ -1631,132 +1198,52 @@ circuit Top : input reset : UInt<1> output io : {flip manager : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, client_id : UInt<2>}}}, flip network : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - io.network.release.ready <= UInt<1>("h00") - io.network.probe.bits.payload.p_type <= UInt<1>("h00") - io.network.probe.bits.payload.addr_block <= UInt<1>("h00") - io.network.probe.bits.header.dst <= UInt<1>("h00") - io.network.probe.bits.header.src <= UInt<1>("h00") - io.network.probe.valid <= UInt<1>("h00") - io.network.finish.ready <= UInt<1>("h00") - io.network.grant.bits.payload.data <= UInt<1>("h00") - io.network.grant.bits.payload.g_type <= UInt<1>("h00") - io.network.grant.bits.payload.is_builtin_type <= UInt<1>("h00") - io.network.grant.bits.payload.manager_xact_id <= UInt<1>("h00") - io.network.grant.bits.payload.client_xact_id <= UInt<1>("h00") - io.network.grant.bits.payload.addr_beat <= UInt<1>("h00") - io.network.grant.bits.header.dst <= UInt<1>("h00") - io.network.grant.bits.header.src <= UInt<1>("h00") - io.network.grant.valid <= UInt<1>("h00") - io.network.acquire.ready <= UInt<1>("h00") - io.manager.release.bits.client_id <= UInt<1>("h00") - io.manager.release.bits.data <= UInt<1>("h00") - io.manager.release.bits.r_type <= UInt<1>("h00") - io.manager.release.bits.voluntary <= UInt<1>("h00") - io.manager.release.bits.client_xact_id <= UInt<1>("h00") - io.manager.release.bits.addr_block <= UInt<1>("h00") - io.manager.release.bits.addr_beat <= UInt<1>("h00") - io.manager.release.valid <= UInt<1>("h00") - io.manager.probe.ready <= UInt<1>("h00") - io.manager.finish.bits.manager_xact_id <= UInt<1>("h00") - io.manager.finish.valid <= UInt<1>("h00") - io.manager.grant.ready <= UInt<1>("h00") - io.manager.acquire.bits.client_id <= UInt<1>("h00") - io.manager.acquire.bits.data <= UInt<1>("h00") - io.manager.acquire.bits.union <= UInt<1>("h00") - io.manager.acquire.bits.a_type <= UInt<1>("h00") - io.manager.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.manager.acquire.bits.addr_beat <= UInt<1>("h00") - io.manager.acquire.bits.client_xact_id <= UInt<1>("h00") - io.manager.acquire.bits.addr_block <= UInt<1>("h00") - io.manager.acquire.valid <= UInt<1>("h00") + io is invalid wire T_6833 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}} - T_6833.bits.payload.client_id <= UInt<1>("h00") - T_6833.bits.payload.data <= UInt<1>("h00") - T_6833.bits.payload.g_type <= UInt<1>("h00") - T_6833.bits.payload.is_builtin_type <= UInt<1>("h00") - T_6833.bits.payload.manager_xact_id <= UInt<1>("h00") - T_6833.bits.payload.client_xact_id <= UInt<1>("h00") - T_6833.bits.payload.addr_beat <= UInt<1>("h00") - T_6833.bits.header.dst <= UInt<1>("h00") - T_6833.bits.header.src <= UInt<1>("h00") - T_6833.valid <= UInt<1>("h00") - T_6833.ready <= UInt<1>("h00") + T_6833 is invalid T_6833.bits.payload <- io.manager.grant.bits T_6833.bits.header.src <= UInt<1>("h00") T_6833.bits.header.dst <= io.manager.grant.bits.client_id T_6833.valid <= io.manager.grant.valid io.manager.grant.ready <= T_6833.ready io.network.grant <- T_6833 - wire T_7474 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}} - T_7474.bits.payload.client_id <= UInt<1>("h00") - T_7474.bits.payload.p_type <= UInt<1>("h00") - T_7474.bits.payload.addr_block <= UInt<1>("h00") - T_7474.bits.header.dst <= UInt<1>("h00") - T_7474.bits.header.src <= UInt<1>("h00") - T_7474.valid <= UInt<1>("h00") - T_7474.ready <= UInt<1>("h00") - T_7474.bits.payload <- io.manager.probe.bits - T_7474.bits.header.src <= UInt<1>("h00") - T_7474.bits.header.dst <= io.manager.probe.bits.client_id - T_7474.valid <= io.manager.probe.valid - io.manager.probe.ready <= T_7474.ready - io.network.probe <- T_7474 + wire T_7463 : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}} + T_7463 is invalid + T_7463.bits.payload <- io.manager.probe.bits + T_7463.bits.header.src <= UInt<1>("h00") + T_7463.bits.header.dst <= io.manager.probe.bits.client_id + T_7463.valid <= io.manager.probe.valid + io.manager.probe.ready <= T_7463.ready + io.network.probe <- T_7463 io.manager.acquire.bits.client_id <= io.network.acquire.bits.header.src - wire T_7796 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}} - T_7796.bits.data <= UInt<1>("h00") - T_7796.bits.union <= UInt<1>("h00") - T_7796.bits.a_type <= UInt<1>("h00") - T_7796.bits.is_builtin_type <= UInt<1>("h00") - T_7796.bits.addr_beat <= UInt<1>("h00") - T_7796.bits.client_xact_id <= UInt<1>("h00") - T_7796.bits.addr_block <= UInt<1>("h00") - T_7796.valid <= UInt<1>("h00") - T_7796.ready <= UInt<1>("h00") - T_7796.valid <= io.network.acquire.valid - T_7796.bits <- io.network.acquire.bits.payload - io.network.acquire.ready <= T_7796.ready - io.manager.acquire <- T_7796 + wire T_7778 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}} + T_7778 is invalid + T_7778.valid <= io.network.acquire.valid + T_7778.bits <- io.network.acquire.bits.payload + io.network.acquire.ready <= T_7778.ready + io.manager.acquire <- T_7778 io.manager.release.bits.client_id <= io.network.release.bits.header.src - wire T_7933 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}} - T_7933.bits.data <= UInt<1>("h00") - T_7933.bits.r_type <= UInt<1>("h00") - T_7933.bits.voluntary <= UInt<1>("h00") - T_7933.bits.client_xact_id <= UInt<1>("h00") - T_7933.bits.addr_block <= UInt<1>("h00") - T_7933.bits.addr_beat <= UInt<1>("h00") - T_7933.valid <= UInt<1>("h00") - T_7933.ready <= UInt<1>("h00") - T_7933.valid <= io.network.release.valid - T_7933.bits <- io.network.release.bits.payload - io.network.release.ready <= T_7933.ready - io.manager.release <- T_7933 - wire T_8057 : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}} - T_8057.bits.manager_xact_id <= UInt<1>("h00") - T_8057.valid <= UInt<1>("h00") - T_8057.ready <= UInt<1>("h00") - T_8057.valid <= io.network.finish.valid - T_8057.bits <- io.network.finish.bits.payload - io.network.finish.ready <= T_8057.ready - io.manager.finish <- T_8057 + wire T_7906 : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}} + T_7906 is invalid + T_7906.valid <= io.network.release.valid + T_7906.bits <- io.network.release.bits.payload + io.network.release.ready <= T_7906.ready + io.manager.release <- T_7906 + wire T_8022 : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}} + T_8022 is invalid + T_8022.valid <= io.network.finish.valid + T_8022.bits <- io.network.finish.bits.payload + io.network.finish.ready <= T_8022.ready + io.manager.finish <- T_8022 module Queue_25 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, count : UInt<1>} - io.count <= UInt<1>("h00") - io.deq.bits.payload.data <= UInt<1>("h00") - io.deq.bits.payload.r_type <= UInt<1>("h00") - io.deq.bits.payload.voluntary <= UInt<1>("h00") - io.deq.bits.payload.client_xact_id <= UInt<1>("h00") - io.deq.bits.payload.addr_block <= UInt<1>("h00") - io.deq.bits.payload.addr_beat <= UInt<1>("h00") - io.deq.bits.header.dst <= UInt<1>("h00") - io.deq.bits.header.src <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}[1] - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) node T_1156 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_1156) @@ -1788,77 +1275,24 @@ circuit Top : node T_1308 = or(T_1305, T_1307) io.enq.ready <= T_1308 infer mport T_1309 = ram[UInt<1>("h00")], clk - wire T_1561 : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}} - T_1561 <- T_1309 - when maybe_flow : - T_1561 <- io.enq.bits - skip - io.deq.bits <- T_1561 - node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) - node T_1688 = and(maybe_full, ptr_match) - node T_1689 = cat(T_1688, ptr_diff) - io.count <= T_1689 + node T_1435 = mux(maybe_flow, io.enq.bits, T_1309) + io.deq.bits <- T_1435 + node T_1561 = sub(UInt<1>("h00"), UInt<1>("h00")) + node ptr_diff = tail(T_1561, 1) + node T_1563 = and(maybe_full, ptr_match) + node T_1564 = cat(T_1563, ptr_diff) + io.count <= T_1564 module TileLinkEnqueuer_24 : input clk : Clock input reset : UInt<1> output io : {flip client : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}, manager : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, p_type : UInt<2>}}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}}} - io.manager.release.bits.payload.data <= UInt<1>("h00") - io.manager.release.bits.payload.r_type <= UInt<1>("h00") - io.manager.release.bits.payload.voluntary <= UInt<1>("h00") - io.manager.release.bits.payload.client_xact_id <= UInt<1>("h00") - io.manager.release.bits.payload.addr_block <= UInt<1>("h00") - io.manager.release.bits.payload.addr_beat <= UInt<1>("h00") - io.manager.release.bits.header.dst <= UInt<1>("h00") - io.manager.release.bits.header.src <= UInt<1>("h00") - io.manager.release.valid <= UInt<1>("h00") - io.manager.probe.ready <= UInt<1>("h00") - io.manager.finish.bits.payload.manager_xact_id <= UInt<1>("h00") - io.manager.finish.bits.header.dst <= UInt<1>("h00") - io.manager.finish.bits.header.src <= UInt<1>("h00") - io.manager.finish.valid <= UInt<1>("h00") - io.manager.grant.ready <= UInt<1>("h00") - io.manager.acquire.bits.payload.data <= UInt<1>("h00") - io.manager.acquire.bits.payload.union <= UInt<1>("h00") - io.manager.acquire.bits.payload.a_type <= UInt<1>("h00") - io.manager.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") - io.manager.acquire.bits.payload.addr_beat <= UInt<1>("h00") - io.manager.acquire.bits.payload.client_xact_id <= UInt<1>("h00") - io.manager.acquire.bits.payload.addr_block <= UInt<1>("h00") - io.manager.acquire.bits.header.dst <= UInt<1>("h00") - io.manager.acquire.bits.header.src <= UInt<1>("h00") - io.manager.acquire.valid <= UInt<1>("h00") - io.client.release.ready <= UInt<1>("h00") - io.client.probe.bits.payload.p_type <= UInt<1>("h00") - io.client.probe.bits.payload.addr_block <= UInt<1>("h00") - io.client.probe.bits.header.dst <= UInt<1>("h00") - io.client.probe.bits.header.src <= UInt<1>("h00") - io.client.probe.valid <= UInt<1>("h00") - io.client.finish.ready <= UInt<1>("h00") - io.client.grant.bits.payload.data <= UInt<1>("h00") - io.client.grant.bits.payload.g_type <= UInt<1>("h00") - io.client.grant.bits.payload.is_builtin_type <= UInt<1>("h00") - io.client.grant.bits.payload.manager_xact_id <= UInt<1>("h00") - io.client.grant.bits.payload.client_xact_id <= UInt<1>("h00") - io.client.grant.bits.payload.addr_beat <= UInt<1>("h00") - io.client.grant.bits.header.dst <= UInt<1>("h00") - io.client.grant.bits.header.src <= UInt<1>("h00") - io.client.grant.valid <= UInt<1>("h00") - io.client.acquire.ready <= UInt<1>("h00") + io is invalid io.manager.acquire <- io.client.acquire io.client.probe <- io.manager.probe inst T_7777 of Queue_25 - T_7777.io.deq.ready <= UInt<1>("h00") - T_7777.io.enq.bits.payload.data <= UInt<1>("h00") - T_7777.io.enq.bits.payload.r_type <= UInt<1>("h00") - T_7777.io.enq.bits.payload.voluntary <= UInt<1>("h00") - T_7777.io.enq.bits.payload.client_xact_id <= UInt<1>("h00") - T_7777.io.enq.bits.payload.addr_block <= UInt<1>("h00") - T_7777.io.enq.bits.payload.addr_beat <= UInt<1>("h00") - T_7777.io.enq.bits.header.dst <= UInt<1>("h00") - T_7777.io.enq.bits.header.src <= UInt<1>("h00") - T_7777.io.enq.valid <= UInt<1>("h00") + T_7777.io is invalid T_7777.clk <= clk T_7777.reset <= reset T_7777.io.enq.valid <= io.client.release.valid @@ -1873,78 +1307,66 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}}, chosen : UInt<2>} - io.chosen <= UInt<1>("h00") - io.out.bits.payload.data <= UInt<1>("h00") - io.out.bits.payload.union <= UInt<1>("h00") - io.out.bits.payload.a_type <= UInt<1>("h00") - io.out.bits.payload.is_builtin_type <= UInt<1>("h00") - io.out.bits.payload.addr_beat <= UInt<1>("h00") - io.out.bits.payload.client_xact_id <= UInt<1>("h00") - io.out.bits.payload.addr_block <= UInt<1>("h00") - io.out.bits.header.dst <= UInt<1>("h00") - io.out.bits.header.src <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") - io.in[2].ready <= UInt<1>("h00") - reg T_3348 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_3350 : UInt<?>, clk, reset, UInt<2>("h02") + io is invalid + reg T_3348 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_3350 : UInt<?>, clk with : (reset => (reset, UInt<2>("h02"))) wire T_3352 : UInt<2> - T_3352 <= UInt<1>("h00") + T_3352 is invalid io.out.valid <= io.in[T_3352].valid io.out.bits <- io.in[T_3352].bits io.chosen <= T_3352 io.in[T_3352].ready <= UInt<1>("h00") - reg last_grant : UInt<2>, clk, reset, UInt<2>("h00") - node T_4129 = gt(UInt<1>("h00"), last_grant) - node T_4130 = and(io.in[0].valid, T_4129) - node T_4132 = gt(UInt<1>("h01"), last_grant) - node T_4133 = and(io.in[1].valid, T_4132) - node T_4135 = gt(UInt<2>("h02"), last_grant) - node T_4136 = and(io.in[2].valid, T_4135) - node T_4139 = or(UInt<1>("h00"), T_4130) - node T_4141 = eq(T_4139, UInt<1>("h00")) - node T_4143 = or(UInt<1>("h00"), T_4130) - node T_4144 = or(T_4143, T_4133) - node T_4146 = eq(T_4144, UInt<1>("h00")) - node T_4148 = or(UInt<1>("h00"), T_4130) - node T_4149 = or(T_4148, T_4133) - node T_4150 = or(T_4149, T_4136) - node T_4152 = eq(T_4150, UInt<1>("h00")) - node T_4154 = or(UInt<1>("h00"), T_4130) - node T_4155 = or(T_4154, T_4133) - node T_4156 = or(T_4155, T_4136) - node T_4157 = or(T_4156, io.in[0].valid) - node T_4159 = eq(T_4157, UInt<1>("h00")) - node T_4161 = or(UInt<1>("h00"), T_4130) - node T_4162 = or(T_4161, T_4133) - node T_4163 = or(T_4162, T_4136) - node T_4164 = or(T_4163, io.in[0].valid) - node T_4165 = or(T_4164, io.in[1].valid) - node T_4167 = eq(T_4165, UInt<1>("h00")) - node T_4169 = gt(UInt<1>("h00"), last_grant) - node T_4170 = and(UInt<1>("h01"), T_4169) - node T_4171 = or(T_4170, T_4152) - node T_4173 = gt(UInt<1>("h01"), last_grant) - node T_4174 = and(T_4141, T_4173) - node T_4175 = or(T_4174, T_4159) - node T_4177 = gt(UInt<2>("h02"), last_grant) - node T_4178 = and(T_4146, T_4177) - node T_4179 = or(T_4178, T_4167) - node T_4181 = eq(T_3350, UInt<1>("h00")) - node T_4182 = mux(T_3348, T_4181, T_4171) - node T_4183 = and(T_4182, io.out.ready) - io.in[0].ready <= T_4183 - node T_4185 = eq(T_3350, UInt<1>("h01")) - node T_4186 = mux(T_3348, T_4185, T_4175) - node T_4187 = and(T_4186, io.out.ready) - io.in[1].ready <= T_4187 - node T_4189 = eq(T_3350, UInt<2>("h02")) - node T_4190 = mux(T_3348, T_4189, T_4179) - node T_4191 = and(T_4190, io.out.ready) - io.in[2].ready <= T_4191 - reg T_4193 : UInt<2>, clk, reset, UInt<2>("h00") - node T_4195 = addw(T_4193, UInt<1>("h01")) + reg last_grant : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + node T_4128 = gt(UInt<1>("h00"), last_grant) + node T_4129 = and(io.in[0].valid, T_4128) + node T_4131 = gt(UInt<1>("h01"), last_grant) + node T_4132 = and(io.in[1].valid, T_4131) + node T_4134 = gt(UInt<2>("h02"), last_grant) + node T_4135 = and(io.in[2].valid, T_4134) + node T_4138 = or(UInt<1>("h00"), T_4129) + node T_4140 = eq(T_4138, UInt<1>("h00")) + node T_4142 = or(UInt<1>("h00"), T_4129) + node T_4143 = or(T_4142, T_4132) + node T_4145 = eq(T_4143, UInt<1>("h00")) + node T_4147 = or(UInt<1>("h00"), T_4129) + node T_4148 = or(T_4147, T_4132) + node T_4149 = or(T_4148, T_4135) + node T_4151 = eq(T_4149, UInt<1>("h00")) + node T_4153 = or(UInt<1>("h00"), T_4129) + node T_4154 = or(T_4153, T_4132) + node T_4155 = or(T_4154, T_4135) + node T_4156 = or(T_4155, io.in[0].valid) + node T_4158 = eq(T_4156, UInt<1>("h00")) + node T_4160 = or(UInt<1>("h00"), T_4129) + node T_4161 = or(T_4160, T_4132) + node T_4162 = or(T_4161, T_4135) + node T_4163 = or(T_4162, io.in[0].valid) + node T_4164 = or(T_4163, io.in[1].valid) + node T_4166 = eq(T_4164, UInt<1>("h00")) + node T_4168 = gt(UInt<1>("h00"), last_grant) + node T_4169 = and(UInt<1>("h01"), T_4168) + node T_4170 = or(T_4169, T_4151) + node T_4172 = gt(UInt<1>("h01"), last_grant) + node T_4173 = and(T_4140, T_4172) + node T_4174 = or(T_4173, T_4158) + node T_4176 = gt(UInt<2>("h02"), last_grant) + node T_4177 = and(T_4145, T_4176) + node T_4178 = or(T_4177, T_4166) + node T_4180 = eq(T_3350, UInt<1>("h00")) + node T_4181 = mux(T_3348, T_4180, T_4170) + node T_4182 = and(T_4181, io.out.ready) + io.in[0].ready <= T_4182 + node T_4184 = eq(T_3350, UInt<1>("h01")) + node T_4185 = mux(T_3348, T_4184, T_4174) + node T_4186 = and(T_4185, io.out.ready) + io.in[1].ready <= T_4186 + node T_4188 = eq(T_3350, UInt<2>("h02")) + node T_4189 = mux(T_3348, T_4188, T_4178) + node T_4190 = and(T_4189, io.out.ready) + io.in[2].ready <= T_4190 + reg T_4192 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + node T_4194 = add(T_4192, UInt<1>("h01")) + node T_4195 = tail(T_4194, 1) node T_4196 = and(io.out.ready, io.out.valid) when T_4196 : node T_4198 = and(UInt<1>("h01"), io.out.bits.payload.is_builtin_type) @@ -1954,7 +1376,7 @@ circuit Top : node T_4206 = or(UInt<1>("h00"), T_4204) node T_4207 = and(T_4198, T_4206) when T_4207 : - T_4193 <= T_4195 + T_4192 <= T_4195 node T_4209 = eq(T_3348, UInt<1>("h00")) when T_4209 : T_3348 <= UInt<1>("h01") @@ -1995,77 +1417,66 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, chosen : UInt<2>} - io.chosen <= UInt<1>("h00") - io.out.bits.payload.data <= UInt<1>("h00") - io.out.bits.payload.r_type <= UInt<1>("h00") - io.out.bits.payload.voluntary <= UInt<1>("h00") - io.out.bits.payload.client_xact_id <= UInt<1>("h00") - io.out.bits.payload.addr_block <= UInt<1>("h00") - io.out.bits.payload.addr_beat <= UInt<1>("h00") - io.out.bits.header.dst <= UInt<1>("h00") - io.out.bits.header.src <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") - io.in[2].ready <= UInt<1>("h00") - reg T_3322 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_3324 : UInt<?>, clk, reset, UInt<2>("h02") + io is invalid + reg T_3322 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_3324 : UInt<?>, clk with : (reset => (reset, UInt<2>("h02"))) wire T_3326 : UInt<2> - T_3326 <= UInt<1>("h00") + T_3326 is invalid io.out.valid <= io.in[T_3326].valid io.out.bits <- io.in[T_3326].bits io.chosen <= T_3326 io.in[T_3326].ready <= UInt<1>("h00") - reg last_grant : UInt<2>, clk, reset, UInt<2>("h00") - node T_4097 = gt(UInt<1>("h00"), last_grant) - node T_4098 = and(io.in[0].valid, T_4097) - node T_4100 = gt(UInt<1>("h01"), last_grant) - node T_4101 = and(io.in[1].valid, T_4100) - node T_4103 = gt(UInt<2>("h02"), last_grant) - node T_4104 = and(io.in[2].valid, T_4103) - node T_4107 = or(UInt<1>("h00"), T_4098) - node T_4109 = eq(T_4107, UInt<1>("h00")) - node T_4111 = or(UInt<1>("h00"), T_4098) - node T_4112 = or(T_4111, T_4101) - node T_4114 = eq(T_4112, UInt<1>("h00")) - node T_4116 = or(UInt<1>("h00"), T_4098) - node T_4117 = or(T_4116, T_4101) - node T_4118 = or(T_4117, T_4104) - node T_4120 = eq(T_4118, UInt<1>("h00")) - node T_4122 = or(UInt<1>("h00"), T_4098) - node T_4123 = or(T_4122, T_4101) - node T_4124 = or(T_4123, T_4104) - node T_4125 = or(T_4124, io.in[0].valid) - node T_4127 = eq(T_4125, UInt<1>("h00")) - node T_4129 = or(UInt<1>("h00"), T_4098) - node T_4130 = or(T_4129, T_4101) - node T_4131 = or(T_4130, T_4104) - node T_4132 = or(T_4131, io.in[0].valid) - node T_4133 = or(T_4132, io.in[1].valid) - node T_4135 = eq(T_4133, UInt<1>("h00")) - node T_4137 = gt(UInt<1>("h00"), last_grant) - node T_4138 = and(UInt<1>("h01"), T_4137) - node T_4139 = or(T_4138, T_4120) - node T_4141 = gt(UInt<1>("h01"), last_grant) - node T_4142 = and(T_4109, T_4141) - node T_4143 = or(T_4142, T_4127) - node T_4145 = gt(UInt<2>("h02"), last_grant) - node T_4146 = and(T_4114, T_4145) - node T_4147 = or(T_4146, T_4135) - node T_4149 = eq(T_3324, UInt<1>("h00")) - node T_4150 = mux(T_3322, T_4149, T_4139) - node T_4151 = and(T_4150, io.out.ready) - io.in[0].ready <= T_4151 - node T_4153 = eq(T_3324, UInt<1>("h01")) - node T_4154 = mux(T_3322, T_4153, T_4143) - node T_4155 = and(T_4154, io.out.ready) - io.in[1].ready <= T_4155 - node T_4157 = eq(T_3324, UInt<2>("h02")) - node T_4158 = mux(T_3322, T_4157, T_4147) - node T_4159 = and(T_4158, io.out.ready) - io.in[2].ready <= T_4159 - reg T_4161 : UInt<2>, clk, reset, UInt<2>("h00") - node T_4163 = addw(T_4161, UInt<1>("h01")) + reg last_grant : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + node T_4096 = gt(UInt<1>("h00"), last_grant) + node T_4097 = and(io.in[0].valid, T_4096) + node T_4099 = gt(UInt<1>("h01"), last_grant) + node T_4100 = and(io.in[1].valid, T_4099) + node T_4102 = gt(UInt<2>("h02"), last_grant) + node T_4103 = and(io.in[2].valid, T_4102) + node T_4106 = or(UInt<1>("h00"), T_4097) + node T_4108 = eq(T_4106, UInt<1>("h00")) + node T_4110 = or(UInt<1>("h00"), T_4097) + node T_4111 = or(T_4110, T_4100) + node T_4113 = eq(T_4111, UInt<1>("h00")) + node T_4115 = or(UInt<1>("h00"), T_4097) + node T_4116 = or(T_4115, T_4100) + node T_4117 = or(T_4116, T_4103) + node T_4119 = eq(T_4117, UInt<1>("h00")) + node T_4121 = or(UInt<1>("h00"), T_4097) + node T_4122 = or(T_4121, T_4100) + node T_4123 = or(T_4122, T_4103) + node T_4124 = or(T_4123, io.in[0].valid) + node T_4126 = eq(T_4124, UInt<1>("h00")) + node T_4128 = or(UInt<1>("h00"), T_4097) + node T_4129 = or(T_4128, T_4100) + node T_4130 = or(T_4129, T_4103) + node T_4131 = or(T_4130, io.in[0].valid) + node T_4132 = or(T_4131, io.in[1].valid) + node T_4134 = eq(T_4132, UInt<1>("h00")) + node T_4136 = gt(UInt<1>("h00"), last_grant) + node T_4137 = and(UInt<1>("h01"), T_4136) + node T_4138 = or(T_4137, T_4119) + node T_4140 = gt(UInt<1>("h01"), last_grant) + node T_4141 = and(T_4108, T_4140) + node T_4142 = or(T_4141, T_4126) + node T_4144 = gt(UInt<2>("h02"), last_grant) + node T_4145 = and(T_4113, T_4144) + node T_4146 = or(T_4145, T_4134) + node T_4148 = eq(T_3324, UInt<1>("h00")) + node T_4149 = mux(T_3322, T_4148, T_4138) + node T_4150 = and(T_4149, io.out.ready) + io.in[0].ready <= T_4150 + node T_4152 = eq(T_3324, UInt<1>("h01")) + node T_4153 = mux(T_3322, T_4152, T_4142) + node T_4154 = and(T_4153, io.out.ready) + io.in[1].ready <= T_4154 + node T_4156 = eq(T_3324, UInt<2>("h02")) + node T_4157 = mux(T_3322, T_4156, T_4146) + node T_4158 = and(T_4157, io.out.ready) + io.in[2].ready <= T_4158 + reg T_4160 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + node T_4162 = add(T_4160, UInt<1>("h01")) + node T_4163 = tail(T_4162, 1) node T_4164 = and(io.out.ready, io.out.valid) when T_4164 : wire T_4167 : UInt<2>[3] @@ -2080,7 +1491,7 @@ circuit Top : node T_4178 = or(T_4177, T_4174) node T_4179 = and(UInt<1>("h01"), T_4178) when T_4179 : - T_4161 <= T_4163 + T_4160 <= T_4163 node T_4181 = eq(T_3322, UInt<1>("h00")) when T_4181 : T_3322 <= UInt<1>("h01") @@ -2121,81 +1532,74 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {header : {src : UInt<2>, dst : UInt<2>}, payload : {manager_xact_id : UInt<4>}}}, chosen : UInt<2>} - io.chosen <= UInt<1>("h00") - io.out.bits.payload.manager_xact_id <= UInt<1>("h00") - io.out.bits.header.dst <= UInt<1>("h00") - io.out.bits.header.src <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") - io.in[2].ready <= UInt<1>("h00") + io is invalid wire T_3194 : UInt<2> - T_3194 <= UInt<1>("h00") + T_3194 is invalid io.out.valid <= io.in[T_3194].valid io.out.bits <- io.in[T_3194].bits io.chosen <= T_3194 io.in[T_3194].ready <= UInt<1>("h00") - reg T_3934 : UInt<2>, clk, reset, UInt<2>("h00") - node T_3935 = gt(UInt<1>("h00"), T_3934) - node T_3936 = and(io.in[0].valid, T_3935) - node T_3938 = gt(UInt<1>("h01"), T_3934) - node T_3939 = and(io.in[1].valid, T_3938) - node T_3941 = gt(UInt<2>("h02"), T_3934) - node T_3942 = and(io.in[2].valid, T_3941) - node T_3945 = or(UInt<1>("h00"), T_3936) - node T_3947 = eq(T_3945, UInt<1>("h00")) - node T_3949 = or(UInt<1>("h00"), T_3936) - node T_3950 = or(T_3949, T_3939) - node T_3952 = eq(T_3950, UInt<1>("h00")) - node T_3954 = or(UInt<1>("h00"), T_3936) - node T_3955 = or(T_3954, T_3939) - node T_3956 = or(T_3955, T_3942) - node T_3958 = eq(T_3956, UInt<1>("h00")) - node T_3960 = or(UInt<1>("h00"), T_3936) - node T_3961 = or(T_3960, T_3939) - node T_3962 = or(T_3961, T_3942) - node T_3963 = or(T_3962, io.in[0].valid) - node T_3965 = eq(T_3963, UInt<1>("h00")) - node T_3967 = or(UInt<1>("h00"), T_3936) - node T_3968 = or(T_3967, T_3939) - node T_3969 = or(T_3968, T_3942) - node T_3970 = or(T_3969, io.in[0].valid) - node T_3971 = or(T_3970, io.in[1].valid) - node T_3973 = eq(T_3971, UInt<1>("h00")) - node T_3975 = gt(UInt<1>("h00"), T_3934) - node T_3976 = and(UInt<1>("h01"), T_3975) - node T_3977 = or(T_3976, T_3958) - node T_3979 = gt(UInt<1>("h01"), T_3934) - node T_3980 = and(T_3947, T_3979) - node T_3981 = or(T_3980, T_3965) - node T_3983 = gt(UInt<2>("h02"), T_3934) - node T_3984 = and(T_3952, T_3983) - node T_3985 = or(T_3984, T_3973) - node T_3987 = eq(UInt<2>("h02"), UInt<1>("h00")) - node T_3988 = mux(UInt<1>("h00"), T_3987, T_3977) - node T_3989 = and(T_3988, io.out.ready) - io.in[0].ready <= T_3989 - node T_3991 = eq(UInt<2>("h02"), UInt<1>("h01")) - node T_3992 = mux(UInt<1>("h00"), T_3991, T_3981) - node T_3993 = and(T_3992, io.out.ready) - io.in[1].ready <= T_3993 - node T_3995 = eq(UInt<2>("h02"), UInt<2>("h02")) - node T_3996 = mux(UInt<1>("h00"), T_3995, T_3985) - node T_3997 = and(T_3996, io.out.ready) - io.in[2].ready <= T_3997 - node T_4000 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02")) - node T_4002 = mux(io.in[0].valid, UInt<1>("h00"), T_4000) - node T_4004 = gt(UInt<2>("h02"), T_3934) - node T_4005 = and(io.in[2].valid, T_4004) - node T_4007 = mux(T_4005, UInt<2>("h02"), T_4002) - node T_4009 = gt(UInt<1>("h01"), T_3934) - node T_4010 = and(io.in[1].valid, T_4009) - node T_4012 = mux(T_4010, UInt<1>("h01"), T_4007) - node T_4013 = mux(UInt<1>("h00"), UInt<2>("h02"), T_4012) - T_3194 <= T_4013 - node T_4014 = and(io.out.ready, io.out.valid) - when T_4014 : - T_3934 <= T_3194 + reg T_3933 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + node T_3934 = gt(UInt<1>("h00"), T_3933) + node T_3935 = and(io.in[0].valid, T_3934) + node T_3937 = gt(UInt<1>("h01"), T_3933) + node T_3938 = and(io.in[1].valid, T_3937) + node T_3940 = gt(UInt<2>("h02"), T_3933) + node T_3941 = and(io.in[2].valid, T_3940) + node T_3944 = or(UInt<1>("h00"), T_3935) + node T_3946 = eq(T_3944, UInt<1>("h00")) + node T_3948 = or(UInt<1>("h00"), T_3935) + node T_3949 = or(T_3948, T_3938) + node T_3951 = eq(T_3949, UInt<1>("h00")) + node T_3953 = or(UInt<1>("h00"), T_3935) + node T_3954 = or(T_3953, T_3938) + node T_3955 = or(T_3954, T_3941) + node T_3957 = eq(T_3955, UInt<1>("h00")) + node T_3959 = or(UInt<1>("h00"), T_3935) + node T_3960 = or(T_3959, T_3938) + node T_3961 = or(T_3960, T_3941) + node T_3962 = or(T_3961, io.in[0].valid) + node T_3964 = eq(T_3962, UInt<1>("h00")) + node T_3966 = or(UInt<1>("h00"), T_3935) + node T_3967 = or(T_3966, T_3938) + node T_3968 = or(T_3967, T_3941) + node T_3969 = or(T_3968, io.in[0].valid) + node T_3970 = or(T_3969, io.in[1].valid) + node T_3972 = eq(T_3970, UInt<1>("h00")) + node T_3974 = gt(UInt<1>("h00"), T_3933) + node T_3975 = and(UInt<1>("h01"), T_3974) + node T_3976 = or(T_3975, T_3957) + node T_3978 = gt(UInt<1>("h01"), T_3933) + node T_3979 = and(T_3946, T_3978) + node T_3980 = or(T_3979, T_3964) + node T_3982 = gt(UInt<2>("h02"), T_3933) + node T_3983 = and(T_3951, T_3982) + node T_3984 = or(T_3983, T_3972) + node T_3986 = eq(UInt<2>("h02"), UInt<1>("h00")) + node T_3987 = mux(UInt<1>("h00"), T_3986, T_3976) + node T_3988 = and(T_3987, io.out.ready) + io.in[0].ready <= T_3988 + node T_3990 = eq(UInt<2>("h02"), UInt<1>("h01")) + node T_3991 = mux(UInt<1>("h00"), T_3990, T_3980) + node T_3992 = and(T_3991, io.out.ready) + io.in[1].ready <= T_3992 + node T_3994 = eq(UInt<2>("h02"), UInt<2>("h02")) + node T_3995 = mux(UInt<1>("h00"), T_3994, T_3984) + node T_3996 = and(T_3995, io.out.ready) + io.in[2].ready <= T_3996 + node T_3999 = mux(io.in[1].valid, UInt<1>("h01"), UInt<2>("h02")) + node T_4001 = mux(io.in[0].valid, UInt<1>("h00"), T_3999) + node T_4003 = gt(UInt<2>("h02"), T_3933) + node T_4004 = and(io.in[2].valid, T_4003) + node T_4006 = mux(T_4004, UInt<2>("h02"), T_4001) + node T_4008 = gt(UInt<1>("h01"), T_3933) + node T_4009 = and(io.in[1].valid, T_4008) + node T_4011 = mux(T_4009, UInt<1>("h01"), T_4006) + node T_4012 = mux(UInt<1>("h00"), UInt<2>("h02"), T_4011) + T_3194 <= T_4012 + node T_4013 = and(io.out.ready, io.out.valid) + when T_4013 : + T_3933 <= T_3194 skip module RocketChipTileLinkArbiter : @@ -2203,624 +1607,172 @@ circuit Top : input reset : UInt<1> output io : {flip clients : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[3], flip managers : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, client_id : UInt<2>}}}[1]} - io.managers[0].release.bits.client_id <= UInt<1>("h00") - io.managers[0].release.bits.data <= UInt<1>("h00") - io.managers[0].release.bits.r_type <= UInt<1>("h00") - io.managers[0].release.bits.voluntary <= UInt<1>("h00") - io.managers[0].release.bits.client_xact_id <= UInt<1>("h00") - io.managers[0].release.bits.addr_block <= UInt<1>("h00") - io.managers[0].release.bits.addr_beat <= UInt<1>("h00") - io.managers[0].release.valid <= UInt<1>("h00") - io.managers[0].probe.ready <= UInt<1>("h00") - io.managers[0].finish.bits.manager_xact_id <= UInt<1>("h00") - io.managers[0].finish.valid <= UInt<1>("h00") - io.managers[0].grant.ready <= UInt<1>("h00") - io.managers[0].acquire.bits.client_id <= UInt<1>("h00") - io.managers[0].acquire.bits.data <= UInt<1>("h00") - io.managers[0].acquire.bits.union <= UInt<1>("h00") - io.managers[0].acquire.bits.a_type <= UInt<1>("h00") - io.managers[0].acquire.bits.is_builtin_type <= UInt<1>("h00") - io.managers[0].acquire.bits.addr_beat <= UInt<1>("h00") - io.managers[0].acquire.bits.client_xact_id <= UInt<1>("h00") - io.managers[0].acquire.bits.addr_block <= UInt<1>("h00") - io.managers[0].acquire.valid <= UInt<1>("h00") - io.clients[0].release.ready <= UInt<1>("h00") - io.clients[0].probe.bits.p_type <= UInt<1>("h00") - io.clients[0].probe.bits.addr_block <= UInt<1>("h00") - io.clients[0].probe.valid <= UInt<1>("h00") - io.clients[0].grant.bits.data <= UInt<1>("h00") - io.clients[0].grant.bits.g_type <= UInt<1>("h00") - io.clients[0].grant.bits.is_builtin_type <= UInt<1>("h00") - io.clients[0].grant.bits.manager_xact_id <= UInt<1>("h00") - io.clients[0].grant.bits.client_xact_id <= UInt<1>("h00") - io.clients[0].grant.bits.addr_beat <= UInt<1>("h00") - io.clients[0].grant.valid <= UInt<1>("h00") - io.clients[0].acquire.ready <= UInt<1>("h00") - io.clients[1].release.ready <= UInt<1>("h00") - io.clients[1].probe.bits.p_type <= UInt<1>("h00") - io.clients[1].probe.bits.addr_block <= UInt<1>("h00") - io.clients[1].probe.valid <= UInt<1>("h00") - io.clients[1].grant.bits.data <= UInt<1>("h00") - io.clients[1].grant.bits.g_type <= UInt<1>("h00") - io.clients[1].grant.bits.is_builtin_type <= UInt<1>("h00") - io.clients[1].grant.bits.manager_xact_id <= UInt<1>("h00") - io.clients[1].grant.bits.client_xact_id <= UInt<1>("h00") - io.clients[1].grant.bits.addr_beat <= UInt<1>("h00") - io.clients[1].grant.valid <= UInt<1>("h00") - io.clients[1].acquire.ready <= UInt<1>("h00") - io.clients[2].release.ready <= UInt<1>("h00") - io.clients[2].probe.bits.p_type <= UInt<1>("h00") - io.clients[2].probe.bits.addr_block <= UInt<1>("h00") - io.clients[2].probe.valid <= UInt<1>("h00") - io.clients[2].grant.bits.data <= UInt<1>("h00") - io.clients[2].grant.bits.g_type <= UInt<1>("h00") - io.clients[2].grant.bits.is_builtin_type <= UInt<1>("h00") - io.clients[2].grant.bits.manager_xact_id <= UInt<1>("h00") - io.clients[2].grant.bits.client_xact_id <= UInt<1>("h00") - io.clients[2].grant.bits.addr_beat <= UInt<1>("h00") - io.clients[2].grant.valid <= UInt<1>("h00") - io.clients[2].acquire.ready <= UInt<1>("h00") + io is invalid inst T_11386 of ClientTileLinkNetworkPort - T_11386.io.network.release.ready <= UInt<1>("h00") - T_11386.io.network.probe.bits.payload.p_type <= UInt<1>("h00") - T_11386.io.network.probe.bits.payload.addr_block <= UInt<1>("h00") - T_11386.io.network.probe.bits.header.dst <= UInt<1>("h00") - T_11386.io.network.probe.bits.header.src <= UInt<1>("h00") - T_11386.io.network.probe.valid <= UInt<1>("h00") - T_11386.io.network.finish.ready <= UInt<1>("h00") - T_11386.io.network.grant.bits.payload.data <= UInt<1>("h00") - T_11386.io.network.grant.bits.payload.g_type <= UInt<1>("h00") - T_11386.io.network.grant.bits.payload.is_builtin_type <= UInt<1>("h00") - T_11386.io.network.grant.bits.payload.manager_xact_id <= UInt<1>("h00") - T_11386.io.network.grant.bits.payload.client_xact_id <= UInt<1>("h00") - T_11386.io.network.grant.bits.payload.addr_beat <= UInt<1>("h00") - T_11386.io.network.grant.bits.header.dst <= UInt<1>("h00") - T_11386.io.network.grant.bits.header.src <= UInt<1>("h00") - T_11386.io.network.grant.valid <= UInt<1>("h00") - T_11386.io.network.acquire.ready <= UInt<1>("h00") - T_11386.io.client.release.bits.data <= UInt<1>("h00") - T_11386.io.client.release.bits.r_type <= UInt<1>("h00") - T_11386.io.client.release.bits.voluntary <= UInt<1>("h00") - T_11386.io.client.release.bits.client_xact_id <= UInt<1>("h00") - T_11386.io.client.release.bits.addr_block <= UInt<1>("h00") - T_11386.io.client.release.bits.addr_beat <= UInt<1>("h00") - T_11386.io.client.release.valid <= UInt<1>("h00") - T_11386.io.client.probe.ready <= UInt<1>("h00") - T_11386.io.client.grant.ready <= UInt<1>("h00") - T_11386.io.client.acquire.bits.data <= UInt<1>("h00") - T_11386.io.client.acquire.bits.union <= UInt<1>("h00") - T_11386.io.client.acquire.bits.a_type <= UInt<1>("h00") - T_11386.io.client.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_11386.io.client.acquire.bits.addr_beat <= UInt<1>("h00") - T_11386.io.client.acquire.bits.client_xact_id <= UInt<1>("h00") - T_11386.io.client.acquire.bits.addr_block <= UInt<1>("h00") - T_11386.io.client.acquire.valid <= UInt<1>("h00") + T_11386.io is invalid T_11386.clk <= clk T_11386.reset <= reset - inst T_11421 of TileLinkEnqueuer - T_11421.io.manager.release.ready <= UInt<1>("h00") - T_11421.io.manager.probe.bits.payload.p_type <= UInt<1>("h00") - T_11421.io.manager.probe.bits.payload.addr_block <= UInt<1>("h00") - T_11421.io.manager.probe.bits.header.dst <= UInt<1>("h00") - T_11421.io.manager.probe.bits.header.src <= UInt<1>("h00") - T_11421.io.manager.probe.valid <= UInt<1>("h00") - T_11421.io.manager.finish.ready <= UInt<1>("h00") - T_11421.io.manager.grant.bits.payload.data <= UInt<1>("h00") - T_11421.io.manager.grant.bits.payload.g_type <= UInt<1>("h00") - T_11421.io.manager.grant.bits.payload.is_builtin_type <= UInt<1>("h00") - T_11421.io.manager.grant.bits.payload.manager_xact_id <= UInt<1>("h00") - T_11421.io.manager.grant.bits.payload.client_xact_id <= UInt<1>("h00") - T_11421.io.manager.grant.bits.payload.addr_beat <= UInt<1>("h00") - T_11421.io.manager.grant.bits.header.dst <= UInt<1>("h00") - T_11421.io.manager.grant.bits.header.src <= UInt<1>("h00") - T_11421.io.manager.grant.valid <= UInt<1>("h00") - T_11421.io.manager.acquire.ready <= UInt<1>("h00") - T_11421.io.client.release.bits.payload.data <= UInt<1>("h00") - T_11421.io.client.release.bits.payload.r_type <= UInt<1>("h00") - T_11421.io.client.release.bits.payload.voluntary <= UInt<1>("h00") - T_11421.io.client.release.bits.payload.client_xact_id <= UInt<1>("h00") - T_11421.io.client.release.bits.payload.addr_block <= UInt<1>("h00") - T_11421.io.client.release.bits.payload.addr_beat <= UInt<1>("h00") - T_11421.io.client.release.bits.header.dst <= UInt<1>("h00") - T_11421.io.client.release.bits.header.src <= UInt<1>("h00") - T_11421.io.client.release.valid <= UInt<1>("h00") - T_11421.io.client.probe.ready <= UInt<1>("h00") - T_11421.io.client.finish.bits.payload.manager_xact_id <= UInt<1>("h00") - T_11421.io.client.finish.bits.header.dst <= UInt<1>("h00") - T_11421.io.client.finish.bits.header.src <= UInt<1>("h00") - T_11421.io.client.finish.valid <= UInt<1>("h00") - T_11421.io.client.grant.ready <= UInt<1>("h00") - T_11421.io.client.acquire.bits.payload.data <= UInt<1>("h00") - T_11421.io.client.acquire.bits.payload.union <= UInt<1>("h00") - T_11421.io.client.acquire.bits.payload.a_type <= UInt<1>("h00") - T_11421.io.client.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") - T_11421.io.client.acquire.bits.payload.addr_beat <= UInt<1>("h00") - T_11421.io.client.acquire.bits.payload.client_xact_id <= UInt<1>("h00") - T_11421.io.client.acquire.bits.payload.addr_block <= UInt<1>("h00") - T_11421.io.client.acquire.bits.header.dst <= UInt<1>("h00") - T_11421.io.client.acquire.bits.header.src <= UInt<1>("h00") - T_11421.io.client.acquire.valid <= UInt<1>("h00") - T_11421.clk <= clk - T_11421.reset <= reset + inst T_11387 of TileLinkEnqueuer + T_11387.io is invalid + T_11387.clk <= clk + T_11387.reset <= reset T_11386.io.client <- io.clients[0] - T_11421.io.client <- T_11386.io.network - inst T_11464 of ClientTileLinkNetworkPort_6 - T_11464.io.network.release.ready <= UInt<1>("h00") - T_11464.io.network.probe.bits.payload.p_type <= UInt<1>("h00") - T_11464.io.network.probe.bits.payload.addr_block <= UInt<1>("h00") - T_11464.io.network.probe.bits.header.dst <= UInt<1>("h00") - T_11464.io.network.probe.bits.header.src <= UInt<1>("h00") - T_11464.io.network.probe.valid <= UInt<1>("h00") - T_11464.io.network.finish.ready <= UInt<1>("h00") - T_11464.io.network.grant.bits.payload.data <= UInt<1>("h00") - T_11464.io.network.grant.bits.payload.g_type <= UInt<1>("h00") - T_11464.io.network.grant.bits.payload.is_builtin_type <= UInt<1>("h00") - T_11464.io.network.grant.bits.payload.manager_xact_id <= UInt<1>("h00") - T_11464.io.network.grant.bits.payload.client_xact_id <= UInt<1>("h00") - T_11464.io.network.grant.bits.payload.addr_beat <= UInt<1>("h00") - T_11464.io.network.grant.bits.header.dst <= UInt<1>("h00") - T_11464.io.network.grant.bits.header.src <= UInt<1>("h00") - T_11464.io.network.grant.valid <= UInt<1>("h00") - T_11464.io.network.acquire.ready <= UInt<1>("h00") - T_11464.io.client.release.bits.data <= UInt<1>("h00") - T_11464.io.client.release.bits.r_type <= UInt<1>("h00") - T_11464.io.client.release.bits.voluntary <= UInt<1>("h00") - T_11464.io.client.release.bits.client_xact_id <= UInt<1>("h00") - T_11464.io.client.release.bits.addr_block <= UInt<1>("h00") - T_11464.io.client.release.bits.addr_beat <= UInt<1>("h00") - T_11464.io.client.release.valid <= UInt<1>("h00") - T_11464.io.client.probe.ready <= UInt<1>("h00") - T_11464.io.client.grant.ready <= UInt<1>("h00") - T_11464.io.client.acquire.bits.data <= UInt<1>("h00") - T_11464.io.client.acquire.bits.union <= UInt<1>("h00") - T_11464.io.client.acquire.bits.a_type <= UInt<1>("h00") - T_11464.io.client.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_11464.io.client.acquire.bits.addr_beat <= UInt<1>("h00") - T_11464.io.client.acquire.bits.client_xact_id <= UInt<1>("h00") - T_11464.io.client.acquire.bits.addr_block <= UInt<1>("h00") - T_11464.io.client.acquire.valid <= UInt<1>("h00") - T_11464.clk <= clk - T_11464.reset <= reset - inst T_11499 of TileLinkEnqueuer - T_11499.io.manager.release.ready <= UInt<1>("h00") - T_11499.io.manager.probe.bits.payload.p_type <= UInt<1>("h00") - T_11499.io.manager.probe.bits.payload.addr_block <= UInt<1>("h00") - T_11499.io.manager.probe.bits.header.dst <= UInt<1>("h00") - T_11499.io.manager.probe.bits.header.src <= UInt<1>("h00") - T_11499.io.manager.probe.valid <= UInt<1>("h00") - T_11499.io.manager.finish.ready <= UInt<1>("h00") - T_11499.io.manager.grant.bits.payload.data <= UInt<1>("h00") - T_11499.io.manager.grant.bits.payload.g_type <= UInt<1>("h00") - T_11499.io.manager.grant.bits.payload.is_builtin_type <= UInt<1>("h00") - T_11499.io.manager.grant.bits.payload.manager_xact_id <= UInt<1>("h00") - T_11499.io.manager.grant.bits.payload.client_xact_id <= UInt<1>("h00") - T_11499.io.manager.grant.bits.payload.addr_beat <= UInt<1>("h00") - T_11499.io.manager.grant.bits.header.dst <= UInt<1>("h00") - T_11499.io.manager.grant.bits.header.src <= UInt<1>("h00") - T_11499.io.manager.grant.valid <= UInt<1>("h00") - T_11499.io.manager.acquire.ready <= UInt<1>("h00") - T_11499.io.client.release.bits.payload.data <= UInt<1>("h00") - T_11499.io.client.release.bits.payload.r_type <= UInt<1>("h00") - T_11499.io.client.release.bits.payload.voluntary <= UInt<1>("h00") - T_11499.io.client.release.bits.payload.client_xact_id <= UInt<1>("h00") - T_11499.io.client.release.bits.payload.addr_block <= UInt<1>("h00") - T_11499.io.client.release.bits.payload.addr_beat <= UInt<1>("h00") - T_11499.io.client.release.bits.header.dst <= UInt<1>("h00") - T_11499.io.client.release.bits.header.src <= UInt<1>("h00") - T_11499.io.client.release.valid <= UInt<1>("h00") - T_11499.io.client.probe.ready <= UInt<1>("h00") - T_11499.io.client.finish.bits.payload.manager_xact_id <= UInt<1>("h00") - T_11499.io.client.finish.bits.header.dst <= UInt<1>("h00") - T_11499.io.client.finish.bits.header.src <= UInt<1>("h00") - T_11499.io.client.finish.valid <= UInt<1>("h00") - T_11499.io.client.grant.ready <= UInt<1>("h00") - T_11499.io.client.acquire.bits.payload.data <= UInt<1>("h00") - T_11499.io.client.acquire.bits.payload.union <= UInt<1>("h00") - T_11499.io.client.acquire.bits.payload.a_type <= UInt<1>("h00") - T_11499.io.client.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") - T_11499.io.client.acquire.bits.payload.addr_beat <= UInt<1>("h00") - T_11499.io.client.acquire.bits.payload.client_xact_id <= UInt<1>("h00") - T_11499.io.client.acquire.bits.payload.addr_block <= UInt<1>("h00") - T_11499.io.client.acquire.bits.header.dst <= UInt<1>("h00") - T_11499.io.client.acquire.bits.header.src <= UInt<1>("h00") - T_11499.io.client.acquire.valid <= UInt<1>("h00") - T_11499.clk <= clk - T_11499.reset <= reset - T_11464.io.client <- io.clients[1] - T_11499.io.client <- T_11464.io.network - inst T_11542 of ClientTileLinkNetworkPort_15 - T_11542.io.network.release.ready <= UInt<1>("h00") - T_11542.io.network.probe.bits.payload.p_type <= UInt<1>("h00") - T_11542.io.network.probe.bits.payload.addr_block <= UInt<1>("h00") - T_11542.io.network.probe.bits.header.dst <= UInt<1>("h00") - T_11542.io.network.probe.bits.header.src <= UInt<1>("h00") - T_11542.io.network.probe.valid <= UInt<1>("h00") - T_11542.io.network.finish.ready <= UInt<1>("h00") - T_11542.io.network.grant.bits.payload.data <= UInt<1>("h00") - T_11542.io.network.grant.bits.payload.g_type <= UInt<1>("h00") - T_11542.io.network.grant.bits.payload.is_builtin_type <= UInt<1>("h00") - T_11542.io.network.grant.bits.payload.manager_xact_id <= UInt<1>("h00") - T_11542.io.network.grant.bits.payload.client_xact_id <= UInt<1>("h00") - T_11542.io.network.grant.bits.payload.addr_beat <= UInt<1>("h00") - T_11542.io.network.grant.bits.header.dst <= UInt<1>("h00") - T_11542.io.network.grant.bits.header.src <= UInt<1>("h00") - T_11542.io.network.grant.valid <= UInt<1>("h00") - T_11542.io.network.acquire.ready <= UInt<1>("h00") - T_11542.io.client.release.bits.data <= UInt<1>("h00") - T_11542.io.client.release.bits.r_type <= UInt<1>("h00") - T_11542.io.client.release.bits.voluntary <= UInt<1>("h00") - T_11542.io.client.release.bits.client_xact_id <= UInt<1>("h00") - T_11542.io.client.release.bits.addr_block <= UInt<1>("h00") - T_11542.io.client.release.bits.addr_beat <= UInt<1>("h00") - T_11542.io.client.release.valid <= UInt<1>("h00") - T_11542.io.client.probe.ready <= UInt<1>("h00") - T_11542.io.client.grant.ready <= UInt<1>("h00") - T_11542.io.client.acquire.bits.data <= UInt<1>("h00") - T_11542.io.client.acquire.bits.union <= UInt<1>("h00") - T_11542.io.client.acquire.bits.a_type <= UInt<1>("h00") - T_11542.io.client.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_11542.io.client.acquire.bits.addr_beat <= UInt<1>("h00") - T_11542.io.client.acquire.bits.client_xact_id <= UInt<1>("h00") - T_11542.io.client.acquire.bits.addr_block <= UInt<1>("h00") - T_11542.io.client.acquire.valid <= UInt<1>("h00") - T_11542.clk <= clk - T_11542.reset <= reset - inst T_11577 of TileLinkEnqueuer - T_11577.io.manager.release.ready <= UInt<1>("h00") - T_11577.io.manager.probe.bits.payload.p_type <= UInt<1>("h00") - T_11577.io.manager.probe.bits.payload.addr_block <= UInt<1>("h00") - T_11577.io.manager.probe.bits.header.dst <= UInt<1>("h00") - T_11577.io.manager.probe.bits.header.src <= UInt<1>("h00") - T_11577.io.manager.probe.valid <= UInt<1>("h00") - T_11577.io.manager.finish.ready <= UInt<1>("h00") - T_11577.io.manager.grant.bits.payload.data <= UInt<1>("h00") - T_11577.io.manager.grant.bits.payload.g_type <= UInt<1>("h00") - T_11577.io.manager.grant.bits.payload.is_builtin_type <= UInt<1>("h00") - T_11577.io.manager.grant.bits.payload.manager_xact_id <= UInt<1>("h00") - T_11577.io.manager.grant.bits.payload.client_xact_id <= UInt<1>("h00") - T_11577.io.manager.grant.bits.payload.addr_beat <= UInt<1>("h00") - T_11577.io.manager.grant.bits.header.dst <= UInt<1>("h00") - T_11577.io.manager.grant.bits.header.src <= UInt<1>("h00") - T_11577.io.manager.grant.valid <= UInt<1>("h00") - T_11577.io.manager.acquire.ready <= UInt<1>("h00") - T_11577.io.client.release.bits.payload.data <= UInt<1>("h00") - T_11577.io.client.release.bits.payload.r_type <= UInt<1>("h00") - T_11577.io.client.release.bits.payload.voluntary <= UInt<1>("h00") - T_11577.io.client.release.bits.payload.client_xact_id <= UInt<1>("h00") - T_11577.io.client.release.bits.payload.addr_block <= UInt<1>("h00") - T_11577.io.client.release.bits.payload.addr_beat <= UInt<1>("h00") - T_11577.io.client.release.bits.header.dst <= UInt<1>("h00") - T_11577.io.client.release.bits.header.src <= UInt<1>("h00") - T_11577.io.client.release.valid <= UInt<1>("h00") - T_11577.io.client.probe.ready <= UInt<1>("h00") - T_11577.io.client.finish.bits.payload.manager_xact_id <= UInt<1>("h00") - T_11577.io.client.finish.bits.header.dst <= UInt<1>("h00") - T_11577.io.client.finish.bits.header.src <= UInt<1>("h00") - T_11577.io.client.finish.valid <= UInt<1>("h00") - T_11577.io.client.grant.ready <= UInt<1>("h00") - T_11577.io.client.acquire.bits.payload.data <= UInt<1>("h00") - T_11577.io.client.acquire.bits.payload.union <= UInt<1>("h00") - T_11577.io.client.acquire.bits.payload.a_type <= UInt<1>("h00") - T_11577.io.client.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") - T_11577.io.client.acquire.bits.payload.addr_beat <= UInt<1>("h00") - T_11577.io.client.acquire.bits.payload.client_xact_id <= UInt<1>("h00") - T_11577.io.client.acquire.bits.payload.addr_block <= UInt<1>("h00") - T_11577.io.client.acquire.bits.header.dst <= UInt<1>("h00") - T_11577.io.client.acquire.bits.header.src <= UInt<1>("h00") - T_11577.io.client.acquire.valid <= UInt<1>("h00") - T_11577.clk <= clk - T_11577.reset <= reset - T_11542.io.client <- io.clients[2] - T_11577.io.client <- T_11542.io.network - inst T_11620 of ManagerTileLinkNetworkPort - T_11620.io.network.release.bits.payload.data <= UInt<1>("h00") - T_11620.io.network.release.bits.payload.r_type <= UInt<1>("h00") - T_11620.io.network.release.bits.payload.voluntary <= UInt<1>("h00") - T_11620.io.network.release.bits.payload.client_xact_id <= UInt<1>("h00") - T_11620.io.network.release.bits.payload.addr_block <= UInt<1>("h00") - T_11620.io.network.release.bits.payload.addr_beat <= UInt<1>("h00") - T_11620.io.network.release.bits.header.dst <= UInt<1>("h00") - T_11620.io.network.release.bits.header.src <= UInt<1>("h00") - T_11620.io.network.release.valid <= UInt<1>("h00") - T_11620.io.network.probe.ready <= UInt<1>("h00") - T_11620.io.network.finish.bits.payload.manager_xact_id <= UInt<1>("h00") - T_11620.io.network.finish.bits.header.dst <= UInt<1>("h00") - T_11620.io.network.finish.bits.header.src <= UInt<1>("h00") - T_11620.io.network.finish.valid <= UInt<1>("h00") - T_11620.io.network.grant.ready <= UInt<1>("h00") - T_11620.io.network.acquire.bits.payload.data <= UInt<1>("h00") - T_11620.io.network.acquire.bits.payload.union <= UInt<1>("h00") - T_11620.io.network.acquire.bits.payload.a_type <= UInt<1>("h00") - T_11620.io.network.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") - T_11620.io.network.acquire.bits.payload.addr_beat <= UInt<1>("h00") - T_11620.io.network.acquire.bits.payload.client_xact_id <= UInt<1>("h00") - T_11620.io.network.acquire.bits.payload.addr_block <= UInt<1>("h00") - T_11620.io.network.acquire.bits.header.dst <= UInt<1>("h00") - T_11620.io.network.acquire.bits.header.src <= UInt<1>("h00") - T_11620.io.network.acquire.valid <= UInt<1>("h00") - T_11620.io.manager.release.ready <= UInt<1>("h00") - T_11620.io.manager.probe.bits.client_id <= UInt<1>("h00") - T_11620.io.manager.probe.bits.p_type <= UInt<1>("h00") - T_11620.io.manager.probe.bits.addr_block <= UInt<1>("h00") - T_11620.io.manager.probe.valid <= UInt<1>("h00") - T_11620.io.manager.finish.ready <= UInt<1>("h00") - T_11620.io.manager.grant.bits.client_id <= UInt<1>("h00") - T_11620.io.manager.grant.bits.data <= UInt<1>("h00") - T_11620.io.manager.grant.bits.g_type <= UInt<1>("h00") - T_11620.io.manager.grant.bits.is_builtin_type <= UInt<1>("h00") - T_11620.io.manager.grant.bits.manager_xact_id <= UInt<1>("h00") - T_11620.io.manager.grant.bits.client_xact_id <= UInt<1>("h00") - T_11620.io.manager.grant.bits.addr_beat <= UInt<1>("h00") - T_11620.io.manager.grant.valid <= UInt<1>("h00") - T_11620.io.manager.acquire.ready <= UInt<1>("h00") - T_11620.clk <= clk - T_11620.reset <= reset - inst T_11661 of TileLinkEnqueuer_24 - T_11661.io.manager.release.ready <= UInt<1>("h00") - T_11661.io.manager.probe.bits.payload.p_type <= UInt<1>("h00") - T_11661.io.manager.probe.bits.payload.addr_block <= UInt<1>("h00") - T_11661.io.manager.probe.bits.header.dst <= UInt<1>("h00") - T_11661.io.manager.probe.bits.header.src <= UInt<1>("h00") - T_11661.io.manager.probe.valid <= UInt<1>("h00") - T_11661.io.manager.finish.ready <= UInt<1>("h00") - T_11661.io.manager.grant.bits.payload.data <= UInt<1>("h00") - T_11661.io.manager.grant.bits.payload.g_type <= UInt<1>("h00") - T_11661.io.manager.grant.bits.payload.is_builtin_type <= UInt<1>("h00") - T_11661.io.manager.grant.bits.payload.manager_xact_id <= UInt<1>("h00") - T_11661.io.manager.grant.bits.payload.client_xact_id <= UInt<1>("h00") - T_11661.io.manager.grant.bits.payload.addr_beat <= UInt<1>("h00") - T_11661.io.manager.grant.bits.header.dst <= UInt<1>("h00") - T_11661.io.manager.grant.bits.header.src <= UInt<1>("h00") - T_11661.io.manager.grant.valid <= UInt<1>("h00") - T_11661.io.manager.acquire.ready <= UInt<1>("h00") - T_11661.io.client.release.bits.payload.data <= UInt<1>("h00") - T_11661.io.client.release.bits.payload.r_type <= UInt<1>("h00") - T_11661.io.client.release.bits.payload.voluntary <= UInt<1>("h00") - T_11661.io.client.release.bits.payload.client_xact_id <= UInt<1>("h00") - T_11661.io.client.release.bits.payload.addr_block <= UInt<1>("h00") - T_11661.io.client.release.bits.payload.addr_beat <= UInt<1>("h00") - T_11661.io.client.release.bits.header.dst <= UInt<1>("h00") - T_11661.io.client.release.bits.header.src <= UInt<1>("h00") - T_11661.io.client.release.valid <= UInt<1>("h00") - T_11661.io.client.probe.ready <= UInt<1>("h00") - T_11661.io.client.finish.bits.payload.manager_xact_id <= UInt<1>("h00") - T_11661.io.client.finish.bits.header.dst <= UInt<1>("h00") - T_11661.io.client.finish.bits.header.src <= UInt<1>("h00") - T_11661.io.client.finish.valid <= UInt<1>("h00") - T_11661.io.client.grant.ready <= UInt<1>("h00") - T_11661.io.client.acquire.bits.payload.data <= UInt<1>("h00") - T_11661.io.client.acquire.bits.payload.union <= UInt<1>("h00") - T_11661.io.client.acquire.bits.payload.a_type <= UInt<1>("h00") - T_11661.io.client.acquire.bits.payload.is_builtin_type <= UInt<1>("h00") - T_11661.io.client.acquire.bits.payload.addr_beat <= UInt<1>("h00") - T_11661.io.client.acquire.bits.payload.client_xact_id <= UInt<1>("h00") - T_11661.io.client.acquire.bits.payload.addr_block <= UInt<1>("h00") - T_11661.io.client.acquire.bits.header.dst <= UInt<1>("h00") - T_11661.io.client.acquire.bits.header.src <= UInt<1>("h00") - T_11661.io.client.acquire.valid <= UInt<1>("h00") - T_11661.clk <= clk - T_11661.reset <= reset - T_11620.io.manager <- io.managers[0] - T_11620.io.network <- T_11661.io.manager - inst T_11704 of LockingRRArbiter - T_11704.io.out.ready <= UInt<1>("h00") - T_11704.io.in[0].bits.payload.data <= UInt<1>("h00") - T_11704.io.in[0].bits.payload.union <= UInt<1>("h00") - T_11704.io.in[0].bits.payload.a_type <= UInt<1>("h00") - T_11704.io.in[0].bits.payload.is_builtin_type <= UInt<1>("h00") - T_11704.io.in[0].bits.payload.addr_beat <= UInt<1>("h00") - T_11704.io.in[0].bits.payload.client_xact_id <= UInt<1>("h00") - T_11704.io.in[0].bits.payload.addr_block <= UInt<1>("h00") - T_11704.io.in[0].bits.header.dst <= UInt<1>("h00") - T_11704.io.in[0].bits.header.src <= UInt<1>("h00") - T_11704.io.in[0].valid <= UInt<1>("h00") - T_11704.io.in[1].bits.payload.data <= UInt<1>("h00") - T_11704.io.in[1].bits.payload.union <= UInt<1>("h00") - T_11704.io.in[1].bits.payload.a_type <= UInt<1>("h00") - T_11704.io.in[1].bits.payload.is_builtin_type <= UInt<1>("h00") - T_11704.io.in[1].bits.payload.addr_beat <= UInt<1>("h00") - T_11704.io.in[1].bits.payload.client_xact_id <= UInt<1>("h00") - T_11704.io.in[1].bits.payload.addr_block <= UInt<1>("h00") - T_11704.io.in[1].bits.header.dst <= UInt<1>("h00") - T_11704.io.in[1].bits.header.src <= UInt<1>("h00") - T_11704.io.in[1].valid <= UInt<1>("h00") - T_11704.io.in[2].bits.payload.data <= UInt<1>("h00") - T_11704.io.in[2].bits.payload.union <= UInt<1>("h00") - T_11704.io.in[2].bits.payload.a_type <= UInt<1>("h00") - T_11704.io.in[2].bits.payload.is_builtin_type <= UInt<1>("h00") - T_11704.io.in[2].bits.payload.addr_beat <= UInt<1>("h00") - T_11704.io.in[2].bits.payload.client_xact_id <= UInt<1>("h00") - T_11704.io.in[2].bits.payload.addr_block <= UInt<1>("h00") - T_11704.io.in[2].bits.header.dst <= UInt<1>("h00") - T_11704.io.in[2].bits.header.src <= UInt<1>("h00") - T_11704.io.in[2].valid <= UInt<1>("h00") - T_11704.clk <= clk - T_11704.reset <= reset - T_11704.io.in[0].valid <= T_11421.io.manager.acquire.valid - T_11704.io.in[0].bits <- T_11421.io.manager.acquire.bits - T_11704.io.in[0].bits.payload.client_xact_id <= T_11421.io.manager.acquire.bits.payload.client_xact_id - T_11421.io.manager.acquire.ready <= T_11704.io.in[0].ready - T_11704.io.in[1].valid <= T_11499.io.manager.acquire.valid - T_11704.io.in[1].bits <- T_11499.io.manager.acquire.bits - T_11704.io.in[1].bits.payload.client_xact_id <= T_11499.io.manager.acquire.bits.payload.client_xact_id - T_11499.io.manager.acquire.ready <= T_11704.io.in[1].ready - T_11704.io.in[2].valid <= T_11577.io.manager.acquire.valid - T_11704.io.in[2].bits <- T_11577.io.manager.acquire.bits - T_11704.io.in[2].bits.payload.client_xact_id <= T_11577.io.manager.acquire.bits.payload.client_xact_id - T_11577.io.manager.acquire.ready <= T_11704.io.in[2].ready - T_11661.io.client.acquire <- T_11704.io.out - inst T_11736 of LockingRRArbiter_26 - T_11736.io.out.ready <= UInt<1>("h00") - T_11736.io.in[0].bits.payload.data <= UInt<1>("h00") - T_11736.io.in[0].bits.payload.r_type <= UInt<1>("h00") - T_11736.io.in[0].bits.payload.voluntary <= UInt<1>("h00") - T_11736.io.in[0].bits.payload.client_xact_id <= UInt<1>("h00") - T_11736.io.in[0].bits.payload.addr_block <= UInt<1>("h00") - T_11736.io.in[0].bits.payload.addr_beat <= UInt<1>("h00") - T_11736.io.in[0].bits.header.dst <= UInt<1>("h00") - T_11736.io.in[0].bits.header.src <= UInt<1>("h00") - T_11736.io.in[0].valid <= UInt<1>("h00") - T_11736.io.in[1].bits.payload.data <= UInt<1>("h00") - T_11736.io.in[1].bits.payload.r_type <= UInt<1>("h00") - T_11736.io.in[1].bits.payload.voluntary <= UInt<1>("h00") - T_11736.io.in[1].bits.payload.client_xact_id <= UInt<1>("h00") - T_11736.io.in[1].bits.payload.addr_block <= UInt<1>("h00") - T_11736.io.in[1].bits.payload.addr_beat <= UInt<1>("h00") - T_11736.io.in[1].bits.header.dst <= UInt<1>("h00") - T_11736.io.in[1].bits.header.src <= UInt<1>("h00") - T_11736.io.in[1].valid <= UInt<1>("h00") - T_11736.io.in[2].bits.payload.data <= UInt<1>("h00") - T_11736.io.in[2].bits.payload.r_type <= UInt<1>("h00") - T_11736.io.in[2].bits.payload.voluntary <= UInt<1>("h00") - T_11736.io.in[2].bits.payload.client_xact_id <= UInt<1>("h00") - T_11736.io.in[2].bits.payload.addr_block <= UInt<1>("h00") - T_11736.io.in[2].bits.payload.addr_beat <= UInt<1>("h00") - T_11736.io.in[2].bits.header.dst <= UInt<1>("h00") - T_11736.io.in[2].bits.header.src <= UInt<1>("h00") - T_11736.io.in[2].valid <= UInt<1>("h00") - T_11736.clk <= clk - T_11736.reset <= reset - T_11736.io.in[0].valid <= T_11421.io.manager.release.valid - T_11736.io.in[0].bits <- T_11421.io.manager.release.bits - T_11736.io.in[0].bits.payload.client_xact_id <= T_11421.io.manager.release.bits.payload.client_xact_id - T_11421.io.manager.release.ready <= T_11736.io.in[0].ready - T_11736.io.in[1].valid <= T_11499.io.manager.release.valid - T_11736.io.in[1].bits <- T_11499.io.manager.release.bits - T_11736.io.in[1].bits.payload.client_xact_id <= T_11499.io.manager.release.bits.payload.client_xact_id - T_11499.io.manager.release.ready <= T_11736.io.in[1].ready - T_11736.io.in[2].valid <= T_11577.io.manager.release.valid - T_11736.io.in[2].bits <- T_11577.io.manager.release.bits - T_11736.io.in[2].bits.payload.client_xact_id <= T_11577.io.manager.release.bits.payload.client_xact_id - T_11577.io.manager.release.ready <= T_11736.io.in[2].ready - T_11661.io.client.release <- T_11736.io.out - inst T_11765 of RRArbiter - T_11765.io.out.ready <= UInt<1>("h00") - T_11765.io.in[0].bits.payload.manager_xact_id <= UInt<1>("h00") - T_11765.io.in[0].bits.header.dst <= UInt<1>("h00") - T_11765.io.in[0].bits.header.src <= UInt<1>("h00") - T_11765.io.in[0].valid <= UInt<1>("h00") - T_11765.io.in[1].bits.payload.manager_xact_id <= UInt<1>("h00") - T_11765.io.in[1].bits.header.dst <= UInt<1>("h00") - T_11765.io.in[1].bits.header.src <= UInt<1>("h00") - T_11765.io.in[1].valid <= UInt<1>("h00") - T_11765.io.in[2].bits.payload.manager_xact_id <= UInt<1>("h00") - T_11765.io.in[2].bits.header.dst <= UInt<1>("h00") - T_11765.io.in[2].bits.header.src <= UInt<1>("h00") - T_11765.io.in[2].valid <= UInt<1>("h00") - T_11765.clk <= clk - T_11765.reset <= reset - T_11765.io.in[0] <- T_11421.io.manager.finish - T_11765.io.in[1] <- T_11499.io.manager.finish - T_11765.io.in[2] <- T_11577.io.manager.finish - T_11661.io.client.finish <- T_11765.io.out - T_11661.io.client.probe.ready <= UInt<1>("h00") - T_11421.io.manager.probe.valid <= UInt<1>("h00") - node T_11782 = eq(T_11661.io.client.probe.bits.header.dst, UInt<1>("h00")) - when T_11782 : - T_11421.io.manager.probe.valid <= T_11661.io.client.probe.valid - T_11661.io.client.probe.ready <= T_11421.io.manager.probe.ready - skip - T_11421.io.manager.probe.bits <- T_11661.io.client.probe.bits - T_11499.io.manager.probe.valid <= UInt<1>("h00") - node T_11785 = eq(T_11661.io.client.probe.bits.header.dst, UInt<1>("h01")) - when T_11785 : - T_11499.io.manager.probe.valid <= T_11661.io.client.probe.valid - T_11661.io.client.probe.ready <= T_11499.io.manager.probe.ready - skip - T_11499.io.manager.probe.bits <- T_11661.io.client.probe.bits - T_11577.io.manager.probe.valid <= UInt<1>("h00") - node T_11788 = eq(T_11661.io.client.probe.bits.header.dst, UInt<2>("h02")) - when T_11788 : - T_11577.io.manager.probe.valid <= T_11661.io.client.probe.valid - T_11661.io.client.probe.ready <= T_11577.io.manager.probe.ready - skip - T_11577.io.manager.probe.bits <- T_11661.io.client.probe.bits - T_11661.io.client.grant.ready <= UInt<1>("h00") - T_11421.io.manager.grant.valid <= UInt<1>("h00") - node T_11792 = eq(T_11661.io.client.grant.bits.header.dst, UInt<1>("h00")) - when T_11792 : - T_11421.io.manager.grant.valid <= T_11661.io.client.grant.valid - T_11661.io.client.grant.ready <= T_11421.io.manager.grant.ready - skip - T_11421.io.manager.grant.bits <- T_11661.io.client.grant.bits - T_11499.io.manager.grant.valid <= UInt<1>("h00") - node T_11795 = eq(T_11661.io.client.grant.bits.header.dst, UInt<1>("h01")) - when T_11795 : - T_11499.io.manager.grant.valid <= T_11661.io.client.grant.valid - T_11661.io.client.grant.ready <= T_11499.io.manager.grant.ready - skip - T_11499.io.manager.grant.bits <- T_11661.io.client.grant.bits - T_11577.io.manager.grant.valid <= UInt<1>("h00") - node T_11798 = eq(T_11661.io.client.grant.bits.header.dst, UInt<2>("h02")) - when T_11798 : - T_11577.io.manager.grant.valid <= T_11661.io.client.grant.valid - T_11661.io.client.grant.ready <= T_11577.io.manager.grant.ready - skip - T_11577.io.manager.grant.bits <- T_11661.io.client.grant.bits + T_11387.io.client <- T_11386.io.network + inst T_11388 of ClientTileLinkNetworkPort_6 + T_11388.io is invalid + T_11388.clk <= clk + T_11388.reset <= reset + inst T_11389 of TileLinkEnqueuer + T_11389.io is invalid + T_11389.clk <= clk + T_11389.reset <= reset + T_11388.io.client <- io.clients[1] + T_11389.io.client <- T_11388.io.network + inst T_11390 of ClientTileLinkNetworkPort_15 + T_11390.io is invalid + T_11390.clk <= clk + T_11390.reset <= reset + inst T_11391 of TileLinkEnqueuer + T_11391.io is invalid + T_11391.clk <= clk + T_11391.reset <= reset + T_11390.io.client <- io.clients[2] + T_11391.io.client <- T_11390.io.network + inst T_11392 of ManagerTileLinkNetworkPort + T_11392.io is invalid + T_11392.clk <= clk + T_11392.reset <= reset + inst T_11393 of TileLinkEnqueuer_24 + T_11393.io is invalid + T_11393.clk <= clk + T_11393.reset <= reset + T_11392.io.manager <- io.managers[0] + T_11392.io.network <- T_11393.io.manager + inst T_11394 of LockingRRArbiter + T_11394.io is invalid + T_11394.clk <= clk + T_11394.reset <= reset + T_11394.io.in[0].valid <= T_11387.io.manager.acquire.valid + T_11394.io.in[0].bits <- T_11387.io.manager.acquire.bits + T_11394.io.in[0].bits.payload.client_xact_id <= T_11387.io.manager.acquire.bits.payload.client_xact_id + T_11387.io.manager.acquire.ready <= T_11394.io.in[0].ready + T_11394.io.in[1].valid <= T_11389.io.manager.acquire.valid + T_11394.io.in[1].bits <- T_11389.io.manager.acquire.bits + T_11394.io.in[1].bits.payload.client_xact_id <= T_11389.io.manager.acquire.bits.payload.client_xact_id + T_11389.io.manager.acquire.ready <= T_11394.io.in[1].ready + T_11394.io.in[2].valid <= T_11391.io.manager.acquire.valid + T_11394.io.in[2].bits <- T_11391.io.manager.acquire.bits + T_11394.io.in[2].bits.payload.client_xact_id <= T_11391.io.manager.acquire.bits.payload.client_xact_id + T_11391.io.manager.acquire.ready <= T_11394.io.in[2].ready + T_11393.io.client.acquire <- T_11394.io.out + inst T_11395 of LockingRRArbiter_26 + T_11395.io is invalid + T_11395.clk <= clk + T_11395.reset <= reset + T_11395.io.in[0].valid <= T_11387.io.manager.release.valid + T_11395.io.in[0].bits <- T_11387.io.manager.release.bits + T_11395.io.in[0].bits.payload.client_xact_id <= T_11387.io.manager.release.bits.payload.client_xact_id + T_11387.io.manager.release.ready <= T_11395.io.in[0].ready + T_11395.io.in[1].valid <= T_11389.io.manager.release.valid + T_11395.io.in[1].bits <- T_11389.io.manager.release.bits + T_11395.io.in[1].bits.payload.client_xact_id <= T_11389.io.manager.release.bits.payload.client_xact_id + T_11389.io.manager.release.ready <= T_11395.io.in[1].ready + T_11395.io.in[2].valid <= T_11391.io.manager.release.valid + T_11395.io.in[2].bits <- T_11391.io.manager.release.bits + T_11395.io.in[2].bits.payload.client_xact_id <= T_11391.io.manager.release.bits.payload.client_xact_id + T_11391.io.manager.release.ready <= T_11395.io.in[2].ready + T_11393.io.client.release <- T_11395.io.out + inst T_11396 of RRArbiter + T_11396.io is invalid + T_11396.clk <= clk + T_11396.reset <= reset + T_11396.io.in[0] <- T_11387.io.manager.finish + T_11396.io.in[1] <- T_11389.io.manager.finish + T_11396.io.in[2] <- T_11391.io.manager.finish + T_11393.io.client.finish <- T_11396.io.out + T_11393.io.client.probe.ready <= UInt<1>("h00") + T_11387.io.manager.probe.valid <= UInt<1>("h00") + node T_11400 = eq(T_11393.io.client.probe.bits.header.dst, UInt<1>("h00")) + when T_11400 : + T_11387.io.manager.probe.valid <= T_11393.io.client.probe.valid + T_11393.io.client.probe.ready <= T_11387.io.manager.probe.ready + skip + T_11387.io.manager.probe.bits <- T_11393.io.client.probe.bits + T_11389.io.manager.probe.valid <= UInt<1>("h00") + node T_11403 = eq(T_11393.io.client.probe.bits.header.dst, UInt<1>("h01")) + when T_11403 : + T_11389.io.manager.probe.valid <= T_11393.io.client.probe.valid + T_11393.io.client.probe.ready <= T_11389.io.manager.probe.ready + skip + T_11389.io.manager.probe.bits <- T_11393.io.client.probe.bits + T_11391.io.manager.probe.valid <= UInt<1>("h00") + node T_11406 = eq(T_11393.io.client.probe.bits.header.dst, UInt<2>("h02")) + when T_11406 : + T_11391.io.manager.probe.valid <= T_11393.io.client.probe.valid + T_11393.io.client.probe.ready <= T_11391.io.manager.probe.ready + skip + T_11391.io.manager.probe.bits <- T_11393.io.client.probe.bits + T_11393.io.client.grant.ready <= UInt<1>("h00") + T_11387.io.manager.grant.valid <= UInt<1>("h00") + node T_11410 = eq(T_11393.io.client.grant.bits.header.dst, UInt<1>("h00")) + when T_11410 : + T_11387.io.manager.grant.valid <= T_11393.io.client.grant.valid + T_11393.io.client.grant.ready <= T_11387.io.manager.grant.ready + skip + T_11387.io.manager.grant.bits <- T_11393.io.client.grant.bits + T_11389.io.manager.grant.valid <= UInt<1>("h00") + node T_11413 = eq(T_11393.io.client.grant.bits.header.dst, UInt<1>("h01")) + when T_11413 : + T_11389.io.manager.grant.valid <= T_11393.io.client.grant.valid + T_11393.io.client.grant.ready <= T_11389.io.manager.grant.ready + skip + T_11389.io.manager.grant.bits <- T_11393.io.client.grant.bits + T_11391.io.manager.grant.valid <= UInt<1>("h00") + node T_11416 = eq(T_11393.io.client.grant.bits.header.dst, UInt<2>("h02")) + when T_11416 : + T_11391.io.manager.grant.valid <= T_11393.io.client.grant.valid + T_11393.io.client.grant.ready <= T_11391.io.manager.grant.ready + skip + T_11391.io.manager.grant.bits <- T_11393.io.client.grant.bits module BroadcastVoluntaryReleaseTracker : input clk : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - io.has_release_match <= UInt<1>("h00") - io.has_acquire_match <= UInt<1>("h00") - io.has_acquire_conflict <= UInt<1>("h00") - io.outer.grant.ready <= UInt<1>("h00") - io.outer.acquire.bits.data <= UInt<1>("h00") - io.outer.acquire.bits.union <= UInt<1>("h00") - io.outer.acquire.bits.a_type <= UInt<1>("h00") - io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.outer.acquire.bits.addr_beat <= UInt<1>("h00") - io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") - io.outer.acquire.bits.addr_block <= UInt<1>("h00") - io.outer.acquire.valid <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.probe.bits.client_id <= UInt<1>("h00") - io.inner.probe.bits.p_type <= UInt<1>("h00") - io.inner.probe.bits.addr_block <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - io.inner.grant.bits.client_id <= UInt<1>("h00") - io.inner.grant.bits.data <= UInt<1>("h00") - io.inner.grant.bits.g_type <= UInt<1>("h00") - io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") - io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") - io.inner.grant.bits.client_xact_id <= UInt<1>("h00") - io.inner.grant.bits.addr_beat <= UInt<1>("h00") - io.inner.grant.valid <= UInt<1>("h00") - io.inner.acquire.ready <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") - reg xact : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk, UInt<1>("h00"), xact + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + reg xact : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk wire coh : {sharers : UInt<1>} + coh is invalid coh.sharers <= UInt<1>("h00") - coh.sharers <= UInt<1>("h00") - reg collect_irel_data : UInt<1>, clk, reset, UInt<1>("h00") - reg irel_data_valid : UInt<4>, clk, reset, UInt<4>("h00") - node T_303 = and(io.inner.release.ready, io.inner.release.valid) - wire T_307 : UInt<2>[3] - T_307[0] <= UInt<1>("h00") - T_307[1] <= UInt<1>("h01") - T_307[2] <= UInt<2>("h02") - node T_312 = eq(T_307[0], io.inner.release.bits.r_type) - node T_313 = eq(T_307[1], io.inner.release.bits.r_type) - node T_314 = eq(T_307[2], io.inner.release.bits.r_type) - node T_316 = or(UInt<1>("h00"), T_312) + reg collect_irel_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg irel_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) + node T_302 = and(io.inner.release.ready, io.inner.release.valid) + wire T_306 : UInt<2>[3] + T_306[0] <= UInt<1>("h00") + T_306[1] <= UInt<1>("h01") + T_306[2] <= UInt<2>("h02") + node T_311 = eq(T_306[0], io.inner.release.bits.r_type) + node T_312 = eq(T_306[1], io.inner.release.bits.r_type) + node T_313 = eq(T_306[2], io.inner.release.bits.r_type) + node T_315 = or(UInt<1>("h00"), T_311) + node T_316 = or(T_315, T_312) node T_317 = or(T_316, T_313) - node T_318 = or(T_317, T_314) - node T_319 = and(UInt<1>("h01"), T_318) - node T_320 = and(T_303, T_319) - reg T_322 : UInt<2>, clk, reset, UInt<2>("h00") - when T_320 : - node T_324 = eq(T_322, UInt<2>("h03")) - node T_326 = and(UInt<1>("h00"), T_324) - node T_329 = addw(T_322, UInt<1>("h01")) - node T_330 = mux(T_326, UInt<1>("h00"), T_329) - T_322 <= T_330 - skip - node T_331 = and(T_320, T_324) - node T_332 = mux(T_319, T_322, UInt<1>("h00")) - node irel_data_done = mux(T_319, T_331, T_303) + node T_318 = and(UInt<1>("h01"), T_317) + node T_319 = and(T_302, T_318) + reg T_321 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_319 : + node T_323 = eq(T_321, UInt<2>("h03")) + node T_325 = and(UInt<1>("h00"), T_323) + node T_328 = add(T_321, UInt<1>("h01")) + node T_329 = tail(T_328, 1) + node T_330 = mux(T_325, UInt<1>("h00"), T_329) + T_321 <= T_330 + skip + node T_331 = and(T_319, T_323) + node T_332 = mux(T_318, T_321, UInt<1>("h00")) + node irel_data_done = mux(T_318, T_331, T_302) node T_335 = and(io.outer.acquire.ready, io.outer.acquire.valid) node T_337 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) wire T_340 : UInt<3>[1] @@ -2829,17 +1781,18 @@ circuit Top : node T_345 = or(UInt<1>("h00"), T_343) node T_346 = and(T_337, T_345) node T_347 = and(T_335, T_346) - reg T_349 : UInt<2>, clk, reset, UInt<2>("h00") + reg T_349 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) when T_347 : node T_351 = eq(T_349, UInt<2>("h03")) node T_353 = and(UInt<1>("h00"), T_351) - node T_356 = addw(T_349, UInt<1>("h01")) - node T_357 = mux(T_353, UInt<1>("h00"), T_356) - T_349 <= T_357 + node T_356 = add(T_349, UInt<1>("h01")) + node T_357 = tail(T_356, 1) + node T_358 = mux(T_353, UInt<1>("h00"), T_357) + T_349 <= T_358 skip - node T_358 = and(T_347, T_351) + node T_359 = and(T_347, T_351) node oacq_data_cnt = mux(T_346, T_349, UInt<1>("h00")) - node oacq_data_done = mux(T_346, T_358, T_335) + node oacq_data_done = mux(T_346, T_359, T_335) io.has_acquire_conflict <= UInt<1>("h00") io.has_release_match <= io.inner.release.bits.voluntary io.has_acquire_match <= UInt<1>("h00") @@ -2850,155 +1803,143 @@ circuit Top : io.inner.release.ready <= UInt<1>("h00") io.inner.grant.valid <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") - wire T_383 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_383.client_id <= UInt<1>("h00") - T_383.data <= UInt<1>("h00") - T_383.g_type <= UInt<1>("h00") - T_383.is_builtin_type <= UInt<1>("h00") - T_383.manager_xact_id <= UInt<1>("h00") - T_383.client_xact_id <= UInt<1>("h00") - T_383.addr_beat <= UInt<1>("h00") - T_383.client_id <= xact.client_id - T_383.is_builtin_type <= UInt<1>("h01") - T_383.g_type <= UInt<3>("h00") - T_383.client_xact_id <= xact.client_xact_id - T_383.manager_xact_id <= UInt<1>("h00") - T_383.addr_beat <= UInt<1>("h00") - T_383.data <= UInt<1>("h00") - io.inner.grant.bits <- T_383 - node T_403 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_409 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_410 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_411 = cat(T_409, T_410) - node T_413 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_414 = cat(UInt<3>("h07"), T_413) - node T_416 = cat(T_403, UInt<1>("h01")) - node T_418 = cat(T_403, UInt<1>("h01")) - node T_420 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_421 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_422 = cat(T_420, T_421) - node T_424 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_426 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_427 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_428 = mux(T_427, T_426, UInt<1>("h00")) - node T_429 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_430 = mux(T_429, T_424, T_428) - node T_431 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_432 = mux(T_431, T_422, T_430) - node T_433 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_434 = mux(T_433, T_418, T_432) - node T_435 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_436 = mux(T_435, T_416, T_434) - node T_437 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_438 = mux(T_437, T_414, T_436) - node T_439 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_440 = mux(T_439, T_411, T_438) - wire T_449 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_449.data <= UInt<1>("h00") - T_449.union <= UInt<1>("h00") - T_449.a_type <= UInt<1>("h00") - T_449.is_builtin_type <= UInt<1>("h00") - T_449.addr_beat <= UInt<1>("h00") - T_449.client_xact_id <= UInt<1>("h00") - T_449.addr_block <= UInt<1>("h00") - T_449.is_builtin_type <= UInt<1>("h01") - T_449.a_type <= UInt<3>("h03") - T_449.client_xact_id <= UInt<1>("h00") - T_449.addr_block <= xact.addr_block - T_449.addr_beat <= oacq_data_cnt - T_449.data <= xact.data_buffer[oacq_data_cnt] - T_449.union <= T_440 - io.outer.acquire.bits <- T_449 + wire T_384 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} + T_384 is invalid + T_384.client_id <= xact.client_id + T_384.is_builtin_type <= UInt<1>("h01") + T_384.g_type <= UInt<3>("h00") + T_384.client_xact_id <= xact.client_xact_id + T_384.manager_xact_id <= UInt<1>("h00") + T_384.addr_beat <= UInt<1>("h00") + T_384.data <= UInt<1>("h00") + io.inner.grant.bits <- T_384 + node T_397 = asUInt(asSInt(UInt<16>("h0ffff"))) + node T_403 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_404 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_405 = cat(T_403, T_404) + node T_407 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_408 = cat(UInt<3>("h07"), T_407) + node T_410 = cat(T_397, UInt<1>("h01")) + node T_412 = cat(T_397, UInt<1>("h01")) + node T_414 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_415 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_416 = cat(T_414, T_415) + node T_418 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_420 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_421 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_422 = mux(T_421, T_420, UInt<1>("h00")) + node T_423 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_424 = mux(T_423, T_418, T_422) + node T_425 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_426 = mux(T_425, T_416, T_424) + node T_427 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_428 = mux(T_427, T_412, T_426) + node T_429 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_430 = mux(T_429, T_410, T_428) + node T_431 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_432 = mux(T_431, T_408, T_430) + node T_433 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_434 = mux(T_433, T_405, T_432) + wire T_443 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} + T_443 is invalid + T_443.is_builtin_type <= UInt<1>("h01") + T_443.a_type <= UInt<3>("h03") + T_443.client_xact_id <= UInt<1>("h00") + T_443.addr_block <= xact.addr_block + T_443.addr_beat <= oacq_data_cnt + T_443.data <= xact.data_buffer[oacq_data_cnt] + T_443.union <= T_434 + io.outer.acquire.bits <- T_443 when collect_irel_data : io.inner.release.ready <= UInt<1>("h01") when io.inner.release.valid : xact.data_buffer[io.inner.release.bits.addr_beat] <= io.inner.release.bits.data - node T_468 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) - node T_469 = or(irel_data_valid, T_468) - node T_470 = not(irel_data_valid) - node T_471 = or(T_470, T_468) - node T_472 = not(T_471) - node T_473 = mux(UInt<1>("h01"), T_469, T_472) - irel_data_valid <= T_473 + node T_455 = dshl(UInt<1>("h01"), io.inner.release.bits.addr_beat) + node T_456 = or(irel_data_valid, T_455) + node T_457 = not(irel_data_valid) + node T_458 = or(T_457, T_455) + node T_459 = not(T_458) + node T_460 = mux(UInt<1>("h01"), T_456, T_459) + irel_data_valid <= T_460 skip when irel_data_done : collect_irel_data <= UInt<1>("h00") skip skip - node T_475 = eq(UInt<1>("h00"), state) - when T_475 : + node T_462 = eq(UInt<1>("h00"), state) + when T_462 : io.inner.release.ready <= UInt<1>("h01") when io.inner.release.valid : xact <- io.inner.release.bits xact.data_buffer[UInt<1>("h00")] <= io.inner.release.bits.data - wire T_481 : UInt<2>[3] - T_481[0] <= UInt<1>("h00") - T_481[1] <= UInt<1>("h01") - T_481[2] <= UInt<2>("h02") - node T_486 = eq(T_481[0], io.inner.release.bits.r_type) - node T_487 = eq(T_481[1], io.inner.release.bits.r_type) - node T_488 = eq(T_481[2], io.inner.release.bits.r_type) - node T_490 = or(UInt<1>("h00"), T_486) - node T_491 = or(T_490, T_487) + wire T_468 : UInt<2>[3] + T_468[0] <= UInt<1>("h00") + T_468[1] <= UInt<1>("h01") + T_468[2] <= UInt<2>("h02") + node T_473 = eq(T_468[0], io.inner.release.bits.r_type) + node T_474 = eq(T_468[1], io.inner.release.bits.r_type) + node T_475 = eq(T_468[2], io.inner.release.bits.r_type) + node T_477 = or(UInt<1>("h00"), T_473) + node T_478 = or(T_477, T_474) + node T_479 = or(T_478, T_475) + node T_480 = and(UInt<1>("h01"), T_479) + collect_irel_data <= T_480 + wire T_482 : UInt<2>[3] + T_482[0] <= UInt<1>("h00") + T_482[1] <= UInt<1>("h01") + T_482[2] <= UInt<2>("h02") + node T_487 = eq(T_482[0], io.inner.release.bits.r_type) + node T_488 = eq(T_482[1], io.inner.release.bits.r_type) + node T_489 = eq(T_482[2], io.inner.release.bits.r_type) + node T_491 = or(UInt<1>("h00"), T_487) node T_492 = or(T_491, T_488) - node T_493 = and(UInt<1>("h01"), T_492) - collect_irel_data <= T_493 - wire T_495 : UInt<2>[3] - T_495[0] <= UInt<1>("h00") - T_495[1] <= UInt<1>("h01") - T_495[2] <= UInt<2>("h02") - node T_500 = eq(T_495[0], io.inner.release.bits.r_type) - node T_501 = eq(T_495[1], io.inner.release.bits.r_type) - node T_502 = eq(T_495[2], io.inner.release.bits.r_type) - node T_504 = or(UInt<1>("h00"), T_500) - node T_505 = or(T_504, T_501) + node T_493 = or(T_492, T_489) + node T_494 = dshl(T_493, io.inner.release.bits.addr_beat) + irel_data_valid <= T_494 + wire T_496 : UInt<2>[3] + T_496[0] <= UInt<1>("h00") + T_496[1] <= UInt<1>("h01") + T_496[2] <= UInt<2>("h02") + node T_501 = eq(T_496[0], io.inner.release.bits.r_type) + node T_502 = eq(T_496[1], io.inner.release.bits.r_type) + node T_503 = eq(T_496[2], io.inner.release.bits.r_type) + node T_505 = or(UInt<1>("h00"), T_501) node T_506 = or(T_505, T_502) - node T_507 = dshl(T_506, io.inner.release.bits.addr_beat) - irel_data_valid <= T_507 - wire T_509 : UInt<2>[3] - T_509[0] <= UInt<1>("h00") - T_509[1] <= UInt<1>("h01") - T_509[2] <= UInt<2>("h02") - node T_514 = eq(T_509[0], io.inner.release.bits.r_type) - node T_515 = eq(T_509[1], io.inner.release.bits.r_type) - node T_516 = eq(T_509[2], io.inner.release.bits.r_type) - node T_518 = or(UInt<1>("h00"), T_514) - node T_519 = or(T_518, T_515) - node T_520 = or(T_519, T_516) - node T_523 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_524 = mux(T_523, UInt<2>("h03"), UInt<1>("h00")) - node T_525 = mux(T_520, UInt<1>("h01"), T_524) - state <= T_525 - skip - skip - node T_526 = eq(UInt<1>("h01"), state) - when T_526 : - node T_528 = eq(collect_irel_data, UInt<1>("h00")) - node T_529 = dshr(irel_data_valid, oacq_data_cnt) - node T_530 = bit(T_529, 0) - node T_531 = or(T_528, T_530) - io.outer.acquire.valid <= T_531 + node T_507 = or(T_506, T_503) + node T_510 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_511 = mux(T_510, UInt<2>("h03"), UInt<1>("h00")) + node T_512 = mux(T_507, UInt<1>("h01"), T_511) + state <= T_512 + skip + skip + node T_513 = eq(UInt<1>("h01"), state) + when T_513 : + node T_515 = eq(collect_irel_data, UInt<1>("h00")) + node T_516 = dshr(irel_data_valid, oacq_data_cnt) + node T_517 = bits(T_516, 0, 0) + node T_518 = or(T_515, T_517) + io.outer.acquire.valid <= T_518 when oacq_data_done : state <= UInt<2>("h02") skip skip - node T_532 = eq(UInt<2>("h02"), state) - when T_532 : + node T_519 = eq(UInt<2>("h02"), state) + when T_519 : io.outer.grant.ready <= io.inner.grant.ready io.inner.grant.valid <= io.outer.grant.valid - node T_533 = and(io.inner.grant.ready, io.inner.grant.valid) - when T_533 : - node T_536 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_538 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_539 = and(io.inner.grant.bits.is_builtin_type, T_538) - node T_541 = eq(T_539, UInt<1>("h00")) - node T_542 = and(T_536, T_541) - node T_543 = mux(T_542, UInt<2>("h03"), UInt<1>("h00")) - state <= T_543 - skip - skip - node T_544 = eq(UInt<2>("h03"), state) - when T_544 : + node T_520 = and(io.inner.grant.ready, io.inner.grant.valid) + when T_520 : + node T_523 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_525 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) + node T_526 = and(io.inner.grant.bits.is_builtin_type, T_525) + node T_528 = eq(T_526, UInt<1>("h00")) + node T_529 = and(T_523, T_528) + node T_530 = mux(T_529, UInt<2>("h03"), UInt<1>("h00")) + state <= T_530 + skip + skip + node T_531 = eq(UInt<2>("h03"), state) + when T_531 : io.inner.finish.ready <= UInt<1>("h01") when io.inner.finish.valid : state <= UInt<1>("h00") @@ -3010,98 +1951,73 @@ circuit Top : input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - io.has_release_match <= UInt<1>("h00") - io.has_acquire_match <= UInt<1>("h00") - io.has_acquire_conflict <= UInt<1>("h00") - io.outer.grant.ready <= UInt<1>("h00") - io.outer.acquire.bits.data <= UInt<1>("h00") - io.outer.acquire.bits.union <= UInt<1>("h00") - io.outer.acquire.bits.a_type <= UInt<1>("h00") - io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.outer.acquire.bits.addr_beat <= UInt<1>("h00") - io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") - io.outer.acquire.bits.addr_block <= UInt<1>("h00") - io.outer.acquire.valid <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.probe.bits.client_id <= UInt<1>("h00") - io.inner.probe.bits.p_type <= UInt<1>("h00") - io.inner.probe.bits.addr_block <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - io.inner.grant.bits.client_id <= UInt<1>("h00") - io.inner.grant.bits.data <= UInt<1>("h00") - io.inner.grant.bits.g_type <= UInt<1>("h00") - io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") - io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") - io.inner.grant.bits.client_xact_id <= UInt<1>("h00") - io.inner.grant.bits.addr_beat <= UInt<1>("h00") - io.inner.grant.valid <= UInt<1>("h00") - io.inner.acquire.ready <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk, UInt<1>("h00"), xact + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk wire coh : {sharers : UInt<1>} + coh is invalid coh.sharers <= UInt<1>("h00") - coh.sharers <= UInt<1>("h00") - node T_304 = neq(state, UInt<1>("h00")) - node T_305 = and(T_304, xact.is_builtin_type) - wire T_310 : UInt<3>[3] - T_310[0] <= UInt<3>("h04") - T_310[1] <= UInt<3>("h05") - T_310[2] <= UInt<3>("h06") - node T_315 = eq(T_310[0], xact.a_type) - node T_316 = eq(T_310[1], xact.a_type) - node T_317 = eq(T_310[2], xact.a_type) - node T_319 = or(UInt<1>("h00"), T_315) + node T_303 = neq(state, UInt<1>("h00")) + node T_304 = and(T_303, xact.is_builtin_type) + wire T_309 : UInt<3>[3] + T_309[0] <= UInt<3>("h04") + T_309[1] <= UInt<3>("h05") + T_309[2] <= UInt<3>("h06") + node T_314 = eq(T_309[0], xact.a_type) + node T_315 = eq(T_309[1], xact.a_type) + node T_316 = eq(T_309[2], xact.a_type) + node T_318 = or(UInt<1>("h00"), T_314) + node T_319 = or(T_318, T_315) node T_320 = or(T_319, T_316) - node T_321 = or(T_320, T_317) - node T_322 = and(T_305, T_321) - node T_324 = eq(T_322, UInt<1>("h00")) - node T_326 = eq(reset, UInt<1>("h00")) - when T_326 : - node T_328 = eq(T_324, UInt<1>("h00")) - when T_328 : - node T_330 = eq(reset, UInt<1>("h00")) - when T_330 : + node T_321 = and(T_304, T_320) + node T_323 = eq(T_321, UInt<1>("h00")) + node T_325 = eq(reset, UInt<1>("h00")) + when T_325 : + node T_327 = eq(T_323, UInt<1>("h00")) + when T_327 : + node T_329 = eq(reset, UInt<1>("h00")) + when T_329 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") skip stop(clk, UInt<1>(1), 1) skip skip - reg release_count : UInt<1>, clk, reset, UInt<1>("h00") - reg pending_probes : UInt<1>, clk, reset, UInt<1>("h00") - node T_335 = bit(pending_probes, 0) - wire T_337 : UInt<1>[1] - T_337[0] <= T_335 - node T_342 = asUInt(asSInt(UInt<1>("h01"))) - node T_345 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) - node T_346 = or(T_342, T_345) - node T_347 = not(T_342) - node T_348 = or(T_347, T_345) - node T_349 = not(T_348) - node mask_self = mux(UInt<1>("h00"), T_346, T_349) - node T_351 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_351) - reg collect_iacq_data : UInt<1>, clk, reset, UInt<1>("h00") - reg iacq_data_valid : UInt<4>, clk, reset, UInt<4>("h00") - node T_357 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_360 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_363 : UInt<3>[1] - T_363[0] <= UInt<3>("h03") - node T_366 = eq(T_363[0], io.inner.acquire.bits.a_type) - node T_368 = or(UInt<1>("h00"), T_366) - node T_369 = and(T_360, T_368) - node T_370 = and(T_357, T_369) - reg T_372 : UInt<2>, clk, reset, UInt<2>("h00") - when T_370 : - node T_374 = eq(T_372, UInt<2>("h03")) - node T_376 = and(UInt<1>("h00"), T_374) - node T_379 = addw(T_372, UInt<1>("h01")) - node T_380 = mux(T_376, UInt<1>("h00"), T_379) - T_372 <= T_380 - skip - node T_381 = and(T_370, T_374) - node T_382 = mux(T_369, T_372, UInt<1>("h00")) - node iacq_data_done = mux(T_369, T_381, T_357) + reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_334 = bits(pending_probes, 0, 0) + wire T_336 : UInt<1>[1] + T_336[0] <= T_334 + node T_341 = asUInt(asSInt(UInt<1>("h01"))) + node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) + node T_345 = or(T_341, T_344) + node T_346 = not(T_341) + node T_347 = or(T_346, T_344) + node T_348 = not(T_347) + node mask_self = mux(UInt<1>("h00"), T_345, T_348) + node T_350 = not(io.incoherent[0]) + node mask_incoherent = and(mask_self, T_350) + reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) + node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_362 : UInt<3>[1] + T_362[0] <= UInt<3>("h03") + node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) + node T_367 = or(UInt<1>("h00"), T_365) + node T_368 = and(T_359, T_367) + node T_369 = and(T_356, T_368) + reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_369 : + node T_373 = eq(T_371, UInt<2>("h03")) + node T_375 = and(UInt<1>("h00"), T_373) + node T_378 = add(T_371, UInt<1>("h01")) + node T_379 = tail(T_378, 1) + node T_380 = mux(T_375, UInt<1>("h00"), T_379) + T_371 <= T_380 + skip + node T_381 = and(T_369, T_373) + node T_382 = mux(T_368, T_371, UInt<1>("h00")) + node iacq_data_done = mux(T_368, T_381, T_356) node T_384 = and(io.inner.release.ready, io.inner.release.valid) wire T_388 : UInt<2>[3] T_388[0] <= UInt<1>("h00") @@ -3115,577 +2031,523 @@ circuit Top : node T_399 = or(T_398, T_395) node T_400 = and(UInt<1>("h01"), T_399) node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk, reset, UInt<2>("h00") + reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) when T_401 : node T_405 = eq(T_403, UInt<2>("h03")) node T_407 = and(UInt<1>("h00"), T_405) - node T_410 = addw(T_403, UInt<1>("h01")) - node T_411 = mux(T_407, UInt<1>("h00"), T_410) - T_403 <= T_411 - skip - node T_412 = and(T_401, T_405) - node T_413 = mux(T_400, T_403, UInt<1>("h00")) - node irel_data_done = mux(T_400, T_412, T_384) - node T_416 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_420 : UInt<3>[1] - T_420[0] <= UInt<3>("h05") - node T_423 = eq(T_420[0], io.inner.grant.bits.g_type) - node T_425 = or(UInt<1>("h00"), T_423) - wire T_427 : UInt<1>[2] - T_427[0] <= UInt<1>("h00") - T_427[1] <= UInt<1>("h01") - node T_431 = eq(T_427[0], io.inner.grant.bits.g_type) - node T_432 = eq(T_427[1], io.inner.grant.bits.g_type) - node T_434 = or(UInt<1>("h00"), T_431) - node T_435 = or(T_434, T_432) - node T_436 = mux(io.inner.grant.bits.is_builtin_type, T_425, T_435) - node T_437 = and(UInt<1>("h01"), T_436) - node T_438 = and(T_416, T_437) - reg T_440 : UInt<2>, clk, reset, UInt<2>("h00") - when T_438 : - node T_442 = eq(T_440, UInt<2>("h03")) - node T_444 = and(UInt<1>("h00"), T_442) - node T_447 = addw(T_440, UInt<1>("h01")) - node T_448 = mux(T_444, UInt<1>("h00"), T_447) - T_440 <= T_448 - skip - node T_449 = and(T_438, T_442) - node ignt_data_cnt = mux(T_437, T_440, UInt<1>("h00")) - node ignt_data_done = mux(T_437, T_449, T_416) - node T_453 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_455 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) - wire T_458 : UInt<3>[1] - T_458[0] <= UInt<3>("h03") - node T_461 = eq(T_458[0], io.outer.acquire.bits.a_type) - node T_463 = or(UInt<1>("h00"), T_461) - node T_464 = and(T_455, T_463) - node T_465 = and(T_453, T_464) - reg T_467 : UInt<2>, clk, reset, UInt<2>("h00") - when T_465 : - node T_469 = eq(T_467, UInt<2>("h03")) - node T_471 = and(UInt<1>("h00"), T_469) - node T_474 = addw(T_467, UInt<1>("h01")) - node T_475 = mux(T_471, UInt<1>("h00"), T_474) - T_467 <= T_475 - skip - node T_476 = and(T_465, T_469) - node oacq_data_cnt = mux(T_464, T_467, UInt<1>("h00")) - node oacq_data_done = mux(T_464, T_476, T_453) - node T_479 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_484 : UInt<3>[1] - T_484[0] <= UInt<3>("h05") - node T_487 = eq(T_484[0], io.outer.grant.bits.g_type) - node T_489 = or(UInt<1>("h00"), T_487) - wire T_491 : UInt<1>[1] - T_491[0] <= UInt<1>("h00") - node T_494 = eq(T_491[0], io.outer.grant.bits.g_type) - node T_496 = or(UInt<1>("h00"), T_494) - node T_497 = mux(io.outer.grant.bits.is_builtin_type, T_489, T_496) - node T_498 = and(UInt<1>("h01"), T_497) - node T_499 = and(T_479, T_498) - reg T_501 : UInt<2>, clk, reset, UInt<2>("h00") - when T_499 : - node T_503 = eq(T_501, UInt<2>("h03")) - node T_505 = and(UInt<1>("h00"), T_503) - node T_508 = addw(T_501, UInt<1>("h01")) - node T_509 = mux(T_505, UInt<1>("h00"), T_508) - T_501 <= T_509 - skip - node T_510 = and(T_499, T_503) - node T_511 = mux(T_498, T_501, UInt<1>("h00")) - node ognt_data_done = mux(T_498, T_510, T_479) - reg pending_ognt_ack : UInt<1>, clk, reset, UInt<1>("h00") - wire T_519 : UInt<3>[3] - T_519[0] <= UInt<3>("h02") - T_519[1] <= UInt<3>("h03") - T_519[2] <= UInt<3>("h04") - node T_524 = eq(T_519[0], xact.a_type) - node T_525 = eq(T_519[1], xact.a_type) - node T_526 = eq(T_519[2], xact.a_type) - node T_528 = or(UInt<1>("h00"), T_524) - node T_529 = or(T_528, T_525) - node T_530 = or(T_529, T_526) - node pending_outer_write = and(xact.is_builtin_type, T_530) - wire T_536 : UInt<3>[3] - T_536[0] <= UInt<3>("h02") - T_536[1] <= UInt<3>("h03") - T_536[2] <= UInt<3>("h04") - node T_541 = eq(T_536[0], io.inner.acquire.bits.a_type) - node T_542 = eq(T_536[1], io.inner.acquire.bits.a_type) - node T_543 = eq(T_536[2], io.inner.acquire.bits.a_type) - node T_545 = or(UInt<1>("h00"), T_541) - node T_546 = or(T_545, T_542) - node T_547 = or(T_546, T_543) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_547) - wire T_552 : UInt<3>[2] - T_552[0] <= UInt<3>("h05") - T_552[1] <= UInt<3>("h04") - node T_556 = eq(T_552[0], io.inner.grant.bits.g_type) - node T_557 = eq(T_552[1], io.inner.grant.bits.g_type) - node T_559 = or(UInt<1>("h00"), T_556) - node T_560 = or(T_559, T_557) - wire T_562 : UInt<1>[2] - T_562[0] <= UInt<1>("h00") - T_562[1] <= UInt<1>("h01") - node T_566 = eq(T_562[0], io.inner.grant.bits.g_type) - node T_567 = eq(T_562[1], io.inner.grant.bits.g_type) - node T_569 = or(UInt<1>("h00"), T_566) - node T_570 = or(T_569, T_567) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_560, T_570) - node T_590 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) - node T_591 = mux(T_590, UInt<3>("h01"), UInt<3>("h03")) - node T_592 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) - node T_593 = mux(T_592, UInt<3>("h01"), T_591) - node T_594 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h04"), T_593) - node T_596 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h03"), T_595) - node T_598 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h03"), T_597) - node T_600 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h05"), T_599) - node T_602 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h04"), T_601) - node T_604 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) - node T_607 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_608 = mux(T_607, UInt<1>("h00"), UInt<1>("h01")) - node T_609 = mux(T_604, T_608, UInt<1>("h01")) - node T_610 = mux(io.inner.acquire.bits.is_builtin_type, T_603, T_609) - wire T_619 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_619.client_id <= UInt<1>("h00") - T_619.data <= UInt<1>("h00") - T_619.g_type <= UInt<1>("h00") - T_619.is_builtin_type <= UInt<1>("h00") - T_619.manager_xact_id <= UInt<1>("h00") - T_619.client_xact_id <= UInt<1>("h00") - T_619.addr_beat <= UInt<1>("h00") - T_619.client_id <= io.inner.acquire.bits.client_id - T_619.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_619.g_type <= T_610 - T_619.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_619.manager_xact_id <= UInt<1>("h01") - T_619.addr_beat <= UInt<1>("h00") - T_619.data <= UInt<1>("h00") - wire T_637 : UInt<3>[2] - T_637[0] <= UInt<3>("h05") - T_637[1] <= UInt<3>("h04") - node T_641 = eq(T_637[0], T_619.g_type) - node T_642 = eq(T_637[1], T_619.g_type) - node T_644 = or(UInt<1>("h00"), T_641) - node T_645 = or(T_644, T_642) - wire T_647 : UInt<1>[2] - T_647[0] <= UInt<1>("h00") - T_647[1] <= UInt<1>("h01") - node T_651 = eq(T_647[0], T_619.g_type) - node T_652 = eq(T_647[1], T_619.g_type) - node T_654 = or(UInt<1>("h00"), T_651) - node T_655 = or(T_654, T_652) - node pending_outer_read_ = mux(T_619.is_builtin_type, T_645, T_655) - wire T_661 : UInt<3>[3] - T_661[0] <= UInt<3>("h02") - T_661[1] <= UInt<3>("h00") - T_661[2] <= UInt<3>("h04") - node T_666 = eq(T_661[0], xact.a_type) - node T_667 = eq(T_661[1], xact.a_type) - node T_668 = eq(T_661[2], xact.a_type) - node T_670 = or(UInt<1>("h00"), T_666) - node T_671 = or(T_670, T_667) - node T_672 = or(T_671, T_668) - node subblock_type = and(xact.is_builtin_type, T_672) - node T_674 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_675 = neq(state, UInt<1>("h00")) - node T_676 = and(T_674, T_675) - node T_678 = eq(collect_iacq_data, UInt<1>("h00")) - node T_679 = and(T_676, T_678) - io.has_acquire_conflict <= T_679 - node T_680 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_681 = and(T_680, collect_iacq_data) - io.has_acquire_match <= T_681 - node T_682 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_684 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) - node T_685 = and(T_682, T_684) - node T_686 = eq(state, UInt<1>("h01")) - node T_687 = and(T_685, T_686) - io.has_release_match <= T_687 - node T_692 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_698 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_410 = add(T_403, UInt<1>("h01")) + node T_411 = tail(T_410, 1) + node T_412 = mux(T_407, UInt<1>("h00"), T_411) + T_403 <= T_412 + skip + node T_413 = and(T_401, T_405) + node T_414 = mux(T_400, T_403, UInt<1>("h00")) + node irel_data_done = mux(T_400, T_413, T_384) + node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) + wire T_421 : UInt<3>[1] + T_421[0] <= UInt<3>("h05") + node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) + node T_426 = or(UInt<1>("h00"), T_424) + wire T_428 : UInt<1>[2] + T_428[0] <= UInt<1>("h00") + T_428[1] <= UInt<1>("h01") + node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) + node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) + node T_435 = or(UInt<1>("h00"), T_432) + node T_436 = or(T_435, T_433) + node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) + node T_438 = and(UInt<1>("h01"), T_437) + node T_439 = and(T_417, T_438) + reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_439 : + node T_443 = eq(T_441, UInt<2>("h03")) + node T_445 = and(UInt<1>("h00"), T_443) + node T_448 = add(T_441, UInt<1>("h01")) + node T_449 = tail(T_448, 1) + node T_450 = mux(T_445, UInt<1>("h00"), T_449) + T_441 <= T_450 + skip + node T_451 = and(T_439, T_443) + node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00")) + node ignt_data_done = mux(T_438, T_451, T_417) + node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) + wire T_460 : UInt<3>[1] + T_460[0] <= UInt<3>("h03") + node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) + node T_465 = or(UInt<1>("h00"), T_463) + node T_466 = and(T_457, T_465) + node T_467 = and(T_455, T_466) + reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_467 : + node T_471 = eq(T_469, UInt<2>("h03")) + node T_473 = and(UInt<1>("h00"), T_471) + node T_476 = add(T_469, UInt<1>("h01")) + node T_477 = tail(T_476, 1) + node T_478 = mux(T_473, UInt<1>("h00"), T_477) + T_469 <= T_478 + skip + node T_479 = and(T_467, T_471) + node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00")) + node oacq_data_done = mux(T_466, T_479, T_455) + node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_487 : UInt<3>[1] + T_487[0] <= UInt<3>("h05") + node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) + node T_492 = or(UInt<1>("h00"), T_490) + wire T_494 : UInt<1>[1] + T_494[0] <= UInt<1>("h00") + node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) + node T_499 = or(UInt<1>("h00"), T_497) + node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) + node T_501 = and(UInt<1>("h01"), T_500) + node T_502 = and(T_482, T_501) + reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_502 : + node T_506 = eq(T_504, UInt<2>("h03")) + node T_508 = and(UInt<1>("h00"), T_506) + node T_511 = add(T_504, UInt<1>("h01")) + node T_512 = tail(T_511, 1) + node T_513 = mux(T_508, UInt<1>("h00"), T_512) + T_504 <= T_513 + skip + node T_514 = and(T_502, T_506) + node T_515 = mux(T_501, T_504, UInt<1>("h00")) + node ognt_data_done = mux(T_501, T_514, T_482) + reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + wire T_523 : UInt<3>[3] + T_523[0] <= UInt<3>("h02") + T_523[1] <= UInt<3>("h03") + T_523[2] <= UInt<3>("h04") + node T_528 = eq(T_523[0], xact.a_type) + node T_529 = eq(T_523[1], xact.a_type) + node T_530 = eq(T_523[2], xact.a_type) + node T_532 = or(UInt<1>("h00"), T_528) + node T_533 = or(T_532, T_529) + node T_534 = or(T_533, T_530) + node pending_outer_write = and(xact.is_builtin_type, T_534) + wire T_540 : UInt<3>[3] + T_540[0] <= UInt<3>("h02") + T_540[1] <= UInt<3>("h03") + T_540[2] <= UInt<3>("h04") + node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) + node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) + node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) + node T_549 = or(UInt<1>("h00"), T_545) + node T_550 = or(T_549, T_546) + node T_551 = or(T_550, T_547) + node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) + wire T_556 : UInt<3>[2] + T_556[0] <= UInt<3>("h05") + T_556[1] <= UInt<3>("h04") + node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) + node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) + node T_563 = or(UInt<1>("h00"), T_560) + node T_564 = or(T_563, T_561) + wire T_566 : UInt<1>[2] + T_566[0] <= UInt<1>("h00") + T_566[1] <= UInt<1>("h01") + node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) + node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) + node T_573 = or(UInt<1>("h00"), T_570) + node T_574 = or(T_573, T_571) + node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) + node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) + node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03")) + node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) + node T_597 = mux(T_596, UInt<3>("h01"), T_595) + node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) + node T_599 = mux(T_598, UInt<3>("h04"), T_597) + node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) + node T_601 = mux(T_600, UInt<3>("h03"), T_599) + node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) + node T_603 = mux(T_602, UInt<3>("h03"), T_601) + node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) + node T_605 = mux(T_604, UInt<3>("h05"), T_603) + node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) + node T_607 = mux(T_606, UInt<3>("h04"), T_605) + node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) + node T_611 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01")) + node T_613 = mux(T_608, T_612, UInt<1>("h01")) + node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) + wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} + T_623 is invalid + T_623.client_id <= io.inner.acquire.bits.client_id + T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type + T_623.g_type <= T_614 + T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id + T_623.manager_xact_id <= UInt<1>("h01") + T_623.addr_beat <= UInt<1>("h00") + T_623.data <= UInt<1>("h00") + wire T_634 : UInt<3>[2] + T_634[0] <= UInt<3>("h05") + T_634[1] <= UInt<3>("h04") + node T_638 = eq(T_634[0], T_623.g_type) + node T_639 = eq(T_634[1], T_623.g_type) + node T_641 = or(UInt<1>("h00"), T_638) + node T_642 = or(T_641, T_639) + wire T_644 : UInt<1>[2] + T_644[0] <= UInt<1>("h00") + T_644[1] <= UInt<1>("h01") + node T_648 = eq(T_644[0], T_623.g_type) + node T_649 = eq(T_644[1], T_623.g_type) + node T_651 = or(UInt<1>("h00"), T_648) + node T_652 = or(T_651, T_649) + node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) + wire T_658 : UInt<3>[3] + T_658[0] <= UInt<3>("h02") + T_658[1] <= UInt<3>("h00") + T_658[2] <= UInt<3>("h04") + node T_663 = eq(T_658[0], xact.a_type) + node T_664 = eq(T_658[1], xact.a_type) + node T_665 = eq(T_658[2], xact.a_type) + node T_667 = or(UInt<1>("h00"), T_663) + node T_668 = or(T_667, T_664) + node T_669 = or(T_668, T_665) + node subblock_type = and(xact.is_builtin_type, T_669) + node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) + node T_672 = neq(state, UInt<1>("h00")) + node T_673 = and(T_671, T_672) + node T_675 = eq(collect_iacq_data, UInt<1>("h00")) + node T_676 = and(T_673, T_675) + io.has_acquire_conflict <= T_676 + node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) + node T_678 = and(T_677, collect_iacq_data) + io.has_acquire_match <= T_678 + node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) + node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) + node T_682 = and(T_679, T_681) + node T_683 = eq(state, UInt<1>("h01")) + node T_684 = and(T_682, T_683) + io.has_release_match <= T_684 + node T_689 = asUInt(asSInt(UInt<16>("h0ffff"))) + node T_695 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_696 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_697 = cat(T_695, T_696) node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_700 = cat(T_698, T_699) - node T_702 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_703 = cat(UInt<3>("h07"), T_702) - node T_705 = cat(T_692, UInt<1>("h01")) - node T_707 = cat(T_692, UInt<1>("h01")) - node T_709 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_710 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_711 = cat(T_709, T_710) - node T_713 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_715 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_716 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_717 = mux(T_716, T_715, UInt<1>("h00")) - node T_718 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_719 = mux(T_718, T_713, T_717) - node T_720 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_721 = mux(T_720, T_711, T_719) - node T_722 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_723 = mux(T_722, T_707, T_721) - node T_724 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_725 = mux(T_724, T_705, T_723) - node T_726 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_727 = mux(T_726, T_703, T_725) - node T_728 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_729 = mux(T_728, T_700, T_727) + node T_700 = cat(UInt<3>("h07"), T_699) + node T_702 = cat(T_689, UInt<1>("h01")) + node T_704 = cat(T_689, UInt<1>("h01")) + node T_706 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_707 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_708 = cat(T_706, T_707) + node T_710 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_712 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_713 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_714 = mux(T_713, T_712, UInt<1>("h00")) + node T_715 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_716 = mux(T_715, T_710, T_714) + node T_717 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_718 = mux(T_717, T_708, T_716) + node T_719 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_720 = mux(T_719, T_704, T_718) + node T_721 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_722 = mux(T_721, T_702, T_720) + node T_723 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_724 = mux(T_723, T_700, T_722) + node T_725 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_726 = mux(T_725, T_697, T_724) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe.data <= UInt<1>("h00") - oacq_probe.union <= UInt<1>("h00") - oacq_probe.a_type <= UInt<1>("h00") - oacq_probe.is_builtin_type <= UInt<1>("h00") - oacq_probe.addr_beat <= UInt<1>("h00") - oacq_probe.client_xact_id <= UInt<1>("h00") - oacq_probe.addr_block <= UInt<1>("h00") + oacq_probe is invalid oacq_probe.is_builtin_type <= UInt<1>("h01") oacq_probe.a_type <= UInt<3>("h03") oacq_probe.client_xact_id <= UInt<1>("h01") oacq_probe.addr_block <= io.inner.release.bits.addr_block oacq_probe.addr_beat <= io.inner.release.bits.addr_beat oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_729 - node T_754 = bits(xact.union, 12, 9) - node T_755 = bits(T_754, 3, 3) - node T_757 = dshl(UInt<1>("h01"), T_755) - node T_759 = eq(xact.a_type, UInt<3>("h04")) - node T_760 = and(xact.is_builtin_type, T_759) - node T_761 = bit(T_757, 0) - node T_762 = bit(T_757, 1) - wire T_764 : UInt<1>[2] - T_764[0] <= T_761 - T_764[1] <= T_762 - node T_769 = subw(UInt<8>("h00"), T_764[0]) - node T_771 = subw(UInt<8>("h00"), T_764[1]) - wire T_773 : UInt<8>[2] - T_773[0] <= T_769 - T_773[1] <= T_771 - node T_777 = cat(T_773[1], T_773[0]) - node T_779 = eq(xact.a_type, UInt<3>("h03")) - node T_780 = and(xact.is_builtin_type, T_779) - node T_782 = eq(xact.a_type, UInt<3>("h02")) - node T_783 = and(xact.is_builtin_type, T_782) - node T_784 = or(T_780, T_783) - node T_785 = bits(xact.union, 16, 1) - node T_787 = mux(T_784, T_785, UInt<16>("h00")) - node T_788 = mux(T_760, T_777, T_787) - node T_796 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_797 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_798 = cat(T_796, T_797) + oacq_probe.union <= T_726 + node T_744 = bits(xact.union, 12, 9) + node T_745 = bits(T_744, 3, 3) + node T_747 = dshl(UInt<1>("h01"), T_745) + node T_749 = eq(xact.a_type, UInt<3>("h04")) + node T_750 = and(xact.is_builtin_type, T_749) + node T_751 = bits(T_747, 0, 0) + node T_752 = bits(T_747, 1, 1) + wire T_754 : UInt<1>[2] + T_754[0] <= T_751 + T_754[1] <= T_752 + node T_759 = sub(UInt<8>("h00"), T_754[0]) + node T_760 = tail(T_759, 1) + node T_762 = sub(UInt<8>("h00"), T_754[1]) + node T_763 = tail(T_762, 1) + wire T_765 : UInt<8>[2] + T_765[0] <= T_760 + T_765[1] <= T_763 + node T_769 = cat(T_765[1], T_765[0]) + node T_771 = eq(xact.a_type, UInt<3>("h03")) + node T_772 = and(xact.is_builtin_type, T_771) + node T_774 = eq(xact.a_type, UInt<3>("h02")) + node T_775 = and(xact.is_builtin_type, T_774) + node T_776 = or(T_772, T_775) + node T_777 = bits(xact.union, 16, 1) + node T_779 = mux(T_776, T_777, UInt<16>("h00")) + node T_780 = mux(T_750, T_769, T_779) + node T_788 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_789 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_790 = cat(T_788, T_789) + node T_792 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_793 = cat(UInt<3>("h07"), T_792) + node T_795 = cat(T_780, UInt<1>("h01")) + node T_797 = cat(T_780, UInt<1>("h01")) + node T_799 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_801 = cat(UInt<3>("h07"), T_800) - node T_803 = cat(T_788, UInt<1>("h01")) - node T_805 = cat(T_788, UInt<1>("h01")) - node T_807 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_808 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_809 = cat(T_807, T_808) - node T_811 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_813 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_814 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_815 = mux(T_814, T_813, UInt<1>("h00")) - node T_816 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_817 = mux(T_816, T_811, T_815) - node T_818 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_819 = mux(T_818, T_809, T_817) - node T_820 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_821 = mux(T_820, T_805, T_819) - node T_822 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_823 = mux(T_822, T_803, T_821) - node T_824 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_825 = mux(T_824, T_801, T_823) - node T_826 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_827 = mux(T_826, T_798, T_825) + node T_801 = cat(T_799, T_800) + node T_803 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_805 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_806 = eq(UInt<3>("h06"), UInt<3>("h02")) + node T_807 = mux(T_806, T_805, UInt<1>("h00")) + node T_808 = eq(UInt<3>("h05"), UInt<3>("h02")) + node T_809 = mux(T_808, T_803, T_807) + node T_810 = eq(UInt<3>("h04"), UInt<3>("h02")) + node T_811 = mux(T_810, T_801, T_809) + node T_812 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_813 = mux(T_812, T_797, T_811) + node T_814 = eq(UInt<3>("h02"), UInt<3>("h02")) + node T_815 = mux(T_814, T_795, T_813) + node T_816 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_817 = mux(T_816, T_793, T_815) + node T_818 = eq(UInt<3>("h00"), UInt<3>("h02")) + node T_819 = mux(T_818, T_790, T_817) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat.data <= UInt<1>("h00") - oacq_write_beat.union <= UInt<1>("h00") - oacq_write_beat.a_type <= UInt<1>("h00") - oacq_write_beat.is_builtin_type <= UInt<1>("h00") - oacq_write_beat.addr_beat <= UInt<1>("h00") - oacq_write_beat.client_xact_id <= UInt<1>("h00") - oacq_write_beat.addr_block <= UInt<1>("h00") + oacq_write_beat is invalid oacq_write_beat.is_builtin_type <= UInt<1>("h01") oacq_write_beat.a_type <= UInt<3>("h02") oacq_write_beat.client_xact_id <= UInt<1>("h01") oacq_write_beat.addr_block <= xact.addr_block oacq_write_beat.addr_beat <= xact.addr_beat oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_827 - node T_861 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_862 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_863 = cat(T_861, T_862) - node T_865 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_866 = cat(UInt<3>("h07"), T_865) - node T_868 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_870 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_872 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_873 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_874 = cat(T_872, T_873) - node T_876 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_878 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_879 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_880 = mux(T_879, T_878, UInt<1>("h00")) - node T_881 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_882 = mux(T_881, T_876, T_880) - node T_883 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_884 = mux(T_883, T_874, T_882) - node T_885 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_886 = mux(T_885, T_870, T_884) - node T_887 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_888 = mux(T_887, T_868, T_886) - node T_889 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_890 = mux(T_889, T_866, T_888) - node T_891 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_892 = mux(T_891, T_863, T_890) + oacq_write_beat.union <= T_819 + node T_846 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_847 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_848 = cat(T_846, T_847) + node T_850 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_851 = cat(UInt<3>("h07"), T_850) + node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) + node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) + node T_857 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_858 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_859 = cat(T_857, T_858) + node T_861 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_863 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_864 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_865 = mux(T_864, T_863, UInt<1>("h00")) + node T_866 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_867 = mux(T_866, T_861, T_865) + node T_868 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_869 = mux(T_868, T_859, T_867) + node T_870 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_871 = mux(T_870, T_855, T_869) + node T_872 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_873 = mux(T_872, T_853, T_871) + node T_874 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_875 = mux(T_874, T_851, T_873) + node T_876 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_877 = mux(T_876, T_848, T_875) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block.data <= UInt<1>("h00") - oacq_write_block.union <= UInt<1>("h00") - oacq_write_block.a_type <= UInt<1>("h00") - oacq_write_block.is_builtin_type <= UInt<1>("h00") - oacq_write_block.addr_beat <= UInt<1>("h00") - oacq_write_block.client_xact_id <= UInt<1>("h00") - oacq_write_block.addr_block <= UInt<1>("h00") + oacq_write_block is invalid oacq_write_block.is_builtin_type <= UInt<1>("h01") oacq_write_block.a_type <= UInt<3>("h03") oacq_write_block.client_xact_id <= UInt<1>("h01") oacq_write_block.addr_block <= xact.addr_block oacq_write_block.addr_beat <= oacq_data_cnt oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_892 - node T_917 = bits(xact.union, 12, 9) - node T_918 = bits(xact.union, 8, 6) - node T_926 = cat(T_917, T_918) - node T_927 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_928 = cat(T_926, T_927) - node T_930 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_931 = cat(T_918, T_930) - node T_933 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_935 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_937 = cat(T_917, T_918) - node T_938 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_939 = cat(T_937, T_938) - node T_941 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_943 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_944 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_945 = mux(T_944, T_943, UInt<1>("h00")) - node T_946 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_947 = mux(T_946, T_941, T_945) - node T_948 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_949 = mux(T_948, T_939, T_947) - node T_950 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_951 = mux(T_950, T_935, T_949) - node T_952 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_953 = mux(T_952, T_933, T_951) - node T_954 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_955 = mux(T_954, T_931, T_953) - node T_956 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_957 = mux(T_956, T_928, T_955) + oacq_write_block.union <= T_877 + node T_895 = bits(xact.union, 12, 9) + node T_896 = bits(xact.union, 8, 6) + node T_904 = cat(T_895, T_896) + node T_905 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_906 = cat(T_904, T_905) + node T_908 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_909 = cat(T_896, T_908) + node T_911 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_913 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_915 = cat(T_895, T_896) + node T_916 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_917 = cat(T_915, T_916) + node T_919 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_921 = cat(UInt<5>("h01"), UInt<1>("h00")) + node T_922 = eq(UInt<3>("h06"), UInt<3>("h00")) + node T_923 = mux(T_922, T_921, UInt<1>("h00")) + node T_924 = eq(UInt<3>("h05"), UInt<3>("h00")) + node T_925 = mux(T_924, T_919, T_923) + node T_926 = eq(UInt<3>("h04"), UInt<3>("h00")) + node T_927 = mux(T_926, T_917, T_925) + node T_928 = eq(UInt<3>("h03"), UInt<3>("h00")) + node T_929 = mux(T_928, T_913, T_927) + node T_930 = eq(UInt<3>("h02"), UInt<3>("h00")) + node T_931 = mux(T_930, T_911, T_929) + node T_932 = eq(UInt<3>("h01"), UInt<3>("h00")) + node T_933 = mux(T_932, T_909, T_931) + node T_934 = eq(UInt<3>("h00"), UInt<3>("h00")) + node T_935 = mux(T_934, T_906, T_933) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= UInt<1>("h00") - oacq_read_beat.a_type <= UInt<1>("h00") - oacq_read_beat.is_builtin_type <= UInt<1>("h00") - oacq_read_beat.addr_beat <= UInt<1>("h00") - oacq_read_beat.client_xact_id <= UInt<1>("h00") - oacq_read_beat.addr_block <= UInt<1>("h00") + oacq_read_beat is invalid oacq_read_beat.is_builtin_type <= UInt<1>("h01") oacq_read_beat.a_type <= UInt<3>("h00") oacq_read_beat.client_xact_id <= UInt<1>("h01") oacq_read_beat.addr_block <= xact.addr_block oacq_read_beat.addr_beat <= xact.addr_beat oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= T_957 - node T_991 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_992 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_993 = cat(T_991, T_992) - node T_995 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_996 = cat(UInt<3>("h07"), T_995) - node T_998 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1000 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1002 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1003 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1004 = cat(T_1002, T_1003) - node T_1006 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1008 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1009 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_1010 = mux(T_1009, T_1008, UInt<1>("h00")) - node T_1011 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_1012 = mux(T_1011, T_1006, T_1010) - node T_1013 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_1014 = mux(T_1013, T_1004, T_1012) - node T_1015 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_1016 = mux(T_1015, T_1000, T_1014) - node T_1017 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_1018 = mux(T_1017, T_998, T_1016) - node T_1019 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_1020 = mux(T_1019, T_996, T_1018) - node T_1021 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_1022 = mux(T_1021, T_993, T_1020) + oacq_read_beat.union <= T_935 + node T_962 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_963 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_964 = cat(T_962, T_963) + node T_966 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_967 = cat(UInt<3>("h07"), T_966) + node T_969 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_971 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_973 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_974 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_975 = cat(T_973, T_974) + node T_977 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_979 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_980 = eq(UInt<3>("h06"), UInt<3>("h01")) + node T_981 = mux(T_980, T_979, UInt<1>("h00")) + node T_982 = eq(UInt<3>("h05"), UInt<3>("h01")) + node T_983 = mux(T_982, T_977, T_981) + node T_984 = eq(UInt<3>("h04"), UInt<3>("h01")) + node T_985 = mux(T_984, T_975, T_983) + node T_986 = eq(UInt<3>("h03"), UInt<3>("h01")) + node T_987 = mux(T_986, T_971, T_985) + node T_988 = eq(UInt<3>("h02"), UInt<3>("h01")) + node T_989 = mux(T_988, T_969, T_987) + node T_990 = eq(UInt<3>("h01"), UInt<3>("h01")) + node T_991 = mux(T_990, T_967, T_989) + node T_992 = eq(UInt<3>("h00"), UInt<3>("h01")) + node T_993 = mux(T_992, T_964, T_991) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= UInt<1>("h00") - oacq_read_block.a_type <= UInt<1>("h00") - oacq_read_block.is_builtin_type <= UInt<1>("h00") - oacq_read_block.addr_beat <= UInt<1>("h00") - oacq_read_block.client_xact_id <= UInt<1>("h00") - oacq_read_block.addr_block <= UInt<1>("h00") + oacq_read_block is invalid oacq_read_block.is_builtin_type <= UInt<1>("h01") oacq_read_block.a_type <= UInt<3>("h01") oacq_read_block.client_xact_id <= UInt<1>("h01") oacq_read_block.addr_block <= xact.addr_block oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= T_1022 + oacq_read_block.union <= T_993 io.outer.acquire.valid <= UInt<1>("h00") - node T_1047 = eq(state, UInt<1>("h01")) - node T_1048 = eq(state, UInt<2>("h03")) - wire T_1057 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1057 <- oacq_write_block - when subblock_type : - T_1057 <- oacq_write_beat - skip - wire T_1073 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1073 <- oacq_read_block - when subblock_type : - T_1073 <- oacq_read_beat - skip - wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1089 <- T_1073 - when T_1048 : - T_1089 <- T_1057 - skip - wire T_1105 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1105 <- T_1089 - when T_1047 : - T_1105 <- oacq_probe - skip - io.outer.acquire.bits <- T_1105 + node T_1011 = eq(state, UInt<1>("h01")) + node T_1012 = eq(state, UInt<2>("h03")) + node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) + node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) + node T_1029 = mux(T_1012, T_1013, T_1021) + node T_1037 = mux(T_1011, oacq_probe, T_1029) + io.outer.acquire.bits <- T_1037 io.outer.grant.ready <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") - node T_1122 = eq(UInt<3>("h04"), xact.a_type) - node T_1123 = mux(T_1122, UInt<1>("h00"), UInt<2>("h02")) - node T_1124 = eq(UInt<3>("h06"), xact.a_type) - node T_1125 = mux(T_1124, UInt<1>("h00"), T_1123) - node T_1126 = eq(UInt<3>("h05"), xact.a_type) - node T_1127 = mux(T_1126, UInt<2>("h02"), T_1125) - node T_1128 = eq(UInt<3>("h02"), xact.a_type) - node T_1129 = mux(T_1128, UInt<1>("h00"), T_1127) - node T_1130 = eq(UInt<3>("h00"), xact.a_type) - node T_1131 = mux(T_1130, UInt<2>("h02"), T_1129) - node T_1132 = eq(UInt<3>("h03"), xact.a_type) - node T_1133 = mux(T_1132, UInt<1>("h00"), T_1131) - node T_1134 = eq(UInt<3>("h01"), xact.a_type) - node T_1135 = mux(T_1134, UInt<2>("h02"), T_1133) - node T_1136 = eq(UInt<1>("h01"), xact.a_type) - node T_1137 = mux(T_1136, UInt<1>("h00"), UInt<2>("h02")) - node T_1138 = eq(UInt<1>("h00"), xact.a_type) - node T_1139 = mux(T_1138, UInt<1>("h01"), T_1137) - node T_1140 = mux(xact.is_builtin_type, T_1135, T_1139) - wire T_1145 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1145.client_id <= UInt<1>("h00") - T_1145.p_type <= UInt<1>("h00") - T_1145.addr_block <= UInt<1>("h00") - T_1145.client_id <= UInt<1>("h00") - T_1145.p_type <= T_1140 - T_1145.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1145 + node T_1054 = eq(UInt<3>("h04"), xact.a_type) + node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02")) + node T_1056 = eq(UInt<3>("h06"), xact.a_type) + node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055) + node T_1058 = eq(UInt<3>("h05"), xact.a_type) + node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057) + node T_1060 = eq(UInt<3>("h02"), xact.a_type) + node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059) + node T_1062 = eq(UInt<3>("h00"), xact.a_type) + node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061) + node T_1064 = eq(UInt<3>("h03"), xact.a_type) + node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063) + node T_1066 = eq(UInt<3>("h01"), xact.a_type) + node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065) + node T_1068 = eq(UInt<1>("h01"), xact.a_type) + node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02")) + node T_1070 = eq(UInt<1>("h00"), xact.a_type) + node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069) + node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) + wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} + T_1077 is invalid + T_1077.client_id <= UInt<1>("h00") + T_1077.p_type <= T_1072 + T_1077.addr_block <= xact.addr_block + io.inner.probe.bits <- T_1077 io.inner.grant.valid <= UInt<1>("h00") - node T_1171 = eq(UInt<3>("h06"), xact.a_type) - node T_1172 = mux(T_1171, UInt<3>("h01"), UInt<3>("h03")) - node T_1173 = eq(UInt<3>("h05"), xact.a_type) - node T_1174 = mux(T_1173, UInt<3>("h01"), T_1172) - node T_1175 = eq(UInt<3>("h04"), xact.a_type) - node T_1176 = mux(T_1175, UInt<3>("h04"), T_1174) - node T_1177 = eq(UInt<3>("h03"), xact.a_type) - node T_1178 = mux(T_1177, UInt<3>("h03"), T_1176) - node T_1179 = eq(UInt<3>("h02"), xact.a_type) - node T_1180 = mux(T_1179, UInt<3>("h03"), T_1178) - node T_1181 = eq(UInt<3>("h01"), xact.a_type) - node T_1182 = mux(T_1181, UInt<3>("h05"), T_1180) - node T_1183 = eq(UInt<3>("h00"), xact.a_type) - node T_1184 = mux(T_1183, UInt<3>("h04"), T_1182) - node T_1185 = eq(xact.a_type, UInt<1>("h00")) - node T_1188 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1189 = mux(T_1188, UInt<1>("h00"), UInt<1>("h01")) - node T_1190 = mux(T_1185, T_1189, UInt<1>("h01")) - node T_1191 = mux(xact.is_builtin_type, T_1184, T_1190) - wire T_1200 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1200.client_id <= UInt<1>("h00") - T_1200.data <= UInt<1>("h00") - T_1200.g_type <= UInt<1>("h00") - T_1200.is_builtin_type <= UInt<1>("h00") - T_1200.manager_xact_id <= UInt<1>("h00") - T_1200.client_xact_id <= UInt<1>("h00") - T_1200.addr_beat <= UInt<1>("h00") - T_1200.client_id <= xact.client_id - T_1200.is_builtin_type <= xact.is_builtin_type - T_1200.g_type <= T_1191 - T_1200.client_xact_id <= xact.client_xact_id - T_1200.manager_xact_id <= UInt<1>("h01") - T_1200.addr_beat <= UInt<1>("h00") - T_1200.data <= UInt<1>("h00") - io.inner.grant.bits <- T_1200 + node T_1100 = eq(UInt<3>("h06"), xact.a_type) + node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03")) + node T_1102 = eq(UInt<3>("h05"), xact.a_type) + node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101) + node T_1104 = eq(UInt<3>("h04"), xact.a_type) + node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103) + node T_1106 = eq(UInt<3>("h03"), xact.a_type) + node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105) + node T_1108 = eq(UInt<3>("h02"), xact.a_type) + node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107) + node T_1110 = eq(UInt<3>("h01"), xact.a_type) + node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109) + node T_1112 = eq(UInt<3>("h00"), xact.a_type) + node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111) + node T_1114 = eq(xact.a_type, UInt<1>("h00")) + node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01")) + node T_1119 = mux(T_1114, T_1118, UInt<1>("h01")) + node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) + wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} + T_1129 is invalid + T_1129.client_id <= xact.client_id + T_1129.is_builtin_type <= xact.is_builtin_type + T_1129.g_type <= T_1120 + T_1129.client_xact_id <= xact.client_xact_id + T_1129.manager_xact_id <= UInt<1>("h01") + T_1129.addr_beat <= UInt<1>("h00") + T_1129.data <= UInt<1>("h00") + io.inner.grant.bits <- T_1129 io.inner.acquire.ready <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") - node T_1218 = neq(state, UInt<1>("h00")) - node T_1219 = and(T_1218, collect_iacq_data) - node T_1220 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1221 = and(T_1219, T_1220) - node T_1222 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1223 = and(T_1221, T_1222) - node T_1225 = eq(T_1223, UInt<1>("h00")) - node T_1227 = eq(reset, UInt<1>("h00")) - when T_1227 : - node T_1229 = eq(T_1225, UInt<1>("h00")) - when T_1229 : - node T_1231 = eq(reset, UInt<1>("h00")) - when T_1231 : + node T_1140 = neq(state, UInt<1>("h00")) + node T_1141 = and(T_1140, collect_iacq_data) + node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1143 = and(T_1141, T_1142) + node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) + node T_1145 = and(T_1143, T_1144) + node T_1147 = eq(T_1145, UInt<1>("h00")) + node T_1149 = eq(reset, UInt<1>("h00")) + when T_1149 : + node T_1151 = eq(T_1147, UInt<1>("h00")) + when T_1151 : + node T_1153 = eq(reset, UInt<1>("h00")) + when T_1153 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1232 = neq(state, UInt<1>("h00")) - node T_1233 = and(T_1232, collect_iacq_data) - node T_1234 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1235 = and(T_1233, T_1234) - node T_1236 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1237 = and(T_1235, T_1236) - node T_1239 = eq(T_1237, UInt<1>("h00")) - node T_1241 = eq(reset, UInt<1>("h00")) - when T_1241 : - node T_1243 = eq(T_1239, UInt<1>("h00")) - when T_1243 : - node T_1245 = eq(reset, UInt<1>("h00")) - when T_1245 : + node T_1154 = neq(state, UInt<1>("h00")) + node T_1155 = and(T_1154, collect_iacq_data) + node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1157 = and(T_1155, T_1156) + node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) + node T_1159 = and(T_1157, T_1158) + node T_1161 = eq(T_1159, UInt<1>("h00")) + node T_1163 = eq(reset, UInt<1>("h00")) + when T_1163 : + node T_1165 = eq(T_1161, UInt<1>("h00")) + when T_1165 : + node T_1167 = eq(reset, UInt<1>("h00")) + when T_1167 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1246 = eq(state, UInt<1>("h00")) - node T_1247 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1248 = and(T_1246, T_1247) - node T_1250 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1253 : UInt<3>[1] - T_1253[0] <= UInt<3>("h03") - node T_1256 = eq(T_1253[0], io.inner.acquire.bits.a_type) - node T_1258 = or(UInt<1>("h00"), T_1256) - node T_1259 = and(T_1250, T_1258) - node T_1260 = and(T_1248, T_1259) - node T_1262 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1263 = and(T_1260, T_1262) - node T_1265 = eq(T_1263, UInt<1>("h00")) - node T_1267 = eq(reset, UInt<1>("h00")) - when T_1267 : - node T_1269 = eq(T_1265, UInt<1>("h00")) - when T_1269 : - node T_1271 = eq(reset, UInt<1>("h00")) - when T_1271 : + node T_1168 = eq(state, UInt<1>("h00")) + node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1170 = and(T_1168, T_1169) + node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_1175 : UInt<3>[1] + T_1175[0] <= UInt<3>("h03") + node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) + node T_1180 = or(UInt<1>("h00"), T_1178) + node T_1181 = and(T_1172, T_1180) + node T_1182 = and(T_1170, T_1181) + node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) + node T_1185 = and(T_1182, T_1184) + node T_1187 = eq(T_1185, UInt<1>("h00")) + node T_1189 = eq(reset, UInt<1>("h00")) + when T_1189 : + node T_1191 = eq(T_1187, UInt<1>("h00")) + when T_1191 : + node T_1193 = eq(reset, UInt<1>("h00")) + when T_1193 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") skip stop(clk, UInt<1>(1), 1) @@ -3695,38 +2557,40 @@ circuit Top : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1275 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1276 = bits(T_1275, 3, 3) - node T_1278 = dshl(UInt<1>("h01"), T_1276) - node T_1280 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1281 = and(io.inner.acquire.bits.is_builtin_type, T_1280) - node T_1282 = bit(T_1278, 0) - node T_1283 = bit(T_1278, 1) - wire T_1285 : UInt<1>[2] - T_1285[0] <= T_1282 - T_1285[1] <= T_1283 - node T_1290 = subw(UInt<8>("h00"), T_1285[0]) - node T_1292 = subw(UInt<8>("h00"), T_1285[1]) - wire T_1294 : UInt<8>[2] - T_1294[0] <= T_1290 - T_1294[1] <= T_1292 - node T_1298 = cat(T_1294[1], T_1294[0]) - node T_1300 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1301 = and(io.inner.acquire.bits.is_builtin_type, T_1300) - node T_1303 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1304 = and(io.inner.acquire.bits.is_builtin_type, T_1303) - node T_1305 = or(T_1301, T_1304) - node T_1306 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1308 = mux(T_1305, T_1306, UInt<16>("h00")) - node T_1309 = mux(T_1281, T_1298, T_1308) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1309 - node T_1312 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) - node T_1313 = or(iacq_data_valid, T_1312) - node T_1314 = not(iacq_data_valid) - node T_1315 = or(T_1314, T_1312) - node T_1316 = not(T_1315) - node T_1317 = mux(UInt<1>("h01"), T_1313, T_1316) - iacq_data_valid <= T_1317 + node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) + node T_1198 = bits(T_1197, 3, 3) + node T_1200 = dshl(UInt<1>("h01"), T_1198) + node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) + node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) + node T_1204 = bits(T_1200, 0, 0) + node T_1205 = bits(T_1200, 1, 1) + wire T_1207 : UInt<1>[2] + T_1207[0] <= T_1204 + T_1207[1] <= T_1205 + node T_1212 = sub(UInt<8>("h00"), T_1207[0]) + node T_1213 = tail(T_1212, 1) + node T_1215 = sub(UInt<8>("h00"), T_1207[1]) + node T_1216 = tail(T_1215, 1) + wire T_1218 : UInt<8>[2] + T_1218[0] <= T_1213 + T_1218[1] <= T_1216 + node T_1222 = cat(T_1218[1], T_1218[0]) + node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) + node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) + node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) + node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) + node T_1229 = or(T_1225, T_1228) + node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) + node T_1232 = mux(T_1229, T_1230, UInt<16>("h00")) + node T_1233 = mux(T_1203, T_1222, T_1232) + xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 + node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) + node T_1237 = or(iacq_data_valid, T_1236) + node T_1238 = not(iacq_data_valid) + node T_1239 = or(T_1238, T_1236) + node T_1240 = not(T_1239) + node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240) + iacq_data_valid <= T_1241 skip when iacq_data_done : collect_iacq_data <= UInt<1>("h00") @@ -3738,194 +2602,201 @@ circuit Top : pending_ognt_ack <= UInt<1>("h00") skip skip - node T_1321 = eq(UInt<1>("h00"), state) - when T_1321 : + node T_1245 = eq(UInt<1>("h00"), state) + when T_1245 : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact <- io.inner.acquire.bits xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data - node T_1327 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1328 = bits(T_1327, 3, 3) - node T_1330 = dshl(UInt<1>("h01"), T_1328) - node T_1332 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1333 = and(io.inner.acquire.bits.is_builtin_type, T_1332) - node T_1334 = bit(T_1330, 0) - node T_1335 = bit(T_1330, 1) - wire T_1337 : UInt<1>[2] - T_1337[0] <= T_1334 - T_1337[1] <= T_1335 - node T_1342 = subw(UInt<8>("h00"), T_1337[0]) - node T_1344 = subw(UInt<8>("h00"), T_1337[1]) - wire T_1346 : UInt<8>[2] - T_1346[0] <= T_1342 - T_1346[1] <= T_1344 - node T_1350 = cat(T_1346[1], T_1346[0]) - node T_1352 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1353 = and(io.inner.acquire.bits.is_builtin_type, T_1352) - node T_1355 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1356 = and(io.inner.acquire.bits.is_builtin_type, T_1355) - node T_1357 = or(T_1353, T_1356) - node T_1358 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1360 = mux(T_1357, T_1358, UInt<16>("h00")) - node T_1361 = mux(T_1333, T_1350, T_1360) - xact.wmask_buffer[UInt<1>("h00")] <= T_1361 - node T_1363 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1366 : UInt<3>[1] - T_1366[0] <= UInt<3>("h03") - node T_1369 = eq(T_1366[0], io.inner.acquire.bits.a_type) - node T_1371 = or(UInt<1>("h00"), T_1369) - node T_1372 = and(T_1363, T_1371) - collect_iacq_data <= T_1372 - wire T_1377 : UInt<3>[3] - T_1377[0] <= UInt<3>("h02") - T_1377[1] <= UInt<3>("h03") - T_1377[2] <= UInt<3>("h04") - node T_1382 = eq(T_1377[0], io.inner.acquire.bits.a_type) - node T_1383 = eq(T_1377[1], io.inner.acquire.bits.a_type) - node T_1384 = eq(T_1377[2], io.inner.acquire.bits.a_type) - node T_1386 = or(UInt<1>("h00"), T_1382) - node T_1387 = or(T_1386, T_1383) - node T_1388 = or(T_1387, T_1384) - node T_1389 = and(io.inner.acquire.bits.is_builtin_type, T_1388) - node T_1390 = dshl(T_1389, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1390 - node T_1392 = neq(mask_incoherent, UInt<1>("h00")) - when T_1392 : + node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) + node T_1252 = bits(T_1251, 3, 3) + node T_1254 = dshl(UInt<1>("h01"), T_1252) + node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) + node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) + node T_1258 = bits(T_1254, 0, 0) + node T_1259 = bits(T_1254, 1, 1) + wire T_1261 : UInt<1>[2] + T_1261[0] <= T_1258 + T_1261[1] <= T_1259 + node T_1266 = sub(UInt<8>("h00"), T_1261[0]) + node T_1267 = tail(T_1266, 1) + node T_1269 = sub(UInt<8>("h00"), T_1261[1]) + node T_1270 = tail(T_1269, 1) + wire T_1272 : UInt<8>[2] + T_1272[0] <= T_1267 + T_1272[1] <= T_1270 + node T_1276 = cat(T_1272[1], T_1272[0]) + node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) + node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) + node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) + node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) + node T_1283 = or(T_1279, T_1282) + node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) + node T_1286 = mux(T_1283, T_1284, UInt<16>("h00")) + node T_1287 = mux(T_1257, T_1276, T_1286) + xact.wmask_buffer[UInt<1>("h00")] <= T_1287 + node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_1292 : UInt<3>[1] + T_1292[0] <= UInt<3>("h03") + node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) + node T_1297 = or(UInt<1>("h00"), T_1295) + node T_1298 = and(T_1289, T_1297) + collect_iacq_data <= T_1298 + wire T_1303 : UInt<3>[3] + T_1303[0] <= UInt<3>("h02") + T_1303[1] <= UInt<3>("h03") + T_1303[2] <= UInt<3>("h04") + node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) + node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) + node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) + node T_1312 = or(UInt<1>("h00"), T_1308) + node T_1313 = or(T_1312, T_1309) + node T_1314 = or(T_1313, T_1310) + node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) + node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) + iacq_data_valid <= T_1316 + node T_1318 = neq(mask_incoherent, UInt<1>("h00")) + when T_1318 : pending_probes <= mask_incoherent - node T_1393 = bit(mask_incoherent, 0) - node T_1394 = bit(mask_incoherent, 1) - node T_1395 = bit(mask_incoherent, 2) - node T_1396 = bit(mask_incoherent, 3) - node T_1398 = cat(UInt<1>("h00"), T_1394) - node T_1399 = addw(T_1393, T_1398) - node T_1402 = cat(UInt<1>("h00"), T_1396) - node T_1403 = addw(T_1395, T_1402) - node T_1404 = cat(UInt<1>("h00"), T_1403) - node T_1405 = addw(T_1399, T_1404) - release_count <= T_1405 + node T_1319 = bits(mask_incoherent, 0, 0) + node T_1320 = bits(mask_incoherent, 1, 1) + node T_1321 = bits(mask_incoherent, 2, 2) + node T_1322 = bits(mask_incoherent, 3, 3) + node T_1324 = cat(UInt<1>("h00"), T_1320) + node T_1325 = add(T_1319, T_1324) + node T_1326 = tail(T_1325, 1) + node T_1329 = cat(UInt<1>("h00"), T_1322) + node T_1330 = add(T_1321, T_1329) + node T_1331 = tail(T_1330, 1) + node T_1332 = cat(UInt<1>("h00"), T_1331) + node T_1333 = add(T_1326, T_1332) + node T_1334 = tail(T_1333, 1) + release_count <= T_1334 skip - node T_1406 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_1407 = mux(pending_outer_write_, UInt<2>("h03"), T_1406) - node T_1408 = mux(T_1392, UInt<1>("h01"), T_1407) - state <= T_1408 + node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) + node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335) + node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336) + state <= T_1337 skip skip - node T_1409 = eq(UInt<1>("h01"), state) - when T_1409 : - node T_1411 = neq(pending_probes, UInt<1>("h00")) - io.inner.probe.valid <= T_1411 + node T_1338 = eq(UInt<1>("h01"), state) + when T_1338 : + node T_1340 = neq(pending_probes, UInt<1>("h00")) + io.inner.probe.valid <= T_1340 when io.inner.probe.ready : - node T_1413 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_1414 = not(T_1413) - node T_1415 = and(pending_probes, T_1414) - pending_probes <= T_1415 - skip - wire T_1417 : UInt<2>[3] - T_1417[0] <= UInt<1>("h00") - T_1417[1] <= UInt<1>("h01") - T_1417[2] <= UInt<2>("h02") - node T_1422 = eq(T_1417[0], io.inner.release.bits.r_type) - node T_1423 = eq(T_1417[1], io.inner.release.bits.r_type) - node T_1424 = eq(T_1417[2], io.inner.release.bits.r_type) - node T_1426 = or(UInt<1>("h00"), T_1422) - node T_1427 = or(T_1426, T_1423) - node T_1428 = or(T_1427, T_1424) - node T_1430 = eq(T_1428, UInt<1>("h00")) - node T_1431 = or(T_1430, io.outer.acquire.ready) - io.inner.release.ready <= T_1431 + node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00")) + node T_1343 = not(T_1342) + node T_1344 = and(pending_probes, T_1343) + pending_probes <= T_1344 + skip + wire T_1346 : UInt<2>[3] + T_1346[0] <= UInt<1>("h00") + T_1346[1] <= UInt<1>("h01") + T_1346[2] <= UInt<2>("h02") + node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) + node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) + node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) + node T_1355 = or(UInt<1>("h00"), T_1351) + node T_1356 = or(T_1355, T_1352) + node T_1357 = or(T_1356, T_1353) + node T_1359 = eq(T_1357, UInt<1>("h00")) + node T_1360 = or(T_1359, io.outer.acquire.ready) + io.inner.release.ready <= T_1360 when io.inner.release.valid : - wire T_1433 : UInt<2>[3] - T_1433[0] <= UInt<1>("h00") - T_1433[1] <= UInt<1>("h01") - T_1433[2] <= UInt<2>("h02") - node T_1438 = eq(T_1433[0], io.inner.release.bits.r_type) - node T_1439 = eq(T_1433[1], io.inner.release.bits.r_type) - node T_1440 = eq(T_1433[2], io.inner.release.bits.r_type) - node T_1442 = or(UInt<1>("h00"), T_1438) - node T_1443 = or(T_1442, T_1439) - node T_1444 = or(T_1443, T_1440) - when T_1444 : + wire T_1362 : UInt<2>[3] + T_1362[0] <= UInt<1>("h00") + T_1362[1] <= UInt<1>("h01") + T_1362[2] <= UInt<2>("h02") + node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) + node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) + node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) + node T_1371 = or(UInt<1>("h00"), T_1367) + node T_1372 = or(T_1371, T_1368) + node T_1373 = or(T_1372, T_1369) + when T_1373 : io.outer.acquire.valid <= UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") - node T_1448 = subw(release_count, UInt<1>("h01")) - release_count <= T_1448 - node T_1450 = eq(release_count, UInt<1>("h01")) - when T_1450 : - node T_1451 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1452 = mux(pending_outer_write, UInt<2>("h03"), T_1451) - state <= T_1452 + node T_1377 = sub(release_count, UInt<1>("h01")) + node T_1378 = tail(T_1377, 1) + release_count <= T_1378 + node T_1380 = eq(release_count, UInt<1>("h01")) + when T_1380 : + node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381) + state <= T_1382 skip skip skip skip - node T_1454 = eq(T_1444, UInt<1>("h00")) - when T_1454 : - node T_1456 = subw(release_count, UInt<1>("h01")) - release_count <= T_1456 - node T_1458 = eq(release_count, UInt<1>("h01")) - when T_1458 : - node T_1459 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1460 = mux(pending_outer_write, UInt<2>("h03"), T_1459) - state <= T_1460 + node T_1384 = eq(T_1373, UInt<1>("h00")) + when T_1384 : + node T_1386 = sub(release_count, UInt<1>("h01")) + node T_1387 = tail(T_1386, 1) + release_count <= T_1387 + node T_1389 = eq(release_count, UInt<1>("h01")) + when T_1389 : + node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390) + state <= T_1391 skip skip skip skip - node T_1461 = eq(UInt<2>("h03"), state) - when T_1461 : - node T_1463 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_1465 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1466 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1467 = bit(T_1466, 0) - node T_1468 = or(T_1465, T_1467) - node T_1469 = and(T_1463, T_1468) - io.outer.acquire.valid <= T_1469 + node T_1392 = eq(UInt<2>("h03"), state) + when T_1392 : + node T_1394 = eq(pending_ognt_ack, UInt<1>("h00")) + node T_1396 = eq(collect_iacq_data, UInt<1>("h00")) + node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) + node T_1398 = bits(T_1397, 0, 0) + node T_1399 = or(T_1396, T_1398) + node T_1400 = and(T_1394, T_1399) + io.outer.acquire.valid <= T_1400 when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") - node T_1471 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state <= T_1471 + node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) + state <= T_1402 skip skip - node T_1472 = eq(UInt<2>("h02"), state) - when T_1472 : - node T_1474 = eq(pending_ognt_ack, UInt<1>("h00")) - io.outer.acquire.valid <= T_1474 - node T_1475 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1475 : + node T_1403 = eq(UInt<2>("h02"), state) + when T_1403 : + node T_1405 = eq(pending_ognt_ack, UInt<1>("h00")) + io.outer.acquire.valid <= T_1405 + node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) + when T_1406 : state <= UInt<3>("h05") skip skip - node T_1476 = eq(UInt<3>("h05"), state) - when T_1476 : + node T_1407 = eq(UInt<3>("h05"), state) + when T_1407 : io.outer.grant.ready <= io.inner.grant.ready io.inner.grant.valid <= io.outer.grant.valid when ignt_data_done : - node T_1479 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1481 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1482 = and(io.inner.grant.bits.is_builtin_type, T_1481) - node T_1484 = eq(T_1482, UInt<1>("h00")) - node T_1485 = and(T_1479, T_1484) - node T_1486 = mux(T_1485, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1486 + node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) + node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) + node T_1415 = eq(T_1413, UInt<1>("h00")) + node T_1416 = and(T_1410, T_1415) + node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00")) + state <= T_1417 skip skip - node T_1487 = eq(UInt<3>("h04"), state) - when T_1487 : + node T_1418 = eq(UInt<3>("h04"), state) + when T_1418 : io.inner.grant.valid <= UInt<1>("h01") when io.inner.grant.ready : - node T_1491 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1493 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1494 = and(io.inner.grant.bits.is_builtin_type, T_1493) - node T_1496 = eq(T_1494, UInt<1>("h00")) - node T_1497 = and(T_1491, T_1496) - node T_1498 = mux(T_1497, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1498 + node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) + node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) + node T_1427 = eq(T_1425, UInt<1>("h00")) + node T_1428 = and(T_1422, T_1427) + node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00")) + state <= T_1429 skip skip - node T_1499 = eq(UInt<3>("h06"), state) - when T_1499 : + node T_1430 = eq(UInt<3>("h06"), state) + when T_1430 : io.inner.finish.ready <= UInt<1>("h01") when io.inner.finish.valid : state <= UInt<1>("h00") @@ -3937,98 +2808,73 @@ circuit Top : input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - io.has_release_match <= UInt<1>("h00") - io.has_acquire_match <= UInt<1>("h00") - io.has_acquire_conflict <= UInt<1>("h00") - io.outer.grant.ready <= UInt<1>("h00") - io.outer.acquire.bits.data <= UInt<1>("h00") - io.outer.acquire.bits.union <= UInt<1>("h00") - io.outer.acquire.bits.a_type <= UInt<1>("h00") - io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.outer.acquire.bits.addr_beat <= UInt<1>("h00") - io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") - io.outer.acquire.bits.addr_block <= UInt<1>("h00") - io.outer.acquire.valid <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.probe.bits.client_id <= UInt<1>("h00") - io.inner.probe.bits.p_type <= UInt<1>("h00") - io.inner.probe.bits.addr_block <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - io.inner.grant.bits.client_id <= UInt<1>("h00") - io.inner.grant.bits.data <= UInt<1>("h00") - io.inner.grant.bits.g_type <= UInt<1>("h00") - io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") - io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") - io.inner.grant.bits.client_xact_id <= UInt<1>("h00") - io.inner.grant.bits.addr_beat <= UInt<1>("h00") - io.inner.grant.valid <= UInt<1>("h00") - io.inner.acquire.ready <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk, UInt<1>("h00"), xact + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk wire coh : {sharers : UInt<1>} + coh is invalid coh.sharers <= UInt<1>("h00") - coh.sharers <= UInt<1>("h00") - node T_304 = neq(state, UInt<1>("h00")) - node T_305 = and(T_304, xact.is_builtin_type) - wire T_310 : UInt<3>[3] - T_310[0] <= UInt<3>("h04") - T_310[1] <= UInt<3>("h05") - T_310[2] <= UInt<3>("h06") - node T_315 = eq(T_310[0], xact.a_type) - node T_316 = eq(T_310[1], xact.a_type) - node T_317 = eq(T_310[2], xact.a_type) - node T_319 = or(UInt<1>("h00"), T_315) + node T_303 = neq(state, UInt<1>("h00")) + node T_304 = and(T_303, xact.is_builtin_type) + wire T_309 : UInt<3>[3] + T_309[0] <= UInt<3>("h04") + T_309[1] <= UInt<3>("h05") + T_309[2] <= UInt<3>("h06") + node T_314 = eq(T_309[0], xact.a_type) + node T_315 = eq(T_309[1], xact.a_type) + node T_316 = eq(T_309[2], xact.a_type) + node T_318 = or(UInt<1>("h00"), T_314) + node T_319 = or(T_318, T_315) node T_320 = or(T_319, T_316) - node T_321 = or(T_320, T_317) - node T_322 = and(T_305, T_321) - node T_324 = eq(T_322, UInt<1>("h00")) - node T_326 = eq(reset, UInt<1>("h00")) - when T_326 : - node T_328 = eq(T_324, UInt<1>("h00")) - when T_328 : - node T_330 = eq(reset, UInt<1>("h00")) - when T_330 : + node T_321 = and(T_304, T_320) + node T_323 = eq(T_321, UInt<1>("h00")) + node T_325 = eq(reset, UInt<1>("h00")) + when T_325 : + node T_327 = eq(T_323, UInt<1>("h00")) + when T_327 : + node T_329 = eq(reset, UInt<1>("h00")) + when T_329 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") skip stop(clk, UInt<1>(1), 1) skip skip - reg release_count : UInt<1>, clk, reset, UInt<1>("h00") - reg pending_probes : UInt<1>, clk, reset, UInt<1>("h00") - node T_335 = bit(pending_probes, 0) - wire T_337 : UInt<1>[1] - T_337[0] <= T_335 - node T_342 = asUInt(asSInt(UInt<1>("h01"))) - node T_345 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) - node T_346 = or(T_342, T_345) - node T_347 = not(T_342) - node T_348 = or(T_347, T_345) - node T_349 = not(T_348) - node mask_self = mux(UInt<1>("h00"), T_346, T_349) - node T_351 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_351) - reg collect_iacq_data : UInt<1>, clk, reset, UInt<1>("h00") - reg iacq_data_valid : UInt<4>, clk, reset, UInt<4>("h00") - node T_357 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_360 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_363 : UInt<3>[1] - T_363[0] <= UInt<3>("h03") - node T_366 = eq(T_363[0], io.inner.acquire.bits.a_type) - node T_368 = or(UInt<1>("h00"), T_366) - node T_369 = and(T_360, T_368) - node T_370 = and(T_357, T_369) - reg T_372 : UInt<2>, clk, reset, UInt<2>("h00") - when T_370 : - node T_374 = eq(T_372, UInt<2>("h03")) - node T_376 = and(UInt<1>("h00"), T_374) - node T_379 = addw(T_372, UInt<1>("h01")) - node T_380 = mux(T_376, UInt<1>("h00"), T_379) - T_372 <= T_380 - skip - node T_381 = and(T_370, T_374) - node T_382 = mux(T_369, T_372, UInt<1>("h00")) - node iacq_data_done = mux(T_369, T_381, T_357) + reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_334 = bits(pending_probes, 0, 0) + wire T_336 : UInt<1>[1] + T_336[0] <= T_334 + node T_341 = asUInt(asSInt(UInt<1>("h01"))) + node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) + node T_345 = or(T_341, T_344) + node T_346 = not(T_341) + node T_347 = or(T_346, T_344) + node T_348 = not(T_347) + node mask_self = mux(UInt<1>("h00"), T_345, T_348) + node T_350 = not(io.incoherent[0]) + node mask_incoherent = and(mask_self, T_350) + reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) + node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_362 : UInt<3>[1] + T_362[0] <= UInt<3>("h03") + node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) + node T_367 = or(UInt<1>("h00"), T_365) + node T_368 = and(T_359, T_367) + node T_369 = and(T_356, T_368) + reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_369 : + node T_373 = eq(T_371, UInt<2>("h03")) + node T_375 = and(UInt<1>("h00"), T_373) + node T_378 = add(T_371, UInt<1>("h01")) + node T_379 = tail(T_378, 1) + node T_380 = mux(T_375, UInt<1>("h00"), T_379) + T_371 <= T_380 + skip + node T_381 = and(T_369, T_373) + node T_382 = mux(T_368, T_371, UInt<1>("h00")) + node iacq_data_done = mux(T_368, T_381, T_356) node T_384 = and(io.inner.release.ready, io.inner.release.valid) wire T_388 : UInt<2>[3] T_388[0] <= UInt<1>("h00") @@ -4042,577 +2888,523 @@ circuit Top : node T_399 = or(T_398, T_395) node T_400 = and(UInt<1>("h01"), T_399) node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk, reset, UInt<2>("h00") + reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) when T_401 : node T_405 = eq(T_403, UInt<2>("h03")) node T_407 = and(UInt<1>("h00"), T_405) - node T_410 = addw(T_403, UInt<1>("h01")) - node T_411 = mux(T_407, UInt<1>("h00"), T_410) - T_403 <= T_411 - skip - node T_412 = and(T_401, T_405) - node T_413 = mux(T_400, T_403, UInt<1>("h00")) - node irel_data_done = mux(T_400, T_412, T_384) - node T_416 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_420 : UInt<3>[1] - T_420[0] <= UInt<3>("h05") - node T_423 = eq(T_420[0], io.inner.grant.bits.g_type) - node T_425 = or(UInt<1>("h00"), T_423) - wire T_427 : UInt<1>[2] - T_427[0] <= UInt<1>("h00") - T_427[1] <= UInt<1>("h01") - node T_431 = eq(T_427[0], io.inner.grant.bits.g_type) - node T_432 = eq(T_427[1], io.inner.grant.bits.g_type) - node T_434 = or(UInt<1>("h00"), T_431) - node T_435 = or(T_434, T_432) - node T_436 = mux(io.inner.grant.bits.is_builtin_type, T_425, T_435) - node T_437 = and(UInt<1>("h01"), T_436) - node T_438 = and(T_416, T_437) - reg T_440 : UInt<2>, clk, reset, UInt<2>("h00") - when T_438 : - node T_442 = eq(T_440, UInt<2>("h03")) - node T_444 = and(UInt<1>("h00"), T_442) - node T_447 = addw(T_440, UInt<1>("h01")) - node T_448 = mux(T_444, UInt<1>("h00"), T_447) - T_440 <= T_448 - skip - node T_449 = and(T_438, T_442) - node ignt_data_cnt = mux(T_437, T_440, UInt<1>("h00")) - node ignt_data_done = mux(T_437, T_449, T_416) - node T_453 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_455 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) - wire T_458 : UInt<3>[1] - T_458[0] <= UInt<3>("h03") - node T_461 = eq(T_458[0], io.outer.acquire.bits.a_type) - node T_463 = or(UInt<1>("h00"), T_461) - node T_464 = and(T_455, T_463) - node T_465 = and(T_453, T_464) - reg T_467 : UInt<2>, clk, reset, UInt<2>("h00") - when T_465 : - node T_469 = eq(T_467, UInt<2>("h03")) - node T_471 = and(UInt<1>("h00"), T_469) - node T_474 = addw(T_467, UInt<1>("h01")) - node T_475 = mux(T_471, UInt<1>("h00"), T_474) - T_467 <= T_475 - skip - node T_476 = and(T_465, T_469) - node oacq_data_cnt = mux(T_464, T_467, UInt<1>("h00")) - node oacq_data_done = mux(T_464, T_476, T_453) - node T_479 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_484 : UInt<3>[1] - T_484[0] <= UInt<3>("h05") - node T_487 = eq(T_484[0], io.outer.grant.bits.g_type) - node T_489 = or(UInt<1>("h00"), T_487) - wire T_491 : UInt<1>[1] - T_491[0] <= UInt<1>("h00") - node T_494 = eq(T_491[0], io.outer.grant.bits.g_type) - node T_496 = or(UInt<1>("h00"), T_494) - node T_497 = mux(io.outer.grant.bits.is_builtin_type, T_489, T_496) - node T_498 = and(UInt<1>("h01"), T_497) - node T_499 = and(T_479, T_498) - reg T_501 : UInt<2>, clk, reset, UInt<2>("h00") - when T_499 : - node T_503 = eq(T_501, UInt<2>("h03")) - node T_505 = and(UInt<1>("h00"), T_503) - node T_508 = addw(T_501, UInt<1>("h01")) - node T_509 = mux(T_505, UInt<1>("h00"), T_508) - T_501 <= T_509 - skip - node T_510 = and(T_499, T_503) - node T_511 = mux(T_498, T_501, UInt<1>("h00")) - node ognt_data_done = mux(T_498, T_510, T_479) - reg pending_ognt_ack : UInt<1>, clk, reset, UInt<1>("h00") - wire T_519 : UInt<3>[3] - T_519[0] <= UInt<3>("h02") - T_519[1] <= UInt<3>("h03") - T_519[2] <= UInt<3>("h04") - node T_524 = eq(T_519[0], xact.a_type) - node T_525 = eq(T_519[1], xact.a_type) - node T_526 = eq(T_519[2], xact.a_type) - node T_528 = or(UInt<1>("h00"), T_524) - node T_529 = or(T_528, T_525) - node T_530 = or(T_529, T_526) - node pending_outer_write = and(xact.is_builtin_type, T_530) - wire T_536 : UInt<3>[3] - T_536[0] <= UInt<3>("h02") - T_536[1] <= UInt<3>("h03") - T_536[2] <= UInt<3>("h04") - node T_541 = eq(T_536[0], io.inner.acquire.bits.a_type) - node T_542 = eq(T_536[1], io.inner.acquire.bits.a_type) - node T_543 = eq(T_536[2], io.inner.acquire.bits.a_type) - node T_545 = or(UInt<1>("h00"), T_541) - node T_546 = or(T_545, T_542) - node T_547 = or(T_546, T_543) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_547) - wire T_552 : UInt<3>[2] - T_552[0] <= UInt<3>("h05") - T_552[1] <= UInt<3>("h04") - node T_556 = eq(T_552[0], io.inner.grant.bits.g_type) - node T_557 = eq(T_552[1], io.inner.grant.bits.g_type) - node T_559 = or(UInt<1>("h00"), T_556) - node T_560 = or(T_559, T_557) - wire T_562 : UInt<1>[2] - T_562[0] <= UInt<1>("h00") - T_562[1] <= UInt<1>("h01") - node T_566 = eq(T_562[0], io.inner.grant.bits.g_type) - node T_567 = eq(T_562[1], io.inner.grant.bits.g_type) - node T_569 = or(UInt<1>("h00"), T_566) - node T_570 = or(T_569, T_567) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_560, T_570) - node T_590 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) - node T_591 = mux(T_590, UInt<3>("h01"), UInt<3>("h03")) - node T_592 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) - node T_593 = mux(T_592, UInt<3>("h01"), T_591) - node T_594 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h04"), T_593) - node T_596 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h03"), T_595) - node T_598 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h03"), T_597) - node T_600 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h05"), T_599) - node T_602 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h04"), T_601) - node T_604 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) - node T_607 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_608 = mux(T_607, UInt<1>("h00"), UInt<1>("h01")) - node T_609 = mux(T_604, T_608, UInt<1>("h01")) - node T_610 = mux(io.inner.acquire.bits.is_builtin_type, T_603, T_609) - wire T_619 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_619.client_id <= UInt<1>("h00") - T_619.data <= UInt<1>("h00") - T_619.g_type <= UInt<1>("h00") - T_619.is_builtin_type <= UInt<1>("h00") - T_619.manager_xact_id <= UInt<1>("h00") - T_619.client_xact_id <= UInt<1>("h00") - T_619.addr_beat <= UInt<1>("h00") - T_619.client_id <= io.inner.acquire.bits.client_id - T_619.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_619.g_type <= T_610 - T_619.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_619.manager_xact_id <= UInt<2>("h02") - T_619.addr_beat <= UInt<1>("h00") - T_619.data <= UInt<1>("h00") - wire T_637 : UInt<3>[2] - T_637[0] <= UInt<3>("h05") - T_637[1] <= UInt<3>("h04") - node T_641 = eq(T_637[0], T_619.g_type) - node T_642 = eq(T_637[1], T_619.g_type) - node T_644 = or(UInt<1>("h00"), T_641) - node T_645 = or(T_644, T_642) - wire T_647 : UInt<1>[2] - T_647[0] <= UInt<1>("h00") - T_647[1] <= UInt<1>("h01") - node T_651 = eq(T_647[0], T_619.g_type) - node T_652 = eq(T_647[1], T_619.g_type) - node T_654 = or(UInt<1>("h00"), T_651) - node T_655 = or(T_654, T_652) - node pending_outer_read_ = mux(T_619.is_builtin_type, T_645, T_655) - wire T_661 : UInt<3>[3] - T_661[0] <= UInt<3>("h02") - T_661[1] <= UInt<3>("h00") - T_661[2] <= UInt<3>("h04") - node T_666 = eq(T_661[0], xact.a_type) - node T_667 = eq(T_661[1], xact.a_type) - node T_668 = eq(T_661[2], xact.a_type) - node T_670 = or(UInt<1>("h00"), T_666) - node T_671 = or(T_670, T_667) - node T_672 = or(T_671, T_668) - node subblock_type = and(xact.is_builtin_type, T_672) - node T_674 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_675 = neq(state, UInt<1>("h00")) - node T_676 = and(T_674, T_675) - node T_678 = eq(collect_iacq_data, UInt<1>("h00")) - node T_679 = and(T_676, T_678) - io.has_acquire_conflict <= T_679 - node T_680 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_681 = and(T_680, collect_iacq_data) - io.has_acquire_match <= T_681 - node T_682 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_684 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) - node T_685 = and(T_682, T_684) - node T_686 = eq(state, UInt<1>("h01")) - node T_687 = and(T_685, T_686) - io.has_release_match <= T_687 - node T_692 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_698 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_410 = add(T_403, UInt<1>("h01")) + node T_411 = tail(T_410, 1) + node T_412 = mux(T_407, UInt<1>("h00"), T_411) + T_403 <= T_412 + skip + node T_413 = and(T_401, T_405) + node T_414 = mux(T_400, T_403, UInt<1>("h00")) + node irel_data_done = mux(T_400, T_413, T_384) + node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) + wire T_421 : UInt<3>[1] + T_421[0] <= UInt<3>("h05") + node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) + node T_426 = or(UInt<1>("h00"), T_424) + wire T_428 : UInt<1>[2] + T_428[0] <= UInt<1>("h00") + T_428[1] <= UInt<1>("h01") + node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) + node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) + node T_435 = or(UInt<1>("h00"), T_432) + node T_436 = or(T_435, T_433) + node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) + node T_438 = and(UInt<1>("h01"), T_437) + node T_439 = and(T_417, T_438) + reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_439 : + node T_443 = eq(T_441, UInt<2>("h03")) + node T_445 = and(UInt<1>("h00"), T_443) + node T_448 = add(T_441, UInt<1>("h01")) + node T_449 = tail(T_448, 1) + node T_450 = mux(T_445, UInt<1>("h00"), T_449) + T_441 <= T_450 + skip + node T_451 = and(T_439, T_443) + node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00")) + node ignt_data_done = mux(T_438, T_451, T_417) + node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) + wire T_460 : UInt<3>[1] + T_460[0] <= UInt<3>("h03") + node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) + node T_465 = or(UInt<1>("h00"), T_463) + node T_466 = and(T_457, T_465) + node T_467 = and(T_455, T_466) + reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_467 : + node T_471 = eq(T_469, UInt<2>("h03")) + node T_473 = and(UInt<1>("h00"), T_471) + node T_476 = add(T_469, UInt<1>("h01")) + node T_477 = tail(T_476, 1) + node T_478 = mux(T_473, UInt<1>("h00"), T_477) + T_469 <= T_478 + skip + node T_479 = and(T_467, T_471) + node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00")) + node oacq_data_done = mux(T_466, T_479, T_455) + node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_487 : UInt<3>[1] + T_487[0] <= UInt<3>("h05") + node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) + node T_492 = or(UInt<1>("h00"), T_490) + wire T_494 : UInt<1>[1] + T_494[0] <= UInt<1>("h00") + node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) + node T_499 = or(UInt<1>("h00"), T_497) + node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) + node T_501 = and(UInt<1>("h01"), T_500) + node T_502 = and(T_482, T_501) + reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_502 : + node T_506 = eq(T_504, UInt<2>("h03")) + node T_508 = and(UInt<1>("h00"), T_506) + node T_511 = add(T_504, UInt<1>("h01")) + node T_512 = tail(T_511, 1) + node T_513 = mux(T_508, UInt<1>("h00"), T_512) + T_504 <= T_513 + skip + node T_514 = and(T_502, T_506) + node T_515 = mux(T_501, T_504, UInt<1>("h00")) + node ognt_data_done = mux(T_501, T_514, T_482) + reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + wire T_523 : UInt<3>[3] + T_523[0] <= UInt<3>("h02") + T_523[1] <= UInt<3>("h03") + T_523[2] <= UInt<3>("h04") + node T_528 = eq(T_523[0], xact.a_type) + node T_529 = eq(T_523[1], xact.a_type) + node T_530 = eq(T_523[2], xact.a_type) + node T_532 = or(UInt<1>("h00"), T_528) + node T_533 = or(T_532, T_529) + node T_534 = or(T_533, T_530) + node pending_outer_write = and(xact.is_builtin_type, T_534) + wire T_540 : UInt<3>[3] + T_540[0] <= UInt<3>("h02") + T_540[1] <= UInt<3>("h03") + T_540[2] <= UInt<3>("h04") + node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) + node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) + node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) + node T_549 = or(UInt<1>("h00"), T_545) + node T_550 = or(T_549, T_546) + node T_551 = or(T_550, T_547) + node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) + wire T_556 : UInt<3>[2] + T_556[0] <= UInt<3>("h05") + T_556[1] <= UInt<3>("h04") + node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) + node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) + node T_563 = or(UInt<1>("h00"), T_560) + node T_564 = or(T_563, T_561) + wire T_566 : UInt<1>[2] + T_566[0] <= UInt<1>("h00") + T_566[1] <= UInt<1>("h01") + node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) + node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) + node T_573 = or(UInt<1>("h00"), T_570) + node T_574 = or(T_573, T_571) + node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) + node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) + node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03")) + node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) + node T_597 = mux(T_596, UInt<3>("h01"), T_595) + node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) + node T_599 = mux(T_598, UInt<3>("h04"), T_597) + node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) + node T_601 = mux(T_600, UInt<3>("h03"), T_599) + node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) + node T_603 = mux(T_602, UInt<3>("h03"), T_601) + node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) + node T_605 = mux(T_604, UInt<3>("h05"), T_603) + node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) + node T_607 = mux(T_606, UInt<3>("h04"), T_605) + node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) + node T_611 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01")) + node T_613 = mux(T_608, T_612, UInt<1>("h01")) + node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) + wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} + T_623 is invalid + T_623.client_id <= io.inner.acquire.bits.client_id + T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type + T_623.g_type <= T_614 + T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id + T_623.manager_xact_id <= UInt<2>("h02") + T_623.addr_beat <= UInt<1>("h00") + T_623.data <= UInt<1>("h00") + wire T_634 : UInt<3>[2] + T_634[0] <= UInt<3>("h05") + T_634[1] <= UInt<3>("h04") + node T_638 = eq(T_634[0], T_623.g_type) + node T_639 = eq(T_634[1], T_623.g_type) + node T_641 = or(UInt<1>("h00"), T_638) + node T_642 = or(T_641, T_639) + wire T_644 : UInt<1>[2] + T_644[0] <= UInt<1>("h00") + T_644[1] <= UInt<1>("h01") + node T_648 = eq(T_644[0], T_623.g_type) + node T_649 = eq(T_644[1], T_623.g_type) + node T_651 = or(UInt<1>("h00"), T_648) + node T_652 = or(T_651, T_649) + node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) + wire T_658 : UInt<3>[3] + T_658[0] <= UInt<3>("h02") + T_658[1] <= UInt<3>("h00") + T_658[2] <= UInt<3>("h04") + node T_663 = eq(T_658[0], xact.a_type) + node T_664 = eq(T_658[1], xact.a_type) + node T_665 = eq(T_658[2], xact.a_type) + node T_667 = or(UInt<1>("h00"), T_663) + node T_668 = or(T_667, T_664) + node T_669 = or(T_668, T_665) + node subblock_type = and(xact.is_builtin_type, T_669) + node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) + node T_672 = neq(state, UInt<1>("h00")) + node T_673 = and(T_671, T_672) + node T_675 = eq(collect_iacq_data, UInt<1>("h00")) + node T_676 = and(T_673, T_675) + io.has_acquire_conflict <= T_676 + node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) + node T_678 = and(T_677, collect_iacq_data) + io.has_acquire_match <= T_678 + node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) + node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) + node T_682 = and(T_679, T_681) + node T_683 = eq(state, UInt<1>("h01")) + node T_684 = and(T_682, T_683) + io.has_release_match <= T_684 + node T_689 = asUInt(asSInt(UInt<16>("h0ffff"))) + node T_695 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_696 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_697 = cat(T_695, T_696) node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_700 = cat(T_698, T_699) - node T_702 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_703 = cat(UInt<3>("h07"), T_702) - node T_705 = cat(T_692, UInt<1>("h01")) - node T_707 = cat(T_692, UInt<1>("h01")) - node T_709 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_710 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_711 = cat(T_709, T_710) - node T_713 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_715 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_716 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_717 = mux(T_716, T_715, UInt<1>("h00")) - node T_718 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_719 = mux(T_718, T_713, T_717) - node T_720 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_721 = mux(T_720, T_711, T_719) - node T_722 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_723 = mux(T_722, T_707, T_721) - node T_724 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_725 = mux(T_724, T_705, T_723) - node T_726 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_727 = mux(T_726, T_703, T_725) - node T_728 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_729 = mux(T_728, T_700, T_727) + node T_700 = cat(UInt<3>("h07"), T_699) + node T_702 = cat(T_689, UInt<1>("h01")) + node T_704 = cat(T_689, UInt<1>("h01")) + node T_706 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_707 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_708 = cat(T_706, T_707) + node T_710 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_712 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_713 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_714 = mux(T_713, T_712, UInt<1>("h00")) + node T_715 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_716 = mux(T_715, T_710, T_714) + node T_717 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_718 = mux(T_717, T_708, T_716) + node T_719 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_720 = mux(T_719, T_704, T_718) + node T_721 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_722 = mux(T_721, T_702, T_720) + node T_723 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_724 = mux(T_723, T_700, T_722) + node T_725 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_726 = mux(T_725, T_697, T_724) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe.data <= UInt<1>("h00") - oacq_probe.union <= UInt<1>("h00") - oacq_probe.a_type <= UInt<1>("h00") - oacq_probe.is_builtin_type <= UInt<1>("h00") - oacq_probe.addr_beat <= UInt<1>("h00") - oacq_probe.client_xact_id <= UInt<1>("h00") - oacq_probe.addr_block <= UInt<1>("h00") + oacq_probe is invalid oacq_probe.is_builtin_type <= UInt<1>("h01") oacq_probe.a_type <= UInt<3>("h03") oacq_probe.client_xact_id <= UInt<2>("h02") oacq_probe.addr_block <= io.inner.release.bits.addr_block oacq_probe.addr_beat <= io.inner.release.bits.addr_beat oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_729 - node T_754 = bits(xact.union, 12, 9) - node T_755 = bits(T_754, 3, 3) - node T_757 = dshl(UInt<1>("h01"), T_755) - node T_759 = eq(xact.a_type, UInt<3>("h04")) - node T_760 = and(xact.is_builtin_type, T_759) - node T_761 = bit(T_757, 0) - node T_762 = bit(T_757, 1) - wire T_764 : UInt<1>[2] - T_764[0] <= T_761 - T_764[1] <= T_762 - node T_769 = subw(UInt<8>("h00"), T_764[0]) - node T_771 = subw(UInt<8>("h00"), T_764[1]) - wire T_773 : UInt<8>[2] - T_773[0] <= T_769 - T_773[1] <= T_771 - node T_777 = cat(T_773[1], T_773[0]) - node T_779 = eq(xact.a_type, UInt<3>("h03")) - node T_780 = and(xact.is_builtin_type, T_779) - node T_782 = eq(xact.a_type, UInt<3>("h02")) - node T_783 = and(xact.is_builtin_type, T_782) - node T_784 = or(T_780, T_783) - node T_785 = bits(xact.union, 16, 1) - node T_787 = mux(T_784, T_785, UInt<16>("h00")) - node T_788 = mux(T_760, T_777, T_787) - node T_796 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_797 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_798 = cat(T_796, T_797) + oacq_probe.union <= T_726 + node T_744 = bits(xact.union, 12, 9) + node T_745 = bits(T_744, 3, 3) + node T_747 = dshl(UInt<1>("h01"), T_745) + node T_749 = eq(xact.a_type, UInt<3>("h04")) + node T_750 = and(xact.is_builtin_type, T_749) + node T_751 = bits(T_747, 0, 0) + node T_752 = bits(T_747, 1, 1) + wire T_754 : UInt<1>[2] + T_754[0] <= T_751 + T_754[1] <= T_752 + node T_759 = sub(UInt<8>("h00"), T_754[0]) + node T_760 = tail(T_759, 1) + node T_762 = sub(UInt<8>("h00"), T_754[1]) + node T_763 = tail(T_762, 1) + wire T_765 : UInt<8>[2] + T_765[0] <= T_760 + T_765[1] <= T_763 + node T_769 = cat(T_765[1], T_765[0]) + node T_771 = eq(xact.a_type, UInt<3>("h03")) + node T_772 = and(xact.is_builtin_type, T_771) + node T_774 = eq(xact.a_type, UInt<3>("h02")) + node T_775 = and(xact.is_builtin_type, T_774) + node T_776 = or(T_772, T_775) + node T_777 = bits(xact.union, 16, 1) + node T_779 = mux(T_776, T_777, UInt<16>("h00")) + node T_780 = mux(T_750, T_769, T_779) + node T_788 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_789 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_790 = cat(T_788, T_789) + node T_792 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_793 = cat(UInt<3>("h07"), T_792) + node T_795 = cat(T_780, UInt<1>("h01")) + node T_797 = cat(T_780, UInt<1>("h01")) + node T_799 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_801 = cat(UInt<3>("h07"), T_800) - node T_803 = cat(T_788, UInt<1>("h01")) - node T_805 = cat(T_788, UInt<1>("h01")) - node T_807 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_808 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_809 = cat(T_807, T_808) - node T_811 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_813 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_814 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_815 = mux(T_814, T_813, UInt<1>("h00")) - node T_816 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_817 = mux(T_816, T_811, T_815) - node T_818 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_819 = mux(T_818, T_809, T_817) - node T_820 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_821 = mux(T_820, T_805, T_819) - node T_822 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_823 = mux(T_822, T_803, T_821) - node T_824 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_825 = mux(T_824, T_801, T_823) - node T_826 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_827 = mux(T_826, T_798, T_825) + node T_801 = cat(T_799, T_800) + node T_803 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_805 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_806 = eq(UInt<3>("h06"), UInt<3>("h02")) + node T_807 = mux(T_806, T_805, UInt<1>("h00")) + node T_808 = eq(UInt<3>("h05"), UInt<3>("h02")) + node T_809 = mux(T_808, T_803, T_807) + node T_810 = eq(UInt<3>("h04"), UInt<3>("h02")) + node T_811 = mux(T_810, T_801, T_809) + node T_812 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_813 = mux(T_812, T_797, T_811) + node T_814 = eq(UInt<3>("h02"), UInt<3>("h02")) + node T_815 = mux(T_814, T_795, T_813) + node T_816 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_817 = mux(T_816, T_793, T_815) + node T_818 = eq(UInt<3>("h00"), UInt<3>("h02")) + node T_819 = mux(T_818, T_790, T_817) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat.data <= UInt<1>("h00") - oacq_write_beat.union <= UInt<1>("h00") - oacq_write_beat.a_type <= UInt<1>("h00") - oacq_write_beat.is_builtin_type <= UInt<1>("h00") - oacq_write_beat.addr_beat <= UInt<1>("h00") - oacq_write_beat.client_xact_id <= UInt<1>("h00") - oacq_write_beat.addr_block <= UInt<1>("h00") + oacq_write_beat is invalid oacq_write_beat.is_builtin_type <= UInt<1>("h01") oacq_write_beat.a_type <= UInt<3>("h02") oacq_write_beat.client_xact_id <= UInt<2>("h02") oacq_write_beat.addr_block <= xact.addr_block oacq_write_beat.addr_beat <= xact.addr_beat oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_827 - node T_861 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_862 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_863 = cat(T_861, T_862) - node T_865 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_866 = cat(UInt<3>("h07"), T_865) - node T_868 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_870 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_872 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_873 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_874 = cat(T_872, T_873) - node T_876 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_878 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_879 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_880 = mux(T_879, T_878, UInt<1>("h00")) - node T_881 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_882 = mux(T_881, T_876, T_880) - node T_883 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_884 = mux(T_883, T_874, T_882) - node T_885 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_886 = mux(T_885, T_870, T_884) - node T_887 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_888 = mux(T_887, T_868, T_886) - node T_889 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_890 = mux(T_889, T_866, T_888) - node T_891 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_892 = mux(T_891, T_863, T_890) + oacq_write_beat.union <= T_819 + node T_846 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_847 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_848 = cat(T_846, T_847) + node T_850 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_851 = cat(UInt<3>("h07"), T_850) + node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) + node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) + node T_857 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_858 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_859 = cat(T_857, T_858) + node T_861 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_863 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_864 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_865 = mux(T_864, T_863, UInt<1>("h00")) + node T_866 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_867 = mux(T_866, T_861, T_865) + node T_868 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_869 = mux(T_868, T_859, T_867) + node T_870 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_871 = mux(T_870, T_855, T_869) + node T_872 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_873 = mux(T_872, T_853, T_871) + node T_874 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_875 = mux(T_874, T_851, T_873) + node T_876 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_877 = mux(T_876, T_848, T_875) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block.data <= UInt<1>("h00") - oacq_write_block.union <= UInt<1>("h00") - oacq_write_block.a_type <= UInt<1>("h00") - oacq_write_block.is_builtin_type <= UInt<1>("h00") - oacq_write_block.addr_beat <= UInt<1>("h00") - oacq_write_block.client_xact_id <= UInt<1>("h00") - oacq_write_block.addr_block <= UInt<1>("h00") + oacq_write_block is invalid oacq_write_block.is_builtin_type <= UInt<1>("h01") oacq_write_block.a_type <= UInt<3>("h03") oacq_write_block.client_xact_id <= UInt<2>("h02") oacq_write_block.addr_block <= xact.addr_block oacq_write_block.addr_beat <= oacq_data_cnt oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_892 - node T_917 = bits(xact.union, 12, 9) - node T_918 = bits(xact.union, 8, 6) - node T_926 = cat(T_917, T_918) - node T_927 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_928 = cat(T_926, T_927) - node T_930 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_931 = cat(T_918, T_930) - node T_933 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_935 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_937 = cat(T_917, T_918) - node T_938 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_939 = cat(T_937, T_938) - node T_941 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_943 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_944 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_945 = mux(T_944, T_943, UInt<1>("h00")) - node T_946 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_947 = mux(T_946, T_941, T_945) - node T_948 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_949 = mux(T_948, T_939, T_947) - node T_950 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_951 = mux(T_950, T_935, T_949) - node T_952 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_953 = mux(T_952, T_933, T_951) - node T_954 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_955 = mux(T_954, T_931, T_953) - node T_956 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_957 = mux(T_956, T_928, T_955) + oacq_write_block.union <= T_877 + node T_895 = bits(xact.union, 12, 9) + node T_896 = bits(xact.union, 8, 6) + node T_904 = cat(T_895, T_896) + node T_905 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_906 = cat(T_904, T_905) + node T_908 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_909 = cat(T_896, T_908) + node T_911 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_913 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_915 = cat(T_895, T_896) + node T_916 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_917 = cat(T_915, T_916) + node T_919 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_921 = cat(UInt<5>("h01"), UInt<1>("h00")) + node T_922 = eq(UInt<3>("h06"), UInt<3>("h00")) + node T_923 = mux(T_922, T_921, UInt<1>("h00")) + node T_924 = eq(UInt<3>("h05"), UInt<3>("h00")) + node T_925 = mux(T_924, T_919, T_923) + node T_926 = eq(UInt<3>("h04"), UInt<3>("h00")) + node T_927 = mux(T_926, T_917, T_925) + node T_928 = eq(UInt<3>("h03"), UInt<3>("h00")) + node T_929 = mux(T_928, T_913, T_927) + node T_930 = eq(UInt<3>("h02"), UInt<3>("h00")) + node T_931 = mux(T_930, T_911, T_929) + node T_932 = eq(UInt<3>("h01"), UInt<3>("h00")) + node T_933 = mux(T_932, T_909, T_931) + node T_934 = eq(UInt<3>("h00"), UInt<3>("h00")) + node T_935 = mux(T_934, T_906, T_933) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= UInt<1>("h00") - oacq_read_beat.a_type <= UInt<1>("h00") - oacq_read_beat.is_builtin_type <= UInt<1>("h00") - oacq_read_beat.addr_beat <= UInt<1>("h00") - oacq_read_beat.client_xact_id <= UInt<1>("h00") - oacq_read_beat.addr_block <= UInt<1>("h00") + oacq_read_beat is invalid oacq_read_beat.is_builtin_type <= UInt<1>("h01") oacq_read_beat.a_type <= UInt<3>("h00") oacq_read_beat.client_xact_id <= UInt<2>("h02") oacq_read_beat.addr_block <= xact.addr_block oacq_read_beat.addr_beat <= xact.addr_beat oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= T_957 - node T_991 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_992 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_993 = cat(T_991, T_992) - node T_995 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_996 = cat(UInt<3>("h07"), T_995) - node T_998 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1000 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1002 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1003 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1004 = cat(T_1002, T_1003) - node T_1006 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1008 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1009 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_1010 = mux(T_1009, T_1008, UInt<1>("h00")) - node T_1011 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_1012 = mux(T_1011, T_1006, T_1010) - node T_1013 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_1014 = mux(T_1013, T_1004, T_1012) - node T_1015 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_1016 = mux(T_1015, T_1000, T_1014) - node T_1017 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_1018 = mux(T_1017, T_998, T_1016) - node T_1019 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_1020 = mux(T_1019, T_996, T_1018) - node T_1021 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_1022 = mux(T_1021, T_993, T_1020) + oacq_read_beat.union <= T_935 + node T_962 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_963 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_964 = cat(T_962, T_963) + node T_966 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_967 = cat(UInt<3>("h07"), T_966) + node T_969 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_971 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_973 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_974 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_975 = cat(T_973, T_974) + node T_977 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_979 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_980 = eq(UInt<3>("h06"), UInt<3>("h01")) + node T_981 = mux(T_980, T_979, UInt<1>("h00")) + node T_982 = eq(UInt<3>("h05"), UInt<3>("h01")) + node T_983 = mux(T_982, T_977, T_981) + node T_984 = eq(UInt<3>("h04"), UInt<3>("h01")) + node T_985 = mux(T_984, T_975, T_983) + node T_986 = eq(UInt<3>("h03"), UInt<3>("h01")) + node T_987 = mux(T_986, T_971, T_985) + node T_988 = eq(UInt<3>("h02"), UInt<3>("h01")) + node T_989 = mux(T_988, T_969, T_987) + node T_990 = eq(UInt<3>("h01"), UInt<3>("h01")) + node T_991 = mux(T_990, T_967, T_989) + node T_992 = eq(UInt<3>("h00"), UInt<3>("h01")) + node T_993 = mux(T_992, T_964, T_991) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= UInt<1>("h00") - oacq_read_block.a_type <= UInt<1>("h00") - oacq_read_block.is_builtin_type <= UInt<1>("h00") - oacq_read_block.addr_beat <= UInt<1>("h00") - oacq_read_block.client_xact_id <= UInt<1>("h00") - oacq_read_block.addr_block <= UInt<1>("h00") + oacq_read_block is invalid oacq_read_block.is_builtin_type <= UInt<1>("h01") oacq_read_block.a_type <= UInt<3>("h01") oacq_read_block.client_xact_id <= UInt<2>("h02") oacq_read_block.addr_block <= xact.addr_block oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= T_1022 + oacq_read_block.union <= T_993 io.outer.acquire.valid <= UInt<1>("h00") - node T_1047 = eq(state, UInt<1>("h01")) - node T_1048 = eq(state, UInt<2>("h03")) - wire T_1057 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1057 <- oacq_write_block - when subblock_type : - T_1057 <- oacq_write_beat - skip - wire T_1073 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1073 <- oacq_read_block - when subblock_type : - T_1073 <- oacq_read_beat - skip - wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1089 <- T_1073 - when T_1048 : - T_1089 <- T_1057 - skip - wire T_1105 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1105 <- T_1089 - when T_1047 : - T_1105 <- oacq_probe - skip - io.outer.acquire.bits <- T_1105 + node T_1011 = eq(state, UInt<1>("h01")) + node T_1012 = eq(state, UInt<2>("h03")) + node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) + node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) + node T_1029 = mux(T_1012, T_1013, T_1021) + node T_1037 = mux(T_1011, oacq_probe, T_1029) + io.outer.acquire.bits <- T_1037 io.outer.grant.ready <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") - node T_1122 = eq(UInt<3>("h04"), xact.a_type) - node T_1123 = mux(T_1122, UInt<1>("h00"), UInt<2>("h02")) - node T_1124 = eq(UInt<3>("h06"), xact.a_type) - node T_1125 = mux(T_1124, UInt<1>("h00"), T_1123) - node T_1126 = eq(UInt<3>("h05"), xact.a_type) - node T_1127 = mux(T_1126, UInt<2>("h02"), T_1125) - node T_1128 = eq(UInt<3>("h02"), xact.a_type) - node T_1129 = mux(T_1128, UInt<1>("h00"), T_1127) - node T_1130 = eq(UInt<3>("h00"), xact.a_type) - node T_1131 = mux(T_1130, UInt<2>("h02"), T_1129) - node T_1132 = eq(UInt<3>("h03"), xact.a_type) - node T_1133 = mux(T_1132, UInt<1>("h00"), T_1131) - node T_1134 = eq(UInt<3>("h01"), xact.a_type) - node T_1135 = mux(T_1134, UInt<2>("h02"), T_1133) - node T_1136 = eq(UInt<1>("h01"), xact.a_type) - node T_1137 = mux(T_1136, UInt<1>("h00"), UInt<2>("h02")) - node T_1138 = eq(UInt<1>("h00"), xact.a_type) - node T_1139 = mux(T_1138, UInt<1>("h01"), T_1137) - node T_1140 = mux(xact.is_builtin_type, T_1135, T_1139) - wire T_1145 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1145.client_id <= UInt<1>("h00") - T_1145.p_type <= UInt<1>("h00") - T_1145.addr_block <= UInt<1>("h00") - T_1145.client_id <= UInt<1>("h00") - T_1145.p_type <= T_1140 - T_1145.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1145 + node T_1054 = eq(UInt<3>("h04"), xact.a_type) + node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02")) + node T_1056 = eq(UInt<3>("h06"), xact.a_type) + node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055) + node T_1058 = eq(UInt<3>("h05"), xact.a_type) + node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057) + node T_1060 = eq(UInt<3>("h02"), xact.a_type) + node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059) + node T_1062 = eq(UInt<3>("h00"), xact.a_type) + node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061) + node T_1064 = eq(UInt<3>("h03"), xact.a_type) + node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063) + node T_1066 = eq(UInt<3>("h01"), xact.a_type) + node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065) + node T_1068 = eq(UInt<1>("h01"), xact.a_type) + node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02")) + node T_1070 = eq(UInt<1>("h00"), xact.a_type) + node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069) + node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) + wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} + T_1077 is invalid + T_1077.client_id <= UInt<1>("h00") + T_1077.p_type <= T_1072 + T_1077.addr_block <= xact.addr_block + io.inner.probe.bits <- T_1077 io.inner.grant.valid <= UInt<1>("h00") - node T_1171 = eq(UInt<3>("h06"), xact.a_type) - node T_1172 = mux(T_1171, UInt<3>("h01"), UInt<3>("h03")) - node T_1173 = eq(UInt<3>("h05"), xact.a_type) - node T_1174 = mux(T_1173, UInt<3>("h01"), T_1172) - node T_1175 = eq(UInt<3>("h04"), xact.a_type) - node T_1176 = mux(T_1175, UInt<3>("h04"), T_1174) - node T_1177 = eq(UInt<3>("h03"), xact.a_type) - node T_1178 = mux(T_1177, UInt<3>("h03"), T_1176) - node T_1179 = eq(UInt<3>("h02"), xact.a_type) - node T_1180 = mux(T_1179, UInt<3>("h03"), T_1178) - node T_1181 = eq(UInt<3>("h01"), xact.a_type) - node T_1182 = mux(T_1181, UInt<3>("h05"), T_1180) - node T_1183 = eq(UInt<3>("h00"), xact.a_type) - node T_1184 = mux(T_1183, UInt<3>("h04"), T_1182) - node T_1185 = eq(xact.a_type, UInt<1>("h00")) - node T_1188 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1189 = mux(T_1188, UInt<1>("h00"), UInt<1>("h01")) - node T_1190 = mux(T_1185, T_1189, UInt<1>("h01")) - node T_1191 = mux(xact.is_builtin_type, T_1184, T_1190) - wire T_1200 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1200.client_id <= UInt<1>("h00") - T_1200.data <= UInt<1>("h00") - T_1200.g_type <= UInt<1>("h00") - T_1200.is_builtin_type <= UInt<1>("h00") - T_1200.manager_xact_id <= UInt<1>("h00") - T_1200.client_xact_id <= UInt<1>("h00") - T_1200.addr_beat <= UInt<1>("h00") - T_1200.client_id <= xact.client_id - T_1200.is_builtin_type <= xact.is_builtin_type - T_1200.g_type <= T_1191 - T_1200.client_xact_id <= xact.client_xact_id - T_1200.manager_xact_id <= UInt<2>("h02") - T_1200.addr_beat <= UInt<1>("h00") - T_1200.data <= UInt<1>("h00") - io.inner.grant.bits <- T_1200 + node T_1100 = eq(UInt<3>("h06"), xact.a_type) + node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03")) + node T_1102 = eq(UInt<3>("h05"), xact.a_type) + node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101) + node T_1104 = eq(UInt<3>("h04"), xact.a_type) + node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103) + node T_1106 = eq(UInt<3>("h03"), xact.a_type) + node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105) + node T_1108 = eq(UInt<3>("h02"), xact.a_type) + node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107) + node T_1110 = eq(UInt<3>("h01"), xact.a_type) + node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109) + node T_1112 = eq(UInt<3>("h00"), xact.a_type) + node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111) + node T_1114 = eq(xact.a_type, UInt<1>("h00")) + node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01")) + node T_1119 = mux(T_1114, T_1118, UInt<1>("h01")) + node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) + wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} + T_1129 is invalid + T_1129.client_id <= xact.client_id + T_1129.is_builtin_type <= xact.is_builtin_type + T_1129.g_type <= T_1120 + T_1129.client_xact_id <= xact.client_xact_id + T_1129.manager_xact_id <= UInt<2>("h02") + T_1129.addr_beat <= UInt<1>("h00") + T_1129.data <= UInt<1>("h00") + io.inner.grant.bits <- T_1129 io.inner.acquire.ready <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") - node T_1218 = neq(state, UInt<1>("h00")) - node T_1219 = and(T_1218, collect_iacq_data) - node T_1220 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1221 = and(T_1219, T_1220) - node T_1222 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1223 = and(T_1221, T_1222) - node T_1225 = eq(T_1223, UInt<1>("h00")) - node T_1227 = eq(reset, UInt<1>("h00")) - when T_1227 : - node T_1229 = eq(T_1225, UInt<1>("h00")) - when T_1229 : - node T_1231 = eq(reset, UInt<1>("h00")) - when T_1231 : + node T_1140 = neq(state, UInt<1>("h00")) + node T_1141 = and(T_1140, collect_iacq_data) + node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1143 = and(T_1141, T_1142) + node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) + node T_1145 = and(T_1143, T_1144) + node T_1147 = eq(T_1145, UInt<1>("h00")) + node T_1149 = eq(reset, UInt<1>("h00")) + when T_1149 : + node T_1151 = eq(T_1147, UInt<1>("h00")) + when T_1151 : + node T_1153 = eq(reset, UInt<1>("h00")) + when T_1153 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1232 = neq(state, UInt<1>("h00")) - node T_1233 = and(T_1232, collect_iacq_data) - node T_1234 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1235 = and(T_1233, T_1234) - node T_1236 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1237 = and(T_1235, T_1236) - node T_1239 = eq(T_1237, UInt<1>("h00")) - node T_1241 = eq(reset, UInt<1>("h00")) - when T_1241 : - node T_1243 = eq(T_1239, UInt<1>("h00")) - when T_1243 : - node T_1245 = eq(reset, UInt<1>("h00")) - when T_1245 : + node T_1154 = neq(state, UInt<1>("h00")) + node T_1155 = and(T_1154, collect_iacq_data) + node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1157 = and(T_1155, T_1156) + node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) + node T_1159 = and(T_1157, T_1158) + node T_1161 = eq(T_1159, UInt<1>("h00")) + node T_1163 = eq(reset, UInt<1>("h00")) + when T_1163 : + node T_1165 = eq(T_1161, UInt<1>("h00")) + when T_1165 : + node T_1167 = eq(reset, UInt<1>("h00")) + when T_1167 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1246 = eq(state, UInt<1>("h00")) - node T_1247 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1248 = and(T_1246, T_1247) - node T_1250 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1253 : UInt<3>[1] - T_1253[0] <= UInt<3>("h03") - node T_1256 = eq(T_1253[0], io.inner.acquire.bits.a_type) - node T_1258 = or(UInt<1>("h00"), T_1256) - node T_1259 = and(T_1250, T_1258) - node T_1260 = and(T_1248, T_1259) - node T_1262 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1263 = and(T_1260, T_1262) - node T_1265 = eq(T_1263, UInt<1>("h00")) - node T_1267 = eq(reset, UInt<1>("h00")) - when T_1267 : - node T_1269 = eq(T_1265, UInt<1>("h00")) - when T_1269 : - node T_1271 = eq(reset, UInt<1>("h00")) - when T_1271 : + node T_1168 = eq(state, UInt<1>("h00")) + node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1170 = and(T_1168, T_1169) + node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_1175 : UInt<3>[1] + T_1175[0] <= UInt<3>("h03") + node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) + node T_1180 = or(UInt<1>("h00"), T_1178) + node T_1181 = and(T_1172, T_1180) + node T_1182 = and(T_1170, T_1181) + node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) + node T_1185 = and(T_1182, T_1184) + node T_1187 = eq(T_1185, UInt<1>("h00")) + node T_1189 = eq(reset, UInt<1>("h00")) + when T_1189 : + node T_1191 = eq(T_1187, UInt<1>("h00")) + when T_1191 : + node T_1193 = eq(reset, UInt<1>("h00")) + when T_1193 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") skip stop(clk, UInt<1>(1), 1) @@ -4622,38 +3414,40 @@ circuit Top : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1275 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1276 = bits(T_1275, 3, 3) - node T_1278 = dshl(UInt<1>("h01"), T_1276) - node T_1280 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1281 = and(io.inner.acquire.bits.is_builtin_type, T_1280) - node T_1282 = bit(T_1278, 0) - node T_1283 = bit(T_1278, 1) - wire T_1285 : UInt<1>[2] - T_1285[0] <= T_1282 - T_1285[1] <= T_1283 - node T_1290 = subw(UInt<8>("h00"), T_1285[0]) - node T_1292 = subw(UInt<8>("h00"), T_1285[1]) - wire T_1294 : UInt<8>[2] - T_1294[0] <= T_1290 - T_1294[1] <= T_1292 - node T_1298 = cat(T_1294[1], T_1294[0]) - node T_1300 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1301 = and(io.inner.acquire.bits.is_builtin_type, T_1300) - node T_1303 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1304 = and(io.inner.acquire.bits.is_builtin_type, T_1303) - node T_1305 = or(T_1301, T_1304) - node T_1306 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1308 = mux(T_1305, T_1306, UInt<16>("h00")) - node T_1309 = mux(T_1281, T_1298, T_1308) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1309 - node T_1312 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) - node T_1313 = or(iacq_data_valid, T_1312) - node T_1314 = not(iacq_data_valid) - node T_1315 = or(T_1314, T_1312) - node T_1316 = not(T_1315) - node T_1317 = mux(UInt<1>("h01"), T_1313, T_1316) - iacq_data_valid <= T_1317 + node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) + node T_1198 = bits(T_1197, 3, 3) + node T_1200 = dshl(UInt<1>("h01"), T_1198) + node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) + node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) + node T_1204 = bits(T_1200, 0, 0) + node T_1205 = bits(T_1200, 1, 1) + wire T_1207 : UInt<1>[2] + T_1207[0] <= T_1204 + T_1207[1] <= T_1205 + node T_1212 = sub(UInt<8>("h00"), T_1207[0]) + node T_1213 = tail(T_1212, 1) + node T_1215 = sub(UInt<8>("h00"), T_1207[1]) + node T_1216 = tail(T_1215, 1) + wire T_1218 : UInt<8>[2] + T_1218[0] <= T_1213 + T_1218[1] <= T_1216 + node T_1222 = cat(T_1218[1], T_1218[0]) + node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) + node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) + node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) + node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) + node T_1229 = or(T_1225, T_1228) + node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) + node T_1232 = mux(T_1229, T_1230, UInt<16>("h00")) + node T_1233 = mux(T_1203, T_1222, T_1232) + xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 + node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) + node T_1237 = or(iacq_data_valid, T_1236) + node T_1238 = not(iacq_data_valid) + node T_1239 = or(T_1238, T_1236) + node T_1240 = not(T_1239) + node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240) + iacq_data_valid <= T_1241 skip when iacq_data_done : collect_iacq_data <= UInt<1>("h00") @@ -4665,194 +3459,201 @@ circuit Top : pending_ognt_ack <= UInt<1>("h00") skip skip - node T_1321 = eq(UInt<1>("h00"), state) - when T_1321 : + node T_1245 = eq(UInt<1>("h00"), state) + when T_1245 : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact <- io.inner.acquire.bits xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data - node T_1327 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1328 = bits(T_1327, 3, 3) - node T_1330 = dshl(UInt<1>("h01"), T_1328) - node T_1332 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1333 = and(io.inner.acquire.bits.is_builtin_type, T_1332) - node T_1334 = bit(T_1330, 0) - node T_1335 = bit(T_1330, 1) - wire T_1337 : UInt<1>[2] - T_1337[0] <= T_1334 - T_1337[1] <= T_1335 - node T_1342 = subw(UInt<8>("h00"), T_1337[0]) - node T_1344 = subw(UInt<8>("h00"), T_1337[1]) - wire T_1346 : UInt<8>[2] - T_1346[0] <= T_1342 - T_1346[1] <= T_1344 - node T_1350 = cat(T_1346[1], T_1346[0]) - node T_1352 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1353 = and(io.inner.acquire.bits.is_builtin_type, T_1352) - node T_1355 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1356 = and(io.inner.acquire.bits.is_builtin_type, T_1355) - node T_1357 = or(T_1353, T_1356) - node T_1358 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1360 = mux(T_1357, T_1358, UInt<16>("h00")) - node T_1361 = mux(T_1333, T_1350, T_1360) - xact.wmask_buffer[UInt<1>("h00")] <= T_1361 - node T_1363 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1366 : UInt<3>[1] - T_1366[0] <= UInt<3>("h03") - node T_1369 = eq(T_1366[0], io.inner.acquire.bits.a_type) - node T_1371 = or(UInt<1>("h00"), T_1369) - node T_1372 = and(T_1363, T_1371) - collect_iacq_data <= T_1372 - wire T_1377 : UInt<3>[3] - T_1377[0] <= UInt<3>("h02") - T_1377[1] <= UInt<3>("h03") - T_1377[2] <= UInt<3>("h04") - node T_1382 = eq(T_1377[0], io.inner.acquire.bits.a_type) - node T_1383 = eq(T_1377[1], io.inner.acquire.bits.a_type) - node T_1384 = eq(T_1377[2], io.inner.acquire.bits.a_type) - node T_1386 = or(UInt<1>("h00"), T_1382) - node T_1387 = or(T_1386, T_1383) - node T_1388 = or(T_1387, T_1384) - node T_1389 = and(io.inner.acquire.bits.is_builtin_type, T_1388) - node T_1390 = dshl(T_1389, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1390 - node T_1392 = neq(mask_incoherent, UInt<1>("h00")) - when T_1392 : + node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) + node T_1252 = bits(T_1251, 3, 3) + node T_1254 = dshl(UInt<1>("h01"), T_1252) + node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) + node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) + node T_1258 = bits(T_1254, 0, 0) + node T_1259 = bits(T_1254, 1, 1) + wire T_1261 : UInt<1>[2] + T_1261[0] <= T_1258 + T_1261[1] <= T_1259 + node T_1266 = sub(UInt<8>("h00"), T_1261[0]) + node T_1267 = tail(T_1266, 1) + node T_1269 = sub(UInt<8>("h00"), T_1261[1]) + node T_1270 = tail(T_1269, 1) + wire T_1272 : UInt<8>[2] + T_1272[0] <= T_1267 + T_1272[1] <= T_1270 + node T_1276 = cat(T_1272[1], T_1272[0]) + node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) + node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) + node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) + node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) + node T_1283 = or(T_1279, T_1282) + node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) + node T_1286 = mux(T_1283, T_1284, UInt<16>("h00")) + node T_1287 = mux(T_1257, T_1276, T_1286) + xact.wmask_buffer[UInt<1>("h00")] <= T_1287 + node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_1292 : UInt<3>[1] + T_1292[0] <= UInt<3>("h03") + node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) + node T_1297 = or(UInt<1>("h00"), T_1295) + node T_1298 = and(T_1289, T_1297) + collect_iacq_data <= T_1298 + wire T_1303 : UInt<3>[3] + T_1303[0] <= UInt<3>("h02") + T_1303[1] <= UInt<3>("h03") + T_1303[2] <= UInt<3>("h04") + node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) + node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) + node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) + node T_1312 = or(UInt<1>("h00"), T_1308) + node T_1313 = or(T_1312, T_1309) + node T_1314 = or(T_1313, T_1310) + node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) + node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) + iacq_data_valid <= T_1316 + node T_1318 = neq(mask_incoherent, UInt<1>("h00")) + when T_1318 : pending_probes <= mask_incoherent - node T_1393 = bit(mask_incoherent, 0) - node T_1394 = bit(mask_incoherent, 1) - node T_1395 = bit(mask_incoherent, 2) - node T_1396 = bit(mask_incoherent, 3) - node T_1398 = cat(UInt<1>("h00"), T_1394) - node T_1399 = addw(T_1393, T_1398) - node T_1402 = cat(UInt<1>("h00"), T_1396) - node T_1403 = addw(T_1395, T_1402) - node T_1404 = cat(UInt<1>("h00"), T_1403) - node T_1405 = addw(T_1399, T_1404) - release_count <= T_1405 + node T_1319 = bits(mask_incoherent, 0, 0) + node T_1320 = bits(mask_incoherent, 1, 1) + node T_1321 = bits(mask_incoherent, 2, 2) + node T_1322 = bits(mask_incoherent, 3, 3) + node T_1324 = cat(UInt<1>("h00"), T_1320) + node T_1325 = add(T_1319, T_1324) + node T_1326 = tail(T_1325, 1) + node T_1329 = cat(UInt<1>("h00"), T_1322) + node T_1330 = add(T_1321, T_1329) + node T_1331 = tail(T_1330, 1) + node T_1332 = cat(UInt<1>("h00"), T_1331) + node T_1333 = add(T_1326, T_1332) + node T_1334 = tail(T_1333, 1) + release_count <= T_1334 skip - node T_1406 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_1407 = mux(pending_outer_write_, UInt<2>("h03"), T_1406) - node T_1408 = mux(T_1392, UInt<1>("h01"), T_1407) - state <= T_1408 + node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) + node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335) + node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336) + state <= T_1337 skip skip - node T_1409 = eq(UInt<1>("h01"), state) - when T_1409 : - node T_1411 = neq(pending_probes, UInt<1>("h00")) - io.inner.probe.valid <= T_1411 + node T_1338 = eq(UInt<1>("h01"), state) + when T_1338 : + node T_1340 = neq(pending_probes, UInt<1>("h00")) + io.inner.probe.valid <= T_1340 when io.inner.probe.ready : - node T_1413 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_1414 = not(T_1413) - node T_1415 = and(pending_probes, T_1414) - pending_probes <= T_1415 - skip - wire T_1417 : UInt<2>[3] - T_1417[0] <= UInt<1>("h00") - T_1417[1] <= UInt<1>("h01") - T_1417[2] <= UInt<2>("h02") - node T_1422 = eq(T_1417[0], io.inner.release.bits.r_type) - node T_1423 = eq(T_1417[1], io.inner.release.bits.r_type) - node T_1424 = eq(T_1417[2], io.inner.release.bits.r_type) - node T_1426 = or(UInt<1>("h00"), T_1422) - node T_1427 = or(T_1426, T_1423) - node T_1428 = or(T_1427, T_1424) - node T_1430 = eq(T_1428, UInt<1>("h00")) - node T_1431 = or(T_1430, io.outer.acquire.ready) - io.inner.release.ready <= T_1431 + node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00")) + node T_1343 = not(T_1342) + node T_1344 = and(pending_probes, T_1343) + pending_probes <= T_1344 + skip + wire T_1346 : UInt<2>[3] + T_1346[0] <= UInt<1>("h00") + T_1346[1] <= UInt<1>("h01") + T_1346[2] <= UInt<2>("h02") + node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) + node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) + node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) + node T_1355 = or(UInt<1>("h00"), T_1351) + node T_1356 = or(T_1355, T_1352) + node T_1357 = or(T_1356, T_1353) + node T_1359 = eq(T_1357, UInt<1>("h00")) + node T_1360 = or(T_1359, io.outer.acquire.ready) + io.inner.release.ready <= T_1360 when io.inner.release.valid : - wire T_1433 : UInt<2>[3] - T_1433[0] <= UInt<1>("h00") - T_1433[1] <= UInt<1>("h01") - T_1433[2] <= UInt<2>("h02") - node T_1438 = eq(T_1433[0], io.inner.release.bits.r_type) - node T_1439 = eq(T_1433[1], io.inner.release.bits.r_type) - node T_1440 = eq(T_1433[2], io.inner.release.bits.r_type) - node T_1442 = or(UInt<1>("h00"), T_1438) - node T_1443 = or(T_1442, T_1439) - node T_1444 = or(T_1443, T_1440) - when T_1444 : + wire T_1362 : UInt<2>[3] + T_1362[0] <= UInt<1>("h00") + T_1362[1] <= UInt<1>("h01") + T_1362[2] <= UInt<2>("h02") + node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) + node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) + node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) + node T_1371 = or(UInt<1>("h00"), T_1367) + node T_1372 = or(T_1371, T_1368) + node T_1373 = or(T_1372, T_1369) + when T_1373 : io.outer.acquire.valid <= UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") - node T_1448 = subw(release_count, UInt<1>("h01")) - release_count <= T_1448 - node T_1450 = eq(release_count, UInt<1>("h01")) - when T_1450 : - node T_1451 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1452 = mux(pending_outer_write, UInt<2>("h03"), T_1451) - state <= T_1452 + node T_1377 = sub(release_count, UInt<1>("h01")) + node T_1378 = tail(T_1377, 1) + release_count <= T_1378 + node T_1380 = eq(release_count, UInt<1>("h01")) + when T_1380 : + node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381) + state <= T_1382 skip skip skip skip - node T_1454 = eq(T_1444, UInt<1>("h00")) - when T_1454 : - node T_1456 = subw(release_count, UInt<1>("h01")) - release_count <= T_1456 - node T_1458 = eq(release_count, UInt<1>("h01")) - when T_1458 : - node T_1459 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1460 = mux(pending_outer_write, UInt<2>("h03"), T_1459) - state <= T_1460 + node T_1384 = eq(T_1373, UInt<1>("h00")) + when T_1384 : + node T_1386 = sub(release_count, UInt<1>("h01")) + node T_1387 = tail(T_1386, 1) + release_count <= T_1387 + node T_1389 = eq(release_count, UInt<1>("h01")) + when T_1389 : + node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390) + state <= T_1391 skip skip skip skip - node T_1461 = eq(UInt<2>("h03"), state) - when T_1461 : - node T_1463 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_1465 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1466 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1467 = bit(T_1466, 0) - node T_1468 = or(T_1465, T_1467) - node T_1469 = and(T_1463, T_1468) - io.outer.acquire.valid <= T_1469 + node T_1392 = eq(UInt<2>("h03"), state) + when T_1392 : + node T_1394 = eq(pending_ognt_ack, UInt<1>("h00")) + node T_1396 = eq(collect_iacq_data, UInt<1>("h00")) + node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) + node T_1398 = bits(T_1397, 0, 0) + node T_1399 = or(T_1396, T_1398) + node T_1400 = and(T_1394, T_1399) + io.outer.acquire.valid <= T_1400 when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") - node T_1471 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state <= T_1471 + node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) + state <= T_1402 skip skip - node T_1472 = eq(UInt<2>("h02"), state) - when T_1472 : - node T_1474 = eq(pending_ognt_ack, UInt<1>("h00")) - io.outer.acquire.valid <= T_1474 - node T_1475 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1475 : + node T_1403 = eq(UInt<2>("h02"), state) + when T_1403 : + node T_1405 = eq(pending_ognt_ack, UInt<1>("h00")) + io.outer.acquire.valid <= T_1405 + node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) + when T_1406 : state <= UInt<3>("h05") skip skip - node T_1476 = eq(UInt<3>("h05"), state) - when T_1476 : + node T_1407 = eq(UInt<3>("h05"), state) + when T_1407 : io.outer.grant.ready <= io.inner.grant.ready io.inner.grant.valid <= io.outer.grant.valid when ignt_data_done : - node T_1479 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1481 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1482 = and(io.inner.grant.bits.is_builtin_type, T_1481) - node T_1484 = eq(T_1482, UInt<1>("h00")) - node T_1485 = and(T_1479, T_1484) - node T_1486 = mux(T_1485, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1486 + node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) + node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) + node T_1415 = eq(T_1413, UInt<1>("h00")) + node T_1416 = and(T_1410, T_1415) + node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00")) + state <= T_1417 skip skip - node T_1487 = eq(UInt<3>("h04"), state) - when T_1487 : + node T_1418 = eq(UInt<3>("h04"), state) + when T_1418 : io.inner.grant.valid <= UInt<1>("h01") when io.inner.grant.ready : - node T_1491 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1493 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1494 = and(io.inner.grant.bits.is_builtin_type, T_1493) - node T_1496 = eq(T_1494, UInt<1>("h00")) - node T_1497 = and(T_1491, T_1496) - node T_1498 = mux(T_1497, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1498 + node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) + node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) + node T_1427 = eq(T_1425, UInt<1>("h00")) + node T_1428 = and(T_1422, T_1427) + node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00")) + state <= T_1429 skip skip - node T_1499 = eq(UInt<3>("h06"), state) - when T_1499 : + node T_1430 = eq(UInt<3>("h06"), state) + when T_1430 : io.inner.finish.ready <= UInt<1>("h01") when io.inner.finish.valid : state <= UInt<1>("h00") @@ -4864,98 +3665,73 @@ circuit Top : input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - io.has_release_match <= UInt<1>("h00") - io.has_acquire_match <= UInt<1>("h00") - io.has_acquire_conflict <= UInt<1>("h00") - io.outer.grant.ready <= UInt<1>("h00") - io.outer.acquire.bits.data <= UInt<1>("h00") - io.outer.acquire.bits.union <= UInt<1>("h00") - io.outer.acquire.bits.a_type <= UInt<1>("h00") - io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.outer.acquire.bits.addr_beat <= UInt<1>("h00") - io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") - io.outer.acquire.bits.addr_block <= UInt<1>("h00") - io.outer.acquire.valid <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.probe.bits.client_id <= UInt<1>("h00") - io.inner.probe.bits.p_type <= UInt<1>("h00") - io.inner.probe.bits.addr_block <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - io.inner.grant.bits.client_id <= UInt<1>("h00") - io.inner.grant.bits.data <= UInt<1>("h00") - io.inner.grant.bits.g_type <= UInt<1>("h00") - io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") - io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") - io.inner.grant.bits.client_xact_id <= UInt<1>("h00") - io.inner.grant.bits.addr_beat <= UInt<1>("h00") - io.inner.grant.valid <= UInt<1>("h00") - io.inner.acquire.ready <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk, UInt<1>("h00"), xact + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk wire coh : {sharers : UInt<1>} + coh is invalid coh.sharers <= UInt<1>("h00") - coh.sharers <= UInt<1>("h00") - node T_304 = neq(state, UInt<1>("h00")) - node T_305 = and(T_304, xact.is_builtin_type) - wire T_310 : UInt<3>[3] - T_310[0] <= UInt<3>("h04") - T_310[1] <= UInt<3>("h05") - T_310[2] <= UInt<3>("h06") - node T_315 = eq(T_310[0], xact.a_type) - node T_316 = eq(T_310[1], xact.a_type) - node T_317 = eq(T_310[2], xact.a_type) - node T_319 = or(UInt<1>("h00"), T_315) + node T_303 = neq(state, UInt<1>("h00")) + node T_304 = and(T_303, xact.is_builtin_type) + wire T_309 : UInt<3>[3] + T_309[0] <= UInt<3>("h04") + T_309[1] <= UInt<3>("h05") + T_309[2] <= UInt<3>("h06") + node T_314 = eq(T_309[0], xact.a_type) + node T_315 = eq(T_309[1], xact.a_type) + node T_316 = eq(T_309[2], xact.a_type) + node T_318 = or(UInt<1>("h00"), T_314) + node T_319 = or(T_318, T_315) node T_320 = or(T_319, T_316) - node T_321 = or(T_320, T_317) - node T_322 = and(T_305, T_321) - node T_324 = eq(T_322, UInt<1>("h00")) - node T_326 = eq(reset, UInt<1>("h00")) - when T_326 : - node T_328 = eq(T_324, UInt<1>("h00")) - when T_328 : - node T_330 = eq(reset, UInt<1>("h00")) - when T_330 : + node T_321 = and(T_304, T_320) + node T_323 = eq(T_321, UInt<1>("h00")) + node T_325 = eq(reset, UInt<1>("h00")) + when T_325 : + node T_327 = eq(T_323, UInt<1>("h00")) + when T_327 : + node T_329 = eq(reset, UInt<1>("h00")) + when T_329 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") skip stop(clk, UInt<1>(1), 1) skip skip - reg release_count : UInt<1>, clk, reset, UInt<1>("h00") - reg pending_probes : UInt<1>, clk, reset, UInt<1>("h00") - node T_335 = bit(pending_probes, 0) - wire T_337 : UInt<1>[1] - T_337[0] <= T_335 - node T_342 = asUInt(asSInt(UInt<1>("h01"))) - node T_345 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) - node T_346 = or(T_342, T_345) - node T_347 = not(T_342) - node T_348 = or(T_347, T_345) - node T_349 = not(T_348) - node mask_self = mux(UInt<1>("h00"), T_346, T_349) - node T_351 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_351) - reg collect_iacq_data : UInt<1>, clk, reset, UInt<1>("h00") - reg iacq_data_valid : UInt<4>, clk, reset, UInt<4>("h00") - node T_357 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_360 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_363 : UInt<3>[1] - T_363[0] <= UInt<3>("h03") - node T_366 = eq(T_363[0], io.inner.acquire.bits.a_type) - node T_368 = or(UInt<1>("h00"), T_366) - node T_369 = and(T_360, T_368) - node T_370 = and(T_357, T_369) - reg T_372 : UInt<2>, clk, reset, UInt<2>("h00") - when T_370 : - node T_374 = eq(T_372, UInt<2>("h03")) - node T_376 = and(UInt<1>("h00"), T_374) - node T_379 = addw(T_372, UInt<1>("h01")) - node T_380 = mux(T_376, UInt<1>("h00"), T_379) - T_372 <= T_380 - skip - node T_381 = and(T_370, T_374) - node T_382 = mux(T_369, T_372, UInt<1>("h00")) - node iacq_data_done = mux(T_369, T_381, T_357) + reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_334 = bits(pending_probes, 0, 0) + wire T_336 : UInt<1>[1] + T_336[0] <= T_334 + node T_341 = asUInt(asSInt(UInt<1>("h01"))) + node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) + node T_345 = or(T_341, T_344) + node T_346 = not(T_341) + node T_347 = or(T_346, T_344) + node T_348 = not(T_347) + node mask_self = mux(UInt<1>("h00"), T_345, T_348) + node T_350 = not(io.incoherent[0]) + node mask_incoherent = and(mask_self, T_350) + reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) + node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_362 : UInt<3>[1] + T_362[0] <= UInt<3>("h03") + node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) + node T_367 = or(UInt<1>("h00"), T_365) + node T_368 = and(T_359, T_367) + node T_369 = and(T_356, T_368) + reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_369 : + node T_373 = eq(T_371, UInt<2>("h03")) + node T_375 = and(UInt<1>("h00"), T_373) + node T_378 = add(T_371, UInt<1>("h01")) + node T_379 = tail(T_378, 1) + node T_380 = mux(T_375, UInt<1>("h00"), T_379) + T_371 <= T_380 + skip + node T_381 = and(T_369, T_373) + node T_382 = mux(T_368, T_371, UInt<1>("h00")) + node iacq_data_done = mux(T_368, T_381, T_356) node T_384 = and(io.inner.release.ready, io.inner.release.valid) wire T_388 : UInt<2>[3] T_388[0] <= UInt<1>("h00") @@ -4969,577 +3745,523 @@ circuit Top : node T_399 = or(T_398, T_395) node T_400 = and(UInt<1>("h01"), T_399) node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk, reset, UInt<2>("h00") + reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) when T_401 : node T_405 = eq(T_403, UInt<2>("h03")) node T_407 = and(UInt<1>("h00"), T_405) - node T_410 = addw(T_403, UInt<1>("h01")) - node T_411 = mux(T_407, UInt<1>("h00"), T_410) - T_403 <= T_411 - skip - node T_412 = and(T_401, T_405) - node T_413 = mux(T_400, T_403, UInt<1>("h00")) - node irel_data_done = mux(T_400, T_412, T_384) - node T_416 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_420 : UInt<3>[1] - T_420[0] <= UInt<3>("h05") - node T_423 = eq(T_420[0], io.inner.grant.bits.g_type) - node T_425 = or(UInt<1>("h00"), T_423) - wire T_427 : UInt<1>[2] - T_427[0] <= UInt<1>("h00") - T_427[1] <= UInt<1>("h01") - node T_431 = eq(T_427[0], io.inner.grant.bits.g_type) - node T_432 = eq(T_427[1], io.inner.grant.bits.g_type) - node T_434 = or(UInt<1>("h00"), T_431) - node T_435 = or(T_434, T_432) - node T_436 = mux(io.inner.grant.bits.is_builtin_type, T_425, T_435) - node T_437 = and(UInt<1>("h01"), T_436) - node T_438 = and(T_416, T_437) - reg T_440 : UInt<2>, clk, reset, UInt<2>("h00") - when T_438 : - node T_442 = eq(T_440, UInt<2>("h03")) - node T_444 = and(UInt<1>("h00"), T_442) - node T_447 = addw(T_440, UInt<1>("h01")) - node T_448 = mux(T_444, UInt<1>("h00"), T_447) - T_440 <= T_448 - skip - node T_449 = and(T_438, T_442) - node ignt_data_cnt = mux(T_437, T_440, UInt<1>("h00")) - node ignt_data_done = mux(T_437, T_449, T_416) - node T_453 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_455 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) - wire T_458 : UInt<3>[1] - T_458[0] <= UInt<3>("h03") - node T_461 = eq(T_458[0], io.outer.acquire.bits.a_type) - node T_463 = or(UInt<1>("h00"), T_461) - node T_464 = and(T_455, T_463) - node T_465 = and(T_453, T_464) - reg T_467 : UInt<2>, clk, reset, UInt<2>("h00") - when T_465 : - node T_469 = eq(T_467, UInt<2>("h03")) - node T_471 = and(UInt<1>("h00"), T_469) - node T_474 = addw(T_467, UInt<1>("h01")) - node T_475 = mux(T_471, UInt<1>("h00"), T_474) - T_467 <= T_475 - skip - node T_476 = and(T_465, T_469) - node oacq_data_cnt = mux(T_464, T_467, UInt<1>("h00")) - node oacq_data_done = mux(T_464, T_476, T_453) - node T_479 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_484 : UInt<3>[1] - T_484[0] <= UInt<3>("h05") - node T_487 = eq(T_484[0], io.outer.grant.bits.g_type) - node T_489 = or(UInt<1>("h00"), T_487) - wire T_491 : UInt<1>[1] - T_491[0] <= UInt<1>("h00") - node T_494 = eq(T_491[0], io.outer.grant.bits.g_type) - node T_496 = or(UInt<1>("h00"), T_494) - node T_497 = mux(io.outer.grant.bits.is_builtin_type, T_489, T_496) - node T_498 = and(UInt<1>("h01"), T_497) - node T_499 = and(T_479, T_498) - reg T_501 : UInt<2>, clk, reset, UInt<2>("h00") - when T_499 : - node T_503 = eq(T_501, UInt<2>("h03")) - node T_505 = and(UInt<1>("h00"), T_503) - node T_508 = addw(T_501, UInt<1>("h01")) - node T_509 = mux(T_505, UInt<1>("h00"), T_508) - T_501 <= T_509 - skip - node T_510 = and(T_499, T_503) - node T_511 = mux(T_498, T_501, UInt<1>("h00")) - node ognt_data_done = mux(T_498, T_510, T_479) - reg pending_ognt_ack : UInt<1>, clk, reset, UInt<1>("h00") - wire T_519 : UInt<3>[3] - T_519[0] <= UInt<3>("h02") - T_519[1] <= UInt<3>("h03") - T_519[2] <= UInt<3>("h04") - node T_524 = eq(T_519[0], xact.a_type) - node T_525 = eq(T_519[1], xact.a_type) - node T_526 = eq(T_519[2], xact.a_type) - node T_528 = or(UInt<1>("h00"), T_524) - node T_529 = or(T_528, T_525) - node T_530 = or(T_529, T_526) - node pending_outer_write = and(xact.is_builtin_type, T_530) - wire T_536 : UInt<3>[3] - T_536[0] <= UInt<3>("h02") - T_536[1] <= UInt<3>("h03") - T_536[2] <= UInt<3>("h04") - node T_541 = eq(T_536[0], io.inner.acquire.bits.a_type) - node T_542 = eq(T_536[1], io.inner.acquire.bits.a_type) - node T_543 = eq(T_536[2], io.inner.acquire.bits.a_type) - node T_545 = or(UInt<1>("h00"), T_541) - node T_546 = or(T_545, T_542) - node T_547 = or(T_546, T_543) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_547) - wire T_552 : UInt<3>[2] - T_552[0] <= UInt<3>("h05") - T_552[1] <= UInt<3>("h04") - node T_556 = eq(T_552[0], io.inner.grant.bits.g_type) - node T_557 = eq(T_552[1], io.inner.grant.bits.g_type) - node T_559 = or(UInt<1>("h00"), T_556) - node T_560 = or(T_559, T_557) - wire T_562 : UInt<1>[2] - T_562[0] <= UInt<1>("h00") - T_562[1] <= UInt<1>("h01") - node T_566 = eq(T_562[0], io.inner.grant.bits.g_type) - node T_567 = eq(T_562[1], io.inner.grant.bits.g_type) - node T_569 = or(UInt<1>("h00"), T_566) - node T_570 = or(T_569, T_567) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_560, T_570) - node T_590 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) - node T_591 = mux(T_590, UInt<3>("h01"), UInt<3>("h03")) - node T_592 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) - node T_593 = mux(T_592, UInt<3>("h01"), T_591) - node T_594 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h04"), T_593) - node T_596 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h03"), T_595) - node T_598 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h03"), T_597) - node T_600 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h05"), T_599) - node T_602 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h04"), T_601) - node T_604 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) - node T_607 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_608 = mux(T_607, UInt<1>("h00"), UInt<1>("h01")) - node T_609 = mux(T_604, T_608, UInt<1>("h01")) - node T_610 = mux(io.inner.acquire.bits.is_builtin_type, T_603, T_609) - wire T_619 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_619.client_id <= UInt<1>("h00") - T_619.data <= UInt<1>("h00") - T_619.g_type <= UInt<1>("h00") - T_619.is_builtin_type <= UInt<1>("h00") - T_619.manager_xact_id <= UInt<1>("h00") - T_619.client_xact_id <= UInt<1>("h00") - T_619.addr_beat <= UInt<1>("h00") - T_619.client_id <= io.inner.acquire.bits.client_id - T_619.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_619.g_type <= T_610 - T_619.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_619.manager_xact_id <= UInt<2>("h03") - T_619.addr_beat <= UInt<1>("h00") - T_619.data <= UInt<1>("h00") - wire T_637 : UInt<3>[2] - T_637[0] <= UInt<3>("h05") - T_637[1] <= UInt<3>("h04") - node T_641 = eq(T_637[0], T_619.g_type) - node T_642 = eq(T_637[1], T_619.g_type) - node T_644 = or(UInt<1>("h00"), T_641) - node T_645 = or(T_644, T_642) - wire T_647 : UInt<1>[2] - T_647[0] <= UInt<1>("h00") - T_647[1] <= UInt<1>("h01") - node T_651 = eq(T_647[0], T_619.g_type) - node T_652 = eq(T_647[1], T_619.g_type) - node T_654 = or(UInt<1>("h00"), T_651) - node T_655 = or(T_654, T_652) - node pending_outer_read_ = mux(T_619.is_builtin_type, T_645, T_655) - wire T_661 : UInt<3>[3] - T_661[0] <= UInt<3>("h02") - T_661[1] <= UInt<3>("h00") - T_661[2] <= UInt<3>("h04") - node T_666 = eq(T_661[0], xact.a_type) - node T_667 = eq(T_661[1], xact.a_type) - node T_668 = eq(T_661[2], xact.a_type) - node T_670 = or(UInt<1>("h00"), T_666) - node T_671 = or(T_670, T_667) - node T_672 = or(T_671, T_668) - node subblock_type = and(xact.is_builtin_type, T_672) - node T_674 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_675 = neq(state, UInt<1>("h00")) - node T_676 = and(T_674, T_675) - node T_678 = eq(collect_iacq_data, UInt<1>("h00")) - node T_679 = and(T_676, T_678) - io.has_acquire_conflict <= T_679 - node T_680 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_681 = and(T_680, collect_iacq_data) - io.has_acquire_match <= T_681 - node T_682 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_684 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) - node T_685 = and(T_682, T_684) - node T_686 = eq(state, UInt<1>("h01")) - node T_687 = and(T_685, T_686) - io.has_release_match <= T_687 - node T_692 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_698 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_410 = add(T_403, UInt<1>("h01")) + node T_411 = tail(T_410, 1) + node T_412 = mux(T_407, UInt<1>("h00"), T_411) + T_403 <= T_412 + skip + node T_413 = and(T_401, T_405) + node T_414 = mux(T_400, T_403, UInt<1>("h00")) + node irel_data_done = mux(T_400, T_413, T_384) + node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) + wire T_421 : UInt<3>[1] + T_421[0] <= UInt<3>("h05") + node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) + node T_426 = or(UInt<1>("h00"), T_424) + wire T_428 : UInt<1>[2] + T_428[0] <= UInt<1>("h00") + T_428[1] <= UInt<1>("h01") + node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) + node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) + node T_435 = or(UInt<1>("h00"), T_432) + node T_436 = or(T_435, T_433) + node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) + node T_438 = and(UInt<1>("h01"), T_437) + node T_439 = and(T_417, T_438) + reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_439 : + node T_443 = eq(T_441, UInt<2>("h03")) + node T_445 = and(UInt<1>("h00"), T_443) + node T_448 = add(T_441, UInt<1>("h01")) + node T_449 = tail(T_448, 1) + node T_450 = mux(T_445, UInt<1>("h00"), T_449) + T_441 <= T_450 + skip + node T_451 = and(T_439, T_443) + node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00")) + node ignt_data_done = mux(T_438, T_451, T_417) + node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) + wire T_460 : UInt<3>[1] + T_460[0] <= UInt<3>("h03") + node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) + node T_465 = or(UInt<1>("h00"), T_463) + node T_466 = and(T_457, T_465) + node T_467 = and(T_455, T_466) + reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_467 : + node T_471 = eq(T_469, UInt<2>("h03")) + node T_473 = and(UInt<1>("h00"), T_471) + node T_476 = add(T_469, UInt<1>("h01")) + node T_477 = tail(T_476, 1) + node T_478 = mux(T_473, UInt<1>("h00"), T_477) + T_469 <= T_478 + skip + node T_479 = and(T_467, T_471) + node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00")) + node oacq_data_done = mux(T_466, T_479, T_455) + node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_487 : UInt<3>[1] + T_487[0] <= UInt<3>("h05") + node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) + node T_492 = or(UInt<1>("h00"), T_490) + wire T_494 : UInt<1>[1] + T_494[0] <= UInt<1>("h00") + node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) + node T_499 = or(UInt<1>("h00"), T_497) + node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) + node T_501 = and(UInt<1>("h01"), T_500) + node T_502 = and(T_482, T_501) + reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_502 : + node T_506 = eq(T_504, UInt<2>("h03")) + node T_508 = and(UInt<1>("h00"), T_506) + node T_511 = add(T_504, UInt<1>("h01")) + node T_512 = tail(T_511, 1) + node T_513 = mux(T_508, UInt<1>("h00"), T_512) + T_504 <= T_513 + skip + node T_514 = and(T_502, T_506) + node T_515 = mux(T_501, T_504, UInt<1>("h00")) + node ognt_data_done = mux(T_501, T_514, T_482) + reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + wire T_523 : UInt<3>[3] + T_523[0] <= UInt<3>("h02") + T_523[1] <= UInt<3>("h03") + T_523[2] <= UInt<3>("h04") + node T_528 = eq(T_523[0], xact.a_type) + node T_529 = eq(T_523[1], xact.a_type) + node T_530 = eq(T_523[2], xact.a_type) + node T_532 = or(UInt<1>("h00"), T_528) + node T_533 = or(T_532, T_529) + node T_534 = or(T_533, T_530) + node pending_outer_write = and(xact.is_builtin_type, T_534) + wire T_540 : UInt<3>[3] + T_540[0] <= UInt<3>("h02") + T_540[1] <= UInt<3>("h03") + T_540[2] <= UInt<3>("h04") + node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) + node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) + node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) + node T_549 = or(UInt<1>("h00"), T_545) + node T_550 = or(T_549, T_546) + node T_551 = or(T_550, T_547) + node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) + wire T_556 : UInt<3>[2] + T_556[0] <= UInt<3>("h05") + T_556[1] <= UInt<3>("h04") + node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) + node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) + node T_563 = or(UInt<1>("h00"), T_560) + node T_564 = or(T_563, T_561) + wire T_566 : UInt<1>[2] + T_566[0] <= UInt<1>("h00") + T_566[1] <= UInt<1>("h01") + node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) + node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) + node T_573 = or(UInt<1>("h00"), T_570) + node T_574 = or(T_573, T_571) + node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) + node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) + node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03")) + node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) + node T_597 = mux(T_596, UInt<3>("h01"), T_595) + node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) + node T_599 = mux(T_598, UInt<3>("h04"), T_597) + node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) + node T_601 = mux(T_600, UInt<3>("h03"), T_599) + node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) + node T_603 = mux(T_602, UInt<3>("h03"), T_601) + node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) + node T_605 = mux(T_604, UInt<3>("h05"), T_603) + node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) + node T_607 = mux(T_606, UInt<3>("h04"), T_605) + node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) + node T_611 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01")) + node T_613 = mux(T_608, T_612, UInt<1>("h01")) + node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) + wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} + T_623 is invalid + T_623.client_id <= io.inner.acquire.bits.client_id + T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type + T_623.g_type <= T_614 + T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id + T_623.manager_xact_id <= UInt<2>("h03") + T_623.addr_beat <= UInt<1>("h00") + T_623.data <= UInt<1>("h00") + wire T_634 : UInt<3>[2] + T_634[0] <= UInt<3>("h05") + T_634[1] <= UInt<3>("h04") + node T_638 = eq(T_634[0], T_623.g_type) + node T_639 = eq(T_634[1], T_623.g_type) + node T_641 = or(UInt<1>("h00"), T_638) + node T_642 = or(T_641, T_639) + wire T_644 : UInt<1>[2] + T_644[0] <= UInt<1>("h00") + T_644[1] <= UInt<1>("h01") + node T_648 = eq(T_644[0], T_623.g_type) + node T_649 = eq(T_644[1], T_623.g_type) + node T_651 = or(UInt<1>("h00"), T_648) + node T_652 = or(T_651, T_649) + node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) + wire T_658 : UInt<3>[3] + T_658[0] <= UInt<3>("h02") + T_658[1] <= UInt<3>("h00") + T_658[2] <= UInt<3>("h04") + node T_663 = eq(T_658[0], xact.a_type) + node T_664 = eq(T_658[1], xact.a_type) + node T_665 = eq(T_658[2], xact.a_type) + node T_667 = or(UInt<1>("h00"), T_663) + node T_668 = or(T_667, T_664) + node T_669 = or(T_668, T_665) + node subblock_type = and(xact.is_builtin_type, T_669) + node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) + node T_672 = neq(state, UInt<1>("h00")) + node T_673 = and(T_671, T_672) + node T_675 = eq(collect_iacq_data, UInt<1>("h00")) + node T_676 = and(T_673, T_675) + io.has_acquire_conflict <= T_676 + node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) + node T_678 = and(T_677, collect_iacq_data) + io.has_acquire_match <= T_678 + node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) + node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) + node T_682 = and(T_679, T_681) + node T_683 = eq(state, UInt<1>("h01")) + node T_684 = and(T_682, T_683) + io.has_release_match <= T_684 + node T_689 = asUInt(asSInt(UInt<16>("h0ffff"))) + node T_695 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_696 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_697 = cat(T_695, T_696) node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_700 = cat(T_698, T_699) - node T_702 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_703 = cat(UInt<3>("h07"), T_702) - node T_705 = cat(T_692, UInt<1>("h01")) - node T_707 = cat(T_692, UInt<1>("h01")) - node T_709 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_710 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_711 = cat(T_709, T_710) - node T_713 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_715 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_716 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_717 = mux(T_716, T_715, UInt<1>("h00")) - node T_718 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_719 = mux(T_718, T_713, T_717) - node T_720 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_721 = mux(T_720, T_711, T_719) - node T_722 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_723 = mux(T_722, T_707, T_721) - node T_724 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_725 = mux(T_724, T_705, T_723) - node T_726 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_727 = mux(T_726, T_703, T_725) - node T_728 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_729 = mux(T_728, T_700, T_727) + node T_700 = cat(UInt<3>("h07"), T_699) + node T_702 = cat(T_689, UInt<1>("h01")) + node T_704 = cat(T_689, UInt<1>("h01")) + node T_706 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_707 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_708 = cat(T_706, T_707) + node T_710 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_712 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_713 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_714 = mux(T_713, T_712, UInt<1>("h00")) + node T_715 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_716 = mux(T_715, T_710, T_714) + node T_717 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_718 = mux(T_717, T_708, T_716) + node T_719 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_720 = mux(T_719, T_704, T_718) + node T_721 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_722 = mux(T_721, T_702, T_720) + node T_723 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_724 = mux(T_723, T_700, T_722) + node T_725 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_726 = mux(T_725, T_697, T_724) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe.data <= UInt<1>("h00") - oacq_probe.union <= UInt<1>("h00") - oacq_probe.a_type <= UInt<1>("h00") - oacq_probe.is_builtin_type <= UInt<1>("h00") - oacq_probe.addr_beat <= UInt<1>("h00") - oacq_probe.client_xact_id <= UInt<1>("h00") - oacq_probe.addr_block <= UInt<1>("h00") + oacq_probe is invalid oacq_probe.is_builtin_type <= UInt<1>("h01") oacq_probe.a_type <= UInt<3>("h03") oacq_probe.client_xact_id <= UInt<2>("h03") oacq_probe.addr_block <= io.inner.release.bits.addr_block oacq_probe.addr_beat <= io.inner.release.bits.addr_beat oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_729 - node T_754 = bits(xact.union, 12, 9) - node T_755 = bits(T_754, 3, 3) - node T_757 = dshl(UInt<1>("h01"), T_755) - node T_759 = eq(xact.a_type, UInt<3>("h04")) - node T_760 = and(xact.is_builtin_type, T_759) - node T_761 = bit(T_757, 0) - node T_762 = bit(T_757, 1) - wire T_764 : UInt<1>[2] - T_764[0] <= T_761 - T_764[1] <= T_762 - node T_769 = subw(UInt<8>("h00"), T_764[0]) - node T_771 = subw(UInt<8>("h00"), T_764[1]) - wire T_773 : UInt<8>[2] - T_773[0] <= T_769 - T_773[1] <= T_771 - node T_777 = cat(T_773[1], T_773[0]) - node T_779 = eq(xact.a_type, UInt<3>("h03")) - node T_780 = and(xact.is_builtin_type, T_779) - node T_782 = eq(xact.a_type, UInt<3>("h02")) - node T_783 = and(xact.is_builtin_type, T_782) - node T_784 = or(T_780, T_783) - node T_785 = bits(xact.union, 16, 1) - node T_787 = mux(T_784, T_785, UInt<16>("h00")) - node T_788 = mux(T_760, T_777, T_787) - node T_796 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_797 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_798 = cat(T_796, T_797) + oacq_probe.union <= T_726 + node T_744 = bits(xact.union, 12, 9) + node T_745 = bits(T_744, 3, 3) + node T_747 = dshl(UInt<1>("h01"), T_745) + node T_749 = eq(xact.a_type, UInt<3>("h04")) + node T_750 = and(xact.is_builtin_type, T_749) + node T_751 = bits(T_747, 0, 0) + node T_752 = bits(T_747, 1, 1) + wire T_754 : UInt<1>[2] + T_754[0] <= T_751 + T_754[1] <= T_752 + node T_759 = sub(UInt<8>("h00"), T_754[0]) + node T_760 = tail(T_759, 1) + node T_762 = sub(UInt<8>("h00"), T_754[1]) + node T_763 = tail(T_762, 1) + wire T_765 : UInt<8>[2] + T_765[0] <= T_760 + T_765[1] <= T_763 + node T_769 = cat(T_765[1], T_765[0]) + node T_771 = eq(xact.a_type, UInt<3>("h03")) + node T_772 = and(xact.is_builtin_type, T_771) + node T_774 = eq(xact.a_type, UInt<3>("h02")) + node T_775 = and(xact.is_builtin_type, T_774) + node T_776 = or(T_772, T_775) + node T_777 = bits(xact.union, 16, 1) + node T_779 = mux(T_776, T_777, UInt<16>("h00")) + node T_780 = mux(T_750, T_769, T_779) + node T_788 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_789 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_790 = cat(T_788, T_789) + node T_792 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_793 = cat(UInt<3>("h07"), T_792) + node T_795 = cat(T_780, UInt<1>("h01")) + node T_797 = cat(T_780, UInt<1>("h01")) + node T_799 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_801 = cat(UInt<3>("h07"), T_800) - node T_803 = cat(T_788, UInt<1>("h01")) - node T_805 = cat(T_788, UInt<1>("h01")) - node T_807 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_808 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_809 = cat(T_807, T_808) - node T_811 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_813 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_814 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_815 = mux(T_814, T_813, UInt<1>("h00")) - node T_816 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_817 = mux(T_816, T_811, T_815) - node T_818 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_819 = mux(T_818, T_809, T_817) - node T_820 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_821 = mux(T_820, T_805, T_819) - node T_822 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_823 = mux(T_822, T_803, T_821) - node T_824 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_825 = mux(T_824, T_801, T_823) - node T_826 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_827 = mux(T_826, T_798, T_825) + node T_801 = cat(T_799, T_800) + node T_803 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_805 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_806 = eq(UInt<3>("h06"), UInt<3>("h02")) + node T_807 = mux(T_806, T_805, UInt<1>("h00")) + node T_808 = eq(UInt<3>("h05"), UInt<3>("h02")) + node T_809 = mux(T_808, T_803, T_807) + node T_810 = eq(UInt<3>("h04"), UInt<3>("h02")) + node T_811 = mux(T_810, T_801, T_809) + node T_812 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_813 = mux(T_812, T_797, T_811) + node T_814 = eq(UInt<3>("h02"), UInt<3>("h02")) + node T_815 = mux(T_814, T_795, T_813) + node T_816 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_817 = mux(T_816, T_793, T_815) + node T_818 = eq(UInt<3>("h00"), UInt<3>("h02")) + node T_819 = mux(T_818, T_790, T_817) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat.data <= UInt<1>("h00") - oacq_write_beat.union <= UInt<1>("h00") - oacq_write_beat.a_type <= UInt<1>("h00") - oacq_write_beat.is_builtin_type <= UInt<1>("h00") - oacq_write_beat.addr_beat <= UInt<1>("h00") - oacq_write_beat.client_xact_id <= UInt<1>("h00") - oacq_write_beat.addr_block <= UInt<1>("h00") + oacq_write_beat is invalid oacq_write_beat.is_builtin_type <= UInt<1>("h01") oacq_write_beat.a_type <= UInt<3>("h02") oacq_write_beat.client_xact_id <= UInt<2>("h03") oacq_write_beat.addr_block <= xact.addr_block oacq_write_beat.addr_beat <= xact.addr_beat oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_827 - node T_861 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_862 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_863 = cat(T_861, T_862) - node T_865 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_866 = cat(UInt<3>("h07"), T_865) - node T_868 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_870 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_872 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_873 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_874 = cat(T_872, T_873) - node T_876 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_878 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_879 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_880 = mux(T_879, T_878, UInt<1>("h00")) - node T_881 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_882 = mux(T_881, T_876, T_880) - node T_883 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_884 = mux(T_883, T_874, T_882) - node T_885 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_886 = mux(T_885, T_870, T_884) - node T_887 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_888 = mux(T_887, T_868, T_886) - node T_889 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_890 = mux(T_889, T_866, T_888) - node T_891 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_892 = mux(T_891, T_863, T_890) + oacq_write_beat.union <= T_819 + node T_846 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_847 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_848 = cat(T_846, T_847) + node T_850 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_851 = cat(UInt<3>("h07"), T_850) + node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) + node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) + node T_857 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_858 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_859 = cat(T_857, T_858) + node T_861 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_863 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_864 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_865 = mux(T_864, T_863, UInt<1>("h00")) + node T_866 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_867 = mux(T_866, T_861, T_865) + node T_868 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_869 = mux(T_868, T_859, T_867) + node T_870 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_871 = mux(T_870, T_855, T_869) + node T_872 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_873 = mux(T_872, T_853, T_871) + node T_874 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_875 = mux(T_874, T_851, T_873) + node T_876 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_877 = mux(T_876, T_848, T_875) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block.data <= UInt<1>("h00") - oacq_write_block.union <= UInt<1>("h00") - oacq_write_block.a_type <= UInt<1>("h00") - oacq_write_block.is_builtin_type <= UInt<1>("h00") - oacq_write_block.addr_beat <= UInt<1>("h00") - oacq_write_block.client_xact_id <= UInt<1>("h00") - oacq_write_block.addr_block <= UInt<1>("h00") + oacq_write_block is invalid oacq_write_block.is_builtin_type <= UInt<1>("h01") oacq_write_block.a_type <= UInt<3>("h03") oacq_write_block.client_xact_id <= UInt<2>("h03") oacq_write_block.addr_block <= xact.addr_block oacq_write_block.addr_beat <= oacq_data_cnt oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_892 - node T_917 = bits(xact.union, 12, 9) - node T_918 = bits(xact.union, 8, 6) - node T_926 = cat(T_917, T_918) - node T_927 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_928 = cat(T_926, T_927) - node T_930 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_931 = cat(T_918, T_930) - node T_933 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_935 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_937 = cat(T_917, T_918) - node T_938 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_939 = cat(T_937, T_938) - node T_941 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_943 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_944 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_945 = mux(T_944, T_943, UInt<1>("h00")) - node T_946 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_947 = mux(T_946, T_941, T_945) - node T_948 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_949 = mux(T_948, T_939, T_947) - node T_950 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_951 = mux(T_950, T_935, T_949) - node T_952 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_953 = mux(T_952, T_933, T_951) - node T_954 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_955 = mux(T_954, T_931, T_953) - node T_956 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_957 = mux(T_956, T_928, T_955) + oacq_write_block.union <= T_877 + node T_895 = bits(xact.union, 12, 9) + node T_896 = bits(xact.union, 8, 6) + node T_904 = cat(T_895, T_896) + node T_905 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_906 = cat(T_904, T_905) + node T_908 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_909 = cat(T_896, T_908) + node T_911 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_913 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_915 = cat(T_895, T_896) + node T_916 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_917 = cat(T_915, T_916) + node T_919 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_921 = cat(UInt<5>("h01"), UInt<1>("h00")) + node T_922 = eq(UInt<3>("h06"), UInt<3>("h00")) + node T_923 = mux(T_922, T_921, UInt<1>("h00")) + node T_924 = eq(UInt<3>("h05"), UInt<3>("h00")) + node T_925 = mux(T_924, T_919, T_923) + node T_926 = eq(UInt<3>("h04"), UInt<3>("h00")) + node T_927 = mux(T_926, T_917, T_925) + node T_928 = eq(UInt<3>("h03"), UInt<3>("h00")) + node T_929 = mux(T_928, T_913, T_927) + node T_930 = eq(UInt<3>("h02"), UInt<3>("h00")) + node T_931 = mux(T_930, T_911, T_929) + node T_932 = eq(UInt<3>("h01"), UInt<3>("h00")) + node T_933 = mux(T_932, T_909, T_931) + node T_934 = eq(UInt<3>("h00"), UInt<3>("h00")) + node T_935 = mux(T_934, T_906, T_933) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= UInt<1>("h00") - oacq_read_beat.a_type <= UInt<1>("h00") - oacq_read_beat.is_builtin_type <= UInt<1>("h00") - oacq_read_beat.addr_beat <= UInt<1>("h00") - oacq_read_beat.client_xact_id <= UInt<1>("h00") - oacq_read_beat.addr_block <= UInt<1>("h00") + oacq_read_beat is invalid oacq_read_beat.is_builtin_type <= UInt<1>("h01") oacq_read_beat.a_type <= UInt<3>("h00") oacq_read_beat.client_xact_id <= UInt<2>("h03") oacq_read_beat.addr_block <= xact.addr_block oacq_read_beat.addr_beat <= xact.addr_beat oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= T_957 - node T_991 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_992 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_993 = cat(T_991, T_992) - node T_995 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_996 = cat(UInt<3>("h07"), T_995) - node T_998 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1000 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1002 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1003 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1004 = cat(T_1002, T_1003) - node T_1006 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1008 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1009 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_1010 = mux(T_1009, T_1008, UInt<1>("h00")) - node T_1011 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_1012 = mux(T_1011, T_1006, T_1010) - node T_1013 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_1014 = mux(T_1013, T_1004, T_1012) - node T_1015 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_1016 = mux(T_1015, T_1000, T_1014) - node T_1017 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_1018 = mux(T_1017, T_998, T_1016) - node T_1019 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_1020 = mux(T_1019, T_996, T_1018) - node T_1021 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_1022 = mux(T_1021, T_993, T_1020) + oacq_read_beat.union <= T_935 + node T_962 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_963 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_964 = cat(T_962, T_963) + node T_966 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_967 = cat(UInt<3>("h07"), T_966) + node T_969 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_971 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_973 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_974 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_975 = cat(T_973, T_974) + node T_977 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_979 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_980 = eq(UInt<3>("h06"), UInt<3>("h01")) + node T_981 = mux(T_980, T_979, UInt<1>("h00")) + node T_982 = eq(UInt<3>("h05"), UInt<3>("h01")) + node T_983 = mux(T_982, T_977, T_981) + node T_984 = eq(UInt<3>("h04"), UInt<3>("h01")) + node T_985 = mux(T_984, T_975, T_983) + node T_986 = eq(UInt<3>("h03"), UInt<3>("h01")) + node T_987 = mux(T_986, T_971, T_985) + node T_988 = eq(UInt<3>("h02"), UInt<3>("h01")) + node T_989 = mux(T_988, T_969, T_987) + node T_990 = eq(UInt<3>("h01"), UInt<3>("h01")) + node T_991 = mux(T_990, T_967, T_989) + node T_992 = eq(UInt<3>("h00"), UInt<3>("h01")) + node T_993 = mux(T_992, T_964, T_991) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= UInt<1>("h00") - oacq_read_block.a_type <= UInt<1>("h00") - oacq_read_block.is_builtin_type <= UInt<1>("h00") - oacq_read_block.addr_beat <= UInt<1>("h00") - oacq_read_block.client_xact_id <= UInt<1>("h00") - oacq_read_block.addr_block <= UInt<1>("h00") + oacq_read_block is invalid oacq_read_block.is_builtin_type <= UInt<1>("h01") oacq_read_block.a_type <= UInt<3>("h01") oacq_read_block.client_xact_id <= UInt<2>("h03") oacq_read_block.addr_block <= xact.addr_block oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= T_1022 + oacq_read_block.union <= T_993 io.outer.acquire.valid <= UInt<1>("h00") - node T_1047 = eq(state, UInt<1>("h01")) - node T_1048 = eq(state, UInt<2>("h03")) - wire T_1057 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1057 <- oacq_write_block - when subblock_type : - T_1057 <- oacq_write_beat - skip - wire T_1073 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1073 <- oacq_read_block - when subblock_type : - T_1073 <- oacq_read_beat - skip - wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1089 <- T_1073 - when T_1048 : - T_1089 <- T_1057 - skip - wire T_1105 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1105 <- T_1089 - when T_1047 : - T_1105 <- oacq_probe - skip - io.outer.acquire.bits <- T_1105 + node T_1011 = eq(state, UInt<1>("h01")) + node T_1012 = eq(state, UInt<2>("h03")) + node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) + node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) + node T_1029 = mux(T_1012, T_1013, T_1021) + node T_1037 = mux(T_1011, oacq_probe, T_1029) + io.outer.acquire.bits <- T_1037 io.outer.grant.ready <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") - node T_1122 = eq(UInt<3>("h04"), xact.a_type) - node T_1123 = mux(T_1122, UInt<1>("h00"), UInt<2>("h02")) - node T_1124 = eq(UInt<3>("h06"), xact.a_type) - node T_1125 = mux(T_1124, UInt<1>("h00"), T_1123) - node T_1126 = eq(UInt<3>("h05"), xact.a_type) - node T_1127 = mux(T_1126, UInt<2>("h02"), T_1125) - node T_1128 = eq(UInt<3>("h02"), xact.a_type) - node T_1129 = mux(T_1128, UInt<1>("h00"), T_1127) - node T_1130 = eq(UInt<3>("h00"), xact.a_type) - node T_1131 = mux(T_1130, UInt<2>("h02"), T_1129) - node T_1132 = eq(UInt<3>("h03"), xact.a_type) - node T_1133 = mux(T_1132, UInt<1>("h00"), T_1131) - node T_1134 = eq(UInt<3>("h01"), xact.a_type) - node T_1135 = mux(T_1134, UInt<2>("h02"), T_1133) - node T_1136 = eq(UInt<1>("h01"), xact.a_type) - node T_1137 = mux(T_1136, UInt<1>("h00"), UInt<2>("h02")) - node T_1138 = eq(UInt<1>("h00"), xact.a_type) - node T_1139 = mux(T_1138, UInt<1>("h01"), T_1137) - node T_1140 = mux(xact.is_builtin_type, T_1135, T_1139) - wire T_1145 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1145.client_id <= UInt<1>("h00") - T_1145.p_type <= UInt<1>("h00") - T_1145.addr_block <= UInt<1>("h00") - T_1145.client_id <= UInt<1>("h00") - T_1145.p_type <= T_1140 - T_1145.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1145 + node T_1054 = eq(UInt<3>("h04"), xact.a_type) + node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02")) + node T_1056 = eq(UInt<3>("h06"), xact.a_type) + node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055) + node T_1058 = eq(UInt<3>("h05"), xact.a_type) + node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057) + node T_1060 = eq(UInt<3>("h02"), xact.a_type) + node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059) + node T_1062 = eq(UInt<3>("h00"), xact.a_type) + node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061) + node T_1064 = eq(UInt<3>("h03"), xact.a_type) + node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063) + node T_1066 = eq(UInt<3>("h01"), xact.a_type) + node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065) + node T_1068 = eq(UInt<1>("h01"), xact.a_type) + node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02")) + node T_1070 = eq(UInt<1>("h00"), xact.a_type) + node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069) + node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) + wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} + T_1077 is invalid + T_1077.client_id <= UInt<1>("h00") + T_1077.p_type <= T_1072 + T_1077.addr_block <= xact.addr_block + io.inner.probe.bits <- T_1077 io.inner.grant.valid <= UInt<1>("h00") - node T_1171 = eq(UInt<3>("h06"), xact.a_type) - node T_1172 = mux(T_1171, UInt<3>("h01"), UInt<3>("h03")) - node T_1173 = eq(UInt<3>("h05"), xact.a_type) - node T_1174 = mux(T_1173, UInt<3>("h01"), T_1172) - node T_1175 = eq(UInt<3>("h04"), xact.a_type) - node T_1176 = mux(T_1175, UInt<3>("h04"), T_1174) - node T_1177 = eq(UInt<3>("h03"), xact.a_type) - node T_1178 = mux(T_1177, UInt<3>("h03"), T_1176) - node T_1179 = eq(UInt<3>("h02"), xact.a_type) - node T_1180 = mux(T_1179, UInt<3>("h03"), T_1178) - node T_1181 = eq(UInt<3>("h01"), xact.a_type) - node T_1182 = mux(T_1181, UInt<3>("h05"), T_1180) - node T_1183 = eq(UInt<3>("h00"), xact.a_type) - node T_1184 = mux(T_1183, UInt<3>("h04"), T_1182) - node T_1185 = eq(xact.a_type, UInt<1>("h00")) - node T_1188 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1189 = mux(T_1188, UInt<1>("h00"), UInt<1>("h01")) - node T_1190 = mux(T_1185, T_1189, UInt<1>("h01")) - node T_1191 = mux(xact.is_builtin_type, T_1184, T_1190) - wire T_1200 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1200.client_id <= UInt<1>("h00") - T_1200.data <= UInt<1>("h00") - T_1200.g_type <= UInt<1>("h00") - T_1200.is_builtin_type <= UInt<1>("h00") - T_1200.manager_xact_id <= UInt<1>("h00") - T_1200.client_xact_id <= UInt<1>("h00") - T_1200.addr_beat <= UInt<1>("h00") - T_1200.client_id <= xact.client_id - T_1200.is_builtin_type <= xact.is_builtin_type - T_1200.g_type <= T_1191 - T_1200.client_xact_id <= xact.client_xact_id - T_1200.manager_xact_id <= UInt<2>("h03") - T_1200.addr_beat <= UInt<1>("h00") - T_1200.data <= UInt<1>("h00") - io.inner.grant.bits <- T_1200 + node T_1100 = eq(UInt<3>("h06"), xact.a_type) + node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03")) + node T_1102 = eq(UInt<3>("h05"), xact.a_type) + node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101) + node T_1104 = eq(UInt<3>("h04"), xact.a_type) + node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103) + node T_1106 = eq(UInt<3>("h03"), xact.a_type) + node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105) + node T_1108 = eq(UInt<3>("h02"), xact.a_type) + node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107) + node T_1110 = eq(UInt<3>("h01"), xact.a_type) + node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109) + node T_1112 = eq(UInt<3>("h00"), xact.a_type) + node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111) + node T_1114 = eq(xact.a_type, UInt<1>("h00")) + node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01")) + node T_1119 = mux(T_1114, T_1118, UInt<1>("h01")) + node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) + wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} + T_1129 is invalid + T_1129.client_id <= xact.client_id + T_1129.is_builtin_type <= xact.is_builtin_type + T_1129.g_type <= T_1120 + T_1129.client_xact_id <= xact.client_xact_id + T_1129.manager_xact_id <= UInt<2>("h03") + T_1129.addr_beat <= UInt<1>("h00") + T_1129.data <= UInt<1>("h00") + io.inner.grant.bits <- T_1129 io.inner.acquire.ready <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") - node T_1218 = neq(state, UInt<1>("h00")) - node T_1219 = and(T_1218, collect_iacq_data) - node T_1220 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1221 = and(T_1219, T_1220) - node T_1222 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1223 = and(T_1221, T_1222) - node T_1225 = eq(T_1223, UInt<1>("h00")) - node T_1227 = eq(reset, UInt<1>("h00")) - when T_1227 : - node T_1229 = eq(T_1225, UInt<1>("h00")) - when T_1229 : - node T_1231 = eq(reset, UInt<1>("h00")) - when T_1231 : + node T_1140 = neq(state, UInt<1>("h00")) + node T_1141 = and(T_1140, collect_iacq_data) + node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1143 = and(T_1141, T_1142) + node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) + node T_1145 = and(T_1143, T_1144) + node T_1147 = eq(T_1145, UInt<1>("h00")) + node T_1149 = eq(reset, UInt<1>("h00")) + when T_1149 : + node T_1151 = eq(T_1147, UInt<1>("h00")) + when T_1151 : + node T_1153 = eq(reset, UInt<1>("h00")) + when T_1153 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1232 = neq(state, UInt<1>("h00")) - node T_1233 = and(T_1232, collect_iacq_data) - node T_1234 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1235 = and(T_1233, T_1234) - node T_1236 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1237 = and(T_1235, T_1236) - node T_1239 = eq(T_1237, UInt<1>("h00")) - node T_1241 = eq(reset, UInt<1>("h00")) - when T_1241 : - node T_1243 = eq(T_1239, UInt<1>("h00")) - when T_1243 : - node T_1245 = eq(reset, UInt<1>("h00")) - when T_1245 : + node T_1154 = neq(state, UInt<1>("h00")) + node T_1155 = and(T_1154, collect_iacq_data) + node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1157 = and(T_1155, T_1156) + node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) + node T_1159 = and(T_1157, T_1158) + node T_1161 = eq(T_1159, UInt<1>("h00")) + node T_1163 = eq(reset, UInt<1>("h00")) + when T_1163 : + node T_1165 = eq(T_1161, UInt<1>("h00")) + when T_1165 : + node T_1167 = eq(reset, UInt<1>("h00")) + when T_1167 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1246 = eq(state, UInt<1>("h00")) - node T_1247 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1248 = and(T_1246, T_1247) - node T_1250 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1253 : UInt<3>[1] - T_1253[0] <= UInt<3>("h03") - node T_1256 = eq(T_1253[0], io.inner.acquire.bits.a_type) - node T_1258 = or(UInt<1>("h00"), T_1256) - node T_1259 = and(T_1250, T_1258) - node T_1260 = and(T_1248, T_1259) - node T_1262 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1263 = and(T_1260, T_1262) - node T_1265 = eq(T_1263, UInt<1>("h00")) - node T_1267 = eq(reset, UInt<1>("h00")) - when T_1267 : - node T_1269 = eq(T_1265, UInt<1>("h00")) - when T_1269 : - node T_1271 = eq(reset, UInt<1>("h00")) - when T_1271 : + node T_1168 = eq(state, UInt<1>("h00")) + node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1170 = and(T_1168, T_1169) + node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_1175 : UInt<3>[1] + T_1175[0] <= UInt<3>("h03") + node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) + node T_1180 = or(UInt<1>("h00"), T_1178) + node T_1181 = and(T_1172, T_1180) + node T_1182 = and(T_1170, T_1181) + node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) + node T_1185 = and(T_1182, T_1184) + node T_1187 = eq(T_1185, UInt<1>("h00")) + node T_1189 = eq(reset, UInt<1>("h00")) + when T_1189 : + node T_1191 = eq(T_1187, UInt<1>("h00")) + when T_1191 : + node T_1193 = eq(reset, UInt<1>("h00")) + when T_1193 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") skip stop(clk, UInt<1>(1), 1) @@ -5549,38 +4271,40 @@ circuit Top : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1275 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1276 = bits(T_1275, 3, 3) - node T_1278 = dshl(UInt<1>("h01"), T_1276) - node T_1280 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1281 = and(io.inner.acquire.bits.is_builtin_type, T_1280) - node T_1282 = bit(T_1278, 0) - node T_1283 = bit(T_1278, 1) - wire T_1285 : UInt<1>[2] - T_1285[0] <= T_1282 - T_1285[1] <= T_1283 - node T_1290 = subw(UInt<8>("h00"), T_1285[0]) - node T_1292 = subw(UInt<8>("h00"), T_1285[1]) - wire T_1294 : UInt<8>[2] - T_1294[0] <= T_1290 - T_1294[1] <= T_1292 - node T_1298 = cat(T_1294[1], T_1294[0]) - node T_1300 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1301 = and(io.inner.acquire.bits.is_builtin_type, T_1300) - node T_1303 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1304 = and(io.inner.acquire.bits.is_builtin_type, T_1303) - node T_1305 = or(T_1301, T_1304) - node T_1306 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1308 = mux(T_1305, T_1306, UInt<16>("h00")) - node T_1309 = mux(T_1281, T_1298, T_1308) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1309 - node T_1312 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) - node T_1313 = or(iacq_data_valid, T_1312) - node T_1314 = not(iacq_data_valid) - node T_1315 = or(T_1314, T_1312) - node T_1316 = not(T_1315) - node T_1317 = mux(UInt<1>("h01"), T_1313, T_1316) - iacq_data_valid <= T_1317 + node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) + node T_1198 = bits(T_1197, 3, 3) + node T_1200 = dshl(UInt<1>("h01"), T_1198) + node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) + node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) + node T_1204 = bits(T_1200, 0, 0) + node T_1205 = bits(T_1200, 1, 1) + wire T_1207 : UInt<1>[2] + T_1207[0] <= T_1204 + T_1207[1] <= T_1205 + node T_1212 = sub(UInt<8>("h00"), T_1207[0]) + node T_1213 = tail(T_1212, 1) + node T_1215 = sub(UInt<8>("h00"), T_1207[1]) + node T_1216 = tail(T_1215, 1) + wire T_1218 : UInt<8>[2] + T_1218[0] <= T_1213 + T_1218[1] <= T_1216 + node T_1222 = cat(T_1218[1], T_1218[0]) + node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) + node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) + node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) + node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) + node T_1229 = or(T_1225, T_1228) + node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) + node T_1232 = mux(T_1229, T_1230, UInt<16>("h00")) + node T_1233 = mux(T_1203, T_1222, T_1232) + xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 + node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) + node T_1237 = or(iacq_data_valid, T_1236) + node T_1238 = not(iacq_data_valid) + node T_1239 = or(T_1238, T_1236) + node T_1240 = not(T_1239) + node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240) + iacq_data_valid <= T_1241 skip when iacq_data_done : collect_iacq_data <= UInt<1>("h00") @@ -5592,194 +4316,201 @@ circuit Top : pending_ognt_ack <= UInt<1>("h00") skip skip - node T_1321 = eq(UInt<1>("h00"), state) - when T_1321 : + node T_1245 = eq(UInt<1>("h00"), state) + when T_1245 : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact <- io.inner.acquire.bits xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data - node T_1327 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1328 = bits(T_1327, 3, 3) - node T_1330 = dshl(UInt<1>("h01"), T_1328) - node T_1332 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1333 = and(io.inner.acquire.bits.is_builtin_type, T_1332) - node T_1334 = bit(T_1330, 0) - node T_1335 = bit(T_1330, 1) - wire T_1337 : UInt<1>[2] - T_1337[0] <= T_1334 - T_1337[1] <= T_1335 - node T_1342 = subw(UInt<8>("h00"), T_1337[0]) - node T_1344 = subw(UInt<8>("h00"), T_1337[1]) - wire T_1346 : UInt<8>[2] - T_1346[0] <= T_1342 - T_1346[1] <= T_1344 - node T_1350 = cat(T_1346[1], T_1346[0]) - node T_1352 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1353 = and(io.inner.acquire.bits.is_builtin_type, T_1352) - node T_1355 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1356 = and(io.inner.acquire.bits.is_builtin_type, T_1355) - node T_1357 = or(T_1353, T_1356) - node T_1358 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1360 = mux(T_1357, T_1358, UInt<16>("h00")) - node T_1361 = mux(T_1333, T_1350, T_1360) - xact.wmask_buffer[UInt<1>("h00")] <= T_1361 - node T_1363 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1366 : UInt<3>[1] - T_1366[0] <= UInt<3>("h03") - node T_1369 = eq(T_1366[0], io.inner.acquire.bits.a_type) - node T_1371 = or(UInt<1>("h00"), T_1369) - node T_1372 = and(T_1363, T_1371) - collect_iacq_data <= T_1372 - wire T_1377 : UInt<3>[3] - T_1377[0] <= UInt<3>("h02") - T_1377[1] <= UInt<3>("h03") - T_1377[2] <= UInt<3>("h04") - node T_1382 = eq(T_1377[0], io.inner.acquire.bits.a_type) - node T_1383 = eq(T_1377[1], io.inner.acquire.bits.a_type) - node T_1384 = eq(T_1377[2], io.inner.acquire.bits.a_type) - node T_1386 = or(UInt<1>("h00"), T_1382) - node T_1387 = or(T_1386, T_1383) - node T_1388 = or(T_1387, T_1384) - node T_1389 = and(io.inner.acquire.bits.is_builtin_type, T_1388) - node T_1390 = dshl(T_1389, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1390 - node T_1392 = neq(mask_incoherent, UInt<1>("h00")) - when T_1392 : + node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) + node T_1252 = bits(T_1251, 3, 3) + node T_1254 = dshl(UInt<1>("h01"), T_1252) + node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) + node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) + node T_1258 = bits(T_1254, 0, 0) + node T_1259 = bits(T_1254, 1, 1) + wire T_1261 : UInt<1>[2] + T_1261[0] <= T_1258 + T_1261[1] <= T_1259 + node T_1266 = sub(UInt<8>("h00"), T_1261[0]) + node T_1267 = tail(T_1266, 1) + node T_1269 = sub(UInt<8>("h00"), T_1261[1]) + node T_1270 = tail(T_1269, 1) + wire T_1272 : UInt<8>[2] + T_1272[0] <= T_1267 + T_1272[1] <= T_1270 + node T_1276 = cat(T_1272[1], T_1272[0]) + node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) + node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) + node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) + node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) + node T_1283 = or(T_1279, T_1282) + node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) + node T_1286 = mux(T_1283, T_1284, UInt<16>("h00")) + node T_1287 = mux(T_1257, T_1276, T_1286) + xact.wmask_buffer[UInt<1>("h00")] <= T_1287 + node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_1292 : UInt<3>[1] + T_1292[0] <= UInt<3>("h03") + node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) + node T_1297 = or(UInt<1>("h00"), T_1295) + node T_1298 = and(T_1289, T_1297) + collect_iacq_data <= T_1298 + wire T_1303 : UInt<3>[3] + T_1303[0] <= UInt<3>("h02") + T_1303[1] <= UInt<3>("h03") + T_1303[2] <= UInt<3>("h04") + node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) + node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) + node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) + node T_1312 = or(UInt<1>("h00"), T_1308) + node T_1313 = or(T_1312, T_1309) + node T_1314 = or(T_1313, T_1310) + node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) + node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) + iacq_data_valid <= T_1316 + node T_1318 = neq(mask_incoherent, UInt<1>("h00")) + when T_1318 : pending_probes <= mask_incoherent - node T_1393 = bit(mask_incoherent, 0) - node T_1394 = bit(mask_incoherent, 1) - node T_1395 = bit(mask_incoherent, 2) - node T_1396 = bit(mask_incoherent, 3) - node T_1398 = cat(UInt<1>("h00"), T_1394) - node T_1399 = addw(T_1393, T_1398) - node T_1402 = cat(UInt<1>("h00"), T_1396) - node T_1403 = addw(T_1395, T_1402) - node T_1404 = cat(UInt<1>("h00"), T_1403) - node T_1405 = addw(T_1399, T_1404) - release_count <= T_1405 + node T_1319 = bits(mask_incoherent, 0, 0) + node T_1320 = bits(mask_incoherent, 1, 1) + node T_1321 = bits(mask_incoherent, 2, 2) + node T_1322 = bits(mask_incoherent, 3, 3) + node T_1324 = cat(UInt<1>("h00"), T_1320) + node T_1325 = add(T_1319, T_1324) + node T_1326 = tail(T_1325, 1) + node T_1329 = cat(UInt<1>("h00"), T_1322) + node T_1330 = add(T_1321, T_1329) + node T_1331 = tail(T_1330, 1) + node T_1332 = cat(UInt<1>("h00"), T_1331) + node T_1333 = add(T_1326, T_1332) + node T_1334 = tail(T_1333, 1) + release_count <= T_1334 skip - node T_1406 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_1407 = mux(pending_outer_write_, UInt<2>("h03"), T_1406) - node T_1408 = mux(T_1392, UInt<1>("h01"), T_1407) - state <= T_1408 + node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) + node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335) + node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336) + state <= T_1337 skip skip - node T_1409 = eq(UInt<1>("h01"), state) - when T_1409 : - node T_1411 = neq(pending_probes, UInt<1>("h00")) - io.inner.probe.valid <= T_1411 + node T_1338 = eq(UInt<1>("h01"), state) + when T_1338 : + node T_1340 = neq(pending_probes, UInt<1>("h00")) + io.inner.probe.valid <= T_1340 when io.inner.probe.ready : - node T_1413 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_1414 = not(T_1413) - node T_1415 = and(pending_probes, T_1414) - pending_probes <= T_1415 - skip - wire T_1417 : UInt<2>[3] - T_1417[0] <= UInt<1>("h00") - T_1417[1] <= UInt<1>("h01") - T_1417[2] <= UInt<2>("h02") - node T_1422 = eq(T_1417[0], io.inner.release.bits.r_type) - node T_1423 = eq(T_1417[1], io.inner.release.bits.r_type) - node T_1424 = eq(T_1417[2], io.inner.release.bits.r_type) - node T_1426 = or(UInt<1>("h00"), T_1422) - node T_1427 = or(T_1426, T_1423) - node T_1428 = or(T_1427, T_1424) - node T_1430 = eq(T_1428, UInt<1>("h00")) - node T_1431 = or(T_1430, io.outer.acquire.ready) - io.inner.release.ready <= T_1431 + node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00")) + node T_1343 = not(T_1342) + node T_1344 = and(pending_probes, T_1343) + pending_probes <= T_1344 + skip + wire T_1346 : UInt<2>[3] + T_1346[0] <= UInt<1>("h00") + T_1346[1] <= UInt<1>("h01") + T_1346[2] <= UInt<2>("h02") + node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) + node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) + node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) + node T_1355 = or(UInt<1>("h00"), T_1351) + node T_1356 = or(T_1355, T_1352) + node T_1357 = or(T_1356, T_1353) + node T_1359 = eq(T_1357, UInt<1>("h00")) + node T_1360 = or(T_1359, io.outer.acquire.ready) + io.inner.release.ready <= T_1360 when io.inner.release.valid : - wire T_1433 : UInt<2>[3] - T_1433[0] <= UInt<1>("h00") - T_1433[1] <= UInt<1>("h01") - T_1433[2] <= UInt<2>("h02") - node T_1438 = eq(T_1433[0], io.inner.release.bits.r_type) - node T_1439 = eq(T_1433[1], io.inner.release.bits.r_type) - node T_1440 = eq(T_1433[2], io.inner.release.bits.r_type) - node T_1442 = or(UInt<1>("h00"), T_1438) - node T_1443 = or(T_1442, T_1439) - node T_1444 = or(T_1443, T_1440) - when T_1444 : + wire T_1362 : UInt<2>[3] + T_1362[0] <= UInt<1>("h00") + T_1362[1] <= UInt<1>("h01") + T_1362[2] <= UInt<2>("h02") + node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) + node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) + node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) + node T_1371 = or(UInt<1>("h00"), T_1367) + node T_1372 = or(T_1371, T_1368) + node T_1373 = or(T_1372, T_1369) + when T_1373 : io.outer.acquire.valid <= UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") - node T_1448 = subw(release_count, UInt<1>("h01")) - release_count <= T_1448 - node T_1450 = eq(release_count, UInt<1>("h01")) - when T_1450 : - node T_1451 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1452 = mux(pending_outer_write, UInt<2>("h03"), T_1451) - state <= T_1452 + node T_1377 = sub(release_count, UInt<1>("h01")) + node T_1378 = tail(T_1377, 1) + release_count <= T_1378 + node T_1380 = eq(release_count, UInt<1>("h01")) + when T_1380 : + node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381) + state <= T_1382 skip skip skip skip - node T_1454 = eq(T_1444, UInt<1>("h00")) - when T_1454 : - node T_1456 = subw(release_count, UInt<1>("h01")) - release_count <= T_1456 - node T_1458 = eq(release_count, UInt<1>("h01")) - when T_1458 : - node T_1459 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1460 = mux(pending_outer_write, UInt<2>("h03"), T_1459) - state <= T_1460 + node T_1384 = eq(T_1373, UInt<1>("h00")) + when T_1384 : + node T_1386 = sub(release_count, UInt<1>("h01")) + node T_1387 = tail(T_1386, 1) + release_count <= T_1387 + node T_1389 = eq(release_count, UInt<1>("h01")) + when T_1389 : + node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390) + state <= T_1391 skip skip skip skip - node T_1461 = eq(UInt<2>("h03"), state) - when T_1461 : - node T_1463 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_1465 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1466 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1467 = bit(T_1466, 0) - node T_1468 = or(T_1465, T_1467) - node T_1469 = and(T_1463, T_1468) - io.outer.acquire.valid <= T_1469 + node T_1392 = eq(UInt<2>("h03"), state) + when T_1392 : + node T_1394 = eq(pending_ognt_ack, UInt<1>("h00")) + node T_1396 = eq(collect_iacq_data, UInt<1>("h00")) + node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) + node T_1398 = bits(T_1397, 0, 0) + node T_1399 = or(T_1396, T_1398) + node T_1400 = and(T_1394, T_1399) + io.outer.acquire.valid <= T_1400 when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") - node T_1471 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state <= T_1471 + node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) + state <= T_1402 skip skip - node T_1472 = eq(UInt<2>("h02"), state) - when T_1472 : - node T_1474 = eq(pending_ognt_ack, UInt<1>("h00")) - io.outer.acquire.valid <= T_1474 - node T_1475 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1475 : + node T_1403 = eq(UInt<2>("h02"), state) + when T_1403 : + node T_1405 = eq(pending_ognt_ack, UInt<1>("h00")) + io.outer.acquire.valid <= T_1405 + node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) + when T_1406 : state <= UInt<3>("h05") skip skip - node T_1476 = eq(UInt<3>("h05"), state) - when T_1476 : + node T_1407 = eq(UInt<3>("h05"), state) + when T_1407 : io.outer.grant.ready <= io.inner.grant.ready io.inner.grant.valid <= io.outer.grant.valid when ignt_data_done : - node T_1479 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1481 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1482 = and(io.inner.grant.bits.is_builtin_type, T_1481) - node T_1484 = eq(T_1482, UInt<1>("h00")) - node T_1485 = and(T_1479, T_1484) - node T_1486 = mux(T_1485, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1486 + node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) + node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) + node T_1415 = eq(T_1413, UInt<1>("h00")) + node T_1416 = and(T_1410, T_1415) + node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00")) + state <= T_1417 skip skip - node T_1487 = eq(UInt<3>("h04"), state) - when T_1487 : + node T_1418 = eq(UInt<3>("h04"), state) + when T_1418 : io.inner.grant.valid <= UInt<1>("h01") when io.inner.grant.ready : - node T_1491 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1493 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1494 = and(io.inner.grant.bits.is_builtin_type, T_1493) - node T_1496 = eq(T_1494, UInt<1>("h00")) - node T_1497 = and(T_1491, T_1496) - node T_1498 = mux(T_1497, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1498 + node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) + node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) + node T_1427 = eq(T_1425, UInt<1>("h00")) + node T_1428 = and(T_1422, T_1427) + node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00")) + state <= T_1429 skip skip - node T_1499 = eq(UInt<3>("h06"), state) - when T_1499 : + node T_1430 = eq(UInt<3>("h06"), state) + when T_1430 : io.inner.finish.ready <= UInt<1>("h01") when io.inner.finish.valid : state <= UInt<1>("h00") @@ -5791,98 +4522,73 @@ circuit Top : input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - io.has_release_match <= UInt<1>("h00") - io.has_acquire_match <= UInt<1>("h00") - io.has_acquire_conflict <= UInt<1>("h00") - io.outer.grant.ready <= UInt<1>("h00") - io.outer.acquire.bits.data <= UInt<1>("h00") - io.outer.acquire.bits.union <= UInt<1>("h00") - io.outer.acquire.bits.a_type <= UInt<1>("h00") - io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.outer.acquire.bits.addr_beat <= UInt<1>("h00") - io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") - io.outer.acquire.bits.addr_block <= UInt<1>("h00") - io.outer.acquire.valid <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.probe.bits.client_id <= UInt<1>("h00") - io.inner.probe.bits.p_type <= UInt<1>("h00") - io.inner.probe.bits.addr_block <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - io.inner.grant.bits.client_id <= UInt<1>("h00") - io.inner.grant.bits.data <= UInt<1>("h00") - io.inner.grant.bits.g_type <= UInt<1>("h00") - io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") - io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") - io.inner.grant.bits.client_xact_id <= UInt<1>("h00") - io.inner.grant.bits.addr_beat <= UInt<1>("h00") - io.inner.grant.valid <= UInt<1>("h00") - io.inner.acquire.ready <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk, UInt<1>("h00"), xact + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk wire coh : {sharers : UInt<1>} + coh is invalid coh.sharers <= UInt<1>("h00") - coh.sharers <= UInt<1>("h00") - node T_304 = neq(state, UInt<1>("h00")) - node T_305 = and(T_304, xact.is_builtin_type) - wire T_310 : UInt<3>[3] - T_310[0] <= UInt<3>("h04") - T_310[1] <= UInt<3>("h05") - T_310[2] <= UInt<3>("h06") - node T_315 = eq(T_310[0], xact.a_type) - node T_316 = eq(T_310[1], xact.a_type) - node T_317 = eq(T_310[2], xact.a_type) - node T_319 = or(UInt<1>("h00"), T_315) + node T_303 = neq(state, UInt<1>("h00")) + node T_304 = and(T_303, xact.is_builtin_type) + wire T_309 : UInt<3>[3] + T_309[0] <= UInt<3>("h04") + T_309[1] <= UInt<3>("h05") + T_309[2] <= UInt<3>("h06") + node T_314 = eq(T_309[0], xact.a_type) + node T_315 = eq(T_309[1], xact.a_type) + node T_316 = eq(T_309[2], xact.a_type) + node T_318 = or(UInt<1>("h00"), T_314) + node T_319 = or(T_318, T_315) node T_320 = or(T_319, T_316) - node T_321 = or(T_320, T_317) - node T_322 = and(T_305, T_321) - node T_324 = eq(T_322, UInt<1>("h00")) - node T_326 = eq(reset, UInt<1>("h00")) - when T_326 : - node T_328 = eq(T_324, UInt<1>("h00")) - when T_328 : - node T_330 = eq(reset, UInt<1>("h00")) - when T_330 : + node T_321 = and(T_304, T_320) + node T_323 = eq(T_321, UInt<1>("h00")) + node T_325 = eq(reset, UInt<1>("h00")) + when T_325 : + node T_327 = eq(T_323, UInt<1>("h00")) + when T_327 : + node T_329 = eq(reset, UInt<1>("h00")) + when T_329 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") skip stop(clk, UInt<1>(1), 1) skip skip - reg release_count : UInt<1>, clk, reset, UInt<1>("h00") - reg pending_probes : UInt<1>, clk, reset, UInt<1>("h00") - node T_335 = bit(pending_probes, 0) - wire T_337 : UInt<1>[1] - T_337[0] <= T_335 - node T_342 = asUInt(asSInt(UInt<1>("h01"))) - node T_345 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) - node T_346 = or(T_342, T_345) - node T_347 = not(T_342) - node T_348 = or(T_347, T_345) - node T_349 = not(T_348) - node mask_self = mux(UInt<1>("h00"), T_346, T_349) - node T_351 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_351) - reg collect_iacq_data : UInt<1>, clk, reset, UInt<1>("h00") - reg iacq_data_valid : UInt<4>, clk, reset, UInt<4>("h00") - node T_357 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_360 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_363 : UInt<3>[1] - T_363[0] <= UInt<3>("h03") - node T_366 = eq(T_363[0], io.inner.acquire.bits.a_type) - node T_368 = or(UInt<1>("h00"), T_366) - node T_369 = and(T_360, T_368) - node T_370 = and(T_357, T_369) - reg T_372 : UInt<2>, clk, reset, UInt<2>("h00") - when T_370 : - node T_374 = eq(T_372, UInt<2>("h03")) - node T_376 = and(UInt<1>("h00"), T_374) - node T_379 = addw(T_372, UInt<1>("h01")) - node T_380 = mux(T_376, UInt<1>("h00"), T_379) - T_372 <= T_380 - skip - node T_381 = and(T_370, T_374) - node T_382 = mux(T_369, T_372, UInt<1>("h00")) - node iacq_data_done = mux(T_369, T_381, T_357) + reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_334 = bits(pending_probes, 0, 0) + wire T_336 : UInt<1>[1] + T_336[0] <= T_334 + node T_341 = asUInt(asSInt(UInt<1>("h01"))) + node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) + node T_345 = or(T_341, T_344) + node T_346 = not(T_341) + node T_347 = or(T_346, T_344) + node T_348 = not(T_347) + node mask_self = mux(UInt<1>("h00"), T_345, T_348) + node T_350 = not(io.incoherent[0]) + node mask_incoherent = and(mask_self, T_350) + reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) + node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_362 : UInt<3>[1] + T_362[0] <= UInt<3>("h03") + node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) + node T_367 = or(UInt<1>("h00"), T_365) + node T_368 = and(T_359, T_367) + node T_369 = and(T_356, T_368) + reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_369 : + node T_373 = eq(T_371, UInt<2>("h03")) + node T_375 = and(UInt<1>("h00"), T_373) + node T_378 = add(T_371, UInt<1>("h01")) + node T_379 = tail(T_378, 1) + node T_380 = mux(T_375, UInt<1>("h00"), T_379) + T_371 <= T_380 + skip + node T_381 = and(T_369, T_373) + node T_382 = mux(T_368, T_371, UInt<1>("h00")) + node iacq_data_done = mux(T_368, T_381, T_356) node T_384 = and(io.inner.release.ready, io.inner.release.valid) wire T_388 : UInt<2>[3] T_388[0] <= UInt<1>("h00") @@ -5896,577 +4602,523 @@ circuit Top : node T_399 = or(T_398, T_395) node T_400 = and(UInt<1>("h01"), T_399) node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk, reset, UInt<2>("h00") + reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) when T_401 : node T_405 = eq(T_403, UInt<2>("h03")) node T_407 = and(UInt<1>("h00"), T_405) - node T_410 = addw(T_403, UInt<1>("h01")) - node T_411 = mux(T_407, UInt<1>("h00"), T_410) - T_403 <= T_411 - skip - node T_412 = and(T_401, T_405) - node T_413 = mux(T_400, T_403, UInt<1>("h00")) - node irel_data_done = mux(T_400, T_412, T_384) - node T_416 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_420 : UInt<3>[1] - T_420[0] <= UInt<3>("h05") - node T_423 = eq(T_420[0], io.inner.grant.bits.g_type) - node T_425 = or(UInt<1>("h00"), T_423) - wire T_427 : UInt<1>[2] - T_427[0] <= UInt<1>("h00") - T_427[1] <= UInt<1>("h01") - node T_431 = eq(T_427[0], io.inner.grant.bits.g_type) - node T_432 = eq(T_427[1], io.inner.grant.bits.g_type) - node T_434 = or(UInt<1>("h00"), T_431) - node T_435 = or(T_434, T_432) - node T_436 = mux(io.inner.grant.bits.is_builtin_type, T_425, T_435) - node T_437 = and(UInt<1>("h01"), T_436) - node T_438 = and(T_416, T_437) - reg T_440 : UInt<2>, clk, reset, UInt<2>("h00") - when T_438 : - node T_442 = eq(T_440, UInt<2>("h03")) - node T_444 = and(UInt<1>("h00"), T_442) - node T_447 = addw(T_440, UInt<1>("h01")) - node T_448 = mux(T_444, UInt<1>("h00"), T_447) - T_440 <= T_448 - skip - node T_449 = and(T_438, T_442) - node ignt_data_cnt = mux(T_437, T_440, UInt<1>("h00")) - node ignt_data_done = mux(T_437, T_449, T_416) - node T_453 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_455 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) - wire T_458 : UInt<3>[1] - T_458[0] <= UInt<3>("h03") - node T_461 = eq(T_458[0], io.outer.acquire.bits.a_type) - node T_463 = or(UInt<1>("h00"), T_461) - node T_464 = and(T_455, T_463) - node T_465 = and(T_453, T_464) - reg T_467 : UInt<2>, clk, reset, UInt<2>("h00") - when T_465 : - node T_469 = eq(T_467, UInt<2>("h03")) - node T_471 = and(UInt<1>("h00"), T_469) - node T_474 = addw(T_467, UInt<1>("h01")) - node T_475 = mux(T_471, UInt<1>("h00"), T_474) - T_467 <= T_475 - skip - node T_476 = and(T_465, T_469) - node oacq_data_cnt = mux(T_464, T_467, UInt<1>("h00")) - node oacq_data_done = mux(T_464, T_476, T_453) - node T_479 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_484 : UInt<3>[1] - T_484[0] <= UInt<3>("h05") - node T_487 = eq(T_484[0], io.outer.grant.bits.g_type) - node T_489 = or(UInt<1>("h00"), T_487) - wire T_491 : UInt<1>[1] - T_491[0] <= UInt<1>("h00") - node T_494 = eq(T_491[0], io.outer.grant.bits.g_type) - node T_496 = or(UInt<1>("h00"), T_494) - node T_497 = mux(io.outer.grant.bits.is_builtin_type, T_489, T_496) - node T_498 = and(UInt<1>("h01"), T_497) - node T_499 = and(T_479, T_498) - reg T_501 : UInt<2>, clk, reset, UInt<2>("h00") - when T_499 : - node T_503 = eq(T_501, UInt<2>("h03")) - node T_505 = and(UInt<1>("h00"), T_503) - node T_508 = addw(T_501, UInt<1>("h01")) - node T_509 = mux(T_505, UInt<1>("h00"), T_508) - T_501 <= T_509 - skip - node T_510 = and(T_499, T_503) - node T_511 = mux(T_498, T_501, UInt<1>("h00")) - node ognt_data_done = mux(T_498, T_510, T_479) - reg pending_ognt_ack : UInt<1>, clk, reset, UInt<1>("h00") - wire T_519 : UInt<3>[3] - T_519[0] <= UInt<3>("h02") - T_519[1] <= UInt<3>("h03") - T_519[2] <= UInt<3>("h04") - node T_524 = eq(T_519[0], xact.a_type) - node T_525 = eq(T_519[1], xact.a_type) - node T_526 = eq(T_519[2], xact.a_type) - node T_528 = or(UInt<1>("h00"), T_524) - node T_529 = or(T_528, T_525) - node T_530 = or(T_529, T_526) - node pending_outer_write = and(xact.is_builtin_type, T_530) - wire T_536 : UInt<3>[3] - T_536[0] <= UInt<3>("h02") - T_536[1] <= UInt<3>("h03") - T_536[2] <= UInt<3>("h04") - node T_541 = eq(T_536[0], io.inner.acquire.bits.a_type) - node T_542 = eq(T_536[1], io.inner.acquire.bits.a_type) - node T_543 = eq(T_536[2], io.inner.acquire.bits.a_type) - node T_545 = or(UInt<1>("h00"), T_541) - node T_546 = or(T_545, T_542) - node T_547 = or(T_546, T_543) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_547) - wire T_552 : UInt<3>[2] - T_552[0] <= UInt<3>("h05") - T_552[1] <= UInt<3>("h04") - node T_556 = eq(T_552[0], io.inner.grant.bits.g_type) - node T_557 = eq(T_552[1], io.inner.grant.bits.g_type) - node T_559 = or(UInt<1>("h00"), T_556) - node T_560 = or(T_559, T_557) - wire T_562 : UInt<1>[2] - T_562[0] <= UInt<1>("h00") - T_562[1] <= UInt<1>("h01") - node T_566 = eq(T_562[0], io.inner.grant.bits.g_type) - node T_567 = eq(T_562[1], io.inner.grant.bits.g_type) - node T_569 = or(UInt<1>("h00"), T_566) - node T_570 = or(T_569, T_567) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_560, T_570) - node T_590 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) - node T_591 = mux(T_590, UInt<3>("h01"), UInt<3>("h03")) - node T_592 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) - node T_593 = mux(T_592, UInt<3>("h01"), T_591) - node T_594 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h04"), T_593) - node T_596 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h03"), T_595) - node T_598 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h03"), T_597) - node T_600 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h05"), T_599) - node T_602 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h04"), T_601) - node T_604 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) - node T_607 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_608 = mux(T_607, UInt<1>("h00"), UInt<1>("h01")) - node T_609 = mux(T_604, T_608, UInt<1>("h01")) - node T_610 = mux(io.inner.acquire.bits.is_builtin_type, T_603, T_609) - wire T_619 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_619.client_id <= UInt<1>("h00") - T_619.data <= UInt<1>("h00") - T_619.g_type <= UInt<1>("h00") - T_619.is_builtin_type <= UInt<1>("h00") - T_619.manager_xact_id <= UInt<1>("h00") - T_619.client_xact_id <= UInt<1>("h00") - T_619.addr_beat <= UInt<1>("h00") - T_619.client_id <= io.inner.acquire.bits.client_id - T_619.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_619.g_type <= T_610 - T_619.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_619.manager_xact_id <= UInt<3>("h04") - T_619.addr_beat <= UInt<1>("h00") - T_619.data <= UInt<1>("h00") - wire T_637 : UInt<3>[2] - T_637[0] <= UInt<3>("h05") - T_637[1] <= UInt<3>("h04") - node T_641 = eq(T_637[0], T_619.g_type) - node T_642 = eq(T_637[1], T_619.g_type) - node T_644 = or(UInt<1>("h00"), T_641) - node T_645 = or(T_644, T_642) - wire T_647 : UInt<1>[2] - T_647[0] <= UInt<1>("h00") - T_647[1] <= UInt<1>("h01") - node T_651 = eq(T_647[0], T_619.g_type) - node T_652 = eq(T_647[1], T_619.g_type) - node T_654 = or(UInt<1>("h00"), T_651) - node T_655 = or(T_654, T_652) - node pending_outer_read_ = mux(T_619.is_builtin_type, T_645, T_655) - wire T_661 : UInt<3>[3] - T_661[0] <= UInt<3>("h02") - T_661[1] <= UInt<3>("h00") - T_661[2] <= UInt<3>("h04") - node T_666 = eq(T_661[0], xact.a_type) - node T_667 = eq(T_661[1], xact.a_type) - node T_668 = eq(T_661[2], xact.a_type) - node T_670 = or(UInt<1>("h00"), T_666) - node T_671 = or(T_670, T_667) - node T_672 = or(T_671, T_668) - node subblock_type = and(xact.is_builtin_type, T_672) - node T_674 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_675 = neq(state, UInt<1>("h00")) - node T_676 = and(T_674, T_675) - node T_678 = eq(collect_iacq_data, UInt<1>("h00")) - node T_679 = and(T_676, T_678) - io.has_acquire_conflict <= T_679 - node T_680 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_681 = and(T_680, collect_iacq_data) - io.has_acquire_match <= T_681 - node T_682 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_684 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) - node T_685 = and(T_682, T_684) - node T_686 = eq(state, UInt<1>("h01")) - node T_687 = and(T_685, T_686) - io.has_release_match <= T_687 - node T_692 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_698 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_410 = add(T_403, UInt<1>("h01")) + node T_411 = tail(T_410, 1) + node T_412 = mux(T_407, UInt<1>("h00"), T_411) + T_403 <= T_412 + skip + node T_413 = and(T_401, T_405) + node T_414 = mux(T_400, T_403, UInt<1>("h00")) + node irel_data_done = mux(T_400, T_413, T_384) + node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) + wire T_421 : UInt<3>[1] + T_421[0] <= UInt<3>("h05") + node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) + node T_426 = or(UInt<1>("h00"), T_424) + wire T_428 : UInt<1>[2] + T_428[0] <= UInt<1>("h00") + T_428[1] <= UInt<1>("h01") + node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) + node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) + node T_435 = or(UInt<1>("h00"), T_432) + node T_436 = or(T_435, T_433) + node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) + node T_438 = and(UInt<1>("h01"), T_437) + node T_439 = and(T_417, T_438) + reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_439 : + node T_443 = eq(T_441, UInt<2>("h03")) + node T_445 = and(UInt<1>("h00"), T_443) + node T_448 = add(T_441, UInt<1>("h01")) + node T_449 = tail(T_448, 1) + node T_450 = mux(T_445, UInt<1>("h00"), T_449) + T_441 <= T_450 + skip + node T_451 = and(T_439, T_443) + node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00")) + node ignt_data_done = mux(T_438, T_451, T_417) + node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) + wire T_460 : UInt<3>[1] + T_460[0] <= UInt<3>("h03") + node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) + node T_465 = or(UInt<1>("h00"), T_463) + node T_466 = and(T_457, T_465) + node T_467 = and(T_455, T_466) + reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_467 : + node T_471 = eq(T_469, UInt<2>("h03")) + node T_473 = and(UInt<1>("h00"), T_471) + node T_476 = add(T_469, UInt<1>("h01")) + node T_477 = tail(T_476, 1) + node T_478 = mux(T_473, UInt<1>("h00"), T_477) + T_469 <= T_478 + skip + node T_479 = and(T_467, T_471) + node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00")) + node oacq_data_done = mux(T_466, T_479, T_455) + node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_487 : UInt<3>[1] + T_487[0] <= UInt<3>("h05") + node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) + node T_492 = or(UInt<1>("h00"), T_490) + wire T_494 : UInt<1>[1] + T_494[0] <= UInt<1>("h00") + node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) + node T_499 = or(UInt<1>("h00"), T_497) + node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) + node T_501 = and(UInt<1>("h01"), T_500) + node T_502 = and(T_482, T_501) + reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_502 : + node T_506 = eq(T_504, UInt<2>("h03")) + node T_508 = and(UInt<1>("h00"), T_506) + node T_511 = add(T_504, UInt<1>("h01")) + node T_512 = tail(T_511, 1) + node T_513 = mux(T_508, UInt<1>("h00"), T_512) + T_504 <= T_513 + skip + node T_514 = and(T_502, T_506) + node T_515 = mux(T_501, T_504, UInt<1>("h00")) + node ognt_data_done = mux(T_501, T_514, T_482) + reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + wire T_523 : UInt<3>[3] + T_523[0] <= UInt<3>("h02") + T_523[1] <= UInt<3>("h03") + T_523[2] <= UInt<3>("h04") + node T_528 = eq(T_523[0], xact.a_type) + node T_529 = eq(T_523[1], xact.a_type) + node T_530 = eq(T_523[2], xact.a_type) + node T_532 = or(UInt<1>("h00"), T_528) + node T_533 = or(T_532, T_529) + node T_534 = or(T_533, T_530) + node pending_outer_write = and(xact.is_builtin_type, T_534) + wire T_540 : UInt<3>[3] + T_540[0] <= UInt<3>("h02") + T_540[1] <= UInt<3>("h03") + T_540[2] <= UInt<3>("h04") + node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) + node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) + node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) + node T_549 = or(UInt<1>("h00"), T_545) + node T_550 = or(T_549, T_546) + node T_551 = or(T_550, T_547) + node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) + wire T_556 : UInt<3>[2] + T_556[0] <= UInt<3>("h05") + T_556[1] <= UInt<3>("h04") + node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) + node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) + node T_563 = or(UInt<1>("h00"), T_560) + node T_564 = or(T_563, T_561) + wire T_566 : UInt<1>[2] + T_566[0] <= UInt<1>("h00") + T_566[1] <= UInt<1>("h01") + node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) + node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) + node T_573 = or(UInt<1>("h00"), T_570) + node T_574 = or(T_573, T_571) + node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) + node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) + node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03")) + node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) + node T_597 = mux(T_596, UInt<3>("h01"), T_595) + node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) + node T_599 = mux(T_598, UInt<3>("h04"), T_597) + node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) + node T_601 = mux(T_600, UInt<3>("h03"), T_599) + node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) + node T_603 = mux(T_602, UInt<3>("h03"), T_601) + node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) + node T_605 = mux(T_604, UInt<3>("h05"), T_603) + node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) + node T_607 = mux(T_606, UInt<3>("h04"), T_605) + node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) + node T_611 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01")) + node T_613 = mux(T_608, T_612, UInt<1>("h01")) + node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) + wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} + T_623 is invalid + T_623.client_id <= io.inner.acquire.bits.client_id + T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type + T_623.g_type <= T_614 + T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id + T_623.manager_xact_id <= UInt<3>("h04") + T_623.addr_beat <= UInt<1>("h00") + T_623.data <= UInt<1>("h00") + wire T_634 : UInt<3>[2] + T_634[0] <= UInt<3>("h05") + T_634[1] <= UInt<3>("h04") + node T_638 = eq(T_634[0], T_623.g_type) + node T_639 = eq(T_634[1], T_623.g_type) + node T_641 = or(UInt<1>("h00"), T_638) + node T_642 = or(T_641, T_639) + wire T_644 : UInt<1>[2] + T_644[0] <= UInt<1>("h00") + T_644[1] <= UInt<1>("h01") + node T_648 = eq(T_644[0], T_623.g_type) + node T_649 = eq(T_644[1], T_623.g_type) + node T_651 = or(UInt<1>("h00"), T_648) + node T_652 = or(T_651, T_649) + node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) + wire T_658 : UInt<3>[3] + T_658[0] <= UInt<3>("h02") + T_658[1] <= UInt<3>("h00") + T_658[2] <= UInt<3>("h04") + node T_663 = eq(T_658[0], xact.a_type) + node T_664 = eq(T_658[1], xact.a_type) + node T_665 = eq(T_658[2], xact.a_type) + node T_667 = or(UInt<1>("h00"), T_663) + node T_668 = or(T_667, T_664) + node T_669 = or(T_668, T_665) + node subblock_type = and(xact.is_builtin_type, T_669) + node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) + node T_672 = neq(state, UInt<1>("h00")) + node T_673 = and(T_671, T_672) + node T_675 = eq(collect_iacq_data, UInt<1>("h00")) + node T_676 = and(T_673, T_675) + io.has_acquire_conflict <= T_676 + node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) + node T_678 = and(T_677, collect_iacq_data) + io.has_acquire_match <= T_678 + node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) + node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) + node T_682 = and(T_679, T_681) + node T_683 = eq(state, UInt<1>("h01")) + node T_684 = and(T_682, T_683) + io.has_release_match <= T_684 + node T_689 = asUInt(asSInt(UInt<16>("h0ffff"))) + node T_695 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_696 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_697 = cat(T_695, T_696) node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_700 = cat(T_698, T_699) - node T_702 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_703 = cat(UInt<3>("h07"), T_702) - node T_705 = cat(T_692, UInt<1>("h01")) - node T_707 = cat(T_692, UInt<1>("h01")) - node T_709 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_710 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_711 = cat(T_709, T_710) - node T_713 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_715 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_716 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_717 = mux(T_716, T_715, UInt<1>("h00")) - node T_718 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_719 = mux(T_718, T_713, T_717) - node T_720 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_721 = mux(T_720, T_711, T_719) - node T_722 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_723 = mux(T_722, T_707, T_721) - node T_724 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_725 = mux(T_724, T_705, T_723) - node T_726 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_727 = mux(T_726, T_703, T_725) - node T_728 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_729 = mux(T_728, T_700, T_727) + node T_700 = cat(UInt<3>("h07"), T_699) + node T_702 = cat(T_689, UInt<1>("h01")) + node T_704 = cat(T_689, UInt<1>("h01")) + node T_706 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_707 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_708 = cat(T_706, T_707) + node T_710 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_712 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_713 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_714 = mux(T_713, T_712, UInt<1>("h00")) + node T_715 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_716 = mux(T_715, T_710, T_714) + node T_717 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_718 = mux(T_717, T_708, T_716) + node T_719 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_720 = mux(T_719, T_704, T_718) + node T_721 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_722 = mux(T_721, T_702, T_720) + node T_723 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_724 = mux(T_723, T_700, T_722) + node T_725 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_726 = mux(T_725, T_697, T_724) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe.data <= UInt<1>("h00") - oacq_probe.union <= UInt<1>("h00") - oacq_probe.a_type <= UInt<1>("h00") - oacq_probe.is_builtin_type <= UInt<1>("h00") - oacq_probe.addr_beat <= UInt<1>("h00") - oacq_probe.client_xact_id <= UInt<1>("h00") - oacq_probe.addr_block <= UInt<1>("h00") + oacq_probe is invalid oacq_probe.is_builtin_type <= UInt<1>("h01") oacq_probe.a_type <= UInt<3>("h03") oacq_probe.client_xact_id <= UInt<3>("h04") oacq_probe.addr_block <= io.inner.release.bits.addr_block oacq_probe.addr_beat <= io.inner.release.bits.addr_beat oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_729 - node T_754 = bits(xact.union, 12, 9) - node T_755 = bits(T_754, 3, 3) - node T_757 = dshl(UInt<1>("h01"), T_755) - node T_759 = eq(xact.a_type, UInt<3>("h04")) - node T_760 = and(xact.is_builtin_type, T_759) - node T_761 = bit(T_757, 0) - node T_762 = bit(T_757, 1) - wire T_764 : UInt<1>[2] - T_764[0] <= T_761 - T_764[1] <= T_762 - node T_769 = subw(UInt<8>("h00"), T_764[0]) - node T_771 = subw(UInt<8>("h00"), T_764[1]) - wire T_773 : UInt<8>[2] - T_773[0] <= T_769 - T_773[1] <= T_771 - node T_777 = cat(T_773[1], T_773[0]) - node T_779 = eq(xact.a_type, UInt<3>("h03")) - node T_780 = and(xact.is_builtin_type, T_779) - node T_782 = eq(xact.a_type, UInt<3>("h02")) - node T_783 = and(xact.is_builtin_type, T_782) - node T_784 = or(T_780, T_783) - node T_785 = bits(xact.union, 16, 1) - node T_787 = mux(T_784, T_785, UInt<16>("h00")) - node T_788 = mux(T_760, T_777, T_787) - node T_796 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_797 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_798 = cat(T_796, T_797) + oacq_probe.union <= T_726 + node T_744 = bits(xact.union, 12, 9) + node T_745 = bits(T_744, 3, 3) + node T_747 = dshl(UInt<1>("h01"), T_745) + node T_749 = eq(xact.a_type, UInt<3>("h04")) + node T_750 = and(xact.is_builtin_type, T_749) + node T_751 = bits(T_747, 0, 0) + node T_752 = bits(T_747, 1, 1) + wire T_754 : UInt<1>[2] + T_754[0] <= T_751 + T_754[1] <= T_752 + node T_759 = sub(UInt<8>("h00"), T_754[0]) + node T_760 = tail(T_759, 1) + node T_762 = sub(UInt<8>("h00"), T_754[1]) + node T_763 = tail(T_762, 1) + wire T_765 : UInt<8>[2] + T_765[0] <= T_760 + T_765[1] <= T_763 + node T_769 = cat(T_765[1], T_765[0]) + node T_771 = eq(xact.a_type, UInt<3>("h03")) + node T_772 = and(xact.is_builtin_type, T_771) + node T_774 = eq(xact.a_type, UInt<3>("h02")) + node T_775 = and(xact.is_builtin_type, T_774) + node T_776 = or(T_772, T_775) + node T_777 = bits(xact.union, 16, 1) + node T_779 = mux(T_776, T_777, UInt<16>("h00")) + node T_780 = mux(T_750, T_769, T_779) + node T_788 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_789 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_790 = cat(T_788, T_789) + node T_792 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_793 = cat(UInt<3>("h07"), T_792) + node T_795 = cat(T_780, UInt<1>("h01")) + node T_797 = cat(T_780, UInt<1>("h01")) + node T_799 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_801 = cat(UInt<3>("h07"), T_800) - node T_803 = cat(T_788, UInt<1>("h01")) - node T_805 = cat(T_788, UInt<1>("h01")) - node T_807 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_808 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_809 = cat(T_807, T_808) - node T_811 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_813 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_814 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_815 = mux(T_814, T_813, UInt<1>("h00")) - node T_816 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_817 = mux(T_816, T_811, T_815) - node T_818 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_819 = mux(T_818, T_809, T_817) - node T_820 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_821 = mux(T_820, T_805, T_819) - node T_822 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_823 = mux(T_822, T_803, T_821) - node T_824 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_825 = mux(T_824, T_801, T_823) - node T_826 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_827 = mux(T_826, T_798, T_825) + node T_801 = cat(T_799, T_800) + node T_803 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_805 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_806 = eq(UInt<3>("h06"), UInt<3>("h02")) + node T_807 = mux(T_806, T_805, UInt<1>("h00")) + node T_808 = eq(UInt<3>("h05"), UInt<3>("h02")) + node T_809 = mux(T_808, T_803, T_807) + node T_810 = eq(UInt<3>("h04"), UInt<3>("h02")) + node T_811 = mux(T_810, T_801, T_809) + node T_812 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_813 = mux(T_812, T_797, T_811) + node T_814 = eq(UInt<3>("h02"), UInt<3>("h02")) + node T_815 = mux(T_814, T_795, T_813) + node T_816 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_817 = mux(T_816, T_793, T_815) + node T_818 = eq(UInt<3>("h00"), UInt<3>("h02")) + node T_819 = mux(T_818, T_790, T_817) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat.data <= UInt<1>("h00") - oacq_write_beat.union <= UInt<1>("h00") - oacq_write_beat.a_type <= UInt<1>("h00") - oacq_write_beat.is_builtin_type <= UInt<1>("h00") - oacq_write_beat.addr_beat <= UInt<1>("h00") - oacq_write_beat.client_xact_id <= UInt<1>("h00") - oacq_write_beat.addr_block <= UInt<1>("h00") + oacq_write_beat is invalid oacq_write_beat.is_builtin_type <= UInt<1>("h01") oacq_write_beat.a_type <= UInt<3>("h02") oacq_write_beat.client_xact_id <= UInt<3>("h04") oacq_write_beat.addr_block <= xact.addr_block oacq_write_beat.addr_beat <= xact.addr_beat oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_827 - node T_861 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_862 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_863 = cat(T_861, T_862) - node T_865 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_866 = cat(UInt<3>("h07"), T_865) - node T_868 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_870 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_872 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_873 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_874 = cat(T_872, T_873) - node T_876 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_878 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_879 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_880 = mux(T_879, T_878, UInt<1>("h00")) - node T_881 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_882 = mux(T_881, T_876, T_880) - node T_883 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_884 = mux(T_883, T_874, T_882) - node T_885 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_886 = mux(T_885, T_870, T_884) - node T_887 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_888 = mux(T_887, T_868, T_886) - node T_889 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_890 = mux(T_889, T_866, T_888) - node T_891 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_892 = mux(T_891, T_863, T_890) + oacq_write_beat.union <= T_819 + node T_846 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_847 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_848 = cat(T_846, T_847) + node T_850 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_851 = cat(UInt<3>("h07"), T_850) + node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) + node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) + node T_857 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_858 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_859 = cat(T_857, T_858) + node T_861 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_863 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_864 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_865 = mux(T_864, T_863, UInt<1>("h00")) + node T_866 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_867 = mux(T_866, T_861, T_865) + node T_868 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_869 = mux(T_868, T_859, T_867) + node T_870 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_871 = mux(T_870, T_855, T_869) + node T_872 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_873 = mux(T_872, T_853, T_871) + node T_874 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_875 = mux(T_874, T_851, T_873) + node T_876 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_877 = mux(T_876, T_848, T_875) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block.data <= UInt<1>("h00") - oacq_write_block.union <= UInt<1>("h00") - oacq_write_block.a_type <= UInt<1>("h00") - oacq_write_block.is_builtin_type <= UInt<1>("h00") - oacq_write_block.addr_beat <= UInt<1>("h00") - oacq_write_block.client_xact_id <= UInt<1>("h00") - oacq_write_block.addr_block <= UInt<1>("h00") + oacq_write_block is invalid oacq_write_block.is_builtin_type <= UInt<1>("h01") oacq_write_block.a_type <= UInt<3>("h03") oacq_write_block.client_xact_id <= UInt<3>("h04") oacq_write_block.addr_block <= xact.addr_block oacq_write_block.addr_beat <= oacq_data_cnt oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_892 - node T_917 = bits(xact.union, 12, 9) - node T_918 = bits(xact.union, 8, 6) - node T_926 = cat(T_917, T_918) - node T_927 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_928 = cat(T_926, T_927) - node T_930 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_931 = cat(T_918, T_930) - node T_933 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_935 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_937 = cat(T_917, T_918) - node T_938 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_939 = cat(T_937, T_938) - node T_941 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_943 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_944 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_945 = mux(T_944, T_943, UInt<1>("h00")) - node T_946 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_947 = mux(T_946, T_941, T_945) - node T_948 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_949 = mux(T_948, T_939, T_947) - node T_950 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_951 = mux(T_950, T_935, T_949) - node T_952 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_953 = mux(T_952, T_933, T_951) - node T_954 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_955 = mux(T_954, T_931, T_953) - node T_956 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_957 = mux(T_956, T_928, T_955) + oacq_write_block.union <= T_877 + node T_895 = bits(xact.union, 12, 9) + node T_896 = bits(xact.union, 8, 6) + node T_904 = cat(T_895, T_896) + node T_905 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_906 = cat(T_904, T_905) + node T_908 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_909 = cat(T_896, T_908) + node T_911 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_913 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_915 = cat(T_895, T_896) + node T_916 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_917 = cat(T_915, T_916) + node T_919 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_921 = cat(UInt<5>("h01"), UInt<1>("h00")) + node T_922 = eq(UInt<3>("h06"), UInt<3>("h00")) + node T_923 = mux(T_922, T_921, UInt<1>("h00")) + node T_924 = eq(UInt<3>("h05"), UInt<3>("h00")) + node T_925 = mux(T_924, T_919, T_923) + node T_926 = eq(UInt<3>("h04"), UInt<3>("h00")) + node T_927 = mux(T_926, T_917, T_925) + node T_928 = eq(UInt<3>("h03"), UInt<3>("h00")) + node T_929 = mux(T_928, T_913, T_927) + node T_930 = eq(UInt<3>("h02"), UInt<3>("h00")) + node T_931 = mux(T_930, T_911, T_929) + node T_932 = eq(UInt<3>("h01"), UInt<3>("h00")) + node T_933 = mux(T_932, T_909, T_931) + node T_934 = eq(UInt<3>("h00"), UInt<3>("h00")) + node T_935 = mux(T_934, T_906, T_933) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= UInt<1>("h00") - oacq_read_beat.a_type <= UInt<1>("h00") - oacq_read_beat.is_builtin_type <= UInt<1>("h00") - oacq_read_beat.addr_beat <= UInt<1>("h00") - oacq_read_beat.client_xact_id <= UInt<1>("h00") - oacq_read_beat.addr_block <= UInt<1>("h00") + oacq_read_beat is invalid oacq_read_beat.is_builtin_type <= UInt<1>("h01") oacq_read_beat.a_type <= UInt<3>("h00") oacq_read_beat.client_xact_id <= UInt<3>("h04") oacq_read_beat.addr_block <= xact.addr_block oacq_read_beat.addr_beat <= xact.addr_beat oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= T_957 - node T_991 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_992 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_993 = cat(T_991, T_992) - node T_995 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_996 = cat(UInt<3>("h07"), T_995) - node T_998 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1000 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1002 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1003 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1004 = cat(T_1002, T_1003) - node T_1006 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1008 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1009 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_1010 = mux(T_1009, T_1008, UInt<1>("h00")) - node T_1011 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_1012 = mux(T_1011, T_1006, T_1010) - node T_1013 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_1014 = mux(T_1013, T_1004, T_1012) - node T_1015 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_1016 = mux(T_1015, T_1000, T_1014) - node T_1017 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_1018 = mux(T_1017, T_998, T_1016) - node T_1019 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_1020 = mux(T_1019, T_996, T_1018) - node T_1021 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_1022 = mux(T_1021, T_993, T_1020) + oacq_read_beat.union <= T_935 + node T_962 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_963 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_964 = cat(T_962, T_963) + node T_966 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_967 = cat(UInt<3>("h07"), T_966) + node T_969 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_971 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_973 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_974 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_975 = cat(T_973, T_974) + node T_977 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_979 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_980 = eq(UInt<3>("h06"), UInt<3>("h01")) + node T_981 = mux(T_980, T_979, UInt<1>("h00")) + node T_982 = eq(UInt<3>("h05"), UInt<3>("h01")) + node T_983 = mux(T_982, T_977, T_981) + node T_984 = eq(UInt<3>("h04"), UInt<3>("h01")) + node T_985 = mux(T_984, T_975, T_983) + node T_986 = eq(UInt<3>("h03"), UInt<3>("h01")) + node T_987 = mux(T_986, T_971, T_985) + node T_988 = eq(UInt<3>("h02"), UInt<3>("h01")) + node T_989 = mux(T_988, T_969, T_987) + node T_990 = eq(UInt<3>("h01"), UInt<3>("h01")) + node T_991 = mux(T_990, T_967, T_989) + node T_992 = eq(UInt<3>("h00"), UInt<3>("h01")) + node T_993 = mux(T_992, T_964, T_991) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= UInt<1>("h00") - oacq_read_block.a_type <= UInt<1>("h00") - oacq_read_block.is_builtin_type <= UInt<1>("h00") - oacq_read_block.addr_beat <= UInt<1>("h00") - oacq_read_block.client_xact_id <= UInt<1>("h00") - oacq_read_block.addr_block <= UInt<1>("h00") + oacq_read_block is invalid oacq_read_block.is_builtin_type <= UInt<1>("h01") oacq_read_block.a_type <= UInt<3>("h01") oacq_read_block.client_xact_id <= UInt<3>("h04") oacq_read_block.addr_block <= xact.addr_block oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= T_1022 + oacq_read_block.union <= T_993 io.outer.acquire.valid <= UInt<1>("h00") - node T_1047 = eq(state, UInt<1>("h01")) - node T_1048 = eq(state, UInt<2>("h03")) - wire T_1057 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1057 <- oacq_write_block - when subblock_type : - T_1057 <- oacq_write_beat - skip - wire T_1073 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1073 <- oacq_read_block - when subblock_type : - T_1073 <- oacq_read_beat - skip - wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1089 <- T_1073 - when T_1048 : - T_1089 <- T_1057 - skip - wire T_1105 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1105 <- T_1089 - when T_1047 : - T_1105 <- oacq_probe - skip - io.outer.acquire.bits <- T_1105 + node T_1011 = eq(state, UInt<1>("h01")) + node T_1012 = eq(state, UInt<2>("h03")) + node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) + node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) + node T_1029 = mux(T_1012, T_1013, T_1021) + node T_1037 = mux(T_1011, oacq_probe, T_1029) + io.outer.acquire.bits <- T_1037 io.outer.grant.ready <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") - node T_1122 = eq(UInt<3>("h04"), xact.a_type) - node T_1123 = mux(T_1122, UInt<1>("h00"), UInt<2>("h02")) - node T_1124 = eq(UInt<3>("h06"), xact.a_type) - node T_1125 = mux(T_1124, UInt<1>("h00"), T_1123) - node T_1126 = eq(UInt<3>("h05"), xact.a_type) - node T_1127 = mux(T_1126, UInt<2>("h02"), T_1125) - node T_1128 = eq(UInt<3>("h02"), xact.a_type) - node T_1129 = mux(T_1128, UInt<1>("h00"), T_1127) - node T_1130 = eq(UInt<3>("h00"), xact.a_type) - node T_1131 = mux(T_1130, UInt<2>("h02"), T_1129) - node T_1132 = eq(UInt<3>("h03"), xact.a_type) - node T_1133 = mux(T_1132, UInt<1>("h00"), T_1131) - node T_1134 = eq(UInt<3>("h01"), xact.a_type) - node T_1135 = mux(T_1134, UInt<2>("h02"), T_1133) - node T_1136 = eq(UInt<1>("h01"), xact.a_type) - node T_1137 = mux(T_1136, UInt<1>("h00"), UInt<2>("h02")) - node T_1138 = eq(UInt<1>("h00"), xact.a_type) - node T_1139 = mux(T_1138, UInt<1>("h01"), T_1137) - node T_1140 = mux(xact.is_builtin_type, T_1135, T_1139) - wire T_1145 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1145.client_id <= UInt<1>("h00") - T_1145.p_type <= UInt<1>("h00") - T_1145.addr_block <= UInt<1>("h00") - T_1145.client_id <= UInt<1>("h00") - T_1145.p_type <= T_1140 - T_1145.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1145 + node T_1054 = eq(UInt<3>("h04"), xact.a_type) + node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02")) + node T_1056 = eq(UInt<3>("h06"), xact.a_type) + node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055) + node T_1058 = eq(UInt<3>("h05"), xact.a_type) + node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057) + node T_1060 = eq(UInt<3>("h02"), xact.a_type) + node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059) + node T_1062 = eq(UInt<3>("h00"), xact.a_type) + node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061) + node T_1064 = eq(UInt<3>("h03"), xact.a_type) + node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063) + node T_1066 = eq(UInt<3>("h01"), xact.a_type) + node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065) + node T_1068 = eq(UInt<1>("h01"), xact.a_type) + node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02")) + node T_1070 = eq(UInt<1>("h00"), xact.a_type) + node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069) + node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) + wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} + T_1077 is invalid + T_1077.client_id <= UInt<1>("h00") + T_1077.p_type <= T_1072 + T_1077.addr_block <= xact.addr_block + io.inner.probe.bits <- T_1077 io.inner.grant.valid <= UInt<1>("h00") - node T_1171 = eq(UInt<3>("h06"), xact.a_type) - node T_1172 = mux(T_1171, UInt<3>("h01"), UInt<3>("h03")) - node T_1173 = eq(UInt<3>("h05"), xact.a_type) - node T_1174 = mux(T_1173, UInt<3>("h01"), T_1172) - node T_1175 = eq(UInt<3>("h04"), xact.a_type) - node T_1176 = mux(T_1175, UInt<3>("h04"), T_1174) - node T_1177 = eq(UInt<3>("h03"), xact.a_type) - node T_1178 = mux(T_1177, UInt<3>("h03"), T_1176) - node T_1179 = eq(UInt<3>("h02"), xact.a_type) - node T_1180 = mux(T_1179, UInt<3>("h03"), T_1178) - node T_1181 = eq(UInt<3>("h01"), xact.a_type) - node T_1182 = mux(T_1181, UInt<3>("h05"), T_1180) - node T_1183 = eq(UInt<3>("h00"), xact.a_type) - node T_1184 = mux(T_1183, UInt<3>("h04"), T_1182) - node T_1185 = eq(xact.a_type, UInt<1>("h00")) - node T_1188 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1189 = mux(T_1188, UInt<1>("h00"), UInt<1>("h01")) - node T_1190 = mux(T_1185, T_1189, UInt<1>("h01")) - node T_1191 = mux(xact.is_builtin_type, T_1184, T_1190) - wire T_1200 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1200.client_id <= UInt<1>("h00") - T_1200.data <= UInt<1>("h00") - T_1200.g_type <= UInt<1>("h00") - T_1200.is_builtin_type <= UInt<1>("h00") - T_1200.manager_xact_id <= UInt<1>("h00") - T_1200.client_xact_id <= UInt<1>("h00") - T_1200.addr_beat <= UInt<1>("h00") - T_1200.client_id <= xact.client_id - T_1200.is_builtin_type <= xact.is_builtin_type - T_1200.g_type <= T_1191 - T_1200.client_xact_id <= xact.client_xact_id - T_1200.manager_xact_id <= UInt<3>("h04") - T_1200.addr_beat <= UInt<1>("h00") - T_1200.data <= UInt<1>("h00") - io.inner.grant.bits <- T_1200 + node T_1100 = eq(UInt<3>("h06"), xact.a_type) + node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03")) + node T_1102 = eq(UInt<3>("h05"), xact.a_type) + node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101) + node T_1104 = eq(UInt<3>("h04"), xact.a_type) + node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103) + node T_1106 = eq(UInt<3>("h03"), xact.a_type) + node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105) + node T_1108 = eq(UInt<3>("h02"), xact.a_type) + node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107) + node T_1110 = eq(UInt<3>("h01"), xact.a_type) + node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109) + node T_1112 = eq(UInt<3>("h00"), xact.a_type) + node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111) + node T_1114 = eq(xact.a_type, UInt<1>("h00")) + node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01")) + node T_1119 = mux(T_1114, T_1118, UInt<1>("h01")) + node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) + wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} + T_1129 is invalid + T_1129.client_id <= xact.client_id + T_1129.is_builtin_type <= xact.is_builtin_type + T_1129.g_type <= T_1120 + T_1129.client_xact_id <= xact.client_xact_id + T_1129.manager_xact_id <= UInt<3>("h04") + T_1129.addr_beat <= UInt<1>("h00") + T_1129.data <= UInt<1>("h00") + io.inner.grant.bits <- T_1129 io.inner.acquire.ready <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") - node T_1218 = neq(state, UInt<1>("h00")) - node T_1219 = and(T_1218, collect_iacq_data) - node T_1220 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1221 = and(T_1219, T_1220) - node T_1222 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1223 = and(T_1221, T_1222) - node T_1225 = eq(T_1223, UInt<1>("h00")) - node T_1227 = eq(reset, UInt<1>("h00")) - when T_1227 : - node T_1229 = eq(T_1225, UInt<1>("h00")) - when T_1229 : - node T_1231 = eq(reset, UInt<1>("h00")) - when T_1231 : + node T_1140 = neq(state, UInt<1>("h00")) + node T_1141 = and(T_1140, collect_iacq_data) + node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1143 = and(T_1141, T_1142) + node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) + node T_1145 = and(T_1143, T_1144) + node T_1147 = eq(T_1145, UInt<1>("h00")) + node T_1149 = eq(reset, UInt<1>("h00")) + when T_1149 : + node T_1151 = eq(T_1147, UInt<1>("h00")) + when T_1151 : + node T_1153 = eq(reset, UInt<1>("h00")) + when T_1153 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1232 = neq(state, UInt<1>("h00")) - node T_1233 = and(T_1232, collect_iacq_data) - node T_1234 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1235 = and(T_1233, T_1234) - node T_1236 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1237 = and(T_1235, T_1236) - node T_1239 = eq(T_1237, UInt<1>("h00")) - node T_1241 = eq(reset, UInt<1>("h00")) - when T_1241 : - node T_1243 = eq(T_1239, UInt<1>("h00")) - when T_1243 : - node T_1245 = eq(reset, UInt<1>("h00")) - when T_1245 : + node T_1154 = neq(state, UInt<1>("h00")) + node T_1155 = and(T_1154, collect_iacq_data) + node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1157 = and(T_1155, T_1156) + node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) + node T_1159 = and(T_1157, T_1158) + node T_1161 = eq(T_1159, UInt<1>("h00")) + node T_1163 = eq(reset, UInt<1>("h00")) + when T_1163 : + node T_1165 = eq(T_1161, UInt<1>("h00")) + when T_1165 : + node T_1167 = eq(reset, UInt<1>("h00")) + when T_1167 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1246 = eq(state, UInt<1>("h00")) - node T_1247 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1248 = and(T_1246, T_1247) - node T_1250 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1253 : UInt<3>[1] - T_1253[0] <= UInt<3>("h03") - node T_1256 = eq(T_1253[0], io.inner.acquire.bits.a_type) - node T_1258 = or(UInt<1>("h00"), T_1256) - node T_1259 = and(T_1250, T_1258) - node T_1260 = and(T_1248, T_1259) - node T_1262 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1263 = and(T_1260, T_1262) - node T_1265 = eq(T_1263, UInt<1>("h00")) - node T_1267 = eq(reset, UInt<1>("h00")) - when T_1267 : - node T_1269 = eq(T_1265, UInt<1>("h00")) - when T_1269 : - node T_1271 = eq(reset, UInt<1>("h00")) - when T_1271 : + node T_1168 = eq(state, UInt<1>("h00")) + node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1170 = and(T_1168, T_1169) + node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_1175 : UInt<3>[1] + T_1175[0] <= UInt<3>("h03") + node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) + node T_1180 = or(UInt<1>("h00"), T_1178) + node T_1181 = and(T_1172, T_1180) + node T_1182 = and(T_1170, T_1181) + node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) + node T_1185 = and(T_1182, T_1184) + node T_1187 = eq(T_1185, UInt<1>("h00")) + node T_1189 = eq(reset, UInt<1>("h00")) + when T_1189 : + node T_1191 = eq(T_1187, UInt<1>("h00")) + when T_1191 : + node T_1193 = eq(reset, UInt<1>("h00")) + when T_1193 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") skip stop(clk, UInt<1>(1), 1) @@ -6476,38 +5128,40 @@ circuit Top : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1275 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1276 = bits(T_1275, 3, 3) - node T_1278 = dshl(UInt<1>("h01"), T_1276) - node T_1280 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1281 = and(io.inner.acquire.bits.is_builtin_type, T_1280) - node T_1282 = bit(T_1278, 0) - node T_1283 = bit(T_1278, 1) - wire T_1285 : UInt<1>[2] - T_1285[0] <= T_1282 - T_1285[1] <= T_1283 - node T_1290 = subw(UInt<8>("h00"), T_1285[0]) - node T_1292 = subw(UInt<8>("h00"), T_1285[1]) - wire T_1294 : UInt<8>[2] - T_1294[0] <= T_1290 - T_1294[1] <= T_1292 - node T_1298 = cat(T_1294[1], T_1294[0]) - node T_1300 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1301 = and(io.inner.acquire.bits.is_builtin_type, T_1300) - node T_1303 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1304 = and(io.inner.acquire.bits.is_builtin_type, T_1303) - node T_1305 = or(T_1301, T_1304) - node T_1306 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1308 = mux(T_1305, T_1306, UInt<16>("h00")) - node T_1309 = mux(T_1281, T_1298, T_1308) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1309 - node T_1312 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) - node T_1313 = or(iacq_data_valid, T_1312) - node T_1314 = not(iacq_data_valid) - node T_1315 = or(T_1314, T_1312) - node T_1316 = not(T_1315) - node T_1317 = mux(UInt<1>("h01"), T_1313, T_1316) - iacq_data_valid <= T_1317 + node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) + node T_1198 = bits(T_1197, 3, 3) + node T_1200 = dshl(UInt<1>("h01"), T_1198) + node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) + node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) + node T_1204 = bits(T_1200, 0, 0) + node T_1205 = bits(T_1200, 1, 1) + wire T_1207 : UInt<1>[2] + T_1207[0] <= T_1204 + T_1207[1] <= T_1205 + node T_1212 = sub(UInt<8>("h00"), T_1207[0]) + node T_1213 = tail(T_1212, 1) + node T_1215 = sub(UInt<8>("h00"), T_1207[1]) + node T_1216 = tail(T_1215, 1) + wire T_1218 : UInt<8>[2] + T_1218[0] <= T_1213 + T_1218[1] <= T_1216 + node T_1222 = cat(T_1218[1], T_1218[0]) + node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) + node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) + node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) + node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) + node T_1229 = or(T_1225, T_1228) + node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) + node T_1232 = mux(T_1229, T_1230, UInt<16>("h00")) + node T_1233 = mux(T_1203, T_1222, T_1232) + xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 + node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) + node T_1237 = or(iacq_data_valid, T_1236) + node T_1238 = not(iacq_data_valid) + node T_1239 = or(T_1238, T_1236) + node T_1240 = not(T_1239) + node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240) + iacq_data_valid <= T_1241 skip when iacq_data_done : collect_iacq_data <= UInt<1>("h00") @@ -6519,194 +5173,201 @@ circuit Top : pending_ognt_ack <= UInt<1>("h00") skip skip - node T_1321 = eq(UInt<1>("h00"), state) - when T_1321 : + node T_1245 = eq(UInt<1>("h00"), state) + when T_1245 : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact <- io.inner.acquire.bits xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data - node T_1327 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1328 = bits(T_1327, 3, 3) - node T_1330 = dshl(UInt<1>("h01"), T_1328) - node T_1332 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1333 = and(io.inner.acquire.bits.is_builtin_type, T_1332) - node T_1334 = bit(T_1330, 0) - node T_1335 = bit(T_1330, 1) - wire T_1337 : UInt<1>[2] - T_1337[0] <= T_1334 - T_1337[1] <= T_1335 - node T_1342 = subw(UInt<8>("h00"), T_1337[0]) - node T_1344 = subw(UInt<8>("h00"), T_1337[1]) - wire T_1346 : UInt<8>[2] - T_1346[0] <= T_1342 - T_1346[1] <= T_1344 - node T_1350 = cat(T_1346[1], T_1346[0]) - node T_1352 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1353 = and(io.inner.acquire.bits.is_builtin_type, T_1352) - node T_1355 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1356 = and(io.inner.acquire.bits.is_builtin_type, T_1355) - node T_1357 = or(T_1353, T_1356) - node T_1358 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1360 = mux(T_1357, T_1358, UInt<16>("h00")) - node T_1361 = mux(T_1333, T_1350, T_1360) - xact.wmask_buffer[UInt<1>("h00")] <= T_1361 - node T_1363 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1366 : UInt<3>[1] - T_1366[0] <= UInt<3>("h03") - node T_1369 = eq(T_1366[0], io.inner.acquire.bits.a_type) - node T_1371 = or(UInt<1>("h00"), T_1369) - node T_1372 = and(T_1363, T_1371) - collect_iacq_data <= T_1372 - wire T_1377 : UInt<3>[3] - T_1377[0] <= UInt<3>("h02") - T_1377[1] <= UInt<3>("h03") - T_1377[2] <= UInt<3>("h04") - node T_1382 = eq(T_1377[0], io.inner.acquire.bits.a_type) - node T_1383 = eq(T_1377[1], io.inner.acquire.bits.a_type) - node T_1384 = eq(T_1377[2], io.inner.acquire.bits.a_type) - node T_1386 = or(UInt<1>("h00"), T_1382) - node T_1387 = or(T_1386, T_1383) - node T_1388 = or(T_1387, T_1384) - node T_1389 = and(io.inner.acquire.bits.is_builtin_type, T_1388) - node T_1390 = dshl(T_1389, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1390 - node T_1392 = neq(mask_incoherent, UInt<1>("h00")) - when T_1392 : + node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) + node T_1252 = bits(T_1251, 3, 3) + node T_1254 = dshl(UInt<1>("h01"), T_1252) + node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) + node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) + node T_1258 = bits(T_1254, 0, 0) + node T_1259 = bits(T_1254, 1, 1) + wire T_1261 : UInt<1>[2] + T_1261[0] <= T_1258 + T_1261[1] <= T_1259 + node T_1266 = sub(UInt<8>("h00"), T_1261[0]) + node T_1267 = tail(T_1266, 1) + node T_1269 = sub(UInt<8>("h00"), T_1261[1]) + node T_1270 = tail(T_1269, 1) + wire T_1272 : UInt<8>[2] + T_1272[0] <= T_1267 + T_1272[1] <= T_1270 + node T_1276 = cat(T_1272[1], T_1272[0]) + node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) + node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) + node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) + node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) + node T_1283 = or(T_1279, T_1282) + node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) + node T_1286 = mux(T_1283, T_1284, UInt<16>("h00")) + node T_1287 = mux(T_1257, T_1276, T_1286) + xact.wmask_buffer[UInt<1>("h00")] <= T_1287 + node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_1292 : UInt<3>[1] + T_1292[0] <= UInt<3>("h03") + node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) + node T_1297 = or(UInt<1>("h00"), T_1295) + node T_1298 = and(T_1289, T_1297) + collect_iacq_data <= T_1298 + wire T_1303 : UInt<3>[3] + T_1303[0] <= UInt<3>("h02") + T_1303[1] <= UInt<3>("h03") + T_1303[2] <= UInt<3>("h04") + node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) + node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) + node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) + node T_1312 = or(UInt<1>("h00"), T_1308) + node T_1313 = or(T_1312, T_1309) + node T_1314 = or(T_1313, T_1310) + node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) + node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) + iacq_data_valid <= T_1316 + node T_1318 = neq(mask_incoherent, UInt<1>("h00")) + when T_1318 : pending_probes <= mask_incoherent - node T_1393 = bit(mask_incoherent, 0) - node T_1394 = bit(mask_incoherent, 1) - node T_1395 = bit(mask_incoherent, 2) - node T_1396 = bit(mask_incoherent, 3) - node T_1398 = cat(UInt<1>("h00"), T_1394) - node T_1399 = addw(T_1393, T_1398) - node T_1402 = cat(UInt<1>("h00"), T_1396) - node T_1403 = addw(T_1395, T_1402) - node T_1404 = cat(UInt<1>("h00"), T_1403) - node T_1405 = addw(T_1399, T_1404) - release_count <= T_1405 + node T_1319 = bits(mask_incoherent, 0, 0) + node T_1320 = bits(mask_incoherent, 1, 1) + node T_1321 = bits(mask_incoherent, 2, 2) + node T_1322 = bits(mask_incoherent, 3, 3) + node T_1324 = cat(UInt<1>("h00"), T_1320) + node T_1325 = add(T_1319, T_1324) + node T_1326 = tail(T_1325, 1) + node T_1329 = cat(UInt<1>("h00"), T_1322) + node T_1330 = add(T_1321, T_1329) + node T_1331 = tail(T_1330, 1) + node T_1332 = cat(UInt<1>("h00"), T_1331) + node T_1333 = add(T_1326, T_1332) + node T_1334 = tail(T_1333, 1) + release_count <= T_1334 skip - node T_1406 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_1407 = mux(pending_outer_write_, UInt<2>("h03"), T_1406) - node T_1408 = mux(T_1392, UInt<1>("h01"), T_1407) - state <= T_1408 + node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) + node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335) + node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336) + state <= T_1337 skip skip - node T_1409 = eq(UInt<1>("h01"), state) - when T_1409 : - node T_1411 = neq(pending_probes, UInt<1>("h00")) - io.inner.probe.valid <= T_1411 + node T_1338 = eq(UInt<1>("h01"), state) + when T_1338 : + node T_1340 = neq(pending_probes, UInt<1>("h00")) + io.inner.probe.valid <= T_1340 when io.inner.probe.ready : - node T_1413 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_1414 = not(T_1413) - node T_1415 = and(pending_probes, T_1414) - pending_probes <= T_1415 - skip - wire T_1417 : UInt<2>[3] - T_1417[0] <= UInt<1>("h00") - T_1417[1] <= UInt<1>("h01") - T_1417[2] <= UInt<2>("h02") - node T_1422 = eq(T_1417[0], io.inner.release.bits.r_type) - node T_1423 = eq(T_1417[1], io.inner.release.bits.r_type) - node T_1424 = eq(T_1417[2], io.inner.release.bits.r_type) - node T_1426 = or(UInt<1>("h00"), T_1422) - node T_1427 = or(T_1426, T_1423) - node T_1428 = or(T_1427, T_1424) - node T_1430 = eq(T_1428, UInt<1>("h00")) - node T_1431 = or(T_1430, io.outer.acquire.ready) - io.inner.release.ready <= T_1431 + node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00")) + node T_1343 = not(T_1342) + node T_1344 = and(pending_probes, T_1343) + pending_probes <= T_1344 + skip + wire T_1346 : UInt<2>[3] + T_1346[0] <= UInt<1>("h00") + T_1346[1] <= UInt<1>("h01") + T_1346[2] <= UInt<2>("h02") + node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) + node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) + node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) + node T_1355 = or(UInt<1>("h00"), T_1351) + node T_1356 = or(T_1355, T_1352) + node T_1357 = or(T_1356, T_1353) + node T_1359 = eq(T_1357, UInt<1>("h00")) + node T_1360 = or(T_1359, io.outer.acquire.ready) + io.inner.release.ready <= T_1360 when io.inner.release.valid : - wire T_1433 : UInt<2>[3] - T_1433[0] <= UInt<1>("h00") - T_1433[1] <= UInt<1>("h01") - T_1433[2] <= UInt<2>("h02") - node T_1438 = eq(T_1433[0], io.inner.release.bits.r_type) - node T_1439 = eq(T_1433[1], io.inner.release.bits.r_type) - node T_1440 = eq(T_1433[2], io.inner.release.bits.r_type) - node T_1442 = or(UInt<1>("h00"), T_1438) - node T_1443 = or(T_1442, T_1439) - node T_1444 = or(T_1443, T_1440) - when T_1444 : + wire T_1362 : UInt<2>[3] + T_1362[0] <= UInt<1>("h00") + T_1362[1] <= UInt<1>("h01") + T_1362[2] <= UInt<2>("h02") + node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) + node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) + node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) + node T_1371 = or(UInt<1>("h00"), T_1367) + node T_1372 = or(T_1371, T_1368) + node T_1373 = or(T_1372, T_1369) + when T_1373 : io.outer.acquire.valid <= UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") - node T_1448 = subw(release_count, UInt<1>("h01")) - release_count <= T_1448 - node T_1450 = eq(release_count, UInt<1>("h01")) - when T_1450 : - node T_1451 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1452 = mux(pending_outer_write, UInt<2>("h03"), T_1451) - state <= T_1452 + node T_1377 = sub(release_count, UInt<1>("h01")) + node T_1378 = tail(T_1377, 1) + release_count <= T_1378 + node T_1380 = eq(release_count, UInt<1>("h01")) + when T_1380 : + node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381) + state <= T_1382 skip skip skip skip - node T_1454 = eq(T_1444, UInt<1>("h00")) - when T_1454 : - node T_1456 = subw(release_count, UInt<1>("h01")) - release_count <= T_1456 - node T_1458 = eq(release_count, UInt<1>("h01")) - when T_1458 : - node T_1459 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1460 = mux(pending_outer_write, UInt<2>("h03"), T_1459) - state <= T_1460 + node T_1384 = eq(T_1373, UInt<1>("h00")) + when T_1384 : + node T_1386 = sub(release_count, UInt<1>("h01")) + node T_1387 = tail(T_1386, 1) + release_count <= T_1387 + node T_1389 = eq(release_count, UInt<1>("h01")) + when T_1389 : + node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390) + state <= T_1391 skip skip skip skip - node T_1461 = eq(UInt<2>("h03"), state) - when T_1461 : - node T_1463 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_1465 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1466 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1467 = bit(T_1466, 0) - node T_1468 = or(T_1465, T_1467) - node T_1469 = and(T_1463, T_1468) - io.outer.acquire.valid <= T_1469 + node T_1392 = eq(UInt<2>("h03"), state) + when T_1392 : + node T_1394 = eq(pending_ognt_ack, UInt<1>("h00")) + node T_1396 = eq(collect_iacq_data, UInt<1>("h00")) + node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) + node T_1398 = bits(T_1397, 0, 0) + node T_1399 = or(T_1396, T_1398) + node T_1400 = and(T_1394, T_1399) + io.outer.acquire.valid <= T_1400 when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") - node T_1471 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state <= T_1471 + node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) + state <= T_1402 skip skip - node T_1472 = eq(UInt<2>("h02"), state) - when T_1472 : - node T_1474 = eq(pending_ognt_ack, UInt<1>("h00")) - io.outer.acquire.valid <= T_1474 - node T_1475 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1475 : + node T_1403 = eq(UInt<2>("h02"), state) + when T_1403 : + node T_1405 = eq(pending_ognt_ack, UInt<1>("h00")) + io.outer.acquire.valid <= T_1405 + node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) + when T_1406 : state <= UInt<3>("h05") skip skip - node T_1476 = eq(UInt<3>("h05"), state) - when T_1476 : + node T_1407 = eq(UInt<3>("h05"), state) + when T_1407 : io.outer.grant.ready <= io.inner.grant.ready io.inner.grant.valid <= io.outer.grant.valid when ignt_data_done : - node T_1479 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1481 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1482 = and(io.inner.grant.bits.is_builtin_type, T_1481) - node T_1484 = eq(T_1482, UInt<1>("h00")) - node T_1485 = and(T_1479, T_1484) - node T_1486 = mux(T_1485, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1486 + node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) + node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) + node T_1415 = eq(T_1413, UInt<1>("h00")) + node T_1416 = and(T_1410, T_1415) + node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00")) + state <= T_1417 skip skip - node T_1487 = eq(UInt<3>("h04"), state) - when T_1487 : + node T_1418 = eq(UInt<3>("h04"), state) + when T_1418 : io.inner.grant.valid <= UInt<1>("h01") when io.inner.grant.ready : - node T_1491 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1493 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1494 = and(io.inner.grant.bits.is_builtin_type, T_1493) - node T_1496 = eq(T_1494, UInt<1>("h00")) - node T_1497 = and(T_1491, T_1496) - node T_1498 = mux(T_1497, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1498 + node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) + node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) + node T_1427 = eq(T_1425, UInt<1>("h00")) + node T_1428 = and(T_1422, T_1427) + node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00")) + state <= T_1429 skip skip - node T_1499 = eq(UInt<3>("h06"), state) - when T_1499 : + node T_1430 = eq(UInt<3>("h06"), state) + when T_1430 : io.inner.finish.ready <= UInt<1>("h01") when io.inner.finish.valid : state <= UInt<1>("h00") @@ -6718,98 +5379,73 @@ circuit Top : input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - io.has_release_match <= UInt<1>("h00") - io.has_acquire_match <= UInt<1>("h00") - io.has_acquire_conflict <= UInt<1>("h00") - io.outer.grant.ready <= UInt<1>("h00") - io.outer.acquire.bits.data <= UInt<1>("h00") - io.outer.acquire.bits.union <= UInt<1>("h00") - io.outer.acquire.bits.a_type <= UInt<1>("h00") - io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.outer.acquire.bits.addr_beat <= UInt<1>("h00") - io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") - io.outer.acquire.bits.addr_block <= UInt<1>("h00") - io.outer.acquire.valid <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.probe.bits.client_id <= UInt<1>("h00") - io.inner.probe.bits.p_type <= UInt<1>("h00") - io.inner.probe.bits.addr_block <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - io.inner.grant.bits.client_id <= UInt<1>("h00") - io.inner.grant.bits.data <= UInt<1>("h00") - io.inner.grant.bits.g_type <= UInt<1>("h00") - io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") - io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") - io.inner.grant.bits.client_xact_id <= UInt<1>("h00") - io.inner.grant.bits.addr_beat <= UInt<1>("h00") - io.inner.grant.valid <= UInt<1>("h00") - io.inner.acquire.ready <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk, UInt<1>("h00"), xact + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk wire coh : {sharers : UInt<1>} + coh is invalid coh.sharers <= UInt<1>("h00") - coh.sharers <= UInt<1>("h00") - node T_304 = neq(state, UInt<1>("h00")) - node T_305 = and(T_304, xact.is_builtin_type) - wire T_310 : UInt<3>[3] - T_310[0] <= UInt<3>("h04") - T_310[1] <= UInt<3>("h05") - T_310[2] <= UInt<3>("h06") - node T_315 = eq(T_310[0], xact.a_type) - node T_316 = eq(T_310[1], xact.a_type) - node T_317 = eq(T_310[2], xact.a_type) - node T_319 = or(UInt<1>("h00"), T_315) + node T_303 = neq(state, UInt<1>("h00")) + node T_304 = and(T_303, xact.is_builtin_type) + wire T_309 : UInt<3>[3] + T_309[0] <= UInt<3>("h04") + T_309[1] <= UInt<3>("h05") + T_309[2] <= UInt<3>("h06") + node T_314 = eq(T_309[0], xact.a_type) + node T_315 = eq(T_309[1], xact.a_type) + node T_316 = eq(T_309[2], xact.a_type) + node T_318 = or(UInt<1>("h00"), T_314) + node T_319 = or(T_318, T_315) node T_320 = or(T_319, T_316) - node T_321 = or(T_320, T_317) - node T_322 = and(T_305, T_321) - node T_324 = eq(T_322, UInt<1>("h00")) - node T_326 = eq(reset, UInt<1>("h00")) - when T_326 : - node T_328 = eq(T_324, UInt<1>("h00")) - when T_328 : - node T_330 = eq(reset, UInt<1>("h00")) - when T_330 : + node T_321 = and(T_304, T_320) + node T_323 = eq(T_321, UInt<1>("h00")) + node T_325 = eq(reset, UInt<1>("h00")) + when T_325 : + node T_327 = eq(T_323, UInt<1>("h00")) + when T_327 : + node T_329 = eq(reset, UInt<1>("h00")) + when T_329 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") skip stop(clk, UInt<1>(1), 1) skip skip - reg release_count : UInt<1>, clk, reset, UInt<1>("h00") - reg pending_probes : UInt<1>, clk, reset, UInt<1>("h00") - node T_335 = bit(pending_probes, 0) - wire T_337 : UInt<1>[1] - T_337[0] <= T_335 - node T_342 = asUInt(asSInt(UInt<1>("h01"))) - node T_345 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) - node T_346 = or(T_342, T_345) - node T_347 = not(T_342) - node T_348 = or(T_347, T_345) - node T_349 = not(T_348) - node mask_self = mux(UInt<1>("h00"), T_346, T_349) - node T_351 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_351) - reg collect_iacq_data : UInt<1>, clk, reset, UInt<1>("h00") - reg iacq_data_valid : UInt<4>, clk, reset, UInt<4>("h00") - node T_357 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_360 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_363 : UInt<3>[1] - T_363[0] <= UInt<3>("h03") - node T_366 = eq(T_363[0], io.inner.acquire.bits.a_type) - node T_368 = or(UInt<1>("h00"), T_366) - node T_369 = and(T_360, T_368) - node T_370 = and(T_357, T_369) - reg T_372 : UInt<2>, clk, reset, UInt<2>("h00") - when T_370 : - node T_374 = eq(T_372, UInt<2>("h03")) - node T_376 = and(UInt<1>("h00"), T_374) - node T_379 = addw(T_372, UInt<1>("h01")) - node T_380 = mux(T_376, UInt<1>("h00"), T_379) - T_372 <= T_380 - skip - node T_381 = and(T_370, T_374) - node T_382 = mux(T_369, T_372, UInt<1>("h00")) - node iacq_data_done = mux(T_369, T_381, T_357) + reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_334 = bits(pending_probes, 0, 0) + wire T_336 : UInt<1>[1] + T_336[0] <= T_334 + node T_341 = asUInt(asSInt(UInt<1>("h01"))) + node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) + node T_345 = or(T_341, T_344) + node T_346 = not(T_341) + node T_347 = or(T_346, T_344) + node T_348 = not(T_347) + node mask_self = mux(UInt<1>("h00"), T_345, T_348) + node T_350 = not(io.incoherent[0]) + node mask_incoherent = and(mask_self, T_350) + reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) + node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_362 : UInt<3>[1] + T_362[0] <= UInt<3>("h03") + node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) + node T_367 = or(UInt<1>("h00"), T_365) + node T_368 = and(T_359, T_367) + node T_369 = and(T_356, T_368) + reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_369 : + node T_373 = eq(T_371, UInt<2>("h03")) + node T_375 = and(UInt<1>("h00"), T_373) + node T_378 = add(T_371, UInt<1>("h01")) + node T_379 = tail(T_378, 1) + node T_380 = mux(T_375, UInt<1>("h00"), T_379) + T_371 <= T_380 + skip + node T_381 = and(T_369, T_373) + node T_382 = mux(T_368, T_371, UInt<1>("h00")) + node iacq_data_done = mux(T_368, T_381, T_356) node T_384 = and(io.inner.release.ready, io.inner.release.valid) wire T_388 : UInt<2>[3] T_388[0] <= UInt<1>("h00") @@ -6823,577 +5459,523 @@ circuit Top : node T_399 = or(T_398, T_395) node T_400 = and(UInt<1>("h01"), T_399) node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk, reset, UInt<2>("h00") + reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) when T_401 : node T_405 = eq(T_403, UInt<2>("h03")) node T_407 = and(UInt<1>("h00"), T_405) - node T_410 = addw(T_403, UInt<1>("h01")) - node T_411 = mux(T_407, UInt<1>("h00"), T_410) - T_403 <= T_411 - skip - node T_412 = and(T_401, T_405) - node T_413 = mux(T_400, T_403, UInt<1>("h00")) - node irel_data_done = mux(T_400, T_412, T_384) - node T_416 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_420 : UInt<3>[1] - T_420[0] <= UInt<3>("h05") - node T_423 = eq(T_420[0], io.inner.grant.bits.g_type) - node T_425 = or(UInt<1>("h00"), T_423) - wire T_427 : UInt<1>[2] - T_427[0] <= UInt<1>("h00") - T_427[1] <= UInt<1>("h01") - node T_431 = eq(T_427[0], io.inner.grant.bits.g_type) - node T_432 = eq(T_427[1], io.inner.grant.bits.g_type) - node T_434 = or(UInt<1>("h00"), T_431) - node T_435 = or(T_434, T_432) - node T_436 = mux(io.inner.grant.bits.is_builtin_type, T_425, T_435) - node T_437 = and(UInt<1>("h01"), T_436) - node T_438 = and(T_416, T_437) - reg T_440 : UInt<2>, clk, reset, UInt<2>("h00") - when T_438 : - node T_442 = eq(T_440, UInt<2>("h03")) - node T_444 = and(UInt<1>("h00"), T_442) - node T_447 = addw(T_440, UInt<1>("h01")) - node T_448 = mux(T_444, UInt<1>("h00"), T_447) - T_440 <= T_448 - skip - node T_449 = and(T_438, T_442) - node ignt_data_cnt = mux(T_437, T_440, UInt<1>("h00")) - node ignt_data_done = mux(T_437, T_449, T_416) - node T_453 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_455 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) - wire T_458 : UInt<3>[1] - T_458[0] <= UInt<3>("h03") - node T_461 = eq(T_458[0], io.outer.acquire.bits.a_type) - node T_463 = or(UInt<1>("h00"), T_461) - node T_464 = and(T_455, T_463) - node T_465 = and(T_453, T_464) - reg T_467 : UInt<2>, clk, reset, UInt<2>("h00") - when T_465 : - node T_469 = eq(T_467, UInt<2>("h03")) - node T_471 = and(UInt<1>("h00"), T_469) - node T_474 = addw(T_467, UInt<1>("h01")) - node T_475 = mux(T_471, UInt<1>("h00"), T_474) - T_467 <= T_475 - skip - node T_476 = and(T_465, T_469) - node oacq_data_cnt = mux(T_464, T_467, UInt<1>("h00")) - node oacq_data_done = mux(T_464, T_476, T_453) - node T_479 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_484 : UInt<3>[1] - T_484[0] <= UInt<3>("h05") - node T_487 = eq(T_484[0], io.outer.grant.bits.g_type) - node T_489 = or(UInt<1>("h00"), T_487) - wire T_491 : UInt<1>[1] - T_491[0] <= UInt<1>("h00") - node T_494 = eq(T_491[0], io.outer.grant.bits.g_type) - node T_496 = or(UInt<1>("h00"), T_494) - node T_497 = mux(io.outer.grant.bits.is_builtin_type, T_489, T_496) - node T_498 = and(UInt<1>("h01"), T_497) - node T_499 = and(T_479, T_498) - reg T_501 : UInt<2>, clk, reset, UInt<2>("h00") - when T_499 : - node T_503 = eq(T_501, UInt<2>("h03")) - node T_505 = and(UInt<1>("h00"), T_503) - node T_508 = addw(T_501, UInt<1>("h01")) - node T_509 = mux(T_505, UInt<1>("h00"), T_508) - T_501 <= T_509 - skip - node T_510 = and(T_499, T_503) - node T_511 = mux(T_498, T_501, UInt<1>("h00")) - node ognt_data_done = mux(T_498, T_510, T_479) - reg pending_ognt_ack : UInt<1>, clk, reset, UInt<1>("h00") - wire T_519 : UInt<3>[3] - T_519[0] <= UInt<3>("h02") - T_519[1] <= UInt<3>("h03") - T_519[2] <= UInt<3>("h04") - node T_524 = eq(T_519[0], xact.a_type) - node T_525 = eq(T_519[1], xact.a_type) - node T_526 = eq(T_519[2], xact.a_type) - node T_528 = or(UInt<1>("h00"), T_524) - node T_529 = or(T_528, T_525) - node T_530 = or(T_529, T_526) - node pending_outer_write = and(xact.is_builtin_type, T_530) - wire T_536 : UInt<3>[3] - T_536[0] <= UInt<3>("h02") - T_536[1] <= UInt<3>("h03") - T_536[2] <= UInt<3>("h04") - node T_541 = eq(T_536[0], io.inner.acquire.bits.a_type) - node T_542 = eq(T_536[1], io.inner.acquire.bits.a_type) - node T_543 = eq(T_536[2], io.inner.acquire.bits.a_type) - node T_545 = or(UInt<1>("h00"), T_541) - node T_546 = or(T_545, T_542) - node T_547 = or(T_546, T_543) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_547) - wire T_552 : UInt<3>[2] - T_552[0] <= UInt<3>("h05") - T_552[1] <= UInt<3>("h04") - node T_556 = eq(T_552[0], io.inner.grant.bits.g_type) - node T_557 = eq(T_552[1], io.inner.grant.bits.g_type) - node T_559 = or(UInt<1>("h00"), T_556) - node T_560 = or(T_559, T_557) - wire T_562 : UInt<1>[2] - T_562[0] <= UInt<1>("h00") - T_562[1] <= UInt<1>("h01") - node T_566 = eq(T_562[0], io.inner.grant.bits.g_type) - node T_567 = eq(T_562[1], io.inner.grant.bits.g_type) - node T_569 = or(UInt<1>("h00"), T_566) - node T_570 = or(T_569, T_567) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_560, T_570) - node T_590 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) - node T_591 = mux(T_590, UInt<3>("h01"), UInt<3>("h03")) - node T_592 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) - node T_593 = mux(T_592, UInt<3>("h01"), T_591) - node T_594 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h04"), T_593) - node T_596 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h03"), T_595) - node T_598 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h03"), T_597) - node T_600 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h05"), T_599) - node T_602 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h04"), T_601) - node T_604 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) - node T_607 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_608 = mux(T_607, UInt<1>("h00"), UInt<1>("h01")) - node T_609 = mux(T_604, T_608, UInt<1>("h01")) - node T_610 = mux(io.inner.acquire.bits.is_builtin_type, T_603, T_609) - wire T_619 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_619.client_id <= UInt<1>("h00") - T_619.data <= UInt<1>("h00") - T_619.g_type <= UInt<1>("h00") - T_619.is_builtin_type <= UInt<1>("h00") - T_619.manager_xact_id <= UInt<1>("h00") - T_619.client_xact_id <= UInt<1>("h00") - T_619.addr_beat <= UInt<1>("h00") - T_619.client_id <= io.inner.acquire.bits.client_id - T_619.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_619.g_type <= T_610 - T_619.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_619.manager_xact_id <= UInt<3>("h05") - T_619.addr_beat <= UInt<1>("h00") - T_619.data <= UInt<1>("h00") - wire T_637 : UInt<3>[2] - T_637[0] <= UInt<3>("h05") - T_637[1] <= UInt<3>("h04") - node T_641 = eq(T_637[0], T_619.g_type) - node T_642 = eq(T_637[1], T_619.g_type) - node T_644 = or(UInt<1>("h00"), T_641) - node T_645 = or(T_644, T_642) - wire T_647 : UInt<1>[2] - T_647[0] <= UInt<1>("h00") - T_647[1] <= UInt<1>("h01") - node T_651 = eq(T_647[0], T_619.g_type) - node T_652 = eq(T_647[1], T_619.g_type) - node T_654 = or(UInt<1>("h00"), T_651) - node T_655 = or(T_654, T_652) - node pending_outer_read_ = mux(T_619.is_builtin_type, T_645, T_655) - wire T_661 : UInt<3>[3] - T_661[0] <= UInt<3>("h02") - T_661[1] <= UInt<3>("h00") - T_661[2] <= UInt<3>("h04") - node T_666 = eq(T_661[0], xact.a_type) - node T_667 = eq(T_661[1], xact.a_type) - node T_668 = eq(T_661[2], xact.a_type) - node T_670 = or(UInt<1>("h00"), T_666) - node T_671 = or(T_670, T_667) - node T_672 = or(T_671, T_668) - node subblock_type = and(xact.is_builtin_type, T_672) - node T_674 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_675 = neq(state, UInt<1>("h00")) - node T_676 = and(T_674, T_675) - node T_678 = eq(collect_iacq_data, UInt<1>("h00")) - node T_679 = and(T_676, T_678) - io.has_acquire_conflict <= T_679 - node T_680 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_681 = and(T_680, collect_iacq_data) - io.has_acquire_match <= T_681 - node T_682 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_684 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) - node T_685 = and(T_682, T_684) - node T_686 = eq(state, UInt<1>("h01")) - node T_687 = and(T_685, T_686) - io.has_release_match <= T_687 - node T_692 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_698 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_410 = add(T_403, UInt<1>("h01")) + node T_411 = tail(T_410, 1) + node T_412 = mux(T_407, UInt<1>("h00"), T_411) + T_403 <= T_412 + skip + node T_413 = and(T_401, T_405) + node T_414 = mux(T_400, T_403, UInt<1>("h00")) + node irel_data_done = mux(T_400, T_413, T_384) + node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) + wire T_421 : UInt<3>[1] + T_421[0] <= UInt<3>("h05") + node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) + node T_426 = or(UInt<1>("h00"), T_424) + wire T_428 : UInt<1>[2] + T_428[0] <= UInt<1>("h00") + T_428[1] <= UInt<1>("h01") + node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) + node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) + node T_435 = or(UInt<1>("h00"), T_432) + node T_436 = or(T_435, T_433) + node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) + node T_438 = and(UInt<1>("h01"), T_437) + node T_439 = and(T_417, T_438) + reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_439 : + node T_443 = eq(T_441, UInt<2>("h03")) + node T_445 = and(UInt<1>("h00"), T_443) + node T_448 = add(T_441, UInt<1>("h01")) + node T_449 = tail(T_448, 1) + node T_450 = mux(T_445, UInt<1>("h00"), T_449) + T_441 <= T_450 + skip + node T_451 = and(T_439, T_443) + node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00")) + node ignt_data_done = mux(T_438, T_451, T_417) + node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) + wire T_460 : UInt<3>[1] + T_460[0] <= UInt<3>("h03") + node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) + node T_465 = or(UInt<1>("h00"), T_463) + node T_466 = and(T_457, T_465) + node T_467 = and(T_455, T_466) + reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_467 : + node T_471 = eq(T_469, UInt<2>("h03")) + node T_473 = and(UInt<1>("h00"), T_471) + node T_476 = add(T_469, UInt<1>("h01")) + node T_477 = tail(T_476, 1) + node T_478 = mux(T_473, UInt<1>("h00"), T_477) + T_469 <= T_478 + skip + node T_479 = and(T_467, T_471) + node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00")) + node oacq_data_done = mux(T_466, T_479, T_455) + node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_487 : UInt<3>[1] + T_487[0] <= UInt<3>("h05") + node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) + node T_492 = or(UInt<1>("h00"), T_490) + wire T_494 : UInt<1>[1] + T_494[0] <= UInt<1>("h00") + node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) + node T_499 = or(UInt<1>("h00"), T_497) + node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) + node T_501 = and(UInt<1>("h01"), T_500) + node T_502 = and(T_482, T_501) + reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_502 : + node T_506 = eq(T_504, UInt<2>("h03")) + node T_508 = and(UInt<1>("h00"), T_506) + node T_511 = add(T_504, UInt<1>("h01")) + node T_512 = tail(T_511, 1) + node T_513 = mux(T_508, UInt<1>("h00"), T_512) + T_504 <= T_513 + skip + node T_514 = and(T_502, T_506) + node T_515 = mux(T_501, T_504, UInt<1>("h00")) + node ognt_data_done = mux(T_501, T_514, T_482) + reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + wire T_523 : UInt<3>[3] + T_523[0] <= UInt<3>("h02") + T_523[1] <= UInt<3>("h03") + T_523[2] <= UInt<3>("h04") + node T_528 = eq(T_523[0], xact.a_type) + node T_529 = eq(T_523[1], xact.a_type) + node T_530 = eq(T_523[2], xact.a_type) + node T_532 = or(UInt<1>("h00"), T_528) + node T_533 = or(T_532, T_529) + node T_534 = or(T_533, T_530) + node pending_outer_write = and(xact.is_builtin_type, T_534) + wire T_540 : UInt<3>[3] + T_540[0] <= UInt<3>("h02") + T_540[1] <= UInt<3>("h03") + T_540[2] <= UInt<3>("h04") + node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) + node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) + node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) + node T_549 = or(UInt<1>("h00"), T_545) + node T_550 = or(T_549, T_546) + node T_551 = or(T_550, T_547) + node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) + wire T_556 : UInt<3>[2] + T_556[0] <= UInt<3>("h05") + T_556[1] <= UInt<3>("h04") + node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) + node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) + node T_563 = or(UInt<1>("h00"), T_560) + node T_564 = or(T_563, T_561) + wire T_566 : UInt<1>[2] + T_566[0] <= UInt<1>("h00") + T_566[1] <= UInt<1>("h01") + node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) + node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) + node T_573 = or(UInt<1>("h00"), T_570) + node T_574 = or(T_573, T_571) + node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) + node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) + node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03")) + node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) + node T_597 = mux(T_596, UInt<3>("h01"), T_595) + node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) + node T_599 = mux(T_598, UInt<3>("h04"), T_597) + node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) + node T_601 = mux(T_600, UInt<3>("h03"), T_599) + node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) + node T_603 = mux(T_602, UInt<3>("h03"), T_601) + node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) + node T_605 = mux(T_604, UInt<3>("h05"), T_603) + node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) + node T_607 = mux(T_606, UInt<3>("h04"), T_605) + node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) + node T_611 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01")) + node T_613 = mux(T_608, T_612, UInt<1>("h01")) + node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) + wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} + T_623 is invalid + T_623.client_id <= io.inner.acquire.bits.client_id + T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type + T_623.g_type <= T_614 + T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id + T_623.manager_xact_id <= UInt<3>("h05") + T_623.addr_beat <= UInt<1>("h00") + T_623.data <= UInt<1>("h00") + wire T_634 : UInt<3>[2] + T_634[0] <= UInt<3>("h05") + T_634[1] <= UInt<3>("h04") + node T_638 = eq(T_634[0], T_623.g_type) + node T_639 = eq(T_634[1], T_623.g_type) + node T_641 = or(UInt<1>("h00"), T_638) + node T_642 = or(T_641, T_639) + wire T_644 : UInt<1>[2] + T_644[0] <= UInt<1>("h00") + T_644[1] <= UInt<1>("h01") + node T_648 = eq(T_644[0], T_623.g_type) + node T_649 = eq(T_644[1], T_623.g_type) + node T_651 = or(UInt<1>("h00"), T_648) + node T_652 = or(T_651, T_649) + node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) + wire T_658 : UInt<3>[3] + T_658[0] <= UInt<3>("h02") + T_658[1] <= UInt<3>("h00") + T_658[2] <= UInt<3>("h04") + node T_663 = eq(T_658[0], xact.a_type) + node T_664 = eq(T_658[1], xact.a_type) + node T_665 = eq(T_658[2], xact.a_type) + node T_667 = or(UInt<1>("h00"), T_663) + node T_668 = or(T_667, T_664) + node T_669 = or(T_668, T_665) + node subblock_type = and(xact.is_builtin_type, T_669) + node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) + node T_672 = neq(state, UInt<1>("h00")) + node T_673 = and(T_671, T_672) + node T_675 = eq(collect_iacq_data, UInt<1>("h00")) + node T_676 = and(T_673, T_675) + io.has_acquire_conflict <= T_676 + node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) + node T_678 = and(T_677, collect_iacq_data) + io.has_acquire_match <= T_678 + node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) + node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) + node T_682 = and(T_679, T_681) + node T_683 = eq(state, UInt<1>("h01")) + node T_684 = and(T_682, T_683) + io.has_release_match <= T_684 + node T_689 = asUInt(asSInt(UInt<16>("h0ffff"))) + node T_695 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_696 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_697 = cat(T_695, T_696) node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_700 = cat(T_698, T_699) - node T_702 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_703 = cat(UInt<3>("h07"), T_702) - node T_705 = cat(T_692, UInt<1>("h01")) - node T_707 = cat(T_692, UInt<1>("h01")) - node T_709 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_710 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_711 = cat(T_709, T_710) - node T_713 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_715 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_716 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_717 = mux(T_716, T_715, UInt<1>("h00")) - node T_718 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_719 = mux(T_718, T_713, T_717) - node T_720 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_721 = mux(T_720, T_711, T_719) - node T_722 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_723 = mux(T_722, T_707, T_721) - node T_724 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_725 = mux(T_724, T_705, T_723) - node T_726 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_727 = mux(T_726, T_703, T_725) - node T_728 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_729 = mux(T_728, T_700, T_727) + node T_700 = cat(UInt<3>("h07"), T_699) + node T_702 = cat(T_689, UInt<1>("h01")) + node T_704 = cat(T_689, UInt<1>("h01")) + node T_706 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_707 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_708 = cat(T_706, T_707) + node T_710 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_712 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_713 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_714 = mux(T_713, T_712, UInt<1>("h00")) + node T_715 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_716 = mux(T_715, T_710, T_714) + node T_717 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_718 = mux(T_717, T_708, T_716) + node T_719 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_720 = mux(T_719, T_704, T_718) + node T_721 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_722 = mux(T_721, T_702, T_720) + node T_723 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_724 = mux(T_723, T_700, T_722) + node T_725 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_726 = mux(T_725, T_697, T_724) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe.data <= UInt<1>("h00") - oacq_probe.union <= UInt<1>("h00") - oacq_probe.a_type <= UInt<1>("h00") - oacq_probe.is_builtin_type <= UInt<1>("h00") - oacq_probe.addr_beat <= UInt<1>("h00") - oacq_probe.client_xact_id <= UInt<1>("h00") - oacq_probe.addr_block <= UInt<1>("h00") + oacq_probe is invalid oacq_probe.is_builtin_type <= UInt<1>("h01") oacq_probe.a_type <= UInt<3>("h03") oacq_probe.client_xact_id <= UInt<3>("h05") oacq_probe.addr_block <= io.inner.release.bits.addr_block oacq_probe.addr_beat <= io.inner.release.bits.addr_beat oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_729 - node T_754 = bits(xact.union, 12, 9) - node T_755 = bits(T_754, 3, 3) - node T_757 = dshl(UInt<1>("h01"), T_755) - node T_759 = eq(xact.a_type, UInt<3>("h04")) - node T_760 = and(xact.is_builtin_type, T_759) - node T_761 = bit(T_757, 0) - node T_762 = bit(T_757, 1) - wire T_764 : UInt<1>[2] - T_764[0] <= T_761 - T_764[1] <= T_762 - node T_769 = subw(UInt<8>("h00"), T_764[0]) - node T_771 = subw(UInt<8>("h00"), T_764[1]) - wire T_773 : UInt<8>[2] - T_773[0] <= T_769 - T_773[1] <= T_771 - node T_777 = cat(T_773[1], T_773[0]) - node T_779 = eq(xact.a_type, UInt<3>("h03")) - node T_780 = and(xact.is_builtin_type, T_779) - node T_782 = eq(xact.a_type, UInt<3>("h02")) - node T_783 = and(xact.is_builtin_type, T_782) - node T_784 = or(T_780, T_783) - node T_785 = bits(xact.union, 16, 1) - node T_787 = mux(T_784, T_785, UInt<16>("h00")) - node T_788 = mux(T_760, T_777, T_787) - node T_796 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_797 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_798 = cat(T_796, T_797) + oacq_probe.union <= T_726 + node T_744 = bits(xact.union, 12, 9) + node T_745 = bits(T_744, 3, 3) + node T_747 = dshl(UInt<1>("h01"), T_745) + node T_749 = eq(xact.a_type, UInt<3>("h04")) + node T_750 = and(xact.is_builtin_type, T_749) + node T_751 = bits(T_747, 0, 0) + node T_752 = bits(T_747, 1, 1) + wire T_754 : UInt<1>[2] + T_754[0] <= T_751 + T_754[1] <= T_752 + node T_759 = sub(UInt<8>("h00"), T_754[0]) + node T_760 = tail(T_759, 1) + node T_762 = sub(UInt<8>("h00"), T_754[1]) + node T_763 = tail(T_762, 1) + wire T_765 : UInt<8>[2] + T_765[0] <= T_760 + T_765[1] <= T_763 + node T_769 = cat(T_765[1], T_765[0]) + node T_771 = eq(xact.a_type, UInt<3>("h03")) + node T_772 = and(xact.is_builtin_type, T_771) + node T_774 = eq(xact.a_type, UInt<3>("h02")) + node T_775 = and(xact.is_builtin_type, T_774) + node T_776 = or(T_772, T_775) + node T_777 = bits(xact.union, 16, 1) + node T_779 = mux(T_776, T_777, UInt<16>("h00")) + node T_780 = mux(T_750, T_769, T_779) + node T_788 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_789 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_790 = cat(T_788, T_789) + node T_792 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_793 = cat(UInt<3>("h07"), T_792) + node T_795 = cat(T_780, UInt<1>("h01")) + node T_797 = cat(T_780, UInt<1>("h01")) + node T_799 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_801 = cat(UInt<3>("h07"), T_800) - node T_803 = cat(T_788, UInt<1>("h01")) - node T_805 = cat(T_788, UInt<1>("h01")) - node T_807 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_808 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_809 = cat(T_807, T_808) - node T_811 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_813 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_814 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_815 = mux(T_814, T_813, UInt<1>("h00")) - node T_816 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_817 = mux(T_816, T_811, T_815) - node T_818 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_819 = mux(T_818, T_809, T_817) - node T_820 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_821 = mux(T_820, T_805, T_819) - node T_822 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_823 = mux(T_822, T_803, T_821) - node T_824 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_825 = mux(T_824, T_801, T_823) - node T_826 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_827 = mux(T_826, T_798, T_825) + node T_801 = cat(T_799, T_800) + node T_803 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_805 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_806 = eq(UInt<3>("h06"), UInt<3>("h02")) + node T_807 = mux(T_806, T_805, UInt<1>("h00")) + node T_808 = eq(UInt<3>("h05"), UInt<3>("h02")) + node T_809 = mux(T_808, T_803, T_807) + node T_810 = eq(UInt<3>("h04"), UInt<3>("h02")) + node T_811 = mux(T_810, T_801, T_809) + node T_812 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_813 = mux(T_812, T_797, T_811) + node T_814 = eq(UInt<3>("h02"), UInt<3>("h02")) + node T_815 = mux(T_814, T_795, T_813) + node T_816 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_817 = mux(T_816, T_793, T_815) + node T_818 = eq(UInt<3>("h00"), UInt<3>("h02")) + node T_819 = mux(T_818, T_790, T_817) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat.data <= UInt<1>("h00") - oacq_write_beat.union <= UInt<1>("h00") - oacq_write_beat.a_type <= UInt<1>("h00") - oacq_write_beat.is_builtin_type <= UInt<1>("h00") - oacq_write_beat.addr_beat <= UInt<1>("h00") - oacq_write_beat.client_xact_id <= UInt<1>("h00") - oacq_write_beat.addr_block <= UInt<1>("h00") + oacq_write_beat is invalid oacq_write_beat.is_builtin_type <= UInt<1>("h01") oacq_write_beat.a_type <= UInt<3>("h02") oacq_write_beat.client_xact_id <= UInt<3>("h05") oacq_write_beat.addr_block <= xact.addr_block oacq_write_beat.addr_beat <= xact.addr_beat oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_827 - node T_861 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_862 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_863 = cat(T_861, T_862) - node T_865 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_866 = cat(UInt<3>("h07"), T_865) - node T_868 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_870 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_872 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_873 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_874 = cat(T_872, T_873) - node T_876 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_878 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_879 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_880 = mux(T_879, T_878, UInt<1>("h00")) - node T_881 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_882 = mux(T_881, T_876, T_880) - node T_883 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_884 = mux(T_883, T_874, T_882) - node T_885 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_886 = mux(T_885, T_870, T_884) - node T_887 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_888 = mux(T_887, T_868, T_886) - node T_889 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_890 = mux(T_889, T_866, T_888) - node T_891 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_892 = mux(T_891, T_863, T_890) + oacq_write_beat.union <= T_819 + node T_846 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_847 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_848 = cat(T_846, T_847) + node T_850 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_851 = cat(UInt<3>("h07"), T_850) + node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) + node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) + node T_857 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_858 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_859 = cat(T_857, T_858) + node T_861 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_863 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_864 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_865 = mux(T_864, T_863, UInt<1>("h00")) + node T_866 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_867 = mux(T_866, T_861, T_865) + node T_868 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_869 = mux(T_868, T_859, T_867) + node T_870 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_871 = mux(T_870, T_855, T_869) + node T_872 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_873 = mux(T_872, T_853, T_871) + node T_874 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_875 = mux(T_874, T_851, T_873) + node T_876 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_877 = mux(T_876, T_848, T_875) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block.data <= UInt<1>("h00") - oacq_write_block.union <= UInt<1>("h00") - oacq_write_block.a_type <= UInt<1>("h00") - oacq_write_block.is_builtin_type <= UInt<1>("h00") - oacq_write_block.addr_beat <= UInt<1>("h00") - oacq_write_block.client_xact_id <= UInt<1>("h00") - oacq_write_block.addr_block <= UInt<1>("h00") + oacq_write_block is invalid oacq_write_block.is_builtin_type <= UInt<1>("h01") oacq_write_block.a_type <= UInt<3>("h03") oacq_write_block.client_xact_id <= UInt<3>("h05") oacq_write_block.addr_block <= xact.addr_block oacq_write_block.addr_beat <= oacq_data_cnt oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_892 - node T_917 = bits(xact.union, 12, 9) - node T_918 = bits(xact.union, 8, 6) - node T_926 = cat(T_917, T_918) - node T_927 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_928 = cat(T_926, T_927) - node T_930 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_931 = cat(T_918, T_930) - node T_933 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_935 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_937 = cat(T_917, T_918) - node T_938 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_939 = cat(T_937, T_938) - node T_941 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_943 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_944 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_945 = mux(T_944, T_943, UInt<1>("h00")) - node T_946 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_947 = mux(T_946, T_941, T_945) - node T_948 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_949 = mux(T_948, T_939, T_947) - node T_950 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_951 = mux(T_950, T_935, T_949) - node T_952 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_953 = mux(T_952, T_933, T_951) - node T_954 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_955 = mux(T_954, T_931, T_953) - node T_956 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_957 = mux(T_956, T_928, T_955) + oacq_write_block.union <= T_877 + node T_895 = bits(xact.union, 12, 9) + node T_896 = bits(xact.union, 8, 6) + node T_904 = cat(T_895, T_896) + node T_905 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_906 = cat(T_904, T_905) + node T_908 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_909 = cat(T_896, T_908) + node T_911 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_913 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_915 = cat(T_895, T_896) + node T_916 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_917 = cat(T_915, T_916) + node T_919 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_921 = cat(UInt<5>("h01"), UInt<1>("h00")) + node T_922 = eq(UInt<3>("h06"), UInt<3>("h00")) + node T_923 = mux(T_922, T_921, UInt<1>("h00")) + node T_924 = eq(UInt<3>("h05"), UInt<3>("h00")) + node T_925 = mux(T_924, T_919, T_923) + node T_926 = eq(UInt<3>("h04"), UInt<3>("h00")) + node T_927 = mux(T_926, T_917, T_925) + node T_928 = eq(UInt<3>("h03"), UInt<3>("h00")) + node T_929 = mux(T_928, T_913, T_927) + node T_930 = eq(UInt<3>("h02"), UInt<3>("h00")) + node T_931 = mux(T_930, T_911, T_929) + node T_932 = eq(UInt<3>("h01"), UInt<3>("h00")) + node T_933 = mux(T_932, T_909, T_931) + node T_934 = eq(UInt<3>("h00"), UInt<3>("h00")) + node T_935 = mux(T_934, T_906, T_933) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= UInt<1>("h00") - oacq_read_beat.a_type <= UInt<1>("h00") - oacq_read_beat.is_builtin_type <= UInt<1>("h00") - oacq_read_beat.addr_beat <= UInt<1>("h00") - oacq_read_beat.client_xact_id <= UInt<1>("h00") - oacq_read_beat.addr_block <= UInt<1>("h00") + oacq_read_beat is invalid oacq_read_beat.is_builtin_type <= UInt<1>("h01") oacq_read_beat.a_type <= UInt<3>("h00") oacq_read_beat.client_xact_id <= UInt<3>("h05") oacq_read_beat.addr_block <= xact.addr_block oacq_read_beat.addr_beat <= xact.addr_beat oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= T_957 - node T_991 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_992 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_993 = cat(T_991, T_992) - node T_995 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_996 = cat(UInt<3>("h07"), T_995) - node T_998 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1000 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1002 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1003 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1004 = cat(T_1002, T_1003) - node T_1006 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1008 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1009 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_1010 = mux(T_1009, T_1008, UInt<1>("h00")) - node T_1011 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_1012 = mux(T_1011, T_1006, T_1010) - node T_1013 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_1014 = mux(T_1013, T_1004, T_1012) - node T_1015 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_1016 = mux(T_1015, T_1000, T_1014) - node T_1017 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_1018 = mux(T_1017, T_998, T_1016) - node T_1019 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_1020 = mux(T_1019, T_996, T_1018) - node T_1021 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_1022 = mux(T_1021, T_993, T_1020) + oacq_read_beat.union <= T_935 + node T_962 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_963 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_964 = cat(T_962, T_963) + node T_966 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_967 = cat(UInt<3>("h07"), T_966) + node T_969 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_971 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_973 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_974 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_975 = cat(T_973, T_974) + node T_977 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_979 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_980 = eq(UInt<3>("h06"), UInt<3>("h01")) + node T_981 = mux(T_980, T_979, UInt<1>("h00")) + node T_982 = eq(UInt<3>("h05"), UInt<3>("h01")) + node T_983 = mux(T_982, T_977, T_981) + node T_984 = eq(UInt<3>("h04"), UInt<3>("h01")) + node T_985 = mux(T_984, T_975, T_983) + node T_986 = eq(UInt<3>("h03"), UInt<3>("h01")) + node T_987 = mux(T_986, T_971, T_985) + node T_988 = eq(UInt<3>("h02"), UInt<3>("h01")) + node T_989 = mux(T_988, T_969, T_987) + node T_990 = eq(UInt<3>("h01"), UInt<3>("h01")) + node T_991 = mux(T_990, T_967, T_989) + node T_992 = eq(UInt<3>("h00"), UInt<3>("h01")) + node T_993 = mux(T_992, T_964, T_991) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= UInt<1>("h00") - oacq_read_block.a_type <= UInt<1>("h00") - oacq_read_block.is_builtin_type <= UInt<1>("h00") - oacq_read_block.addr_beat <= UInt<1>("h00") - oacq_read_block.client_xact_id <= UInt<1>("h00") - oacq_read_block.addr_block <= UInt<1>("h00") + oacq_read_block is invalid oacq_read_block.is_builtin_type <= UInt<1>("h01") oacq_read_block.a_type <= UInt<3>("h01") oacq_read_block.client_xact_id <= UInt<3>("h05") oacq_read_block.addr_block <= xact.addr_block oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= T_1022 + oacq_read_block.union <= T_993 io.outer.acquire.valid <= UInt<1>("h00") - node T_1047 = eq(state, UInt<1>("h01")) - node T_1048 = eq(state, UInt<2>("h03")) - wire T_1057 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1057 <- oacq_write_block - when subblock_type : - T_1057 <- oacq_write_beat - skip - wire T_1073 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1073 <- oacq_read_block - when subblock_type : - T_1073 <- oacq_read_beat - skip - wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1089 <- T_1073 - when T_1048 : - T_1089 <- T_1057 - skip - wire T_1105 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1105 <- T_1089 - when T_1047 : - T_1105 <- oacq_probe - skip - io.outer.acquire.bits <- T_1105 + node T_1011 = eq(state, UInt<1>("h01")) + node T_1012 = eq(state, UInt<2>("h03")) + node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) + node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) + node T_1029 = mux(T_1012, T_1013, T_1021) + node T_1037 = mux(T_1011, oacq_probe, T_1029) + io.outer.acquire.bits <- T_1037 io.outer.grant.ready <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") - node T_1122 = eq(UInt<3>("h04"), xact.a_type) - node T_1123 = mux(T_1122, UInt<1>("h00"), UInt<2>("h02")) - node T_1124 = eq(UInt<3>("h06"), xact.a_type) - node T_1125 = mux(T_1124, UInt<1>("h00"), T_1123) - node T_1126 = eq(UInt<3>("h05"), xact.a_type) - node T_1127 = mux(T_1126, UInt<2>("h02"), T_1125) - node T_1128 = eq(UInt<3>("h02"), xact.a_type) - node T_1129 = mux(T_1128, UInt<1>("h00"), T_1127) - node T_1130 = eq(UInt<3>("h00"), xact.a_type) - node T_1131 = mux(T_1130, UInt<2>("h02"), T_1129) - node T_1132 = eq(UInt<3>("h03"), xact.a_type) - node T_1133 = mux(T_1132, UInt<1>("h00"), T_1131) - node T_1134 = eq(UInt<3>("h01"), xact.a_type) - node T_1135 = mux(T_1134, UInt<2>("h02"), T_1133) - node T_1136 = eq(UInt<1>("h01"), xact.a_type) - node T_1137 = mux(T_1136, UInt<1>("h00"), UInt<2>("h02")) - node T_1138 = eq(UInt<1>("h00"), xact.a_type) - node T_1139 = mux(T_1138, UInt<1>("h01"), T_1137) - node T_1140 = mux(xact.is_builtin_type, T_1135, T_1139) - wire T_1145 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1145.client_id <= UInt<1>("h00") - T_1145.p_type <= UInt<1>("h00") - T_1145.addr_block <= UInt<1>("h00") - T_1145.client_id <= UInt<1>("h00") - T_1145.p_type <= T_1140 - T_1145.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1145 + node T_1054 = eq(UInt<3>("h04"), xact.a_type) + node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02")) + node T_1056 = eq(UInt<3>("h06"), xact.a_type) + node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055) + node T_1058 = eq(UInt<3>("h05"), xact.a_type) + node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057) + node T_1060 = eq(UInt<3>("h02"), xact.a_type) + node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059) + node T_1062 = eq(UInt<3>("h00"), xact.a_type) + node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061) + node T_1064 = eq(UInt<3>("h03"), xact.a_type) + node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063) + node T_1066 = eq(UInt<3>("h01"), xact.a_type) + node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065) + node T_1068 = eq(UInt<1>("h01"), xact.a_type) + node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02")) + node T_1070 = eq(UInt<1>("h00"), xact.a_type) + node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069) + node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) + wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} + T_1077 is invalid + T_1077.client_id <= UInt<1>("h00") + T_1077.p_type <= T_1072 + T_1077.addr_block <= xact.addr_block + io.inner.probe.bits <- T_1077 io.inner.grant.valid <= UInt<1>("h00") - node T_1171 = eq(UInt<3>("h06"), xact.a_type) - node T_1172 = mux(T_1171, UInt<3>("h01"), UInt<3>("h03")) - node T_1173 = eq(UInt<3>("h05"), xact.a_type) - node T_1174 = mux(T_1173, UInt<3>("h01"), T_1172) - node T_1175 = eq(UInt<3>("h04"), xact.a_type) - node T_1176 = mux(T_1175, UInt<3>("h04"), T_1174) - node T_1177 = eq(UInt<3>("h03"), xact.a_type) - node T_1178 = mux(T_1177, UInt<3>("h03"), T_1176) - node T_1179 = eq(UInt<3>("h02"), xact.a_type) - node T_1180 = mux(T_1179, UInt<3>("h03"), T_1178) - node T_1181 = eq(UInt<3>("h01"), xact.a_type) - node T_1182 = mux(T_1181, UInt<3>("h05"), T_1180) - node T_1183 = eq(UInt<3>("h00"), xact.a_type) - node T_1184 = mux(T_1183, UInt<3>("h04"), T_1182) - node T_1185 = eq(xact.a_type, UInt<1>("h00")) - node T_1188 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1189 = mux(T_1188, UInt<1>("h00"), UInt<1>("h01")) - node T_1190 = mux(T_1185, T_1189, UInt<1>("h01")) - node T_1191 = mux(xact.is_builtin_type, T_1184, T_1190) - wire T_1200 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1200.client_id <= UInt<1>("h00") - T_1200.data <= UInt<1>("h00") - T_1200.g_type <= UInt<1>("h00") - T_1200.is_builtin_type <= UInt<1>("h00") - T_1200.manager_xact_id <= UInt<1>("h00") - T_1200.client_xact_id <= UInt<1>("h00") - T_1200.addr_beat <= UInt<1>("h00") - T_1200.client_id <= xact.client_id - T_1200.is_builtin_type <= xact.is_builtin_type - T_1200.g_type <= T_1191 - T_1200.client_xact_id <= xact.client_xact_id - T_1200.manager_xact_id <= UInt<3>("h05") - T_1200.addr_beat <= UInt<1>("h00") - T_1200.data <= UInt<1>("h00") - io.inner.grant.bits <- T_1200 + node T_1100 = eq(UInt<3>("h06"), xact.a_type) + node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03")) + node T_1102 = eq(UInt<3>("h05"), xact.a_type) + node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101) + node T_1104 = eq(UInt<3>("h04"), xact.a_type) + node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103) + node T_1106 = eq(UInt<3>("h03"), xact.a_type) + node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105) + node T_1108 = eq(UInt<3>("h02"), xact.a_type) + node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107) + node T_1110 = eq(UInt<3>("h01"), xact.a_type) + node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109) + node T_1112 = eq(UInt<3>("h00"), xact.a_type) + node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111) + node T_1114 = eq(xact.a_type, UInt<1>("h00")) + node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01")) + node T_1119 = mux(T_1114, T_1118, UInt<1>("h01")) + node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) + wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} + T_1129 is invalid + T_1129.client_id <= xact.client_id + T_1129.is_builtin_type <= xact.is_builtin_type + T_1129.g_type <= T_1120 + T_1129.client_xact_id <= xact.client_xact_id + T_1129.manager_xact_id <= UInt<3>("h05") + T_1129.addr_beat <= UInt<1>("h00") + T_1129.data <= UInt<1>("h00") + io.inner.grant.bits <- T_1129 io.inner.acquire.ready <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") - node T_1218 = neq(state, UInt<1>("h00")) - node T_1219 = and(T_1218, collect_iacq_data) - node T_1220 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1221 = and(T_1219, T_1220) - node T_1222 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1223 = and(T_1221, T_1222) - node T_1225 = eq(T_1223, UInt<1>("h00")) - node T_1227 = eq(reset, UInt<1>("h00")) - when T_1227 : - node T_1229 = eq(T_1225, UInt<1>("h00")) - when T_1229 : - node T_1231 = eq(reset, UInt<1>("h00")) - when T_1231 : + node T_1140 = neq(state, UInt<1>("h00")) + node T_1141 = and(T_1140, collect_iacq_data) + node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1143 = and(T_1141, T_1142) + node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) + node T_1145 = and(T_1143, T_1144) + node T_1147 = eq(T_1145, UInt<1>("h00")) + node T_1149 = eq(reset, UInt<1>("h00")) + when T_1149 : + node T_1151 = eq(T_1147, UInt<1>("h00")) + when T_1151 : + node T_1153 = eq(reset, UInt<1>("h00")) + when T_1153 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1232 = neq(state, UInt<1>("h00")) - node T_1233 = and(T_1232, collect_iacq_data) - node T_1234 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1235 = and(T_1233, T_1234) - node T_1236 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1237 = and(T_1235, T_1236) - node T_1239 = eq(T_1237, UInt<1>("h00")) - node T_1241 = eq(reset, UInt<1>("h00")) - when T_1241 : - node T_1243 = eq(T_1239, UInt<1>("h00")) - when T_1243 : - node T_1245 = eq(reset, UInt<1>("h00")) - when T_1245 : + node T_1154 = neq(state, UInt<1>("h00")) + node T_1155 = and(T_1154, collect_iacq_data) + node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1157 = and(T_1155, T_1156) + node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) + node T_1159 = and(T_1157, T_1158) + node T_1161 = eq(T_1159, UInt<1>("h00")) + node T_1163 = eq(reset, UInt<1>("h00")) + when T_1163 : + node T_1165 = eq(T_1161, UInt<1>("h00")) + when T_1165 : + node T_1167 = eq(reset, UInt<1>("h00")) + when T_1167 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1246 = eq(state, UInt<1>("h00")) - node T_1247 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1248 = and(T_1246, T_1247) - node T_1250 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1253 : UInt<3>[1] - T_1253[0] <= UInt<3>("h03") - node T_1256 = eq(T_1253[0], io.inner.acquire.bits.a_type) - node T_1258 = or(UInt<1>("h00"), T_1256) - node T_1259 = and(T_1250, T_1258) - node T_1260 = and(T_1248, T_1259) - node T_1262 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1263 = and(T_1260, T_1262) - node T_1265 = eq(T_1263, UInt<1>("h00")) - node T_1267 = eq(reset, UInt<1>("h00")) - when T_1267 : - node T_1269 = eq(T_1265, UInt<1>("h00")) - when T_1269 : - node T_1271 = eq(reset, UInt<1>("h00")) - when T_1271 : + node T_1168 = eq(state, UInt<1>("h00")) + node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1170 = and(T_1168, T_1169) + node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_1175 : UInt<3>[1] + T_1175[0] <= UInt<3>("h03") + node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) + node T_1180 = or(UInt<1>("h00"), T_1178) + node T_1181 = and(T_1172, T_1180) + node T_1182 = and(T_1170, T_1181) + node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) + node T_1185 = and(T_1182, T_1184) + node T_1187 = eq(T_1185, UInt<1>("h00")) + node T_1189 = eq(reset, UInt<1>("h00")) + when T_1189 : + node T_1191 = eq(T_1187, UInt<1>("h00")) + when T_1191 : + node T_1193 = eq(reset, UInt<1>("h00")) + when T_1193 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") skip stop(clk, UInt<1>(1), 1) @@ -7403,38 +5985,40 @@ circuit Top : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1275 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1276 = bits(T_1275, 3, 3) - node T_1278 = dshl(UInt<1>("h01"), T_1276) - node T_1280 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1281 = and(io.inner.acquire.bits.is_builtin_type, T_1280) - node T_1282 = bit(T_1278, 0) - node T_1283 = bit(T_1278, 1) - wire T_1285 : UInt<1>[2] - T_1285[0] <= T_1282 - T_1285[1] <= T_1283 - node T_1290 = subw(UInt<8>("h00"), T_1285[0]) - node T_1292 = subw(UInt<8>("h00"), T_1285[1]) - wire T_1294 : UInt<8>[2] - T_1294[0] <= T_1290 - T_1294[1] <= T_1292 - node T_1298 = cat(T_1294[1], T_1294[0]) - node T_1300 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1301 = and(io.inner.acquire.bits.is_builtin_type, T_1300) - node T_1303 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1304 = and(io.inner.acquire.bits.is_builtin_type, T_1303) - node T_1305 = or(T_1301, T_1304) - node T_1306 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1308 = mux(T_1305, T_1306, UInt<16>("h00")) - node T_1309 = mux(T_1281, T_1298, T_1308) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1309 - node T_1312 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) - node T_1313 = or(iacq_data_valid, T_1312) - node T_1314 = not(iacq_data_valid) - node T_1315 = or(T_1314, T_1312) - node T_1316 = not(T_1315) - node T_1317 = mux(UInt<1>("h01"), T_1313, T_1316) - iacq_data_valid <= T_1317 + node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) + node T_1198 = bits(T_1197, 3, 3) + node T_1200 = dshl(UInt<1>("h01"), T_1198) + node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) + node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) + node T_1204 = bits(T_1200, 0, 0) + node T_1205 = bits(T_1200, 1, 1) + wire T_1207 : UInt<1>[2] + T_1207[0] <= T_1204 + T_1207[1] <= T_1205 + node T_1212 = sub(UInt<8>("h00"), T_1207[0]) + node T_1213 = tail(T_1212, 1) + node T_1215 = sub(UInt<8>("h00"), T_1207[1]) + node T_1216 = tail(T_1215, 1) + wire T_1218 : UInt<8>[2] + T_1218[0] <= T_1213 + T_1218[1] <= T_1216 + node T_1222 = cat(T_1218[1], T_1218[0]) + node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) + node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) + node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) + node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) + node T_1229 = or(T_1225, T_1228) + node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) + node T_1232 = mux(T_1229, T_1230, UInt<16>("h00")) + node T_1233 = mux(T_1203, T_1222, T_1232) + xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 + node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) + node T_1237 = or(iacq_data_valid, T_1236) + node T_1238 = not(iacq_data_valid) + node T_1239 = or(T_1238, T_1236) + node T_1240 = not(T_1239) + node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240) + iacq_data_valid <= T_1241 skip when iacq_data_done : collect_iacq_data <= UInt<1>("h00") @@ -7446,194 +6030,201 @@ circuit Top : pending_ognt_ack <= UInt<1>("h00") skip skip - node T_1321 = eq(UInt<1>("h00"), state) - when T_1321 : + node T_1245 = eq(UInt<1>("h00"), state) + when T_1245 : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact <- io.inner.acquire.bits xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data - node T_1327 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1328 = bits(T_1327, 3, 3) - node T_1330 = dshl(UInt<1>("h01"), T_1328) - node T_1332 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1333 = and(io.inner.acquire.bits.is_builtin_type, T_1332) - node T_1334 = bit(T_1330, 0) - node T_1335 = bit(T_1330, 1) - wire T_1337 : UInt<1>[2] - T_1337[0] <= T_1334 - T_1337[1] <= T_1335 - node T_1342 = subw(UInt<8>("h00"), T_1337[0]) - node T_1344 = subw(UInt<8>("h00"), T_1337[1]) - wire T_1346 : UInt<8>[2] - T_1346[0] <= T_1342 - T_1346[1] <= T_1344 - node T_1350 = cat(T_1346[1], T_1346[0]) - node T_1352 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1353 = and(io.inner.acquire.bits.is_builtin_type, T_1352) - node T_1355 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1356 = and(io.inner.acquire.bits.is_builtin_type, T_1355) - node T_1357 = or(T_1353, T_1356) - node T_1358 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1360 = mux(T_1357, T_1358, UInt<16>("h00")) - node T_1361 = mux(T_1333, T_1350, T_1360) - xact.wmask_buffer[UInt<1>("h00")] <= T_1361 - node T_1363 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1366 : UInt<3>[1] - T_1366[0] <= UInt<3>("h03") - node T_1369 = eq(T_1366[0], io.inner.acquire.bits.a_type) - node T_1371 = or(UInt<1>("h00"), T_1369) - node T_1372 = and(T_1363, T_1371) - collect_iacq_data <= T_1372 - wire T_1377 : UInt<3>[3] - T_1377[0] <= UInt<3>("h02") - T_1377[1] <= UInt<3>("h03") - T_1377[2] <= UInt<3>("h04") - node T_1382 = eq(T_1377[0], io.inner.acquire.bits.a_type) - node T_1383 = eq(T_1377[1], io.inner.acquire.bits.a_type) - node T_1384 = eq(T_1377[2], io.inner.acquire.bits.a_type) - node T_1386 = or(UInt<1>("h00"), T_1382) - node T_1387 = or(T_1386, T_1383) - node T_1388 = or(T_1387, T_1384) - node T_1389 = and(io.inner.acquire.bits.is_builtin_type, T_1388) - node T_1390 = dshl(T_1389, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1390 - node T_1392 = neq(mask_incoherent, UInt<1>("h00")) - when T_1392 : + node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) + node T_1252 = bits(T_1251, 3, 3) + node T_1254 = dshl(UInt<1>("h01"), T_1252) + node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) + node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) + node T_1258 = bits(T_1254, 0, 0) + node T_1259 = bits(T_1254, 1, 1) + wire T_1261 : UInt<1>[2] + T_1261[0] <= T_1258 + T_1261[1] <= T_1259 + node T_1266 = sub(UInt<8>("h00"), T_1261[0]) + node T_1267 = tail(T_1266, 1) + node T_1269 = sub(UInt<8>("h00"), T_1261[1]) + node T_1270 = tail(T_1269, 1) + wire T_1272 : UInt<8>[2] + T_1272[0] <= T_1267 + T_1272[1] <= T_1270 + node T_1276 = cat(T_1272[1], T_1272[0]) + node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) + node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) + node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) + node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) + node T_1283 = or(T_1279, T_1282) + node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) + node T_1286 = mux(T_1283, T_1284, UInt<16>("h00")) + node T_1287 = mux(T_1257, T_1276, T_1286) + xact.wmask_buffer[UInt<1>("h00")] <= T_1287 + node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_1292 : UInt<3>[1] + T_1292[0] <= UInt<3>("h03") + node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) + node T_1297 = or(UInt<1>("h00"), T_1295) + node T_1298 = and(T_1289, T_1297) + collect_iacq_data <= T_1298 + wire T_1303 : UInt<3>[3] + T_1303[0] <= UInt<3>("h02") + T_1303[1] <= UInt<3>("h03") + T_1303[2] <= UInt<3>("h04") + node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) + node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) + node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) + node T_1312 = or(UInt<1>("h00"), T_1308) + node T_1313 = or(T_1312, T_1309) + node T_1314 = or(T_1313, T_1310) + node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) + node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) + iacq_data_valid <= T_1316 + node T_1318 = neq(mask_incoherent, UInt<1>("h00")) + when T_1318 : pending_probes <= mask_incoherent - node T_1393 = bit(mask_incoherent, 0) - node T_1394 = bit(mask_incoherent, 1) - node T_1395 = bit(mask_incoherent, 2) - node T_1396 = bit(mask_incoherent, 3) - node T_1398 = cat(UInt<1>("h00"), T_1394) - node T_1399 = addw(T_1393, T_1398) - node T_1402 = cat(UInt<1>("h00"), T_1396) - node T_1403 = addw(T_1395, T_1402) - node T_1404 = cat(UInt<1>("h00"), T_1403) - node T_1405 = addw(T_1399, T_1404) - release_count <= T_1405 + node T_1319 = bits(mask_incoherent, 0, 0) + node T_1320 = bits(mask_incoherent, 1, 1) + node T_1321 = bits(mask_incoherent, 2, 2) + node T_1322 = bits(mask_incoherent, 3, 3) + node T_1324 = cat(UInt<1>("h00"), T_1320) + node T_1325 = add(T_1319, T_1324) + node T_1326 = tail(T_1325, 1) + node T_1329 = cat(UInt<1>("h00"), T_1322) + node T_1330 = add(T_1321, T_1329) + node T_1331 = tail(T_1330, 1) + node T_1332 = cat(UInt<1>("h00"), T_1331) + node T_1333 = add(T_1326, T_1332) + node T_1334 = tail(T_1333, 1) + release_count <= T_1334 skip - node T_1406 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_1407 = mux(pending_outer_write_, UInt<2>("h03"), T_1406) - node T_1408 = mux(T_1392, UInt<1>("h01"), T_1407) - state <= T_1408 + node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) + node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335) + node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336) + state <= T_1337 skip skip - node T_1409 = eq(UInt<1>("h01"), state) - when T_1409 : - node T_1411 = neq(pending_probes, UInt<1>("h00")) - io.inner.probe.valid <= T_1411 + node T_1338 = eq(UInt<1>("h01"), state) + when T_1338 : + node T_1340 = neq(pending_probes, UInt<1>("h00")) + io.inner.probe.valid <= T_1340 when io.inner.probe.ready : - node T_1413 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_1414 = not(T_1413) - node T_1415 = and(pending_probes, T_1414) - pending_probes <= T_1415 - skip - wire T_1417 : UInt<2>[3] - T_1417[0] <= UInt<1>("h00") - T_1417[1] <= UInt<1>("h01") - T_1417[2] <= UInt<2>("h02") - node T_1422 = eq(T_1417[0], io.inner.release.bits.r_type) - node T_1423 = eq(T_1417[1], io.inner.release.bits.r_type) - node T_1424 = eq(T_1417[2], io.inner.release.bits.r_type) - node T_1426 = or(UInt<1>("h00"), T_1422) - node T_1427 = or(T_1426, T_1423) - node T_1428 = or(T_1427, T_1424) - node T_1430 = eq(T_1428, UInt<1>("h00")) - node T_1431 = or(T_1430, io.outer.acquire.ready) - io.inner.release.ready <= T_1431 + node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00")) + node T_1343 = not(T_1342) + node T_1344 = and(pending_probes, T_1343) + pending_probes <= T_1344 + skip + wire T_1346 : UInt<2>[3] + T_1346[0] <= UInt<1>("h00") + T_1346[1] <= UInt<1>("h01") + T_1346[2] <= UInt<2>("h02") + node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) + node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) + node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) + node T_1355 = or(UInt<1>("h00"), T_1351) + node T_1356 = or(T_1355, T_1352) + node T_1357 = or(T_1356, T_1353) + node T_1359 = eq(T_1357, UInt<1>("h00")) + node T_1360 = or(T_1359, io.outer.acquire.ready) + io.inner.release.ready <= T_1360 when io.inner.release.valid : - wire T_1433 : UInt<2>[3] - T_1433[0] <= UInt<1>("h00") - T_1433[1] <= UInt<1>("h01") - T_1433[2] <= UInt<2>("h02") - node T_1438 = eq(T_1433[0], io.inner.release.bits.r_type) - node T_1439 = eq(T_1433[1], io.inner.release.bits.r_type) - node T_1440 = eq(T_1433[2], io.inner.release.bits.r_type) - node T_1442 = or(UInt<1>("h00"), T_1438) - node T_1443 = or(T_1442, T_1439) - node T_1444 = or(T_1443, T_1440) - when T_1444 : + wire T_1362 : UInt<2>[3] + T_1362[0] <= UInt<1>("h00") + T_1362[1] <= UInt<1>("h01") + T_1362[2] <= UInt<2>("h02") + node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) + node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) + node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) + node T_1371 = or(UInt<1>("h00"), T_1367) + node T_1372 = or(T_1371, T_1368) + node T_1373 = or(T_1372, T_1369) + when T_1373 : io.outer.acquire.valid <= UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") - node T_1448 = subw(release_count, UInt<1>("h01")) - release_count <= T_1448 - node T_1450 = eq(release_count, UInt<1>("h01")) - when T_1450 : - node T_1451 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1452 = mux(pending_outer_write, UInt<2>("h03"), T_1451) - state <= T_1452 + node T_1377 = sub(release_count, UInt<1>("h01")) + node T_1378 = tail(T_1377, 1) + release_count <= T_1378 + node T_1380 = eq(release_count, UInt<1>("h01")) + when T_1380 : + node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381) + state <= T_1382 skip skip skip skip - node T_1454 = eq(T_1444, UInt<1>("h00")) - when T_1454 : - node T_1456 = subw(release_count, UInt<1>("h01")) - release_count <= T_1456 - node T_1458 = eq(release_count, UInt<1>("h01")) - when T_1458 : - node T_1459 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1460 = mux(pending_outer_write, UInt<2>("h03"), T_1459) - state <= T_1460 + node T_1384 = eq(T_1373, UInt<1>("h00")) + when T_1384 : + node T_1386 = sub(release_count, UInt<1>("h01")) + node T_1387 = tail(T_1386, 1) + release_count <= T_1387 + node T_1389 = eq(release_count, UInt<1>("h01")) + when T_1389 : + node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390) + state <= T_1391 skip skip skip skip - node T_1461 = eq(UInt<2>("h03"), state) - when T_1461 : - node T_1463 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_1465 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1466 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1467 = bit(T_1466, 0) - node T_1468 = or(T_1465, T_1467) - node T_1469 = and(T_1463, T_1468) - io.outer.acquire.valid <= T_1469 + node T_1392 = eq(UInt<2>("h03"), state) + when T_1392 : + node T_1394 = eq(pending_ognt_ack, UInt<1>("h00")) + node T_1396 = eq(collect_iacq_data, UInt<1>("h00")) + node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) + node T_1398 = bits(T_1397, 0, 0) + node T_1399 = or(T_1396, T_1398) + node T_1400 = and(T_1394, T_1399) + io.outer.acquire.valid <= T_1400 when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") - node T_1471 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state <= T_1471 + node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) + state <= T_1402 skip skip - node T_1472 = eq(UInt<2>("h02"), state) - when T_1472 : - node T_1474 = eq(pending_ognt_ack, UInt<1>("h00")) - io.outer.acquire.valid <= T_1474 - node T_1475 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1475 : + node T_1403 = eq(UInt<2>("h02"), state) + when T_1403 : + node T_1405 = eq(pending_ognt_ack, UInt<1>("h00")) + io.outer.acquire.valid <= T_1405 + node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) + when T_1406 : state <= UInt<3>("h05") skip skip - node T_1476 = eq(UInt<3>("h05"), state) - when T_1476 : + node T_1407 = eq(UInt<3>("h05"), state) + when T_1407 : io.outer.grant.ready <= io.inner.grant.ready io.inner.grant.valid <= io.outer.grant.valid when ignt_data_done : - node T_1479 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1481 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1482 = and(io.inner.grant.bits.is_builtin_type, T_1481) - node T_1484 = eq(T_1482, UInt<1>("h00")) - node T_1485 = and(T_1479, T_1484) - node T_1486 = mux(T_1485, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1486 + node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) + node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) + node T_1415 = eq(T_1413, UInt<1>("h00")) + node T_1416 = and(T_1410, T_1415) + node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00")) + state <= T_1417 skip skip - node T_1487 = eq(UInt<3>("h04"), state) - when T_1487 : + node T_1418 = eq(UInt<3>("h04"), state) + when T_1418 : io.inner.grant.valid <= UInt<1>("h01") when io.inner.grant.ready : - node T_1491 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1493 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1494 = and(io.inner.grant.bits.is_builtin_type, T_1493) - node T_1496 = eq(T_1494, UInt<1>("h00")) - node T_1497 = and(T_1491, T_1496) - node T_1498 = mux(T_1497, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1498 + node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) + node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) + node T_1427 = eq(T_1425, UInt<1>("h00")) + node T_1428 = and(T_1422, T_1427) + node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00")) + state <= T_1429 skip skip - node T_1499 = eq(UInt<3>("h06"), state) - when T_1499 : + node T_1430 = eq(UInt<3>("h06"), state) + when T_1430 : io.inner.finish.ready <= UInt<1>("h01") when io.inner.finish.valid : state <= UInt<1>("h00") @@ -7645,98 +6236,73 @@ circuit Top : input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - io.has_release_match <= UInt<1>("h00") - io.has_acquire_match <= UInt<1>("h00") - io.has_acquire_conflict <= UInt<1>("h00") - io.outer.grant.ready <= UInt<1>("h00") - io.outer.acquire.bits.data <= UInt<1>("h00") - io.outer.acquire.bits.union <= UInt<1>("h00") - io.outer.acquire.bits.a_type <= UInt<1>("h00") - io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.outer.acquire.bits.addr_beat <= UInt<1>("h00") - io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") - io.outer.acquire.bits.addr_block <= UInt<1>("h00") - io.outer.acquire.valid <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.probe.bits.client_id <= UInt<1>("h00") - io.inner.probe.bits.p_type <= UInt<1>("h00") - io.inner.probe.bits.addr_block <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - io.inner.grant.bits.client_id <= UInt<1>("h00") - io.inner.grant.bits.data <= UInt<1>("h00") - io.inner.grant.bits.g_type <= UInt<1>("h00") - io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") - io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") - io.inner.grant.bits.client_xact_id <= UInt<1>("h00") - io.inner.grant.bits.addr_beat <= UInt<1>("h00") - io.inner.grant.valid <= UInt<1>("h00") - io.inner.acquire.ready <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk, UInt<1>("h00"), xact + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk wire coh : {sharers : UInt<1>} + coh is invalid coh.sharers <= UInt<1>("h00") - coh.sharers <= UInt<1>("h00") - node T_304 = neq(state, UInt<1>("h00")) - node T_305 = and(T_304, xact.is_builtin_type) - wire T_310 : UInt<3>[3] - T_310[0] <= UInt<3>("h04") - T_310[1] <= UInt<3>("h05") - T_310[2] <= UInt<3>("h06") - node T_315 = eq(T_310[0], xact.a_type) - node T_316 = eq(T_310[1], xact.a_type) - node T_317 = eq(T_310[2], xact.a_type) - node T_319 = or(UInt<1>("h00"), T_315) + node T_303 = neq(state, UInt<1>("h00")) + node T_304 = and(T_303, xact.is_builtin_type) + wire T_309 : UInt<3>[3] + T_309[0] <= UInt<3>("h04") + T_309[1] <= UInt<3>("h05") + T_309[2] <= UInt<3>("h06") + node T_314 = eq(T_309[0], xact.a_type) + node T_315 = eq(T_309[1], xact.a_type) + node T_316 = eq(T_309[2], xact.a_type) + node T_318 = or(UInt<1>("h00"), T_314) + node T_319 = or(T_318, T_315) node T_320 = or(T_319, T_316) - node T_321 = or(T_320, T_317) - node T_322 = and(T_305, T_321) - node T_324 = eq(T_322, UInt<1>("h00")) - node T_326 = eq(reset, UInt<1>("h00")) - when T_326 : - node T_328 = eq(T_324, UInt<1>("h00")) - when T_328 : - node T_330 = eq(reset, UInt<1>("h00")) - when T_330 : + node T_321 = and(T_304, T_320) + node T_323 = eq(T_321, UInt<1>("h00")) + node T_325 = eq(reset, UInt<1>("h00")) + when T_325 : + node T_327 = eq(T_323, UInt<1>("h00")) + when T_327 : + node T_329 = eq(reset, UInt<1>("h00")) + when T_329 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") skip stop(clk, UInt<1>(1), 1) skip skip - reg release_count : UInt<1>, clk, reset, UInt<1>("h00") - reg pending_probes : UInt<1>, clk, reset, UInt<1>("h00") - node T_335 = bit(pending_probes, 0) - wire T_337 : UInt<1>[1] - T_337[0] <= T_335 - node T_342 = asUInt(asSInt(UInt<1>("h01"))) - node T_345 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) - node T_346 = or(T_342, T_345) - node T_347 = not(T_342) - node T_348 = or(T_347, T_345) - node T_349 = not(T_348) - node mask_self = mux(UInt<1>("h00"), T_346, T_349) - node T_351 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_351) - reg collect_iacq_data : UInt<1>, clk, reset, UInt<1>("h00") - reg iacq_data_valid : UInt<4>, clk, reset, UInt<4>("h00") - node T_357 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_360 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_363 : UInt<3>[1] - T_363[0] <= UInt<3>("h03") - node T_366 = eq(T_363[0], io.inner.acquire.bits.a_type) - node T_368 = or(UInt<1>("h00"), T_366) - node T_369 = and(T_360, T_368) - node T_370 = and(T_357, T_369) - reg T_372 : UInt<2>, clk, reset, UInt<2>("h00") - when T_370 : - node T_374 = eq(T_372, UInt<2>("h03")) - node T_376 = and(UInt<1>("h00"), T_374) - node T_379 = addw(T_372, UInt<1>("h01")) - node T_380 = mux(T_376, UInt<1>("h00"), T_379) - T_372 <= T_380 - skip - node T_381 = and(T_370, T_374) - node T_382 = mux(T_369, T_372, UInt<1>("h00")) - node iacq_data_done = mux(T_369, T_381, T_357) + reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_334 = bits(pending_probes, 0, 0) + wire T_336 : UInt<1>[1] + T_336[0] <= T_334 + node T_341 = asUInt(asSInt(UInt<1>("h01"))) + node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) + node T_345 = or(T_341, T_344) + node T_346 = not(T_341) + node T_347 = or(T_346, T_344) + node T_348 = not(T_347) + node mask_self = mux(UInt<1>("h00"), T_345, T_348) + node T_350 = not(io.incoherent[0]) + node mask_incoherent = and(mask_self, T_350) + reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) + node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_362 : UInt<3>[1] + T_362[0] <= UInt<3>("h03") + node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) + node T_367 = or(UInt<1>("h00"), T_365) + node T_368 = and(T_359, T_367) + node T_369 = and(T_356, T_368) + reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_369 : + node T_373 = eq(T_371, UInt<2>("h03")) + node T_375 = and(UInt<1>("h00"), T_373) + node T_378 = add(T_371, UInt<1>("h01")) + node T_379 = tail(T_378, 1) + node T_380 = mux(T_375, UInt<1>("h00"), T_379) + T_371 <= T_380 + skip + node T_381 = and(T_369, T_373) + node T_382 = mux(T_368, T_371, UInt<1>("h00")) + node iacq_data_done = mux(T_368, T_381, T_356) node T_384 = and(io.inner.release.ready, io.inner.release.valid) wire T_388 : UInt<2>[3] T_388[0] <= UInt<1>("h00") @@ -7750,577 +6316,523 @@ circuit Top : node T_399 = or(T_398, T_395) node T_400 = and(UInt<1>("h01"), T_399) node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk, reset, UInt<2>("h00") + reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) when T_401 : node T_405 = eq(T_403, UInt<2>("h03")) node T_407 = and(UInt<1>("h00"), T_405) - node T_410 = addw(T_403, UInt<1>("h01")) - node T_411 = mux(T_407, UInt<1>("h00"), T_410) - T_403 <= T_411 - skip - node T_412 = and(T_401, T_405) - node T_413 = mux(T_400, T_403, UInt<1>("h00")) - node irel_data_done = mux(T_400, T_412, T_384) - node T_416 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_420 : UInt<3>[1] - T_420[0] <= UInt<3>("h05") - node T_423 = eq(T_420[0], io.inner.grant.bits.g_type) - node T_425 = or(UInt<1>("h00"), T_423) - wire T_427 : UInt<1>[2] - T_427[0] <= UInt<1>("h00") - T_427[1] <= UInt<1>("h01") - node T_431 = eq(T_427[0], io.inner.grant.bits.g_type) - node T_432 = eq(T_427[1], io.inner.grant.bits.g_type) - node T_434 = or(UInt<1>("h00"), T_431) - node T_435 = or(T_434, T_432) - node T_436 = mux(io.inner.grant.bits.is_builtin_type, T_425, T_435) - node T_437 = and(UInt<1>("h01"), T_436) - node T_438 = and(T_416, T_437) - reg T_440 : UInt<2>, clk, reset, UInt<2>("h00") - when T_438 : - node T_442 = eq(T_440, UInt<2>("h03")) - node T_444 = and(UInt<1>("h00"), T_442) - node T_447 = addw(T_440, UInt<1>("h01")) - node T_448 = mux(T_444, UInt<1>("h00"), T_447) - T_440 <= T_448 - skip - node T_449 = and(T_438, T_442) - node ignt_data_cnt = mux(T_437, T_440, UInt<1>("h00")) - node ignt_data_done = mux(T_437, T_449, T_416) - node T_453 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_455 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) - wire T_458 : UInt<3>[1] - T_458[0] <= UInt<3>("h03") - node T_461 = eq(T_458[0], io.outer.acquire.bits.a_type) - node T_463 = or(UInt<1>("h00"), T_461) - node T_464 = and(T_455, T_463) - node T_465 = and(T_453, T_464) - reg T_467 : UInt<2>, clk, reset, UInt<2>("h00") - when T_465 : - node T_469 = eq(T_467, UInt<2>("h03")) - node T_471 = and(UInt<1>("h00"), T_469) - node T_474 = addw(T_467, UInt<1>("h01")) - node T_475 = mux(T_471, UInt<1>("h00"), T_474) - T_467 <= T_475 - skip - node T_476 = and(T_465, T_469) - node oacq_data_cnt = mux(T_464, T_467, UInt<1>("h00")) - node oacq_data_done = mux(T_464, T_476, T_453) - node T_479 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_484 : UInt<3>[1] - T_484[0] <= UInt<3>("h05") - node T_487 = eq(T_484[0], io.outer.grant.bits.g_type) - node T_489 = or(UInt<1>("h00"), T_487) - wire T_491 : UInt<1>[1] - T_491[0] <= UInt<1>("h00") - node T_494 = eq(T_491[0], io.outer.grant.bits.g_type) - node T_496 = or(UInt<1>("h00"), T_494) - node T_497 = mux(io.outer.grant.bits.is_builtin_type, T_489, T_496) - node T_498 = and(UInt<1>("h01"), T_497) - node T_499 = and(T_479, T_498) - reg T_501 : UInt<2>, clk, reset, UInt<2>("h00") - when T_499 : - node T_503 = eq(T_501, UInt<2>("h03")) - node T_505 = and(UInt<1>("h00"), T_503) - node T_508 = addw(T_501, UInt<1>("h01")) - node T_509 = mux(T_505, UInt<1>("h00"), T_508) - T_501 <= T_509 - skip - node T_510 = and(T_499, T_503) - node T_511 = mux(T_498, T_501, UInt<1>("h00")) - node ognt_data_done = mux(T_498, T_510, T_479) - reg pending_ognt_ack : UInt<1>, clk, reset, UInt<1>("h00") - wire T_519 : UInt<3>[3] - T_519[0] <= UInt<3>("h02") - T_519[1] <= UInt<3>("h03") - T_519[2] <= UInt<3>("h04") - node T_524 = eq(T_519[0], xact.a_type) - node T_525 = eq(T_519[1], xact.a_type) - node T_526 = eq(T_519[2], xact.a_type) - node T_528 = or(UInt<1>("h00"), T_524) - node T_529 = or(T_528, T_525) - node T_530 = or(T_529, T_526) - node pending_outer_write = and(xact.is_builtin_type, T_530) - wire T_536 : UInt<3>[3] - T_536[0] <= UInt<3>("h02") - T_536[1] <= UInt<3>("h03") - T_536[2] <= UInt<3>("h04") - node T_541 = eq(T_536[0], io.inner.acquire.bits.a_type) - node T_542 = eq(T_536[1], io.inner.acquire.bits.a_type) - node T_543 = eq(T_536[2], io.inner.acquire.bits.a_type) - node T_545 = or(UInt<1>("h00"), T_541) - node T_546 = or(T_545, T_542) - node T_547 = or(T_546, T_543) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_547) - wire T_552 : UInt<3>[2] - T_552[0] <= UInt<3>("h05") - T_552[1] <= UInt<3>("h04") - node T_556 = eq(T_552[0], io.inner.grant.bits.g_type) - node T_557 = eq(T_552[1], io.inner.grant.bits.g_type) - node T_559 = or(UInt<1>("h00"), T_556) - node T_560 = or(T_559, T_557) - wire T_562 : UInt<1>[2] - T_562[0] <= UInt<1>("h00") - T_562[1] <= UInt<1>("h01") - node T_566 = eq(T_562[0], io.inner.grant.bits.g_type) - node T_567 = eq(T_562[1], io.inner.grant.bits.g_type) - node T_569 = or(UInt<1>("h00"), T_566) - node T_570 = or(T_569, T_567) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_560, T_570) - node T_590 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) - node T_591 = mux(T_590, UInt<3>("h01"), UInt<3>("h03")) - node T_592 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) - node T_593 = mux(T_592, UInt<3>("h01"), T_591) - node T_594 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h04"), T_593) - node T_596 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h03"), T_595) - node T_598 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h03"), T_597) - node T_600 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h05"), T_599) - node T_602 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h04"), T_601) - node T_604 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) - node T_607 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_608 = mux(T_607, UInt<1>("h00"), UInt<1>("h01")) - node T_609 = mux(T_604, T_608, UInt<1>("h01")) - node T_610 = mux(io.inner.acquire.bits.is_builtin_type, T_603, T_609) - wire T_619 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_619.client_id <= UInt<1>("h00") - T_619.data <= UInt<1>("h00") - T_619.g_type <= UInt<1>("h00") - T_619.is_builtin_type <= UInt<1>("h00") - T_619.manager_xact_id <= UInt<1>("h00") - T_619.client_xact_id <= UInt<1>("h00") - T_619.addr_beat <= UInt<1>("h00") - T_619.client_id <= io.inner.acquire.bits.client_id - T_619.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_619.g_type <= T_610 - T_619.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_619.manager_xact_id <= UInt<3>("h06") - T_619.addr_beat <= UInt<1>("h00") - T_619.data <= UInt<1>("h00") - wire T_637 : UInt<3>[2] - T_637[0] <= UInt<3>("h05") - T_637[1] <= UInt<3>("h04") - node T_641 = eq(T_637[0], T_619.g_type) - node T_642 = eq(T_637[1], T_619.g_type) - node T_644 = or(UInt<1>("h00"), T_641) - node T_645 = or(T_644, T_642) - wire T_647 : UInt<1>[2] - T_647[0] <= UInt<1>("h00") - T_647[1] <= UInt<1>("h01") - node T_651 = eq(T_647[0], T_619.g_type) - node T_652 = eq(T_647[1], T_619.g_type) - node T_654 = or(UInt<1>("h00"), T_651) - node T_655 = or(T_654, T_652) - node pending_outer_read_ = mux(T_619.is_builtin_type, T_645, T_655) - wire T_661 : UInt<3>[3] - T_661[0] <= UInt<3>("h02") - T_661[1] <= UInt<3>("h00") - T_661[2] <= UInt<3>("h04") - node T_666 = eq(T_661[0], xact.a_type) - node T_667 = eq(T_661[1], xact.a_type) - node T_668 = eq(T_661[2], xact.a_type) - node T_670 = or(UInt<1>("h00"), T_666) - node T_671 = or(T_670, T_667) - node T_672 = or(T_671, T_668) - node subblock_type = and(xact.is_builtin_type, T_672) - node T_674 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_675 = neq(state, UInt<1>("h00")) - node T_676 = and(T_674, T_675) - node T_678 = eq(collect_iacq_data, UInt<1>("h00")) - node T_679 = and(T_676, T_678) - io.has_acquire_conflict <= T_679 - node T_680 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_681 = and(T_680, collect_iacq_data) - io.has_acquire_match <= T_681 - node T_682 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_684 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) - node T_685 = and(T_682, T_684) - node T_686 = eq(state, UInt<1>("h01")) - node T_687 = and(T_685, T_686) - io.has_release_match <= T_687 - node T_692 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_698 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_410 = add(T_403, UInt<1>("h01")) + node T_411 = tail(T_410, 1) + node T_412 = mux(T_407, UInt<1>("h00"), T_411) + T_403 <= T_412 + skip + node T_413 = and(T_401, T_405) + node T_414 = mux(T_400, T_403, UInt<1>("h00")) + node irel_data_done = mux(T_400, T_413, T_384) + node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) + wire T_421 : UInt<3>[1] + T_421[0] <= UInt<3>("h05") + node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) + node T_426 = or(UInt<1>("h00"), T_424) + wire T_428 : UInt<1>[2] + T_428[0] <= UInt<1>("h00") + T_428[1] <= UInt<1>("h01") + node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) + node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) + node T_435 = or(UInt<1>("h00"), T_432) + node T_436 = or(T_435, T_433) + node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) + node T_438 = and(UInt<1>("h01"), T_437) + node T_439 = and(T_417, T_438) + reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_439 : + node T_443 = eq(T_441, UInt<2>("h03")) + node T_445 = and(UInt<1>("h00"), T_443) + node T_448 = add(T_441, UInt<1>("h01")) + node T_449 = tail(T_448, 1) + node T_450 = mux(T_445, UInt<1>("h00"), T_449) + T_441 <= T_450 + skip + node T_451 = and(T_439, T_443) + node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00")) + node ignt_data_done = mux(T_438, T_451, T_417) + node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) + wire T_460 : UInt<3>[1] + T_460[0] <= UInt<3>("h03") + node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) + node T_465 = or(UInt<1>("h00"), T_463) + node T_466 = and(T_457, T_465) + node T_467 = and(T_455, T_466) + reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_467 : + node T_471 = eq(T_469, UInt<2>("h03")) + node T_473 = and(UInt<1>("h00"), T_471) + node T_476 = add(T_469, UInt<1>("h01")) + node T_477 = tail(T_476, 1) + node T_478 = mux(T_473, UInt<1>("h00"), T_477) + T_469 <= T_478 + skip + node T_479 = and(T_467, T_471) + node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00")) + node oacq_data_done = mux(T_466, T_479, T_455) + node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_487 : UInt<3>[1] + T_487[0] <= UInt<3>("h05") + node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) + node T_492 = or(UInt<1>("h00"), T_490) + wire T_494 : UInt<1>[1] + T_494[0] <= UInt<1>("h00") + node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) + node T_499 = or(UInt<1>("h00"), T_497) + node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) + node T_501 = and(UInt<1>("h01"), T_500) + node T_502 = and(T_482, T_501) + reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_502 : + node T_506 = eq(T_504, UInt<2>("h03")) + node T_508 = and(UInt<1>("h00"), T_506) + node T_511 = add(T_504, UInt<1>("h01")) + node T_512 = tail(T_511, 1) + node T_513 = mux(T_508, UInt<1>("h00"), T_512) + T_504 <= T_513 + skip + node T_514 = and(T_502, T_506) + node T_515 = mux(T_501, T_504, UInt<1>("h00")) + node ognt_data_done = mux(T_501, T_514, T_482) + reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + wire T_523 : UInt<3>[3] + T_523[0] <= UInt<3>("h02") + T_523[1] <= UInt<3>("h03") + T_523[2] <= UInt<3>("h04") + node T_528 = eq(T_523[0], xact.a_type) + node T_529 = eq(T_523[1], xact.a_type) + node T_530 = eq(T_523[2], xact.a_type) + node T_532 = or(UInt<1>("h00"), T_528) + node T_533 = or(T_532, T_529) + node T_534 = or(T_533, T_530) + node pending_outer_write = and(xact.is_builtin_type, T_534) + wire T_540 : UInt<3>[3] + T_540[0] <= UInt<3>("h02") + T_540[1] <= UInt<3>("h03") + T_540[2] <= UInt<3>("h04") + node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) + node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) + node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) + node T_549 = or(UInt<1>("h00"), T_545) + node T_550 = or(T_549, T_546) + node T_551 = or(T_550, T_547) + node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) + wire T_556 : UInt<3>[2] + T_556[0] <= UInt<3>("h05") + T_556[1] <= UInt<3>("h04") + node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) + node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) + node T_563 = or(UInt<1>("h00"), T_560) + node T_564 = or(T_563, T_561) + wire T_566 : UInt<1>[2] + T_566[0] <= UInt<1>("h00") + T_566[1] <= UInt<1>("h01") + node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) + node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) + node T_573 = or(UInt<1>("h00"), T_570) + node T_574 = or(T_573, T_571) + node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) + node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) + node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03")) + node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) + node T_597 = mux(T_596, UInt<3>("h01"), T_595) + node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) + node T_599 = mux(T_598, UInt<3>("h04"), T_597) + node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) + node T_601 = mux(T_600, UInt<3>("h03"), T_599) + node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) + node T_603 = mux(T_602, UInt<3>("h03"), T_601) + node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) + node T_605 = mux(T_604, UInt<3>("h05"), T_603) + node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) + node T_607 = mux(T_606, UInt<3>("h04"), T_605) + node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) + node T_611 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01")) + node T_613 = mux(T_608, T_612, UInt<1>("h01")) + node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) + wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} + T_623 is invalid + T_623.client_id <= io.inner.acquire.bits.client_id + T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type + T_623.g_type <= T_614 + T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id + T_623.manager_xact_id <= UInt<3>("h06") + T_623.addr_beat <= UInt<1>("h00") + T_623.data <= UInt<1>("h00") + wire T_634 : UInt<3>[2] + T_634[0] <= UInt<3>("h05") + T_634[1] <= UInt<3>("h04") + node T_638 = eq(T_634[0], T_623.g_type) + node T_639 = eq(T_634[1], T_623.g_type) + node T_641 = or(UInt<1>("h00"), T_638) + node T_642 = or(T_641, T_639) + wire T_644 : UInt<1>[2] + T_644[0] <= UInt<1>("h00") + T_644[1] <= UInt<1>("h01") + node T_648 = eq(T_644[0], T_623.g_type) + node T_649 = eq(T_644[1], T_623.g_type) + node T_651 = or(UInt<1>("h00"), T_648) + node T_652 = or(T_651, T_649) + node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) + wire T_658 : UInt<3>[3] + T_658[0] <= UInt<3>("h02") + T_658[1] <= UInt<3>("h00") + T_658[2] <= UInt<3>("h04") + node T_663 = eq(T_658[0], xact.a_type) + node T_664 = eq(T_658[1], xact.a_type) + node T_665 = eq(T_658[2], xact.a_type) + node T_667 = or(UInt<1>("h00"), T_663) + node T_668 = or(T_667, T_664) + node T_669 = or(T_668, T_665) + node subblock_type = and(xact.is_builtin_type, T_669) + node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) + node T_672 = neq(state, UInt<1>("h00")) + node T_673 = and(T_671, T_672) + node T_675 = eq(collect_iacq_data, UInt<1>("h00")) + node T_676 = and(T_673, T_675) + io.has_acquire_conflict <= T_676 + node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) + node T_678 = and(T_677, collect_iacq_data) + io.has_acquire_match <= T_678 + node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) + node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) + node T_682 = and(T_679, T_681) + node T_683 = eq(state, UInt<1>("h01")) + node T_684 = and(T_682, T_683) + io.has_release_match <= T_684 + node T_689 = asUInt(asSInt(UInt<16>("h0ffff"))) + node T_695 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_696 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_697 = cat(T_695, T_696) node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_700 = cat(T_698, T_699) - node T_702 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_703 = cat(UInt<3>("h07"), T_702) - node T_705 = cat(T_692, UInt<1>("h01")) - node T_707 = cat(T_692, UInt<1>("h01")) - node T_709 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_710 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_711 = cat(T_709, T_710) - node T_713 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_715 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_716 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_717 = mux(T_716, T_715, UInt<1>("h00")) - node T_718 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_719 = mux(T_718, T_713, T_717) - node T_720 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_721 = mux(T_720, T_711, T_719) - node T_722 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_723 = mux(T_722, T_707, T_721) - node T_724 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_725 = mux(T_724, T_705, T_723) - node T_726 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_727 = mux(T_726, T_703, T_725) - node T_728 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_729 = mux(T_728, T_700, T_727) + node T_700 = cat(UInt<3>("h07"), T_699) + node T_702 = cat(T_689, UInt<1>("h01")) + node T_704 = cat(T_689, UInt<1>("h01")) + node T_706 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_707 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_708 = cat(T_706, T_707) + node T_710 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_712 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_713 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_714 = mux(T_713, T_712, UInt<1>("h00")) + node T_715 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_716 = mux(T_715, T_710, T_714) + node T_717 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_718 = mux(T_717, T_708, T_716) + node T_719 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_720 = mux(T_719, T_704, T_718) + node T_721 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_722 = mux(T_721, T_702, T_720) + node T_723 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_724 = mux(T_723, T_700, T_722) + node T_725 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_726 = mux(T_725, T_697, T_724) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe.data <= UInt<1>("h00") - oacq_probe.union <= UInt<1>("h00") - oacq_probe.a_type <= UInt<1>("h00") - oacq_probe.is_builtin_type <= UInt<1>("h00") - oacq_probe.addr_beat <= UInt<1>("h00") - oacq_probe.client_xact_id <= UInt<1>("h00") - oacq_probe.addr_block <= UInt<1>("h00") + oacq_probe is invalid oacq_probe.is_builtin_type <= UInt<1>("h01") oacq_probe.a_type <= UInt<3>("h03") oacq_probe.client_xact_id <= UInt<3>("h06") oacq_probe.addr_block <= io.inner.release.bits.addr_block oacq_probe.addr_beat <= io.inner.release.bits.addr_beat oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_729 - node T_754 = bits(xact.union, 12, 9) - node T_755 = bits(T_754, 3, 3) - node T_757 = dshl(UInt<1>("h01"), T_755) - node T_759 = eq(xact.a_type, UInt<3>("h04")) - node T_760 = and(xact.is_builtin_type, T_759) - node T_761 = bit(T_757, 0) - node T_762 = bit(T_757, 1) - wire T_764 : UInt<1>[2] - T_764[0] <= T_761 - T_764[1] <= T_762 - node T_769 = subw(UInt<8>("h00"), T_764[0]) - node T_771 = subw(UInt<8>("h00"), T_764[1]) - wire T_773 : UInt<8>[2] - T_773[0] <= T_769 - T_773[1] <= T_771 - node T_777 = cat(T_773[1], T_773[0]) - node T_779 = eq(xact.a_type, UInt<3>("h03")) - node T_780 = and(xact.is_builtin_type, T_779) - node T_782 = eq(xact.a_type, UInt<3>("h02")) - node T_783 = and(xact.is_builtin_type, T_782) - node T_784 = or(T_780, T_783) - node T_785 = bits(xact.union, 16, 1) - node T_787 = mux(T_784, T_785, UInt<16>("h00")) - node T_788 = mux(T_760, T_777, T_787) - node T_796 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_797 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_798 = cat(T_796, T_797) + oacq_probe.union <= T_726 + node T_744 = bits(xact.union, 12, 9) + node T_745 = bits(T_744, 3, 3) + node T_747 = dshl(UInt<1>("h01"), T_745) + node T_749 = eq(xact.a_type, UInt<3>("h04")) + node T_750 = and(xact.is_builtin_type, T_749) + node T_751 = bits(T_747, 0, 0) + node T_752 = bits(T_747, 1, 1) + wire T_754 : UInt<1>[2] + T_754[0] <= T_751 + T_754[1] <= T_752 + node T_759 = sub(UInt<8>("h00"), T_754[0]) + node T_760 = tail(T_759, 1) + node T_762 = sub(UInt<8>("h00"), T_754[1]) + node T_763 = tail(T_762, 1) + wire T_765 : UInt<8>[2] + T_765[0] <= T_760 + T_765[1] <= T_763 + node T_769 = cat(T_765[1], T_765[0]) + node T_771 = eq(xact.a_type, UInt<3>("h03")) + node T_772 = and(xact.is_builtin_type, T_771) + node T_774 = eq(xact.a_type, UInt<3>("h02")) + node T_775 = and(xact.is_builtin_type, T_774) + node T_776 = or(T_772, T_775) + node T_777 = bits(xact.union, 16, 1) + node T_779 = mux(T_776, T_777, UInt<16>("h00")) + node T_780 = mux(T_750, T_769, T_779) + node T_788 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_789 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_790 = cat(T_788, T_789) + node T_792 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_793 = cat(UInt<3>("h07"), T_792) + node T_795 = cat(T_780, UInt<1>("h01")) + node T_797 = cat(T_780, UInt<1>("h01")) + node T_799 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_801 = cat(UInt<3>("h07"), T_800) - node T_803 = cat(T_788, UInt<1>("h01")) - node T_805 = cat(T_788, UInt<1>("h01")) - node T_807 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_808 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_809 = cat(T_807, T_808) - node T_811 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_813 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_814 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_815 = mux(T_814, T_813, UInt<1>("h00")) - node T_816 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_817 = mux(T_816, T_811, T_815) - node T_818 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_819 = mux(T_818, T_809, T_817) - node T_820 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_821 = mux(T_820, T_805, T_819) - node T_822 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_823 = mux(T_822, T_803, T_821) - node T_824 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_825 = mux(T_824, T_801, T_823) - node T_826 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_827 = mux(T_826, T_798, T_825) + node T_801 = cat(T_799, T_800) + node T_803 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_805 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_806 = eq(UInt<3>("h06"), UInt<3>("h02")) + node T_807 = mux(T_806, T_805, UInt<1>("h00")) + node T_808 = eq(UInt<3>("h05"), UInt<3>("h02")) + node T_809 = mux(T_808, T_803, T_807) + node T_810 = eq(UInt<3>("h04"), UInt<3>("h02")) + node T_811 = mux(T_810, T_801, T_809) + node T_812 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_813 = mux(T_812, T_797, T_811) + node T_814 = eq(UInt<3>("h02"), UInt<3>("h02")) + node T_815 = mux(T_814, T_795, T_813) + node T_816 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_817 = mux(T_816, T_793, T_815) + node T_818 = eq(UInt<3>("h00"), UInt<3>("h02")) + node T_819 = mux(T_818, T_790, T_817) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat.data <= UInt<1>("h00") - oacq_write_beat.union <= UInt<1>("h00") - oacq_write_beat.a_type <= UInt<1>("h00") - oacq_write_beat.is_builtin_type <= UInt<1>("h00") - oacq_write_beat.addr_beat <= UInt<1>("h00") - oacq_write_beat.client_xact_id <= UInt<1>("h00") - oacq_write_beat.addr_block <= UInt<1>("h00") + oacq_write_beat is invalid oacq_write_beat.is_builtin_type <= UInt<1>("h01") oacq_write_beat.a_type <= UInt<3>("h02") oacq_write_beat.client_xact_id <= UInt<3>("h06") oacq_write_beat.addr_block <= xact.addr_block oacq_write_beat.addr_beat <= xact.addr_beat oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_827 - node T_861 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_862 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_863 = cat(T_861, T_862) - node T_865 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_866 = cat(UInt<3>("h07"), T_865) - node T_868 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_870 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_872 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_873 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_874 = cat(T_872, T_873) - node T_876 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_878 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_879 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_880 = mux(T_879, T_878, UInt<1>("h00")) - node T_881 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_882 = mux(T_881, T_876, T_880) - node T_883 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_884 = mux(T_883, T_874, T_882) - node T_885 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_886 = mux(T_885, T_870, T_884) - node T_887 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_888 = mux(T_887, T_868, T_886) - node T_889 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_890 = mux(T_889, T_866, T_888) - node T_891 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_892 = mux(T_891, T_863, T_890) + oacq_write_beat.union <= T_819 + node T_846 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_847 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_848 = cat(T_846, T_847) + node T_850 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_851 = cat(UInt<3>("h07"), T_850) + node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) + node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) + node T_857 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_858 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_859 = cat(T_857, T_858) + node T_861 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_863 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_864 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_865 = mux(T_864, T_863, UInt<1>("h00")) + node T_866 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_867 = mux(T_866, T_861, T_865) + node T_868 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_869 = mux(T_868, T_859, T_867) + node T_870 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_871 = mux(T_870, T_855, T_869) + node T_872 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_873 = mux(T_872, T_853, T_871) + node T_874 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_875 = mux(T_874, T_851, T_873) + node T_876 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_877 = mux(T_876, T_848, T_875) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block.data <= UInt<1>("h00") - oacq_write_block.union <= UInt<1>("h00") - oacq_write_block.a_type <= UInt<1>("h00") - oacq_write_block.is_builtin_type <= UInt<1>("h00") - oacq_write_block.addr_beat <= UInt<1>("h00") - oacq_write_block.client_xact_id <= UInt<1>("h00") - oacq_write_block.addr_block <= UInt<1>("h00") + oacq_write_block is invalid oacq_write_block.is_builtin_type <= UInt<1>("h01") oacq_write_block.a_type <= UInt<3>("h03") oacq_write_block.client_xact_id <= UInt<3>("h06") oacq_write_block.addr_block <= xact.addr_block oacq_write_block.addr_beat <= oacq_data_cnt oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_892 - node T_917 = bits(xact.union, 12, 9) - node T_918 = bits(xact.union, 8, 6) - node T_926 = cat(T_917, T_918) - node T_927 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_928 = cat(T_926, T_927) - node T_930 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_931 = cat(T_918, T_930) - node T_933 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_935 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_937 = cat(T_917, T_918) - node T_938 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_939 = cat(T_937, T_938) - node T_941 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_943 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_944 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_945 = mux(T_944, T_943, UInt<1>("h00")) - node T_946 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_947 = mux(T_946, T_941, T_945) - node T_948 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_949 = mux(T_948, T_939, T_947) - node T_950 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_951 = mux(T_950, T_935, T_949) - node T_952 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_953 = mux(T_952, T_933, T_951) - node T_954 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_955 = mux(T_954, T_931, T_953) - node T_956 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_957 = mux(T_956, T_928, T_955) + oacq_write_block.union <= T_877 + node T_895 = bits(xact.union, 12, 9) + node T_896 = bits(xact.union, 8, 6) + node T_904 = cat(T_895, T_896) + node T_905 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_906 = cat(T_904, T_905) + node T_908 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_909 = cat(T_896, T_908) + node T_911 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_913 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_915 = cat(T_895, T_896) + node T_916 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_917 = cat(T_915, T_916) + node T_919 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_921 = cat(UInt<5>("h01"), UInt<1>("h00")) + node T_922 = eq(UInt<3>("h06"), UInt<3>("h00")) + node T_923 = mux(T_922, T_921, UInt<1>("h00")) + node T_924 = eq(UInt<3>("h05"), UInt<3>("h00")) + node T_925 = mux(T_924, T_919, T_923) + node T_926 = eq(UInt<3>("h04"), UInt<3>("h00")) + node T_927 = mux(T_926, T_917, T_925) + node T_928 = eq(UInt<3>("h03"), UInt<3>("h00")) + node T_929 = mux(T_928, T_913, T_927) + node T_930 = eq(UInt<3>("h02"), UInt<3>("h00")) + node T_931 = mux(T_930, T_911, T_929) + node T_932 = eq(UInt<3>("h01"), UInt<3>("h00")) + node T_933 = mux(T_932, T_909, T_931) + node T_934 = eq(UInt<3>("h00"), UInt<3>("h00")) + node T_935 = mux(T_934, T_906, T_933) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= UInt<1>("h00") - oacq_read_beat.a_type <= UInt<1>("h00") - oacq_read_beat.is_builtin_type <= UInt<1>("h00") - oacq_read_beat.addr_beat <= UInt<1>("h00") - oacq_read_beat.client_xact_id <= UInt<1>("h00") - oacq_read_beat.addr_block <= UInt<1>("h00") + oacq_read_beat is invalid oacq_read_beat.is_builtin_type <= UInt<1>("h01") oacq_read_beat.a_type <= UInt<3>("h00") oacq_read_beat.client_xact_id <= UInt<3>("h06") oacq_read_beat.addr_block <= xact.addr_block oacq_read_beat.addr_beat <= xact.addr_beat oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= T_957 - node T_991 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_992 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_993 = cat(T_991, T_992) - node T_995 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_996 = cat(UInt<3>("h07"), T_995) - node T_998 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1000 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1002 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1003 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1004 = cat(T_1002, T_1003) - node T_1006 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1008 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1009 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_1010 = mux(T_1009, T_1008, UInt<1>("h00")) - node T_1011 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_1012 = mux(T_1011, T_1006, T_1010) - node T_1013 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_1014 = mux(T_1013, T_1004, T_1012) - node T_1015 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_1016 = mux(T_1015, T_1000, T_1014) - node T_1017 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_1018 = mux(T_1017, T_998, T_1016) - node T_1019 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_1020 = mux(T_1019, T_996, T_1018) - node T_1021 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_1022 = mux(T_1021, T_993, T_1020) + oacq_read_beat.union <= T_935 + node T_962 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_963 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_964 = cat(T_962, T_963) + node T_966 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_967 = cat(UInt<3>("h07"), T_966) + node T_969 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_971 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_973 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_974 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_975 = cat(T_973, T_974) + node T_977 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_979 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_980 = eq(UInt<3>("h06"), UInt<3>("h01")) + node T_981 = mux(T_980, T_979, UInt<1>("h00")) + node T_982 = eq(UInt<3>("h05"), UInt<3>("h01")) + node T_983 = mux(T_982, T_977, T_981) + node T_984 = eq(UInt<3>("h04"), UInt<3>("h01")) + node T_985 = mux(T_984, T_975, T_983) + node T_986 = eq(UInt<3>("h03"), UInt<3>("h01")) + node T_987 = mux(T_986, T_971, T_985) + node T_988 = eq(UInt<3>("h02"), UInt<3>("h01")) + node T_989 = mux(T_988, T_969, T_987) + node T_990 = eq(UInt<3>("h01"), UInt<3>("h01")) + node T_991 = mux(T_990, T_967, T_989) + node T_992 = eq(UInt<3>("h00"), UInt<3>("h01")) + node T_993 = mux(T_992, T_964, T_991) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= UInt<1>("h00") - oacq_read_block.a_type <= UInt<1>("h00") - oacq_read_block.is_builtin_type <= UInt<1>("h00") - oacq_read_block.addr_beat <= UInt<1>("h00") - oacq_read_block.client_xact_id <= UInt<1>("h00") - oacq_read_block.addr_block <= UInt<1>("h00") + oacq_read_block is invalid oacq_read_block.is_builtin_type <= UInt<1>("h01") oacq_read_block.a_type <= UInt<3>("h01") oacq_read_block.client_xact_id <= UInt<3>("h06") oacq_read_block.addr_block <= xact.addr_block oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= T_1022 + oacq_read_block.union <= T_993 io.outer.acquire.valid <= UInt<1>("h00") - node T_1047 = eq(state, UInt<1>("h01")) - node T_1048 = eq(state, UInt<2>("h03")) - wire T_1057 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1057 <- oacq_write_block - when subblock_type : - T_1057 <- oacq_write_beat - skip - wire T_1073 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1073 <- oacq_read_block - when subblock_type : - T_1073 <- oacq_read_beat - skip - wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1089 <- T_1073 - when T_1048 : - T_1089 <- T_1057 - skip - wire T_1105 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1105 <- T_1089 - when T_1047 : - T_1105 <- oacq_probe - skip - io.outer.acquire.bits <- T_1105 + node T_1011 = eq(state, UInt<1>("h01")) + node T_1012 = eq(state, UInt<2>("h03")) + node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) + node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) + node T_1029 = mux(T_1012, T_1013, T_1021) + node T_1037 = mux(T_1011, oacq_probe, T_1029) + io.outer.acquire.bits <- T_1037 io.outer.grant.ready <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") - node T_1122 = eq(UInt<3>("h04"), xact.a_type) - node T_1123 = mux(T_1122, UInt<1>("h00"), UInt<2>("h02")) - node T_1124 = eq(UInt<3>("h06"), xact.a_type) - node T_1125 = mux(T_1124, UInt<1>("h00"), T_1123) - node T_1126 = eq(UInt<3>("h05"), xact.a_type) - node T_1127 = mux(T_1126, UInt<2>("h02"), T_1125) - node T_1128 = eq(UInt<3>("h02"), xact.a_type) - node T_1129 = mux(T_1128, UInt<1>("h00"), T_1127) - node T_1130 = eq(UInt<3>("h00"), xact.a_type) - node T_1131 = mux(T_1130, UInt<2>("h02"), T_1129) - node T_1132 = eq(UInt<3>("h03"), xact.a_type) - node T_1133 = mux(T_1132, UInt<1>("h00"), T_1131) - node T_1134 = eq(UInt<3>("h01"), xact.a_type) - node T_1135 = mux(T_1134, UInt<2>("h02"), T_1133) - node T_1136 = eq(UInt<1>("h01"), xact.a_type) - node T_1137 = mux(T_1136, UInt<1>("h00"), UInt<2>("h02")) - node T_1138 = eq(UInt<1>("h00"), xact.a_type) - node T_1139 = mux(T_1138, UInt<1>("h01"), T_1137) - node T_1140 = mux(xact.is_builtin_type, T_1135, T_1139) - wire T_1145 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1145.client_id <= UInt<1>("h00") - T_1145.p_type <= UInt<1>("h00") - T_1145.addr_block <= UInt<1>("h00") - T_1145.client_id <= UInt<1>("h00") - T_1145.p_type <= T_1140 - T_1145.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1145 + node T_1054 = eq(UInt<3>("h04"), xact.a_type) + node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02")) + node T_1056 = eq(UInt<3>("h06"), xact.a_type) + node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055) + node T_1058 = eq(UInt<3>("h05"), xact.a_type) + node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057) + node T_1060 = eq(UInt<3>("h02"), xact.a_type) + node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059) + node T_1062 = eq(UInt<3>("h00"), xact.a_type) + node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061) + node T_1064 = eq(UInt<3>("h03"), xact.a_type) + node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063) + node T_1066 = eq(UInt<3>("h01"), xact.a_type) + node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065) + node T_1068 = eq(UInt<1>("h01"), xact.a_type) + node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02")) + node T_1070 = eq(UInt<1>("h00"), xact.a_type) + node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069) + node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) + wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} + T_1077 is invalid + T_1077.client_id <= UInt<1>("h00") + T_1077.p_type <= T_1072 + T_1077.addr_block <= xact.addr_block + io.inner.probe.bits <- T_1077 io.inner.grant.valid <= UInt<1>("h00") - node T_1171 = eq(UInt<3>("h06"), xact.a_type) - node T_1172 = mux(T_1171, UInt<3>("h01"), UInt<3>("h03")) - node T_1173 = eq(UInt<3>("h05"), xact.a_type) - node T_1174 = mux(T_1173, UInt<3>("h01"), T_1172) - node T_1175 = eq(UInt<3>("h04"), xact.a_type) - node T_1176 = mux(T_1175, UInt<3>("h04"), T_1174) - node T_1177 = eq(UInt<3>("h03"), xact.a_type) - node T_1178 = mux(T_1177, UInt<3>("h03"), T_1176) - node T_1179 = eq(UInt<3>("h02"), xact.a_type) - node T_1180 = mux(T_1179, UInt<3>("h03"), T_1178) - node T_1181 = eq(UInt<3>("h01"), xact.a_type) - node T_1182 = mux(T_1181, UInt<3>("h05"), T_1180) - node T_1183 = eq(UInt<3>("h00"), xact.a_type) - node T_1184 = mux(T_1183, UInt<3>("h04"), T_1182) - node T_1185 = eq(xact.a_type, UInt<1>("h00")) - node T_1188 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1189 = mux(T_1188, UInt<1>("h00"), UInt<1>("h01")) - node T_1190 = mux(T_1185, T_1189, UInt<1>("h01")) - node T_1191 = mux(xact.is_builtin_type, T_1184, T_1190) - wire T_1200 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1200.client_id <= UInt<1>("h00") - T_1200.data <= UInt<1>("h00") - T_1200.g_type <= UInt<1>("h00") - T_1200.is_builtin_type <= UInt<1>("h00") - T_1200.manager_xact_id <= UInt<1>("h00") - T_1200.client_xact_id <= UInt<1>("h00") - T_1200.addr_beat <= UInt<1>("h00") - T_1200.client_id <= xact.client_id - T_1200.is_builtin_type <= xact.is_builtin_type - T_1200.g_type <= T_1191 - T_1200.client_xact_id <= xact.client_xact_id - T_1200.manager_xact_id <= UInt<3>("h06") - T_1200.addr_beat <= UInt<1>("h00") - T_1200.data <= UInt<1>("h00") - io.inner.grant.bits <- T_1200 + node T_1100 = eq(UInt<3>("h06"), xact.a_type) + node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03")) + node T_1102 = eq(UInt<3>("h05"), xact.a_type) + node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101) + node T_1104 = eq(UInt<3>("h04"), xact.a_type) + node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103) + node T_1106 = eq(UInt<3>("h03"), xact.a_type) + node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105) + node T_1108 = eq(UInt<3>("h02"), xact.a_type) + node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107) + node T_1110 = eq(UInt<3>("h01"), xact.a_type) + node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109) + node T_1112 = eq(UInt<3>("h00"), xact.a_type) + node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111) + node T_1114 = eq(xact.a_type, UInt<1>("h00")) + node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01")) + node T_1119 = mux(T_1114, T_1118, UInt<1>("h01")) + node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) + wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} + T_1129 is invalid + T_1129.client_id <= xact.client_id + T_1129.is_builtin_type <= xact.is_builtin_type + T_1129.g_type <= T_1120 + T_1129.client_xact_id <= xact.client_xact_id + T_1129.manager_xact_id <= UInt<3>("h06") + T_1129.addr_beat <= UInt<1>("h00") + T_1129.data <= UInt<1>("h00") + io.inner.grant.bits <- T_1129 io.inner.acquire.ready <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") - node T_1218 = neq(state, UInt<1>("h00")) - node T_1219 = and(T_1218, collect_iacq_data) - node T_1220 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1221 = and(T_1219, T_1220) - node T_1222 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1223 = and(T_1221, T_1222) - node T_1225 = eq(T_1223, UInt<1>("h00")) - node T_1227 = eq(reset, UInt<1>("h00")) - when T_1227 : - node T_1229 = eq(T_1225, UInt<1>("h00")) - when T_1229 : - node T_1231 = eq(reset, UInt<1>("h00")) - when T_1231 : + node T_1140 = neq(state, UInt<1>("h00")) + node T_1141 = and(T_1140, collect_iacq_data) + node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1143 = and(T_1141, T_1142) + node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) + node T_1145 = and(T_1143, T_1144) + node T_1147 = eq(T_1145, UInt<1>("h00")) + node T_1149 = eq(reset, UInt<1>("h00")) + when T_1149 : + node T_1151 = eq(T_1147, UInt<1>("h00")) + when T_1151 : + node T_1153 = eq(reset, UInt<1>("h00")) + when T_1153 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1232 = neq(state, UInt<1>("h00")) - node T_1233 = and(T_1232, collect_iacq_data) - node T_1234 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1235 = and(T_1233, T_1234) - node T_1236 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1237 = and(T_1235, T_1236) - node T_1239 = eq(T_1237, UInt<1>("h00")) - node T_1241 = eq(reset, UInt<1>("h00")) - when T_1241 : - node T_1243 = eq(T_1239, UInt<1>("h00")) - when T_1243 : - node T_1245 = eq(reset, UInt<1>("h00")) - when T_1245 : + node T_1154 = neq(state, UInt<1>("h00")) + node T_1155 = and(T_1154, collect_iacq_data) + node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1157 = and(T_1155, T_1156) + node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) + node T_1159 = and(T_1157, T_1158) + node T_1161 = eq(T_1159, UInt<1>("h00")) + node T_1163 = eq(reset, UInt<1>("h00")) + when T_1163 : + node T_1165 = eq(T_1161, UInt<1>("h00")) + when T_1165 : + node T_1167 = eq(reset, UInt<1>("h00")) + when T_1167 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1246 = eq(state, UInt<1>("h00")) - node T_1247 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1248 = and(T_1246, T_1247) - node T_1250 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1253 : UInt<3>[1] - T_1253[0] <= UInt<3>("h03") - node T_1256 = eq(T_1253[0], io.inner.acquire.bits.a_type) - node T_1258 = or(UInt<1>("h00"), T_1256) - node T_1259 = and(T_1250, T_1258) - node T_1260 = and(T_1248, T_1259) - node T_1262 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1263 = and(T_1260, T_1262) - node T_1265 = eq(T_1263, UInt<1>("h00")) - node T_1267 = eq(reset, UInt<1>("h00")) - when T_1267 : - node T_1269 = eq(T_1265, UInt<1>("h00")) - when T_1269 : - node T_1271 = eq(reset, UInt<1>("h00")) - when T_1271 : + node T_1168 = eq(state, UInt<1>("h00")) + node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1170 = and(T_1168, T_1169) + node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_1175 : UInt<3>[1] + T_1175[0] <= UInt<3>("h03") + node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) + node T_1180 = or(UInt<1>("h00"), T_1178) + node T_1181 = and(T_1172, T_1180) + node T_1182 = and(T_1170, T_1181) + node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) + node T_1185 = and(T_1182, T_1184) + node T_1187 = eq(T_1185, UInt<1>("h00")) + node T_1189 = eq(reset, UInt<1>("h00")) + when T_1189 : + node T_1191 = eq(T_1187, UInt<1>("h00")) + when T_1191 : + node T_1193 = eq(reset, UInt<1>("h00")) + when T_1193 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") skip stop(clk, UInt<1>(1), 1) @@ -8330,38 +6842,40 @@ circuit Top : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1275 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1276 = bits(T_1275, 3, 3) - node T_1278 = dshl(UInt<1>("h01"), T_1276) - node T_1280 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1281 = and(io.inner.acquire.bits.is_builtin_type, T_1280) - node T_1282 = bit(T_1278, 0) - node T_1283 = bit(T_1278, 1) - wire T_1285 : UInt<1>[2] - T_1285[0] <= T_1282 - T_1285[1] <= T_1283 - node T_1290 = subw(UInt<8>("h00"), T_1285[0]) - node T_1292 = subw(UInt<8>("h00"), T_1285[1]) - wire T_1294 : UInt<8>[2] - T_1294[0] <= T_1290 - T_1294[1] <= T_1292 - node T_1298 = cat(T_1294[1], T_1294[0]) - node T_1300 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1301 = and(io.inner.acquire.bits.is_builtin_type, T_1300) - node T_1303 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1304 = and(io.inner.acquire.bits.is_builtin_type, T_1303) - node T_1305 = or(T_1301, T_1304) - node T_1306 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1308 = mux(T_1305, T_1306, UInt<16>("h00")) - node T_1309 = mux(T_1281, T_1298, T_1308) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1309 - node T_1312 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) - node T_1313 = or(iacq_data_valid, T_1312) - node T_1314 = not(iacq_data_valid) - node T_1315 = or(T_1314, T_1312) - node T_1316 = not(T_1315) - node T_1317 = mux(UInt<1>("h01"), T_1313, T_1316) - iacq_data_valid <= T_1317 + node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) + node T_1198 = bits(T_1197, 3, 3) + node T_1200 = dshl(UInt<1>("h01"), T_1198) + node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) + node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) + node T_1204 = bits(T_1200, 0, 0) + node T_1205 = bits(T_1200, 1, 1) + wire T_1207 : UInt<1>[2] + T_1207[0] <= T_1204 + T_1207[1] <= T_1205 + node T_1212 = sub(UInt<8>("h00"), T_1207[0]) + node T_1213 = tail(T_1212, 1) + node T_1215 = sub(UInt<8>("h00"), T_1207[1]) + node T_1216 = tail(T_1215, 1) + wire T_1218 : UInt<8>[2] + T_1218[0] <= T_1213 + T_1218[1] <= T_1216 + node T_1222 = cat(T_1218[1], T_1218[0]) + node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) + node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) + node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) + node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) + node T_1229 = or(T_1225, T_1228) + node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) + node T_1232 = mux(T_1229, T_1230, UInt<16>("h00")) + node T_1233 = mux(T_1203, T_1222, T_1232) + xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 + node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) + node T_1237 = or(iacq_data_valid, T_1236) + node T_1238 = not(iacq_data_valid) + node T_1239 = or(T_1238, T_1236) + node T_1240 = not(T_1239) + node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240) + iacq_data_valid <= T_1241 skip when iacq_data_done : collect_iacq_data <= UInt<1>("h00") @@ -8373,194 +6887,201 @@ circuit Top : pending_ognt_ack <= UInt<1>("h00") skip skip - node T_1321 = eq(UInt<1>("h00"), state) - when T_1321 : + node T_1245 = eq(UInt<1>("h00"), state) + when T_1245 : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact <- io.inner.acquire.bits xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data - node T_1327 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1328 = bits(T_1327, 3, 3) - node T_1330 = dshl(UInt<1>("h01"), T_1328) - node T_1332 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1333 = and(io.inner.acquire.bits.is_builtin_type, T_1332) - node T_1334 = bit(T_1330, 0) - node T_1335 = bit(T_1330, 1) - wire T_1337 : UInt<1>[2] - T_1337[0] <= T_1334 - T_1337[1] <= T_1335 - node T_1342 = subw(UInt<8>("h00"), T_1337[0]) - node T_1344 = subw(UInt<8>("h00"), T_1337[1]) - wire T_1346 : UInt<8>[2] - T_1346[0] <= T_1342 - T_1346[1] <= T_1344 - node T_1350 = cat(T_1346[1], T_1346[0]) - node T_1352 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1353 = and(io.inner.acquire.bits.is_builtin_type, T_1352) - node T_1355 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1356 = and(io.inner.acquire.bits.is_builtin_type, T_1355) - node T_1357 = or(T_1353, T_1356) - node T_1358 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1360 = mux(T_1357, T_1358, UInt<16>("h00")) - node T_1361 = mux(T_1333, T_1350, T_1360) - xact.wmask_buffer[UInt<1>("h00")] <= T_1361 - node T_1363 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1366 : UInt<3>[1] - T_1366[0] <= UInt<3>("h03") - node T_1369 = eq(T_1366[0], io.inner.acquire.bits.a_type) - node T_1371 = or(UInt<1>("h00"), T_1369) - node T_1372 = and(T_1363, T_1371) - collect_iacq_data <= T_1372 - wire T_1377 : UInt<3>[3] - T_1377[0] <= UInt<3>("h02") - T_1377[1] <= UInt<3>("h03") - T_1377[2] <= UInt<3>("h04") - node T_1382 = eq(T_1377[0], io.inner.acquire.bits.a_type) - node T_1383 = eq(T_1377[1], io.inner.acquire.bits.a_type) - node T_1384 = eq(T_1377[2], io.inner.acquire.bits.a_type) - node T_1386 = or(UInt<1>("h00"), T_1382) - node T_1387 = or(T_1386, T_1383) - node T_1388 = or(T_1387, T_1384) - node T_1389 = and(io.inner.acquire.bits.is_builtin_type, T_1388) - node T_1390 = dshl(T_1389, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1390 - node T_1392 = neq(mask_incoherent, UInt<1>("h00")) - when T_1392 : + node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) + node T_1252 = bits(T_1251, 3, 3) + node T_1254 = dshl(UInt<1>("h01"), T_1252) + node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) + node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) + node T_1258 = bits(T_1254, 0, 0) + node T_1259 = bits(T_1254, 1, 1) + wire T_1261 : UInt<1>[2] + T_1261[0] <= T_1258 + T_1261[1] <= T_1259 + node T_1266 = sub(UInt<8>("h00"), T_1261[0]) + node T_1267 = tail(T_1266, 1) + node T_1269 = sub(UInt<8>("h00"), T_1261[1]) + node T_1270 = tail(T_1269, 1) + wire T_1272 : UInt<8>[2] + T_1272[0] <= T_1267 + T_1272[1] <= T_1270 + node T_1276 = cat(T_1272[1], T_1272[0]) + node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) + node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) + node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) + node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) + node T_1283 = or(T_1279, T_1282) + node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) + node T_1286 = mux(T_1283, T_1284, UInt<16>("h00")) + node T_1287 = mux(T_1257, T_1276, T_1286) + xact.wmask_buffer[UInt<1>("h00")] <= T_1287 + node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_1292 : UInt<3>[1] + T_1292[0] <= UInt<3>("h03") + node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) + node T_1297 = or(UInt<1>("h00"), T_1295) + node T_1298 = and(T_1289, T_1297) + collect_iacq_data <= T_1298 + wire T_1303 : UInt<3>[3] + T_1303[0] <= UInt<3>("h02") + T_1303[1] <= UInt<3>("h03") + T_1303[2] <= UInt<3>("h04") + node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) + node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) + node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) + node T_1312 = or(UInt<1>("h00"), T_1308) + node T_1313 = or(T_1312, T_1309) + node T_1314 = or(T_1313, T_1310) + node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) + node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) + iacq_data_valid <= T_1316 + node T_1318 = neq(mask_incoherent, UInt<1>("h00")) + when T_1318 : pending_probes <= mask_incoherent - node T_1393 = bit(mask_incoherent, 0) - node T_1394 = bit(mask_incoherent, 1) - node T_1395 = bit(mask_incoherent, 2) - node T_1396 = bit(mask_incoherent, 3) - node T_1398 = cat(UInt<1>("h00"), T_1394) - node T_1399 = addw(T_1393, T_1398) - node T_1402 = cat(UInt<1>("h00"), T_1396) - node T_1403 = addw(T_1395, T_1402) - node T_1404 = cat(UInt<1>("h00"), T_1403) - node T_1405 = addw(T_1399, T_1404) - release_count <= T_1405 + node T_1319 = bits(mask_incoherent, 0, 0) + node T_1320 = bits(mask_incoherent, 1, 1) + node T_1321 = bits(mask_incoherent, 2, 2) + node T_1322 = bits(mask_incoherent, 3, 3) + node T_1324 = cat(UInt<1>("h00"), T_1320) + node T_1325 = add(T_1319, T_1324) + node T_1326 = tail(T_1325, 1) + node T_1329 = cat(UInt<1>("h00"), T_1322) + node T_1330 = add(T_1321, T_1329) + node T_1331 = tail(T_1330, 1) + node T_1332 = cat(UInt<1>("h00"), T_1331) + node T_1333 = add(T_1326, T_1332) + node T_1334 = tail(T_1333, 1) + release_count <= T_1334 skip - node T_1406 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_1407 = mux(pending_outer_write_, UInt<2>("h03"), T_1406) - node T_1408 = mux(T_1392, UInt<1>("h01"), T_1407) - state <= T_1408 + node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) + node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335) + node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336) + state <= T_1337 skip skip - node T_1409 = eq(UInt<1>("h01"), state) - when T_1409 : - node T_1411 = neq(pending_probes, UInt<1>("h00")) - io.inner.probe.valid <= T_1411 + node T_1338 = eq(UInt<1>("h01"), state) + when T_1338 : + node T_1340 = neq(pending_probes, UInt<1>("h00")) + io.inner.probe.valid <= T_1340 when io.inner.probe.ready : - node T_1413 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_1414 = not(T_1413) - node T_1415 = and(pending_probes, T_1414) - pending_probes <= T_1415 - skip - wire T_1417 : UInt<2>[3] - T_1417[0] <= UInt<1>("h00") - T_1417[1] <= UInt<1>("h01") - T_1417[2] <= UInt<2>("h02") - node T_1422 = eq(T_1417[0], io.inner.release.bits.r_type) - node T_1423 = eq(T_1417[1], io.inner.release.bits.r_type) - node T_1424 = eq(T_1417[2], io.inner.release.bits.r_type) - node T_1426 = or(UInt<1>("h00"), T_1422) - node T_1427 = or(T_1426, T_1423) - node T_1428 = or(T_1427, T_1424) - node T_1430 = eq(T_1428, UInt<1>("h00")) - node T_1431 = or(T_1430, io.outer.acquire.ready) - io.inner.release.ready <= T_1431 + node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00")) + node T_1343 = not(T_1342) + node T_1344 = and(pending_probes, T_1343) + pending_probes <= T_1344 + skip + wire T_1346 : UInt<2>[3] + T_1346[0] <= UInt<1>("h00") + T_1346[1] <= UInt<1>("h01") + T_1346[2] <= UInt<2>("h02") + node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) + node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) + node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) + node T_1355 = or(UInt<1>("h00"), T_1351) + node T_1356 = or(T_1355, T_1352) + node T_1357 = or(T_1356, T_1353) + node T_1359 = eq(T_1357, UInt<1>("h00")) + node T_1360 = or(T_1359, io.outer.acquire.ready) + io.inner.release.ready <= T_1360 when io.inner.release.valid : - wire T_1433 : UInt<2>[3] - T_1433[0] <= UInt<1>("h00") - T_1433[1] <= UInt<1>("h01") - T_1433[2] <= UInt<2>("h02") - node T_1438 = eq(T_1433[0], io.inner.release.bits.r_type) - node T_1439 = eq(T_1433[1], io.inner.release.bits.r_type) - node T_1440 = eq(T_1433[2], io.inner.release.bits.r_type) - node T_1442 = or(UInt<1>("h00"), T_1438) - node T_1443 = or(T_1442, T_1439) - node T_1444 = or(T_1443, T_1440) - when T_1444 : + wire T_1362 : UInt<2>[3] + T_1362[0] <= UInt<1>("h00") + T_1362[1] <= UInt<1>("h01") + T_1362[2] <= UInt<2>("h02") + node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) + node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) + node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) + node T_1371 = or(UInt<1>("h00"), T_1367) + node T_1372 = or(T_1371, T_1368) + node T_1373 = or(T_1372, T_1369) + when T_1373 : io.outer.acquire.valid <= UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") - node T_1448 = subw(release_count, UInt<1>("h01")) - release_count <= T_1448 - node T_1450 = eq(release_count, UInt<1>("h01")) - when T_1450 : - node T_1451 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1452 = mux(pending_outer_write, UInt<2>("h03"), T_1451) - state <= T_1452 + node T_1377 = sub(release_count, UInt<1>("h01")) + node T_1378 = tail(T_1377, 1) + release_count <= T_1378 + node T_1380 = eq(release_count, UInt<1>("h01")) + when T_1380 : + node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381) + state <= T_1382 skip skip skip skip - node T_1454 = eq(T_1444, UInt<1>("h00")) - when T_1454 : - node T_1456 = subw(release_count, UInt<1>("h01")) - release_count <= T_1456 - node T_1458 = eq(release_count, UInt<1>("h01")) - when T_1458 : - node T_1459 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1460 = mux(pending_outer_write, UInt<2>("h03"), T_1459) - state <= T_1460 + node T_1384 = eq(T_1373, UInt<1>("h00")) + when T_1384 : + node T_1386 = sub(release_count, UInt<1>("h01")) + node T_1387 = tail(T_1386, 1) + release_count <= T_1387 + node T_1389 = eq(release_count, UInt<1>("h01")) + when T_1389 : + node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390) + state <= T_1391 skip skip skip skip - node T_1461 = eq(UInt<2>("h03"), state) - when T_1461 : - node T_1463 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_1465 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1466 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1467 = bit(T_1466, 0) - node T_1468 = or(T_1465, T_1467) - node T_1469 = and(T_1463, T_1468) - io.outer.acquire.valid <= T_1469 + node T_1392 = eq(UInt<2>("h03"), state) + when T_1392 : + node T_1394 = eq(pending_ognt_ack, UInt<1>("h00")) + node T_1396 = eq(collect_iacq_data, UInt<1>("h00")) + node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) + node T_1398 = bits(T_1397, 0, 0) + node T_1399 = or(T_1396, T_1398) + node T_1400 = and(T_1394, T_1399) + io.outer.acquire.valid <= T_1400 when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") - node T_1471 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state <= T_1471 + node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) + state <= T_1402 skip skip - node T_1472 = eq(UInt<2>("h02"), state) - when T_1472 : - node T_1474 = eq(pending_ognt_ack, UInt<1>("h00")) - io.outer.acquire.valid <= T_1474 - node T_1475 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1475 : + node T_1403 = eq(UInt<2>("h02"), state) + when T_1403 : + node T_1405 = eq(pending_ognt_ack, UInt<1>("h00")) + io.outer.acquire.valid <= T_1405 + node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) + when T_1406 : state <= UInt<3>("h05") skip skip - node T_1476 = eq(UInt<3>("h05"), state) - when T_1476 : + node T_1407 = eq(UInt<3>("h05"), state) + when T_1407 : io.outer.grant.ready <= io.inner.grant.ready io.inner.grant.valid <= io.outer.grant.valid when ignt_data_done : - node T_1479 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1481 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1482 = and(io.inner.grant.bits.is_builtin_type, T_1481) - node T_1484 = eq(T_1482, UInt<1>("h00")) - node T_1485 = and(T_1479, T_1484) - node T_1486 = mux(T_1485, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1486 + node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) + node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) + node T_1415 = eq(T_1413, UInt<1>("h00")) + node T_1416 = and(T_1410, T_1415) + node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00")) + state <= T_1417 skip skip - node T_1487 = eq(UInt<3>("h04"), state) - when T_1487 : + node T_1418 = eq(UInt<3>("h04"), state) + when T_1418 : io.inner.grant.valid <= UInt<1>("h01") when io.inner.grant.ready : - node T_1491 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1493 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1494 = and(io.inner.grant.bits.is_builtin_type, T_1493) - node T_1496 = eq(T_1494, UInt<1>("h00")) - node T_1497 = and(T_1491, T_1496) - node T_1498 = mux(T_1497, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1498 + node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) + node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) + node T_1427 = eq(T_1425, UInt<1>("h00")) + node T_1428 = and(T_1422, T_1427) + node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00")) + state <= T_1429 skip skip - node T_1499 = eq(UInt<3>("h06"), state) - when T_1499 : + node T_1430 = eq(UInt<3>("h06"), state) + when T_1430 : io.inner.finish.ready <= UInt<1>("h01") when io.inner.finish.valid : state <= UInt<1>("h00") @@ -8572,98 +7093,73 @@ circuit Top : input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>} - io.has_release_match <= UInt<1>("h00") - io.has_acquire_match <= UInt<1>("h00") - io.has_acquire_conflict <= UInt<1>("h00") - io.outer.grant.ready <= UInt<1>("h00") - io.outer.acquire.bits.data <= UInt<1>("h00") - io.outer.acquire.bits.union <= UInt<1>("h00") - io.outer.acquire.bits.a_type <= UInt<1>("h00") - io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.outer.acquire.bits.addr_beat <= UInt<1>("h00") - io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") - io.outer.acquire.bits.addr_block <= UInt<1>("h00") - io.outer.acquire.valid <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.probe.bits.client_id <= UInt<1>("h00") - io.inner.probe.bits.p_type <= UInt<1>("h00") - io.inner.probe.bits.addr_block <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - io.inner.grant.bits.client_id <= UInt<1>("h00") - io.inner.grant.bits.data <= UInt<1>("h00") - io.inner.grant.bits.g_type <= UInt<1>("h00") - io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") - io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") - io.inner.grant.bits.client_xact_id <= UInt<1>("h00") - io.inner.grant.bits.addr_beat <= UInt<1>("h00") - io.inner.grant.valid <= UInt<1>("h00") - io.inner.acquire.ready <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") - reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk, UInt<1>("h00"), xact + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk wire coh : {sharers : UInt<1>} + coh is invalid coh.sharers <= UInt<1>("h00") - coh.sharers <= UInt<1>("h00") - node T_304 = neq(state, UInt<1>("h00")) - node T_305 = and(T_304, xact.is_builtin_type) - wire T_310 : UInt<3>[3] - T_310[0] <= UInt<3>("h04") - T_310[1] <= UInt<3>("h05") - T_310[2] <= UInt<3>("h06") - node T_315 = eq(T_310[0], xact.a_type) - node T_316 = eq(T_310[1], xact.a_type) - node T_317 = eq(T_310[2], xact.a_type) - node T_319 = or(UInt<1>("h00"), T_315) + node T_303 = neq(state, UInt<1>("h00")) + node T_304 = and(T_303, xact.is_builtin_type) + wire T_309 : UInt<3>[3] + T_309[0] <= UInt<3>("h04") + T_309[1] <= UInt<3>("h05") + T_309[2] <= UInt<3>("h06") + node T_314 = eq(T_309[0], xact.a_type) + node T_315 = eq(T_309[1], xact.a_type) + node T_316 = eq(T_309[2], xact.a_type) + node T_318 = or(UInt<1>("h00"), T_314) + node T_319 = or(T_318, T_315) node T_320 = or(T_319, T_316) - node T_321 = or(T_320, T_317) - node T_322 = and(T_305, T_321) - node T_324 = eq(T_322, UInt<1>("h00")) - node T_326 = eq(reset, UInt<1>("h00")) - when T_326 : - node T_328 = eq(T_324, UInt<1>("h00")) - when T_328 : - node T_330 = eq(reset, UInt<1>("h00")) - when T_330 : + node T_321 = and(T_304, T_320) + node T_323 = eq(T_321, UInt<1>("h00")) + node T_325 = eq(reset, UInt<1>("h00")) + when T_325 : + node T_327 = eq(T_323, UInt<1>("h00")) + when T_327 : + node T_329 = eq(reset, UInt<1>("h00")) + when T_329 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches") skip stop(clk, UInt<1>(1), 1) skip skip - reg release_count : UInt<1>, clk, reset, UInt<1>("h00") - reg pending_probes : UInt<1>, clk, reset, UInt<1>("h00") - node T_335 = bit(pending_probes, 0) - wire T_337 : UInt<1>[1] - T_337[0] <= T_335 - node T_342 = asUInt(asSInt(UInt<1>("h01"))) - node T_345 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) - node T_346 = or(T_342, T_345) - node T_347 = not(T_342) - node T_348 = or(T_347, T_345) - node T_349 = not(T_348) - node mask_self = mux(UInt<1>("h00"), T_346, T_349) - node T_351 = not(io.incoherent[0]) - node mask_incoherent = and(mask_self, T_351) - reg collect_iacq_data : UInt<1>, clk, reset, UInt<1>("h00") - reg iacq_data_valid : UInt<4>, clk, reset, UInt<4>("h00") - node T_357 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_360 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_363 : UInt<3>[1] - T_363[0] <= UInt<3>("h03") - node T_366 = eq(T_363[0], io.inner.acquire.bits.a_type) - node T_368 = or(UInt<1>("h00"), T_366) - node T_369 = and(T_360, T_368) - node T_370 = and(T_357, T_369) - reg T_372 : UInt<2>, clk, reset, UInt<2>("h00") - when T_370 : - node T_374 = eq(T_372, UInt<2>("h03")) - node T_376 = and(UInt<1>("h00"), T_374) - node T_379 = addw(T_372, UInt<1>("h01")) - node T_380 = mux(T_376, UInt<1>("h00"), T_379) - T_372 <= T_380 - skip - node T_381 = and(T_370, T_374) - node T_382 = mux(T_369, T_372, UInt<1>("h00")) - node iacq_data_done = mux(T_369, T_381, T_357) + reg release_count : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg pending_probes : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_334 = bits(pending_probes, 0, 0) + wire T_336 : UInt<1>[1] + T_336[0] <= T_334 + node T_341 = asUInt(asSInt(UInt<1>("h01"))) + node T_344 = dshl(UInt<1>("h01"), io.inner.acquire.bits.client_id) + node T_345 = or(T_341, T_344) + node T_346 = not(T_341) + node T_347 = or(T_346, T_344) + node T_348 = not(T_347) + node mask_self = mux(UInt<1>("h00"), T_345, T_348) + node T_350 = not(io.incoherent[0]) + node mask_incoherent = and(mask_self, T_350) + reg collect_iacq_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg iacq_data_valid : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) + node T_356 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_359 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_362 : UInt<3>[1] + T_362[0] <= UInt<3>("h03") + node T_365 = eq(T_362[0], io.inner.acquire.bits.a_type) + node T_367 = or(UInt<1>("h00"), T_365) + node T_368 = and(T_359, T_367) + node T_369 = and(T_356, T_368) + reg T_371 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_369 : + node T_373 = eq(T_371, UInt<2>("h03")) + node T_375 = and(UInt<1>("h00"), T_373) + node T_378 = add(T_371, UInt<1>("h01")) + node T_379 = tail(T_378, 1) + node T_380 = mux(T_375, UInt<1>("h00"), T_379) + T_371 <= T_380 + skip + node T_381 = and(T_369, T_373) + node T_382 = mux(T_368, T_371, UInt<1>("h00")) + node iacq_data_done = mux(T_368, T_381, T_356) node T_384 = and(io.inner.release.ready, io.inner.release.valid) wire T_388 : UInt<2>[3] T_388[0] <= UInt<1>("h00") @@ -8677,577 +7173,523 @@ circuit Top : node T_399 = or(T_398, T_395) node T_400 = and(UInt<1>("h01"), T_399) node T_401 = and(T_384, T_400) - reg T_403 : UInt<2>, clk, reset, UInt<2>("h00") + reg T_403 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) when T_401 : node T_405 = eq(T_403, UInt<2>("h03")) node T_407 = and(UInt<1>("h00"), T_405) - node T_410 = addw(T_403, UInt<1>("h01")) - node T_411 = mux(T_407, UInt<1>("h00"), T_410) - T_403 <= T_411 - skip - node T_412 = and(T_401, T_405) - node T_413 = mux(T_400, T_403, UInt<1>("h00")) - node irel_data_done = mux(T_400, T_412, T_384) - node T_416 = and(io.inner.grant.ready, io.inner.grant.valid) - wire T_420 : UInt<3>[1] - T_420[0] <= UInt<3>("h05") - node T_423 = eq(T_420[0], io.inner.grant.bits.g_type) - node T_425 = or(UInt<1>("h00"), T_423) - wire T_427 : UInt<1>[2] - T_427[0] <= UInt<1>("h00") - T_427[1] <= UInt<1>("h01") - node T_431 = eq(T_427[0], io.inner.grant.bits.g_type) - node T_432 = eq(T_427[1], io.inner.grant.bits.g_type) - node T_434 = or(UInt<1>("h00"), T_431) - node T_435 = or(T_434, T_432) - node T_436 = mux(io.inner.grant.bits.is_builtin_type, T_425, T_435) - node T_437 = and(UInt<1>("h01"), T_436) - node T_438 = and(T_416, T_437) - reg T_440 : UInt<2>, clk, reset, UInt<2>("h00") - when T_438 : - node T_442 = eq(T_440, UInt<2>("h03")) - node T_444 = and(UInt<1>("h00"), T_442) - node T_447 = addw(T_440, UInt<1>("h01")) - node T_448 = mux(T_444, UInt<1>("h00"), T_447) - T_440 <= T_448 - skip - node T_449 = and(T_438, T_442) - node ignt_data_cnt = mux(T_437, T_440, UInt<1>("h00")) - node ignt_data_done = mux(T_437, T_449, T_416) - node T_453 = and(io.outer.acquire.ready, io.outer.acquire.valid) - node T_455 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) - wire T_458 : UInt<3>[1] - T_458[0] <= UInt<3>("h03") - node T_461 = eq(T_458[0], io.outer.acquire.bits.a_type) - node T_463 = or(UInt<1>("h00"), T_461) - node T_464 = and(T_455, T_463) - node T_465 = and(T_453, T_464) - reg T_467 : UInt<2>, clk, reset, UInt<2>("h00") - when T_465 : - node T_469 = eq(T_467, UInt<2>("h03")) - node T_471 = and(UInt<1>("h00"), T_469) - node T_474 = addw(T_467, UInt<1>("h01")) - node T_475 = mux(T_471, UInt<1>("h00"), T_474) - T_467 <= T_475 - skip - node T_476 = and(T_465, T_469) - node oacq_data_cnt = mux(T_464, T_467, UInt<1>("h00")) - node oacq_data_done = mux(T_464, T_476, T_453) - node T_479 = and(io.outer.grant.ready, io.outer.grant.valid) - wire T_484 : UInt<3>[1] - T_484[0] <= UInt<3>("h05") - node T_487 = eq(T_484[0], io.outer.grant.bits.g_type) - node T_489 = or(UInt<1>("h00"), T_487) - wire T_491 : UInt<1>[1] - T_491[0] <= UInt<1>("h00") - node T_494 = eq(T_491[0], io.outer.grant.bits.g_type) - node T_496 = or(UInt<1>("h00"), T_494) - node T_497 = mux(io.outer.grant.bits.is_builtin_type, T_489, T_496) - node T_498 = and(UInt<1>("h01"), T_497) - node T_499 = and(T_479, T_498) - reg T_501 : UInt<2>, clk, reset, UInt<2>("h00") - when T_499 : - node T_503 = eq(T_501, UInt<2>("h03")) - node T_505 = and(UInt<1>("h00"), T_503) - node T_508 = addw(T_501, UInt<1>("h01")) - node T_509 = mux(T_505, UInt<1>("h00"), T_508) - T_501 <= T_509 - skip - node T_510 = and(T_499, T_503) - node T_511 = mux(T_498, T_501, UInt<1>("h00")) - node ognt_data_done = mux(T_498, T_510, T_479) - reg pending_ognt_ack : UInt<1>, clk, reset, UInt<1>("h00") - wire T_519 : UInt<3>[3] - T_519[0] <= UInt<3>("h02") - T_519[1] <= UInt<3>("h03") - T_519[2] <= UInt<3>("h04") - node T_524 = eq(T_519[0], xact.a_type) - node T_525 = eq(T_519[1], xact.a_type) - node T_526 = eq(T_519[2], xact.a_type) - node T_528 = or(UInt<1>("h00"), T_524) - node T_529 = or(T_528, T_525) - node T_530 = or(T_529, T_526) - node pending_outer_write = and(xact.is_builtin_type, T_530) - wire T_536 : UInt<3>[3] - T_536[0] <= UInt<3>("h02") - T_536[1] <= UInt<3>("h03") - T_536[2] <= UInt<3>("h04") - node T_541 = eq(T_536[0], io.inner.acquire.bits.a_type) - node T_542 = eq(T_536[1], io.inner.acquire.bits.a_type) - node T_543 = eq(T_536[2], io.inner.acquire.bits.a_type) - node T_545 = or(UInt<1>("h00"), T_541) - node T_546 = or(T_545, T_542) - node T_547 = or(T_546, T_543) - node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_547) - wire T_552 : UInt<3>[2] - T_552[0] <= UInt<3>("h05") - T_552[1] <= UInt<3>("h04") - node T_556 = eq(T_552[0], io.inner.grant.bits.g_type) - node T_557 = eq(T_552[1], io.inner.grant.bits.g_type) - node T_559 = or(UInt<1>("h00"), T_556) - node T_560 = or(T_559, T_557) - wire T_562 : UInt<1>[2] - T_562[0] <= UInt<1>("h00") - T_562[1] <= UInt<1>("h01") - node T_566 = eq(T_562[0], io.inner.grant.bits.g_type) - node T_567 = eq(T_562[1], io.inner.grant.bits.g_type) - node T_569 = or(UInt<1>("h00"), T_566) - node T_570 = or(T_569, T_567) - node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_560, T_570) - node T_590 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) - node T_591 = mux(T_590, UInt<3>("h01"), UInt<3>("h03")) - node T_592 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) - node T_593 = mux(T_592, UInt<3>("h01"), T_591) - node T_594 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) - node T_595 = mux(T_594, UInt<3>("h04"), T_593) - node T_596 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) - node T_597 = mux(T_596, UInt<3>("h03"), T_595) - node T_598 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) - node T_599 = mux(T_598, UInt<3>("h03"), T_597) - node T_600 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) - node T_601 = mux(T_600, UInt<3>("h05"), T_599) - node T_602 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) - node T_603 = mux(T_602, UInt<3>("h04"), T_601) - node T_604 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) - node T_607 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_608 = mux(T_607, UInt<1>("h00"), UInt<1>("h01")) - node T_609 = mux(T_604, T_608, UInt<1>("h01")) - node T_610 = mux(io.inner.acquire.bits.is_builtin_type, T_603, T_609) - wire T_619 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_619.client_id <= UInt<1>("h00") - T_619.data <= UInt<1>("h00") - T_619.g_type <= UInt<1>("h00") - T_619.is_builtin_type <= UInt<1>("h00") - T_619.manager_xact_id <= UInt<1>("h00") - T_619.client_xact_id <= UInt<1>("h00") - T_619.addr_beat <= UInt<1>("h00") - T_619.client_id <= io.inner.acquire.bits.client_id - T_619.is_builtin_type <= io.inner.acquire.bits.is_builtin_type - T_619.g_type <= T_610 - T_619.client_xact_id <= io.inner.acquire.bits.client_xact_id - T_619.manager_xact_id <= UInt<3>("h07") - T_619.addr_beat <= UInt<1>("h00") - T_619.data <= UInt<1>("h00") - wire T_637 : UInt<3>[2] - T_637[0] <= UInt<3>("h05") - T_637[1] <= UInt<3>("h04") - node T_641 = eq(T_637[0], T_619.g_type) - node T_642 = eq(T_637[1], T_619.g_type) - node T_644 = or(UInt<1>("h00"), T_641) - node T_645 = or(T_644, T_642) - wire T_647 : UInt<1>[2] - T_647[0] <= UInt<1>("h00") - T_647[1] <= UInt<1>("h01") - node T_651 = eq(T_647[0], T_619.g_type) - node T_652 = eq(T_647[1], T_619.g_type) - node T_654 = or(UInt<1>("h00"), T_651) - node T_655 = or(T_654, T_652) - node pending_outer_read_ = mux(T_619.is_builtin_type, T_645, T_655) - wire T_661 : UInt<3>[3] - T_661[0] <= UInt<3>("h02") - T_661[1] <= UInt<3>("h00") - T_661[2] <= UInt<3>("h04") - node T_666 = eq(T_661[0], xact.a_type) - node T_667 = eq(T_661[1], xact.a_type) - node T_668 = eq(T_661[2], xact.a_type) - node T_670 = or(UInt<1>("h00"), T_666) - node T_671 = or(T_670, T_667) - node T_672 = or(T_671, T_668) - node subblock_type = and(xact.is_builtin_type, T_672) - node T_674 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_675 = neq(state, UInt<1>("h00")) - node T_676 = and(T_674, T_675) - node T_678 = eq(collect_iacq_data, UInt<1>("h00")) - node T_679 = and(T_676, T_678) - io.has_acquire_conflict <= T_679 - node T_680 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) - node T_681 = and(T_680, collect_iacq_data) - io.has_acquire_match <= T_681 - node T_682 = eq(xact.addr_block, io.inner.release.bits.addr_block) - node T_684 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) - node T_685 = and(T_682, T_684) - node T_686 = eq(state, UInt<1>("h01")) - node T_687 = and(T_685, T_686) - io.has_release_match <= T_687 - node T_692 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_698 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_410 = add(T_403, UInt<1>("h01")) + node T_411 = tail(T_410, 1) + node T_412 = mux(T_407, UInt<1>("h00"), T_411) + T_403 <= T_412 + skip + node T_413 = and(T_401, T_405) + node T_414 = mux(T_400, T_403, UInt<1>("h00")) + node irel_data_done = mux(T_400, T_413, T_384) + node T_417 = and(io.inner.grant.ready, io.inner.grant.valid) + wire T_421 : UInt<3>[1] + T_421[0] <= UInt<3>("h05") + node T_424 = eq(T_421[0], io.inner.grant.bits.g_type) + node T_426 = or(UInt<1>("h00"), T_424) + wire T_428 : UInt<1>[2] + T_428[0] <= UInt<1>("h00") + T_428[1] <= UInt<1>("h01") + node T_432 = eq(T_428[0], io.inner.grant.bits.g_type) + node T_433 = eq(T_428[1], io.inner.grant.bits.g_type) + node T_435 = or(UInt<1>("h00"), T_432) + node T_436 = or(T_435, T_433) + node T_437 = mux(io.inner.grant.bits.is_builtin_type, T_426, T_436) + node T_438 = and(UInt<1>("h01"), T_437) + node T_439 = and(T_417, T_438) + reg T_441 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_439 : + node T_443 = eq(T_441, UInt<2>("h03")) + node T_445 = and(UInt<1>("h00"), T_443) + node T_448 = add(T_441, UInt<1>("h01")) + node T_449 = tail(T_448, 1) + node T_450 = mux(T_445, UInt<1>("h00"), T_449) + T_441 <= T_450 + skip + node T_451 = and(T_439, T_443) + node ignt_data_cnt = mux(T_438, T_441, UInt<1>("h00")) + node ignt_data_done = mux(T_438, T_451, T_417) + node T_455 = and(io.outer.acquire.ready, io.outer.acquire.valid) + node T_457 = and(UInt<1>("h01"), io.outer.acquire.bits.is_builtin_type) + wire T_460 : UInt<3>[1] + T_460[0] <= UInt<3>("h03") + node T_463 = eq(T_460[0], io.outer.acquire.bits.a_type) + node T_465 = or(UInt<1>("h00"), T_463) + node T_466 = and(T_457, T_465) + node T_467 = and(T_455, T_466) + reg T_469 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_467 : + node T_471 = eq(T_469, UInt<2>("h03")) + node T_473 = and(UInt<1>("h00"), T_471) + node T_476 = add(T_469, UInt<1>("h01")) + node T_477 = tail(T_476, 1) + node T_478 = mux(T_473, UInt<1>("h00"), T_477) + T_469 <= T_478 + skip + node T_479 = and(T_467, T_471) + node oacq_data_cnt = mux(T_466, T_469, UInt<1>("h00")) + node oacq_data_done = mux(T_466, T_479, T_455) + node T_482 = and(io.outer.grant.ready, io.outer.grant.valid) + wire T_487 : UInt<3>[1] + T_487[0] <= UInt<3>("h05") + node T_490 = eq(T_487[0], io.outer.grant.bits.g_type) + node T_492 = or(UInt<1>("h00"), T_490) + wire T_494 : UInt<1>[1] + T_494[0] <= UInt<1>("h00") + node T_497 = eq(T_494[0], io.outer.grant.bits.g_type) + node T_499 = or(UInt<1>("h00"), T_497) + node T_500 = mux(io.outer.grant.bits.is_builtin_type, T_492, T_499) + node T_501 = and(UInt<1>("h01"), T_500) + node T_502 = and(T_482, T_501) + reg T_504 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_502 : + node T_506 = eq(T_504, UInt<2>("h03")) + node T_508 = and(UInt<1>("h00"), T_506) + node T_511 = add(T_504, UInt<1>("h01")) + node T_512 = tail(T_511, 1) + node T_513 = mux(T_508, UInt<1>("h00"), T_512) + T_504 <= T_513 + skip + node T_514 = and(T_502, T_506) + node T_515 = mux(T_501, T_504, UInt<1>("h00")) + node ognt_data_done = mux(T_501, T_514, T_482) + reg pending_ognt_ack : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + wire T_523 : UInt<3>[3] + T_523[0] <= UInt<3>("h02") + T_523[1] <= UInt<3>("h03") + T_523[2] <= UInt<3>("h04") + node T_528 = eq(T_523[0], xact.a_type) + node T_529 = eq(T_523[1], xact.a_type) + node T_530 = eq(T_523[2], xact.a_type) + node T_532 = or(UInt<1>("h00"), T_528) + node T_533 = or(T_532, T_529) + node T_534 = or(T_533, T_530) + node pending_outer_write = and(xact.is_builtin_type, T_534) + wire T_540 : UInt<3>[3] + T_540[0] <= UInt<3>("h02") + T_540[1] <= UInt<3>("h03") + T_540[2] <= UInt<3>("h04") + node T_545 = eq(T_540[0], io.inner.acquire.bits.a_type) + node T_546 = eq(T_540[1], io.inner.acquire.bits.a_type) + node T_547 = eq(T_540[2], io.inner.acquire.bits.a_type) + node T_549 = or(UInt<1>("h00"), T_545) + node T_550 = or(T_549, T_546) + node T_551 = or(T_550, T_547) + node pending_outer_write_ = and(io.inner.acquire.bits.is_builtin_type, T_551) + wire T_556 : UInt<3>[2] + T_556[0] <= UInt<3>("h05") + T_556[1] <= UInt<3>("h04") + node T_560 = eq(T_556[0], io.inner.grant.bits.g_type) + node T_561 = eq(T_556[1], io.inner.grant.bits.g_type) + node T_563 = or(UInt<1>("h00"), T_560) + node T_564 = or(T_563, T_561) + wire T_566 : UInt<1>[2] + T_566[0] <= UInt<1>("h00") + T_566[1] <= UInt<1>("h01") + node T_570 = eq(T_566[0], io.inner.grant.bits.g_type) + node T_571 = eq(T_566[1], io.inner.grant.bits.g_type) + node T_573 = or(UInt<1>("h00"), T_570) + node T_574 = or(T_573, T_571) + node pending_outer_read = mux(io.inner.grant.bits.is_builtin_type, T_564, T_574) + node T_594 = eq(UInt<3>("h06"), io.inner.acquire.bits.a_type) + node T_595 = mux(T_594, UInt<3>("h01"), UInt<3>("h03")) + node T_596 = eq(UInt<3>("h05"), io.inner.acquire.bits.a_type) + node T_597 = mux(T_596, UInt<3>("h01"), T_595) + node T_598 = eq(UInt<3>("h04"), io.inner.acquire.bits.a_type) + node T_599 = mux(T_598, UInt<3>("h04"), T_597) + node T_600 = eq(UInt<3>("h03"), io.inner.acquire.bits.a_type) + node T_601 = mux(T_600, UInt<3>("h03"), T_599) + node T_602 = eq(UInt<3>("h02"), io.inner.acquire.bits.a_type) + node T_603 = mux(T_602, UInt<3>("h03"), T_601) + node T_604 = eq(UInt<3>("h01"), io.inner.acquire.bits.a_type) + node T_605 = mux(T_604, UInt<3>("h05"), T_603) + node T_606 = eq(UInt<3>("h00"), io.inner.acquire.bits.a_type) + node T_607 = mux(T_606, UInt<3>("h04"), T_605) + node T_608 = eq(io.inner.acquire.bits.a_type, UInt<1>("h00")) + node T_611 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_612 = mux(T_611, UInt<1>("h00"), UInt<1>("h01")) + node T_613 = mux(T_608, T_612, UInt<1>("h01")) + node T_614 = mux(io.inner.acquire.bits.is_builtin_type, T_607, T_613) + wire T_623 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} + T_623 is invalid + T_623.client_id <= io.inner.acquire.bits.client_id + T_623.is_builtin_type <= io.inner.acquire.bits.is_builtin_type + T_623.g_type <= T_614 + T_623.client_xact_id <= io.inner.acquire.bits.client_xact_id + T_623.manager_xact_id <= UInt<3>("h07") + T_623.addr_beat <= UInt<1>("h00") + T_623.data <= UInt<1>("h00") + wire T_634 : UInt<3>[2] + T_634[0] <= UInt<3>("h05") + T_634[1] <= UInt<3>("h04") + node T_638 = eq(T_634[0], T_623.g_type) + node T_639 = eq(T_634[1], T_623.g_type) + node T_641 = or(UInt<1>("h00"), T_638) + node T_642 = or(T_641, T_639) + wire T_644 : UInt<1>[2] + T_644[0] <= UInt<1>("h00") + T_644[1] <= UInt<1>("h01") + node T_648 = eq(T_644[0], T_623.g_type) + node T_649 = eq(T_644[1], T_623.g_type) + node T_651 = or(UInt<1>("h00"), T_648) + node T_652 = or(T_651, T_649) + node pending_outer_read_ = mux(T_623.is_builtin_type, T_642, T_652) + wire T_658 : UInt<3>[3] + T_658[0] <= UInt<3>("h02") + T_658[1] <= UInt<3>("h00") + T_658[2] <= UInt<3>("h04") + node T_663 = eq(T_658[0], xact.a_type) + node T_664 = eq(T_658[1], xact.a_type) + node T_665 = eq(T_658[2], xact.a_type) + node T_667 = or(UInt<1>("h00"), T_663) + node T_668 = or(T_667, T_664) + node T_669 = or(T_668, T_665) + node subblock_type = and(xact.is_builtin_type, T_669) + node T_671 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) + node T_672 = neq(state, UInt<1>("h00")) + node T_673 = and(T_671, T_672) + node T_675 = eq(collect_iacq_data, UInt<1>("h00")) + node T_676 = and(T_673, T_675) + io.has_acquire_conflict <= T_676 + node T_677 = eq(xact.addr_block, io.inner.acquire.bits.addr_block) + node T_678 = and(T_677, collect_iacq_data) + io.has_acquire_match <= T_678 + node T_679 = eq(xact.addr_block, io.inner.release.bits.addr_block) + node T_681 = eq(io.inner.release.bits.voluntary, UInt<1>("h00")) + node T_682 = and(T_679, T_681) + node T_683 = eq(state, UInt<1>("h01")) + node T_684 = and(T_682, T_683) + io.has_release_match <= T_684 + node T_689 = asUInt(asSInt(UInt<16>("h0ffff"))) + node T_695 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_696 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_697 = cat(T_695, T_696) node T_699 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_700 = cat(T_698, T_699) - node T_702 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_703 = cat(UInt<3>("h07"), T_702) - node T_705 = cat(T_692, UInt<1>("h01")) - node T_707 = cat(T_692, UInt<1>("h01")) - node T_709 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_710 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_711 = cat(T_709, T_710) - node T_713 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_715 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_716 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_717 = mux(T_716, T_715, UInt<1>("h00")) - node T_718 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_719 = mux(T_718, T_713, T_717) - node T_720 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_721 = mux(T_720, T_711, T_719) - node T_722 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_723 = mux(T_722, T_707, T_721) - node T_724 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_725 = mux(T_724, T_705, T_723) - node T_726 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_727 = mux(T_726, T_703, T_725) - node T_728 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_729 = mux(T_728, T_700, T_727) + node T_700 = cat(UInt<3>("h07"), T_699) + node T_702 = cat(T_689, UInt<1>("h01")) + node T_704 = cat(T_689, UInt<1>("h01")) + node T_706 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_707 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_708 = cat(T_706, T_707) + node T_710 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_712 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_713 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_714 = mux(T_713, T_712, UInt<1>("h00")) + node T_715 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_716 = mux(T_715, T_710, T_714) + node T_717 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_718 = mux(T_717, T_708, T_716) + node T_719 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_720 = mux(T_719, T_704, T_718) + node T_721 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_722 = mux(T_721, T_702, T_720) + node T_723 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_724 = mux(T_723, T_700, T_722) + node T_725 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_726 = mux(T_725, T_697, T_724) wire oacq_probe : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_probe.data <= UInt<1>("h00") - oacq_probe.union <= UInt<1>("h00") - oacq_probe.a_type <= UInt<1>("h00") - oacq_probe.is_builtin_type <= UInt<1>("h00") - oacq_probe.addr_beat <= UInt<1>("h00") - oacq_probe.client_xact_id <= UInt<1>("h00") - oacq_probe.addr_block <= UInt<1>("h00") + oacq_probe is invalid oacq_probe.is_builtin_type <= UInt<1>("h01") oacq_probe.a_type <= UInt<3>("h03") oacq_probe.client_xact_id <= UInt<3>("h07") oacq_probe.addr_block <= io.inner.release.bits.addr_block oacq_probe.addr_beat <= io.inner.release.bits.addr_beat oacq_probe.data <= io.inner.release.bits.data - oacq_probe.union <= T_729 - node T_754 = bits(xact.union, 12, 9) - node T_755 = bits(T_754, 3, 3) - node T_757 = dshl(UInt<1>("h01"), T_755) - node T_759 = eq(xact.a_type, UInt<3>("h04")) - node T_760 = and(xact.is_builtin_type, T_759) - node T_761 = bit(T_757, 0) - node T_762 = bit(T_757, 1) - wire T_764 : UInt<1>[2] - T_764[0] <= T_761 - T_764[1] <= T_762 - node T_769 = subw(UInt<8>("h00"), T_764[0]) - node T_771 = subw(UInt<8>("h00"), T_764[1]) - wire T_773 : UInt<8>[2] - T_773[0] <= T_769 - T_773[1] <= T_771 - node T_777 = cat(T_773[1], T_773[0]) - node T_779 = eq(xact.a_type, UInt<3>("h03")) - node T_780 = and(xact.is_builtin_type, T_779) - node T_782 = eq(xact.a_type, UInt<3>("h02")) - node T_783 = and(xact.is_builtin_type, T_782) - node T_784 = or(T_780, T_783) - node T_785 = bits(xact.union, 16, 1) - node T_787 = mux(T_784, T_785, UInt<16>("h00")) - node T_788 = mux(T_760, T_777, T_787) - node T_796 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_797 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_798 = cat(T_796, T_797) + oacq_probe.union <= T_726 + node T_744 = bits(xact.union, 12, 9) + node T_745 = bits(T_744, 3, 3) + node T_747 = dshl(UInt<1>("h01"), T_745) + node T_749 = eq(xact.a_type, UInt<3>("h04")) + node T_750 = and(xact.is_builtin_type, T_749) + node T_751 = bits(T_747, 0, 0) + node T_752 = bits(T_747, 1, 1) + wire T_754 : UInt<1>[2] + T_754[0] <= T_751 + T_754[1] <= T_752 + node T_759 = sub(UInt<8>("h00"), T_754[0]) + node T_760 = tail(T_759, 1) + node T_762 = sub(UInt<8>("h00"), T_754[1]) + node T_763 = tail(T_762, 1) + wire T_765 : UInt<8>[2] + T_765[0] <= T_760 + T_765[1] <= T_763 + node T_769 = cat(T_765[1], T_765[0]) + node T_771 = eq(xact.a_type, UInt<3>("h03")) + node T_772 = and(xact.is_builtin_type, T_771) + node T_774 = eq(xact.a_type, UInt<3>("h02")) + node T_775 = and(xact.is_builtin_type, T_774) + node T_776 = or(T_772, T_775) + node T_777 = bits(xact.union, 16, 1) + node T_779 = mux(T_776, T_777, UInt<16>("h00")) + node T_780 = mux(T_750, T_769, T_779) + node T_788 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_789 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_790 = cat(T_788, T_789) + node T_792 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_793 = cat(UInt<3>("h07"), T_792) + node T_795 = cat(T_780, UInt<1>("h01")) + node T_797 = cat(T_780, UInt<1>("h01")) + node T_799 = cat(UInt<1>("h00"), UInt<3>("h07")) node T_800 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_801 = cat(UInt<3>("h07"), T_800) - node T_803 = cat(T_788, UInt<1>("h01")) - node T_805 = cat(T_788, UInt<1>("h01")) - node T_807 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_808 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_809 = cat(T_807, T_808) - node T_811 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_813 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_814 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_815 = mux(T_814, T_813, UInt<1>("h00")) - node T_816 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_817 = mux(T_816, T_811, T_815) - node T_818 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_819 = mux(T_818, T_809, T_817) - node T_820 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_821 = mux(T_820, T_805, T_819) - node T_822 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_823 = mux(T_822, T_803, T_821) - node T_824 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_825 = mux(T_824, T_801, T_823) - node T_826 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_827 = mux(T_826, T_798, T_825) + node T_801 = cat(T_799, T_800) + node T_803 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_805 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_806 = eq(UInt<3>("h06"), UInt<3>("h02")) + node T_807 = mux(T_806, T_805, UInt<1>("h00")) + node T_808 = eq(UInt<3>("h05"), UInt<3>("h02")) + node T_809 = mux(T_808, T_803, T_807) + node T_810 = eq(UInt<3>("h04"), UInt<3>("h02")) + node T_811 = mux(T_810, T_801, T_809) + node T_812 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_813 = mux(T_812, T_797, T_811) + node T_814 = eq(UInt<3>("h02"), UInt<3>("h02")) + node T_815 = mux(T_814, T_795, T_813) + node T_816 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_817 = mux(T_816, T_793, T_815) + node T_818 = eq(UInt<3>("h00"), UInt<3>("h02")) + node T_819 = mux(T_818, T_790, T_817) wire oacq_write_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_beat.data <= UInt<1>("h00") - oacq_write_beat.union <= UInt<1>("h00") - oacq_write_beat.a_type <= UInt<1>("h00") - oacq_write_beat.is_builtin_type <= UInt<1>("h00") - oacq_write_beat.addr_beat <= UInt<1>("h00") - oacq_write_beat.client_xact_id <= UInt<1>("h00") - oacq_write_beat.addr_block <= UInt<1>("h00") + oacq_write_beat is invalid oacq_write_beat.is_builtin_type <= UInt<1>("h01") oacq_write_beat.a_type <= UInt<3>("h02") oacq_write_beat.client_xact_id <= UInt<3>("h07") oacq_write_beat.addr_block <= xact.addr_block oacq_write_beat.addr_beat <= xact.addr_beat oacq_write_beat.data <= xact.data_buffer[0] - oacq_write_beat.union <= T_827 - node T_861 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_862 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_863 = cat(T_861, T_862) - node T_865 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_866 = cat(UInt<3>("h07"), T_865) - node T_868 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_870 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) - node T_872 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_873 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_874 = cat(T_872, T_873) - node T_876 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_878 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_879 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_880 = mux(T_879, T_878, UInt<1>("h00")) - node T_881 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_882 = mux(T_881, T_876, T_880) - node T_883 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_884 = mux(T_883, T_874, T_882) - node T_885 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_886 = mux(T_885, T_870, T_884) - node T_887 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_888 = mux(T_887, T_868, T_886) - node T_889 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_890 = mux(T_889, T_866, T_888) - node T_891 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_892 = mux(T_891, T_863, T_890) + oacq_write_beat.union <= T_819 + node T_846 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_847 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_848 = cat(T_846, T_847) + node T_850 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_851 = cat(UInt<3>("h07"), T_850) + node T_853 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) + node T_855 = cat(xact.wmask_buffer[oacq_data_cnt], UInt<1>("h01")) + node T_857 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_858 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_859 = cat(T_857, T_858) + node T_861 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_863 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_864 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_865 = mux(T_864, T_863, UInt<1>("h00")) + node T_866 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_867 = mux(T_866, T_861, T_865) + node T_868 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_869 = mux(T_868, T_859, T_867) + node T_870 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_871 = mux(T_870, T_855, T_869) + node T_872 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_873 = mux(T_872, T_853, T_871) + node T_874 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_875 = mux(T_874, T_851, T_873) + node T_876 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_877 = mux(T_876, T_848, T_875) wire oacq_write_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_write_block.data <= UInt<1>("h00") - oacq_write_block.union <= UInt<1>("h00") - oacq_write_block.a_type <= UInt<1>("h00") - oacq_write_block.is_builtin_type <= UInt<1>("h00") - oacq_write_block.addr_beat <= UInt<1>("h00") - oacq_write_block.client_xact_id <= UInt<1>("h00") - oacq_write_block.addr_block <= UInt<1>("h00") + oacq_write_block is invalid oacq_write_block.is_builtin_type <= UInt<1>("h01") oacq_write_block.a_type <= UInt<3>("h03") oacq_write_block.client_xact_id <= UInt<3>("h07") oacq_write_block.addr_block <= xact.addr_block oacq_write_block.addr_beat <= oacq_data_cnt oacq_write_block.data <= xact.data_buffer[oacq_data_cnt] - oacq_write_block.union <= T_892 - node T_917 = bits(xact.union, 12, 9) - node T_918 = bits(xact.union, 8, 6) - node T_926 = cat(T_917, T_918) - node T_927 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_928 = cat(T_926, T_927) - node T_930 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_931 = cat(T_918, T_930) - node T_933 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_935 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_937 = cat(T_917, T_918) - node T_938 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_939 = cat(T_937, T_938) - node T_941 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_943 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_944 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_945 = mux(T_944, T_943, UInt<1>("h00")) - node T_946 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_947 = mux(T_946, T_941, T_945) - node T_948 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_949 = mux(T_948, T_939, T_947) - node T_950 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_951 = mux(T_950, T_935, T_949) - node T_952 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_953 = mux(T_952, T_933, T_951) - node T_954 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_955 = mux(T_954, T_931, T_953) - node T_956 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_957 = mux(T_956, T_928, T_955) + oacq_write_block.union <= T_877 + node T_895 = bits(xact.union, 12, 9) + node T_896 = bits(xact.union, 8, 6) + node T_904 = cat(T_895, T_896) + node T_905 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_906 = cat(T_904, T_905) + node T_908 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_909 = cat(T_896, T_908) + node T_911 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_913 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_915 = cat(T_895, T_896) + node T_916 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_917 = cat(T_915, T_916) + node T_919 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_921 = cat(UInt<5>("h01"), UInt<1>("h00")) + node T_922 = eq(UInt<3>("h06"), UInt<3>("h00")) + node T_923 = mux(T_922, T_921, UInt<1>("h00")) + node T_924 = eq(UInt<3>("h05"), UInt<3>("h00")) + node T_925 = mux(T_924, T_919, T_923) + node T_926 = eq(UInt<3>("h04"), UInt<3>("h00")) + node T_927 = mux(T_926, T_917, T_925) + node T_928 = eq(UInt<3>("h03"), UInt<3>("h00")) + node T_929 = mux(T_928, T_913, T_927) + node T_930 = eq(UInt<3>("h02"), UInt<3>("h00")) + node T_931 = mux(T_930, T_911, T_929) + node T_932 = eq(UInt<3>("h01"), UInt<3>("h00")) + node T_933 = mux(T_932, T_909, T_931) + node T_934 = eq(UInt<3>("h00"), UInt<3>("h00")) + node T_935 = mux(T_934, T_906, T_933) wire oacq_read_beat : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= UInt<1>("h00") - oacq_read_beat.a_type <= UInt<1>("h00") - oacq_read_beat.is_builtin_type <= UInt<1>("h00") - oacq_read_beat.addr_beat <= UInt<1>("h00") - oacq_read_beat.client_xact_id <= UInt<1>("h00") - oacq_read_beat.addr_block <= UInt<1>("h00") + oacq_read_beat is invalid oacq_read_beat.is_builtin_type <= UInt<1>("h01") oacq_read_beat.a_type <= UInt<3>("h00") oacq_read_beat.client_xact_id <= UInt<3>("h07") oacq_read_beat.addr_block <= xact.addr_block oacq_read_beat.addr_beat <= xact.addr_beat oacq_read_beat.data <= UInt<1>("h00") - oacq_read_beat.union <= T_957 - node T_991 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_992 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_993 = cat(T_991, T_992) - node T_995 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_996 = cat(UInt<3>("h07"), T_995) - node T_998 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1000 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1002 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1003 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1004 = cat(T_1002, T_1003) - node T_1006 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1008 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1009 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_1010 = mux(T_1009, T_1008, UInt<1>("h00")) - node T_1011 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_1012 = mux(T_1011, T_1006, T_1010) - node T_1013 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_1014 = mux(T_1013, T_1004, T_1012) - node T_1015 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_1016 = mux(T_1015, T_1000, T_1014) - node T_1017 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_1018 = mux(T_1017, T_998, T_1016) - node T_1019 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_1020 = mux(T_1019, T_996, T_1018) - node T_1021 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_1022 = mux(T_1021, T_993, T_1020) + oacq_read_beat.union <= T_935 + node T_962 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_963 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_964 = cat(T_962, T_963) + node T_966 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_967 = cat(UInt<3>("h07"), T_966) + node T_969 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_971 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_973 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_974 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_975 = cat(T_973, T_974) + node T_977 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_979 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_980 = eq(UInt<3>("h06"), UInt<3>("h01")) + node T_981 = mux(T_980, T_979, UInt<1>("h00")) + node T_982 = eq(UInt<3>("h05"), UInt<3>("h01")) + node T_983 = mux(T_982, T_977, T_981) + node T_984 = eq(UInt<3>("h04"), UInt<3>("h01")) + node T_985 = mux(T_984, T_975, T_983) + node T_986 = eq(UInt<3>("h03"), UInt<3>("h01")) + node T_987 = mux(T_986, T_971, T_985) + node T_988 = eq(UInt<3>("h02"), UInt<3>("h01")) + node T_989 = mux(T_988, T_969, T_987) + node T_990 = eq(UInt<3>("h01"), UInt<3>("h01")) + node T_991 = mux(T_990, T_967, T_989) + node T_992 = eq(UInt<3>("h00"), UInt<3>("h01")) + node T_993 = mux(T_992, T_964, T_991) wire oacq_read_block : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= UInt<1>("h00") - oacq_read_block.a_type <= UInt<1>("h00") - oacq_read_block.is_builtin_type <= UInt<1>("h00") - oacq_read_block.addr_beat <= UInt<1>("h00") - oacq_read_block.client_xact_id <= UInt<1>("h00") - oacq_read_block.addr_block <= UInt<1>("h00") + oacq_read_block is invalid oacq_read_block.is_builtin_type <= UInt<1>("h01") oacq_read_block.a_type <= UInt<3>("h01") oacq_read_block.client_xact_id <= UInt<3>("h07") oacq_read_block.addr_block <= xact.addr_block oacq_read_block.addr_beat <= UInt<1>("h00") oacq_read_block.data <= UInt<1>("h00") - oacq_read_block.union <= T_1022 + oacq_read_block.union <= T_993 io.outer.acquire.valid <= UInt<1>("h00") - node T_1047 = eq(state, UInt<1>("h01")) - node T_1048 = eq(state, UInt<2>("h03")) - wire T_1057 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1057 <- oacq_write_block - when subblock_type : - T_1057 <- oacq_write_beat - skip - wire T_1073 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1073 <- oacq_read_block - when subblock_type : - T_1073 <- oacq_read_beat - skip - wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1089 <- T_1073 - when T_1048 : - T_1089 <- T_1057 - skip - wire T_1105 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>} - T_1105 <- T_1089 - when T_1047 : - T_1105 <- oacq_probe - skip - io.outer.acquire.bits <- T_1105 + node T_1011 = eq(state, UInt<1>("h01")) + node T_1012 = eq(state, UInt<2>("h03")) + node T_1013 = mux(subblock_type, oacq_write_beat, oacq_write_block) + node T_1021 = mux(subblock_type, oacq_read_beat, oacq_read_block) + node T_1029 = mux(T_1012, T_1013, T_1021) + node T_1037 = mux(T_1011, oacq_probe, T_1029) + io.outer.acquire.bits <- T_1037 io.outer.grant.ready <= UInt<1>("h00") io.inner.probe.valid <= UInt<1>("h00") - node T_1122 = eq(UInt<3>("h04"), xact.a_type) - node T_1123 = mux(T_1122, UInt<1>("h00"), UInt<2>("h02")) - node T_1124 = eq(UInt<3>("h06"), xact.a_type) - node T_1125 = mux(T_1124, UInt<1>("h00"), T_1123) - node T_1126 = eq(UInt<3>("h05"), xact.a_type) - node T_1127 = mux(T_1126, UInt<2>("h02"), T_1125) - node T_1128 = eq(UInt<3>("h02"), xact.a_type) - node T_1129 = mux(T_1128, UInt<1>("h00"), T_1127) - node T_1130 = eq(UInt<3>("h00"), xact.a_type) - node T_1131 = mux(T_1130, UInt<2>("h02"), T_1129) - node T_1132 = eq(UInt<3>("h03"), xact.a_type) - node T_1133 = mux(T_1132, UInt<1>("h00"), T_1131) - node T_1134 = eq(UInt<3>("h01"), xact.a_type) - node T_1135 = mux(T_1134, UInt<2>("h02"), T_1133) - node T_1136 = eq(UInt<1>("h01"), xact.a_type) - node T_1137 = mux(T_1136, UInt<1>("h00"), UInt<2>("h02")) - node T_1138 = eq(UInt<1>("h00"), xact.a_type) - node T_1139 = mux(T_1138, UInt<1>("h01"), T_1137) - node T_1140 = mux(xact.is_builtin_type, T_1135, T_1139) - wire T_1145 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} - T_1145.client_id <= UInt<1>("h00") - T_1145.p_type <= UInt<1>("h00") - T_1145.addr_block <= UInt<1>("h00") - T_1145.client_id <= UInt<1>("h00") - T_1145.p_type <= T_1140 - T_1145.addr_block <= xact.addr_block - io.inner.probe.bits <- T_1145 + node T_1054 = eq(UInt<3>("h04"), xact.a_type) + node T_1055 = mux(T_1054, UInt<1>("h00"), UInt<2>("h02")) + node T_1056 = eq(UInt<3>("h06"), xact.a_type) + node T_1057 = mux(T_1056, UInt<1>("h00"), T_1055) + node T_1058 = eq(UInt<3>("h05"), xact.a_type) + node T_1059 = mux(T_1058, UInt<2>("h02"), T_1057) + node T_1060 = eq(UInt<3>("h02"), xact.a_type) + node T_1061 = mux(T_1060, UInt<1>("h00"), T_1059) + node T_1062 = eq(UInt<3>("h00"), xact.a_type) + node T_1063 = mux(T_1062, UInt<2>("h02"), T_1061) + node T_1064 = eq(UInt<3>("h03"), xact.a_type) + node T_1065 = mux(T_1064, UInt<1>("h00"), T_1063) + node T_1066 = eq(UInt<3>("h01"), xact.a_type) + node T_1067 = mux(T_1066, UInt<2>("h02"), T_1065) + node T_1068 = eq(UInt<1>("h01"), xact.a_type) + node T_1069 = mux(T_1068, UInt<1>("h00"), UInt<2>("h02")) + node T_1070 = eq(UInt<1>("h00"), xact.a_type) + node T_1071 = mux(T_1070, UInt<1>("h01"), T_1069) + node T_1072 = mux(xact.is_builtin_type, T_1067, T_1071) + wire T_1077 : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>} + T_1077 is invalid + T_1077.client_id <= UInt<1>("h00") + T_1077.p_type <= T_1072 + T_1077.addr_block <= xact.addr_block + io.inner.probe.bits <- T_1077 io.inner.grant.valid <= UInt<1>("h00") - node T_1171 = eq(UInt<3>("h06"), xact.a_type) - node T_1172 = mux(T_1171, UInt<3>("h01"), UInt<3>("h03")) - node T_1173 = eq(UInt<3>("h05"), xact.a_type) - node T_1174 = mux(T_1173, UInt<3>("h01"), T_1172) - node T_1175 = eq(UInt<3>("h04"), xact.a_type) - node T_1176 = mux(T_1175, UInt<3>("h04"), T_1174) - node T_1177 = eq(UInt<3>("h03"), xact.a_type) - node T_1178 = mux(T_1177, UInt<3>("h03"), T_1176) - node T_1179 = eq(UInt<3>("h02"), xact.a_type) - node T_1180 = mux(T_1179, UInt<3>("h03"), T_1178) - node T_1181 = eq(UInt<3>("h01"), xact.a_type) - node T_1182 = mux(T_1181, UInt<3>("h05"), T_1180) - node T_1183 = eq(UInt<3>("h00"), xact.a_type) - node T_1184 = mux(T_1183, UInt<3>("h04"), T_1182) - node T_1185 = eq(xact.a_type, UInt<1>("h00")) - node T_1188 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1189 = mux(T_1188, UInt<1>("h00"), UInt<1>("h01")) - node T_1190 = mux(T_1185, T_1189, UInt<1>("h01")) - node T_1191 = mux(xact.is_builtin_type, T_1184, T_1190) - wire T_1200 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} - T_1200.client_id <= UInt<1>("h00") - T_1200.data <= UInt<1>("h00") - T_1200.g_type <= UInt<1>("h00") - T_1200.is_builtin_type <= UInt<1>("h00") - T_1200.manager_xact_id <= UInt<1>("h00") - T_1200.client_xact_id <= UInt<1>("h00") - T_1200.addr_beat <= UInt<1>("h00") - T_1200.client_id <= xact.client_id - T_1200.is_builtin_type <= xact.is_builtin_type - T_1200.g_type <= T_1191 - T_1200.client_xact_id <= xact.client_xact_id - T_1200.manager_xact_id <= UInt<3>("h07") - T_1200.addr_beat <= UInt<1>("h00") - T_1200.data <= UInt<1>("h00") - io.inner.grant.bits <- T_1200 + node T_1100 = eq(UInt<3>("h06"), xact.a_type) + node T_1101 = mux(T_1100, UInt<3>("h01"), UInt<3>("h03")) + node T_1102 = eq(UInt<3>("h05"), xact.a_type) + node T_1103 = mux(T_1102, UInt<3>("h01"), T_1101) + node T_1104 = eq(UInt<3>("h04"), xact.a_type) + node T_1105 = mux(T_1104, UInt<3>("h04"), T_1103) + node T_1106 = eq(UInt<3>("h03"), xact.a_type) + node T_1107 = mux(T_1106, UInt<3>("h03"), T_1105) + node T_1108 = eq(UInt<3>("h02"), xact.a_type) + node T_1109 = mux(T_1108, UInt<3>("h03"), T_1107) + node T_1110 = eq(UInt<3>("h01"), xact.a_type) + node T_1111 = mux(T_1110, UInt<3>("h05"), T_1109) + node T_1112 = eq(UInt<3>("h00"), xact.a_type) + node T_1113 = mux(T_1112, UInt<3>("h04"), T_1111) + node T_1114 = eq(xact.a_type, UInt<1>("h00")) + node T_1117 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1118 = mux(T_1117, UInt<1>("h00"), UInt<1>("h01")) + node T_1119 = mux(T_1114, T_1118, UInt<1>("h01")) + node T_1120 = mux(xact.is_builtin_type, T_1113, T_1119) + wire T_1129 : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>} + T_1129 is invalid + T_1129.client_id <= xact.client_id + T_1129.is_builtin_type <= xact.is_builtin_type + T_1129.g_type <= T_1120 + T_1129.client_xact_id <= xact.client_xact_id + T_1129.manager_xact_id <= UInt<3>("h07") + T_1129.addr_beat <= UInt<1>("h00") + T_1129.data <= UInt<1>("h00") + io.inner.grant.bits <- T_1129 io.inner.acquire.ready <= UInt<1>("h00") io.inner.release.ready <= UInt<1>("h00") io.inner.finish.ready <= UInt<1>("h00") - node T_1218 = neq(state, UInt<1>("h00")) - node T_1219 = and(T_1218, collect_iacq_data) - node T_1220 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1221 = and(T_1219, T_1220) - node T_1222 = neq(io.inner.acquire.bits.client_id, xact.client_id) - node T_1223 = and(T_1221, T_1222) - node T_1225 = eq(T_1223, UInt<1>("h00")) - node T_1227 = eq(reset, UInt<1>("h00")) - when T_1227 : - node T_1229 = eq(T_1225, UInt<1>("h00")) - when T_1229 : - node T_1231 = eq(reset, UInt<1>("h00")) - when T_1231 : + node T_1140 = neq(state, UInt<1>("h00")) + node T_1141 = and(T_1140, collect_iacq_data) + node T_1142 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1143 = and(T_1141, T_1142) + node T_1144 = neq(io.inner.acquire.bits.client_id, xact.client_id) + node T_1145 = and(T_1143, T_1144) + node T_1147 = eq(T_1145, UInt<1>("h00")) + node T_1149 = eq(reset, UInt<1>("h00")) + when T_1149 : + node T_1151 = eq(T_1147, UInt<1>("h00")) + when T_1151 : + node T_1153 = eq(reset, UInt<1>("h00")) + when T_1153 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1232 = neq(state, UInt<1>("h00")) - node T_1233 = and(T_1232, collect_iacq_data) - node T_1234 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1235 = and(T_1233, T_1234) - node T_1236 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) - node T_1237 = and(T_1235, T_1236) - node T_1239 = eq(T_1237, UInt<1>("h00")) - node T_1241 = eq(reset, UInt<1>("h00")) - when T_1241 : - node T_1243 = eq(T_1239, UInt<1>("h00")) - when T_1243 : - node T_1245 = eq(reset, UInt<1>("h00")) - when T_1245 : + node T_1154 = neq(state, UInt<1>("h00")) + node T_1155 = and(T_1154, collect_iacq_data) + node T_1156 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1157 = and(T_1155, T_1156) + node T_1158 = neq(io.inner.acquire.bits.client_xact_id, xact.client_xact_id) + node T_1159 = and(T_1157, T_1158) + node T_1161 = eq(T_1159, UInt<1>("h00")) + node T_1163 = eq(reset, UInt<1>("h00")) + when T_1163 : + node T_1165 = eq(T_1161, UInt<1>("h00")) + when T_1165 : + node T_1167 = eq(reset, UInt<1>("h00")) + when T_1167 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request.") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1246 = eq(state, UInt<1>("h00")) - node T_1247 = and(io.inner.acquire.ready, io.inner.acquire.valid) - node T_1248 = and(T_1246, T_1247) - node T_1250 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1253 : UInt<3>[1] - T_1253[0] <= UInt<3>("h03") - node T_1256 = eq(T_1253[0], io.inner.acquire.bits.a_type) - node T_1258 = or(UInt<1>("h00"), T_1256) - node T_1259 = and(T_1250, T_1258) - node T_1260 = and(T_1248, T_1259) - node T_1262 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) - node T_1263 = and(T_1260, T_1262) - node T_1265 = eq(T_1263, UInt<1>("h00")) - node T_1267 = eq(reset, UInt<1>("h00")) - when T_1267 : - node T_1269 = eq(T_1265, UInt<1>("h00")) - when T_1269 : - node T_1271 = eq(reset, UInt<1>("h00")) - when T_1271 : + node T_1168 = eq(state, UInt<1>("h00")) + node T_1169 = and(io.inner.acquire.ready, io.inner.acquire.valid) + node T_1170 = and(T_1168, T_1169) + node T_1172 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_1175 : UInt<3>[1] + T_1175[0] <= UInt<3>("h03") + node T_1178 = eq(T_1175[0], io.inner.acquire.bits.a_type) + node T_1180 = or(UInt<1>("h00"), T_1178) + node T_1181 = and(T_1172, T_1180) + node T_1182 = and(T_1170, T_1181) + node T_1184 = neq(io.inner.acquire.bits.addr_beat, UInt<1>("h00")) + node T_1185 = and(T_1182, T_1184) + node T_1187 = eq(T_1185, UInt<1>("h00")) + node T_1189 = eq(reset, UInt<1>("h00")) + when T_1189 : + node T_1191 = eq(T_1187, UInt<1>("h00")) + when T_1191 : + node T_1193 = eq(reset, UInt<1>("h00")) + when T_1193 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat.") skip stop(clk, UInt<1>(1), 1) @@ -9257,38 +7699,40 @@ circuit Top : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact.data_buffer[io.inner.acquire.bits.addr_beat] <= io.inner.acquire.bits.data - node T_1275 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1276 = bits(T_1275, 3, 3) - node T_1278 = dshl(UInt<1>("h01"), T_1276) - node T_1280 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1281 = and(io.inner.acquire.bits.is_builtin_type, T_1280) - node T_1282 = bit(T_1278, 0) - node T_1283 = bit(T_1278, 1) - wire T_1285 : UInt<1>[2] - T_1285[0] <= T_1282 - T_1285[1] <= T_1283 - node T_1290 = subw(UInt<8>("h00"), T_1285[0]) - node T_1292 = subw(UInt<8>("h00"), T_1285[1]) - wire T_1294 : UInt<8>[2] - T_1294[0] <= T_1290 - T_1294[1] <= T_1292 - node T_1298 = cat(T_1294[1], T_1294[0]) - node T_1300 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1301 = and(io.inner.acquire.bits.is_builtin_type, T_1300) - node T_1303 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1304 = and(io.inner.acquire.bits.is_builtin_type, T_1303) - node T_1305 = or(T_1301, T_1304) - node T_1306 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1308 = mux(T_1305, T_1306, UInt<16>("h00")) - node T_1309 = mux(T_1281, T_1298, T_1308) - xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1309 - node T_1312 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) - node T_1313 = or(iacq_data_valid, T_1312) - node T_1314 = not(iacq_data_valid) - node T_1315 = or(T_1314, T_1312) - node T_1316 = not(T_1315) - node T_1317 = mux(UInt<1>("h01"), T_1313, T_1316) - iacq_data_valid <= T_1317 + node T_1197 = bits(io.inner.acquire.bits.union, 12, 9) + node T_1198 = bits(T_1197, 3, 3) + node T_1200 = dshl(UInt<1>("h01"), T_1198) + node T_1202 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) + node T_1203 = and(io.inner.acquire.bits.is_builtin_type, T_1202) + node T_1204 = bits(T_1200, 0, 0) + node T_1205 = bits(T_1200, 1, 1) + wire T_1207 : UInt<1>[2] + T_1207[0] <= T_1204 + T_1207[1] <= T_1205 + node T_1212 = sub(UInt<8>("h00"), T_1207[0]) + node T_1213 = tail(T_1212, 1) + node T_1215 = sub(UInt<8>("h00"), T_1207[1]) + node T_1216 = tail(T_1215, 1) + wire T_1218 : UInt<8>[2] + T_1218[0] <= T_1213 + T_1218[1] <= T_1216 + node T_1222 = cat(T_1218[1], T_1218[0]) + node T_1224 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) + node T_1225 = and(io.inner.acquire.bits.is_builtin_type, T_1224) + node T_1227 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) + node T_1228 = and(io.inner.acquire.bits.is_builtin_type, T_1227) + node T_1229 = or(T_1225, T_1228) + node T_1230 = bits(io.inner.acquire.bits.union, 16, 1) + node T_1232 = mux(T_1229, T_1230, UInt<16>("h00")) + node T_1233 = mux(T_1203, T_1222, T_1232) + xact.wmask_buffer[io.inner.acquire.bits.addr_beat] <= T_1233 + node T_1236 = dshl(UInt<1>("h01"), io.inner.acquire.bits.addr_beat) + node T_1237 = or(iacq_data_valid, T_1236) + node T_1238 = not(iacq_data_valid) + node T_1239 = or(T_1238, T_1236) + node T_1240 = not(T_1239) + node T_1241 = mux(UInt<1>("h01"), T_1237, T_1240) + iacq_data_valid <= T_1241 skip when iacq_data_done : collect_iacq_data <= UInt<1>("h00") @@ -9300,194 +7744,201 @@ circuit Top : pending_ognt_ack <= UInt<1>("h00") skip skip - node T_1321 = eq(UInt<1>("h00"), state) - when T_1321 : + node T_1245 = eq(UInt<1>("h00"), state) + when T_1245 : io.inner.acquire.ready <= UInt<1>("h01") when io.inner.acquire.valid : xact <- io.inner.acquire.bits xact.data_buffer[UInt<1>("h00")] <= io.inner.acquire.bits.data - node T_1327 = bits(io.inner.acquire.bits.union, 12, 9) - node T_1328 = bits(T_1327, 3, 3) - node T_1330 = dshl(UInt<1>("h01"), T_1328) - node T_1332 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) - node T_1333 = and(io.inner.acquire.bits.is_builtin_type, T_1332) - node T_1334 = bit(T_1330, 0) - node T_1335 = bit(T_1330, 1) - wire T_1337 : UInt<1>[2] - T_1337[0] <= T_1334 - T_1337[1] <= T_1335 - node T_1342 = subw(UInt<8>("h00"), T_1337[0]) - node T_1344 = subw(UInt<8>("h00"), T_1337[1]) - wire T_1346 : UInt<8>[2] - T_1346[0] <= T_1342 - T_1346[1] <= T_1344 - node T_1350 = cat(T_1346[1], T_1346[0]) - node T_1352 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) - node T_1353 = and(io.inner.acquire.bits.is_builtin_type, T_1352) - node T_1355 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) - node T_1356 = and(io.inner.acquire.bits.is_builtin_type, T_1355) - node T_1357 = or(T_1353, T_1356) - node T_1358 = bits(io.inner.acquire.bits.union, 16, 1) - node T_1360 = mux(T_1357, T_1358, UInt<16>("h00")) - node T_1361 = mux(T_1333, T_1350, T_1360) - xact.wmask_buffer[UInt<1>("h00")] <= T_1361 - node T_1363 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) - wire T_1366 : UInt<3>[1] - T_1366[0] <= UInt<3>("h03") - node T_1369 = eq(T_1366[0], io.inner.acquire.bits.a_type) - node T_1371 = or(UInt<1>("h00"), T_1369) - node T_1372 = and(T_1363, T_1371) - collect_iacq_data <= T_1372 - wire T_1377 : UInt<3>[3] - T_1377[0] <= UInt<3>("h02") - T_1377[1] <= UInt<3>("h03") - T_1377[2] <= UInt<3>("h04") - node T_1382 = eq(T_1377[0], io.inner.acquire.bits.a_type) - node T_1383 = eq(T_1377[1], io.inner.acquire.bits.a_type) - node T_1384 = eq(T_1377[2], io.inner.acquire.bits.a_type) - node T_1386 = or(UInt<1>("h00"), T_1382) - node T_1387 = or(T_1386, T_1383) - node T_1388 = or(T_1387, T_1384) - node T_1389 = and(io.inner.acquire.bits.is_builtin_type, T_1388) - node T_1390 = dshl(T_1389, io.inner.acquire.bits.addr_beat) - iacq_data_valid <= T_1390 - node T_1392 = neq(mask_incoherent, UInt<1>("h00")) - when T_1392 : + node T_1251 = bits(io.inner.acquire.bits.union, 12, 9) + node T_1252 = bits(T_1251, 3, 3) + node T_1254 = dshl(UInt<1>("h01"), T_1252) + node T_1256 = eq(io.inner.acquire.bits.a_type, UInt<3>("h04")) + node T_1257 = and(io.inner.acquire.bits.is_builtin_type, T_1256) + node T_1258 = bits(T_1254, 0, 0) + node T_1259 = bits(T_1254, 1, 1) + wire T_1261 : UInt<1>[2] + T_1261[0] <= T_1258 + T_1261[1] <= T_1259 + node T_1266 = sub(UInt<8>("h00"), T_1261[0]) + node T_1267 = tail(T_1266, 1) + node T_1269 = sub(UInt<8>("h00"), T_1261[1]) + node T_1270 = tail(T_1269, 1) + wire T_1272 : UInt<8>[2] + T_1272[0] <= T_1267 + T_1272[1] <= T_1270 + node T_1276 = cat(T_1272[1], T_1272[0]) + node T_1278 = eq(io.inner.acquire.bits.a_type, UInt<3>("h03")) + node T_1279 = and(io.inner.acquire.bits.is_builtin_type, T_1278) + node T_1281 = eq(io.inner.acquire.bits.a_type, UInt<3>("h02")) + node T_1282 = and(io.inner.acquire.bits.is_builtin_type, T_1281) + node T_1283 = or(T_1279, T_1282) + node T_1284 = bits(io.inner.acquire.bits.union, 16, 1) + node T_1286 = mux(T_1283, T_1284, UInt<16>("h00")) + node T_1287 = mux(T_1257, T_1276, T_1286) + xact.wmask_buffer[UInt<1>("h00")] <= T_1287 + node T_1289 = and(UInt<1>("h01"), io.inner.acquire.bits.is_builtin_type) + wire T_1292 : UInt<3>[1] + T_1292[0] <= UInt<3>("h03") + node T_1295 = eq(T_1292[0], io.inner.acquire.bits.a_type) + node T_1297 = or(UInt<1>("h00"), T_1295) + node T_1298 = and(T_1289, T_1297) + collect_iacq_data <= T_1298 + wire T_1303 : UInt<3>[3] + T_1303[0] <= UInt<3>("h02") + T_1303[1] <= UInt<3>("h03") + T_1303[2] <= UInt<3>("h04") + node T_1308 = eq(T_1303[0], io.inner.acquire.bits.a_type) + node T_1309 = eq(T_1303[1], io.inner.acquire.bits.a_type) + node T_1310 = eq(T_1303[2], io.inner.acquire.bits.a_type) + node T_1312 = or(UInt<1>("h00"), T_1308) + node T_1313 = or(T_1312, T_1309) + node T_1314 = or(T_1313, T_1310) + node T_1315 = and(io.inner.acquire.bits.is_builtin_type, T_1314) + node T_1316 = dshl(T_1315, io.inner.acquire.bits.addr_beat) + iacq_data_valid <= T_1316 + node T_1318 = neq(mask_incoherent, UInt<1>("h00")) + when T_1318 : pending_probes <= mask_incoherent - node T_1393 = bit(mask_incoherent, 0) - node T_1394 = bit(mask_incoherent, 1) - node T_1395 = bit(mask_incoherent, 2) - node T_1396 = bit(mask_incoherent, 3) - node T_1398 = cat(UInt<1>("h00"), T_1394) - node T_1399 = addw(T_1393, T_1398) - node T_1402 = cat(UInt<1>("h00"), T_1396) - node T_1403 = addw(T_1395, T_1402) - node T_1404 = cat(UInt<1>("h00"), T_1403) - node T_1405 = addw(T_1399, T_1404) - release_count <= T_1405 + node T_1319 = bits(mask_incoherent, 0, 0) + node T_1320 = bits(mask_incoherent, 1, 1) + node T_1321 = bits(mask_incoherent, 2, 2) + node T_1322 = bits(mask_incoherent, 3, 3) + node T_1324 = cat(UInt<1>("h00"), T_1320) + node T_1325 = add(T_1319, T_1324) + node T_1326 = tail(T_1325, 1) + node T_1329 = cat(UInt<1>("h00"), T_1322) + node T_1330 = add(T_1321, T_1329) + node T_1331 = tail(T_1330, 1) + node T_1332 = cat(UInt<1>("h00"), T_1331) + node T_1333 = add(T_1326, T_1332) + node T_1334 = tail(T_1333, 1) + release_count <= T_1334 skip - node T_1406 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) - node T_1407 = mux(pending_outer_write_, UInt<2>("h03"), T_1406) - node T_1408 = mux(T_1392, UInt<1>("h01"), T_1407) - state <= T_1408 + node T_1335 = mux(pending_outer_read_, UInt<2>("h02"), UInt<3>("h04")) + node T_1336 = mux(pending_outer_write_, UInt<2>("h03"), T_1335) + node T_1337 = mux(T_1318, UInt<1>("h01"), T_1336) + state <= T_1337 skip skip - node T_1409 = eq(UInt<1>("h01"), state) - when T_1409 : - node T_1411 = neq(pending_probes, UInt<1>("h00")) - io.inner.probe.valid <= T_1411 + node T_1338 = eq(UInt<1>("h01"), state) + when T_1338 : + node T_1340 = neq(pending_probes, UInt<1>("h00")) + io.inner.probe.valid <= T_1340 when io.inner.probe.ready : - node T_1413 = dshl(UInt<1>("h01"), UInt<1>("h00")) - node T_1414 = not(T_1413) - node T_1415 = and(pending_probes, T_1414) - pending_probes <= T_1415 - skip - wire T_1417 : UInt<2>[3] - T_1417[0] <= UInt<1>("h00") - T_1417[1] <= UInt<1>("h01") - T_1417[2] <= UInt<2>("h02") - node T_1422 = eq(T_1417[0], io.inner.release.bits.r_type) - node T_1423 = eq(T_1417[1], io.inner.release.bits.r_type) - node T_1424 = eq(T_1417[2], io.inner.release.bits.r_type) - node T_1426 = or(UInt<1>("h00"), T_1422) - node T_1427 = or(T_1426, T_1423) - node T_1428 = or(T_1427, T_1424) - node T_1430 = eq(T_1428, UInt<1>("h00")) - node T_1431 = or(T_1430, io.outer.acquire.ready) - io.inner.release.ready <= T_1431 + node T_1342 = dshl(UInt<1>("h01"), UInt<1>("h00")) + node T_1343 = not(T_1342) + node T_1344 = and(pending_probes, T_1343) + pending_probes <= T_1344 + skip + wire T_1346 : UInt<2>[3] + T_1346[0] <= UInt<1>("h00") + T_1346[1] <= UInt<1>("h01") + T_1346[2] <= UInt<2>("h02") + node T_1351 = eq(T_1346[0], io.inner.release.bits.r_type) + node T_1352 = eq(T_1346[1], io.inner.release.bits.r_type) + node T_1353 = eq(T_1346[2], io.inner.release.bits.r_type) + node T_1355 = or(UInt<1>("h00"), T_1351) + node T_1356 = or(T_1355, T_1352) + node T_1357 = or(T_1356, T_1353) + node T_1359 = eq(T_1357, UInt<1>("h00")) + node T_1360 = or(T_1359, io.outer.acquire.ready) + io.inner.release.ready <= T_1360 when io.inner.release.valid : - wire T_1433 : UInt<2>[3] - T_1433[0] <= UInt<1>("h00") - T_1433[1] <= UInt<1>("h01") - T_1433[2] <= UInt<2>("h02") - node T_1438 = eq(T_1433[0], io.inner.release.bits.r_type) - node T_1439 = eq(T_1433[1], io.inner.release.bits.r_type) - node T_1440 = eq(T_1433[2], io.inner.release.bits.r_type) - node T_1442 = or(UInt<1>("h00"), T_1438) - node T_1443 = or(T_1442, T_1439) - node T_1444 = or(T_1443, T_1440) - when T_1444 : + wire T_1362 : UInt<2>[3] + T_1362[0] <= UInt<1>("h00") + T_1362[1] <= UInt<1>("h01") + T_1362[2] <= UInt<2>("h02") + node T_1367 = eq(T_1362[0], io.inner.release.bits.r_type) + node T_1368 = eq(T_1362[1], io.inner.release.bits.r_type) + node T_1369 = eq(T_1362[2], io.inner.release.bits.r_type) + node T_1371 = or(UInt<1>("h00"), T_1367) + node T_1372 = or(T_1371, T_1368) + node T_1373 = or(T_1372, T_1369) + when T_1373 : io.outer.acquire.valid <= UInt<1>("h01") when io.outer.acquire.ready : when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") - node T_1448 = subw(release_count, UInt<1>("h01")) - release_count <= T_1448 - node T_1450 = eq(release_count, UInt<1>("h01")) - when T_1450 : - node T_1451 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1452 = mux(pending_outer_write, UInt<2>("h03"), T_1451) - state <= T_1452 + node T_1377 = sub(release_count, UInt<1>("h01")) + node T_1378 = tail(T_1377, 1) + release_count <= T_1378 + node T_1380 = eq(release_count, UInt<1>("h01")) + when T_1380 : + node T_1381 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_1382 = mux(pending_outer_write, UInt<2>("h03"), T_1381) + state <= T_1382 skip skip skip skip - node T_1454 = eq(T_1444, UInt<1>("h00")) - when T_1454 : - node T_1456 = subw(release_count, UInt<1>("h01")) - release_count <= T_1456 - node T_1458 = eq(release_count, UInt<1>("h01")) - when T_1458 : - node T_1459 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) - node T_1460 = mux(pending_outer_write, UInt<2>("h03"), T_1459) - state <= T_1460 + node T_1384 = eq(T_1373, UInt<1>("h00")) + when T_1384 : + node T_1386 = sub(release_count, UInt<1>("h01")) + node T_1387 = tail(T_1386, 1) + release_count <= T_1387 + node T_1389 = eq(release_count, UInt<1>("h01")) + when T_1389 : + node T_1390 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h04")) + node T_1391 = mux(pending_outer_write, UInt<2>("h03"), T_1390) + state <= T_1391 skip skip skip skip - node T_1461 = eq(UInt<2>("h03"), state) - when T_1461 : - node T_1463 = eq(pending_ognt_ack, UInt<1>("h00")) - node T_1465 = eq(collect_iacq_data, UInt<1>("h00")) - node T_1466 = dshr(iacq_data_valid, oacq_data_cnt) - node T_1467 = bit(T_1466, 0) - node T_1468 = or(T_1465, T_1467) - node T_1469 = and(T_1463, T_1468) - io.outer.acquire.valid <= T_1469 + node T_1392 = eq(UInt<2>("h03"), state) + when T_1392 : + node T_1394 = eq(pending_ognt_ack, UInt<1>("h00")) + node T_1396 = eq(collect_iacq_data, UInt<1>("h00")) + node T_1397 = dshr(iacq_data_valid, oacq_data_cnt) + node T_1398 = bits(T_1397, 0, 0) + node T_1399 = or(T_1396, T_1398) + node T_1400 = and(T_1394, T_1399) + io.outer.acquire.valid <= T_1400 when oacq_data_done : pending_ognt_ack <= UInt<1>("h01") - node T_1471 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) - state <= T_1471 + node T_1402 = mux(pending_outer_read, UInt<2>("h02"), UInt<3>("h05")) + state <= T_1402 skip skip - node T_1472 = eq(UInt<2>("h02"), state) - when T_1472 : - node T_1474 = eq(pending_ognt_ack, UInt<1>("h00")) - io.outer.acquire.valid <= T_1474 - node T_1475 = and(io.outer.acquire.ready, io.outer.acquire.valid) - when T_1475 : + node T_1403 = eq(UInt<2>("h02"), state) + when T_1403 : + node T_1405 = eq(pending_ognt_ack, UInt<1>("h00")) + io.outer.acquire.valid <= T_1405 + node T_1406 = and(io.outer.acquire.ready, io.outer.acquire.valid) + when T_1406 : state <= UInt<3>("h05") skip skip - node T_1476 = eq(UInt<3>("h05"), state) - when T_1476 : + node T_1407 = eq(UInt<3>("h05"), state) + when T_1407 : io.outer.grant.ready <= io.inner.grant.ready io.inner.grant.valid <= io.outer.grant.valid when ignt_data_done : - node T_1479 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1481 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1482 = and(io.inner.grant.bits.is_builtin_type, T_1481) - node T_1484 = eq(T_1482, UInt<1>("h00")) - node T_1485 = and(T_1479, T_1484) - node T_1486 = mux(T_1485, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1486 + node T_1410 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1412 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) + node T_1413 = and(io.inner.grant.bits.is_builtin_type, T_1412) + node T_1415 = eq(T_1413, UInt<1>("h00")) + node T_1416 = and(T_1410, T_1415) + node T_1417 = mux(T_1416, UInt<3>("h06"), UInt<1>("h00")) + state <= T_1417 skip skip - node T_1487 = eq(UInt<3>("h04"), state) - when T_1487 : + node T_1418 = eq(UInt<3>("h04"), state) + when T_1418 : io.inner.grant.valid <= UInt<1>("h01") when io.inner.grant.ready : - node T_1491 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1493 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) - node T_1494 = and(io.inner.grant.bits.is_builtin_type, T_1493) - node T_1496 = eq(T_1494, UInt<1>("h00")) - node T_1497 = and(T_1491, T_1496) - node T_1498 = mux(T_1497, UInt<3>("h06"), UInt<1>("h00")) - state <= T_1498 + node T_1422 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1424 = eq(io.inner.grant.bits.g_type, UInt<3>("h00")) + node T_1425 = and(io.inner.grant.bits.is_builtin_type, T_1424) + node T_1427 = eq(T_1425, UInt<1>("h00")) + node T_1428 = and(T_1422, T_1427) + node T_1429 = mux(T_1428, UInt<3>("h06"), UInt<1>("h00")) + state <= T_1429 skip skip - node T_1499 = eq(UInt<3>("h06"), state) - when T_1499 : + node T_1430 = eq(UInt<3>("h06"), state) + when T_1430 : io.inner.finish.ready <= UInt<1>("h01") when io.inner.finish.valid : state <= UInt<1>("h00") @@ -9499,241 +7950,226 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, chosen : UInt<3>} - io.chosen <= UInt<1>("h00") - io.out.bits.client_id <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.bits.g_type <= UInt<1>("h00") - io.out.bits.is_builtin_type <= UInt<1>("h00") - io.out.bits.manager_xact_id <= UInt<1>("h00") - io.out.bits.client_xact_id <= UInt<1>("h00") - io.out.bits.addr_beat <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") - io.in[2].ready <= UInt<1>("h00") - io.in[3].ready <= UInt<1>("h00") - io.in[4].ready <= UInt<1>("h00") - io.in[5].ready <= UInt<1>("h00") - io.in[6].ready <= UInt<1>("h00") - io.in[7].ready <= UInt<1>("h00") - reg T_1502 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_1504 : UInt<?>, clk, reset, UInt<3>("h07") + io is invalid + reg T_1502 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_1504 : UInt<?>, clk with : (reset => (reset, UInt<3>("h07"))) wire T_1506 : UInt<3> - T_1506 <= UInt<1>("h00") + T_1506 is invalid io.out.valid <= io.in[T_1506].valid io.out.bits <- io.in[T_1506].bits io.chosen <= T_1506 io.in[T_1506].ready <= UInt<1>("h00") - reg last_grant : UInt<3>, clk, reset, UInt<3>("h00") - node T_1707 = gt(UInt<1>("h00"), last_grant) - node T_1708 = and(io.in[0].valid, T_1707) - node T_1710 = gt(UInt<1>("h01"), last_grant) - node T_1711 = and(io.in[1].valid, T_1710) - node T_1713 = gt(UInt<2>("h02"), last_grant) - node T_1714 = and(io.in[2].valid, T_1713) - node T_1716 = gt(UInt<2>("h03"), last_grant) - node T_1717 = and(io.in[3].valid, T_1716) - node T_1719 = gt(UInt<3>("h04"), last_grant) - node T_1720 = and(io.in[4].valid, T_1719) - node T_1722 = gt(UInt<3>("h05"), last_grant) - node T_1723 = and(io.in[5].valid, T_1722) - node T_1725 = gt(UInt<3>("h06"), last_grant) - node T_1726 = and(io.in[6].valid, T_1725) - node T_1728 = gt(UInt<3>("h07"), last_grant) - node T_1729 = and(io.in[7].valid, T_1728) - node T_1732 = or(UInt<1>("h00"), T_1708) - node T_1734 = eq(T_1732, UInt<1>("h00")) - node T_1736 = or(UInt<1>("h00"), T_1708) - node T_1737 = or(T_1736, T_1711) - node T_1739 = eq(T_1737, UInt<1>("h00")) - node T_1741 = or(UInt<1>("h00"), T_1708) - node T_1742 = or(T_1741, T_1711) - node T_1743 = or(T_1742, T_1714) - node T_1745 = eq(T_1743, UInt<1>("h00")) - node T_1747 = or(UInt<1>("h00"), T_1708) - node T_1748 = or(T_1747, T_1711) - node T_1749 = or(T_1748, T_1714) - node T_1750 = or(T_1749, T_1717) - node T_1752 = eq(T_1750, UInt<1>("h00")) - node T_1754 = or(UInt<1>("h00"), T_1708) - node T_1755 = or(T_1754, T_1711) - node T_1756 = or(T_1755, T_1714) - node T_1757 = or(T_1756, T_1717) - node T_1758 = or(T_1757, T_1720) - node T_1760 = eq(T_1758, UInt<1>("h00")) - node T_1762 = or(UInt<1>("h00"), T_1708) - node T_1763 = or(T_1762, T_1711) - node T_1764 = or(T_1763, T_1714) - node T_1765 = or(T_1764, T_1717) - node T_1766 = or(T_1765, T_1720) - node T_1767 = or(T_1766, T_1723) - node T_1769 = eq(T_1767, UInt<1>("h00")) - node T_1771 = or(UInt<1>("h00"), T_1708) - node T_1772 = or(T_1771, T_1711) - node T_1773 = or(T_1772, T_1714) - node T_1774 = or(T_1773, T_1717) - node T_1775 = or(T_1774, T_1720) - node T_1776 = or(T_1775, T_1723) - node T_1777 = or(T_1776, T_1726) - node T_1779 = eq(T_1777, UInt<1>("h00")) - node T_1781 = or(UInt<1>("h00"), T_1708) - node T_1782 = or(T_1781, T_1711) - node T_1783 = or(T_1782, T_1714) - node T_1784 = or(T_1783, T_1717) - node T_1785 = or(T_1784, T_1720) - node T_1786 = or(T_1785, T_1723) - node T_1787 = or(T_1786, T_1726) - node T_1788 = or(T_1787, T_1729) - node T_1790 = eq(T_1788, UInt<1>("h00")) - node T_1792 = or(UInt<1>("h00"), T_1708) - node T_1793 = or(T_1792, T_1711) - node T_1794 = or(T_1793, T_1714) - node T_1795 = or(T_1794, T_1717) - node T_1796 = or(T_1795, T_1720) - node T_1797 = or(T_1796, T_1723) - node T_1798 = or(T_1797, T_1726) - node T_1799 = or(T_1798, T_1729) - node T_1800 = or(T_1799, io.in[0].valid) - node T_1802 = eq(T_1800, UInt<1>("h00")) - node T_1804 = or(UInt<1>("h00"), T_1708) - node T_1805 = or(T_1804, T_1711) - node T_1806 = or(T_1805, T_1714) - node T_1807 = or(T_1806, T_1717) - node T_1808 = or(T_1807, T_1720) - node T_1809 = or(T_1808, T_1723) - node T_1810 = or(T_1809, T_1726) - node T_1811 = or(T_1810, T_1729) - node T_1812 = or(T_1811, io.in[0].valid) - node T_1813 = or(T_1812, io.in[1].valid) - node T_1815 = eq(T_1813, UInt<1>("h00")) - node T_1817 = or(UInt<1>("h00"), T_1708) - node T_1818 = or(T_1817, T_1711) - node T_1819 = or(T_1818, T_1714) - node T_1820 = or(T_1819, T_1717) - node T_1821 = or(T_1820, T_1720) - node T_1822 = or(T_1821, T_1723) - node T_1823 = or(T_1822, T_1726) - node T_1824 = or(T_1823, T_1729) - node T_1825 = or(T_1824, io.in[0].valid) - node T_1826 = or(T_1825, io.in[1].valid) - node T_1827 = or(T_1826, io.in[2].valid) - node T_1829 = eq(T_1827, UInt<1>("h00")) - node T_1831 = or(UInt<1>("h00"), T_1708) - node T_1832 = or(T_1831, T_1711) - node T_1833 = or(T_1832, T_1714) - node T_1834 = or(T_1833, T_1717) - node T_1835 = or(T_1834, T_1720) - node T_1836 = or(T_1835, T_1723) - node T_1837 = or(T_1836, T_1726) - node T_1838 = or(T_1837, T_1729) - node T_1839 = or(T_1838, io.in[0].valid) - node T_1840 = or(T_1839, io.in[1].valid) - node T_1841 = or(T_1840, io.in[2].valid) - node T_1842 = or(T_1841, io.in[3].valid) - node T_1844 = eq(T_1842, UInt<1>("h00")) - node T_1846 = or(UInt<1>("h00"), T_1708) - node T_1847 = or(T_1846, T_1711) - node T_1848 = or(T_1847, T_1714) - node T_1849 = or(T_1848, T_1717) - node T_1850 = or(T_1849, T_1720) - node T_1851 = or(T_1850, T_1723) - node T_1852 = or(T_1851, T_1726) - node T_1853 = or(T_1852, T_1729) - node T_1854 = or(T_1853, io.in[0].valid) - node T_1855 = or(T_1854, io.in[1].valid) - node T_1856 = or(T_1855, io.in[2].valid) - node T_1857 = or(T_1856, io.in[3].valid) - node T_1858 = or(T_1857, io.in[4].valid) - node T_1860 = eq(T_1858, UInt<1>("h00")) - node T_1862 = or(UInt<1>("h00"), T_1708) - node T_1863 = or(T_1862, T_1711) - node T_1864 = or(T_1863, T_1714) - node T_1865 = or(T_1864, T_1717) - node T_1866 = or(T_1865, T_1720) - node T_1867 = or(T_1866, T_1723) - node T_1868 = or(T_1867, T_1726) - node T_1869 = or(T_1868, T_1729) - node T_1870 = or(T_1869, io.in[0].valid) - node T_1871 = or(T_1870, io.in[1].valid) - node T_1872 = or(T_1871, io.in[2].valid) - node T_1873 = or(T_1872, io.in[3].valid) - node T_1874 = or(T_1873, io.in[4].valid) - node T_1875 = or(T_1874, io.in[5].valid) - node T_1877 = eq(T_1875, UInt<1>("h00")) - node T_1879 = or(UInt<1>("h00"), T_1708) - node T_1880 = or(T_1879, T_1711) - node T_1881 = or(T_1880, T_1714) - node T_1882 = or(T_1881, T_1717) - node T_1883 = or(T_1882, T_1720) - node T_1884 = or(T_1883, T_1723) - node T_1885 = or(T_1884, T_1726) - node T_1886 = or(T_1885, T_1729) - node T_1887 = or(T_1886, io.in[0].valid) - node T_1888 = or(T_1887, io.in[1].valid) - node T_1889 = or(T_1888, io.in[2].valid) - node T_1890 = or(T_1889, io.in[3].valid) - node T_1891 = or(T_1890, io.in[4].valid) - node T_1892 = or(T_1891, io.in[5].valid) - node T_1893 = or(T_1892, io.in[6].valid) - node T_1895 = eq(T_1893, UInt<1>("h00")) - node T_1897 = gt(UInt<1>("h00"), last_grant) - node T_1898 = and(UInt<1>("h01"), T_1897) - node T_1899 = or(T_1898, T_1790) - node T_1901 = gt(UInt<1>("h01"), last_grant) - node T_1902 = and(T_1734, T_1901) - node T_1903 = or(T_1902, T_1802) - node T_1905 = gt(UInt<2>("h02"), last_grant) - node T_1906 = and(T_1739, T_1905) - node T_1907 = or(T_1906, T_1815) - node T_1909 = gt(UInt<2>("h03"), last_grant) - node T_1910 = and(T_1745, T_1909) - node T_1911 = or(T_1910, T_1829) - node T_1913 = gt(UInt<3>("h04"), last_grant) - node T_1914 = and(T_1752, T_1913) - node T_1915 = or(T_1914, T_1844) - node T_1917 = gt(UInt<3>("h05"), last_grant) - node T_1918 = and(T_1760, T_1917) - node T_1919 = or(T_1918, T_1860) - node T_1921 = gt(UInt<3>("h06"), last_grant) - node T_1922 = and(T_1769, T_1921) - node T_1923 = or(T_1922, T_1877) - node T_1925 = gt(UInt<3>("h07"), last_grant) - node T_1926 = and(T_1779, T_1925) - node T_1927 = or(T_1926, T_1895) - node T_1929 = eq(T_1504, UInt<1>("h00")) - node T_1930 = mux(T_1502, T_1929, T_1899) - node T_1931 = and(T_1930, io.out.ready) - io.in[0].ready <= T_1931 - node T_1933 = eq(T_1504, UInt<1>("h01")) - node T_1934 = mux(T_1502, T_1933, T_1903) - node T_1935 = and(T_1934, io.out.ready) - io.in[1].ready <= T_1935 - node T_1937 = eq(T_1504, UInt<2>("h02")) - node T_1938 = mux(T_1502, T_1937, T_1907) - node T_1939 = and(T_1938, io.out.ready) - io.in[2].ready <= T_1939 - node T_1941 = eq(T_1504, UInt<2>("h03")) - node T_1942 = mux(T_1502, T_1941, T_1911) - node T_1943 = and(T_1942, io.out.ready) - io.in[3].ready <= T_1943 - node T_1945 = eq(T_1504, UInt<3>("h04")) - node T_1946 = mux(T_1502, T_1945, T_1915) - node T_1947 = and(T_1946, io.out.ready) - io.in[4].ready <= T_1947 - node T_1949 = eq(T_1504, UInt<3>("h05")) - node T_1950 = mux(T_1502, T_1949, T_1919) - node T_1951 = and(T_1950, io.out.ready) - io.in[5].ready <= T_1951 - node T_1953 = eq(T_1504, UInt<3>("h06")) - node T_1954 = mux(T_1502, T_1953, T_1923) - node T_1955 = and(T_1954, io.out.ready) - io.in[6].ready <= T_1955 - node T_1957 = eq(T_1504, UInt<3>("h07")) - node T_1958 = mux(T_1502, T_1957, T_1927) - node T_1959 = and(T_1958, io.out.ready) - io.in[7].ready <= T_1959 - reg T_1961 : UInt<2>, clk, reset, UInt<2>("h00") - node T_1963 = addw(T_1961, UInt<1>("h01")) + reg last_grant : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + node T_1706 = gt(UInt<1>("h00"), last_grant) + node T_1707 = and(io.in[0].valid, T_1706) + node T_1709 = gt(UInt<1>("h01"), last_grant) + node T_1710 = and(io.in[1].valid, T_1709) + node T_1712 = gt(UInt<2>("h02"), last_grant) + node T_1713 = and(io.in[2].valid, T_1712) + node T_1715 = gt(UInt<2>("h03"), last_grant) + node T_1716 = and(io.in[3].valid, T_1715) + node T_1718 = gt(UInt<3>("h04"), last_grant) + node T_1719 = and(io.in[4].valid, T_1718) + node T_1721 = gt(UInt<3>("h05"), last_grant) + node T_1722 = and(io.in[5].valid, T_1721) + node T_1724 = gt(UInt<3>("h06"), last_grant) + node T_1725 = and(io.in[6].valid, T_1724) + node T_1727 = gt(UInt<3>("h07"), last_grant) + node T_1728 = and(io.in[7].valid, T_1727) + node T_1731 = or(UInt<1>("h00"), T_1707) + node T_1733 = eq(T_1731, UInt<1>("h00")) + node T_1735 = or(UInt<1>("h00"), T_1707) + node T_1736 = or(T_1735, T_1710) + node T_1738 = eq(T_1736, UInt<1>("h00")) + node T_1740 = or(UInt<1>("h00"), T_1707) + node T_1741 = or(T_1740, T_1710) + node T_1742 = or(T_1741, T_1713) + node T_1744 = eq(T_1742, UInt<1>("h00")) + node T_1746 = or(UInt<1>("h00"), T_1707) + node T_1747 = or(T_1746, T_1710) + node T_1748 = or(T_1747, T_1713) + node T_1749 = or(T_1748, T_1716) + node T_1751 = eq(T_1749, UInt<1>("h00")) + node T_1753 = or(UInt<1>("h00"), T_1707) + node T_1754 = or(T_1753, T_1710) + node T_1755 = or(T_1754, T_1713) + node T_1756 = or(T_1755, T_1716) + node T_1757 = or(T_1756, T_1719) + node T_1759 = eq(T_1757, UInt<1>("h00")) + node T_1761 = or(UInt<1>("h00"), T_1707) + node T_1762 = or(T_1761, T_1710) + node T_1763 = or(T_1762, T_1713) + node T_1764 = or(T_1763, T_1716) + node T_1765 = or(T_1764, T_1719) + node T_1766 = or(T_1765, T_1722) + node T_1768 = eq(T_1766, UInt<1>("h00")) + node T_1770 = or(UInt<1>("h00"), T_1707) + node T_1771 = or(T_1770, T_1710) + node T_1772 = or(T_1771, T_1713) + node T_1773 = or(T_1772, T_1716) + node T_1774 = or(T_1773, T_1719) + node T_1775 = or(T_1774, T_1722) + node T_1776 = or(T_1775, T_1725) + node T_1778 = eq(T_1776, UInt<1>("h00")) + node T_1780 = or(UInt<1>("h00"), T_1707) + node T_1781 = or(T_1780, T_1710) + node T_1782 = or(T_1781, T_1713) + node T_1783 = or(T_1782, T_1716) + node T_1784 = or(T_1783, T_1719) + node T_1785 = or(T_1784, T_1722) + node T_1786 = or(T_1785, T_1725) + node T_1787 = or(T_1786, T_1728) + node T_1789 = eq(T_1787, UInt<1>("h00")) + node T_1791 = or(UInt<1>("h00"), T_1707) + node T_1792 = or(T_1791, T_1710) + node T_1793 = or(T_1792, T_1713) + node T_1794 = or(T_1793, T_1716) + node T_1795 = or(T_1794, T_1719) + node T_1796 = or(T_1795, T_1722) + node T_1797 = or(T_1796, T_1725) + node T_1798 = or(T_1797, T_1728) + node T_1799 = or(T_1798, io.in[0].valid) + node T_1801 = eq(T_1799, UInt<1>("h00")) + node T_1803 = or(UInt<1>("h00"), T_1707) + node T_1804 = or(T_1803, T_1710) + node T_1805 = or(T_1804, T_1713) + node T_1806 = or(T_1805, T_1716) + node T_1807 = or(T_1806, T_1719) + node T_1808 = or(T_1807, T_1722) + node T_1809 = or(T_1808, T_1725) + node T_1810 = or(T_1809, T_1728) + node T_1811 = or(T_1810, io.in[0].valid) + node T_1812 = or(T_1811, io.in[1].valid) + node T_1814 = eq(T_1812, UInt<1>("h00")) + node T_1816 = or(UInt<1>("h00"), T_1707) + node T_1817 = or(T_1816, T_1710) + node T_1818 = or(T_1817, T_1713) + node T_1819 = or(T_1818, T_1716) + node T_1820 = or(T_1819, T_1719) + node T_1821 = or(T_1820, T_1722) + node T_1822 = or(T_1821, T_1725) + node T_1823 = or(T_1822, T_1728) + node T_1824 = or(T_1823, io.in[0].valid) + node T_1825 = or(T_1824, io.in[1].valid) + node T_1826 = or(T_1825, io.in[2].valid) + node T_1828 = eq(T_1826, UInt<1>("h00")) + node T_1830 = or(UInt<1>("h00"), T_1707) + node T_1831 = or(T_1830, T_1710) + node T_1832 = or(T_1831, T_1713) + node T_1833 = or(T_1832, T_1716) + node T_1834 = or(T_1833, T_1719) + node T_1835 = or(T_1834, T_1722) + node T_1836 = or(T_1835, T_1725) + node T_1837 = or(T_1836, T_1728) + node T_1838 = or(T_1837, io.in[0].valid) + node T_1839 = or(T_1838, io.in[1].valid) + node T_1840 = or(T_1839, io.in[2].valid) + node T_1841 = or(T_1840, io.in[3].valid) + node T_1843 = eq(T_1841, UInt<1>("h00")) + node T_1845 = or(UInt<1>("h00"), T_1707) + node T_1846 = or(T_1845, T_1710) + node T_1847 = or(T_1846, T_1713) + node T_1848 = or(T_1847, T_1716) + node T_1849 = or(T_1848, T_1719) + node T_1850 = or(T_1849, T_1722) + node T_1851 = or(T_1850, T_1725) + node T_1852 = or(T_1851, T_1728) + node T_1853 = or(T_1852, io.in[0].valid) + node T_1854 = or(T_1853, io.in[1].valid) + node T_1855 = or(T_1854, io.in[2].valid) + node T_1856 = or(T_1855, io.in[3].valid) + node T_1857 = or(T_1856, io.in[4].valid) + node T_1859 = eq(T_1857, UInt<1>("h00")) + node T_1861 = or(UInt<1>("h00"), T_1707) + node T_1862 = or(T_1861, T_1710) + node T_1863 = or(T_1862, T_1713) + node T_1864 = or(T_1863, T_1716) + node T_1865 = or(T_1864, T_1719) + node T_1866 = or(T_1865, T_1722) + node T_1867 = or(T_1866, T_1725) + node T_1868 = or(T_1867, T_1728) + node T_1869 = or(T_1868, io.in[0].valid) + node T_1870 = or(T_1869, io.in[1].valid) + node T_1871 = or(T_1870, io.in[2].valid) + node T_1872 = or(T_1871, io.in[3].valid) + node T_1873 = or(T_1872, io.in[4].valid) + node T_1874 = or(T_1873, io.in[5].valid) + node T_1876 = eq(T_1874, UInt<1>("h00")) + node T_1878 = or(UInt<1>("h00"), T_1707) + node T_1879 = or(T_1878, T_1710) + node T_1880 = or(T_1879, T_1713) + node T_1881 = or(T_1880, T_1716) + node T_1882 = or(T_1881, T_1719) + node T_1883 = or(T_1882, T_1722) + node T_1884 = or(T_1883, T_1725) + node T_1885 = or(T_1884, T_1728) + node T_1886 = or(T_1885, io.in[0].valid) + node T_1887 = or(T_1886, io.in[1].valid) + node T_1888 = or(T_1887, io.in[2].valid) + node T_1889 = or(T_1888, io.in[3].valid) + node T_1890 = or(T_1889, io.in[4].valid) + node T_1891 = or(T_1890, io.in[5].valid) + node T_1892 = or(T_1891, io.in[6].valid) + node T_1894 = eq(T_1892, UInt<1>("h00")) + node T_1896 = gt(UInt<1>("h00"), last_grant) + node T_1897 = and(UInt<1>("h01"), T_1896) + node T_1898 = or(T_1897, T_1789) + node T_1900 = gt(UInt<1>("h01"), last_grant) + node T_1901 = and(T_1733, T_1900) + node T_1902 = or(T_1901, T_1801) + node T_1904 = gt(UInt<2>("h02"), last_grant) + node T_1905 = and(T_1738, T_1904) + node T_1906 = or(T_1905, T_1814) + node T_1908 = gt(UInt<2>("h03"), last_grant) + node T_1909 = and(T_1744, T_1908) + node T_1910 = or(T_1909, T_1828) + node T_1912 = gt(UInt<3>("h04"), last_grant) + node T_1913 = and(T_1751, T_1912) + node T_1914 = or(T_1913, T_1843) + node T_1916 = gt(UInt<3>("h05"), last_grant) + node T_1917 = and(T_1759, T_1916) + node T_1918 = or(T_1917, T_1859) + node T_1920 = gt(UInt<3>("h06"), last_grant) + node T_1921 = and(T_1768, T_1920) + node T_1922 = or(T_1921, T_1876) + node T_1924 = gt(UInt<3>("h07"), last_grant) + node T_1925 = and(T_1778, T_1924) + node T_1926 = or(T_1925, T_1894) + node T_1928 = eq(T_1504, UInt<1>("h00")) + node T_1929 = mux(T_1502, T_1928, T_1898) + node T_1930 = and(T_1929, io.out.ready) + io.in[0].ready <= T_1930 + node T_1932 = eq(T_1504, UInt<1>("h01")) + node T_1933 = mux(T_1502, T_1932, T_1902) + node T_1934 = and(T_1933, io.out.ready) + io.in[1].ready <= T_1934 + node T_1936 = eq(T_1504, UInt<2>("h02")) + node T_1937 = mux(T_1502, T_1936, T_1906) + node T_1938 = and(T_1937, io.out.ready) + io.in[2].ready <= T_1938 + node T_1940 = eq(T_1504, UInt<2>("h03")) + node T_1941 = mux(T_1502, T_1940, T_1910) + node T_1942 = and(T_1941, io.out.ready) + io.in[3].ready <= T_1942 + node T_1944 = eq(T_1504, UInt<3>("h04")) + node T_1945 = mux(T_1502, T_1944, T_1914) + node T_1946 = and(T_1945, io.out.ready) + io.in[4].ready <= T_1946 + node T_1948 = eq(T_1504, UInt<3>("h05")) + node T_1949 = mux(T_1502, T_1948, T_1918) + node T_1950 = and(T_1949, io.out.ready) + io.in[5].ready <= T_1950 + node T_1952 = eq(T_1504, UInt<3>("h06")) + node T_1953 = mux(T_1502, T_1952, T_1922) + node T_1954 = and(T_1953, io.out.ready) + io.in[6].ready <= T_1954 + node T_1956 = eq(T_1504, UInt<3>("h07")) + node T_1957 = mux(T_1502, T_1956, T_1926) + node T_1958 = and(T_1957, io.out.ready) + io.in[7].ready <= T_1958 + reg T_1960 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + node T_1962 = add(T_1960, UInt<1>("h01")) + node T_1963 = tail(T_1962, 1) node T_1964 = and(io.out.ready, io.out.valid) when T_1964 : wire T_1968 : UInt<3>[1] @@ -9750,7 +8186,7 @@ circuit Top : node T_1984 = mux(io.out.bits.is_builtin_type, T_1973, T_1983) node T_1985 = and(UInt<1>("h01"), T_1984) when T_1985 : - T_1961 <= T_1963 + T_1960 <= T_1963 node T_1987 = eq(T_1502, UInt<1>("h00")) when T_1987 : T_1502 <= UInt<1>("h01") @@ -9826,241 +8262,230 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, chosen : UInt<3>} - io.chosen <= UInt<1>("h00") - io.out.bits.client_id <= UInt<1>("h00") - io.out.bits.p_type <= UInt<1>("h00") - io.out.bits.addr_block <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") - io.in[2].ready <= UInt<1>("h00") - io.in[3].ready <= UInt<1>("h00") - io.in[4].ready <= UInt<1>("h00") - io.in[5].ready <= UInt<1>("h00") - io.in[6].ready <= UInt<1>("h00") - io.in[7].ready <= UInt<1>("h00") - reg T_1318 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_1320 : UInt<?>, clk, reset, UInt<3>("h07") + io is invalid + reg T_1318 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_1320 : UInt<?>, clk with : (reset => (reset, UInt<3>("h07"))) wire T_1322 : UInt<3> - T_1322 <= UInt<1>("h00") + T_1322 is invalid io.out.valid <= io.in[T_1322].valid io.out.bits <- io.in[T_1322].bits io.chosen <= T_1322 io.in[T_1322].ready <= UInt<1>("h00") - reg last_grant : UInt<3>, clk, reset, UInt<3>("h00") - node T_1499 = gt(UInt<1>("h00"), last_grant) - node T_1500 = and(io.in[0].valid, T_1499) - node T_1502 = gt(UInt<1>("h01"), last_grant) - node T_1503 = and(io.in[1].valid, T_1502) - node T_1505 = gt(UInt<2>("h02"), last_grant) - node T_1506 = and(io.in[2].valid, T_1505) - node T_1508 = gt(UInt<2>("h03"), last_grant) - node T_1509 = and(io.in[3].valid, T_1508) - node T_1511 = gt(UInt<3>("h04"), last_grant) - node T_1512 = and(io.in[4].valid, T_1511) - node T_1514 = gt(UInt<3>("h05"), last_grant) - node T_1515 = and(io.in[5].valid, T_1514) - node T_1517 = gt(UInt<3>("h06"), last_grant) - node T_1518 = and(io.in[6].valid, T_1517) - node T_1520 = gt(UInt<3>("h07"), last_grant) - node T_1521 = and(io.in[7].valid, T_1520) - node T_1524 = or(UInt<1>("h00"), T_1500) - node T_1526 = eq(T_1524, UInt<1>("h00")) - node T_1528 = or(UInt<1>("h00"), T_1500) - node T_1529 = or(T_1528, T_1503) - node T_1531 = eq(T_1529, UInt<1>("h00")) - node T_1533 = or(UInt<1>("h00"), T_1500) - node T_1534 = or(T_1533, T_1503) - node T_1535 = or(T_1534, T_1506) - node T_1537 = eq(T_1535, UInt<1>("h00")) - node T_1539 = or(UInt<1>("h00"), T_1500) - node T_1540 = or(T_1539, T_1503) - node T_1541 = or(T_1540, T_1506) - node T_1542 = or(T_1541, T_1509) - node T_1544 = eq(T_1542, UInt<1>("h00")) - node T_1546 = or(UInt<1>("h00"), T_1500) - node T_1547 = or(T_1546, T_1503) - node T_1548 = or(T_1547, T_1506) - node T_1549 = or(T_1548, T_1509) - node T_1550 = or(T_1549, T_1512) - node T_1552 = eq(T_1550, UInt<1>("h00")) - node T_1554 = or(UInt<1>("h00"), T_1500) - node T_1555 = or(T_1554, T_1503) - node T_1556 = or(T_1555, T_1506) - node T_1557 = or(T_1556, T_1509) - node T_1558 = or(T_1557, T_1512) - node T_1559 = or(T_1558, T_1515) - node T_1561 = eq(T_1559, UInt<1>("h00")) - node T_1563 = or(UInt<1>("h00"), T_1500) - node T_1564 = or(T_1563, T_1503) - node T_1565 = or(T_1564, T_1506) - node T_1566 = or(T_1565, T_1509) - node T_1567 = or(T_1566, T_1512) - node T_1568 = or(T_1567, T_1515) - node T_1569 = or(T_1568, T_1518) - node T_1571 = eq(T_1569, UInt<1>("h00")) - node T_1573 = or(UInt<1>("h00"), T_1500) - node T_1574 = or(T_1573, T_1503) - node T_1575 = or(T_1574, T_1506) - node T_1576 = or(T_1575, T_1509) - node T_1577 = or(T_1576, T_1512) - node T_1578 = or(T_1577, T_1515) - node T_1579 = or(T_1578, T_1518) - node T_1580 = or(T_1579, T_1521) - node T_1582 = eq(T_1580, UInt<1>("h00")) - node T_1584 = or(UInt<1>("h00"), T_1500) - node T_1585 = or(T_1584, T_1503) - node T_1586 = or(T_1585, T_1506) - node T_1587 = or(T_1586, T_1509) - node T_1588 = or(T_1587, T_1512) - node T_1589 = or(T_1588, T_1515) - node T_1590 = or(T_1589, T_1518) - node T_1591 = or(T_1590, T_1521) - node T_1592 = or(T_1591, io.in[0].valid) - node T_1594 = eq(T_1592, UInt<1>("h00")) - node T_1596 = or(UInt<1>("h00"), T_1500) - node T_1597 = or(T_1596, T_1503) - node T_1598 = or(T_1597, T_1506) - node T_1599 = or(T_1598, T_1509) - node T_1600 = or(T_1599, T_1512) - node T_1601 = or(T_1600, T_1515) - node T_1602 = or(T_1601, T_1518) - node T_1603 = or(T_1602, T_1521) - node T_1604 = or(T_1603, io.in[0].valid) - node T_1605 = or(T_1604, io.in[1].valid) - node T_1607 = eq(T_1605, UInt<1>("h00")) - node T_1609 = or(UInt<1>("h00"), T_1500) - node T_1610 = or(T_1609, T_1503) - node T_1611 = or(T_1610, T_1506) - node T_1612 = or(T_1611, T_1509) - node T_1613 = or(T_1612, T_1512) - node T_1614 = or(T_1613, T_1515) - node T_1615 = or(T_1614, T_1518) - node T_1616 = or(T_1615, T_1521) - node T_1617 = or(T_1616, io.in[0].valid) - node T_1618 = or(T_1617, io.in[1].valid) - node T_1619 = or(T_1618, io.in[2].valid) - node T_1621 = eq(T_1619, UInt<1>("h00")) - node T_1623 = or(UInt<1>("h00"), T_1500) - node T_1624 = or(T_1623, T_1503) - node T_1625 = or(T_1624, T_1506) - node T_1626 = or(T_1625, T_1509) - node T_1627 = or(T_1626, T_1512) - node T_1628 = or(T_1627, T_1515) - node T_1629 = or(T_1628, T_1518) - node T_1630 = or(T_1629, T_1521) - node T_1631 = or(T_1630, io.in[0].valid) - node T_1632 = or(T_1631, io.in[1].valid) - node T_1633 = or(T_1632, io.in[2].valid) - node T_1634 = or(T_1633, io.in[3].valid) - node T_1636 = eq(T_1634, UInt<1>("h00")) - node T_1638 = or(UInt<1>("h00"), T_1500) - node T_1639 = or(T_1638, T_1503) - node T_1640 = or(T_1639, T_1506) - node T_1641 = or(T_1640, T_1509) - node T_1642 = or(T_1641, T_1512) - node T_1643 = or(T_1642, T_1515) - node T_1644 = or(T_1643, T_1518) - node T_1645 = or(T_1644, T_1521) - node T_1646 = or(T_1645, io.in[0].valid) - node T_1647 = or(T_1646, io.in[1].valid) - node T_1648 = or(T_1647, io.in[2].valid) - node T_1649 = or(T_1648, io.in[3].valid) - node T_1650 = or(T_1649, io.in[4].valid) - node T_1652 = eq(T_1650, UInt<1>("h00")) - node T_1654 = or(UInt<1>("h00"), T_1500) - node T_1655 = or(T_1654, T_1503) - node T_1656 = or(T_1655, T_1506) - node T_1657 = or(T_1656, T_1509) - node T_1658 = or(T_1657, T_1512) - node T_1659 = or(T_1658, T_1515) - node T_1660 = or(T_1659, T_1518) - node T_1661 = or(T_1660, T_1521) - node T_1662 = or(T_1661, io.in[0].valid) - node T_1663 = or(T_1662, io.in[1].valid) - node T_1664 = or(T_1663, io.in[2].valid) - node T_1665 = or(T_1664, io.in[3].valid) - node T_1666 = or(T_1665, io.in[4].valid) - node T_1667 = or(T_1666, io.in[5].valid) - node T_1669 = eq(T_1667, UInt<1>("h00")) - node T_1671 = or(UInt<1>("h00"), T_1500) - node T_1672 = or(T_1671, T_1503) - node T_1673 = or(T_1672, T_1506) - node T_1674 = or(T_1673, T_1509) - node T_1675 = or(T_1674, T_1512) - node T_1676 = or(T_1675, T_1515) - node T_1677 = or(T_1676, T_1518) - node T_1678 = or(T_1677, T_1521) - node T_1679 = or(T_1678, io.in[0].valid) - node T_1680 = or(T_1679, io.in[1].valid) - node T_1681 = or(T_1680, io.in[2].valid) - node T_1682 = or(T_1681, io.in[3].valid) - node T_1683 = or(T_1682, io.in[4].valid) - node T_1684 = or(T_1683, io.in[5].valid) - node T_1685 = or(T_1684, io.in[6].valid) - node T_1687 = eq(T_1685, UInt<1>("h00")) - node T_1689 = gt(UInt<1>("h00"), last_grant) - node T_1690 = and(UInt<1>("h01"), T_1689) - node T_1691 = or(T_1690, T_1582) - node T_1693 = gt(UInt<1>("h01"), last_grant) - node T_1694 = and(T_1526, T_1693) - node T_1695 = or(T_1694, T_1594) - node T_1697 = gt(UInt<2>("h02"), last_grant) - node T_1698 = and(T_1531, T_1697) - node T_1699 = or(T_1698, T_1607) - node T_1701 = gt(UInt<2>("h03"), last_grant) - node T_1702 = and(T_1537, T_1701) - node T_1703 = or(T_1702, T_1621) - node T_1705 = gt(UInt<3>("h04"), last_grant) - node T_1706 = and(T_1544, T_1705) - node T_1707 = or(T_1706, T_1636) - node T_1709 = gt(UInt<3>("h05"), last_grant) - node T_1710 = and(T_1552, T_1709) - node T_1711 = or(T_1710, T_1652) - node T_1713 = gt(UInt<3>("h06"), last_grant) - node T_1714 = and(T_1561, T_1713) - node T_1715 = or(T_1714, T_1669) - node T_1717 = gt(UInt<3>("h07"), last_grant) - node T_1718 = and(T_1571, T_1717) - node T_1719 = or(T_1718, T_1687) - node T_1721 = eq(T_1320, UInt<1>("h00")) - node T_1722 = mux(T_1318, T_1721, T_1691) - node T_1723 = and(T_1722, io.out.ready) - io.in[0].ready <= T_1723 - node T_1725 = eq(T_1320, UInt<1>("h01")) - node T_1726 = mux(T_1318, T_1725, T_1695) - node T_1727 = and(T_1726, io.out.ready) - io.in[1].ready <= T_1727 - node T_1729 = eq(T_1320, UInt<2>("h02")) - node T_1730 = mux(T_1318, T_1729, T_1699) - node T_1731 = and(T_1730, io.out.ready) - io.in[2].ready <= T_1731 - node T_1733 = eq(T_1320, UInt<2>("h03")) - node T_1734 = mux(T_1318, T_1733, T_1703) - node T_1735 = and(T_1734, io.out.ready) - io.in[3].ready <= T_1735 - node T_1737 = eq(T_1320, UInt<3>("h04")) - node T_1738 = mux(T_1318, T_1737, T_1707) - node T_1739 = and(T_1738, io.out.ready) - io.in[4].ready <= T_1739 - node T_1741 = eq(T_1320, UInt<3>("h05")) - node T_1742 = mux(T_1318, T_1741, T_1711) - node T_1743 = and(T_1742, io.out.ready) - io.in[5].ready <= T_1743 - node T_1745 = eq(T_1320, UInt<3>("h06")) - node T_1746 = mux(T_1318, T_1745, T_1715) - node T_1747 = and(T_1746, io.out.ready) - io.in[6].ready <= T_1747 - node T_1749 = eq(T_1320, UInt<3>("h07")) - node T_1750 = mux(T_1318, T_1749, T_1719) - node T_1751 = and(T_1750, io.out.ready) - io.in[7].ready <= T_1751 - reg T_1753 : UInt<2>, clk, reset, UInt<2>("h00") - node T_1755 = addw(T_1753, UInt<1>("h01")) + reg last_grant : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + node T_1498 = gt(UInt<1>("h00"), last_grant) + node T_1499 = and(io.in[0].valid, T_1498) + node T_1501 = gt(UInt<1>("h01"), last_grant) + node T_1502 = and(io.in[1].valid, T_1501) + node T_1504 = gt(UInt<2>("h02"), last_grant) + node T_1505 = and(io.in[2].valid, T_1504) + node T_1507 = gt(UInt<2>("h03"), last_grant) + node T_1508 = and(io.in[3].valid, T_1507) + node T_1510 = gt(UInt<3>("h04"), last_grant) + node T_1511 = and(io.in[4].valid, T_1510) + node T_1513 = gt(UInt<3>("h05"), last_grant) + node T_1514 = and(io.in[5].valid, T_1513) + node T_1516 = gt(UInt<3>("h06"), last_grant) + node T_1517 = and(io.in[6].valid, T_1516) + node T_1519 = gt(UInt<3>("h07"), last_grant) + node T_1520 = and(io.in[7].valid, T_1519) + node T_1523 = or(UInt<1>("h00"), T_1499) + node T_1525 = eq(T_1523, UInt<1>("h00")) + node T_1527 = or(UInt<1>("h00"), T_1499) + node T_1528 = or(T_1527, T_1502) + node T_1530 = eq(T_1528, UInt<1>("h00")) + node T_1532 = or(UInt<1>("h00"), T_1499) + node T_1533 = or(T_1532, T_1502) + node T_1534 = or(T_1533, T_1505) + node T_1536 = eq(T_1534, UInt<1>("h00")) + node T_1538 = or(UInt<1>("h00"), T_1499) + node T_1539 = or(T_1538, T_1502) + node T_1540 = or(T_1539, T_1505) + node T_1541 = or(T_1540, T_1508) + node T_1543 = eq(T_1541, UInt<1>("h00")) + node T_1545 = or(UInt<1>("h00"), T_1499) + node T_1546 = or(T_1545, T_1502) + node T_1547 = or(T_1546, T_1505) + node T_1548 = or(T_1547, T_1508) + node T_1549 = or(T_1548, T_1511) + node T_1551 = eq(T_1549, UInt<1>("h00")) + node T_1553 = or(UInt<1>("h00"), T_1499) + node T_1554 = or(T_1553, T_1502) + node T_1555 = or(T_1554, T_1505) + node T_1556 = or(T_1555, T_1508) + node T_1557 = or(T_1556, T_1511) + node T_1558 = or(T_1557, T_1514) + node T_1560 = eq(T_1558, UInt<1>("h00")) + node T_1562 = or(UInt<1>("h00"), T_1499) + node T_1563 = or(T_1562, T_1502) + node T_1564 = or(T_1563, T_1505) + node T_1565 = or(T_1564, T_1508) + node T_1566 = or(T_1565, T_1511) + node T_1567 = or(T_1566, T_1514) + node T_1568 = or(T_1567, T_1517) + node T_1570 = eq(T_1568, UInt<1>("h00")) + node T_1572 = or(UInt<1>("h00"), T_1499) + node T_1573 = or(T_1572, T_1502) + node T_1574 = or(T_1573, T_1505) + node T_1575 = or(T_1574, T_1508) + node T_1576 = or(T_1575, T_1511) + node T_1577 = or(T_1576, T_1514) + node T_1578 = or(T_1577, T_1517) + node T_1579 = or(T_1578, T_1520) + node T_1581 = eq(T_1579, UInt<1>("h00")) + node T_1583 = or(UInt<1>("h00"), T_1499) + node T_1584 = or(T_1583, T_1502) + node T_1585 = or(T_1584, T_1505) + node T_1586 = or(T_1585, T_1508) + node T_1587 = or(T_1586, T_1511) + node T_1588 = or(T_1587, T_1514) + node T_1589 = or(T_1588, T_1517) + node T_1590 = or(T_1589, T_1520) + node T_1591 = or(T_1590, io.in[0].valid) + node T_1593 = eq(T_1591, UInt<1>("h00")) + node T_1595 = or(UInt<1>("h00"), T_1499) + node T_1596 = or(T_1595, T_1502) + node T_1597 = or(T_1596, T_1505) + node T_1598 = or(T_1597, T_1508) + node T_1599 = or(T_1598, T_1511) + node T_1600 = or(T_1599, T_1514) + node T_1601 = or(T_1600, T_1517) + node T_1602 = or(T_1601, T_1520) + node T_1603 = or(T_1602, io.in[0].valid) + node T_1604 = or(T_1603, io.in[1].valid) + node T_1606 = eq(T_1604, UInt<1>("h00")) + node T_1608 = or(UInt<1>("h00"), T_1499) + node T_1609 = or(T_1608, T_1502) + node T_1610 = or(T_1609, T_1505) + node T_1611 = or(T_1610, T_1508) + node T_1612 = or(T_1611, T_1511) + node T_1613 = or(T_1612, T_1514) + node T_1614 = or(T_1613, T_1517) + node T_1615 = or(T_1614, T_1520) + node T_1616 = or(T_1615, io.in[0].valid) + node T_1617 = or(T_1616, io.in[1].valid) + node T_1618 = or(T_1617, io.in[2].valid) + node T_1620 = eq(T_1618, UInt<1>("h00")) + node T_1622 = or(UInt<1>("h00"), T_1499) + node T_1623 = or(T_1622, T_1502) + node T_1624 = or(T_1623, T_1505) + node T_1625 = or(T_1624, T_1508) + node T_1626 = or(T_1625, T_1511) + node T_1627 = or(T_1626, T_1514) + node T_1628 = or(T_1627, T_1517) + node T_1629 = or(T_1628, T_1520) + node T_1630 = or(T_1629, io.in[0].valid) + node T_1631 = or(T_1630, io.in[1].valid) + node T_1632 = or(T_1631, io.in[2].valid) + node T_1633 = or(T_1632, io.in[3].valid) + node T_1635 = eq(T_1633, UInt<1>("h00")) + node T_1637 = or(UInt<1>("h00"), T_1499) + node T_1638 = or(T_1637, T_1502) + node T_1639 = or(T_1638, T_1505) + node T_1640 = or(T_1639, T_1508) + node T_1641 = or(T_1640, T_1511) + node T_1642 = or(T_1641, T_1514) + node T_1643 = or(T_1642, T_1517) + node T_1644 = or(T_1643, T_1520) + node T_1645 = or(T_1644, io.in[0].valid) + node T_1646 = or(T_1645, io.in[1].valid) + node T_1647 = or(T_1646, io.in[2].valid) + node T_1648 = or(T_1647, io.in[3].valid) + node T_1649 = or(T_1648, io.in[4].valid) + node T_1651 = eq(T_1649, UInt<1>("h00")) + node T_1653 = or(UInt<1>("h00"), T_1499) + node T_1654 = or(T_1653, T_1502) + node T_1655 = or(T_1654, T_1505) + node T_1656 = or(T_1655, T_1508) + node T_1657 = or(T_1656, T_1511) + node T_1658 = or(T_1657, T_1514) + node T_1659 = or(T_1658, T_1517) + node T_1660 = or(T_1659, T_1520) + node T_1661 = or(T_1660, io.in[0].valid) + node T_1662 = or(T_1661, io.in[1].valid) + node T_1663 = or(T_1662, io.in[2].valid) + node T_1664 = or(T_1663, io.in[3].valid) + node T_1665 = or(T_1664, io.in[4].valid) + node T_1666 = or(T_1665, io.in[5].valid) + node T_1668 = eq(T_1666, UInt<1>("h00")) + node T_1670 = or(UInt<1>("h00"), T_1499) + node T_1671 = or(T_1670, T_1502) + node T_1672 = or(T_1671, T_1505) + node T_1673 = or(T_1672, T_1508) + node T_1674 = or(T_1673, T_1511) + node T_1675 = or(T_1674, T_1514) + node T_1676 = or(T_1675, T_1517) + node T_1677 = or(T_1676, T_1520) + node T_1678 = or(T_1677, io.in[0].valid) + node T_1679 = or(T_1678, io.in[1].valid) + node T_1680 = or(T_1679, io.in[2].valid) + node T_1681 = or(T_1680, io.in[3].valid) + node T_1682 = or(T_1681, io.in[4].valid) + node T_1683 = or(T_1682, io.in[5].valid) + node T_1684 = or(T_1683, io.in[6].valid) + node T_1686 = eq(T_1684, UInt<1>("h00")) + node T_1688 = gt(UInt<1>("h00"), last_grant) + node T_1689 = and(UInt<1>("h01"), T_1688) + node T_1690 = or(T_1689, T_1581) + node T_1692 = gt(UInt<1>("h01"), last_grant) + node T_1693 = and(T_1525, T_1692) + node T_1694 = or(T_1693, T_1593) + node T_1696 = gt(UInt<2>("h02"), last_grant) + node T_1697 = and(T_1530, T_1696) + node T_1698 = or(T_1697, T_1606) + node T_1700 = gt(UInt<2>("h03"), last_grant) + node T_1701 = and(T_1536, T_1700) + node T_1702 = or(T_1701, T_1620) + node T_1704 = gt(UInt<3>("h04"), last_grant) + node T_1705 = and(T_1543, T_1704) + node T_1706 = or(T_1705, T_1635) + node T_1708 = gt(UInt<3>("h05"), last_grant) + node T_1709 = and(T_1551, T_1708) + node T_1710 = or(T_1709, T_1651) + node T_1712 = gt(UInt<3>("h06"), last_grant) + node T_1713 = and(T_1560, T_1712) + node T_1714 = or(T_1713, T_1668) + node T_1716 = gt(UInt<3>("h07"), last_grant) + node T_1717 = and(T_1570, T_1716) + node T_1718 = or(T_1717, T_1686) + node T_1720 = eq(T_1320, UInt<1>("h00")) + node T_1721 = mux(T_1318, T_1720, T_1690) + node T_1722 = and(T_1721, io.out.ready) + io.in[0].ready <= T_1722 + node T_1724 = eq(T_1320, UInt<1>("h01")) + node T_1725 = mux(T_1318, T_1724, T_1694) + node T_1726 = and(T_1725, io.out.ready) + io.in[1].ready <= T_1726 + node T_1728 = eq(T_1320, UInt<2>("h02")) + node T_1729 = mux(T_1318, T_1728, T_1698) + node T_1730 = and(T_1729, io.out.ready) + io.in[2].ready <= T_1730 + node T_1732 = eq(T_1320, UInt<2>("h03")) + node T_1733 = mux(T_1318, T_1732, T_1702) + node T_1734 = and(T_1733, io.out.ready) + io.in[3].ready <= T_1734 + node T_1736 = eq(T_1320, UInt<3>("h04")) + node T_1737 = mux(T_1318, T_1736, T_1706) + node T_1738 = and(T_1737, io.out.ready) + io.in[4].ready <= T_1738 + node T_1740 = eq(T_1320, UInt<3>("h05")) + node T_1741 = mux(T_1318, T_1740, T_1710) + node T_1742 = and(T_1741, io.out.ready) + io.in[5].ready <= T_1742 + node T_1744 = eq(T_1320, UInt<3>("h06")) + node T_1745 = mux(T_1318, T_1744, T_1714) + node T_1746 = and(T_1745, io.out.ready) + io.in[6].ready <= T_1746 + node T_1748 = eq(T_1320, UInt<3>("h07")) + node T_1749 = mux(T_1318, T_1748, T_1718) + node T_1750 = and(T_1749, io.out.ready) + io.in[7].ready <= T_1750 + reg T_1752 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + node T_1754 = add(T_1752, UInt<1>("h01")) + node T_1755 = tail(T_1754, 1) node T_1756 = and(io.out.ready, io.out.valid) when T_1756 : when UInt<1>("h00") : - T_1753 <= T_1755 + T_1752 <= T_1755 node T_1759 = eq(T_1318, UInt<1>("h00")) when T_1759 : T_1318 <= UInt<1>("h01") @@ -10136,241 +8561,226 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}[8], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, chosen : UInt<3>} - io.chosen <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.bits.union <= UInt<1>("h00") - io.out.bits.a_type <= UInt<1>("h00") - io.out.bits.is_builtin_type <= UInt<1>("h00") - io.out.bits.addr_beat <= UInt<1>("h00") - io.out.bits.client_xact_id <= UInt<1>("h00") - io.out.bits.addr_block <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") - io.in[2].ready <= UInt<1>("h00") - io.in[3].ready <= UInt<1>("h00") - io.in[4].ready <= UInt<1>("h00") - io.in[5].ready <= UInt<1>("h00") - io.in[6].ready <= UInt<1>("h00") - io.in[7].ready <= UInt<1>("h00") - reg T_444 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_446 : UInt<?>, clk, reset, UInt<3>("h07") + io is invalid + reg T_444 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_446 : UInt<?>, clk with : (reset => (reset, UInt<3>("h07"))) wire T_448 : UInt<3> - T_448 <= UInt<1>("h00") + T_448 is invalid io.out.valid <= io.in[T_448].valid io.out.bits <- io.in[T_448].bits io.chosen <= T_448 io.in[T_448].ready <= UInt<1>("h00") - reg last_grant : UInt<3>, clk, reset, UInt<3>("h00") - node T_511 = gt(UInt<1>("h00"), last_grant) - node T_512 = and(io.in[0].valid, T_511) - node T_514 = gt(UInt<1>("h01"), last_grant) - node T_515 = and(io.in[1].valid, T_514) - node T_517 = gt(UInt<2>("h02"), last_grant) - node T_518 = and(io.in[2].valid, T_517) - node T_520 = gt(UInt<2>("h03"), last_grant) - node T_521 = and(io.in[3].valid, T_520) - node T_523 = gt(UInt<3>("h04"), last_grant) - node T_524 = and(io.in[4].valid, T_523) - node T_526 = gt(UInt<3>("h05"), last_grant) - node T_527 = and(io.in[5].valid, T_526) - node T_529 = gt(UInt<3>("h06"), last_grant) - node T_530 = and(io.in[6].valid, T_529) - node T_532 = gt(UInt<3>("h07"), last_grant) - node T_533 = and(io.in[7].valid, T_532) - node T_536 = or(UInt<1>("h00"), T_512) - node T_538 = eq(T_536, UInt<1>("h00")) - node T_540 = or(UInt<1>("h00"), T_512) - node T_541 = or(T_540, T_515) - node T_543 = eq(T_541, UInt<1>("h00")) - node T_545 = or(UInt<1>("h00"), T_512) - node T_546 = or(T_545, T_515) - node T_547 = or(T_546, T_518) - node T_549 = eq(T_547, UInt<1>("h00")) - node T_551 = or(UInt<1>("h00"), T_512) - node T_552 = or(T_551, T_515) - node T_553 = or(T_552, T_518) - node T_554 = or(T_553, T_521) - node T_556 = eq(T_554, UInt<1>("h00")) - node T_558 = or(UInt<1>("h00"), T_512) - node T_559 = or(T_558, T_515) - node T_560 = or(T_559, T_518) - node T_561 = or(T_560, T_521) - node T_562 = or(T_561, T_524) - node T_564 = eq(T_562, UInt<1>("h00")) - node T_566 = or(UInt<1>("h00"), T_512) - node T_567 = or(T_566, T_515) - node T_568 = or(T_567, T_518) - node T_569 = or(T_568, T_521) - node T_570 = or(T_569, T_524) - node T_571 = or(T_570, T_527) - node T_573 = eq(T_571, UInt<1>("h00")) - node T_575 = or(UInt<1>("h00"), T_512) - node T_576 = or(T_575, T_515) - node T_577 = or(T_576, T_518) - node T_578 = or(T_577, T_521) - node T_579 = or(T_578, T_524) - node T_580 = or(T_579, T_527) - node T_581 = or(T_580, T_530) - node T_583 = eq(T_581, UInt<1>("h00")) - node T_585 = or(UInt<1>("h00"), T_512) - node T_586 = or(T_585, T_515) - node T_587 = or(T_586, T_518) - node T_588 = or(T_587, T_521) - node T_589 = or(T_588, T_524) - node T_590 = or(T_589, T_527) - node T_591 = or(T_590, T_530) - node T_592 = or(T_591, T_533) - node T_594 = eq(T_592, UInt<1>("h00")) - node T_596 = or(UInt<1>("h00"), T_512) - node T_597 = or(T_596, T_515) - node T_598 = or(T_597, T_518) - node T_599 = or(T_598, T_521) - node T_600 = or(T_599, T_524) - node T_601 = or(T_600, T_527) - node T_602 = or(T_601, T_530) - node T_603 = or(T_602, T_533) - node T_604 = or(T_603, io.in[0].valid) - node T_606 = eq(T_604, UInt<1>("h00")) - node T_608 = or(UInt<1>("h00"), T_512) - node T_609 = or(T_608, T_515) - node T_610 = or(T_609, T_518) - node T_611 = or(T_610, T_521) - node T_612 = or(T_611, T_524) - node T_613 = or(T_612, T_527) - node T_614 = or(T_613, T_530) - node T_615 = or(T_614, T_533) - node T_616 = or(T_615, io.in[0].valid) - node T_617 = or(T_616, io.in[1].valid) - node T_619 = eq(T_617, UInt<1>("h00")) - node T_621 = or(UInt<1>("h00"), T_512) - node T_622 = or(T_621, T_515) - node T_623 = or(T_622, T_518) - node T_624 = or(T_623, T_521) - node T_625 = or(T_624, T_524) - node T_626 = or(T_625, T_527) - node T_627 = or(T_626, T_530) - node T_628 = or(T_627, T_533) - node T_629 = or(T_628, io.in[0].valid) - node T_630 = or(T_629, io.in[1].valid) - node T_631 = or(T_630, io.in[2].valid) - node T_633 = eq(T_631, UInt<1>("h00")) - node T_635 = or(UInt<1>("h00"), T_512) - node T_636 = or(T_635, T_515) - node T_637 = or(T_636, T_518) - node T_638 = or(T_637, T_521) - node T_639 = or(T_638, T_524) - node T_640 = or(T_639, T_527) - node T_641 = or(T_640, T_530) - node T_642 = or(T_641, T_533) - node T_643 = or(T_642, io.in[0].valid) - node T_644 = or(T_643, io.in[1].valid) - node T_645 = or(T_644, io.in[2].valid) - node T_646 = or(T_645, io.in[3].valid) - node T_648 = eq(T_646, UInt<1>("h00")) - node T_650 = or(UInt<1>("h00"), T_512) - node T_651 = or(T_650, T_515) - node T_652 = or(T_651, T_518) - node T_653 = or(T_652, T_521) - node T_654 = or(T_653, T_524) - node T_655 = or(T_654, T_527) - node T_656 = or(T_655, T_530) - node T_657 = or(T_656, T_533) - node T_658 = or(T_657, io.in[0].valid) - node T_659 = or(T_658, io.in[1].valid) - node T_660 = or(T_659, io.in[2].valid) - node T_661 = or(T_660, io.in[3].valid) - node T_662 = or(T_661, io.in[4].valid) - node T_664 = eq(T_662, UInt<1>("h00")) - node T_666 = or(UInt<1>("h00"), T_512) - node T_667 = or(T_666, T_515) - node T_668 = or(T_667, T_518) - node T_669 = or(T_668, T_521) - node T_670 = or(T_669, T_524) - node T_671 = or(T_670, T_527) - node T_672 = or(T_671, T_530) - node T_673 = or(T_672, T_533) - node T_674 = or(T_673, io.in[0].valid) - node T_675 = or(T_674, io.in[1].valid) - node T_676 = or(T_675, io.in[2].valid) - node T_677 = or(T_676, io.in[3].valid) - node T_678 = or(T_677, io.in[4].valid) - node T_679 = or(T_678, io.in[5].valid) - node T_681 = eq(T_679, UInt<1>("h00")) - node T_683 = or(UInt<1>("h00"), T_512) - node T_684 = or(T_683, T_515) - node T_685 = or(T_684, T_518) - node T_686 = or(T_685, T_521) - node T_687 = or(T_686, T_524) - node T_688 = or(T_687, T_527) - node T_689 = or(T_688, T_530) - node T_690 = or(T_689, T_533) - node T_691 = or(T_690, io.in[0].valid) - node T_692 = or(T_691, io.in[1].valid) - node T_693 = or(T_692, io.in[2].valid) - node T_694 = or(T_693, io.in[3].valid) - node T_695 = or(T_694, io.in[4].valid) - node T_696 = or(T_695, io.in[5].valid) - node T_697 = or(T_696, io.in[6].valid) - node T_699 = eq(T_697, UInt<1>("h00")) - node T_701 = gt(UInt<1>("h00"), last_grant) - node T_702 = and(UInt<1>("h01"), T_701) - node T_703 = or(T_702, T_594) - node T_705 = gt(UInt<1>("h01"), last_grant) - node T_706 = and(T_538, T_705) - node T_707 = or(T_706, T_606) - node T_709 = gt(UInt<2>("h02"), last_grant) - node T_710 = and(T_543, T_709) - node T_711 = or(T_710, T_619) - node T_713 = gt(UInt<2>("h03"), last_grant) - node T_714 = and(T_549, T_713) - node T_715 = or(T_714, T_633) - node T_717 = gt(UInt<3>("h04"), last_grant) - node T_718 = and(T_556, T_717) - node T_719 = or(T_718, T_648) - node T_721 = gt(UInt<3>("h05"), last_grant) - node T_722 = and(T_564, T_721) - node T_723 = or(T_722, T_664) - node T_725 = gt(UInt<3>("h06"), last_grant) - node T_726 = and(T_573, T_725) - node T_727 = or(T_726, T_681) - node T_729 = gt(UInt<3>("h07"), last_grant) - node T_730 = and(T_583, T_729) - node T_731 = or(T_730, T_699) - node T_733 = eq(T_446, UInt<1>("h00")) - node T_734 = mux(T_444, T_733, T_703) - node T_735 = and(T_734, io.out.ready) - io.in[0].ready <= T_735 - node T_737 = eq(T_446, UInt<1>("h01")) - node T_738 = mux(T_444, T_737, T_707) - node T_739 = and(T_738, io.out.ready) - io.in[1].ready <= T_739 - node T_741 = eq(T_446, UInt<2>("h02")) - node T_742 = mux(T_444, T_741, T_711) - node T_743 = and(T_742, io.out.ready) - io.in[2].ready <= T_743 - node T_745 = eq(T_446, UInt<2>("h03")) - node T_746 = mux(T_444, T_745, T_715) - node T_747 = and(T_746, io.out.ready) - io.in[3].ready <= T_747 - node T_749 = eq(T_446, UInt<3>("h04")) - node T_750 = mux(T_444, T_749, T_719) - node T_751 = and(T_750, io.out.ready) - io.in[4].ready <= T_751 - node T_753 = eq(T_446, UInt<3>("h05")) - node T_754 = mux(T_444, T_753, T_723) - node T_755 = and(T_754, io.out.ready) - io.in[5].ready <= T_755 - node T_757 = eq(T_446, UInt<3>("h06")) - node T_758 = mux(T_444, T_757, T_727) - node T_759 = and(T_758, io.out.ready) - io.in[6].ready <= T_759 - node T_761 = eq(T_446, UInt<3>("h07")) - node T_762 = mux(T_444, T_761, T_731) - node T_763 = and(T_762, io.out.ready) - io.in[7].ready <= T_763 - reg T_765 : UInt<2>, clk, reset, UInt<2>("h00") - node T_767 = addw(T_765, UInt<1>("h01")) + reg last_grant : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + node T_510 = gt(UInt<1>("h00"), last_grant) + node T_511 = and(io.in[0].valid, T_510) + node T_513 = gt(UInt<1>("h01"), last_grant) + node T_514 = and(io.in[1].valid, T_513) + node T_516 = gt(UInt<2>("h02"), last_grant) + node T_517 = and(io.in[2].valid, T_516) + node T_519 = gt(UInt<2>("h03"), last_grant) + node T_520 = and(io.in[3].valid, T_519) + node T_522 = gt(UInt<3>("h04"), last_grant) + node T_523 = and(io.in[4].valid, T_522) + node T_525 = gt(UInt<3>("h05"), last_grant) + node T_526 = and(io.in[5].valid, T_525) + node T_528 = gt(UInt<3>("h06"), last_grant) + node T_529 = and(io.in[6].valid, T_528) + node T_531 = gt(UInt<3>("h07"), last_grant) + node T_532 = and(io.in[7].valid, T_531) + node T_535 = or(UInt<1>("h00"), T_511) + node T_537 = eq(T_535, UInt<1>("h00")) + node T_539 = or(UInt<1>("h00"), T_511) + node T_540 = or(T_539, T_514) + node T_542 = eq(T_540, UInt<1>("h00")) + node T_544 = or(UInt<1>("h00"), T_511) + node T_545 = or(T_544, T_514) + node T_546 = or(T_545, T_517) + node T_548 = eq(T_546, UInt<1>("h00")) + node T_550 = or(UInt<1>("h00"), T_511) + node T_551 = or(T_550, T_514) + node T_552 = or(T_551, T_517) + node T_553 = or(T_552, T_520) + node T_555 = eq(T_553, UInt<1>("h00")) + node T_557 = or(UInt<1>("h00"), T_511) + node T_558 = or(T_557, T_514) + node T_559 = or(T_558, T_517) + node T_560 = or(T_559, T_520) + node T_561 = or(T_560, T_523) + node T_563 = eq(T_561, UInt<1>("h00")) + node T_565 = or(UInt<1>("h00"), T_511) + node T_566 = or(T_565, T_514) + node T_567 = or(T_566, T_517) + node T_568 = or(T_567, T_520) + node T_569 = or(T_568, T_523) + node T_570 = or(T_569, T_526) + node T_572 = eq(T_570, UInt<1>("h00")) + node T_574 = or(UInt<1>("h00"), T_511) + node T_575 = or(T_574, T_514) + node T_576 = or(T_575, T_517) + node T_577 = or(T_576, T_520) + node T_578 = or(T_577, T_523) + node T_579 = or(T_578, T_526) + node T_580 = or(T_579, T_529) + node T_582 = eq(T_580, UInt<1>("h00")) + node T_584 = or(UInt<1>("h00"), T_511) + node T_585 = or(T_584, T_514) + node T_586 = or(T_585, T_517) + node T_587 = or(T_586, T_520) + node T_588 = or(T_587, T_523) + node T_589 = or(T_588, T_526) + node T_590 = or(T_589, T_529) + node T_591 = or(T_590, T_532) + node T_593 = eq(T_591, UInt<1>("h00")) + node T_595 = or(UInt<1>("h00"), T_511) + node T_596 = or(T_595, T_514) + node T_597 = or(T_596, T_517) + node T_598 = or(T_597, T_520) + node T_599 = or(T_598, T_523) + node T_600 = or(T_599, T_526) + node T_601 = or(T_600, T_529) + node T_602 = or(T_601, T_532) + node T_603 = or(T_602, io.in[0].valid) + node T_605 = eq(T_603, UInt<1>("h00")) + node T_607 = or(UInt<1>("h00"), T_511) + node T_608 = or(T_607, T_514) + node T_609 = or(T_608, T_517) + node T_610 = or(T_609, T_520) + node T_611 = or(T_610, T_523) + node T_612 = or(T_611, T_526) + node T_613 = or(T_612, T_529) + node T_614 = or(T_613, T_532) + node T_615 = or(T_614, io.in[0].valid) + node T_616 = or(T_615, io.in[1].valid) + node T_618 = eq(T_616, UInt<1>("h00")) + node T_620 = or(UInt<1>("h00"), T_511) + node T_621 = or(T_620, T_514) + node T_622 = or(T_621, T_517) + node T_623 = or(T_622, T_520) + node T_624 = or(T_623, T_523) + node T_625 = or(T_624, T_526) + node T_626 = or(T_625, T_529) + node T_627 = or(T_626, T_532) + node T_628 = or(T_627, io.in[0].valid) + node T_629 = or(T_628, io.in[1].valid) + node T_630 = or(T_629, io.in[2].valid) + node T_632 = eq(T_630, UInt<1>("h00")) + node T_634 = or(UInt<1>("h00"), T_511) + node T_635 = or(T_634, T_514) + node T_636 = or(T_635, T_517) + node T_637 = or(T_636, T_520) + node T_638 = or(T_637, T_523) + node T_639 = or(T_638, T_526) + node T_640 = or(T_639, T_529) + node T_641 = or(T_640, T_532) + node T_642 = or(T_641, io.in[0].valid) + node T_643 = or(T_642, io.in[1].valid) + node T_644 = or(T_643, io.in[2].valid) + node T_645 = or(T_644, io.in[3].valid) + node T_647 = eq(T_645, UInt<1>("h00")) + node T_649 = or(UInt<1>("h00"), T_511) + node T_650 = or(T_649, T_514) + node T_651 = or(T_650, T_517) + node T_652 = or(T_651, T_520) + node T_653 = or(T_652, T_523) + node T_654 = or(T_653, T_526) + node T_655 = or(T_654, T_529) + node T_656 = or(T_655, T_532) + node T_657 = or(T_656, io.in[0].valid) + node T_658 = or(T_657, io.in[1].valid) + node T_659 = or(T_658, io.in[2].valid) + node T_660 = or(T_659, io.in[3].valid) + node T_661 = or(T_660, io.in[4].valid) + node T_663 = eq(T_661, UInt<1>("h00")) + node T_665 = or(UInt<1>("h00"), T_511) + node T_666 = or(T_665, T_514) + node T_667 = or(T_666, T_517) + node T_668 = or(T_667, T_520) + node T_669 = or(T_668, T_523) + node T_670 = or(T_669, T_526) + node T_671 = or(T_670, T_529) + node T_672 = or(T_671, T_532) + node T_673 = or(T_672, io.in[0].valid) + node T_674 = or(T_673, io.in[1].valid) + node T_675 = or(T_674, io.in[2].valid) + node T_676 = or(T_675, io.in[3].valid) + node T_677 = or(T_676, io.in[4].valid) + node T_678 = or(T_677, io.in[5].valid) + node T_680 = eq(T_678, UInt<1>("h00")) + node T_682 = or(UInt<1>("h00"), T_511) + node T_683 = or(T_682, T_514) + node T_684 = or(T_683, T_517) + node T_685 = or(T_684, T_520) + node T_686 = or(T_685, T_523) + node T_687 = or(T_686, T_526) + node T_688 = or(T_687, T_529) + node T_689 = or(T_688, T_532) + node T_690 = or(T_689, io.in[0].valid) + node T_691 = or(T_690, io.in[1].valid) + node T_692 = or(T_691, io.in[2].valid) + node T_693 = or(T_692, io.in[3].valid) + node T_694 = or(T_693, io.in[4].valid) + node T_695 = or(T_694, io.in[5].valid) + node T_696 = or(T_695, io.in[6].valid) + node T_698 = eq(T_696, UInt<1>("h00")) + node T_700 = gt(UInt<1>("h00"), last_grant) + node T_701 = and(UInt<1>("h01"), T_700) + node T_702 = or(T_701, T_593) + node T_704 = gt(UInt<1>("h01"), last_grant) + node T_705 = and(T_537, T_704) + node T_706 = or(T_705, T_605) + node T_708 = gt(UInt<2>("h02"), last_grant) + node T_709 = and(T_542, T_708) + node T_710 = or(T_709, T_618) + node T_712 = gt(UInt<2>("h03"), last_grant) + node T_713 = and(T_548, T_712) + node T_714 = or(T_713, T_632) + node T_716 = gt(UInt<3>("h04"), last_grant) + node T_717 = and(T_555, T_716) + node T_718 = or(T_717, T_647) + node T_720 = gt(UInt<3>("h05"), last_grant) + node T_721 = and(T_563, T_720) + node T_722 = or(T_721, T_663) + node T_724 = gt(UInt<3>("h06"), last_grant) + node T_725 = and(T_572, T_724) + node T_726 = or(T_725, T_680) + node T_728 = gt(UInt<3>("h07"), last_grant) + node T_729 = and(T_582, T_728) + node T_730 = or(T_729, T_698) + node T_732 = eq(T_446, UInt<1>("h00")) + node T_733 = mux(T_444, T_732, T_702) + node T_734 = and(T_733, io.out.ready) + io.in[0].ready <= T_734 + node T_736 = eq(T_446, UInt<1>("h01")) + node T_737 = mux(T_444, T_736, T_706) + node T_738 = and(T_737, io.out.ready) + io.in[1].ready <= T_738 + node T_740 = eq(T_446, UInt<2>("h02")) + node T_741 = mux(T_444, T_740, T_710) + node T_742 = and(T_741, io.out.ready) + io.in[2].ready <= T_742 + node T_744 = eq(T_446, UInt<2>("h03")) + node T_745 = mux(T_444, T_744, T_714) + node T_746 = and(T_745, io.out.ready) + io.in[3].ready <= T_746 + node T_748 = eq(T_446, UInt<3>("h04")) + node T_749 = mux(T_444, T_748, T_718) + node T_750 = and(T_749, io.out.ready) + io.in[4].ready <= T_750 + node T_752 = eq(T_446, UInt<3>("h05")) + node T_753 = mux(T_444, T_752, T_722) + node T_754 = and(T_753, io.out.ready) + io.in[5].ready <= T_754 + node T_756 = eq(T_446, UInt<3>("h06")) + node T_757 = mux(T_444, T_756, T_726) + node T_758 = and(T_757, io.out.ready) + io.in[6].ready <= T_758 + node T_760 = eq(T_446, UInt<3>("h07")) + node T_761 = mux(T_444, T_760, T_730) + node T_762 = and(T_761, io.out.ready) + io.in[7].ready <= T_762 + reg T_764 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + node T_766 = add(T_764, UInt<1>("h01")) + node T_767 = tail(T_766, 1) node T_768 = and(io.out.ready, io.out.valid) when T_768 : node T_770 = and(UInt<1>("h01"), io.out.bits.is_builtin_type) @@ -10380,7 +8790,7 @@ circuit Top : node T_778 = or(UInt<1>("h00"), T_776) node T_779 = and(T_770, T_778) when T_779 : - T_765 <= T_767 + T_764 <= T_767 node T_781 = eq(T_444, UInt<1>("h00")) when T_781 : T_444 <= UInt<1>("h01") @@ -10456,1314 +8866,734 @@ circuit Top : input reset : UInt<1> output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}[8], out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}} - io.out.grant.ready <= UInt<1>("h00") - io.out.acquire.bits.data <= UInt<1>("h00") - io.out.acquire.bits.union <= UInt<1>("h00") - io.out.acquire.bits.a_type <= UInt<1>("h00") - io.out.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.out.acquire.bits.addr_beat <= UInt<1>("h00") - io.out.acquire.bits.client_xact_id <= UInt<1>("h00") - io.out.acquire.bits.addr_block <= UInt<1>("h00") - io.out.acquire.valid <= UInt<1>("h00") - io.in[0].grant.bits.data <= UInt<1>("h00") - io.in[0].grant.bits.g_type <= UInt<1>("h00") - io.in[0].grant.bits.is_builtin_type <= UInt<1>("h00") - io.in[0].grant.bits.manager_xact_id <= UInt<1>("h00") - io.in[0].grant.bits.client_xact_id <= UInt<1>("h00") - io.in[0].grant.bits.addr_beat <= UInt<1>("h00") - io.in[0].grant.valid <= UInt<1>("h00") - io.in[0].acquire.ready <= UInt<1>("h00") - io.in[1].grant.bits.data <= UInt<1>("h00") - io.in[1].grant.bits.g_type <= UInt<1>("h00") - io.in[1].grant.bits.is_builtin_type <= UInt<1>("h00") - io.in[1].grant.bits.manager_xact_id <= UInt<1>("h00") - io.in[1].grant.bits.client_xact_id <= UInt<1>("h00") - io.in[1].grant.bits.addr_beat <= UInt<1>("h00") - io.in[1].grant.valid <= UInt<1>("h00") - io.in[1].acquire.ready <= UInt<1>("h00") - io.in[2].grant.bits.data <= UInt<1>("h00") - io.in[2].grant.bits.g_type <= UInt<1>("h00") - io.in[2].grant.bits.is_builtin_type <= UInt<1>("h00") - io.in[2].grant.bits.manager_xact_id <= UInt<1>("h00") - io.in[2].grant.bits.client_xact_id <= UInt<1>("h00") - io.in[2].grant.bits.addr_beat <= UInt<1>("h00") - io.in[2].grant.valid <= UInt<1>("h00") - io.in[2].acquire.ready <= UInt<1>("h00") - io.in[3].grant.bits.data <= UInt<1>("h00") - io.in[3].grant.bits.g_type <= UInt<1>("h00") - io.in[3].grant.bits.is_builtin_type <= UInt<1>("h00") - io.in[3].grant.bits.manager_xact_id <= UInt<1>("h00") - io.in[3].grant.bits.client_xact_id <= UInt<1>("h00") - io.in[3].grant.bits.addr_beat <= UInt<1>("h00") - io.in[3].grant.valid <= UInt<1>("h00") - io.in[3].acquire.ready <= UInt<1>("h00") - io.in[4].grant.bits.data <= UInt<1>("h00") - io.in[4].grant.bits.g_type <= UInt<1>("h00") - io.in[4].grant.bits.is_builtin_type <= UInt<1>("h00") - io.in[4].grant.bits.manager_xact_id <= UInt<1>("h00") - io.in[4].grant.bits.client_xact_id <= UInt<1>("h00") - io.in[4].grant.bits.addr_beat <= UInt<1>("h00") - io.in[4].grant.valid <= UInt<1>("h00") - io.in[4].acquire.ready <= UInt<1>("h00") - io.in[5].grant.bits.data <= UInt<1>("h00") - io.in[5].grant.bits.g_type <= UInt<1>("h00") - io.in[5].grant.bits.is_builtin_type <= UInt<1>("h00") - io.in[5].grant.bits.manager_xact_id <= UInt<1>("h00") - io.in[5].grant.bits.client_xact_id <= UInt<1>("h00") - io.in[5].grant.bits.addr_beat <= UInt<1>("h00") - io.in[5].grant.valid <= UInt<1>("h00") - io.in[5].acquire.ready <= UInt<1>("h00") - io.in[6].grant.bits.data <= UInt<1>("h00") - io.in[6].grant.bits.g_type <= UInt<1>("h00") - io.in[6].grant.bits.is_builtin_type <= UInt<1>("h00") - io.in[6].grant.bits.manager_xact_id <= UInt<1>("h00") - io.in[6].grant.bits.client_xact_id <= UInt<1>("h00") - io.in[6].grant.bits.addr_beat <= UInt<1>("h00") - io.in[6].grant.valid <= UInt<1>("h00") - io.in[6].acquire.ready <= UInt<1>("h00") - io.in[7].grant.bits.data <= UInt<1>("h00") - io.in[7].grant.bits.g_type <= UInt<1>("h00") - io.in[7].grant.bits.is_builtin_type <= UInt<1>("h00") - io.in[7].grant.bits.manager_xact_id <= UInt<1>("h00") - io.in[7].grant.bits.client_xact_id <= UInt<1>("h00") - io.in[7].grant.bits.addr_beat <= UInt<1>("h00") - io.in[7].grant.valid <= UInt<1>("h00") - io.in[7].acquire.ready <= UInt<1>("h00") + io is invalid inst T_1593 of LockingRRArbiter_35 - T_1593.io.out.ready <= UInt<1>("h00") - T_1593.io.in[0].bits.data <= UInt<1>("h00") - T_1593.io.in[0].bits.union <= UInt<1>("h00") - T_1593.io.in[0].bits.a_type <= UInt<1>("h00") - T_1593.io.in[0].bits.is_builtin_type <= UInt<1>("h00") - T_1593.io.in[0].bits.addr_beat <= UInt<1>("h00") - T_1593.io.in[0].bits.client_xact_id <= UInt<1>("h00") - T_1593.io.in[0].bits.addr_block <= UInt<1>("h00") - T_1593.io.in[0].valid <= UInt<1>("h00") - T_1593.io.in[1].bits.data <= UInt<1>("h00") - T_1593.io.in[1].bits.union <= UInt<1>("h00") - T_1593.io.in[1].bits.a_type <= UInt<1>("h00") - T_1593.io.in[1].bits.is_builtin_type <= UInt<1>("h00") - T_1593.io.in[1].bits.addr_beat <= UInt<1>("h00") - T_1593.io.in[1].bits.client_xact_id <= UInt<1>("h00") - T_1593.io.in[1].bits.addr_block <= UInt<1>("h00") - T_1593.io.in[1].valid <= UInt<1>("h00") - T_1593.io.in[2].bits.data <= UInt<1>("h00") - T_1593.io.in[2].bits.union <= UInt<1>("h00") - T_1593.io.in[2].bits.a_type <= UInt<1>("h00") - T_1593.io.in[2].bits.is_builtin_type <= UInt<1>("h00") - T_1593.io.in[2].bits.addr_beat <= UInt<1>("h00") - T_1593.io.in[2].bits.client_xact_id <= UInt<1>("h00") - T_1593.io.in[2].bits.addr_block <= UInt<1>("h00") - T_1593.io.in[2].valid <= UInt<1>("h00") - T_1593.io.in[3].bits.data <= UInt<1>("h00") - T_1593.io.in[3].bits.union <= UInt<1>("h00") - T_1593.io.in[3].bits.a_type <= UInt<1>("h00") - T_1593.io.in[3].bits.is_builtin_type <= UInt<1>("h00") - T_1593.io.in[3].bits.addr_beat <= UInt<1>("h00") - T_1593.io.in[3].bits.client_xact_id <= UInt<1>("h00") - T_1593.io.in[3].bits.addr_block <= UInt<1>("h00") - T_1593.io.in[3].valid <= UInt<1>("h00") - T_1593.io.in[4].bits.data <= UInt<1>("h00") - T_1593.io.in[4].bits.union <= UInt<1>("h00") - T_1593.io.in[4].bits.a_type <= UInt<1>("h00") - T_1593.io.in[4].bits.is_builtin_type <= UInt<1>("h00") - T_1593.io.in[4].bits.addr_beat <= UInt<1>("h00") - T_1593.io.in[4].bits.client_xact_id <= UInt<1>("h00") - T_1593.io.in[4].bits.addr_block <= UInt<1>("h00") - T_1593.io.in[4].valid <= UInt<1>("h00") - T_1593.io.in[5].bits.data <= UInt<1>("h00") - T_1593.io.in[5].bits.union <= UInt<1>("h00") - T_1593.io.in[5].bits.a_type <= UInt<1>("h00") - T_1593.io.in[5].bits.is_builtin_type <= UInt<1>("h00") - T_1593.io.in[5].bits.addr_beat <= UInt<1>("h00") - T_1593.io.in[5].bits.client_xact_id <= UInt<1>("h00") - T_1593.io.in[5].bits.addr_block <= UInt<1>("h00") - T_1593.io.in[5].valid <= UInt<1>("h00") - T_1593.io.in[6].bits.data <= UInt<1>("h00") - T_1593.io.in[6].bits.union <= UInt<1>("h00") - T_1593.io.in[6].bits.a_type <= UInt<1>("h00") - T_1593.io.in[6].bits.is_builtin_type <= UInt<1>("h00") - T_1593.io.in[6].bits.addr_beat <= UInt<1>("h00") - T_1593.io.in[6].bits.client_xact_id <= UInt<1>("h00") - T_1593.io.in[6].bits.addr_block <= UInt<1>("h00") - T_1593.io.in[6].valid <= UInt<1>("h00") - T_1593.io.in[7].bits.data <= UInt<1>("h00") - T_1593.io.in[7].bits.union <= UInt<1>("h00") - T_1593.io.in[7].bits.a_type <= UInt<1>("h00") - T_1593.io.in[7].bits.is_builtin_type <= UInt<1>("h00") - T_1593.io.in[7].bits.addr_beat <= UInt<1>("h00") - T_1593.io.in[7].bits.client_xact_id <= UInt<1>("h00") - T_1593.io.in[7].bits.addr_block <= UInt<1>("h00") - T_1593.io.in[7].valid <= UInt<1>("h00") + T_1593.io is invalid T_1593.clk <= clk T_1593.reset <= reset T_1593.io.in[0].valid <= io.in[0].acquire.valid T_1593.io.in[0].bits <- io.in[0].acquire.bits - node T_1660 = cat(io.in[0].acquire.bits.client_xact_id, UInt<3>("h00")) - T_1593.io.in[0].bits.client_xact_id <= T_1660 + node T_1595 = cat(io.in[0].acquire.bits.client_xact_id, UInt<3>("h00")) + T_1593.io.in[0].bits.client_xact_id <= T_1595 io.in[0].acquire.ready <= T_1593.io.in[0].ready T_1593.io.in[1].valid <= io.in[1].acquire.valid T_1593.io.in[1].bits <- io.in[1].acquire.bits - node T_1662 = cat(io.in[1].acquire.bits.client_xact_id, UInt<3>("h01")) - T_1593.io.in[1].bits.client_xact_id <= T_1662 + node T_1597 = cat(io.in[1].acquire.bits.client_xact_id, UInt<3>("h01")) + T_1593.io.in[1].bits.client_xact_id <= T_1597 io.in[1].acquire.ready <= T_1593.io.in[1].ready T_1593.io.in[2].valid <= io.in[2].acquire.valid T_1593.io.in[2].bits <- io.in[2].acquire.bits - node T_1664 = cat(io.in[2].acquire.bits.client_xact_id, UInt<3>("h02")) - T_1593.io.in[2].bits.client_xact_id <= T_1664 + node T_1599 = cat(io.in[2].acquire.bits.client_xact_id, UInt<3>("h02")) + T_1593.io.in[2].bits.client_xact_id <= T_1599 io.in[2].acquire.ready <= T_1593.io.in[2].ready T_1593.io.in[3].valid <= io.in[3].acquire.valid T_1593.io.in[3].bits <- io.in[3].acquire.bits - node T_1666 = cat(io.in[3].acquire.bits.client_xact_id, UInt<3>("h03")) - T_1593.io.in[3].bits.client_xact_id <= T_1666 + node T_1601 = cat(io.in[3].acquire.bits.client_xact_id, UInt<3>("h03")) + T_1593.io.in[3].bits.client_xact_id <= T_1601 io.in[3].acquire.ready <= T_1593.io.in[3].ready T_1593.io.in[4].valid <= io.in[4].acquire.valid T_1593.io.in[4].bits <- io.in[4].acquire.bits - node T_1668 = cat(io.in[4].acquire.bits.client_xact_id, UInt<3>("h04")) - T_1593.io.in[4].bits.client_xact_id <= T_1668 + node T_1603 = cat(io.in[4].acquire.bits.client_xact_id, UInt<3>("h04")) + T_1593.io.in[4].bits.client_xact_id <= T_1603 io.in[4].acquire.ready <= T_1593.io.in[4].ready T_1593.io.in[5].valid <= io.in[5].acquire.valid T_1593.io.in[5].bits <- io.in[5].acquire.bits - node T_1670 = cat(io.in[5].acquire.bits.client_xact_id, UInt<3>("h05")) - T_1593.io.in[5].bits.client_xact_id <= T_1670 + node T_1605 = cat(io.in[5].acquire.bits.client_xact_id, UInt<3>("h05")) + T_1593.io.in[5].bits.client_xact_id <= T_1605 io.in[5].acquire.ready <= T_1593.io.in[5].ready T_1593.io.in[6].valid <= io.in[6].acquire.valid T_1593.io.in[6].bits <- io.in[6].acquire.bits - node T_1672 = cat(io.in[6].acquire.bits.client_xact_id, UInt<3>("h06")) - T_1593.io.in[6].bits.client_xact_id <= T_1672 + node T_1607 = cat(io.in[6].acquire.bits.client_xact_id, UInt<3>("h06")) + T_1593.io.in[6].bits.client_xact_id <= T_1607 io.in[6].acquire.ready <= T_1593.io.in[6].ready T_1593.io.in[7].valid <= io.in[7].acquire.valid T_1593.io.in[7].bits <- io.in[7].acquire.bits - node T_1674 = cat(io.in[7].acquire.bits.client_xact_id, UInt<3>("h07")) - T_1593.io.in[7].bits.client_xact_id <= T_1674 + node T_1609 = cat(io.in[7].acquire.bits.client_xact_id, UInt<3>("h07")) + T_1593.io.in[7].bits.client_xact_id <= T_1609 io.in[7].acquire.ready <= T_1593.io.in[7].ready io.out.acquire <- T_1593.io.out io.out.grant.ready <= UInt<1>("h00") io.in[0].grant.valid <= UInt<1>("h00") - node T_1677 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1679 = eq(T_1677, UInt<1>("h00")) - when T_1679 : + node T_1612 = bits(io.out.grant.bits.client_xact_id, 2, 0) + node T_1614 = eq(T_1612, UInt<1>("h00")) + when T_1614 : io.in[0].grant.valid <= io.out.grant.valid io.out.grant.ready <= io.in[0].grant.ready skip io.in[0].grant.bits <- io.out.grant.bits - node T_1680 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[0].grant.bits.client_xact_id <= T_1680 + node T_1615 = shr(io.out.grant.bits.client_xact_id, 3) + io.in[0].grant.bits.client_xact_id <= T_1615 io.in[1].grant.valid <= UInt<1>("h00") - node T_1682 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1684 = eq(T_1682, UInt<1>("h01")) - when T_1684 : + node T_1617 = bits(io.out.grant.bits.client_xact_id, 2, 0) + node T_1619 = eq(T_1617, UInt<1>("h01")) + when T_1619 : io.in[1].grant.valid <= io.out.grant.valid io.out.grant.ready <= io.in[1].grant.ready skip io.in[1].grant.bits <- io.out.grant.bits - node T_1685 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[1].grant.bits.client_xact_id <= T_1685 + node T_1620 = shr(io.out.grant.bits.client_xact_id, 3) + io.in[1].grant.bits.client_xact_id <= T_1620 io.in[2].grant.valid <= UInt<1>("h00") - node T_1687 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1689 = eq(T_1687, UInt<2>("h02")) - when T_1689 : + node T_1622 = bits(io.out.grant.bits.client_xact_id, 2, 0) + node T_1624 = eq(T_1622, UInt<2>("h02")) + when T_1624 : io.in[2].grant.valid <= io.out.grant.valid io.out.grant.ready <= io.in[2].grant.ready skip io.in[2].grant.bits <- io.out.grant.bits - node T_1690 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[2].grant.bits.client_xact_id <= T_1690 + node T_1625 = shr(io.out.grant.bits.client_xact_id, 3) + io.in[2].grant.bits.client_xact_id <= T_1625 io.in[3].grant.valid <= UInt<1>("h00") - node T_1692 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1694 = eq(T_1692, UInt<2>("h03")) - when T_1694 : + node T_1627 = bits(io.out.grant.bits.client_xact_id, 2, 0) + node T_1629 = eq(T_1627, UInt<2>("h03")) + when T_1629 : io.in[3].grant.valid <= io.out.grant.valid io.out.grant.ready <= io.in[3].grant.ready skip io.in[3].grant.bits <- io.out.grant.bits - node T_1695 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[3].grant.bits.client_xact_id <= T_1695 + node T_1630 = shr(io.out.grant.bits.client_xact_id, 3) + io.in[3].grant.bits.client_xact_id <= T_1630 io.in[4].grant.valid <= UInt<1>("h00") - node T_1697 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1699 = eq(T_1697, UInt<3>("h04")) - when T_1699 : + node T_1632 = bits(io.out.grant.bits.client_xact_id, 2, 0) + node T_1634 = eq(T_1632, UInt<3>("h04")) + when T_1634 : io.in[4].grant.valid <= io.out.grant.valid io.out.grant.ready <= io.in[4].grant.ready skip io.in[4].grant.bits <- io.out.grant.bits - node T_1700 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[4].grant.bits.client_xact_id <= T_1700 + node T_1635 = shr(io.out.grant.bits.client_xact_id, 3) + io.in[4].grant.bits.client_xact_id <= T_1635 io.in[5].grant.valid <= UInt<1>("h00") - node T_1702 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1704 = eq(T_1702, UInt<3>("h05")) - when T_1704 : + node T_1637 = bits(io.out.grant.bits.client_xact_id, 2, 0) + node T_1639 = eq(T_1637, UInt<3>("h05")) + when T_1639 : io.in[5].grant.valid <= io.out.grant.valid io.out.grant.ready <= io.in[5].grant.ready skip io.in[5].grant.bits <- io.out.grant.bits - node T_1705 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[5].grant.bits.client_xact_id <= T_1705 + node T_1640 = shr(io.out.grant.bits.client_xact_id, 3) + io.in[5].grant.bits.client_xact_id <= T_1640 io.in[6].grant.valid <= UInt<1>("h00") - node T_1707 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1709 = eq(T_1707, UInt<3>("h06")) - when T_1709 : + node T_1642 = bits(io.out.grant.bits.client_xact_id, 2, 0) + node T_1644 = eq(T_1642, UInt<3>("h06")) + when T_1644 : io.in[6].grant.valid <= io.out.grant.valid io.out.grant.ready <= io.in[6].grant.ready skip io.in[6].grant.bits <- io.out.grant.bits - node T_1710 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[6].grant.bits.client_xact_id <= T_1710 + node T_1645 = shr(io.out.grant.bits.client_xact_id, 3) + io.in[6].grant.bits.client_xact_id <= T_1645 io.in[7].grant.valid <= UInt<1>("h00") - node T_1712 = bits(io.out.grant.bits.client_xact_id, 2, 0) - node T_1714 = eq(T_1712, UInt<3>("h07")) - when T_1714 : + node T_1647 = bits(io.out.grant.bits.client_xact_id, 2, 0) + node T_1649 = eq(T_1647, UInt<3>("h07")) + when T_1649 : io.in[7].grant.valid <= io.out.grant.valid io.out.grant.ready <= io.in[7].grant.ready skip io.in[7].grant.bits <- io.out.grant.bits - node T_1715 = shr(io.out.grant.bits.client_xact_id, 3) - io.in[7].grant.bits.client_xact_id <= T_1715 + node T_1650 = shr(io.out.grant.bits.client_xact_id, 3) + io.in[7].grant.bits.client_xact_id <= T_1650 module L2BroadcastHub : input clk : Clock input reset : UInt<1> output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}} - io.outer.grant.ready <= UInt<1>("h00") - io.outer.acquire.bits.data <= UInt<1>("h00") - io.outer.acquire.bits.union <= UInt<1>("h00") - io.outer.acquire.bits.a_type <= UInt<1>("h00") - io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.outer.acquire.bits.addr_beat <= UInt<1>("h00") - io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") - io.outer.acquire.bits.addr_block <= UInt<1>("h00") - io.outer.acquire.valid <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.probe.bits.client_id <= UInt<1>("h00") - io.inner.probe.bits.p_type <= UInt<1>("h00") - io.inner.probe.bits.addr_block <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - io.inner.finish.ready <= UInt<1>("h00") - io.inner.grant.bits.client_id <= UInt<1>("h00") - io.inner.grant.bits.data <= UInt<1>("h00") - io.inner.grant.bits.g_type <= UInt<1>("h00") - io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") - io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") - io.inner.grant.bits.client_xact_id <= UInt<1>("h00") - io.inner.grant.bits.addr_beat <= UInt<1>("h00") - io.inner.grant.valid <= UInt<1>("h00") - io.inner.acquire.ready <= UInt<1>("h00") + io is invalid inst T_1060 of BroadcastVoluntaryReleaseTracker - T_1060.io.outer.grant.bits.data <= UInt<1>("h00") - T_1060.io.outer.grant.bits.g_type <= UInt<1>("h00") - T_1060.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") - T_1060.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") - T_1060.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") - T_1060.io.outer.grant.bits.addr_beat <= UInt<1>("h00") - T_1060.io.outer.grant.valid <= UInt<1>("h00") - T_1060.io.outer.acquire.ready <= UInt<1>("h00") - T_1060.io.incoherent[0] <= UInt<1>("h00") - T_1060.io.inner.release.bits.client_id <= UInt<1>("h00") - T_1060.io.inner.release.bits.data <= UInt<1>("h00") - T_1060.io.inner.release.bits.r_type <= UInt<1>("h00") - T_1060.io.inner.release.bits.voluntary <= UInt<1>("h00") - T_1060.io.inner.release.bits.client_xact_id <= UInt<1>("h00") - T_1060.io.inner.release.bits.addr_block <= UInt<1>("h00") - T_1060.io.inner.release.bits.addr_beat <= UInt<1>("h00") - T_1060.io.inner.release.valid <= UInt<1>("h00") - T_1060.io.inner.probe.ready <= UInt<1>("h00") - T_1060.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") - T_1060.io.inner.finish.valid <= UInt<1>("h00") - T_1060.io.inner.grant.ready <= UInt<1>("h00") - T_1060.io.inner.acquire.bits.client_id <= UInt<1>("h00") - T_1060.io.inner.acquire.bits.data <= UInt<1>("h00") - T_1060.io.inner.acquire.bits.union <= UInt<1>("h00") - T_1060.io.inner.acquire.bits.a_type <= UInt<1>("h00") - T_1060.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_1060.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") - T_1060.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") - T_1060.io.inner.acquire.bits.addr_block <= UInt<1>("h00") - T_1060.io.inner.acquire.valid <= UInt<1>("h00") + T_1060.io is invalid T_1060.clk <= clk T_1060.reset <= reset - inst T_1091 of BroadcastAcquireTracker - T_1091.io.outer.grant.bits.data <= UInt<1>("h00") - T_1091.io.outer.grant.bits.g_type <= UInt<1>("h00") - T_1091.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") - T_1091.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") - T_1091.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") - T_1091.io.outer.grant.bits.addr_beat <= UInt<1>("h00") - T_1091.io.outer.grant.valid <= UInt<1>("h00") - T_1091.io.outer.acquire.ready <= UInt<1>("h00") - T_1091.io.incoherent[0] <= UInt<1>("h00") - T_1091.io.inner.release.bits.client_id <= UInt<1>("h00") - T_1091.io.inner.release.bits.data <= UInt<1>("h00") - T_1091.io.inner.release.bits.r_type <= UInt<1>("h00") - T_1091.io.inner.release.bits.voluntary <= UInt<1>("h00") - T_1091.io.inner.release.bits.client_xact_id <= UInt<1>("h00") - T_1091.io.inner.release.bits.addr_block <= UInt<1>("h00") - T_1091.io.inner.release.bits.addr_beat <= UInt<1>("h00") - T_1091.io.inner.release.valid <= UInt<1>("h00") - T_1091.io.inner.probe.ready <= UInt<1>("h00") - T_1091.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") - T_1091.io.inner.finish.valid <= UInt<1>("h00") - T_1091.io.inner.grant.ready <= UInt<1>("h00") - T_1091.io.inner.acquire.bits.client_id <= UInt<1>("h00") - T_1091.io.inner.acquire.bits.data <= UInt<1>("h00") - T_1091.io.inner.acquire.bits.union <= UInt<1>("h00") - T_1091.io.inner.acquire.bits.a_type <= UInt<1>("h00") - T_1091.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_1091.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") - T_1091.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") - T_1091.io.inner.acquire.bits.addr_block <= UInt<1>("h00") - T_1091.io.inner.acquire.valid <= UInt<1>("h00") - T_1091.clk <= clk - T_1091.reset <= reset - inst T_1122 of BroadcastAcquireTracker_27 - T_1122.io.outer.grant.bits.data <= UInt<1>("h00") - T_1122.io.outer.grant.bits.g_type <= UInt<1>("h00") - T_1122.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") - T_1122.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") - T_1122.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") - T_1122.io.outer.grant.bits.addr_beat <= UInt<1>("h00") - T_1122.io.outer.grant.valid <= UInt<1>("h00") - T_1122.io.outer.acquire.ready <= UInt<1>("h00") - T_1122.io.incoherent[0] <= UInt<1>("h00") - T_1122.io.inner.release.bits.client_id <= UInt<1>("h00") - T_1122.io.inner.release.bits.data <= UInt<1>("h00") - T_1122.io.inner.release.bits.r_type <= UInt<1>("h00") - T_1122.io.inner.release.bits.voluntary <= UInt<1>("h00") - T_1122.io.inner.release.bits.client_xact_id <= UInt<1>("h00") - T_1122.io.inner.release.bits.addr_block <= UInt<1>("h00") - T_1122.io.inner.release.bits.addr_beat <= UInt<1>("h00") - T_1122.io.inner.release.valid <= UInt<1>("h00") - T_1122.io.inner.probe.ready <= UInt<1>("h00") - T_1122.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") - T_1122.io.inner.finish.valid <= UInt<1>("h00") - T_1122.io.inner.grant.ready <= UInt<1>("h00") - T_1122.io.inner.acquire.bits.client_id <= UInt<1>("h00") - T_1122.io.inner.acquire.bits.data <= UInt<1>("h00") - T_1122.io.inner.acquire.bits.union <= UInt<1>("h00") - T_1122.io.inner.acquire.bits.a_type <= UInt<1>("h00") - T_1122.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_1122.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") - T_1122.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") - T_1122.io.inner.acquire.bits.addr_block <= UInt<1>("h00") - T_1122.io.inner.acquire.valid <= UInt<1>("h00") - T_1122.clk <= clk - T_1122.reset <= reset - inst T_1153 of BroadcastAcquireTracker_28 - T_1153.io.outer.grant.bits.data <= UInt<1>("h00") - T_1153.io.outer.grant.bits.g_type <= UInt<1>("h00") - T_1153.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") - T_1153.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") - T_1153.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") - T_1153.io.outer.grant.bits.addr_beat <= UInt<1>("h00") - T_1153.io.outer.grant.valid <= UInt<1>("h00") - T_1153.io.outer.acquire.ready <= UInt<1>("h00") - T_1153.io.incoherent[0] <= UInt<1>("h00") - T_1153.io.inner.release.bits.client_id <= UInt<1>("h00") - T_1153.io.inner.release.bits.data <= UInt<1>("h00") - T_1153.io.inner.release.bits.r_type <= UInt<1>("h00") - T_1153.io.inner.release.bits.voluntary <= UInt<1>("h00") - T_1153.io.inner.release.bits.client_xact_id <= UInt<1>("h00") - T_1153.io.inner.release.bits.addr_block <= UInt<1>("h00") - T_1153.io.inner.release.bits.addr_beat <= UInt<1>("h00") - T_1153.io.inner.release.valid <= UInt<1>("h00") - T_1153.io.inner.probe.ready <= UInt<1>("h00") - T_1153.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") - T_1153.io.inner.finish.valid <= UInt<1>("h00") - T_1153.io.inner.grant.ready <= UInt<1>("h00") - T_1153.io.inner.acquire.bits.client_id <= UInt<1>("h00") - T_1153.io.inner.acquire.bits.data <= UInt<1>("h00") - T_1153.io.inner.acquire.bits.union <= UInt<1>("h00") - T_1153.io.inner.acquire.bits.a_type <= UInt<1>("h00") - T_1153.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_1153.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") - T_1153.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") - T_1153.io.inner.acquire.bits.addr_block <= UInt<1>("h00") - T_1153.io.inner.acquire.valid <= UInt<1>("h00") - T_1153.clk <= clk - T_1153.reset <= reset - inst T_1184 of BroadcastAcquireTracker_29 - T_1184.io.outer.grant.bits.data <= UInt<1>("h00") - T_1184.io.outer.grant.bits.g_type <= UInt<1>("h00") - T_1184.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") - T_1184.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") - T_1184.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") - T_1184.io.outer.grant.bits.addr_beat <= UInt<1>("h00") - T_1184.io.outer.grant.valid <= UInt<1>("h00") - T_1184.io.outer.acquire.ready <= UInt<1>("h00") - T_1184.io.incoherent[0] <= UInt<1>("h00") - T_1184.io.inner.release.bits.client_id <= UInt<1>("h00") - T_1184.io.inner.release.bits.data <= UInt<1>("h00") - T_1184.io.inner.release.bits.r_type <= UInt<1>("h00") - T_1184.io.inner.release.bits.voluntary <= UInt<1>("h00") - T_1184.io.inner.release.bits.client_xact_id <= UInt<1>("h00") - T_1184.io.inner.release.bits.addr_block <= UInt<1>("h00") - T_1184.io.inner.release.bits.addr_beat <= UInt<1>("h00") - T_1184.io.inner.release.valid <= UInt<1>("h00") - T_1184.io.inner.probe.ready <= UInt<1>("h00") - T_1184.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") - T_1184.io.inner.finish.valid <= UInt<1>("h00") - T_1184.io.inner.grant.ready <= UInt<1>("h00") - T_1184.io.inner.acquire.bits.client_id <= UInt<1>("h00") - T_1184.io.inner.acquire.bits.data <= UInt<1>("h00") - T_1184.io.inner.acquire.bits.union <= UInt<1>("h00") - T_1184.io.inner.acquire.bits.a_type <= UInt<1>("h00") - T_1184.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_1184.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") - T_1184.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") - T_1184.io.inner.acquire.bits.addr_block <= UInt<1>("h00") - T_1184.io.inner.acquire.valid <= UInt<1>("h00") - T_1184.clk <= clk - T_1184.reset <= reset - inst T_1215 of BroadcastAcquireTracker_30 - T_1215.io.outer.grant.bits.data <= UInt<1>("h00") - T_1215.io.outer.grant.bits.g_type <= UInt<1>("h00") - T_1215.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") - T_1215.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") - T_1215.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") - T_1215.io.outer.grant.bits.addr_beat <= UInt<1>("h00") - T_1215.io.outer.grant.valid <= UInt<1>("h00") - T_1215.io.outer.acquire.ready <= UInt<1>("h00") - T_1215.io.incoherent[0] <= UInt<1>("h00") - T_1215.io.inner.release.bits.client_id <= UInt<1>("h00") - T_1215.io.inner.release.bits.data <= UInt<1>("h00") - T_1215.io.inner.release.bits.r_type <= UInt<1>("h00") - T_1215.io.inner.release.bits.voluntary <= UInt<1>("h00") - T_1215.io.inner.release.bits.client_xact_id <= UInt<1>("h00") - T_1215.io.inner.release.bits.addr_block <= UInt<1>("h00") - T_1215.io.inner.release.bits.addr_beat <= UInt<1>("h00") - T_1215.io.inner.release.valid <= UInt<1>("h00") - T_1215.io.inner.probe.ready <= UInt<1>("h00") - T_1215.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") - T_1215.io.inner.finish.valid <= UInt<1>("h00") - T_1215.io.inner.grant.ready <= UInt<1>("h00") - T_1215.io.inner.acquire.bits.client_id <= UInt<1>("h00") - T_1215.io.inner.acquire.bits.data <= UInt<1>("h00") - T_1215.io.inner.acquire.bits.union <= UInt<1>("h00") - T_1215.io.inner.acquire.bits.a_type <= UInt<1>("h00") - T_1215.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_1215.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") - T_1215.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") - T_1215.io.inner.acquire.bits.addr_block <= UInt<1>("h00") - T_1215.io.inner.acquire.valid <= UInt<1>("h00") - T_1215.clk <= clk - T_1215.reset <= reset - inst T_1246 of BroadcastAcquireTracker_31 - T_1246.io.outer.grant.bits.data <= UInt<1>("h00") - T_1246.io.outer.grant.bits.g_type <= UInt<1>("h00") - T_1246.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") - T_1246.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") - T_1246.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") - T_1246.io.outer.grant.bits.addr_beat <= UInt<1>("h00") - T_1246.io.outer.grant.valid <= UInt<1>("h00") - T_1246.io.outer.acquire.ready <= UInt<1>("h00") - T_1246.io.incoherent[0] <= UInt<1>("h00") - T_1246.io.inner.release.bits.client_id <= UInt<1>("h00") - T_1246.io.inner.release.bits.data <= UInt<1>("h00") - T_1246.io.inner.release.bits.r_type <= UInt<1>("h00") - T_1246.io.inner.release.bits.voluntary <= UInt<1>("h00") - T_1246.io.inner.release.bits.client_xact_id <= UInt<1>("h00") - T_1246.io.inner.release.bits.addr_block <= UInt<1>("h00") - T_1246.io.inner.release.bits.addr_beat <= UInt<1>("h00") - T_1246.io.inner.release.valid <= UInt<1>("h00") - T_1246.io.inner.probe.ready <= UInt<1>("h00") - T_1246.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") - T_1246.io.inner.finish.valid <= UInt<1>("h00") - T_1246.io.inner.grant.ready <= UInt<1>("h00") - T_1246.io.inner.acquire.bits.client_id <= UInt<1>("h00") - T_1246.io.inner.acquire.bits.data <= UInt<1>("h00") - T_1246.io.inner.acquire.bits.union <= UInt<1>("h00") - T_1246.io.inner.acquire.bits.a_type <= UInt<1>("h00") - T_1246.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_1246.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") - T_1246.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") - T_1246.io.inner.acquire.bits.addr_block <= UInt<1>("h00") - T_1246.io.inner.acquire.valid <= UInt<1>("h00") - T_1246.clk <= clk - T_1246.reset <= reset - inst T_1277 of BroadcastAcquireTracker_32 - T_1277.io.outer.grant.bits.data <= UInt<1>("h00") - T_1277.io.outer.grant.bits.g_type <= UInt<1>("h00") - T_1277.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") - T_1277.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") - T_1277.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") - T_1277.io.outer.grant.bits.addr_beat <= UInt<1>("h00") - T_1277.io.outer.grant.valid <= UInt<1>("h00") - T_1277.io.outer.acquire.ready <= UInt<1>("h00") - T_1277.io.incoherent[0] <= UInt<1>("h00") - T_1277.io.inner.release.bits.client_id <= UInt<1>("h00") - T_1277.io.inner.release.bits.data <= UInt<1>("h00") - T_1277.io.inner.release.bits.r_type <= UInt<1>("h00") - T_1277.io.inner.release.bits.voluntary <= UInt<1>("h00") - T_1277.io.inner.release.bits.client_xact_id <= UInt<1>("h00") - T_1277.io.inner.release.bits.addr_block <= UInt<1>("h00") - T_1277.io.inner.release.bits.addr_beat <= UInt<1>("h00") - T_1277.io.inner.release.valid <= UInt<1>("h00") - T_1277.io.inner.probe.ready <= UInt<1>("h00") - T_1277.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") - T_1277.io.inner.finish.valid <= UInt<1>("h00") - T_1277.io.inner.grant.ready <= UInt<1>("h00") - T_1277.io.inner.acquire.bits.client_id <= UInt<1>("h00") - T_1277.io.inner.acquire.bits.data <= UInt<1>("h00") - T_1277.io.inner.acquire.bits.union <= UInt<1>("h00") - T_1277.io.inner.acquire.bits.a_type <= UInt<1>("h00") - T_1277.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_1277.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") - T_1277.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") - T_1277.io.inner.acquire.bits.addr_block <= UInt<1>("h00") - T_1277.io.inner.acquire.valid <= UInt<1>("h00") - T_1277.clk <= clk - T_1277.reset <= reset + inst T_1061 of BroadcastAcquireTracker + T_1061.io is invalid + T_1061.clk <= clk + T_1061.reset <= reset + inst T_1062 of BroadcastAcquireTracker_27 + T_1062.io is invalid + T_1062.clk <= clk + T_1062.reset <= reset + inst T_1063 of BroadcastAcquireTracker_28 + T_1063.io is invalid + T_1063.clk <= clk + T_1063.reset <= reset + inst T_1064 of BroadcastAcquireTracker_29 + T_1064.io is invalid + T_1064.clk <= clk + T_1064.reset <= reset + inst T_1065 of BroadcastAcquireTracker_30 + T_1065.io is invalid + T_1065.clk <= clk + T_1065.reset <= reset + inst T_1066 of BroadcastAcquireTracker_31 + T_1066.io is invalid + T_1066.clk <= clk + T_1066.reset <= reset + inst T_1067 of BroadcastAcquireTracker_32 + T_1067.io is invalid + T_1067.clk <= clk + T_1067.reset <= reset T_1060.io.incoherent <= io.incoherent - T_1091.io.incoherent <= io.incoherent - T_1122.io.incoherent <= io.incoherent - T_1153.io.incoherent <= io.incoherent - T_1184.io.incoherent <= io.incoherent - T_1215.io.incoherent <= io.incoherent - T_1246.io.incoherent <= io.incoherent - T_1277.io.incoherent <= io.incoherent - reg sdq : UInt<128>[4], clk, UInt<1>("h00"), sdq - reg sdq_val : UInt<4>, clk, reset, UInt<4>("h00") - node T_1325 = not(sdq_val) - node T_1326 = bit(T_1325, 0) - node T_1327 = bit(T_1325, 1) - node T_1328 = bit(T_1325, 2) - node T_1329 = bit(T_1325, 3) - wire T_1331 : UInt<1>[4] - T_1331[0] <= T_1326 - T_1331[1] <= T_1327 - T_1331[2] <= T_1328 - T_1331[3] <= T_1329 - node T_1341 = mux(T_1331[2], UInt<2>("h02"), UInt<2>("h03")) - node T_1342 = mux(T_1331[1], UInt<1>("h01"), T_1341) - node sdq_alloc_id = mux(T_1331[0], UInt<1>("h00"), T_1342) - node T_1344 = not(sdq_val) - node T_1346 = eq(T_1344, UInt<1>("h00")) - node sdq_rdy = eq(T_1346, UInt<1>("h00")) - node T_1349 = and(io.inner.acquire.ready, io.inner.acquire.valid) - wire T_1354 : UInt<3>[3] - T_1354[0] <= UInt<3>("h02") - T_1354[1] <= UInt<3>("h03") - T_1354[2] <= UInt<3>("h04") - node T_1359 = eq(T_1354[0], io.inner.acquire.bits.a_type) - node T_1360 = eq(T_1354[1], io.inner.acquire.bits.a_type) - node T_1361 = eq(T_1354[2], io.inner.acquire.bits.a_type) - node T_1363 = or(UInt<1>("h00"), T_1359) - node T_1364 = or(T_1363, T_1360) - node T_1365 = or(T_1364, T_1361) - node T_1366 = and(io.inner.acquire.bits.is_builtin_type, T_1365) - node sdq_enq = and(T_1349, T_1366) + T_1061.io.incoherent <= io.incoherent + T_1062.io.incoherent <= io.incoherent + T_1063.io.incoherent <= io.incoherent + T_1064.io.incoherent <= io.incoherent + T_1065.io.incoherent <= io.incoherent + T_1066.io.incoherent <= io.incoherent + T_1067.io.incoherent <= io.incoherent + reg sdq : UInt<128>[4], clk + reg sdq_val : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) + node T_1085 = not(sdq_val) + node T_1086 = bits(T_1085, 0, 0) + node T_1087 = bits(T_1085, 1, 1) + node T_1088 = bits(T_1085, 2, 2) + node T_1089 = bits(T_1085, 3, 3) + wire T_1091 : UInt<1>[4] + T_1091[0] <= T_1086 + T_1091[1] <= T_1087 + T_1091[2] <= T_1088 + T_1091[3] <= T_1089 + node T_1101 = mux(T_1091[2], UInt<2>("h02"), UInt<2>("h03")) + node T_1102 = mux(T_1091[1], UInt<1>("h01"), T_1101) + node sdq_alloc_id = mux(T_1091[0], UInt<1>("h00"), T_1102) + node T_1104 = not(sdq_val) + node T_1106 = eq(T_1104, UInt<1>("h00")) + node sdq_rdy = eq(T_1106, UInt<1>("h00")) + node T_1109 = and(io.inner.acquire.ready, io.inner.acquire.valid) + wire T_1114 : UInt<3>[3] + T_1114[0] <= UInt<3>("h02") + T_1114[1] <= UInt<3>("h03") + T_1114[2] <= UInt<3>("h04") + node T_1119 = eq(T_1114[0], io.inner.acquire.bits.a_type) + node T_1120 = eq(T_1114[1], io.inner.acquire.bits.a_type) + node T_1121 = eq(T_1114[2], io.inner.acquire.bits.a_type) + node T_1123 = or(UInt<1>("h00"), T_1119) + node T_1124 = or(T_1123, T_1120) + node T_1125 = or(T_1124, T_1121) + node T_1126 = and(io.inner.acquire.bits.is_builtin_type, T_1125) + node sdq_enq = and(T_1109, T_1126) when sdq_enq : sdq[sdq_alloc_id] <= io.inner.acquire.bits.data skip - wire T_1370 : UInt<1>[8] - T_1370[0] <= T_1060.io.has_acquire_conflict - T_1370[1] <= T_1091.io.has_acquire_conflict - T_1370[2] <= T_1122.io.has_acquire_conflict - T_1370[3] <= T_1153.io.has_acquire_conflict - T_1370[4] <= T_1184.io.has_acquire_conflict - T_1370[5] <= T_1215.io.has_acquire_conflict - T_1370[6] <= T_1246.io.has_acquire_conflict - T_1370[7] <= T_1277.io.has_acquire_conflict - node T_1380 = cat(T_1370[7], T_1370[6]) - node T_1381 = cat(T_1370[5], T_1370[4]) - node T_1382 = cat(T_1380, T_1381) - node T_1383 = cat(T_1370[3], T_1370[2]) - node T_1384 = cat(T_1370[1], T_1370[0]) - node T_1385 = cat(T_1383, T_1384) - node acquireConflicts = cat(T_1382, T_1385) - wire T_1388 : UInt<1>[8] - T_1388[0] <= T_1060.io.has_acquire_match - T_1388[1] <= T_1091.io.has_acquire_match - T_1388[2] <= T_1122.io.has_acquire_match - T_1388[3] <= T_1153.io.has_acquire_match - T_1388[4] <= T_1184.io.has_acquire_match - T_1388[5] <= T_1215.io.has_acquire_match - T_1388[6] <= T_1246.io.has_acquire_match - T_1388[7] <= T_1277.io.has_acquire_match - node T_1398 = cat(T_1388[7], T_1388[6]) - node T_1399 = cat(T_1388[5], T_1388[4]) - node T_1400 = cat(T_1398, T_1399) - node T_1401 = cat(T_1388[3], T_1388[2]) - node T_1402 = cat(T_1388[1], T_1388[0]) - node T_1403 = cat(T_1401, T_1402) - node acquireMatches = cat(T_1400, T_1403) - wire T_1406 : UInt<1>[8] - T_1406[0] <= T_1060.io.inner.acquire.ready - T_1406[1] <= T_1091.io.inner.acquire.ready - T_1406[2] <= T_1122.io.inner.acquire.ready - T_1406[3] <= T_1153.io.inner.acquire.ready - T_1406[4] <= T_1184.io.inner.acquire.ready - T_1406[5] <= T_1215.io.inner.acquire.ready - T_1406[6] <= T_1246.io.inner.acquire.ready - T_1406[7] <= T_1277.io.inner.acquire.ready - node T_1416 = cat(T_1406[7], T_1406[6]) - node T_1417 = cat(T_1406[5], T_1406[4]) - node T_1418 = cat(T_1416, T_1417) - node T_1419 = cat(T_1406[3], T_1406[2]) - node T_1420 = cat(T_1406[1], T_1406[0]) - node T_1421 = cat(T_1419, T_1420) - node acquireReadys = cat(T_1418, T_1421) - node T_1424 = neq(acquireMatches, UInt<1>("h00")) - node T_1425 = bit(acquireMatches, 0) - node T_1426 = bit(acquireMatches, 1) - node T_1427 = bit(acquireMatches, 2) - node T_1428 = bit(acquireMatches, 3) - node T_1429 = bit(acquireMatches, 4) - node T_1430 = bit(acquireMatches, 5) - node T_1431 = bit(acquireMatches, 6) - node T_1432 = bit(acquireMatches, 7) - wire T_1434 : UInt<1>[8] - T_1434[0] <= T_1425 - T_1434[1] <= T_1426 - T_1434[2] <= T_1427 - T_1434[3] <= T_1428 - T_1434[4] <= T_1429 - T_1434[5] <= T_1430 - T_1434[6] <= T_1431 - T_1434[7] <= T_1432 - node T_1452 = mux(T_1434[6], UInt<3>("h06"), UInt<3>("h07")) - node T_1453 = mux(T_1434[5], UInt<3>("h05"), T_1452) - node T_1454 = mux(T_1434[4], UInt<3>("h04"), T_1453) - node T_1455 = mux(T_1434[3], UInt<2>("h03"), T_1454) - node T_1456 = mux(T_1434[2], UInt<2>("h02"), T_1455) - node T_1457 = mux(T_1434[1], UInt<1>("h01"), T_1456) - node T_1458 = mux(T_1434[0], UInt<1>("h00"), T_1457) - node T_1459 = bit(acquireReadys, 0) - node T_1460 = bit(acquireReadys, 1) - node T_1461 = bit(acquireReadys, 2) - node T_1462 = bit(acquireReadys, 3) - node T_1463 = bit(acquireReadys, 4) - node T_1464 = bit(acquireReadys, 5) - node T_1465 = bit(acquireReadys, 6) - node T_1466 = bit(acquireReadys, 7) - wire T_1468 : UInt<1>[8] - T_1468[0] <= T_1459 - T_1468[1] <= T_1460 - T_1468[2] <= T_1461 - T_1468[3] <= T_1462 - T_1468[4] <= T_1463 - T_1468[5] <= T_1464 - T_1468[6] <= T_1465 - T_1468[7] <= T_1466 - node T_1486 = mux(T_1468[6], UInt<3>("h06"), UInt<3>("h07")) - node T_1487 = mux(T_1468[5], UInt<3>("h05"), T_1486) - node T_1488 = mux(T_1468[4], UInt<3>("h04"), T_1487) - node T_1489 = mux(T_1468[3], UInt<2>("h03"), T_1488) - node T_1490 = mux(T_1468[2], UInt<2>("h02"), T_1489) - node T_1491 = mux(T_1468[1], UInt<1>("h01"), T_1490) - node T_1492 = mux(T_1468[0], UInt<1>("h00"), T_1491) - node acquire_idx = mux(T_1424, T_1458, T_1492) - node T_1495 = neq(acquireConflicts, UInt<1>("h00")) - node T_1497 = eq(sdq_rdy, UInt<1>("h00")) - node block_acquires = or(T_1495, T_1497) - node T_1500 = neq(acquireReadys, UInt<1>("h00")) - node T_1502 = eq(block_acquires, UInt<1>("h00")) - node T_1503 = and(T_1500, T_1502) - io.inner.acquire.ready <= T_1503 + wire T_1130 : UInt<1>[8] + T_1130[0] <= T_1060.io.has_acquire_conflict + T_1130[1] <= T_1061.io.has_acquire_conflict + T_1130[2] <= T_1062.io.has_acquire_conflict + T_1130[3] <= T_1063.io.has_acquire_conflict + T_1130[4] <= T_1064.io.has_acquire_conflict + T_1130[5] <= T_1065.io.has_acquire_conflict + T_1130[6] <= T_1066.io.has_acquire_conflict + T_1130[7] <= T_1067.io.has_acquire_conflict + node T_1140 = cat(T_1130[7], T_1130[6]) + node T_1141 = cat(T_1130[5], T_1130[4]) + node T_1142 = cat(T_1140, T_1141) + node T_1143 = cat(T_1130[3], T_1130[2]) + node T_1144 = cat(T_1130[1], T_1130[0]) + node T_1145 = cat(T_1143, T_1144) + node acquireConflicts = cat(T_1142, T_1145) + wire T_1148 : UInt<1>[8] + T_1148[0] <= T_1060.io.has_acquire_match + T_1148[1] <= T_1061.io.has_acquire_match + T_1148[2] <= T_1062.io.has_acquire_match + T_1148[3] <= T_1063.io.has_acquire_match + T_1148[4] <= T_1064.io.has_acquire_match + T_1148[5] <= T_1065.io.has_acquire_match + T_1148[6] <= T_1066.io.has_acquire_match + T_1148[7] <= T_1067.io.has_acquire_match + node T_1158 = cat(T_1148[7], T_1148[6]) + node T_1159 = cat(T_1148[5], T_1148[4]) + node T_1160 = cat(T_1158, T_1159) + node T_1161 = cat(T_1148[3], T_1148[2]) + node T_1162 = cat(T_1148[1], T_1148[0]) + node T_1163 = cat(T_1161, T_1162) + node acquireMatches = cat(T_1160, T_1163) + wire T_1166 : UInt<1>[8] + T_1166[0] <= T_1060.io.inner.acquire.ready + T_1166[1] <= T_1061.io.inner.acquire.ready + T_1166[2] <= T_1062.io.inner.acquire.ready + T_1166[3] <= T_1063.io.inner.acquire.ready + T_1166[4] <= T_1064.io.inner.acquire.ready + T_1166[5] <= T_1065.io.inner.acquire.ready + T_1166[6] <= T_1066.io.inner.acquire.ready + T_1166[7] <= T_1067.io.inner.acquire.ready + node T_1176 = cat(T_1166[7], T_1166[6]) + node T_1177 = cat(T_1166[5], T_1166[4]) + node T_1178 = cat(T_1176, T_1177) + node T_1179 = cat(T_1166[3], T_1166[2]) + node T_1180 = cat(T_1166[1], T_1166[0]) + node T_1181 = cat(T_1179, T_1180) + node acquireReadys = cat(T_1178, T_1181) + node T_1184 = neq(acquireMatches, UInt<1>("h00")) + node T_1185 = bits(acquireMatches, 0, 0) + node T_1186 = bits(acquireMatches, 1, 1) + node T_1187 = bits(acquireMatches, 2, 2) + node T_1188 = bits(acquireMatches, 3, 3) + node T_1189 = bits(acquireMatches, 4, 4) + node T_1190 = bits(acquireMatches, 5, 5) + node T_1191 = bits(acquireMatches, 6, 6) + node T_1192 = bits(acquireMatches, 7, 7) + wire T_1194 : UInt<1>[8] + T_1194[0] <= T_1185 + T_1194[1] <= T_1186 + T_1194[2] <= T_1187 + T_1194[3] <= T_1188 + T_1194[4] <= T_1189 + T_1194[5] <= T_1190 + T_1194[6] <= T_1191 + T_1194[7] <= T_1192 + node T_1212 = mux(T_1194[6], UInt<3>("h06"), UInt<3>("h07")) + node T_1213 = mux(T_1194[5], UInt<3>("h05"), T_1212) + node T_1214 = mux(T_1194[4], UInt<3>("h04"), T_1213) + node T_1215 = mux(T_1194[3], UInt<2>("h03"), T_1214) + node T_1216 = mux(T_1194[2], UInt<2>("h02"), T_1215) + node T_1217 = mux(T_1194[1], UInt<1>("h01"), T_1216) + node T_1218 = mux(T_1194[0], UInt<1>("h00"), T_1217) + node T_1219 = bits(acquireReadys, 0, 0) + node T_1220 = bits(acquireReadys, 1, 1) + node T_1221 = bits(acquireReadys, 2, 2) + node T_1222 = bits(acquireReadys, 3, 3) + node T_1223 = bits(acquireReadys, 4, 4) + node T_1224 = bits(acquireReadys, 5, 5) + node T_1225 = bits(acquireReadys, 6, 6) + node T_1226 = bits(acquireReadys, 7, 7) + wire T_1228 : UInt<1>[8] + T_1228[0] <= T_1219 + T_1228[1] <= T_1220 + T_1228[2] <= T_1221 + T_1228[3] <= T_1222 + T_1228[4] <= T_1223 + T_1228[5] <= T_1224 + T_1228[6] <= T_1225 + T_1228[7] <= T_1226 + node T_1246 = mux(T_1228[6], UInt<3>("h06"), UInt<3>("h07")) + node T_1247 = mux(T_1228[5], UInt<3>("h05"), T_1246) + node T_1248 = mux(T_1228[4], UInt<3>("h04"), T_1247) + node T_1249 = mux(T_1228[3], UInt<2>("h03"), T_1248) + node T_1250 = mux(T_1228[2], UInt<2>("h02"), T_1249) + node T_1251 = mux(T_1228[1], UInt<1>("h01"), T_1250) + node T_1252 = mux(T_1228[0], UInt<1>("h00"), T_1251) + node acquire_idx = mux(T_1184, T_1218, T_1252) + node T_1255 = neq(acquireConflicts, UInt<1>("h00")) + node T_1257 = eq(sdq_rdy, UInt<1>("h00")) + node block_acquires = or(T_1255, T_1257) + node T_1260 = neq(acquireReadys, UInt<1>("h00")) + node T_1262 = eq(block_acquires, UInt<1>("h00")) + node T_1263 = and(T_1260, T_1262) + io.inner.acquire.ready <= T_1263 T_1060.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1550 : {idx : UInt<2>, loc : UInt<2>} - T_1550.loc <= UInt<1>("h00") - T_1550.idx <= UInt<1>("h00") - T_1550.idx <= sdq_alloc_id - T_1550.loc <= UInt<1>("h00") - node T_1598 = cat(T_1550.idx, T_1550.loc) - T_1060.io.inner.acquire.bits.data <= T_1598 - node T_1600 = eq(block_acquires, UInt<1>("h00")) - node T_1601 = and(io.inner.acquire.valid, T_1600) - node T_1603 = eq(acquire_idx, UInt<1>("h00")) - node T_1604 = and(T_1601, T_1603) - T_1060.io.inner.acquire.valid <= T_1604 - T_1091.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1651 : {idx : UInt<2>, loc : UInt<2>} - T_1651.loc <= UInt<1>("h00") - T_1651.idx <= UInt<1>("h00") - T_1651.idx <= sdq_alloc_id - T_1651.loc <= UInt<1>("h00") - node T_1699 = cat(T_1651.idx, T_1651.loc) - T_1091.io.inner.acquire.bits.data <= T_1699 - node T_1701 = eq(block_acquires, UInt<1>("h00")) - node T_1702 = and(io.inner.acquire.valid, T_1701) - node T_1704 = eq(acquire_idx, UInt<1>("h01")) - node T_1705 = and(T_1702, T_1704) - T_1091.io.inner.acquire.valid <= T_1705 - T_1122.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1752 : {idx : UInt<2>, loc : UInt<2>} - T_1752.loc <= UInt<1>("h00") - T_1752.idx <= UInt<1>("h00") - T_1752.idx <= sdq_alloc_id - T_1752.loc <= UInt<1>("h00") - node T_1800 = cat(T_1752.idx, T_1752.loc) - T_1122.io.inner.acquire.bits.data <= T_1800 - node T_1802 = eq(block_acquires, UInt<1>("h00")) - node T_1803 = and(io.inner.acquire.valid, T_1802) - node T_1805 = eq(acquire_idx, UInt<2>("h02")) - node T_1806 = and(T_1803, T_1805) - T_1122.io.inner.acquire.valid <= T_1806 - T_1153.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1853 : {idx : UInt<2>, loc : UInt<2>} - T_1853.loc <= UInt<1>("h00") - T_1853.idx <= UInt<1>("h00") - T_1853.idx <= sdq_alloc_id - T_1853.loc <= UInt<1>("h00") - node T_1901 = cat(T_1853.idx, T_1853.loc) - T_1153.io.inner.acquire.bits.data <= T_1901 - node T_1903 = eq(block_acquires, UInt<1>("h00")) - node T_1904 = and(io.inner.acquire.valid, T_1903) - node T_1906 = eq(acquire_idx, UInt<2>("h03")) - node T_1907 = and(T_1904, T_1906) - T_1153.io.inner.acquire.valid <= T_1907 - T_1184.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_1954 : {idx : UInt<2>, loc : UInt<2>} - T_1954.loc <= UInt<1>("h00") - T_1954.idx <= UInt<1>("h00") - T_1954.idx <= sdq_alloc_id - T_1954.loc <= UInt<1>("h00") - node T_2002 = cat(T_1954.idx, T_1954.loc) - T_1184.io.inner.acquire.bits.data <= T_2002 - node T_2004 = eq(block_acquires, UInt<1>("h00")) - node T_2005 = and(io.inner.acquire.valid, T_2004) - node T_2007 = eq(acquire_idx, UInt<3>("h04")) - node T_2008 = and(T_2005, T_2007) - T_1184.io.inner.acquire.valid <= T_2008 - T_1215.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_2055 : {idx : UInt<2>, loc : UInt<2>} - T_2055.loc <= UInt<1>("h00") - T_2055.idx <= UInt<1>("h00") - T_2055.idx <= sdq_alloc_id - T_2055.loc <= UInt<1>("h00") - node T_2103 = cat(T_2055.idx, T_2055.loc) - T_1215.io.inner.acquire.bits.data <= T_2103 - node T_2105 = eq(block_acquires, UInt<1>("h00")) - node T_2106 = and(io.inner.acquire.valid, T_2105) - node T_2108 = eq(acquire_idx, UInt<3>("h05")) - node T_2109 = and(T_2106, T_2108) - T_1215.io.inner.acquire.valid <= T_2109 - T_1246.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_2156 : {idx : UInt<2>, loc : UInt<2>} - T_2156.loc <= UInt<1>("h00") - T_2156.idx <= UInt<1>("h00") - T_2156.idx <= sdq_alloc_id - T_2156.loc <= UInt<1>("h00") - node T_2204 = cat(T_2156.idx, T_2156.loc) - T_1246.io.inner.acquire.bits.data <= T_2204 - node T_2206 = eq(block_acquires, UInt<1>("h00")) - node T_2207 = and(io.inner.acquire.valid, T_2206) - node T_2209 = eq(acquire_idx, UInt<3>("h06")) - node T_2210 = and(T_2207, T_2209) - T_1246.io.inner.acquire.valid <= T_2210 - T_1277.io.inner.acquire.bits <- io.inner.acquire.bits - wire T_2257 : {idx : UInt<2>, loc : UInt<2>} - T_2257.loc <= UInt<1>("h00") - T_2257.idx <= UInt<1>("h00") - T_2257.idx <= sdq_alloc_id - T_2257.loc <= UInt<1>("h00") - node T_2305 = cat(T_2257.idx, T_2257.loc) - T_1277.io.inner.acquire.bits.data <= T_2305 - node T_2307 = eq(block_acquires, UInt<1>("h00")) - node T_2308 = and(io.inner.acquire.valid, T_2307) - node T_2310 = eq(acquire_idx, UInt<3>("h07")) - node T_2311 = and(T_2308, T_2310) - T_1277.io.inner.acquire.valid <= T_2311 - node T_2312 = and(io.inner.release.ready, io.inner.release.valid) - node T_2313 = and(T_2312, io.inner.release.bits.voluntary) - wire T_2315 : UInt<2>[3] - T_2315[0] <= UInt<1>("h00") - T_2315[1] <= UInt<1>("h01") - T_2315[2] <= UInt<2>("h02") - node T_2320 = eq(T_2315[0], io.inner.release.bits.r_type) - node T_2321 = eq(T_2315[1], io.inner.release.bits.r_type) - node T_2322 = eq(T_2315[2], io.inner.release.bits.r_type) - node T_2324 = or(UInt<1>("h00"), T_2320) - node T_2325 = or(T_2324, T_2321) - node T_2326 = or(T_2325, T_2322) - node vwbdq_enq = and(T_2313, T_2326) - reg rel_data_cnt : UInt<2>, clk, reset, UInt<2>("h00") + wire T_1310 : {idx : UInt<2>, loc : UInt<2>} + T_1310 is invalid + T_1310.idx <= sdq_alloc_id + T_1310.loc <= UInt<1>("h00") + node T_1356 = cat(T_1310.idx, T_1310.loc) + T_1060.io.inner.acquire.bits.data <= T_1356 + node T_1358 = eq(block_acquires, UInt<1>("h00")) + node T_1359 = and(io.inner.acquire.valid, T_1358) + node T_1361 = eq(acquire_idx, UInt<1>("h00")) + node T_1362 = and(T_1359, T_1361) + T_1060.io.inner.acquire.valid <= T_1362 + T_1061.io.inner.acquire.bits <- io.inner.acquire.bits + wire T_1409 : {idx : UInt<2>, loc : UInt<2>} + T_1409 is invalid + T_1409.idx <= sdq_alloc_id + T_1409.loc <= UInt<1>("h00") + node T_1455 = cat(T_1409.idx, T_1409.loc) + T_1061.io.inner.acquire.bits.data <= T_1455 + node T_1457 = eq(block_acquires, UInt<1>("h00")) + node T_1458 = and(io.inner.acquire.valid, T_1457) + node T_1460 = eq(acquire_idx, UInt<1>("h01")) + node T_1461 = and(T_1458, T_1460) + T_1061.io.inner.acquire.valid <= T_1461 + T_1062.io.inner.acquire.bits <- io.inner.acquire.bits + wire T_1508 : {idx : UInt<2>, loc : UInt<2>} + T_1508 is invalid + T_1508.idx <= sdq_alloc_id + T_1508.loc <= UInt<1>("h00") + node T_1554 = cat(T_1508.idx, T_1508.loc) + T_1062.io.inner.acquire.bits.data <= T_1554 + node T_1556 = eq(block_acquires, UInt<1>("h00")) + node T_1557 = and(io.inner.acquire.valid, T_1556) + node T_1559 = eq(acquire_idx, UInt<2>("h02")) + node T_1560 = and(T_1557, T_1559) + T_1062.io.inner.acquire.valid <= T_1560 + T_1063.io.inner.acquire.bits <- io.inner.acquire.bits + wire T_1607 : {idx : UInt<2>, loc : UInt<2>} + T_1607 is invalid + T_1607.idx <= sdq_alloc_id + T_1607.loc <= UInt<1>("h00") + node T_1653 = cat(T_1607.idx, T_1607.loc) + T_1063.io.inner.acquire.bits.data <= T_1653 + node T_1655 = eq(block_acquires, UInt<1>("h00")) + node T_1656 = and(io.inner.acquire.valid, T_1655) + node T_1658 = eq(acquire_idx, UInt<2>("h03")) + node T_1659 = and(T_1656, T_1658) + T_1063.io.inner.acquire.valid <= T_1659 + T_1064.io.inner.acquire.bits <- io.inner.acquire.bits + wire T_1706 : {idx : UInt<2>, loc : UInt<2>} + T_1706 is invalid + T_1706.idx <= sdq_alloc_id + T_1706.loc <= UInt<1>("h00") + node T_1752 = cat(T_1706.idx, T_1706.loc) + T_1064.io.inner.acquire.bits.data <= T_1752 + node T_1754 = eq(block_acquires, UInt<1>("h00")) + node T_1755 = and(io.inner.acquire.valid, T_1754) + node T_1757 = eq(acquire_idx, UInt<3>("h04")) + node T_1758 = and(T_1755, T_1757) + T_1064.io.inner.acquire.valid <= T_1758 + T_1065.io.inner.acquire.bits <- io.inner.acquire.bits + wire T_1805 : {idx : UInt<2>, loc : UInt<2>} + T_1805 is invalid + T_1805.idx <= sdq_alloc_id + T_1805.loc <= UInt<1>("h00") + node T_1851 = cat(T_1805.idx, T_1805.loc) + T_1065.io.inner.acquire.bits.data <= T_1851 + node T_1853 = eq(block_acquires, UInt<1>("h00")) + node T_1854 = and(io.inner.acquire.valid, T_1853) + node T_1856 = eq(acquire_idx, UInt<3>("h05")) + node T_1857 = and(T_1854, T_1856) + T_1065.io.inner.acquire.valid <= T_1857 + T_1066.io.inner.acquire.bits <- io.inner.acquire.bits + wire T_1904 : {idx : UInt<2>, loc : UInt<2>} + T_1904 is invalid + T_1904.idx <= sdq_alloc_id + T_1904.loc <= UInt<1>("h00") + node T_1950 = cat(T_1904.idx, T_1904.loc) + T_1066.io.inner.acquire.bits.data <= T_1950 + node T_1952 = eq(block_acquires, UInt<1>("h00")) + node T_1953 = and(io.inner.acquire.valid, T_1952) + node T_1955 = eq(acquire_idx, UInt<3>("h06")) + node T_1956 = and(T_1953, T_1955) + T_1066.io.inner.acquire.valid <= T_1956 + T_1067.io.inner.acquire.bits <- io.inner.acquire.bits + wire T_2003 : {idx : UInt<2>, loc : UInt<2>} + T_2003 is invalid + T_2003.idx <= sdq_alloc_id + T_2003.loc <= UInt<1>("h00") + node T_2049 = cat(T_2003.idx, T_2003.loc) + T_1067.io.inner.acquire.bits.data <= T_2049 + node T_2051 = eq(block_acquires, UInt<1>("h00")) + node T_2052 = and(io.inner.acquire.valid, T_2051) + node T_2054 = eq(acquire_idx, UInt<3>("h07")) + node T_2055 = and(T_2052, T_2054) + T_1067.io.inner.acquire.valid <= T_2055 + node T_2056 = and(io.inner.release.ready, io.inner.release.valid) + node T_2057 = and(T_2056, io.inner.release.bits.voluntary) + wire T_2059 : UInt<2>[3] + T_2059[0] <= UInt<1>("h00") + T_2059[1] <= UInt<1>("h01") + T_2059[2] <= UInt<2>("h02") + node T_2064 = eq(T_2059[0], io.inner.release.bits.r_type) + node T_2065 = eq(T_2059[1], io.inner.release.bits.r_type) + node T_2066 = eq(T_2059[2], io.inner.release.bits.r_type) + node T_2068 = or(UInt<1>("h00"), T_2064) + node T_2069 = or(T_2068, T_2065) + node T_2070 = or(T_2069, T_2066) + node vwbdq_enq = and(T_2057, T_2070) + reg rel_data_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) when vwbdq_enq : - node T_2331 = eq(rel_data_cnt, UInt<2>("h03")) - node T_2333 = and(UInt<1>("h00"), T_2331) - node T_2336 = addw(rel_data_cnt, UInt<1>("h01")) - node T_2337 = mux(T_2333, UInt<1>("h00"), T_2336) - rel_data_cnt <= T_2337 - skip - node rel_data_done = and(vwbdq_enq, T_2331) - reg vwbdq : UInt<128>[4], clk, UInt<1>("h00"), vwbdq + node T_2075 = eq(rel_data_cnt, UInt<2>("h03")) + node T_2077 = and(UInt<1>("h00"), T_2075) + node T_2080 = add(rel_data_cnt, UInt<1>("h01")) + node T_2081 = tail(T_2080, 1) + node T_2082 = mux(T_2077, UInt<1>("h00"), T_2081) + rel_data_cnt <= T_2082 + skip + node rel_data_done = and(vwbdq_enq, T_2075) + reg vwbdq : UInt<128>[4], clk when vwbdq_enq : vwbdq[rel_data_cnt] <= io.inner.release.bits.data skip - wire T_2356 : UInt<1>[8] - T_2356[0] <= T_1060.io.inner.release.ready - T_2356[1] <= T_1091.io.inner.release.ready - T_2356[2] <= T_1122.io.inner.release.ready - T_2356[3] <= T_1153.io.inner.release.ready - T_2356[4] <= T_1184.io.inner.release.ready - T_2356[5] <= T_1215.io.inner.release.ready - T_2356[6] <= T_1246.io.inner.release.ready - T_2356[7] <= T_1277.io.inner.release.ready - node T_2366 = cat(T_2356[7], T_2356[6]) - node T_2367 = cat(T_2356[5], T_2356[4]) - node T_2368 = cat(T_2366, T_2367) - node T_2369 = cat(T_2356[3], T_2356[2]) - node T_2370 = cat(T_2356[1], T_2356[0]) - node T_2371 = cat(T_2369, T_2370) - node releaseReadys = cat(T_2368, T_2371) - wire T_2374 : UInt<1>[8] - T_2374[0] <= T_1060.io.has_release_match - T_2374[1] <= T_1091.io.has_release_match - T_2374[2] <= T_1122.io.has_release_match - T_2374[3] <= T_1153.io.has_release_match - T_2374[4] <= T_1184.io.has_release_match - T_2374[5] <= T_1215.io.has_release_match - T_2374[6] <= T_1246.io.has_release_match - T_2374[7] <= T_1277.io.has_release_match - node T_2384 = cat(T_2374[7], T_2374[6]) - node T_2385 = cat(T_2374[5], T_2374[4]) - node T_2386 = cat(T_2384, T_2385) - node T_2387 = cat(T_2374[3], T_2374[2]) - node T_2388 = cat(T_2374[1], T_2374[0]) - node T_2389 = cat(T_2387, T_2388) - node releaseMatches = cat(T_2386, T_2389) - node T_2391 = bit(releaseMatches, 0) - node T_2392 = bit(releaseMatches, 1) - node T_2393 = bit(releaseMatches, 2) - node T_2394 = bit(releaseMatches, 3) - node T_2395 = bit(releaseMatches, 4) - node T_2396 = bit(releaseMatches, 5) - node T_2397 = bit(releaseMatches, 6) - node T_2398 = bit(releaseMatches, 7) - wire T_2400 : UInt<1>[8] - T_2400[0] <= T_2391 - T_2400[1] <= T_2392 - T_2400[2] <= T_2393 - T_2400[3] <= T_2394 - T_2400[4] <= T_2395 - T_2400[5] <= T_2396 - T_2400[6] <= T_2397 - T_2400[7] <= T_2398 - node T_2418 = mux(T_2400[6], UInt<3>("h06"), UInt<3>("h07")) - node T_2419 = mux(T_2400[5], UInt<3>("h05"), T_2418) - node T_2420 = mux(T_2400[4], UInt<3>("h04"), T_2419) - node T_2421 = mux(T_2400[3], UInt<2>("h03"), T_2420) - node T_2422 = mux(T_2400[2], UInt<2>("h02"), T_2421) - node T_2423 = mux(T_2400[1], UInt<1>("h01"), T_2422) - node release_idx = mux(T_2400[0], UInt<1>("h00"), T_2423) - node T_2425 = dshr(releaseReadys, release_idx) - node T_2426 = bit(T_2425, 0) - io.inner.release.ready <= T_2426 - node T_2428 = eq(release_idx, UInt<1>("h00")) - node T_2429 = and(io.inner.release.valid, T_2428) - T_1060.io.inner.release.valid <= T_2429 + wire T_2101 : UInt<1>[8] + T_2101[0] <= T_1060.io.inner.release.ready + T_2101[1] <= T_1061.io.inner.release.ready + T_2101[2] <= T_1062.io.inner.release.ready + T_2101[3] <= T_1063.io.inner.release.ready + T_2101[4] <= T_1064.io.inner.release.ready + T_2101[5] <= T_1065.io.inner.release.ready + T_2101[6] <= T_1066.io.inner.release.ready + T_2101[7] <= T_1067.io.inner.release.ready + node T_2111 = cat(T_2101[7], T_2101[6]) + node T_2112 = cat(T_2101[5], T_2101[4]) + node T_2113 = cat(T_2111, T_2112) + node T_2114 = cat(T_2101[3], T_2101[2]) + node T_2115 = cat(T_2101[1], T_2101[0]) + node T_2116 = cat(T_2114, T_2115) + node releaseReadys = cat(T_2113, T_2116) + wire T_2119 : UInt<1>[8] + T_2119[0] <= T_1060.io.has_release_match + T_2119[1] <= T_1061.io.has_release_match + T_2119[2] <= T_1062.io.has_release_match + T_2119[3] <= T_1063.io.has_release_match + T_2119[4] <= T_1064.io.has_release_match + T_2119[5] <= T_1065.io.has_release_match + T_2119[6] <= T_1066.io.has_release_match + T_2119[7] <= T_1067.io.has_release_match + node T_2129 = cat(T_2119[7], T_2119[6]) + node T_2130 = cat(T_2119[5], T_2119[4]) + node T_2131 = cat(T_2129, T_2130) + node T_2132 = cat(T_2119[3], T_2119[2]) + node T_2133 = cat(T_2119[1], T_2119[0]) + node T_2134 = cat(T_2132, T_2133) + node releaseMatches = cat(T_2131, T_2134) + node T_2136 = bits(releaseMatches, 0, 0) + node T_2137 = bits(releaseMatches, 1, 1) + node T_2138 = bits(releaseMatches, 2, 2) + node T_2139 = bits(releaseMatches, 3, 3) + node T_2140 = bits(releaseMatches, 4, 4) + node T_2141 = bits(releaseMatches, 5, 5) + node T_2142 = bits(releaseMatches, 6, 6) + node T_2143 = bits(releaseMatches, 7, 7) + wire T_2145 : UInt<1>[8] + T_2145[0] <= T_2136 + T_2145[1] <= T_2137 + T_2145[2] <= T_2138 + T_2145[3] <= T_2139 + T_2145[4] <= T_2140 + T_2145[5] <= T_2141 + T_2145[6] <= T_2142 + T_2145[7] <= T_2143 + node T_2163 = mux(T_2145[6], UInt<3>("h06"), UInt<3>("h07")) + node T_2164 = mux(T_2145[5], UInt<3>("h05"), T_2163) + node T_2165 = mux(T_2145[4], UInt<3>("h04"), T_2164) + node T_2166 = mux(T_2145[3], UInt<2>("h03"), T_2165) + node T_2167 = mux(T_2145[2], UInt<2>("h02"), T_2166) + node T_2168 = mux(T_2145[1], UInt<1>("h01"), T_2167) + node release_idx = mux(T_2145[0], UInt<1>("h00"), T_2168) + node T_2170 = dshr(releaseReadys, release_idx) + node T_2171 = bits(T_2170, 0, 0) + io.inner.release.ready <= T_2171 + node T_2173 = eq(release_idx, UInt<1>("h00")) + node T_2174 = and(io.inner.release.valid, T_2173) + T_1060.io.inner.release.valid <= T_2174 T_1060.io.inner.release.bits <- io.inner.release.bits - wire T_2476 : {idx : UInt<2>, loc : UInt<2>} - T_2476.loc <= UInt<1>("h00") - T_2476.idx <= UInt<1>("h00") - T_2476.idx <= rel_data_cnt - T_2476.loc <= UInt<1>("h01") - node T_2524 = cat(T_2476.idx, T_2476.loc) - T_1060.io.inner.release.bits.data <= T_2524 - node T_2526 = eq(release_idx, UInt<1>("h01")) - node T_2527 = and(io.inner.release.valid, T_2526) - T_1091.io.inner.release.valid <= T_2527 - T_1091.io.inner.release.bits <- io.inner.release.bits - wire T_2574 : {idx : UInt<2>, loc : UInt<2>} - T_2574.loc <= UInt<1>("h00") - T_2574.idx <= UInt<1>("h00") - T_2574.idx <= rel_data_cnt - T_2574.loc <= UInt<2>("h02") - node T_2622 = cat(T_2574.idx, T_2574.loc) - T_1091.io.inner.release.bits.data <= T_2622 - node T_2624 = eq(release_idx, UInt<2>("h02")) - node T_2625 = and(io.inner.release.valid, T_2624) - T_1122.io.inner.release.valid <= T_2625 - T_1122.io.inner.release.bits <- io.inner.release.bits - wire T_2672 : {idx : UInt<2>, loc : UInt<2>} - T_2672.loc <= UInt<1>("h00") - T_2672.idx <= UInt<1>("h00") - T_2672.idx <= rel_data_cnt - T_2672.loc <= UInt<2>("h02") - node T_2720 = cat(T_2672.idx, T_2672.loc) - T_1122.io.inner.release.bits.data <= T_2720 - node T_2722 = eq(release_idx, UInt<2>("h03")) - node T_2723 = and(io.inner.release.valid, T_2722) - T_1153.io.inner.release.valid <= T_2723 - T_1153.io.inner.release.bits <- io.inner.release.bits - wire T_2770 : {idx : UInt<2>, loc : UInt<2>} - T_2770.loc <= UInt<1>("h00") - T_2770.idx <= UInt<1>("h00") - T_2770.idx <= rel_data_cnt - T_2770.loc <= UInt<2>("h02") - node T_2818 = cat(T_2770.idx, T_2770.loc) - T_1153.io.inner.release.bits.data <= T_2818 - node T_2820 = eq(release_idx, UInt<3>("h04")) - node T_2821 = and(io.inner.release.valid, T_2820) - T_1184.io.inner.release.valid <= T_2821 - T_1184.io.inner.release.bits <- io.inner.release.bits - wire T_2868 : {idx : UInt<2>, loc : UInt<2>} - T_2868.loc <= UInt<1>("h00") - T_2868.idx <= UInt<1>("h00") - T_2868.idx <= rel_data_cnt - T_2868.loc <= UInt<2>("h02") - node T_2916 = cat(T_2868.idx, T_2868.loc) - T_1184.io.inner.release.bits.data <= T_2916 - node T_2918 = eq(release_idx, UInt<3>("h05")) - node T_2919 = and(io.inner.release.valid, T_2918) - T_1215.io.inner.release.valid <= T_2919 - T_1215.io.inner.release.bits <- io.inner.release.bits - wire T_2966 : {idx : UInt<2>, loc : UInt<2>} - T_2966.loc <= UInt<1>("h00") - T_2966.idx <= UInt<1>("h00") - T_2966.idx <= rel_data_cnt - T_2966.loc <= UInt<2>("h02") - node T_3014 = cat(T_2966.idx, T_2966.loc) - T_1215.io.inner.release.bits.data <= T_3014 - node T_3016 = eq(release_idx, UInt<3>("h06")) - node T_3017 = and(io.inner.release.valid, T_3016) - T_1246.io.inner.release.valid <= T_3017 - T_1246.io.inner.release.bits <- io.inner.release.bits - wire T_3064 : {idx : UInt<2>, loc : UInt<2>} - T_3064.loc <= UInt<1>("h00") - T_3064.idx <= UInt<1>("h00") - T_3064.idx <= rel_data_cnt - T_3064.loc <= UInt<2>("h02") - node T_3112 = cat(T_3064.idx, T_3064.loc) - T_1246.io.inner.release.bits.data <= T_3112 - node T_3114 = eq(release_idx, UInt<3>("h07")) - node T_3115 = and(io.inner.release.valid, T_3114) - T_1277.io.inner.release.valid <= T_3115 - T_1277.io.inner.release.bits <- io.inner.release.bits - wire T_3162 : {idx : UInt<2>, loc : UInt<2>} - T_3162.loc <= UInt<1>("h00") - T_3162.idx <= UInt<1>("h00") - T_3162.idx <= rel_data_cnt - T_3162.loc <= UInt<2>("h02") - node T_3210 = cat(T_3162.idx, T_3162.loc) - T_1277.io.inner.release.bits.data <= T_3210 - node T_3212 = neq(releaseMatches, UInt<1>("h00")) - node T_3214 = eq(T_3212, UInt<1>("h00")) - node T_3215 = and(io.inner.release.valid, T_3214) - node T_3217 = eq(T_3215, UInt<1>("h00")) - node T_3219 = eq(reset, UInt<1>("h00")) - when T_3219 : - node T_3221 = eq(T_3217, UInt<1>("h00")) - when T_3221 : - node T_3223 = eq(reset, UInt<1>("h00")) - when T_3223 : + wire T_2221 : {idx : UInt<2>, loc : UInt<2>} + T_2221 is invalid + T_2221.idx <= rel_data_cnt + T_2221.loc <= UInt<1>("h01") + node T_2267 = cat(T_2221.idx, T_2221.loc) + T_1060.io.inner.release.bits.data <= T_2267 + node T_2269 = eq(release_idx, UInt<1>("h01")) + node T_2270 = and(io.inner.release.valid, T_2269) + T_1061.io.inner.release.valid <= T_2270 + T_1061.io.inner.release.bits <- io.inner.release.bits + wire T_2317 : {idx : UInt<2>, loc : UInt<2>} + T_2317 is invalid + T_2317.idx <= rel_data_cnt + T_2317.loc <= UInt<2>("h02") + node T_2363 = cat(T_2317.idx, T_2317.loc) + T_1061.io.inner.release.bits.data <= T_2363 + node T_2365 = eq(release_idx, UInt<2>("h02")) + node T_2366 = and(io.inner.release.valid, T_2365) + T_1062.io.inner.release.valid <= T_2366 + T_1062.io.inner.release.bits <- io.inner.release.bits + wire T_2413 : {idx : UInt<2>, loc : UInt<2>} + T_2413 is invalid + T_2413.idx <= rel_data_cnt + T_2413.loc <= UInt<2>("h02") + node T_2459 = cat(T_2413.idx, T_2413.loc) + T_1062.io.inner.release.bits.data <= T_2459 + node T_2461 = eq(release_idx, UInt<2>("h03")) + node T_2462 = and(io.inner.release.valid, T_2461) + T_1063.io.inner.release.valid <= T_2462 + T_1063.io.inner.release.bits <- io.inner.release.bits + wire T_2509 : {idx : UInt<2>, loc : UInt<2>} + T_2509 is invalid + T_2509.idx <= rel_data_cnt + T_2509.loc <= UInt<2>("h02") + node T_2555 = cat(T_2509.idx, T_2509.loc) + T_1063.io.inner.release.bits.data <= T_2555 + node T_2557 = eq(release_idx, UInt<3>("h04")) + node T_2558 = and(io.inner.release.valid, T_2557) + T_1064.io.inner.release.valid <= T_2558 + T_1064.io.inner.release.bits <- io.inner.release.bits + wire T_2605 : {idx : UInt<2>, loc : UInt<2>} + T_2605 is invalid + T_2605.idx <= rel_data_cnt + T_2605.loc <= UInt<2>("h02") + node T_2651 = cat(T_2605.idx, T_2605.loc) + T_1064.io.inner.release.bits.data <= T_2651 + node T_2653 = eq(release_idx, UInt<3>("h05")) + node T_2654 = and(io.inner.release.valid, T_2653) + T_1065.io.inner.release.valid <= T_2654 + T_1065.io.inner.release.bits <- io.inner.release.bits + wire T_2701 : {idx : UInt<2>, loc : UInt<2>} + T_2701 is invalid + T_2701.idx <= rel_data_cnt + T_2701.loc <= UInt<2>("h02") + node T_2747 = cat(T_2701.idx, T_2701.loc) + T_1065.io.inner.release.bits.data <= T_2747 + node T_2749 = eq(release_idx, UInt<3>("h06")) + node T_2750 = and(io.inner.release.valid, T_2749) + T_1066.io.inner.release.valid <= T_2750 + T_1066.io.inner.release.bits <- io.inner.release.bits + wire T_2797 : {idx : UInt<2>, loc : UInt<2>} + T_2797 is invalid + T_2797.idx <= rel_data_cnt + T_2797.loc <= UInt<2>("h02") + node T_2843 = cat(T_2797.idx, T_2797.loc) + T_1066.io.inner.release.bits.data <= T_2843 + node T_2845 = eq(release_idx, UInt<3>("h07")) + node T_2846 = and(io.inner.release.valid, T_2845) + T_1067.io.inner.release.valid <= T_2846 + T_1067.io.inner.release.bits <- io.inner.release.bits + wire T_2893 : {idx : UInt<2>, loc : UInt<2>} + T_2893 is invalid + T_2893.idx <= rel_data_cnt + T_2893.loc <= UInt<2>("h02") + node T_2939 = cat(T_2893.idx, T_2893.loc) + T_1067.io.inner.release.bits.data <= T_2939 + node T_2941 = neq(releaseMatches, UInt<1>("h00")) + node T_2943 = eq(T_2941, UInt<1>("h00")) + node T_2944 = and(io.inner.release.valid, T_2943) + node T_2946 = eq(T_2944, UInt<1>("h00")) + node T_2948 = eq(reset, UInt<1>("h00")) + when T_2948 : + node T_2950 = eq(T_2946, UInt<1>("h00")) + when T_2950 : + node T_2952 = eq(reset, UInt<1>("h00")) + when T_2952 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Non-voluntary release should always have a Tracker waiting for it.") skip stop(clk, UInt<1>(1), 1) skip skip - inst T_3224 of LockingRRArbiter_33 - T_3224.io.out.ready <= UInt<1>("h00") - T_3224.io.in[0].bits.client_id <= UInt<1>("h00") - T_3224.io.in[0].bits.data <= UInt<1>("h00") - T_3224.io.in[0].bits.g_type <= UInt<1>("h00") - T_3224.io.in[0].bits.is_builtin_type <= UInt<1>("h00") - T_3224.io.in[0].bits.manager_xact_id <= UInt<1>("h00") - T_3224.io.in[0].bits.client_xact_id <= UInt<1>("h00") - T_3224.io.in[0].bits.addr_beat <= UInt<1>("h00") - T_3224.io.in[0].valid <= UInt<1>("h00") - T_3224.io.in[1].bits.client_id <= UInt<1>("h00") - T_3224.io.in[1].bits.data <= UInt<1>("h00") - T_3224.io.in[1].bits.g_type <= UInt<1>("h00") - T_3224.io.in[1].bits.is_builtin_type <= UInt<1>("h00") - T_3224.io.in[1].bits.manager_xact_id <= UInt<1>("h00") - T_3224.io.in[1].bits.client_xact_id <= UInt<1>("h00") - T_3224.io.in[1].bits.addr_beat <= UInt<1>("h00") - T_3224.io.in[1].valid <= UInt<1>("h00") - T_3224.io.in[2].bits.client_id <= UInt<1>("h00") - T_3224.io.in[2].bits.data <= UInt<1>("h00") - T_3224.io.in[2].bits.g_type <= UInt<1>("h00") - T_3224.io.in[2].bits.is_builtin_type <= UInt<1>("h00") - T_3224.io.in[2].bits.manager_xact_id <= UInt<1>("h00") - T_3224.io.in[2].bits.client_xact_id <= UInt<1>("h00") - T_3224.io.in[2].bits.addr_beat <= UInt<1>("h00") - T_3224.io.in[2].valid <= UInt<1>("h00") - T_3224.io.in[3].bits.client_id <= UInt<1>("h00") - T_3224.io.in[3].bits.data <= UInt<1>("h00") - T_3224.io.in[3].bits.g_type <= UInt<1>("h00") - T_3224.io.in[3].bits.is_builtin_type <= UInt<1>("h00") - T_3224.io.in[3].bits.manager_xact_id <= UInt<1>("h00") - T_3224.io.in[3].bits.client_xact_id <= UInt<1>("h00") - T_3224.io.in[3].bits.addr_beat <= UInt<1>("h00") - T_3224.io.in[3].valid <= UInt<1>("h00") - T_3224.io.in[4].bits.client_id <= UInt<1>("h00") - T_3224.io.in[4].bits.data <= UInt<1>("h00") - T_3224.io.in[4].bits.g_type <= UInt<1>("h00") - T_3224.io.in[4].bits.is_builtin_type <= UInt<1>("h00") - T_3224.io.in[4].bits.manager_xact_id <= UInt<1>("h00") - T_3224.io.in[4].bits.client_xact_id <= UInt<1>("h00") - T_3224.io.in[4].bits.addr_beat <= UInt<1>("h00") - T_3224.io.in[4].valid <= UInt<1>("h00") - T_3224.io.in[5].bits.client_id <= UInt<1>("h00") - T_3224.io.in[5].bits.data <= UInt<1>("h00") - T_3224.io.in[5].bits.g_type <= UInt<1>("h00") - T_3224.io.in[5].bits.is_builtin_type <= UInt<1>("h00") - T_3224.io.in[5].bits.manager_xact_id <= UInt<1>("h00") - T_3224.io.in[5].bits.client_xact_id <= UInt<1>("h00") - T_3224.io.in[5].bits.addr_beat <= UInt<1>("h00") - T_3224.io.in[5].valid <= UInt<1>("h00") - T_3224.io.in[6].bits.client_id <= UInt<1>("h00") - T_3224.io.in[6].bits.data <= UInt<1>("h00") - T_3224.io.in[6].bits.g_type <= UInt<1>("h00") - T_3224.io.in[6].bits.is_builtin_type <= UInt<1>("h00") - T_3224.io.in[6].bits.manager_xact_id <= UInt<1>("h00") - T_3224.io.in[6].bits.client_xact_id <= UInt<1>("h00") - T_3224.io.in[6].bits.addr_beat <= UInt<1>("h00") - T_3224.io.in[6].valid <= UInt<1>("h00") - T_3224.io.in[7].bits.client_id <= UInt<1>("h00") - T_3224.io.in[7].bits.data <= UInt<1>("h00") - T_3224.io.in[7].bits.g_type <= UInt<1>("h00") - T_3224.io.in[7].bits.is_builtin_type <= UInt<1>("h00") - T_3224.io.in[7].bits.manager_xact_id <= UInt<1>("h00") - T_3224.io.in[7].bits.client_xact_id <= UInt<1>("h00") - T_3224.io.in[7].bits.addr_beat <= UInt<1>("h00") - T_3224.io.in[7].valid <= UInt<1>("h00") - T_3224.clk <= clk - T_3224.reset <= reset - io.inner.grant <- T_3224.io.out - T_3224.io.in[0] <- T_1060.io.inner.grant - T_3224.io.in[1] <- T_1091.io.inner.grant - T_3224.io.in[2] <- T_1122.io.inner.grant - T_3224.io.in[3] <- T_1153.io.inner.grant - T_3224.io.in[4] <- T_1184.io.inner.grant - T_3224.io.in[5] <- T_1215.io.inner.grant - T_3224.io.in[6] <- T_1246.io.inner.grant - T_3224.io.in[7] <- T_1277.io.inner.grant + inst T_2953 of LockingRRArbiter_33 + T_2953.io is invalid + T_2953.clk <= clk + T_2953.reset <= reset + io.inner.grant <- T_2953.io.out + T_2953.io.in[0] <- T_1060.io.inner.grant + T_2953.io.in[1] <- T_1061.io.inner.grant + T_2953.io.in[2] <- T_1062.io.inner.grant + T_2953.io.in[3] <- T_1063.io.inner.grant + T_2953.io.in[4] <- T_1064.io.inner.grant + T_2953.io.in[5] <- T_1065.io.inner.grant + T_2953.io.in[6] <- T_1066.io.inner.grant + T_2953.io.in[7] <- T_1067.io.inner.grant io.inner.grant.bits.data <= io.outer.grant.bits.data io.inner.grant.bits.addr_beat <= io.outer.grant.bits.addr_beat - inst T_3290 of LockingRRArbiter_34 - T_3290.io.out.ready <= UInt<1>("h00") - T_3290.io.in[0].bits.client_id <= UInt<1>("h00") - T_3290.io.in[0].bits.p_type <= UInt<1>("h00") - T_3290.io.in[0].bits.addr_block <= UInt<1>("h00") - T_3290.io.in[0].valid <= UInt<1>("h00") - T_3290.io.in[1].bits.client_id <= UInt<1>("h00") - T_3290.io.in[1].bits.p_type <= UInt<1>("h00") - T_3290.io.in[1].bits.addr_block <= UInt<1>("h00") - T_3290.io.in[1].valid <= UInt<1>("h00") - T_3290.io.in[2].bits.client_id <= UInt<1>("h00") - T_3290.io.in[2].bits.p_type <= UInt<1>("h00") - T_3290.io.in[2].bits.addr_block <= UInt<1>("h00") - T_3290.io.in[2].valid <= UInt<1>("h00") - T_3290.io.in[3].bits.client_id <= UInt<1>("h00") - T_3290.io.in[3].bits.p_type <= UInt<1>("h00") - T_3290.io.in[3].bits.addr_block <= UInt<1>("h00") - T_3290.io.in[3].valid <= UInt<1>("h00") - T_3290.io.in[4].bits.client_id <= UInt<1>("h00") - T_3290.io.in[4].bits.p_type <= UInt<1>("h00") - T_3290.io.in[4].bits.addr_block <= UInt<1>("h00") - T_3290.io.in[4].valid <= UInt<1>("h00") - T_3290.io.in[5].bits.client_id <= UInt<1>("h00") - T_3290.io.in[5].bits.p_type <= UInt<1>("h00") - T_3290.io.in[5].bits.addr_block <= UInt<1>("h00") - T_3290.io.in[5].valid <= UInt<1>("h00") - T_3290.io.in[6].bits.client_id <= UInt<1>("h00") - T_3290.io.in[6].bits.p_type <= UInt<1>("h00") - T_3290.io.in[6].bits.addr_block <= UInt<1>("h00") - T_3290.io.in[6].valid <= UInt<1>("h00") - T_3290.io.in[7].bits.client_id <= UInt<1>("h00") - T_3290.io.in[7].bits.p_type <= UInt<1>("h00") - T_3290.io.in[7].bits.addr_block <= UInt<1>("h00") - T_3290.io.in[7].valid <= UInt<1>("h00") - T_3290.clk <= clk - T_3290.reset <= reset - io.inner.probe <- T_3290.io.out - T_3290.io.in[0] <- T_1060.io.inner.probe - T_3290.io.in[1] <- T_1091.io.inner.probe - T_3290.io.in[2] <- T_1122.io.inner.probe - T_3290.io.in[3] <- T_1153.io.inner.probe - T_3290.io.in[4] <- T_1184.io.inner.probe - T_3290.io.in[5] <- T_1215.io.inner.probe - T_3290.io.in[6] <- T_1246.io.inner.probe - T_3290.io.in[7] <- T_1277.io.inner.probe + inst T_2954 of LockingRRArbiter_34 + T_2954.io is invalid + T_2954.clk <= clk + T_2954.reset <= reset + io.inner.probe <- T_2954.io.out + T_2954.io.in[0] <- T_1060.io.inner.probe + T_2954.io.in[1] <- T_1061.io.inner.probe + T_2954.io.in[2] <- T_1062.io.inner.probe + T_2954.io.in[3] <- T_1063.io.inner.probe + T_2954.io.in[4] <- T_1064.io.inner.probe + T_2954.io.in[5] <- T_1065.io.inner.probe + T_2954.io.in[6] <- T_1066.io.inner.probe + T_2954.io.in[7] <- T_1067.io.inner.probe T_1060.io.inner.finish.bits <- io.inner.finish.bits - T_1091.io.inner.finish.bits <- io.inner.finish.bits - T_1122.io.inner.finish.bits <- io.inner.finish.bits - T_1153.io.inner.finish.bits <- io.inner.finish.bits - T_1184.io.inner.finish.bits <- io.inner.finish.bits - T_1215.io.inner.finish.bits <- io.inner.finish.bits - T_1246.io.inner.finish.bits <- io.inner.finish.bits - T_1277.io.inner.finish.bits <- io.inner.finish.bits - node T_3325 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h00")) - node T_3326 = and(io.inner.finish.valid, T_3325) - T_1060.io.inner.finish.valid <= T_3326 - node T_3328 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h01")) - node T_3329 = and(io.inner.finish.valid, T_3328) - T_1091.io.inner.finish.valid <= T_3329 - node T_3331 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h02")) - node T_3332 = and(io.inner.finish.valid, T_3331) - T_1122.io.inner.finish.valid <= T_3332 - node T_3334 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h03")) - node T_3335 = and(io.inner.finish.valid, T_3334) - T_1153.io.inner.finish.valid <= T_3335 - node T_3337 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h04")) - node T_3338 = and(io.inner.finish.valid, T_3337) - T_1184.io.inner.finish.valid <= T_3338 - node T_3340 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h05")) - node T_3341 = and(io.inner.finish.valid, T_3340) - T_1215.io.inner.finish.valid <= T_3341 - node T_3343 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h06")) - node T_3344 = and(io.inner.finish.valid, T_3343) - T_1246.io.inner.finish.valid <= T_3344 - node T_3346 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h07")) - node T_3347 = and(io.inner.finish.valid, T_3346) - T_1277.io.inner.finish.valid <= T_3347 - wire T_3349 : UInt<1>[8] - T_3349[0] <= T_1060.io.inner.finish.ready - T_3349[1] <= T_1091.io.inner.finish.ready - T_3349[2] <= T_1122.io.inner.finish.ready - T_3349[3] <= T_1153.io.inner.finish.ready - T_3349[4] <= T_1184.io.inner.finish.ready - T_3349[5] <= T_1215.io.inner.finish.ready - T_3349[6] <= T_1246.io.inner.finish.ready - T_3349[7] <= T_1277.io.inner.finish.ready - io.inner.finish.ready <= T_3349[io.inner.finish.bits.manager_xact_id] + T_1061.io.inner.finish.bits <- io.inner.finish.bits + T_1062.io.inner.finish.bits <- io.inner.finish.bits + T_1063.io.inner.finish.bits <- io.inner.finish.bits + T_1064.io.inner.finish.bits <- io.inner.finish.bits + T_1065.io.inner.finish.bits <- io.inner.finish.bits + T_1066.io.inner.finish.bits <- io.inner.finish.bits + T_1067.io.inner.finish.bits <- io.inner.finish.bits + node T_2956 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h00")) + node T_2957 = and(io.inner.finish.valid, T_2956) + T_1060.io.inner.finish.valid <= T_2957 + node T_2959 = eq(io.inner.finish.bits.manager_xact_id, UInt<1>("h01")) + node T_2960 = and(io.inner.finish.valid, T_2959) + T_1061.io.inner.finish.valid <= T_2960 + node T_2962 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h02")) + node T_2963 = and(io.inner.finish.valid, T_2962) + T_1062.io.inner.finish.valid <= T_2963 + node T_2965 = eq(io.inner.finish.bits.manager_xact_id, UInt<2>("h03")) + node T_2966 = and(io.inner.finish.valid, T_2965) + T_1063.io.inner.finish.valid <= T_2966 + node T_2968 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h04")) + node T_2969 = and(io.inner.finish.valid, T_2968) + T_1064.io.inner.finish.valid <= T_2969 + node T_2971 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h05")) + node T_2972 = and(io.inner.finish.valid, T_2971) + T_1065.io.inner.finish.valid <= T_2972 + node T_2974 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h06")) + node T_2975 = and(io.inner.finish.valid, T_2974) + T_1066.io.inner.finish.valid <= T_2975 + node T_2977 = eq(io.inner.finish.bits.manager_xact_id, UInt<3>("h07")) + node T_2978 = and(io.inner.finish.valid, T_2977) + T_1067.io.inner.finish.valid <= T_2978 + wire T_2980 : UInt<1>[8] + T_2980[0] <= T_1060.io.inner.finish.ready + T_2980[1] <= T_1061.io.inner.finish.ready + T_2980[2] <= T_1062.io.inner.finish.ready + T_2980[3] <= T_1063.io.inner.finish.ready + T_2980[4] <= T_1064.io.inner.finish.ready + T_2980[5] <= T_1065.io.inner.finish.ready + T_2980[6] <= T_1066.io.inner.finish.ready + T_2980[7] <= T_1067.io.inner.finish.ready + io.inner.finish.ready <= T_2980[io.inner.finish.bits.manager_xact_id] inst outer_arb of ClientUncachedTileLinkIOArbiter - outer_arb.io.out.grant.bits.data <= UInt<1>("h00") - outer_arb.io.out.grant.bits.g_type <= UInt<1>("h00") - outer_arb.io.out.grant.bits.is_builtin_type <= UInt<1>("h00") - outer_arb.io.out.grant.bits.manager_xact_id <= UInt<1>("h00") - outer_arb.io.out.grant.bits.client_xact_id <= UInt<1>("h00") - outer_arb.io.out.grant.bits.addr_beat <= UInt<1>("h00") - outer_arb.io.out.grant.valid <= UInt<1>("h00") - outer_arb.io.out.acquire.ready <= UInt<1>("h00") - outer_arb.io.in[0].grant.ready <= UInt<1>("h00") - outer_arb.io.in[0].acquire.bits.data <= UInt<1>("h00") - outer_arb.io.in[0].acquire.bits.union <= UInt<1>("h00") - outer_arb.io.in[0].acquire.bits.a_type <= UInt<1>("h00") - outer_arb.io.in[0].acquire.bits.is_builtin_type <= UInt<1>("h00") - outer_arb.io.in[0].acquire.bits.addr_beat <= UInt<1>("h00") - outer_arb.io.in[0].acquire.bits.client_xact_id <= UInt<1>("h00") - outer_arb.io.in[0].acquire.bits.addr_block <= UInt<1>("h00") - outer_arb.io.in[0].acquire.valid <= UInt<1>("h00") - outer_arb.io.in[1].grant.ready <= UInt<1>("h00") - outer_arb.io.in[1].acquire.bits.data <= UInt<1>("h00") - outer_arb.io.in[1].acquire.bits.union <= UInt<1>("h00") - outer_arb.io.in[1].acquire.bits.a_type <= UInt<1>("h00") - outer_arb.io.in[1].acquire.bits.is_builtin_type <= UInt<1>("h00") - outer_arb.io.in[1].acquire.bits.addr_beat <= UInt<1>("h00") - outer_arb.io.in[1].acquire.bits.client_xact_id <= UInt<1>("h00") - outer_arb.io.in[1].acquire.bits.addr_block <= UInt<1>("h00") - outer_arb.io.in[1].acquire.valid <= UInt<1>("h00") - outer_arb.io.in[2].grant.ready <= UInt<1>("h00") - outer_arb.io.in[2].acquire.bits.data <= UInt<1>("h00") - outer_arb.io.in[2].acquire.bits.union <= UInt<1>("h00") - outer_arb.io.in[2].acquire.bits.a_type <= UInt<1>("h00") - outer_arb.io.in[2].acquire.bits.is_builtin_type <= UInt<1>("h00") - outer_arb.io.in[2].acquire.bits.addr_beat <= UInt<1>("h00") - outer_arb.io.in[2].acquire.bits.client_xact_id <= UInt<1>("h00") - outer_arb.io.in[2].acquire.bits.addr_block <= UInt<1>("h00") - outer_arb.io.in[2].acquire.valid <= UInt<1>("h00") - outer_arb.io.in[3].grant.ready <= UInt<1>("h00") - outer_arb.io.in[3].acquire.bits.data <= UInt<1>("h00") - outer_arb.io.in[3].acquire.bits.union <= UInt<1>("h00") - outer_arb.io.in[3].acquire.bits.a_type <= UInt<1>("h00") - outer_arb.io.in[3].acquire.bits.is_builtin_type <= UInt<1>("h00") - outer_arb.io.in[3].acquire.bits.addr_beat <= UInt<1>("h00") - outer_arb.io.in[3].acquire.bits.client_xact_id <= UInt<1>("h00") - outer_arb.io.in[3].acquire.bits.addr_block <= UInt<1>("h00") - outer_arb.io.in[3].acquire.valid <= UInt<1>("h00") - outer_arb.io.in[4].grant.ready <= UInt<1>("h00") - outer_arb.io.in[4].acquire.bits.data <= UInt<1>("h00") - outer_arb.io.in[4].acquire.bits.union <= UInt<1>("h00") - outer_arb.io.in[4].acquire.bits.a_type <= UInt<1>("h00") - outer_arb.io.in[4].acquire.bits.is_builtin_type <= UInt<1>("h00") - outer_arb.io.in[4].acquire.bits.addr_beat <= UInt<1>("h00") - outer_arb.io.in[4].acquire.bits.client_xact_id <= UInt<1>("h00") - outer_arb.io.in[4].acquire.bits.addr_block <= UInt<1>("h00") - outer_arb.io.in[4].acquire.valid <= UInt<1>("h00") - outer_arb.io.in[5].grant.ready <= UInt<1>("h00") - outer_arb.io.in[5].acquire.bits.data <= UInt<1>("h00") - outer_arb.io.in[5].acquire.bits.union <= UInt<1>("h00") - outer_arb.io.in[5].acquire.bits.a_type <= UInt<1>("h00") - outer_arb.io.in[5].acquire.bits.is_builtin_type <= UInt<1>("h00") - outer_arb.io.in[5].acquire.bits.addr_beat <= UInt<1>("h00") - outer_arb.io.in[5].acquire.bits.client_xact_id <= UInt<1>("h00") - outer_arb.io.in[5].acquire.bits.addr_block <= UInt<1>("h00") - outer_arb.io.in[5].acquire.valid <= UInt<1>("h00") - outer_arb.io.in[6].grant.ready <= UInt<1>("h00") - outer_arb.io.in[6].acquire.bits.data <= UInt<1>("h00") - outer_arb.io.in[6].acquire.bits.union <= UInt<1>("h00") - outer_arb.io.in[6].acquire.bits.a_type <= UInt<1>("h00") - outer_arb.io.in[6].acquire.bits.is_builtin_type <= UInt<1>("h00") - outer_arb.io.in[6].acquire.bits.addr_beat <= UInt<1>("h00") - outer_arb.io.in[6].acquire.bits.client_xact_id <= UInt<1>("h00") - outer_arb.io.in[6].acquire.bits.addr_block <= UInt<1>("h00") - outer_arb.io.in[6].acquire.valid <= UInt<1>("h00") - outer_arb.io.in[7].grant.ready <= UInt<1>("h00") - outer_arb.io.in[7].acquire.bits.data <= UInt<1>("h00") - outer_arb.io.in[7].acquire.bits.union <= UInt<1>("h00") - outer_arb.io.in[7].acquire.bits.a_type <= UInt<1>("h00") - outer_arb.io.in[7].acquire.bits.is_builtin_type <= UInt<1>("h00") - outer_arb.io.in[7].acquire.bits.addr_beat <= UInt<1>("h00") - outer_arb.io.in[7].acquire.bits.client_xact_id <= UInt<1>("h00") - outer_arb.io.in[7].acquire.bits.addr_block <= UInt<1>("h00") - outer_arb.io.in[7].acquire.valid <= UInt<1>("h00") + outer_arb.io is invalid outer_arb.clk <= clk outer_arb.reset <= reset outer_arb.io.in[0] <- T_1060.io.outer - outer_arb.io.in[1] <- T_1091.io.outer - outer_arb.io.in[2] <- T_1122.io.outer - outer_arb.io.in[3] <- T_1153.io.outer - outer_arb.io.in[4] <- T_1184.io.outer - outer_arb.io.in[5] <- T_1215.io.outer - outer_arb.io.in[6] <- T_1246.io.outer - outer_arb.io.in[7] <- T_1277.io.outer + outer_arb.io.in[1] <- T_1061.io.outer + outer_arb.io.in[2] <- T_1062.io.outer + outer_arb.io.in[3] <- T_1063.io.outer + outer_arb.io.in[4] <- T_1064.io.outer + outer_arb.io.in[5] <- T_1065.io.outer + outer_arb.io.in[6] <- T_1066.io.outer + outer_arb.io.in[7] <- T_1067.io.outer wire outer_data_ptr : {idx : UInt<2>, loc : UInt<2>} - outer_data_ptr.loc <= UInt<1>("h00") - outer_data_ptr.idx <= UInt<1>("h00") - node T_3581 = bits(outer_arb.io.out.acquire.bits.data, 1, 0) - outer_data_ptr.loc <= T_3581 - node T_3582 = bits(outer_arb.io.out.acquire.bits.data, 3, 2) - outer_data_ptr.idx <= T_3582 + outer_data_ptr is invalid + node T_3130 = bits(outer_arb.io.out.acquire.bits.data, 1, 0) + outer_data_ptr.loc <= T_3130 + node T_3131 = bits(outer_arb.io.out.acquire.bits.data, 3, 2) + outer_data_ptr.idx <= T_3131 node is_in_sdq = eq(outer_data_ptr.loc, UInt<1>("h00")) - node T_3584 = and(io.outer.acquire.ready, io.outer.acquire.valid) - wire T_3589 : UInt<3>[3] - T_3589[0] <= UInt<3>("h02") - T_3589[1] <= UInt<3>("h03") - T_3589[2] <= UInt<3>("h04") - node T_3594 = eq(T_3589[0], io.outer.acquire.bits.a_type) - node T_3595 = eq(T_3589[1], io.outer.acquire.bits.a_type) - node T_3596 = eq(T_3589[2], io.outer.acquire.bits.a_type) - node T_3598 = or(UInt<1>("h00"), T_3594) - node T_3599 = or(T_3598, T_3595) - node T_3600 = or(T_3599, T_3596) - node T_3601 = and(io.outer.acquire.bits.is_builtin_type, T_3600) - node T_3602 = and(T_3584, T_3601) - node T_3603 = eq(outer_data_ptr.loc, UInt<1>("h00")) - node free_sdq = and(T_3602, T_3603) + node T_3133 = and(io.outer.acquire.ready, io.outer.acquire.valid) + wire T_3138 : UInt<3>[3] + T_3138[0] <= UInt<3>("h02") + T_3138[1] <= UInt<3>("h03") + T_3138[2] <= UInt<3>("h04") + node T_3143 = eq(T_3138[0], io.outer.acquire.bits.a_type) + node T_3144 = eq(T_3138[1], io.outer.acquire.bits.a_type) + node T_3145 = eq(T_3138[2], io.outer.acquire.bits.a_type) + node T_3147 = or(UInt<1>("h00"), T_3143) + node T_3148 = or(T_3147, T_3144) + node T_3149 = or(T_3148, T_3145) + node T_3150 = and(io.outer.acquire.bits.is_builtin_type, T_3149) + node T_3151 = and(T_3133, T_3150) + node T_3152 = eq(outer_data_ptr.loc, UInt<1>("h00")) + node free_sdq = and(T_3151, T_3152) io.outer <- outer_arb.io.out - node T_3607 = eq(UInt<1>("h01"), outer_data_ptr.loc) - node T_3608 = mux(T_3607, vwbdq[outer_data_ptr.idx], io.inner.release.bits.data) - node T_3609 = eq(UInt<1>("h00"), outer_data_ptr.loc) - node T_3610 = mux(T_3609, sdq[outer_data_ptr.idx], T_3608) - io.outer.acquire.bits.data <= T_3610 - node T_3611 = or(io.outer.acquire.valid, sdq_enq) - when T_3611 : - node T_3613 = dshl(UInt<1>("h01"), outer_data_ptr.idx) - node T_3615 = subw(UInt<4>("h00"), free_sdq) - node T_3616 = and(T_3613, T_3615) - node T_3617 = not(T_3616) - node T_3618 = and(sdq_val, T_3617) - node T_3619 = bits(sdq_val, 3, 0) - node T_3620 = not(T_3619) - node T_3621 = bit(T_3620, 0) - node T_3622 = bit(T_3620, 1) - node T_3623 = bit(T_3620, 2) - node T_3624 = bit(T_3620, 3) - wire T_3630 : UInt<4>[4] - T_3630[0] <= UInt<4>("h01") - T_3630[1] <= UInt<4>("h02") - T_3630[2] <= UInt<4>("h04") - T_3630[3] <= UInt<4>("h08") - node T_3638 = mux(T_3624, T_3630[3], UInt<4>("h00")) - node T_3639 = mux(T_3623, T_3630[2], T_3638) - node T_3640 = mux(T_3622, T_3630[1], T_3639) - node T_3641 = mux(T_3621, T_3630[0], T_3640) - node T_3643 = subw(UInt<4>("h00"), sdq_enq) - node T_3644 = and(T_3641, T_3643) - node T_3645 = or(T_3618, T_3644) - sdq_val <= T_3645 + node T_3156 = eq(UInt<1>("h01"), outer_data_ptr.loc) + node T_3157 = mux(T_3156, vwbdq[outer_data_ptr.idx], io.inner.release.bits.data) + node T_3158 = eq(UInt<1>("h00"), outer_data_ptr.loc) + node T_3159 = mux(T_3158, sdq[outer_data_ptr.idx], T_3157) + io.outer.acquire.bits.data <= T_3159 + node T_3160 = or(io.outer.acquire.valid, sdq_enq) + when T_3160 : + node T_3162 = dshl(UInt<1>("h01"), outer_data_ptr.idx) + node T_3164 = sub(UInt<4>("h00"), free_sdq) + node T_3165 = tail(T_3164, 1) + node T_3166 = and(T_3162, T_3165) + node T_3167 = not(T_3166) + node T_3168 = and(sdq_val, T_3167) + node T_3169 = bits(sdq_val, 3, 0) + node T_3170 = not(T_3169) + node T_3171 = bits(T_3170, 0, 0) + node T_3172 = bits(T_3170, 1, 1) + node T_3173 = bits(T_3170, 2, 2) + node T_3174 = bits(T_3170, 3, 3) + wire T_3180 : UInt<4>[4] + T_3180[0] <= UInt<4>("h01") + T_3180[1] <= UInt<4>("h02") + T_3180[2] <= UInt<4>("h04") + T_3180[3] <= UInt<4>("h08") + node T_3188 = mux(T_3174, T_3180[3], UInt<4>("h00")) + node T_3189 = mux(T_3173, T_3180[2], T_3188) + node T_3190 = mux(T_3172, T_3180[1], T_3189) + node T_3191 = mux(T_3171, T_3180[0], T_3190) + node T_3193 = sub(UInt<4>("h00"), sdq_enq) + node T_3194 = tail(T_3193, 1) + node T_3195 = and(T_3191, T_3194) + node T_3196 = or(T_3168, T_3195) + sdq_val <= T_3196 skip module Queue_36 : @@ -11771,24 +9601,11 @@ circuit Top : input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, count : UInt<2>} - io.count <= UInt<1>("h00") - io.deq.bits.user <= UInt<1>("h00") - io.deq.bits.id <= UInt<1>("h00") - io.deq.bits.region <= UInt<1>("h00") - io.deq.bits.qos <= UInt<1>("h00") - io.deq.bits.prot <= UInt<1>("h00") - io.deq.bits.cache <= UInt<1>("h00") - io.deq.bits.lock <= UInt<1>("h00") - io.deq.bits.burst <= UInt<1>("h00") - io.deq.bits.size <= UInt<1>("h00") - io.deq.bits.len <= UInt<1>("h00") - io.deq.bits.addr <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}[2] - reg T_125 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_127 : UInt<1>, clk, reset, UInt<1>("h00") - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg T_125 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_127 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(T_125, T_127) node T_132 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_132) @@ -11806,54 +9623,50 @@ circuit Top : T_146 <- io.enq.bits node T_159 = eq(T_125, UInt<1>("h01")) node T_161 = and(UInt<1>("h00"), T_159) - node T_164 = addw(T_125, UInt<1>("h01")) - node T_165 = mux(T_161, UInt<1>("h00"), T_164) - T_125 <= T_165 + node T_164 = add(T_125, UInt<1>("h01")) + node T_165 = tail(T_164, 1) + node T_166 = mux(T_161, UInt<1>("h00"), T_165) + T_125 <= T_166 skip when do_deq : - node T_167 = eq(T_127, UInt<1>("h01")) - node T_169 = and(UInt<1>("h00"), T_167) - node T_172 = addw(T_127, UInt<1>("h01")) - node T_173 = mux(T_169, UInt<1>("h00"), T_172) - T_127 <= T_173 - skip - node T_174 = neq(do_enq, do_deq) - when T_174 : + node T_168 = eq(T_127, UInt<1>("h01")) + node T_170 = and(UInt<1>("h00"), T_168) + node T_173 = add(T_127, UInt<1>("h01")) + node T_174 = tail(T_173, 1) + node T_175 = mux(T_170, UInt<1>("h00"), T_174) + T_127 <= T_175 + skip + node T_176 = neq(do_enq, do_deq) + when T_176 : maybe_full <= do_enq skip - node T_176 = eq(empty, UInt<1>("h00")) - node T_178 = and(UInt<1>("h00"), io.enq.valid) - node T_179 = or(T_176, T_178) - io.deq.valid <= T_179 - node T_181 = eq(full, UInt<1>("h00")) - node T_183 = and(UInt<1>("h00"), io.deq.ready) - node T_184 = or(T_181, T_183) - io.enq.ready <= T_184 - infer mport T_185 = ram[T_127], clk - wire T_209 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} - T_209 <- T_185 - when maybe_flow : - T_209 <- io.enq.bits - skip - io.deq.bits <- T_209 - node ptr_diff = subw(T_125, T_127) - node T_222 = and(maybe_full, ptr_match) - node T_223 = cat(T_222, ptr_diff) - io.count <= T_223 + node T_178 = eq(empty, UInt<1>("h00")) + node T_180 = and(UInt<1>("h00"), io.enq.valid) + node T_181 = or(T_178, T_180) + io.deq.valid <= T_181 + node T_183 = eq(full, UInt<1>("h00")) + node T_185 = and(UInt<1>("h00"), io.deq.ready) + node T_186 = or(T_183, T_185) + io.enq.ready <= T_186 + infer mport T_187 = ram[T_127], clk + node T_199 = mux(maybe_flow, io.enq.bits, T_187) + io.deq.bits <- T_199 + node T_211 = sub(T_125, T_127) + node ptr_diff = tail(T_211, 1) + node T_213 = and(maybe_full, ptr_match) + node T_214 = cat(T_213, ptr_diff) + io.count <= T_214 module Queue_37 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<5>}, count : UInt<2>} - io.count <= UInt<1>("h00") - io.deq.bits <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : UInt<5>[2] - reg T_26 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_28 : UInt<1>, clk, reset, UInt<1>("h00") - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg T_26 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_28 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(T_26, T_28) node T_33 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_33) @@ -11871,55 +9684,46 @@ circuit Top : T_47 <= io.enq.bits node T_49 = eq(T_26, UInt<1>("h01")) node T_51 = and(UInt<1>("h00"), T_49) - node T_54 = addw(T_26, UInt<1>("h01")) - node T_55 = mux(T_51, UInt<1>("h00"), T_54) - T_26 <= T_55 + node T_54 = add(T_26, UInt<1>("h01")) + node T_55 = tail(T_54, 1) + node T_56 = mux(T_51, UInt<1>("h00"), T_55) + T_26 <= T_56 skip when do_deq : - node T_57 = eq(T_28, UInt<1>("h01")) - node T_59 = and(UInt<1>("h00"), T_57) - node T_62 = addw(T_28, UInt<1>("h01")) - node T_63 = mux(T_59, UInt<1>("h00"), T_62) - T_28 <= T_63 - skip - node T_64 = neq(do_enq, do_deq) - when T_64 : + node T_58 = eq(T_28, UInt<1>("h01")) + node T_60 = and(UInt<1>("h00"), T_58) + node T_63 = add(T_28, UInt<1>("h01")) + node T_64 = tail(T_63, 1) + node T_65 = mux(T_60, UInt<1>("h00"), T_64) + T_28 <= T_65 + skip + node T_66 = neq(do_enq, do_deq) + when T_66 : maybe_full <= do_enq skip - node T_66 = eq(empty, UInt<1>("h00")) - node T_68 = and(UInt<1>("h00"), io.enq.valid) - node T_69 = or(T_66, T_68) - io.deq.valid <= T_69 - node T_71 = eq(full, UInt<1>("h00")) - node T_73 = and(UInt<1>("h00"), io.deq.ready) - node T_74 = or(T_71, T_73) - io.enq.ready <= T_74 - infer mport T_75 = ram[T_28], clk - node T_76 = mux(maybe_flow, io.enq.bits, T_75) - io.deq.bits <= T_76 - node ptr_diff = subw(T_26, T_28) - node T_78 = and(maybe_full, ptr_match) - node T_79 = cat(T_78, ptr_diff) - io.count <= T_79 + node T_68 = eq(empty, UInt<1>("h00")) + node T_70 = and(UInt<1>("h00"), io.enq.valid) + node T_71 = or(T_68, T_70) + io.deq.valid <= T_71 + node T_73 = eq(full, UInt<1>("h00")) + node T_75 = and(UInt<1>("h00"), io.deq.ready) + node T_76 = or(T_73, T_75) + io.enq.ready <= T_76 + infer mport T_77 = ram[T_28], clk + node T_78 = mux(maybe_flow, io.enq.bits, T_77) + io.deq.bits <= T_78 + node T_79 = sub(T_26, T_28) + node ptr_diff = tail(T_79, 1) + node T_81 = and(maybe_full, ptr_match) + node T_82 = cat(T_81, ptr_diff) + io.count <= T_82 module NastiErrorSlave : input clk : Clock input reset : UInt<1> input io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} - io.r.bits.user <= UInt<1>("h00") - io.r.bits.id <= UInt<1>("h00") - io.r.bits.last <= UInt<1>("h00") - io.r.bits.data <= UInt<1>("h00") - io.r.bits.resp <= UInt<1>("h00") - io.r.valid <= UInt<1>("h00") - io.ar.ready <= UInt<1>("h00") - io.b.bits.user <= UInt<1>("h00") - io.b.bits.id <= UInt<1>("h00") - io.b.bits.resp <= UInt<1>("h00") - io.b.valid <= UInt<1>("h00") - io.w.ready <= UInt<1>("h00") - io.aw.ready <= UInt<1>("h00") + io is invalid node T_322 = and(io.ar.ready, io.ar.valid) when T_322 : node T_324 = eq(reset, UInt<1>("h00")) @@ -11937,227 +9741,205 @@ circuit Top : skip skip inst r_queue of Queue_36 - r_queue.io.deq.ready <= UInt<1>("h00") - r_queue.io.enq.bits.user <= UInt<1>("h00") - r_queue.io.enq.bits.id <= UInt<1>("h00") - r_queue.io.enq.bits.region <= UInt<1>("h00") - r_queue.io.enq.bits.qos <= UInt<1>("h00") - r_queue.io.enq.bits.prot <= UInt<1>("h00") - r_queue.io.enq.bits.cache <= UInt<1>("h00") - r_queue.io.enq.bits.lock <= UInt<1>("h00") - r_queue.io.enq.bits.burst <= UInt<1>("h00") - r_queue.io.enq.bits.size <= UInt<1>("h00") - r_queue.io.enq.bits.len <= UInt<1>("h00") - r_queue.io.enq.bits.addr <= UInt<1>("h00") - r_queue.io.enq.valid <= UInt<1>("h00") + r_queue.io is invalid r_queue.clk <= clk r_queue.reset <= reset r_queue.io.enq <- io.ar - reg responding : UInt<1>, clk, reset, UInt<1>("h00") - reg beats_left : UInt<8>, clk, reset, UInt<8>("h00") - node T_359 = eq(responding, UInt<1>("h00")) - node T_360 = and(T_359, r_queue.io.deq.valid) - when T_360 : + reg responding : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg beats_left : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) + node T_346 = eq(responding, UInt<1>("h00")) + node T_347 = and(T_346, r_queue.io.deq.valid) + when T_347 : responding <= UInt<1>("h01") beats_left <= r_queue.io.deq.bits.len skip - node T_362 = and(r_queue.io.deq.valid, responding) - io.r.valid <= T_362 + node T_349 = and(r_queue.io.deq.valid, responding) + io.r.valid <= T_349 io.r.bits.id <= r_queue.io.deq.bits.id io.r.bits.data <= UInt<1>("h00") io.r.bits.resp <= UInt<2>("h03") - node T_372 = eq(beats_left, UInt<1>("h00")) - io.r.bits.last <= T_372 - node T_373 = and(io.r.ready, io.r.valid) - node T_374 = and(T_373, io.r.bits.last) - r_queue.io.deq.ready <= T_374 - node T_375 = and(io.r.ready, io.r.valid) - when T_375 : - node T_377 = eq(beats_left, UInt<1>("h00")) - when T_377 : + node T_359 = eq(beats_left, UInt<1>("h00")) + io.r.bits.last <= T_359 + node T_360 = and(io.r.ready, io.r.valid) + node T_361 = and(T_360, io.r.bits.last) + r_queue.io.deq.ready <= T_361 + node T_362 = and(io.r.ready, io.r.valid) + when T_362 : + node T_364 = eq(beats_left, UInt<1>("h00")) + when T_364 : responding <= UInt<1>("h00") skip - node T_380 = eq(T_377, UInt<1>("h00")) - when T_380 : - node T_382 = subw(beats_left, UInt<1>("h01")) - beats_left <= T_382 + node T_367 = eq(T_364, UInt<1>("h00")) + when T_367 : + node T_369 = sub(beats_left, UInt<1>("h01")) + node T_370 = tail(T_369, 1) + beats_left <= T_370 skip skip - reg draining : UInt<1>, clk, reset, UInt<1>("h00") + reg draining : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) io.w.ready <= draining - node T_385 = and(io.aw.ready, io.aw.valid) - when T_385 : + node T_373 = and(io.aw.ready, io.aw.valid) + when T_373 : draining <= UInt<1>("h01") skip - node T_387 = and(io.w.ready, io.w.valid) - node T_388 = and(T_387, io.w.bits.last) - when T_388 : + node T_375 = and(io.w.ready, io.w.valid) + node T_376 = and(T_375, io.w.bits.last) + when T_376 : draining <= UInt<1>("h00") skip inst b_queue of Queue_37 - b_queue.io.deq.ready <= UInt<1>("h00") - b_queue.io.enq.bits <= UInt<1>("h00") - b_queue.io.enq.valid <= UInt<1>("h00") + b_queue.io is invalid b_queue.clk <= clk b_queue.reset <= reset - node T_396 = eq(draining, UInt<1>("h00")) - node T_397 = and(io.aw.valid, T_396) - b_queue.io.enq.valid <= T_397 + node T_381 = eq(draining, UInt<1>("h00")) + node T_382 = and(io.aw.valid, T_381) + b_queue.io.enq.valid <= T_382 b_queue.io.enq.bits <= io.aw.bits.id - node T_399 = eq(draining, UInt<1>("h00")) - node T_400 = and(b_queue.io.enq.ready, T_399) - io.aw.ready <= T_400 - node T_402 = eq(draining, UInt<1>("h00")) - node T_403 = and(b_queue.io.deq.valid, T_402) - io.b.valid <= T_403 + node T_384 = eq(draining, UInt<1>("h00")) + node T_385 = and(b_queue.io.enq.ready, T_384) + io.aw.ready <= T_385 + node T_387 = eq(draining, UInt<1>("h00")) + node T_388 = and(b_queue.io.deq.valid, T_387) + io.b.valid <= T_388 io.b.bits.id <= b_queue.io.deq.bits io.b.bits.resp <= UInt<2>("h03") - node T_406 = eq(draining, UInt<1>("h00")) - node T_407 = and(io.b.ready, T_406) - b_queue.io.deq.ready <= T_407 + node T_391 = eq(draining, UInt<1>("h00")) + node T_392 = and(io.b.ready, T_391) + b_queue.io.deq.ready <= T_392 module RRArbiter_38 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}[5], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, chosen : UInt<3>} - io.chosen <= UInt<1>("h00") - io.out.bits.user <= UInt<1>("h00") - io.out.bits.id <= UInt<1>("h00") - io.out.bits.resp <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") - io.in[2].ready <= UInt<1>("h00") - io.in[3].ready <= UInt<1>("h00") - io.in[4].ready <= UInt<1>("h00") + io is invalid wire T_196 : UInt<3> - T_196 <= UInt<1>("h00") + T_196 is invalid io.out.valid <= io.in[T_196].valid io.out.bits <- io.in[T_196].bits io.chosen <= T_196 io.in[T_196].ready <= UInt<1>("h00") - reg T_234 : UInt<3>, clk, reset, UInt<3>("h00") - node T_235 = gt(UInt<1>("h00"), T_234) - node T_236 = and(io.in[0].valid, T_235) - node T_238 = gt(UInt<1>("h01"), T_234) - node T_239 = and(io.in[1].valid, T_238) - node T_241 = gt(UInt<2>("h02"), T_234) - node T_242 = and(io.in[2].valid, T_241) - node T_244 = gt(UInt<2>("h03"), T_234) - node T_245 = and(io.in[3].valid, T_244) - node T_247 = gt(UInt<3>("h04"), T_234) - node T_248 = and(io.in[4].valid, T_247) - node T_251 = or(UInt<1>("h00"), T_236) - node T_253 = eq(T_251, UInt<1>("h00")) - node T_255 = or(UInt<1>("h00"), T_236) - node T_256 = or(T_255, T_239) - node T_258 = eq(T_256, UInt<1>("h00")) - node T_260 = or(UInt<1>("h00"), T_236) - node T_261 = or(T_260, T_239) - node T_262 = or(T_261, T_242) - node T_264 = eq(T_262, UInt<1>("h00")) - node T_266 = or(UInt<1>("h00"), T_236) - node T_267 = or(T_266, T_239) - node T_268 = or(T_267, T_242) - node T_269 = or(T_268, T_245) - node T_271 = eq(T_269, UInt<1>("h00")) - node T_273 = or(UInt<1>("h00"), T_236) - node T_274 = or(T_273, T_239) - node T_275 = or(T_274, T_242) - node T_276 = or(T_275, T_245) - node T_277 = or(T_276, T_248) - node T_279 = eq(T_277, UInt<1>("h00")) - node T_281 = or(UInt<1>("h00"), T_236) - node T_282 = or(T_281, T_239) - node T_283 = or(T_282, T_242) - node T_284 = or(T_283, T_245) - node T_285 = or(T_284, T_248) - node T_286 = or(T_285, io.in[0].valid) - node T_288 = eq(T_286, UInt<1>("h00")) - node T_290 = or(UInt<1>("h00"), T_236) - node T_291 = or(T_290, T_239) - node T_292 = or(T_291, T_242) - node T_293 = or(T_292, T_245) - node T_294 = or(T_293, T_248) - node T_295 = or(T_294, io.in[0].valid) - node T_296 = or(T_295, io.in[1].valid) - node T_298 = eq(T_296, UInt<1>("h00")) - node T_300 = or(UInt<1>("h00"), T_236) - node T_301 = or(T_300, T_239) - node T_302 = or(T_301, T_242) - node T_303 = or(T_302, T_245) - node T_304 = or(T_303, T_248) - node T_305 = or(T_304, io.in[0].valid) - node T_306 = or(T_305, io.in[1].valid) - node T_307 = or(T_306, io.in[2].valid) - node T_309 = eq(T_307, UInt<1>("h00")) - node T_311 = or(UInt<1>("h00"), T_236) - node T_312 = or(T_311, T_239) - node T_313 = or(T_312, T_242) - node T_314 = or(T_313, T_245) - node T_315 = or(T_314, T_248) - node T_316 = or(T_315, io.in[0].valid) - node T_317 = or(T_316, io.in[1].valid) - node T_318 = or(T_317, io.in[2].valid) - node T_319 = or(T_318, io.in[3].valid) - node T_321 = eq(T_319, UInt<1>("h00")) - node T_323 = gt(UInt<1>("h00"), T_234) - node T_324 = and(UInt<1>("h01"), T_323) - node T_325 = or(T_324, T_279) - node T_327 = gt(UInt<1>("h01"), T_234) - node T_328 = and(T_253, T_327) - node T_329 = or(T_328, T_288) - node T_331 = gt(UInt<2>("h02"), T_234) - node T_332 = and(T_258, T_331) - node T_333 = or(T_332, T_298) - node T_335 = gt(UInt<2>("h03"), T_234) - node T_336 = and(T_264, T_335) - node T_337 = or(T_336, T_309) - node T_339 = gt(UInt<3>("h04"), T_234) - node T_340 = and(T_271, T_339) - node T_341 = or(T_340, T_321) - node T_343 = eq(UInt<3>("h04"), UInt<1>("h00")) - node T_344 = mux(UInt<1>("h00"), T_343, T_325) - node T_345 = and(T_344, io.out.ready) - io.in[0].ready <= T_345 - node T_347 = eq(UInt<3>("h04"), UInt<1>("h01")) - node T_348 = mux(UInt<1>("h00"), T_347, T_329) - node T_349 = and(T_348, io.out.ready) - io.in[1].ready <= T_349 - node T_351 = eq(UInt<3>("h04"), UInt<2>("h02")) - node T_352 = mux(UInt<1>("h00"), T_351, T_333) - node T_353 = and(T_352, io.out.ready) - io.in[2].ready <= T_353 - node T_355 = eq(UInt<3>("h04"), UInt<2>("h03")) - node T_356 = mux(UInt<1>("h00"), T_355, T_337) - node T_357 = and(T_356, io.out.ready) - io.in[3].ready <= T_357 - node T_359 = eq(UInt<3>("h04"), UInt<3>("h04")) - node T_360 = mux(UInt<1>("h00"), T_359, T_341) - node T_361 = and(T_360, io.out.ready) - io.in[4].ready <= T_361 - node T_364 = mux(io.in[3].valid, UInt<2>("h03"), UInt<3>("h04")) - node T_366 = mux(io.in[2].valid, UInt<2>("h02"), T_364) - node T_368 = mux(io.in[1].valid, UInt<1>("h01"), T_366) - node T_370 = mux(io.in[0].valid, UInt<1>("h00"), T_368) - node T_372 = gt(UInt<3>("h04"), T_234) - node T_373 = and(io.in[4].valid, T_372) - node T_375 = mux(T_373, UInt<3>("h04"), T_370) - node T_377 = gt(UInt<2>("h03"), T_234) - node T_378 = and(io.in[3].valid, T_377) - node T_380 = mux(T_378, UInt<2>("h03"), T_375) - node T_382 = gt(UInt<2>("h02"), T_234) - node T_383 = and(io.in[2].valid, T_382) - node T_385 = mux(T_383, UInt<2>("h02"), T_380) - node T_387 = gt(UInt<1>("h01"), T_234) - node T_388 = and(io.in[1].valid, T_387) - node T_390 = mux(T_388, UInt<1>("h01"), T_385) - node T_391 = mux(UInt<1>("h00"), UInt<3>("h04"), T_390) - T_196 <= T_391 - node T_392 = and(io.out.ready, io.out.valid) - when T_392 : - T_234 <= T_196 + reg T_233 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + node T_234 = gt(UInt<1>("h00"), T_233) + node T_235 = and(io.in[0].valid, T_234) + node T_237 = gt(UInt<1>("h01"), T_233) + node T_238 = and(io.in[1].valid, T_237) + node T_240 = gt(UInt<2>("h02"), T_233) + node T_241 = and(io.in[2].valid, T_240) + node T_243 = gt(UInt<2>("h03"), T_233) + node T_244 = and(io.in[3].valid, T_243) + node T_246 = gt(UInt<3>("h04"), T_233) + node T_247 = and(io.in[4].valid, T_246) + node T_250 = or(UInt<1>("h00"), T_235) + node T_252 = eq(T_250, UInt<1>("h00")) + node T_254 = or(UInt<1>("h00"), T_235) + node T_255 = or(T_254, T_238) + node T_257 = eq(T_255, UInt<1>("h00")) + node T_259 = or(UInt<1>("h00"), T_235) + node T_260 = or(T_259, T_238) + node T_261 = or(T_260, T_241) + node T_263 = eq(T_261, UInt<1>("h00")) + node T_265 = or(UInt<1>("h00"), T_235) + node T_266 = or(T_265, T_238) + node T_267 = or(T_266, T_241) + node T_268 = or(T_267, T_244) + node T_270 = eq(T_268, UInt<1>("h00")) + node T_272 = or(UInt<1>("h00"), T_235) + node T_273 = or(T_272, T_238) + node T_274 = or(T_273, T_241) + node T_275 = or(T_274, T_244) + node T_276 = or(T_275, T_247) + node T_278 = eq(T_276, UInt<1>("h00")) + node T_280 = or(UInt<1>("h00"), T_235) + node T_281 = or(T_280, T_238) + node T_282 = or(T_281, T_241) + node T_283 = or(T_282, T_244) + node T_284 = or(T_283, T_247) + node T_285 = or(T_284, io.in[0].valid) + node T_287 = eq(T_285, UInt<1>("h00")) + node T_289 = or(UInt<1>("h00"), T_235) + node T_290 = or(T_289, T_238) + node T_291 = or(T_290, T_241) + node T_292 = or(T_291, T_244) + node T_293 = or(T_292, T_247) + node T_294 = or(T_293, io.in[0].valid) + node T_295 = or(T_294, io.in[1].valid) + node T_297 = eq(T_295, UInt<1>("h00")) + node T_299 = or(UInt<1>("h00"), T_235) + node T_300 = or(T_299, T_238) + node T_301 = or(T_300, T_241) + node T_302 = or(T_301, T_244) + node T_303 = or(T_302, T_247) + node T_304 = or(T_303, io.in[0].valid) + node T_305 = or(T_304, io.in[1].valid) + node T_306 = or(T_305, io.in[2].valid) + node T_308 = eq(T_306, UInt<1>("h00")) + node T_310 = or(UInt<1>("h00"), T_235) + node T_311 = or(T_310, T_238) + node T_312 = or(T_311, T_241) + node T_313 = or(T_312, T_244) + node T_314 = or(T_313, T_247) + node T_315 = or(T_314, io.in[0].valid) + node T_316 = or(T_315, io.in[1].valid) + node T_317 = or(T_316, io.in[2].valid) + node T_318 = or(T_317, io.in[3].valid) + node T_320 = eq(T_318, UInt<1>("h00")) + node T_322 = gt(UInt<1>("h00"), T_233) + node T_323 = and(UInt<1>("h01"), T_322) + node T_324 = or(T_323, T_278) + node T_326 = gt(UInt<1>("h01"), T_233) + node T_327 = and(T_252, T_326) + node T_328 = or(T_327, T_287) + node T_330 = gt(UInt<2>("h02"), T_233) + node T_331 = and(T_257, T_330) + node T_332 = or(T_331, T_297) + node T_334 = gt(UInt<2>("h03"), T_233) + node T_335 = and(T_263, T_334) + node T_336 = or(T_335, T_308) + node T_338 = gt(UInt<3>("h04"), T_233) + node T_339 = and(T_270, T_338) + node T_340 = or(T_339, T_320) + node T_342 = eq(UInt<3>("h04"), UInt<1>("h00")) + node T_343 = mux(UInt<1>("h00"), T_342, T_324) + node T_344 = and(T_343, io.out.ready) + io.in[0].ready <= T_344 + node T_346 = eq(UInt<3>("h04"), UInt<1>("h01")) + node T_347 = mux(UInt<1>("h00"), T_346, T_328) + node T_348 = and(T_347, io.out.ready) + io.in[1].ready <= T_348 + node T_350 = eq(UInt<3>("h04"), UInt<2>("h02")) + node T_351 = mux(UInt<1>("h00"), T_350, T_332) + node T_352 = and(T_351, io.out.ready) + io.in[2].ready <= T_352 + node T_354 = eq(UInt<3>("h04"), UInt<2>("h03")) + node T_355 = mux(UInt<1>("h00"), T_354, T_336) + node T_356 = and(T_355, io.out.ready) + io.in[3].ready <= T_356 + node T_358 = eq(UInt<3>("h04"), UInt<3>("h04")) + node T_359 = mux(UInt<1>("h00"), T_358, T_340) + node T_360 = and(T_359, io.out.ready) + io.in[4].ready <= T_360 + node T_363 = mux(io.in[3].valid, UInt<2>("h03"), UInt<3>("h04")) + node T_365 = mux(io.in[2].valid, UInt<2>("h02"), T_363) + node T_367 = mux(io.in[1].valid, UInt<1>("h01"), T_365) + node T_369 = mux(io.in[0].valid, UInt<1>("h00"), T_367) + node T_371 = gt(UInt<3>("h04"), T_233) + node T_372 = and(io.in[4].valid, T_371) + node T_374 = mux(T_372, UInt<3>("h04"), T_369) + node T_376 = gt(UInt<2>("h03"), T_233) + node T_377 = and(io.in[3].valid, T_376) + node T_379 = mux(T_377, UInt<2>("h03"), T_374) + node T_381 = gt(UInt<2>("h02"), T_233) + node T_382 = and(io.in[2].valid, T_381) + node T_384 = mux(T_382, UInt<2>("h02"), T_379) + node T_386 = gt(UInt<1>("h01"), T_233) + node T_387 = and(io.in[1].valid, T_386) + node T_389 = mux(T_387, UInt<1>("h01"), T_384) + node T_390 = mux(UInt<1>("h00"), UInt<3>("h04"), T_389) + T_196 <= T_390 + node T_391 = and(io.out.ready, io.out.valid) + when T_391 : + T_233 <= T_196 skip module JunctionsPeekingArbiter : @@ -12165,113 +9947,125 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}[5], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} - io.out.bits.user <= UInt<1>("h00") - io.out.bits.id <= UInt<1>("h00") - io.out.bits.last <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.bits.resp <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") - io.in[2].ready <= UInt<1>("h00") - io.in[3].ready <= UInt<1>("h00") - io.in[4].ready <= UInt<1>("h00") - reg T_273 : UInt<3>, clk, reset, UInt<3>("h00") - reg T_275 : UInt<1>, clk, reset, UInt<1>("h00") + io is invalid + reg T_273 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + reg T_275 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) wire T_277 : UInt<1>[5] T_277[0] <= io.in[0].valid T_277[1] <= io.in[1].valid T_277[2] <= io.in[2].valid T_277[3] <= io.in[3].valid T_277[4] <= io.in[4].valid - node T_285 = addw(T_273, UInt<1>("h01")) - node T_287 = lt(T_285, UInt<3>("h05")) - node T_289 = addw(UInt<1>("h00"), T_285) - node T_292 = subw(T_285, UInt<3>("h05")) - node T_294 = mux(T_287, T_277[T_289], T_277[T_292]) - node T_296 = lt(T_285, UInt<3>("h04")) - node T_298 = addw(UInt<1>("h01"), T_285) - node T_301 = subw(T_285, UInt<3>("h04")) - node T_303 = mux(T_296, T_277[T_298], T_277[T_301]) - node T_305 = lt(T_285, UInt<2>("h03")) - node T_307 = addw(UInt<2>("h02"), T_285) - node T_310 = subw(T_285, UInt<2>("h03")) - node T_312 = mux(T_305, T_277[T_307], T_277[T_310]) - node T_314 = lt(T_285, UInt<2>("h02")) - node T_316 = addw(UInt<2>("h03"), T_285) - node T_319 = subw(T_285, UInt<2>("h02")) - node T_321 = mux(T_314, T_277[T_316], T_277[T_319]) - node T_323 = lt(T_285, UInt<1>("h01")) - node T_325 = addw(UInt<3>("h04"), T_285) - node T_328 = subw(T_285, UInt<1>("h01")) - node T_330 = mux(T_323, T_277[T_325], T_277[T_328]) - wire T_332 : UInt<1>[5] - T_332[0] <= T_294 - T_332[1] <= T_303 - T_332[2] <= T_312 - T_332[3] <= T_321 - T_332[4] <= T_330 - wire T_345 : UInt<3>[5] - T_345[0] <= UInt<1>("h00") - T_345[1] <= UInt<1>("h01") - T_345[2] <= UInt<2>("h02") - T_345[3] <= UInt<2>("h03") - T_345[4] <= UInt<3>("h04") - node T_353 = addw(T_273, UInt<1>("h01")) - node T_355 = lt(T_353, UInt<3>("h05")) - node T_357 = addw(UInt<1>("h00"), T_353) - node T_360 = subw(T_353, UInt<3>("h05")) - node T_362 = mux(T_355, T_345[T_357], T_345[T_360]) - node T_364 = lt(T_353, UInt<3>("h04")) - node T_366 = addw(UInt<1>("h01"), T_353) - node T_369 = subw(T_353, UInt<3>("h04")) - node T_371 = mux(T_364, T_345[T_366], T_345[T_369]) - node T_373 = lt(T_353, UInt<2>("h03")) - node T_375 = addw(UInt<2>("h02"), T_353) - node T_378 = subw(T_353, UInt<2>("h03")) - node T_380 = mux(T_373, T_345[T_375], T_345[T_378]) - node T_382 = lt(T_353, UInt<2>("h02")) - node T_384 = addw(UInt<2>("h03"), T_353) - node T_387 = subw(T_353, UInt<2>("h02")) - node T_389 = mux(T_382, T_345[T_384], T_345[T_387]) - node T_391 = lt(T_353, UInt<1>("h01")) - node T_393 = addw(UInt<3>("h04"), T_353) - node T_396 = subw(T_353, UInt<1>("h01")) - node T_398 = mux(T_391, T_345[T_393], T_345[T_396]) - wire T_400 : UInt<3>[5] - T_400[0] <= T_362 - T_400[1] <= T_371 - T_400[2] <= T_380 - T_400[3] <= T_389 - T_400[4] <= T_398 - node T_407 = mux(T_332[3], T_400[3], T_400[4]) - node T_408 = mux(T_332[2], T_400[2], T_407) - node T_409 = mux(T_332[1], T_400[1], T_408) - node T_410 = mux(T_332[0], T_400[0], T_409) - node T_411 = mux(T_275, T_273, T_410) - node T_413 = eq(T_411, UInt<1>("h00")) - node T_414 = and(io.out.ready, T_413) - io.in[0].ready <= T_414 - node T_416 = eq(T_411, UInt<1>("h01")) - node T_417 = and(io.out.ready, T_416) - io.in[1].ready <= T_417 - node T_419 = eq(T_411, UInt<2>("h02")) - node T_420 = and(io.out.ready, T_419) - io.in[2].ready <= T_420 - node T_422 = eq(T_411, UInt<2>("h03")) - node T_423 = and(io.out.ready, T_422) - io.in[3].ready <= T_423 - node T_425 = eq(T_411, UInt<3>("h04")) - node T_426 = and(io.out.ready, T_425) - io.in[4].ready <= T_426 - io.out.valid <= io.in[T_411].valid - io.out.bits <- io.in[T_411].bits - node T_457 = and(io.out.ready, io.out.valid) - when T_457 : - node T_459 = eq(T_275, UInt<1>("h00")) - node T_461 = and(T_459, UInt<1>("h01")) - when T_461 : - T_273 <= T_410 + node T_285 = add(T_273, UInt<1>("h01")) + node T_286 = tail(T_285, 1) + node T_288 = lt(T_286, UInt<3>("h05")) + node T_290 = add(UInt<1>("h00"), T_286) + node T_291 = tail(T_290, 1) + node T_294 = sub(T_286, UInt<3>("h05")) + node T_295 = tail(T_294, 1) + node T_297 = mux(T_288, T_277[T_291], T_277[T_295]) + node T_299 = lt(T_286, UInt<3>("h04")) + node T_301 = add(UInt<1>("h01"), T_286) + node T_302 = tail(T_301, 1) + node T_305 = sub(T_286, UInt<3>("h04")) + node T_306 = tail(T_305, 1) + node T_308 = mux(T_299, T_277[T_302], T_277[T_306]) + node T_310 = lt(T_286, UInt<2>("h03")) + node T_312 = add(UInt<2>("h02"), T_286) + node T_313 = tail(T_312, 1) + node T_316 = sub(T_286, UInt<2>("h03")) + node T_317 = tail(T_316, 1) + node T_319 = mux(T_310, T_277[T_313], T_277[T_317]) + node T_321 = lt(T_286, UInt<2>("h02")) + node T_323 = add(UInt<2>("h03"), T_286) + node T_324 = tail(T_323, 1) + node T_327 = sub(T_286, UInt<2>("h02")) + node T_328 = tail(T_327, 1) + node T_330 = mux(T_321, T_277[T_324], T_277[T_328]) + node T_332 = lt(T_286, UInt<1>("h01")) + node T_334 = add(UInt<3>("h04"), T_286) + node T_335 = tail(T_334, 1) + node T_338 = sub(T_286, UInt<1>("h01")) + node T_339 = tail(T_338, 1) + node T_341 = mux(T_332, T_277[T_335], T_277[T_339]) + wire T_343 : UInt<1>[5] + T_343[0] <= T_297 + T_343[1] <= T_308 + T_343[2] <= T_319 + T_343[3] <= T_330 + T_343[4] <= T_341 + wire T_356 : UInt<3>[5] + T_356[0] <= UInt<1>("h00") + T_356[1] <= UInt<1>("h01") + T_356[2] <= UInt<2>("h02") + T_356[3] <= UInt<2>("h03") + T_356[4] <= UInt<3>("h04") + node T_364 = add(T_273, UInt<1>("h01")) + node T_365 = tail(T_364, 1) + node T_367 = lt(T_365, UInt<3>("h05")) + node T_369 = add(UInt<1>("h00"), T_365) + node T_370 = tail(T_369, 1) + node T_373 = sub(T_365, UInt<3>("h05")) + node T_374 = tail(T_373, 1) + node T_376 = mux(T_367, T_356[T_370], T_356[T_374]) + node T_378 = lt(T_365, UInt<3>("h04")) + node T_380 = add(UInt<1>("h01"), T_365) + node T_381 = tail(T_380, 1) + node T_384 = sub(T_365, UInt<3>("h04")) + node T_385 = tail(T_384, 1) + node T_387 = mux(T_378, T_356[T_381], T_356[T_385]) + node T_389 = lt(T_365, UInt<2>("h03")) + node T_391 = add(UInt<2>("h02"), T_365) + node T_392 = tail(T_391, 1) + node T_395 = sub(T_365, UInt<2>("h03")) + node T_396 = tail(T_395, 1) + node T_398 = mux(T_389, T_356[T_392], T_356[T_396]) + node T_400 = lt(T_365, UInt<2>("h02")) + node T_402 = add(UInt<2>("h03"), T_365) + node T_403 = tail(T_402, 1) + node T_406 = sub(T_365, UInt<2>("h02")) + node T_407 = tail(T_406, 1) + node T_409 = mux(T_400, T_356[T_403], T_356[T_407]) + node T_411 = lt(T_365, UInt<1>("h01")) + node T_413 = add(UInt<3>("h04"), T_365) + node T_414 = tail(T_413, 1) + node T_417 = sub(T_365, UInt<1>("h01")) + node T_418 = tail(T_417, 1) + node T_420 = mux(T_411, T_356[T_414], T_356[T_418]) + wire T_422 : UInt<3>[5] + T_422[0] <= T_376 + T_422[1] <= T_387 + T_422[2] <= T_398 + T_422[3] <= T_409 + T_422[4] <= T_420 + node T_429 = mux(T_343[3], T_422[3], T_422[4]) + node T_430 = mux(T_343[2], T_422[2], T_429) + node T_431 = mux(T_343[1], T_422[1], T_430) + node T_432 = mux(T_343[0], T_422[0], T_431) + node T_433 = mux(T_275, T_273, T_432) + node T_435 = eq(T_433, UInt<1>("h00")) + node T_436 = and(io.out.ready, T_435) + io.in[0].ready <= T_436 + node T_438 = eq(T_433, UInt<1>("h01")) + node T_439 = and(io.out.ready, T_438) + io.in[1].ready <= T_439 + node T_441 = eq(T_433, UInt<2>("h02")) + node T_442 = and(io.out.ready, T_441) + io.in[2].ready <= T_442 + node T_444 = eq(T_433, UInt<2>("h03")) + node T_445 = and(io.out.ready, T_444) + io.in[3].ready <= T_445 + node T_447 = eq(T_433, UInt<3>("h04")) + node T_448 = and(io.out.ready, T_447) + io.in[4].ready <= T_448 + io.out.valid <= io.in[T_433].valid + io.out.bits <- io.in[T_433].bits + node T_479 = and(io.out.ready, io.out.valid) + when T_479 : + node T_481 = eq(T_275, UInt<1>("h00")) + node T_483 = and(T_481, UInt<1>("h01")) + when T_483 : + T_273 <= T_432 T_275 <= UInt<1>("h01") skip when io.out.bits.last : @@ -12284,143 +10078,7 @@ circuit Top : input reset : UInt<1> output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]} - io.slave[0].r.ready <= UInt<1>("h00") - io.slave[0].ar.bits.user <= UInt<1>("h00") - io.slave[0].ar.bits.id <= UInt<1>("h00") - io.slave[0].ar.bits.region <= UInt<1>("h00") - io.slave[0].ar.bits.qos <= UInt<1>("h00") - io.slave[0].ar.bits.prot <= UInt<1>("h00") - io.slave[0].ar.bits.cache <= UInt<1>("h00") - io.slave[0].ar.bits.lock <= UInt<1>("h00") - io.slave[0].ar.bits.burst <= UInt<1>("h00") - io.slave[0].ar.bits.size <= UInt<1>("h00") - io.slave[0].ar.bits.len <= UInt<1>("h00") - io.slave[0].ar.bits.addr <= UInt<1>("h00") - io.slave[0].ar.valid <= UInt<1>("h00") - io.slave[0].b.ready <= UInt<1>("h00") - io.slave[0].w.bits.user <= UInt<1>("h00") - io.slave[0].w.bits.strb <= UInt<1>("h00") - io.slave[0].w.bits.last <= UInt<1>("h00") - io.slave[0].w.bits.data <= UInt<1>("h00") - io.slave[0].w.valid <= UInt<1>("h00") - io.slave[0].aw.bits.user <= UInt<1>("h00") - io.slave[0].aw.bits.id <= UInt<1>("h00") - io.slave[0].aw.bits.region <= UInt<1>("h00") - io.slave[0].aw.bits.qos <= UInt<1>("h00") - io.slave[0].aw.bits.prot <= UInt<1>("h00") - io.slave[0].aw.bits.cache <= UInt<1>("h00") - io.slave[0].aw.bits.lock <= UInt<1>("h00") - io.slave[0].aw.bits.burst <= UInt<1>("h00") - io.slave[0].aw.bits.size <= UInt<1>("h00") - io.slave[0].aw.bits.len <= UInt<1>("h00") - io.slave[0].aw.bits.addr <= UInt<1>("h00") - io.slave[0].aw.valid <= UInt<1>("h00") - io.slave[1].r.ready <= UInt<1>("h00") - io.slave[1].ar.bits.user <= UInt<1>("h00") - io.slave[1].ar.bits.id <= UInt<1>("h00") - io.slave[1].ar.bits.region <= UInt<1>("h00") - io.slave[1].ar.bits.qos <= UInt<1>("h00") - io.slave[1].ar.bits.prot <= UInt<1>("h00") - io.slave[1].ar.bits.cache <= UInt<1>("h00") - io.slave[1].ar.bits.lock <= UInt<1>("h00") - io.slave[1].ar.bits.burst <= UInt<1>("h00") - io.slave[1].ar.bits.size <= UInt<1>("h00") - io.slave[1].ar.bits.len <= UInt<1>("h00") - io.slave[1].ar.bits.addr <= UInt<1>("h00") - io.slave[1].ar.valid <= UInt<1>("h00") - io.slave[1].b.ready <= UInt<1>("h00") - io.slave[1].w.bits.user <= UInt<1>("h00") - io.slave[1].w.bits.strb <= UInt<1>("h00") - io.slave[1].w.bits.last <= UInt<1>("h00") - io.slave[1].w.bits.data <= UInt<1>("h00") - io.slave[1].w.valid <= UInt<1>("h00") - io.slave[1].aw.bits.user <= UInt<1>("h00") - io.slave[1].aw.bits.id <= UInt<1>("h00") - io.slave[1].aw.bits.region <= UInt<1>("h00") - io.slave[1].aw.bits.qos <= UInt<1>("h00") - io.slave[1].aw.bits.prot <= UInt<1>("h00") - io.slave[1].aw.bits.cache <= UInt<1>("h00") - io.slave[1].aw.bits.lock <= UInt<1>("h00") - io.slave[1].aw.bits.burst <= UInt<1>("h00") - io.slave[1].aw.bits.size <= UInt<1>("h00") - io.slave[1].aw.bits.len <= UInt<1>("h00") - io.slave[1].aw.bits.addr <= UInt<1>("h00") - io.slave[1].aw.valid <= UInt<1>("h00") - io.slave[2].r.ready <= UInt<1>("h00") - io.slave[2].ar.bits.user <= UInt<1>("h00") - io.slave[2].ar.bits.id <= UInt<1>("h00") - io.slave[2].ar.bits.region <= UInt<1>("h00") - io.slave[2].ar.bits.qos <= UInt<1>("h00") - io.slave[2].ar.bits.prot <= UInt<1>("h00") - io.slave[2].ar.bits.cache <= UInt<1>("h00") - io.slave[2].ar.bits.lock <= UInt<1>("h00") - io.slave[2].ar.bits.burst <= UInt<1>("h00") - io.slave[2].ar.bits.size <= UInt<1>("h00") - io.slave[2].ar.bits.len <= UInt<1>("h00") - io.slave[2].ar.bits.addr <= UInt<1>("h00") - io.slave[2].ar.valid <= UInt<1>("h00") - io.slave[2].b.ready <= UInt<1>("h00") - io.slave[2].w.bits.user <= UInt<1>("h00") - io.slave[2].w.bits.strb <= UInt<1>("h00") - io.slave[2].w.bits.last <= UInt<1>("h00") - io.slave[2].w.bits.data <= UInt<1>("h00") - io.slave[2].w.valid <= UInt<1>("h00") - io.slave[2].aw.bits.user <= UInt<1>("h00") - io.slave[2].aw.bits.id <= UInt<1>("h00") - io.slave[2].aw.bits.region <= UInt<1>("h00") - io.slave[2].aw.bits.qos <= UInt<1>("h00") - io.slave[2].aw.bits.prot <= UInt<1>("h00") - io.slave[2].aw.bits.cache <= UInt<1>("h00") - io.slave[2].aw.bits.lock <= UInt<1>("h00") - io.slave[2].aw.bits.burst <= UInt<1>("h00") - io.slave[2].aw.bits.size <= UInt<1>("h00") - io.slave[2].aw.bits.len <= UInt<1>("h00") - io.slave[2].aw.bits.addr <= UInt<1>("h00") - io.slave[2].aw.valid <= UInt<1>("h00") - io.slave[3].r.ready <= UInt<1>("h00") - io.slave[3].ar.bits.user <= UInt<1>("h00") - io.slave[3].ar.bits.id <= UInt<1>("h00") - io.slave[3].ar.bits.region <= UInt<1>("h00") - io.slave[3].ar.bits.qos <= UInt<1>("h00") - io.slave[3].ar.bits.prot <= UInt<1>("h00") - io.slave[3].ar.bits.cache <= UInt<1>("h00") - io.slave[3].ar.bits.lock <= UInt<1>("h00") - io.slave[3].ar.bits.burst <= UInt<1>("h00") - io.slave[3].ar.bits.size <= UInt<1>("h00") - io.slave[3].ar.bits.len <= UInt<1>("h00") - io.slave[3].ar.bits.addr <= UInt<1>("h00") - io.slave[3].ar.valid <= UInt<1>("h00") - io.slave[3].b.ready <= UInt<1>("h00") - io.slave[3].w.bits.user <= UInt<1>("h00") - io.slave[3].w.bits.strb <= UInt<1>("h00") - io.slave[3].w.bits.last <= UInt<1>("h00") - io.slave[3].w.bits.data <= UInt<1>("h00") - io.slave[3].w.valid <= UInt<1>("h00") - io.slave[3].aw.bits.user <= UInt<1>("h00") - io.slave[3].aw.bits.id <= UInt<1>("h00") - io.slave[3].aw.bits.region <= UInt<1>("h00") - io.slave[3].aw.bits.qos <= UInt<1>("h00") - io.slave[3].aw.bits.prot <= UInt<1>("h00") - io.slave[3].aw.bits.cache <= UInt<1>("h00") - io.slave[3].aw.bits.lock <= UInt<1>("h00") - io.slave[3].aw.bits.burst <= UInt<1>("h00") - io.slave[3].aw.bits.size <= UInt<1>("h00") - io.slave[3].aw.bits.len <= UInt<1>("h00") - io.slave[3].aw.bits.addr <= UInt<1>("h00") - io.slave[3].aw.valid <= UInt<1>("h00") - io.master.r.bits.user <= UInt<1>("h00") - io.master.r.bits.id <= UInt<1>("h00") - io.master.r.bits.last <= UInt<1>("h00") - io.master.r.bits.data <= UInt<1>("h00") - io.master.r.bits.resp <= UInt<1>("h00") - io.master.r.valid <= UInt<1>("h00") - io.master.ar.ready <= UInt<1>("h00") - io.master.b.bits.user <= UInt<1>("h00") - io.master.b.bits.id <= UInt<1>("h00") - io.master.b.bits.resp <= UInt<1>("h00") - io.master.b.valid <= UInt<1>("h00") - io.master.w.ready <= UInt<1>("h00") - io.master.aw.ready <= UInt<1>("h00") + io is invalid node T_1437 = geq(io.master.ar.bits.addr, UInt<1>("h00")) node T_1439 = lt(io.master.ar.bits.addr, UInt<31>("h040000000")) node T_1440 = and(T_1437, T_1439) @@ -12461,21 +10119,21 @@ circuit Top : node T_1493 = cat(T_1487[3], T_1487[2]) node T_1494 = cat(T_1487[1], T_1487[0]) node aw_route = cat(T_1493, T_1494) - node T_1499 = bit(ar_route, 0) + node T_1499 = bits(ar_route, 0, 0) node T_1500 = and(io.master.ar.valid, T_1499) io.slave[0].ar.valid <= T_1500 io.slave[0].ar.bits <- io.master.ar.bits - node T_1501 = bit(ar_route, 0) + node T_1501 = bits(ar_route, 0, 0) node T_1502 = and(io.slave[0].ar.ready, T_1501) node T_1503 = or(UInt<1>("h00"), T_1502) - node T_1504 = bit(aw_route, 0) + node T_1504 = bits(aw_route, 0, 0) node T_1505 = and(io.master.aw.valid, T_1504) io.slave[0].aw.valid <= T_1505 io.slave[0].aw.bits <- io.master.aw.bits - node T_1506 = bit(aw_route, 0) + node T_1506 = bits(aw_route, 0, 0) node T_1507 = and(io.slave[0].aw.ready, T_1506) node T_1508 = or(UInt<1>("h00"), T_1507) - reg T_1510 : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1510 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node T_1511 = and(io.slave[0].aw.ready, io.slave[0].aw.valid) when T_1511 : T_1510 <= UInt<1>("h01") @@ -12490,21 +10148,21 @@ circuit Top : io.slave[0].w.bits <- io.master.w.bits node T_1517 = and(io.slave[0].w.ready, T_1510) node T_1518 = or(UInt<1>("h00"), T_1517) - node T_1519 = bit(ar_route, 1) + node T_1519 = bits(ar_route, 1, 1) node T_1520 = and(io.master.ar.valid, T_1519) io.slave[1].ar.valid <= T_1520 io.slave[1].ar.bits <- io.master.ar.bits - node T_1521 = bit(ar_route, 1) + node T_1521 = bits(ar_route, 1, 1) node T_1522 = and(io.slave[1].ar.ready, T_1521) node T_1523 = or(T_1503, T_1522) - node T_1524 = bit(aw_route, 1) + node T_1524 = bits(aw_route, 1, 1) node T_1525 = and(io.master.aw.valid, T_1524) io.slave[1].aw.valid <= T_1525 io.slave[1].aw.bits <- io.master.aw.bits - node T_1526 = bit(aw_route, 1) + node T_1526 = bits(aw_route, 1, 1) node T_1527 = and(io.slave[1].aw.ready, T_1526) node T_1528 = or(T_1508, T_1527) - reg T_1530 : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1530 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node T_1531 = and(io.slave[1].aw.ready, io.slave[1].aw.valid) when T_1531 : T_1530 <= UInt<1>("h01") @@ -12519,21 +10177,21 @@ circuit Top : io.slave[1].w.bits <- io.master.w.bits node T_1537 = and(io.slave[1].w.ready, T_1530) node T_1538 = or(T_1518, T_1537) - node T_1539 = bit(ar_route, 2) + node T_1539 = bits(ar_route, 2, 2) node T_1540 = and(io.master.ar.valid, T_1539) io.slave[2].ar.valid <= T_1540 io.slave[2].ar.bits <- io.master.ar.bits - node T_1541 = bit(ar_route, 2) + node T_1541 = bits(ar_route, 2, 2) node T_1542 = and(io.slave[2].ar.ready, T_1541) node T_1543 = or(T_1523, T_1542) - node T_1544 = bit(aw_route, 2) + node T_1544 = bits(aw_route, 2, 2) node T_1545 = and(io.master.aw.valid, T_1544) io.slave[2].aw.valid <= T_1545 io.slave[2].aw.bits <- io.master.aw.bits - node T_1546 = bit(aw_route, 2) + node T_1546 = bits(aw_route, 2, 2) node T_1547 = and(io.slave[2].aw.ready, T_1546) node T_1548 = or(T_1528, T_1547) - reg T_1550 : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1550 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node T_1551 = and(io.slave[2].aw.ready, io.slave[2].aw.valid) when T_1551 : T_1550 <= UInt<1>("h01") @@ -12548,21 +10206,21 @@ circuit Top : io.slave[2].w.bits <- io.master.w.bits node T_1557 = and(io.slave[2].w.ready, T_1550) node T_1558 = or(T_1538, T_1557) - node T_1559 = bit(ar_route, 3) + node T_1559 = bits(ar_route, 3, 3) node T_1560 = and(io.master.ar.valid, T_1559) io.slave[3].ar.valid <= T_1560 io.slave[3].ar.bits <- io.master.ar.bits - node T_1561 = bit(ar_route, 3) + node T_1561 = bits(ar_route, 3, 3) node T_1562 = and(io.slave[3].ar.ready, T_1561) node ar_ready = or(T_1543, T_1562) - node T_1564 = bit(aw_route, 3) + node T_1564 = bits(aw_route, 3, 3) node T_1565 = and(io.master.aw.valid, T_1564) io.slave[3].aw.valid <= T_1565 io.slave[3].aw.bits <- io.master.aw.bits - node T_1566 = bit(aw_route, 3) + node T_1566 = bits(aw_route, 3, 3) node T_1567 = and(io.slave[3].aw.ready, T_1566) node aw_ready = or(T_1548, T_1567) - reg T_1570 : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1570 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node T_1571 = and(io.slave[3].aw.ready, io.slave[3].aw.valid) when T_1571 : T_1570 <= UInt<1>("h01") @@ -12582,111 +10240,31 @@ circuit Top : node T_1584 = neq(aw_route, UInt<1>("h00")) node w_invalid = eq(T_1584, UInt<1>("h00")) inst err_slave of NastiErrorSlave - err_slave.io.r.ready <= UInt<1>("h00") - err_slave.io.ar.bits.user <= UInt<1>("h00") - err_slave.io.ar.bits.id <= UInt<1>("h00") - err_slave.io.ar.bits.region <= UInt<1>("h00") - err_slave.io.ar.bits.qos <= UInt<1>("h00") - err_slave.io.ar.bits.prot <= UInt<1>("h00") - err_slave.io.ar.bits.cache <= UInt<1>("h00") - err_slave.io.ar.bits.lock <= UInt<1>("h00") - err_slave.io.ar.bits.burst <= UInt<1>("h00") - err_slave.io.ar.bits.size <= UInt<1>("h00") - err_slave.io.ar.bits.len <= UInt<1>("h00") - err_slave.io.ar.bits.addr <= UInt<1>("h00") - err_slave.io.ar.valid <= UInt<1>("h00") - err_slave.io.b.ready <= UInt<1>("h00") - err_slave.io.w.bits.user <= UInt<1>("h00") - err_slave.io.w.bits.strb <= UInt<1>("h00") - err_slave.io.w.bits.last <= UInt<1>("h00") - err_slave.io.w.bits.data <= UInt<1>("h00") - err_slave.io.w.valid <= UInt<1>("h00") - err_slave.io.aw.bits.user <= UInt<1>("h00") - err_slave.io.aw.bits.id <= UInt<1>("h00") - err_slave.io.aw.bits.region <= UInt<1>("h00") - err_slave.io.aw.bits.qos <= UInt<1>("h00") - err_slave.io.aw.bits.prot <= UInt<1>("h00") - err_slave.io.aw.bits.cache <= UInt<1>("h00") - err_slave.io.aw.bits.lock <= UInt<1>("h00") - err_slave.io.aw.bits.burst <= UInt<1>("h00") - err_slave.io.aw.bits.size <= UInt<1>("h00") - err_slave.io.aw.bits.len <= UInt<1>("h00") - err_slave.io.aw.bits.addr <= UInt<1>("h00") - err_slave.io.aw.valid <= UInt<1>("h00") + err_slave.io is invalid err_slave.clk <= clk err_slave.reset <= reset - node T_1619 = and(r_invalid, io.master.ar.valid) - err_slave.io.ar.valid <= T_1619 + node T_1588 = and(r_invalid, io.master.ar.valid) + err_slave.io.ar.valid <= T_1588 err_slave.io.ar.bits <- io.master.ar.bits - node T_1620 = and(w_invalid, io.master.aw.valid) - err_slave.io.aw.valid <= T_1620 + node T_1589 = and(w_invalid, io.master.aw.valid) + err_slave.io.aw.valid <= T_1589 err_slave.io.aw.bits <- io.master.aw.bits err_slave.io.w.valid <= io.master.w.valid err_slave.io.w.bits <- io.master.w.bits - node T_1621 = and(r_invalid, err_slave.io.ar.ready) - node T_1622 = or(ar_ready, T_1621) - io.master.ar.ready <= T_1622 - node T_1623 = and(w_invalid, err_slave.io.aw.ready) - node T_1624 = or(aw_ready, T_1623) - io.master.aw.ready <= T_1624 - node T_1625 = or(w_ready, err_slave.io.w.ready) - io.master.w.ready <= T_1625 + node T_1590 = and(r_invalid, err_slave.io.ar.ready) + node T_1591 = or(ar_ready, T_1590) + io.master.ar.ready <= T_1591 + node T_1592 = and(w_invalid, err_slave.io.aw.ready) + node T_1593 = or(aw_ready, T_1592) + io.master.aw.ready <= T_1593 + node T_1594 = or(w_ready, err_slave.io.w.ready) + io.master.w.ready <= T_1594 inst b_arb of RRArbiter_38 - b_arb.io.out.ready <= UInt<1>("h00") - b_arb.io.in[0].bits.user <= UInt<1>("h00") - b_arb.io.in[0].bits.id <= UInt<1>("h00") - b_arb.io.in[0].bits.resp <= UInt<1>("h00") - b_arb.io.in[0].valid <= UInt<1>("h00") - b_arb.io.in[1].bits.user <= UInt<1>("h00") - b_arb.io.in[1].bits.id <= UInt<1>("h00") - b_arb.io.in[1].bits.resp <= UInt<1>("h00") - b_arb.io.in[1].valid <= UInt<1>("h00") - b_arb.io.in[2].bits.user <= UInt<1>("h00") - b_arb.io.in[2].bits.id <= UInt<1>("h00") - b_arb.io.in[2].bits.resp <= UInt<1>("h00") - b_arb.io.in[2].valid <= UInt<1>("h00") - b_arb.io.in[3].bits.user <= UInt<1>("h00") - b_arb.io.in[3].bits.id <= UInt<1>("h00") - b_arb.io.in[3].bits.resp <= UInt<1>("h00") - b_arb.io.in[3].valid <= UInt<1>("h00") - b_arb.io.in[4].bits.user <= UInt<1>("h00") - b_arb.io.in[4].bits.id <= UInt<1>("h00") - b_arb.io.in[4].bits.resp <= UInt<1>("h00") - b_arb.io.in[4].valid <= UInt<1>("h00") + b_arb.io is invalid b_arb.clk <= clk b_arb.reset <= reset inst r_arb of JunctionsPeekingArbiter - r_arb.io.out.ready <= UInt<1>("h00") - r_arb.io.in[0].bits.user <= UInt<1>("h00") - r_arb.io.in[0].bits.id <= UInt<1>("h00") - r_arb.io.in[0].bits.last <= UInt<1>("h00") - r_arb.io.in[0].bits.data <= UInt<1>("h00") - r_arb.io.in[0].bits.resp <= UInt<1>("h00") - r_arb.io.in[0].valid <= UInt<1>("h00") - r_arb.io.in[1].bits.user <= UInt<1>("h00") - r_arb.io.in[1].bits.id <= UInt<1>("h00") - r_arb.io.in[1].bits.last <= UInt<1>("h00") - r_arb.io.in[1].bits.data <= UInt<1>("h00") - r_arb.io.in[1].bits.resp <= UInt<1>("h00") - r_arb.io.in[1].valid <= UInt<1>("h00") - r_arb.io.in[2].bits.user <= UInt<1>("h00") - r_arb.io.in[2].bits.id <= UInt<1>("h00") - r_arb.io.in[2].bits.last <= UInt<1>("h00") - r_arb.io.in[2].bits.data <= UInt<1>("h00") - r_arb.io.in[2].bits.resp <= UInt<1>("h00") - r_arb.io.in[2].valid <= UInt<1>("h00") - r_arb.io.in[3].bits.user <= UInt<1>("h00") - r_arb.io.in[3].bits.id <= UInt<1>("h00") - r_arb.io.in[3].bits.last <= UInt<1>("h00") - r_arb.io.in[3].bits.data <= UInt<1>("h00") - r_arb.io.in[3].bits.resp <= UInt<1>("h00") - r_arb.io.in[3].valid <= UInt<1>("h00") - r_arb.io.in[4].bits.user <= UInt<1>("h00") - r_arb.io.in[4].bits.id <= UInt<1>("h00") - r_arb.io.in[4].bits.last <= UInt<1>("h00") - r_arb.io.in[4].bits.data <= UInt<1>("h00") - r_arb.io.in[4].bits.resp <= UInt<1>("h00") - r_arb.io.in[4].valid <= UInt<1>("h00") + r_arb.io is invalid r_arb.clk <= clk r_arb.reset <= reset b_arb.io.in[0] <- io.slave[0].b @@ -12707,19 +10285,7 @@ circuit Top : input reset : UInt<1> input io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} - io.r.bits.user <= UInt<1>("h00") - io.r.bits.id <= UInt<1>("h00") - io.r.bits.last <= UInt<1>("h00") - io.r.bits.data <= UInt<1>("h00") - io.r.bits.resp <= UInt<1>("h00") - io.r.valid <= UInt<1>("h00") - io.ar.ready <= UInt<1>("h00") - io.b.bits.user <= UInt<1>("h00") - io.b.bits.id <= UInt<1>("h00") - io.b.bits.resp <= UInt<1>("h00") - io.b.valid <= UInt<1>("h00") - io.w.ready <= UInt<1>("h00") - io.aw.ready <= UInt<1>("h00") + io is invalid node T_322 = and(io.ar.ready, io.ar.valid) when T_322 : node T_324 = eq(reset, UInt<1>("h00")) @@ -12737,227 +10303,78 @@ circuit Top : skip skip inst r_queue of Queue_36 - r_queue.io.deq.ready <= UInt<1>("h00") - r_queue.io.enq.bits.user <= UInt<1>("h00") - r_queue.io.enq.bits.id <= UInt<1>("h00") - r_queue.io.enq.bits.region <= UInt<1>("h00") - r_queue.io.enq.bits.qos <= UInt<1>("h00") - r_queue.io.enq.bits.prot <= UInt<1>("h00") - r_queue.io.enq.bits.cache <= UInt<1>("h00") - r_queue.io.enq.bits.lock <= UInt<1>("h00") - r_queue.io.enq.bits.burst <= UInt<1>("h00") - r_queue.io.enq.bits.size <= UInt<1>("h00") - r_queue.io.enq.bits.len <= UInt<1>("h00") - r_queue.io.enq.bits.addr <= UInt<1>("h00") - r_queue.io.enq.valid <= UInt<1>("h00") + r_queue.io is invalid r_queue.clk <= clk r_queue.reset <= reset r_queue.io.enq <- io.ar - reg responding : UInt<1>, clk, reset, UInt<1>("h00") - reg beats_left : UInt<8>, clk, reset, UInt<8>("h00") - node T_359 = eq(responding, UInt<1>("h00")) - node T_360 = and(T_359, r_queue.io.deq.valid) - when T_360 : + reg responding : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg beats_left : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) + node T_346 = eq(responding, UInt<1>("h00")) + node T_347 = and(T_346, r_queue.io.deq.valid) + when T_347 : responding <= UInt<1>("h01") beats_left <= r_queue.io.deq.bits.len skip - node T_362 = and(r_queue.io.deq.valid, responding) - io.r.valid <= T_362 + node T_349 = and(r_queue.io.deq.valid, responding) + io.r.valid <= T_349 io.r.bits.id <= r_queue.io.deq.bits.id io.r.bits.data <= UInt<1>("h00") io.r.bits.resp <= UInt<2>("h03") - node T_365 = eq(beats_left, UInt<1>("h00")) - io.r.bits.last <= T_365 - node T_366 = and(io.r.ready, io.r.valid) - node T_367 = and(T_366, io.r.bits.last) - r_queue.io.deq.ready <= T_367 - node T_368 = and(io.r.ready, io.r.valid) - when T_368 : - node T_370 = eq(beats_left, UInt<1>("h00")) - when T_370 : + node T_352 = eq(beats_left, UInt<1>("h00")) + io.r.bits.last <= T_352 + node T_353 = and(io.r.ready, io.r.valid) + node T_354 = and(T_353, io.r.bits.last) + r_queue.io.deq.ready <= T_354 + node T_355 = and(io.r.ready, io.r.valid) + when T_355 : + node T_357 = eq(beats_left, UInt<1>("h00")) + when T_357 : responding <= UInt<1>("h00") skip - node T_373 = eq(T_370, UInt<1>("h00")) - when T_373 : - node T_375 = subw(beats_left, UInt<1>("h01")) - beats_left <= T_375 + node T_360 = eq(T_357, UInt<1>("h00")) + when T_360 : + node T_362 = sub(beats_left, UInt<1>("h01")) + node T_363 = tail(T_362, 1) + beats_left <= T_363 skip skip - reg draining : UInt<1>, clk, reset, UInt<1>("h00") + reg draining : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) io.w.ready <= draining - node T_378 = and(io.aw.ready, io.aw.valid) - when T_378 : + node T_366 = and(io.aw.ready, io.aw.valid) + when T_366 : draining <= UInt<1>("h01") skip - node T_380 = and(io.w.ready, io.w.valid) - node T_381 = and(T_380, io.w.bits.last) - when T_381 : + node T_368 = and(io.w.ready, io.w.valid) + node T_369 = and(T_368, io.w.bits.last) + when T_369 : draining <= UInt<1>("h00") skip inst b_queue of Queue_37 - b_queue.io.deq.ready <= UInt<1>("h00") - b_queue.io.enq.bits <= UInt<1>("h00") - b_queue.io.enq.valid <= UInt<1>("h00") + b_queue.io is invalid b_queue.clk <= clk b_queue.reset <= reset - node T_389 = eq(draining, UInt<1>("h00")) - node T_390 = and(io.aw.valid, T_389) - b_queue.io.enq.valid <= T_390 + node T_374 = eq(draining, UInt<1>("h00")) + node T_375 = and(io.aw.valid, T_374) + b_queue.io.enq.valid <= T_375 b_queue.io.enq.bits <= io.aw.bits.id - node T_392 = eq(draining, UInt<1>("h00")) - node T_393 = and(b_queue.io.enq.ready, T_392) - io.aw.ready <= T_393 - node T_395 = eq(draining, UInt<1>("h00")) - node T_396 = and(b_queue.io.deq.valid, T_395) - io.b.valid <= T_396 + node T_377 = eq(draining, UInt<1>("h00")) + node T_378 = and(b_queue.io.enq.ready, T_377) + io.aw.ready <= T_378 + node T_380 = eq(draining, UInt<1>("h00")) + node T_381 = and(b_queue.io.deq.valid, T_380) + io.b.valid <= T_381 io.b.bits.id <= b_queue.io.deq.bits io.b.bits.resp <= UInt<2>("h03") - node T_399 = eq(draining, UInt<1>("h00")) - node T_400 = and(io.b.ready, T_399) - b_queue.io.deq.ready <= T_400 + node T_384 = eq(draining, UInt<1>("h00")) + node T_385 = and(io.b.ready, T_384) + b_queue.io.deq.ready <= T_385 module NastiRouter_39 : input clk : Clock input reset : UInt<1> output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]} - io.slave[0].r.ready <= UInt<1>("h00") - io.slave[0].ar.bits.user <= UInt<1>("h00") - io.slave[0].ar.bits.id <= UInt<1>("h00") - io.slave[0].ar.bits.region <= UInt<1>("h00") - io.slave[0].ar.bits.qos <= UInt<1>("h00") - io.slave[0].ar.bits.prot <= UInt<1>("h00") - io.slave[0].ar.bits.cache <= UInt<1>("h00") - io.slave[0].ar.bits.lock <= UInt<1>("h00") - io.slave[0].ar.bits.burst <= UInt<1>("h00") - io.slave[0].ar.bits.size <= UInt<1>("h00") - io.slave[0].ar.bits.len <= UInt<1>("h00") - io.slave[0].ar.bits.addr <= UInt<1>("h00") - io.slave[0].ar.valid <= UInt<1>("h00") - io.slave[0].b.ready <= UInt<1>("h00") - io.slave[0].w.bits.user <= UInt<1>("h00") - io.slave[0].w.bits.strb <= UInt<1>("h00") - io.slave[0].w.bits.last <= UInt<1>("h00") - io.slave[0].w.bits.data <= UInt<1>("h00") - io.slave[0].w.valid <= UInt<1>("h00") - io.slave[0].aw.bits.user <= UInt<1>("h00") - io.slave[0].aw.bits.id <= UInt<1>("h00") - io.slave[0].aw.bits.region <= UInt<1>("h00") - io.slave[0].aw.bits.qos <= UInt<1>("h00") - io.slave[0].aw.bits.prot <= UInt<1>("h00") - io.slave[0].aw.bits.cache <= UInt<1>("h00") - io.slave[0].aw.bits.lock <= UInt<1>("h00") - io.slave[0].aw.bits.burst <= UInt<1>("h00") - io.slave[0].aw.bits.size <= UInt<1>("h00") - io.slave[0].aw.bits.len <= UInt<1>("h00") - io.slave[0].aw.bits.addr <= UInt<1>("h00") - io.slave[0].aw.valid <= UInt<1>("h00") - io.slave[1].r.ready <= UInt<1>("h00") - io.slave[1].ar.bits.user <= UInt<1>("h00") - io.slave[1].ar.bits.id <= UInt<1>("h00") - io.slave[1].ar.bits.region <= UInt<1>("h00") - io.slave[1].ar.bits.qos <= UInt<1>("h00") - io.slave[1].ar.bits.prot <= UInt<1>("h00") - io.slave[1].ar.bits.cache <= UInt<1>("h00") - io.slave[1].ar.bits.lock <= UInt<1>("h00") - io.slave[1].ar.bits.burst <= UInt<1>("h00") - io.slave[1].ar.bits.size <= UInt<1>("h00") - io.slave[1].ar.bits.len <= UInt<1>("h00") - io.slave[1].ar.bits.addr <= UInt<1>("h00") - io.slave[1].ar.valid <= UInt<1>("h00") - io.slave[1].b.ready <= UInt<1>("h00") - io.slave[1].w.bits.user <= UInt<1>("h00") - io.slave[1].w.bits.strb <= UInt<1>("h00") - io.slave[1].w.bits.last <= UInt<1>("h00") - io.slave[1].w.bits.data <= UInt<1>("h00") - io.slave[1].w.valid <= UInt<1>("h00") - io.slave[1].aw.bits.user <= UInt<1>("h00") - io.slave[1].aw.bits.id <= UInt<1>("h00") - io.slave[1].aw.bits.region <= UInt<1>("h00") - io.slave[1].aw.bits.qos <= UInt<1>("h00") - io.slave[1].aw.bits.prot <= UInt<1>("h00") - io.slave[1].aw.bits.cache <= UInt<1>("h00") - io.slave[1].aw.bits.lock <= UInt<1>("h00") - io.slave[1].aw.bits.burst <= UInt<1>("h00") - io.slave[1].aw.bits.size <= UInt<1>("h00") - io.slave[1].aw.bits.len <= UInt<1>("h00") - io.slave[1].aw.bits.addr <= UInt<1>("h00") - io.slave[1].aw.valid <= UInt<1>("h00") - io.slave[2].r.ready <= UInt<1>("h00") - io.slave[2].ar.bits.user <= UInt<1>("h00") - io.slave[2].ar.bits.id <= UInt<1>("h00") - io.slave[2].ar.bits.region <= UInt<1>("h00") - io.slave[2].ar.bits.qos <= UInt<1>("h00") - io.slave[2].ar.bits.prot <= UInt<1>("h00") - io.slave[2].ar.bits.cache <= UInt<1>("h00") - io.slave[2].ar.bits.lock <= UInt<1>("h00") - io.slave[2].ar.bits.burst <= UInt<1>("h00") - io.slave[2].ar.bits.size <= UInt<1>("h00") - io.slave[2].ar.bits.len <= UInt<1>("h00") - io.slave[2].ar.bits.addr <= UInt<1>("h00") - io.slave[2].ar.valid <= UInt<1>("h00") - io.slave[2].b.ready <= UInt<1>("h00") - io.slave[2].w.bits.user <= UInt<1>("h00") - io.slave[2].w.bits.strb <= UInt<1>("h00") - io.slave[2].w.bits.last <= UInt<1>("h00") - io.slave[2].w.bits.data <= UInt<1>("h00") - io.slave[2].w.valid <= UInt<1>("h00") - io.slave[2].aw.bits.user <= UInt<1>("h00") - io.slave[2].aw.bits.id <= UInt<1>("h00") - io.slave[2].aw.bits.region <= UInt<1>("h00") - io.slave[2].aw.bits.qos <= UInt<1>("h00") - io.slave[2].aw.bits.prot <= UInt<1>("h00") - io.slave[2].aw.bits.cache <= UInt<1>("h00") - io.slave[2].aw.bits.lock <= UInt<1>("h00") - io.slave[2].aw.bits.burst <= UInt<1>("h00") - io.slave[2].aw.bits.size <= UInt<1>("h00") - io.slave[2].aw.bits.len <= UInt<1>("h00") - io.slave[2].aw.bits.addr <= UInt<1>("h00") - io.slave[2].aw.valid <= UInt<1>("h00") - io.slave[3].r.ready <= UInt<1>("h00") - io.slave[3].ar.bits.user <= UInt<1>("h00") - io.slave[3].ar.bits.id <= UInt<1>("h00") - io.slave[3].ar.bits.region <= UInt<1>("h00") - io.slave[3].ar.bits.qos <= UInt<1>("h00") - io.slave[3].ar.bits.prot <= UInt<1>("h00") - io.slave[3].ar.bits.cache <= UInt<1>("h00") - io.slave[3].ar.bits.lock <= UInt<1>("h00") - io.slave[3].ar.bits.burst <= UInt<1>("h00") - io.slave[3].ar.bits.size <= UInt<1>("h00") - io.slave[3].ar.bits.len <= UInt<1>("h00") - io.slave[3].ar.bits.addr <= UInt<1>("h00") - io.slave[3].ar.valid <= UInt<1>("h00") - io.slave[3].b.ready <= UInt<1>("h00") - io.slave[3].w.bits.user <= UInt<1>("h00") - io.slave[3].w.bits.strb <= UInt<1>("h00") - io.slave[3].w.bits.last <= UInt<1>("h00") - io.slave[3].w.bits.data <= UInt<1>("h00") - io.slave[3].w.valid <= UInt<1>("h00") - io.slave[3].aw.bits.user <= UInt<1>("h00") - io.slave[3].aw.bits.id <= UInt<1>("h00") - io.slave[3].aw.bits.region <= UInt<1>("h00") - io.slave[3].aw.bits.qos <= UInt<1>("h00") - io.slave[3].aw.bits.prot <= UInt<1>("h00") - io.slave[3].aw.bits.cache <= UInt<1>("h00") - io.slave[3].aw.bits.lock <= UInt<1>("h00") - io.slave[3].aw.bits.burst <= UInt<1>("h00") - io.slave[3].aw.bits.size <= UInt<1>("h00") - io.slave[3].aw.bits.len <= UInt<1>("h00") - io.slave[3].aw.bits.addr <= UInt<1>("h00") - io.slave[3].aw.valid <= UInt<1>("h00") - io.master.r.bits.user <= UInt<1>("h00") - io.master.r.bits.id <= UInt<1>("h00") - io.master.r.bits.last <= UInt<1>("h00") - io.master.r.bits.data <= UInt<1>("h00") - io.master.r.bits.resp <= UInt<1>("h00") - io.master.r.valid <= UInt<1>("h00") - io.master.ar.ready <= UInt<1>("h00") - io.master.b.bits.user <= UInt<1>("h00") - io.master.b.bits.id <= UInt<1>("h00") - io.master.b.bits.resp <= UInt<1>("h00") - io.master.b.valid <= UInt<1>("h00") - io.master.w.ready <= UInt<1>("h00") - io.master.aw.ready <= UInt<1>("h00") + io is invalid node T_1437 = geq(io.master.ar.bits.addr, UInt<1>("h00")) node T_1439 = lt(io.master.ar.bits.addr, UInt<31>("h040000000")) node T_1440 = and(T_1437, T_1439) @@ -12998,21 +10415,21 @@ circuit Top : node T_1493 = cat(T_1487[3], T_1487[2]) node T_1494 = cat(T_1487[1], T_1487[0]) node aw_route = cat(T_1493, T_1494) - node T_1499 = bit(ar_route, 0) + node T_1499 = bits(ar_route, 0, 0) node T_1500 = and(io.master.ar.valid, T_1499) io.slave[0].ar.valid <= T_1500 io.slave[0].ar.bits <- io.master.ar.bits - node T_1501 = bit(ar_route, 0) + node T_1501 = bits(ar_route, 0, 0) node T_1502 = and(io.slave[0].ar.ready, T_1501) node T_1503 = or(UInt<1>("h00"), T_1502) - node T_1504 = bit(aw_route, 0) + node T_1504 = bits(aw_route, 0, 0) node T_1505 = and(io.master.aw.valid, T_1504) io.slave[0].aw.valid <= T_1505 io.slave[0].aw.bits <- io.master.aw.bits - node T_1506 = bit(aw_route, 0) + node T_1506 = bits(aw_route, 0, 0) node T_1507 = and(io.slave[0].aw.ready, T_1506) node T_1508 = or(UInt<1>("h00"), T_1507) - reg T_1510 : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1510 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node T_1511 = and(io.slave[0].aw.ready, io.slave[0].aw.valid) when T_1511 : T_1510 <= UInt<1>("h01") @@ -13027,21 +10444,21 @@ circuit Top : io.slave[0].w.bits <- io.master.w.bits node T_1517 = and(io.slave[0].w.ready, T_1510) node T_1518 = or(UInt<1>("h00"), T_1517) - node T_1519 = bit(ar_route, 1) + node T_1519 = bits(ar_route, 1, 1) node T_1520 = and(io.master.ar.valid, T_1519) io.slave[1].ar.valid <= T_1520 io.slave[1].ar.bits <- io.master.ar.bits - node T_1521 = bit(ar_route, 1) + node T_1521 = bits(ar_route, 1, 1) node T_1522 = and(io.slave[1].ar.ready, T_1521) node T_1523 = or(T_1503, T_1522) - node T_1524 = bit(aw_route, 1) + node T_1524 = bits(aw_route, 1, 1) node T_1525 = and(io.master.aw.valid, T_1524) io.slave[1].aw.valid <= T_1525 io.slave[1].aw.bits <- io.master.aw.bits - node T_1526 = bit(aw_route, 1) + node T_1526 = bits(aw_route, 1, 1) node T_1527 = and(io.slave[1].aw.ready, T_1526) node T_1528 = or(T_1508, T_1527) - reg T_1530 : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1530 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node T_1531 = and(io.slave[1].aw.ready, io.slave[1].aw.valid) when T_1531 : T_1530 <= UInt<1>("h01") @@ -13056,21 +10473,21 @@ circuit Top : io.slave[1].w.bits <- io.master.w.bits node T_1537 = and(io.slave[1].w.ready, T_1530) node T_1538 = or(T_1518, T_1537) - node T_1539 = bit(ar_route, 2) + node T_1539 = bits(ar_route, 2, 2) node T_1540 = and(io.master.ar.valid, T_1539) io.slave[2].ar.valid <= T_1540 io.slave[2].ar.bits <- io.master.ar.bits - node T_1541 = bit(ar_route, 2) + node T_1541 = bits(ar_route, 2, 2) node T_1542 = and(io.slave[2].ar.ready, T_1541) node T_1543 = or(T_1523, T_1542) - node T_1544 = bit(aw_route, 2) + node T_1544 = bits(aw_route, 2, 2) node T_1545 = and(io.master.aw.valid, T_1544) io.slave[2].aw.valid <= T_1545 io.slave[2].aw.bits <- io.master.aw.bits - node T_1546 = bit(aw_route, 2) + node T_1546 = bits(aw_route, 2, 2) node T_1547 = and(io.slave[2].aw.ready, T_1546) node T_1548 = or(T_1528, T_1547) - reg T_1550 : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1550 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node T_1551 = and(io.slave[2].aw.ready, io.slave[2].aw.valid) when T_1551 : T_1550 <= UInt<1>("h01") @@ -13085,21 +10502,21 @@ circuit Top : io.slave[2].w.bits <- io.master.w.bits node T_1557 = and(io.slave[2].w.ready, T_1550) node T_1558 = or(T_1538, T_1557) - node T_1559 = bit(ar_route, 3) + node T_1559 = bits(ar_route, 3, 3) node T_1560 = and(io.master.ar.valid, T_1559) io.slave[3].ar.valid <= T_1560 io.slave[3].ar.bits <- io.master.ar.bits - node T_1561 = bit(ar_route, 3) + node T_1561 = bits(ar_route, 3, 3) node T_1562 = and(io.slave[3].ar.ready, T_1561) node ar_ready = or(T_1543, T_1562) - node T_1564 = bit(aw_route, 3) + node T_1564 = bits(aw_route, 3, 3) node T_1565 = and(io.master.aw.valid, T_1564) io.slave[3].aw.valid <= T_1565 io.slave[3].aw.bits <- io.master.aw.bits - node T_1566 = bit(aw_route, 3) + node T_1566 = bits(aw_route, 3, 3) node T_1567 = and(io.slave[3].aw.ready, T_1566) node aw_ready = or(T_1548, T_1567) - reg T_1570 : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1570 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node T_1571 = and(io.slave[3].aw.ready, io.slave[3].aw.valid) when T_1571 : T_1570 <= UInt<1>("h01") @@ -13119,111 +10536,31 @@ circuit Top : node T_1584 = neq(aw_route, UInt<1>("h00")) node w_invalid = eq(T_1584, UInt<1>("h00")) inst err_slave of NastiErrorSlave_40 - err_slave.io.r.ready <= UInt<1>("h00") - err_slave.io.ar.bits.user <= UInt<1>("h00") - err_slave.io.ar.bits.id <= UInt<1>("h00") - err_slave.io.ar.bits.region <= UInt<1>("h00") - err_slave.io.ar.bits.qos <= UInt<1>("h00") - err_slave.io.ar.bits.prot <= UInt<1>("h00") - err_slave.io.ar.bits.cache <= UInt<1>("h00") - err_slave.io.ar.bits.lock <= UInt<1>("h00") - err_slave.io.ar.bits.burst <= UInt<1>("h00") - err_slave.io.ar.bits.size <= UInt<1>("h00") - err_slave.io.ar.bits.len <= UInt<1>("h00") - err_slave.io.ar.bits.addr <= UInt<1>("h00") - err_slave.io.ar.valid <= UInt<1>("h00") - err_slave.io.b.ready <= UInt<1>("h00") - err_slave.io.w.bits.user <= UInt<1>("h00") - err_slave.io.w.bits.strb <= UInt<1>("h00") - err_slave.io.w.bits.last <= UInt<1>("h00") - err_slave.io.w.bits.data <= UInt<1>("h00") - err_slave.io.w.valid <= UInt<1>("h00") - err_slave.io.aw.bits.user <= UInt<1>("h00") - err_slave.io.aw.bits.id <= UInt<1>("h00") - err_slave.io.aw.bits.region <= UInt<1>("h00") - err_slave.io.aw.bits.qos <= UInt<1>("h00") - err_slave.io.aw.bits.prot <= UInt<1>("h00") - err_slave.io.aw.bits.cache <= UInt<1>("h00") - err_slave.io.aw.bits.lock <= UInt<1>("h00") - err_slave.io.aw.bits.burst <= UInt<1>("h00") - err_slave.io.aw.bits.size <= UInt<1>("h00") - err_slave.io.aw.bits.len <= UInt<1>("h00") - err_slave.io.aw.bits.addr <= UInt<1>("h00") - err_slave.io.aw.valid <= UInt<1>("h00") + err_slave.io is invalid err_slave.clk <= clk err_slave.reset <= reset - node T_1619 = and(r_invalid, io.master.ar.valid) - err_slave.io.ar.valid <= T_1619 + node T_1588 = and(r_invalid, io.master.ar.valid) + err_slave.io.ar.valid <= T_1588 err_slave.io.ar.bits <- io.master.ar.bits - node T_1620 = and(w_invalid, io.master.aw.valid) - err_slave.io.aw.valid <= T_1620 + node T_1589 = and(w_invalid, io.master.aw.valid) + err_slave.io.aw.valid <= T_1589 err_slave.io.aw.bits <- io.master.aw.bits err_slave.io.w.valid <= io.master.w.valid err_slave.io.w.bits <- io.master.w.bits - node T_1621 = and(r_invalid, err_slave.io.ar.ready) - node T_1622 = or(ar_ready, T_1621) - io.master.ar.ready <= T_1622 - node T_1623 = and(w_invalid, err_slave.io.aw.ready) - node T_1624 = or(aw_ready, T_1623) - io.master.aw.ready <= T_1624 - node T_1625 = or(w_ready, err_slave.io.w.ready) - io.master.w.ready <= T_1625 + node T_1590 = and(r_invalid, err_slave.io.ar.ready) + node T_1591 = or(ar_ready, T_1590) + io.master.ar.ready <= T_1591 + node T_1592 = and(w_invalid, err_slave.io.aw.ready) + node T_1593 = or(aw_ready, T_1592) + io.master.aw.ready <= T_1593 + node T_1594 = or(w_ready, err_slave.io.w.ready) + io.master.w.ready <= T_1594 inst b_arb of RRArbiter_38 - b_arb.io.out.ready <= UInt<1>("h00") - b_arb.io.in[0].bits.user <= UInt<1>("h00") - b_arb.io.in[0].bits.id <= UInt<1>("h00") - b_arb.io.in[0].bits.resp <= UInt<1>("h00") - b_arb.io.in[0].valid <= UInt<1>("h00") - b_arb.io.in[1].bits.user <= UInt<1>("h00") - b_arb.io.in[1].bits.id <= UInt<1>("h00") - b_arb.io.in[1].bits.resp <= UInt<1>("h00") - b_arb.io.in[1].valid <= UInt<1>("h00") - b_arb.io.in[2].bits.user <= UInt<1>("h00") - b_arb.io.in[2].bits.id <= UInt<1>("h00") - b_arb.io.in[2].bits.resp <= UInt<1>("h00") - b_arb.io.in[2].valid <= UInt<1>("h00") - b_arb.io.in[3].bits.user <= UInt<1>("h00") - b_arb.io.in[3].bits.id <= UInt<1>("h00") - b_arb.io.in[3].bits.resp <= UInt<1>("h00") - b_arb.io.in[3].valid <= UInt<1>("h00") - b_arb.io.in[4].bits.user <= UInt<1>("h00") - b_arb.io.in[4].bits.id <= UInt<1>("h00") - b_arb.io.in[4].bits.resp <= UInt<1>("h00") - b_arb.io.in[4].valid <= UInt<1>("h00") + b_arb.io is invalid b_arb.clk <= clk b_arb.reset <= reset inst r_arb of JunctionsPeekingArbiter - r_arb.io.out.ready <= UInt<1>("h00") - r_arb.io.in[0].bits.user <= UInt<1>("h00") - r_arb.io.in[0].bits.id <= UInt<1>("h00") - r_arb.io.in[0].bits.last <= UInt<1>("h00") - r_arb.io.in[0].bits.data <= UInt<1>("h00") - r_arb.io.in[0].bits.resp <= UInt<1>("h00") - r_arb.io.in[0].valid <= UInt<1>("h00") - r_arb.io.in[1].bits.user <= UInt<1>("h00") - r_arb.io.in[1].bits.id <= UInt<1>("h00") - r_arb.io.in[1].bits.last <= UInt<1>("h00") - r_arb.io.in[1].bits.data <= UInt<1>("h00") - r_arb.io.in[1].bits.resp <= UInt<1>("h00") - r_arb.io.in[1].valid <= UInt<1>("h00") - r_arb.io.in[2].bits.user <= UInt<1>("h00") - r_arb.io.in[2].bits.id <= UInt<1>("h00") - r_arb.io.in[2].bits.last <= UInt<1>("h00") - r_arb.io.in[2].bits.data <= UInt<1>("h00") - r_arb.io.in[2].bits.resp <= UInt<1>("h00") - r_arb.io.in[2].valid <= UInt<1>("h00") - r_arb.io.in[3].bits.user <= UInt<1>("h00") - r_arb.io.in[3].bits.id <= UInt<1>("h00") - r_arb.io.in[3].bits.last <= UInt<1>("h00") - r_arb.io.in[3].bits.data <= UInt<1>("h00") - r_arb.io.in[3].bits.resp <= UInt<1>("h00") - r_arb.io.in[3].valid <= UInt<1>("h00") - r_arb.io.in[4].bits.user <= UInt<1>("h00") - r_arb.io.in[4].bits.id <= UInt<1>("h00") - r_arb.io.in[4].bits.last <= UInt<1>("h00") - r_arb.io.in[4].bits.data <= UInt<1>("h00") - r_arb.io.in[4].bits.resp <= UInt<1>("h00") - r_arb.io.in[4].valid <= UInt<1>("h00") + r_arb.io is invalid r_arb.clk <= clk r_arb.reset <= reset b_arb.io.in[0] <- io.slave[0].b @@ -13244,64 +10581,50 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, chosen : UInt<1>} - io.chosen <= UInt<1>("h00") - io.out.bits.user <= UInt<1>("h00") - io.out.bits.id <= UInt<1>("h00") - io.out.bits.region <= UInt<1>("h00") - io.out.bits.qos <= UInt<1>("h00") - io.out.bits.prot <= UInt<1>("h00") - io.out.bits.cache <= UInt<1>("h00") - io.out.bits.lock <= UInt<1>("h00") - io.out.bits.burst <= UInt<1>("h00") - io.out.bits.size <= UInt<1>("h00") - io.out.bits.len <= UInt<1>("h00") - io.out.bits.addr <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") + io is invalid wire T_306 : UInt<1> - T_306 <= UInt<1>("h00") + T_306 is invalid io.out.valid <= io.in[T_306].valid io.out.bits <- io.in[T_306].bits io.chosen <= T_306 io.in[T_306].ready <= UInt<1>("h00") - reg T_392 : UInt<1>, clk, reset, UInt<1>("h00") - node T_393 = gt(UInt<1>("h00"), T_392) - node T_394 = and(io.in[0].valid, T_393) - node T_396 = gt(UInt<1>("h01"), T_392) - node T_397 = and(io.in[1].valid, T_396) - node T_400 = or(UInt<1>("h00"), T_394) - node T_402 = eq(T_400, UInt<1>("h00")) - node T_404 = or(UInt<1>("h00"), T_394) - node T_405 = or(T_404, T_397) - node T_407 = eq(T_405, UInt<1>("h00")) - node T_409 = or(UInt<1>("h00"), T_394) - node T_410 = or(T_409, T_397) - node T_411 = or(T_410, io.in[0].valid) - node T_413 = eq(T_411, UInt<1>("h00")) - node T_415 = gt(UInt<1>("h00"), T_392) - node T_416 = and(UInt<1>("h01"), T_415) - node T_417 = or(T_416, T_407) - node T_419 = gt(UInt<1>("h01"), T_392) - node T_420 = and(T_402, T_419) - node T_421 = or(T_420, T_413) - node T_423 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_424 = mux(UInt<1>("h00"), T_423, T_417) - node T_425 = and(T_424, io.out.ready) - io.in[0].ready <= T_425 - node T_427 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_428 = mux(UInt<1>("h00"), T_427, T_421) - node T_429 = and(T_428, io.out.ready) - io.in[1].ready <= T_429 - node T_432 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_434 = gt(UInt<1>("h01"), T_392) - node T_435 = and(io.in[1].valid, T_434) - node T_437 = mux(T_435, UInt<1>("h01"), T_432) - node T_438 = mux(UInt<1>("h00"), UInt<1>("h01"), T_437) - T_306 <= T_438 - node T_439 = and(io.out.ready, io.out.valid) - when T_439 : - T_392 <= T_306 + reg T_391 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_392 = gt(UInt<1>("h00"), T_391) + node T_393 = and(io.in[0].valid, T_392) + node T_395 = gt(UInt<1>("h01"), T_391) + node T_396 = and(io.in[1].valid, T_395) + node T_399 = or(UInt<1>("h00"), T_393) + node T_401 = eq(T_399, UInt<1>("h00")) + node T_403 = or(UInt<1>("h00"), T_393) + node T_404 = or(T_403, T_396) + node T_406 = eq(T_404, UInt<1>("h00")) + node T_408 = or(UInt<1>("h00"), T_393) + node T_409 = or(T_408, T_396) + node T_410 = or(T_409, io.in[0].valid) + node T_412 = eq(T_410, UInt<1>("h00")) + node T_414 = gt(UInt<1>("h00"), T_391) + node T_415 = and(UInt<1>("h01"), T_414) + node T_416 = or(T_415, T_406) + node T_418 = gt(UInt<1>("h01"), T_391) + node T_419 = and(T_401, T_418) + node T_420 = or(T_419, T_412) + node T_422 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_423 = mux(UInt<1>("h00"), T_422, T_416) + node T_424 = and(T_423, io.out.ready) + io.in[0].ready <= T_424 + node T_426 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_427 = mux(UInt<1>("h00"), T_426, T_420) + node T_428 = and(T_427, io.out.ready) + io.in[1].ready <= T_428 + node T_431 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_433 = gt(UInt<1>("h01"), T_391) + node T_434 = and(io.in[1].valid, T_433) + node T_436 = mux(T_434, UInt<1>("h01"), T_431) + node T_437 = mux(UInt<1>("h00"), UInt<1>("h01"), T_436) + T_306 <= T_437 + node T_438 = and(io.out.ready, io.out.valid) + when T_438 : + T_391 <= T_306 skip module NastiArbiter : @@ -13309,971 +10632,250 @@ circuit Top : input reset : UInt<1> output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} - io.slave.r.ready <= UInt<1>("h00") - io.slave.ar.bits.user <= UInt<1>("h00") - io.slave.ar.bits.id <= UInt<1>("h00") - io.slave.ar.bits.region <= UInt<1>("h00") - io.slave.ar.bits.qos <= UInt<1>("h00") - io.slave.ar.bits.prot <= UInt<1>("h00") - io.slave.ar.bits.cache <= UInt<1>("h00") - io.slave.ar.bits.lock <= UInt<1>("h00") - io.slave.ar.bits.burst <= UInt<1>("h00") - io.slave.ar.bits.size <= UInt<1>("h00") - io.slave.ar.bits.len <= UInt<1>("h00") - io.slave.ar.bits.addr <= UInt<1>("h00") - io.slave.ar.valid <= UInt<1>("h00") - io.slave.b.ready <= UInt<1>("h00") - io.slave.w.bits.user <= UInt<1>("h00") - io.slave.w.bits.strb <= UInt<1>("h00") - io.slave.w.bits.last <= UInt<1>("h00") - io.slave.w.bits.data <= UInt<1>("h00") - io.slave.w.valid <= UInt<1>("h00") - io.slave.aw.bits.user <= UInt<1>("h00") - io.slave.aw.bits.id <= UInt<1>("h00") - io.slave.aw.bits.region <= UInt<1>("h00") - io.slave.aw.bits.qos <= UInt<1>("h00") - io.slave.aw.bits.prot <= UInt<1>("h00") - io.slave.aw.bits.cache <= UInt<1>("h00") - io.slave.aw.bits.lock <= UInt<1>("h00") - io.slave.aw.bits.burst <= UInt<1>("h00") - io.slave.aw.bits.size <= UInt<1>("h00") - io.slave.aw.bits.len <= UInt<1>("h00") - io.slave.aw.bits.addr <= UInt<1>("h00") - io.slave.aw.valid <= UInt<1>("h00") - io.master[0].r.bits.user <= UInt<1>("h00") - io.master[0].r.bits.id <= UInt<1>("h00") - io.master[0].r.bits.last <= UInt<1>("h00") - io.master[0].r.bits.data <= UInt<1>("h00") - io.master[0].r.bits.resp <= UInt<1>("h00") - io.master[0].r.valid <= UInt<1>("h00") - io.master[0].ar.ready <= UInt<1>("h00") - io.master[0].b.bits.user <= UInt<1>("h00") - io.master[0].b.bits.id <= UInt<1>("h00") - io.master[0].b.bits.resp <= UInt<1>("h00") - io.master[0].b.valid <= UInt<1>("h00") - io.master[0].w.ready <= UInt<1>("h00") - io.master[0].aw.ready <= UInt<1>("h00") - io.master[1].r.bits.user <= UInt<1>("h00") - io.master[1].r.bits.id <= UInt<1>("h00") - io.master[1].r.bits.last <= UInt<1>("h00") - io.master[1].r.bits.data <= UInt<1>("h00") - io.master[1].r.bits.resp <= UInt<1>("h00") - io.master[1].r.valid <= UInt<1>("h00") - io.master[1].ar.ready <= UInt<1>("h00") - io.master[1].b.bits.user <= UInt<1>("h00") - io.master[1].b.bits.id <= UInt<1>("h00") - io.master[1].b.bits.resp <= UInt<1>("h00") - io.master[1].b.valid <= UInt<1>("h00") - io.master[1].w.ready <= UInt<1>("h00") - io.master[1].aw.ready <= UInt<1>("h00") + io is invalid inst T_1767 of RRArbiter_45 - T_1767.io.out.ready <= UInt<1>("h00") - T_1767.io.in[0].bits.user <= UInt<1>("h00") - T_1767.io.in[0].bits.id <= UInt<1>("h00") - T_1767.io.in[0].bits.region <= UInt<1>("h00") - T_1767.io.in[0].bits.qos <= UInt<1>("h00") - T_1767.io.in[0].bits.prot <= UInt<1>("h00") - T_1767.io.in[0].bits.cache <= UInt<1>("h00") - T_1767.io.in[0].bits.lock <= UInt<1>("h00") - T_1767.io.in[0].bits.burst <= UInt<1>("h00") - T_1767.io.in[0].bits.size <= UInt<1>("h00") - T_1767.io.in[0].bits.len <= UInt<1>("h00") - T_1767.io.in[0].bits.addr <= UInt<1>("h00") - T_1767.io.in[0].valid <= UInt<1>("h00") - T_1767.io.in[1].bits.user <= UInt<1>("h00") - T_1767.io.in[1].bits.id <= UInt<1>("h00") - T_1767.io.in[1].bits.region <= UInt<1>("h00") - T_1767.io.in[1].bits.qos <= UInt<1>("h00") - T_1767.io.in[1].bits.prot <= UInt<1>("h00") - T_1767.io.in[1].bits.cache <= UInt<1>("h00") - T_1767.io.in[1].bits.lock <= UInt<1>("h00") - T_1767.io.in[1].bits.burst <= UInt<1>("h00") - T_1767.io.in[1].bits.size <= UInt<1>("h00") - T_1767.io.in[1].bits.len <= UInt<1>("h00") - T_1767.io.in[1].bits.addr <= UInt<1>("h00") - T_1767.io.in[1].valid <= UInt<1>("h00") + T_1767.io is invalid T_1767.clk <= clk T_1767.reset <= reset - inst T_1805 of RRArbiter_45 - T_1805.io.out.ready <= UInt<1>("h00") - T_1805.io.in[0].bits.user <= UInt<1>("h00") - T_1805.io.in[0].bits.id <= UInt<1>("h00") - T_1805.io.in[0].bits.region <= UInt<1>("h00") - T_1805.io.in[0].bits.qos <= UInt<1>("h00") - T_1805.io.in[0].bits.prot <= UInt<1>("h00") - T_1805.io.in[0].bits.cache <= UInt<1>("h00") - T_1805.io.in[0].bits.lock <= UInt<1>("h00") - T_1805.io.in[0].bits.burst <= UInt<1>("h00") - T_1805.io.in[0].bits.size <= UInt<1>("h00") - T_1805.io.in[0].bits.len <= UInt<1>("h00") - T_1805.io.in[0].bits.addr <= UInt<1>("h00") - T_1805.io.in[0].valid <= UInt<1>("h00") - T_1805.io.in[1].bits.user <= UInt<1>("h00") - T_1805.io.in[1].bits.id <= UInt<1>("h00") - T_1805.io.in[1].bits.region <= UInt<1>("h00") - T_1805.io.in[1].bits.qos <= UInt<1>("h00") - T_1805.io.in[1].bits.prot <= UInt<1>("h00") - T_1805.io.in[1].bits.cache <= UInt<1>("h00") - T_1805.io.in[1].bits.lock <= UInt<1>("h00") - T_1805.io.in[1].bits.burst <= UInt<1>("h00") - T_1805.io.in[1].bits.size <= UInt<1>("h00") - T_1805.io.in[1].bits.len <= UInt<1>("h00") - T_1805.io.in[1].bits.addr <= UInt<1>("h00") - T_1805.io.in[1].valid <= UInt<1>("h00") - T_1805.clk <= clk - T_1805.reset <= reset - node T_1831 = bits(io.slave.r.bits.id, 0, 0) - node T_1832 = bits(io.slave.b.bits.id, 0, 0) - reg T_1834 : UInt<1>, clk, UInt<1>("h00"), T_1834 - reg T_1836 : UInt<1>, clk, reset, UInt<1>("h01") - node T_1837 = and(T_1805.io.out.ready, T_1805.io.out.valid) - when T_1837 : - T_1834 <= T_1805.io.chosen - T_1836 <= UInt<1>("h00") - skip - node T_1839 = and(io.slave.w.ready, io.slave.w.valid) - node T_1840 = and(T_1839, io.slave.w.bits.last) - when T_1840 : - T_1836 <= UInt<1>("h01") + inst T_1780 of RRArbiter_45 + T_1780.io is invalid + T_1780.clk <= clk + T_1780.reset <= reset + node T_1781 = bits(io.slave.r.bits.id, 0, 0) + node T_1782 = bits(io.slave.b.bits.id, 0, 0) + reg T_1784 : UInt<1>, clk + reg T_1786 : UInt<1>, clk with : (reset => (reset, UInt<1>("h01"))) + node T_1787 = and(T_1780.io.out.ready, T_1780.io.out.valid) + when T_1787 : + T_1784 <= T_1780.io.chosen + T_1786 <= UInt<1>("h00") + skip + node T_1789 = and(io.slave.w.ready, io.slave.w.valid) + node T_1790 = and(T_1789, io.slave.w.bits.last) + when T_1790 : + T_1786 <= UInt<1>("h01") skip T_1767.io.in[0] <- io.master[0].ar - node T_1843 = cat(io.master[0].ar.bits.id, UInt<1>("h00")) - T_1767.io.in[0].bits.id <= T_1843 - T_1805.io.in[0] <- io.master[0].aw - node T_1845 = cat(io.master[0].aw.bits.id, UInt<1>("h00")) - T_1805.io.in[0].bits.id <= T_1845 - node T_1847 = eq(T_1831, UInt<1>("h00")) - node T_1848 = and(io.slave.r.valid, T_1847) - io.master[0].r.valid <= T_1848 + node T_1793 = cat(io.master[0].ar.bits.id, UInt<1>("h00")) + T_1767.io.in[0].bits.id <= T_1793 + T_1780.io.in[0] <- io.master[0].aw + node T_1795 = cat(io.master[0].aw.bits.id, UInt<1>("h00")) + T_1780.io.in[0].bits.id <= T_1795 + node T_1797 = eq(T_1781, UInt<1>("h00")) + node T_1798 = and(io.slave.r.valid, T_1797) + io.master[0].r.valid <= T_1798 io.master[0].r.bits <- io.slave.r.bits - node T_1850 = dshr(io.slave.r.bits.id, UInt<1>("h01")) - io.master[0].r.bits.id <= T_1850 - node T_1852 = eq(T_1832, UInt<1>("h00")) - node T_1853 = and(io.slave.b.valid, T_1852) - io.master[0].b.valid <= T_1853 + node T_1800 = dshr(io.slave.r.bits.id, UInt<1>("h01")) + io.master[0].r.bits.id <= T_1800 + node T_1802 = eq(T_1782, UInt<1>("h00")) + node T_1803 = and(io.slave.b.valid, T_1802) + io.master[0].b.valid <= T_1803 io.master[0].b.bits <- io.slave.b.bits - node T_1855 = dshr(io.slave.b.bits.id, UInt<1>("h01")) - io.master[0].b.bits.id <= T_1855 - node T_1857 = eq(T_1834, UInt<1>("h00")) - node T_1858 = and(io.slave.w.ready, T_1857) - node T_1860 = eq(T_1836, UInt<1>("h00")) - node T_1861 = and(T_1858, T_1860) - io.master[0].w.ready <= T_1861 + node T_1805 = dshr(io.slave.b.bits.id, UInt<1>("h01")) + io.master[0].b.bits.id <= T_1805 + node T_1807 = eq(T_1784, UInt<1>("h00")) + node T_1808 = and(io.slave.w.ready, T_1807) + node T_1810 = eq(T_1786, UInt<1>("h00")) + node T_1811 = and(T_1808, T_1810) + io.master[0].w.ready <= T_1811 T_1767.io.in[1] <- io.master[1].ar - node T_1863 = cat(io.master[1].ar.bits.id, UInt<1>("h01")) - T_1767.io.in[1].bits.id <= T_1863 - T_1805.io.in[1] <- io.master[1].aw - node T_1865 = cat(io.master[1].aw.bits.id, UInt<1>("h01")) - T_1805.io.in[1].bits.id <= T_1865 - node T_1867 = eq(T_1831, UInt<1>("h01")) - node T_1868 = and(io.slave.r.valid, T_1867) - io.master[1].r.valid <= T_1868 + node T_1813 = cat(io.master[1].ar.bits.id, UInt<1>("h01")) + T_1767.io.in[1].bits.id <= T_1813 + T_1780.io.in[1] <- io.master[1].aw + node T_1815 = cat(io.master[1].aw.bits.id, UInt<1>("h01")) + T_1780.io.in[1].bits.id <= T_1815 + node T_1817 = eq(T_1781, UInt<1>("h01")) + node T_1818 = and(io.slave.r.valid, T_1817) + io.master[1].r.valid <= T_1818 io.master[1].r.bits <- io.slave.r.bits - node T_1870 = dshr(io.slave.r.bits.id, UInt<1>("h01")) - io.master[1].r.bits.id <= T_1870 - node T_1872 = eq(T_1832, UInt<1>("h01")) - node T_1873 = and(io.slave.b.valid, T_1872) - io.master[1].b.valid <= T_1873 + node T_1820 = dshr(io.slave.r.bits.id, UInt<1>("h01")) + io.master[1].r.bits.id <= T_1820 + node T_1822 = eq(T_1782, UInt<1>("h01")) + node T_1823 = and(io.slave.b.valid, T_1822) + io.master[1].b.valid <= T_1823 io.master[1].b.bits <- io.slave.b.bits - node T_1875 = dshr(io.slave.b.bits.id, UInt<1>("h01")) - io.master[1].b.bits.id <= T_1875 - node T_1877 = eq(T_1834, UInt<1>("h01")) - node T_1878 = and(io.slave.w.ready, T_1877) - node T_1880 = eq(T_1836, UInt<1>("h00")) - node T_1881 = and(T_1878, T_1880) - io.master[1].w.ready <= T_1881 - io.slave.r.ready <= io.master[T_1831].r.ready - io.slave.b.ready <= io.master[T_1832].b.ready - io.slave.w.bits <- io.master[T_1834].w.bits - node T_2519 = eq(T_1836, UInt<1>("h00")) - node T_2520 = and(io.master[T_1834].w.valid, T_2519) - io.slave.w.valid <= T_2520 + node T_1825 = dshr(io.slave.b.bits.id, UInt<1>("h01")) + io.master[1].b.bits.id <= T_1825 + node T_1827 = eq(T_1784, UInt<1>("h01")) + node T_1828 = and(io.slave.w.ready, T_1827) + node T_1830 = eq(T_1786, UInt<1>("h00")) + node T_1831 = and(T_1828, T_1830) + io.master[1].w.ready <= T_1831 + io.slave.r.ready <= io.master[T_1781].r.ready + io.slave.b.ready <= io.master[T_1782].b.ready + io.slave.w.bits <- io.master[T_1784].w.bits + node T_2469 = eq(T_1786, UInt<1>("h00")) + node T_2470 = and(io.master[T_1784].w.valid, T_2469) + io.slave.w.valid <= T_2470 io.slave.ar <- T_1767.io.out - io.slave.aw.bits <- T_1805.io.out.bits - node T_2521 = and(T_1805.io.out.valid, T_1836) - io.slave.aw.valid <= T_2521 - node T_2522 = and(io.slave.aw.ready, T_1836) - T_1805.io.out.ready <= T_2522 + io.slave.aw.bits <- T_1780.io.out.bits + node T_2471 = and(T_1780.io.out.valid, T_1786) + io.slave.aw.valid <= T_2471 + node T_2472 = and(io.slave.aw.ready, T_1786) + T_1780.io.out.ready <= T_2472 module NastiCrossbar : input clk : Clock input reset : UInt<1> output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]} - io.slaves[0].r.ready <= UInt<1>("h00") - io.slaves[0].ar.bits.user <= UInt<1>("h00") - io.slaves[0].ar.bits.id <= UInt<1>("h00") - io.slaves[0].ar.bits.region <= UInt<1>("h00") - io.slaves[0].ar.bits.qos <= UInt<1>("h00") - io.slaves[0].ar.bits.prot <= UInt<1>("h00") - io.slaves[0].ar.bits.cache <= UInt<1>("h00") - io.slaves[0].ar.bits.lock <= UInt<1>("h00") - io.slaves[0].ar.bits.burst <= UInt<1>("h00") - io.slaves[0].ar.bits.size <= UInt<1>("h00") - io.slaves[0].ar.bits.len <= UInt<1>("h00") - io.slaves[0].ar.bits.addr <= UInt<1>("h00") - io.slaves[0].ar.valid <= UInt<1>("h00") - io.slaves[0].b.ready <= UInt<1>("h00") - io.slaves[0].w.bits.user <= UInt<1>("h00") - io.slaves[0].w.bits.strb <= UInt<1>("h00") - io.slaves[0].w.bits.last <= UInt<1>("h00") - io.slaves[0].w.bits.data <= UInt<1>("h00") - io.slaves[0].w.valid <= UInt<1>("h00") - io.slaves[0].aw.bits.user <= UInt<1>("h00") - io.slaves[0].aw.bits.id <= UInt<1>("h00") - io.slaves[0].aw.bits.region <= UInt<1>("h00") - io.slaves[0].aw.bits.qos <= UInt<1>("h00") - io.slaves[0].aw.bits.prot <= UInt<1>("h00") - io.slaves[0].aw.bits.cache <= UInt<1>("h00") - io.slaves[0].aw.bits.lock <= UInt<1>("h00") - io.slaves[0].aw.bits.burst <= UInt<1>("h00") - io.slaves[0].aw.bits.size <= UInt<1>("h00") - io.slaves[0].aw.bits.len <= UInt<1>("h00") - io.slaves[0].aw.bits.addr <= UInt<1>("h00") - io.slaves[0].aw.valid <= UInt<1>("h00") - io.slaves[1].r.ready <= UInt<1>("h00") - io.slaves[1].ar.bits.user <= UInt<1>("h00") - io.slaves[1].ar.bits.id <= UInt<1>("h00") - io.slaves[1].ar.bits.region <= UInt<1>("h00") - io.slaves[1].ar.bits.qos <= UInt<1>("h00") - io.slaves[1].ar.bits.prot <= UInt<1>("h00") - io.slaves[1].ar.bits.cache <= UInt<1>("h00") - io.slaves[1].ar.bits.lock <= UInt<1>("h00") - io.slaves[1].ar.bits.burst <= UInt<1>("h00") - io.slaves[1].ar.bits.size <= UInt<1>("h00") - io.slaves[1].ar.bits.len <= UInt<1>("h00") - io.slaves[1].ar.bits.addr <= UInt<1>("h00") - io.slaves[1].ar.valid <= UInt<1>("h00") - io.slaves[1].b.ready <= UInt<1>("h00") - io.slaves[1].w.bits.user <= UInt<1>("h00") - io.slaves[1].w.bits.strb <= UInt<1>("h00") - io.slaves[1].w.bits.last <= UInt<1>("h00") - io.slaves[1].w.bits.data <= UInt<1>("h00") - io.slaves[1].w.valid <= UInt<1>("h00") - io.slaves[1].aw.bits.user <= UInt<1>("h00") - io.slaves[1].aw.bits.id <= UInt<1>("h00") - io.slaves[1].aw.bits.region <= UInt<1>("h00") - io.slaves[1].aw.bits.qos <= UInt<1>("h00") - io.slaves[1].aw.bits.prot <= UInt<1>("h00") - io.slaves[1].aw.bits.cache <= UInt<1>("h00") - io.slaves[1].aw.bits.lock <= UInt<1>("h00") - io.slaves[1].aw.bits.burst <= UInt<1>("h00") - io.slaves[1].aw.bits.size <= UInt<1>("h00") - io.slaves[1].aw.bits.len <= UInt<1>("h00") - io.slaves[1].aw.bits.addr <= UInt<1>("h00") - io.slaves[1].aw.valid <= UInt<1>("h00") - io.slaves[2].r.ready <= UInt<1>("h00") - io.slaves[2].ar.bits.user <= UInt<1>("h00") - io.slaves[2].ar.bits.id <= UInt<1>("h00") - io.slaves[2].ar.bits.region <= UInt<1>("h00") - io.slaves[2].ar.bits.qos <= UInt<1>("h00") - io.slaves[2].ar.bits.prot <= UInt<1>("h00") - io.slaves[2].ar.bits.cache <= UInt<1>("h00") - io.slaves[2].ar.bits.lock <= UInt<1>("h00") - io.slaves[2].ar.bits.burst <= UInt<1>("h00") - io.slaves[2].ar.bits.size <= UInt<1>("h00") - io.slaves[2].ar.bits.len <= UInt<1>("h00") - io.slaves[2].ar.bits.addr <= UInt<1>("h00") - io.slaves[2].ar.valid <= UInt<1>("h00") - io.slaves[2].b.ready <= UInt<1>("h00") - io.slaves[2].w.bits.user <= UInt<1>("h00") - io.slaves[2].w.bits.strb <= UInt<1>("h00") - io.slaves[2].w.bits.last <= UInt<1>("h00") - io.slaves[2].w.bits.data <= UInt<1>("h00") - io.slaves[2].w.valid <= UInt<1>("h00") - io.slaves[2].aw.bits.user <= UInt<1>("h00") - io.slaves[2].aw.bits.id <= UInt<1>("h00") - io.slaves[2].aw.bits.region <= UInt<1>("h00") - io.slaves[2].aw.bits.qos <= UInt<1>("h00") - io.slaves[2].aw.bits.prot <= UInt<1>("h00") - io.slaves[2].aw.bits.cache <= UInt<1>("h00") - io.slaves[2].aw.bits.lock <= UInt<1>("h00") - io.slaves[2].aw.bits.burst <= UInt<1>("h00") - io.slaves[2].aw.bits.size <= UInt<1>("h00") - io.slaves[2].aw.bits.len <= UInt<1>("h00") - io.slaves[2].aw.bits.addr <= UInt<1>("h00") - io.slaves[2].aw.valid <= UInt<1>("h00") - io.slaves[3].r.ready <= UInt<1>("h00") - io.slaves[3].ar.bits.user <= UInt<1>("h00") - io.slaves[3].ar.bits.id <= UInt<1>("h00") - io.slaves[3].ar.bits.region <= UInt<1>("h00") - io.slaves[3].ar.bits.qos <= UInt<1>("h00") - io.slaves[3].ar.bits.prot <= UInt<1>("h00") - io.slaves[3].ar.bits.cache <= UInt<1>("h00") - io.slaves[3].ar.bits.lock <= UInt<1>("h00") - io.slaves[3].ar.bits.burst <= UInt<1>("h00") - io.slaves[3].ar.bits.size <= UInt<1>("h00") - io.slaves[3].ar.bits.len <= UInt<1>("h00") - io.slaves[3].ar.bits.addr <= UInt<1>("h00") - io.slaves[3].ar.valid <= UInt<1>("h00") - io.slaves[3].b.ready <= UInt<1>("h00") - io.slaves[3].w.bits.user <= UInt<1>("h00") - io.slaves[3].w.bits.strb <= UInt<1>("h00") - io.slaves[3].w.bits.last <= UInt<1>("h00") - io.slaves[3].w.bits.data <= UInt<1>("h00") - io.slaves[3].w.valid <= UInt<1>("h00") - io.slaves[3].aw.bits.user <= UInt<1>("h00") - io.slaves[3].aw.bits.id <= UInt<1>("h00") - io.slaves[3].aw.bits.region <= UInt<1>("h00") - io.slaves[3].aw.bits.qos <= UInt<1>("h00") - io.slaves[3].aw.bits.prot <= UInt<1>("h00") - io.slaves[3].aw.bits.cache <= UInt<1>("h00") - io.slaves[3].aw.bits.lock <= UInt<1>("h00") - io.slaves[3].aw.bits.burst <= UInt<1>("h00") - io.slaves[3].aw.bits.size <= UInt<1>("h00") - io.slaves[3].aw.bits.len <= UInt<1>("h00") - io.slaves[3].aw.bits.addr <= UInt<1>("h00") - io.slaves[3].aw.valid <= UInt<1>("h00") - io.masters[0].r.bits.user <= UInt<1>("h00") - io.masters[0].r.bits.id <= UInt<1>("h00") - io.masters[0].r.bits.last <= UInt<1>("h00") - io.masters[0].r.bits.data <= UInt<1>("h00") - io.masters[0].r.bits.resp <= UInt<1>("h00") - io.masters[0].r.valid <= UInt<1>("h00") - io.masters[0].ar.ready <= UInt<1>("h00") - io.masters[0].b.bits.user <= UInt<1>("h00") - io.masters[0].b.bits.id <= UInt<1>("h00") - io.masters[0].b.bits.resp <= UInt<1>("h00") - io.masters[0].b.valid <= UInt<1>("h00") - io.masters[0].w.ready <= UInt<1>("h00") - io.masters[0].aw.ready <= UInt<1>("h00") - io.masters[1].r.bits.user <= UInt<1>("h00") - io.masters[1].r.bits.id <= UInt<1>("h00") - io.masters[1].r.bits.last <= UInt<1>("h00") - io.masters[1].r.bits.data <= UInt<1>("h00") - io.masters[1].r.bits.resp <= UInt<1>("h00") - io.masters[1].r.valid <= UInt<1>("h00") - io.masters[1].ar.ready <= UInt<1>("h00") - io.masters[1].b.bits.user <= UInt<1>("h00") - io.masters[1].b.bits.id <= UInt<1>("h00") - io.masters[1].b.bits.resp <= UInt<1>("h00") - io.masters[1].b.valid <= UInt<1>("h00") - io.masters[1].w.ready <= UInt<1>("h00") - io.masters[1].aw.ready <= UInt<1>("h00") + io is invalid inst T_2710 of NastiRouter - T_2710.io.slave[0].r.bits.user <= UInt<1>("h00") - T_2710.io.slave[0].r.bits.id <= UInt<1>("h00") - T_2710.io.slave[0].r.bits.last <= UInt<1>("h00") - T_2710.io.slave[0].r.bits.data <= UInt<1>("h00") - T_2710.io.slave[0].r.bits.resp <= UInt<1>("h00") - T_2710.io.slave[0].r.valid <= UInt<1>("h00") - T_2710.io.slave[0].ar.ready <= UInt<1>("h00") - T_2710.io.slave[0].b.bits.user <= UInt<1>("h00") - T_2710.io.slave[0].b.bits.id <= UInt<1>("h00") - T_2710.io.slave[0].b.bits.resp <= UInt<1>("h00") - T_2710.io.slave[0].b.valid <= UInt<1>("h00") - T_2710.io.slave[0].w.ready <= UInt<1>("h00") - T_2710.io.slave[0].aw.ready <= UInt<1>("h00") - T_2710.io.slave[1].r.bits.user <= UInt<1>("h00") - T_2710.io.slave[1].r.bits.id <= UInt<1>("h00") - T_2710.io.slave[1].r.bits.last <= UInt<1>("h00") - T_2710.io.slave[1].r.bits.data <= UInt<1>("h00") - T_2710.io.slave[1].r.bits.resp <= UInt<1>("h00") - T_2710.io.slave[1].r.valid <= UInt<1>("h00") - T_2710.io.slave[1].ar.ready <= UInt<1>("h00") - T_2710.io.slave[1].b.bits.user <= UInt<1>("h00") - T_2710.io.slave[1].b.bits.id <= UInt<1>("h00") - T_2710.io.slave[1].b.bits.resp <= UInt<1>("h00") - T_2710.io.slave[1].b.valid <= UInt<1>("h00") - T_2710.io.slave[1].w.ready <= UInt<1>("h00") - T_2710.io.slave[1].aw.ready <= UInt<1>("h00") - T_2710.io.slave[2].r.bits.user <= UInt<1>("h00") - T_2710.io.slave[2].r.bits.id <= UInt<1>("h00") - T_2710.io.slave[2].r.bits.last <= UInt<1>("h00") - T_2710.io.slave[2].r.bits.data <= UInt<1>("h00") - T_2710.io.slave[2].r.bits.resp <= UInt<1>("h00") - T_2710.io.slave[2].r.valid <= UInt<1>("h00") - T_2710.io.slave[2].ar.ready <= UInt<1>("h00") - T_2710.io.slave[2].b.bits.user <= UInt<1>("h00") - T_2710.io.slave[2].b.bits.id <= UInt<1>("h00") - T_2710.io.slave[2].b.bits.resp <= UInt<1>("h00") - T_2710.io.slave[2].b.valid <= UInt<1>("h00") - T_2710.io.slave[2].w.ready <= UInt<1>("h00") - T_2710.io.slave[2].aw.ready <= UInt<1>("h00") - T_2710.io.slave[3].r.bits.user <= UInt<1>("h00") - T_2710.io.slave[3].r.bits.id <= UInt<1>("h00") - T_2710.io.slave[3].r.bits.last <= UInt<1>("h00") - T_2710.io.slave[3].r.bits.data <= UInt<1>("h00") - T_2710.io.slave[3].r.bits.resp <= UInt<1>("h00") - T_2710.io.slave[3].r.valid <= UInt<1>("h00") - T_2710.io.slave[3].ar.ready <= UInt<1>("h00") - T_2710.io.slave[3].b.bits.user <= UInt<1>("h00") - T_2710.io.slave[3].b.bits.id <= UInt<1>("h00") - T_2710.io.slave[3].b.bits.resp <= UInt<1>("h00") - T_2710.io.slave[3].b.valid <= UInt<1>("h00") - T_2710.io.slave[3].w.ready <= UInt<1>("h00") - T_2710.io.slave[3].aw.ready <= UInt<1>("h00") - T_2710.io.master.r.ready <= UInt<1>("h00") - T_2710.io.master.ar.bits.user <= UInt<1>("h00") - T_2710.io.master.ar.bits.id <= UInt<1>("h00") - T_2710.io.master.ar.bits.region <= UInt<1>("h00") - T_2710.io.master.ar.bits.qos <= UInt<1>("h00") - T_2710.io.master.ar.bits.prot <= UInt<1>("h00") - T_2710.io.master.ar.bits.cache <= UInt<1>("h00") - T_2710.io.master.ar.bits.lock <= UInt<1>("h00") - T_2710.io.master.ar.bits.burst <= UInt<1>("h00") - T_2710.io.master.ar.bits.size <= UInt<1>("h00") - T_2710.io.master.ar.bits.len <= UInt<1>("h00") - T_2710.io.master.ar.bits.addr <= UInt<1>("h00") - T_2710.io.master.ar.valid <= UInt<1>("h00") - T_2710.io.master.b.ready <= UInt<1>("h00") - T_2710.io.master.w.bits.user <= UInt<1>("h00") - T_2710.io.master.w.bits.strb <= UInt<1>("h00") - T_2710.io.master.w.bits.last <= UInt<1>("h00") - T_2710.io.master.w.bits.data <= UInt<1>("h00") - T_2710.io.master.w.valid <= UInt<1>("h00") - T_2710.io.master.aw.bits.user <= UInt<1>("h00") - T_2710.io.master.aw.bits.id <= UInt<1>("h00") - T_2710.io.master.aw.bits.region <= UInt<1>("h00") - T_2710.io.master.aw.bits.qos <= UInt<1>("h00") - T_2710.io.master.aw.bits.prot <= UInt<1>("h00") - T_2710.io.master.aw.bits.cache <= UInt<1>("h00") - T_2710.io.master.aw.bits.lock <= UInt<1>("h00") - T_2710.io.master.aw.bits.burst <= UInt<1>("h00") - T_2710.io.master.aw.bits.size <= UInt<1>("h00") - T_2710.io.master.aw.bits.len <= UInt<1>("h00") - T_2710.io.master.aw.bits.addr <= UInt<1>("h00") - T_2710.io.master.aw.valid <= UInt<1>("h00") + T_2710.io is invalid T_2710.clk <= clk T_2710.reset <= reset - inst T_2794 of NastiRouter_39 - T_2794.io.slave[0].r.bits.user <= UInt<1>("h00") - T_2794.io.slave[0].r.bits.id <= UInt<1>("h00") - T_2794.io.slave[0].r.bits.last <= UInt<1>("h00") - T_2794.io.slave[0].r.bits.data <= UInt<1>("h00") - T_2794.io.slave[0].r.bits.resp <= UInt<1>("h00") - T_2794.io.slave[0].r.valid <= UInt<1>("h00") - T_2794.io.slave[0].ar.ready <= UInt<1>("h00") - T_2794.io.slave[0].b.bits.user <= UInt<1>("h00") - T_2794.io.slave[0].b.bits.id <= UInt<1>("h00") - T_2794.io.slave[0].b.bits.resp <= UInt<1>("h00") - T_2794.io.slave[0].b.valid <= UInt<1>("h00") - T_2794.io.slave[0].w.ready <= UInt<1>("h00") - T_2794.io.slave[0].aw.ready <= UInt<1>("h00") - T_2794.io.slave[1].r.bits.user <= UInt<1>("h00") - T_2794.io.slave[1].r.bits.id <= UInt<1>("h00") - T_2794.io.slave[1].r.bits.last <= UInt<1>("h00") - T_2794.io.slave[1].r.bits.data <= UInt<1>("h00") - T_2794.io.slave[1].r.bits.resp <= UInt<1>("h00") - T_2794.io.slave[1].r.valid <= UInt<1>("h00") - T_2794.io.slave[1].ar.ready <= UInt<1>("h00") - T_2794.io.slave[1].b.bits.user <= UInt<1>("h00") - T_2794.io.slave[1].b.bits.id <= UInt<1>("h00") - T_2794.io.slave[1].b.bits.resp <= UInt<1>("h00") - T_2794.io.slave[1].b.valid <= UInt<1>("h00") - T_2794.io.slave[1].w.ready <= UInt<1>("h00") - T_2794.io.slave[1].aw.ready <= UInt<1>("h00") - T_2794.io.slave[2].r.bits.user <= UInt<1>("h00") - T_2794.io.slave[2].r.bits.id <= UInt<1>("h00") - T_2794.io.slave[2].r.bits.last <= UInt<1>("h00") - T_2794.io.slave[2].r.bits.data <= UInt<1>("h00") - T_2794.io.slave[2].r.bits.resp <= UInt<1>("h00") - T_2794.io.slave[2].r.valid <= UInt<1>("h00") - T_2794.io.slave[2].ar.ready <= UInt<1>("h00") - T_2794.io.slave[2].b.bits.user <= UInt<1>("h00") - T_2794.io.slave[2].b.bits.id <= UInt<1>("h00") - T_2794.io.slave[2].b.bits.resp <= UInt<1>("h00") - T_2794.io.slave[2].b.valid <= UInt<1>("h00") - T_2794.io.slave[2].w.ready <= UInt<1>("h00") - T_2794.io.slave[2].aw.ready <= UInt<1>("h00") - T_2794.io.slave[3].r.bits.user <= UInt<1>("h00") - T_2794.io.slave[3].r.bits.id <= UInt<1>("h00") - T_2794.io.slave[3].r.bits.last <= UInt<1>("h00") - T_2794.io.slave[3].r.bits.data <= UInt<1>("h00") - T_2794.io.slave[3].r.bits.resp <= UInt<1>("h00") - T_2794.io.slave[3].r.valid <= UInt<1>("h00") - T_2794.io.slave[3].ar.ready <= UInt<1>("h00") - T_2794.io.slave[3].b.bits.user <= UInt<1>("h00") - T_2794.io.slave[3].b.bits.id <= UInt<1>("h00") - T_2794.io.slave[3].b.bits.resp <= UInt<1>("h00") - T_2794.io.slave[3].b.valid <= UInt<1>("h00") - T_2794.io.slave[3].w.ready <= UInt<1>("h00") - T_2794.io.slave[3].aw.ready <= UInt<1>("h00") - T_2794.io.master.r.ready <= UInt<1>("h00") - T_2794.io.master.ar.bits.user <= UInt<1>("h00") - T_2794.io.master.ar.bits.id <= UInt<1>("h00") - T_2794.io.master.ar.bits.region <= UInt<1>("h00") - T_2794.io.master.ar.bits.qos <= UInt<1>("h00") - T_2794.io.master.ar.bits.prot <= UInt<1>("h00") - T_2794.io.master.ar.bits.cache <= UInt<1>("h00") - T_2794.io.master.ar.bits.lock <= UInt<1>("h00") - T_2794.io.master.ar.bits.burst <= UInt<1>("h00") - T_2794.io.master.ar.bits.size <= UInt<1>("h00") - T_2794.io.master.ar.bits.len <= UInt<1>("h00") - T_2794.io.master.ar.bits.addr <= UInt<1>("h00") - T_2794.io.master.ar.valid <= UInt<1>("h00") - T_2794.io.master.b.ready <= UInt<1>("h00") - T_2794.io.master.w.bits.user <= UInt<1>("h00") - T_2794.io.master.w.bits.strb <= UInt<1>("h00") - T_2794.io.master.w.bits.last <= UInt<1>("h00") - T_2794.io.master.w.bits.data <= UInt<1>("h00") - T_2794.io.master.w.valid <= UInt<1>("h00") - T_2794.io.master.aw.bits.user <= UInt<1>("h00") - T_2794.io.master.aw.bits.id <= UInt<1>("h00") - T_2794.io.master.aw.bits.region <= UInt<1>("h00") - T_2794.io.master.aw.bits.qos <= UInt<1>("h00") - T_2794.io.master.aw.bits.prot <= UInt<1>("h00") - T_2794.io.master.aw.bits.cache <= UInt<1>("h00") - T_2794.io.master.aw.bits.lock <= UInt<1>("h00") - T_2794.io.master.aw.bits.burst <= UInt<1>("h00") - T_2794.io.master.aw.bits.size <= UInt<1>("h00") - T_2794.io.master.aw.bits.len <= UInt<1>("h00") - T_2794.io.master.aw.bits.addr <= UInt<1>("h00") - T_2794.io.master.aw.valid <= UInt<1>("h00") - T_2794.clk <= clk - T_2794.reset <= reset - wire T_4312 : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]}[2] - T_4312[0] <- T_2710.io - T_4312[1] <- T_2794.io - inst T_8615 of NastiArbiter - T_8615.io.slave.r.bits.user <= UInt<1>("h00") - T_8615.io.slave.r.bits.id <= UInt<1>("h00") - T_8615.io.slave.r.bits.last <= UInt<1>("h00") - T_8615.io.slave.r.bits.data <= UInt<1>("h00") - T_8615.io.slave.r.bits.resp <= UInt<1>("h00") - T_8615.io.slave.r.valid <= UInt<1>("h00") - T_8615.io.slave.ar.ready <= UInt<1>("h00") - T_8615.io.slave.b.bits.user <= UInt<1>("h00") - T_8615.io.slave.b.bits.id <= UInt<1>("h00") - T_8615.io.slave.b.bits.resp <= UInt<1>("h00") - T_8615.io.slave.b.valid <= UInt<1>("h00") - T_8615.io.slave.w.ready <= UInt<1>("h00") - T_8615.io.slave.aw.ready <= UInt<1>("h00") - T_8615.io.master[0].r.ready <= UInt<1>("h00") - T_8615.io.master[0].ar.bits.user <= UInt<1>("h00") - T_8615.io.master[0].ar.bits.id <= UInt<1>("h00") - T_8615.io.master[0].ar.bits.region <= UInt<1>("h00") - T_8615.io.master[0].ar.bits.qos <= UInt<1>("h00") - T_8615.io.master[0].ar.bits.prot <= UInt<1>("h00") - T_8615.io.master[0].ar.bits.cache <= UInt<1>("h00") - T_8615.io.master[0].ar.bits.lock <= UInt<1>("h00") - T_8615.io.master[0].ar.bits.burst <= UInt<1>("h00") - T_8615.io.master[0].ar.bits.size <= UInt<1>("h00") - T_8615.io.master[0].ar.bits.len <= UInt<1>("h00") - T_8615.io.master[0].ar.bits.addr <= UInt<1>("h00") - T_8615.io.master[0].ar.valid <= UInt<1>("h00") - T_8615.io.master[0].b.ready <= UInt<1>("h00") - T_8615.io.master[0].w.bits.user <= UInt<1>("h00") - T_8615.io.master[0].w.bits.strb <= UInt<1>("h00") - T_8615.io.master[0].w.bits.last <= UInt<1>("h00") - T_8615.io.master[0].w.bits.data <= UInt<1>("h00") - T_8615.io.master[0].w.valid <= UInt<1>("h00") - T_8615.io.master[0].aw.bits.user <= UInt<1>("h00") - T_8615.io.master[0].aw.bits.id <= UInt<1>("h00") - T_8615.io.master[0].aw.bits.region <= UInt<1>("h00") - T_8615.io.master[0].aw.bits.qos <= UInt<1>("h00") - T_8615.io.master[0].aw.bits.prot <= UInt<1>("h00") - T_8615.io.master[0].aw.bits.cache <= UInt<1>("h00") - T_8615.io.master[0].aw.bits.lock <= UInt<1>("h00") - T_8615.io.master[0].aw.bits.burst <= UInt<1>("h00") - T_8615.io.master[0].aw.bits.size <= UInt<1>("h00") - T_8615.io.master[0].aw.bits.len <= UInt<1>("h00") - T_8615.io.master[0].aw.bits.addr <= UInt<1>("h00") - T_8615.io.master[0].aw.valid <= UInt<1>("h00") - T_8615.io.master[1].r.ready <= UInt<1>("h00") - T_8615.io.master[1].ar.bits.user <= UInt<1>("h00") - T_8615.io.master[1].ar.bits.id <= UInt<1>("h00") - T_8615.io.master[1].ar.bits.region <= UInt<1>("h00") - T_8615.io.master[1].ar.bits.qos <= UInt<1>("h00") - T_8615.io.master[1].ar.bits.prot <= UInt<1>("h00") - T_8615.io.master[1].ar.bits.cache <= UInt<1>("h00") - T_8615.io.master[1].ar.bits.lock <= UInt<1>("h00") - T_8615.io.master[1].ar.bits.burst <= UInt<1>("h00") - T_8615.io.master[1].ar.bits.size <= UInt<1>("h00") - T_8615.io.master[1].ar.bits.len <= UInt<1>("h00") - T_8615.io.master[1].ar.bits.addr <= UInt<1>("h00") - T_8615.io.master[1].ar.valid <= UInt<1>("h00") - T_8615.io.master[1].b.ready <= UInt<1>("h00") - T_8615.io.master[1].w.bits.user <= UInt<1>("h00") - T_8615.io.master[1].w.bits.strb <= UInt<1>("h00") - T_8615.io.master[1].w.bits.last <= UInt<1>("h00") - T_8615.io.master[1].w.bits.data <= UInt<1>("h00") - T_8615.io.master[1].w.valid <= UInt<1>("h00") - T_8615.io.master[1].aw.bits.user <= UInt<1>("h00") - T_8615.io.master[1].aw.bits.id <= UInt<1>("h00") - T_8615.io.master[1].aw.bits.region <= UInt<1>("h00") - T_8615.io.master[1].aw.bits.qos <= UInt<1>("h00") - T_8615.io.master[1].aw.bits.prot <= UInt<1>("h00") - T_8615.io.master[1].aw.bits.cache <= UInt<1>("h00") - T_8615.io.master[1].aw.bits.lock <= UInt<1>("h00") - T_8615.io.master[1].aw.bits.burst <= UInt<1>("h00") - T_8615.io.master[1].aw.bits.size <= UInt<1>("h00") - T_8615.io.master[1].aw.bits.len <= UInt<1>("h00") - T_8615.io.master[1].aw.bits.addr <= UInt<1>("h00") - T_8615.io.master[1].aw.valid <= UInt<1>("h00") - T_8615.clk <= clk - T_8615.reset <= reset - inst T_8691 of NastiArbiter - T_8691.io.slave.r.bits.user <= UInt<1>("h00") - T_8691.io.slave.r.bits.id <= UInt<1>("h00") - T_8691.io.slave.r.bits.last <= UInt<1>("h00") - T_8691.io.slave.r.bits.data <= UInt<1>("h00") - T_8691.io.slave.r.bits.resp <= UInt<1>("h00") - T_8691.io.slave.r.valid <= UInt<1>("h00") - T_8691.io.slave.ar.ready <= UInt<1>("h00") - T_8691.io.slave.b.bits.user <= UInt<1>("h00") - T_8691.io.slave.b.bits.id <= UInt<1>("h00") - T_8691.io.slave.b.bits.resp <= UInt<1>("h00") - T_8691.io.slave.b.valid <= UInt<1>("h00") - T_8691.io.slave.w.ready <= UInt<1>("h00") - T_8691.io.slave.aw.ready <= UInt<1>("h00") - T_8691.io.master[0].r.ready <= UInt<1>("h00") - T_8691.io.master[0].ar.bits.user <= UInt<1>("h00") - T_8691.io.master[0].ar.bits.id <= UInt<1>("h00") - T_8691.io.master[0].ar.bits.region <= UInt<1>("h00") - T_8691.io.master[0].ar.bits.qos <= UInt<1>("h00") - T_8691.io.master[0].ar.bits.prot <= UInt<1>("h00") - T_8691.io.master[0].ar.bits.cache <= UInt<1>("h00") - T_8691.io.master[0].ar.bits.lock <= UInt<1>("h00") - T_8691.io.master[0].ar.bits.burst <= UInt<1>("h00") - T_8691.io.master[0].ar.bits.size <= UInt<1>("h00") - T_8691.io.master[0].ar.bits.len <= UInt<1>("h00") - T_8691.io.master[0].ar.bits.addr <= UInt<1>("h00") - T_8691.io.master[0].ar.valid <= UInt<1>("h00") - T_8691.io.master[0].b.ready <= UInt<1>("h00") - T_8691.io.master[0].w.bits.user <= UInt<1>("h00") - T_8691.io.master[0].w.bits.strb <= UInt<1>("h00") - T_8691.io.master[0].w.bits.last <= UInt<1>("h00") - T_8691.io.master[0].w.bits.data <= UInt<1>("h00") - T_8691.io.master[0].w.valid <= UInt<1>("h00") - T_8691.io.master[0].aw.bits.user <= UInt<1>("h00") - T_8691.io.master[0].aw.bits.id <= UInt<1>("h00") - T_8691.io.master[0].aw.bits.region <= UInt<1>("h00") - T_8691.io.master[0].aw.bits.qos <= UInt<1>("h00") - T_8691.io.master[0].aw.bits.prot <= UInt<1>("h00") - T_8691.io.master[0].aw.bits.cache <= UInt<1>("h00") - T_8691.io.master[0].aw.bits.lock <= UInt<1>("h00") - T_8691.io.master[0].aw.bits.burst <= UInt<1>("h00") - T_8691.io.master[0].aw.bits.size <= UInt<1>("h00") - T_8691.io.master[0].aw.bits.len <= UInt<1>("h00") - T_8691.io.master[0].aw.bits.addr <= UInt<1>("h00") - T_8691.io.master[0].aw.valid <= UInt<1>("h00") - T_8691.io.master[1].r.ready <= UInt<1>("h00") - T_8691.io.master[1].ar.bits.user <= UInt<1>("h00") - T_8691.io.master[1].ar.bits.id <= UInt<1>("h00") - T_8691.io.master[1].ar.bits.region <= UInt<1>("h00") - T_8691.io.master[1].ar.bits.qos <= UInt<1>("h00") - T_8691.io.master[1].ar.bits.prot <= UInt<1>("h00") - T_8691.io.master[1].ar.bits.cache <= UInt<1>("h00") - T_8691.io.master[1].ar.bits.lock <= UInt<1>("h00") - T_8691.io.master[1].ar.bits.burst <= UInt<1>("h00") - T_8691.io.master[1].ar.bits.size <= UInt<1>("h00") - T_8691.io.master[1].ar.bits.len <= UInt<1>("h00") - T_8691.io.master[1].ar.bits.addr <= UInt<1>("h00") - T_8691.io.master[1].ar.valid <= UInt<1>("h00") - T_8691.io.master[1].b.ready <= UInt<1>("h00") - T_8691.io.master[1].w.bits.user <= UInt<1>("h00") - T_8691.io.master[1].w.bits.strb <= UInt<1>("h00") - T_8691.io.master[1].w.bits.last <= UInt<1>("h00") - T_8691.io.master[1].w.bits.data <= UInt<1>("h00") - T_8691.io.master[1].w.valid <= UInt<1>("h00") - T_8691.io.master[1].aw.bits.user <= UInt<1>("h00") - T_8691.io.master[1].aw.bits.id <= UInt<1>("h00") - T_8691.io.master[1].aw.bits.region <= UInt<1>("h00") - T_8691.io.master[1].aw.bits.qos <= UInt<1>("h00") - T_8691.io.master[1].aw.bits.prot <= UInt<1>("h00") - T_8691.io.master[1].aw.bits.cache <= UInt<1>("h00") - T_8691.io.master[1].aw.bits.lock <= UInt<1>("h00") - T_8691.io.master[1].aw.bits.burst <= UInt<1>("h00") - T_8691.io.master[1].aw.bits.size <= UInt<1>("h00") - T_8691.io.master[1].aw.bits.len <= UInt<1>("h00") - T_8691.io.master[1].aw.bits.addr <= UInt<1>("h00") - T_8691.io.master[1].aw.valid <= UInt<1>("h00") - T_8691.clk <= clk - T_8691.reset <= reset - inst T_8767 of NastiArbiter - T_8767.io.slave.r.bits.user <= UInt<1>("h00") - T_8767.io.slave.r.bits.id <= UInt<1>("h00") - T_8767.io.slave.r.bits.last <= UInt<1>("h00") - T_8767.io.slave.r.bits.data <= UInt<1>("h00") - T_8767.io.slave.r.bits.resp <= UInt<1>("h00") - T_8767.io.slave.r.valid <= UInt<1>("h00") - T_8767.io.slave.ar.ready <= UInt<1>("h00") - T_8767.io.slave.b.bits.user <= UInt<1>("h00") - T_8767.io.slave.b.bits.id <= UInt<1>("h00") - T_8767.io.slave.b.bits.resp <= UInt<1>("h00") - T_8767.io.slave.b.valid <= UInt<1>("h00") - T_8767.io.slave.w.ready <= UInt<1>("h00") - T_8767.io.slave.aw.ready <= UInt<1>("h00") - T_8767.io.master[0].r.ready <= UInt<1>("h00") - T_8767.io.master[0].ar.bits.user <= UInt<1>("h00") - T_8767.io.master[0].ar.bits.id <= UInt<1>("h00") - T_8767.io.master[0].ar.bits.region <= UInt<1>("h00") - T_8767.io.master[0].ar.bits.qos <= UInt<1>("h00") - T_8767.io.master[0].ar.bits.prot <= UInt<1>("h00") - T_8767.io.master[0].ar.bits.cache <= UInt<1>("h00") - T_8767.io.master[0].ar.bits.lock <= UInt<1>("h00") - T_8767.io.master[0].ar.bits.burst <= UInt<1>("h00") - T_8767.io.master[0].ar.bits.size <= UInt<1>("h00") - T_8767.io.master[0].ar.bits.len <= UInt<1>("h00") - T_8767.io.master[0].ar.bits.addr <= UInt<1>("h00") - T_8767.io.master[0].ar.valid <= UInt<1>("h00") - T_8767.io.master[0].b.ready <= UInt<1>("h00") - T_8767.io.master[0].w.bits.user <= UInt<1>("h00") - T_8767.io.master[0].w.bits.strb <= UInt<1>("h00") - T_8767.io.master[0].w.bits.last <= UInt<1>("h00") - T_8767.io.master[0].w.bits.data <= UInt<1>("h00") - T_8767.io.master[0].w.valid <= UInt<1>("h00") - T_8767.io.master[0].aw.bits.user <= UInt<1>("h00") - T_8767.io.master[0].aw.bits.id <= UInt<1>("h00") - T_8767.io.master[0].aw.bits.region <= UInt<1>("h00") - T_8767.io.master[0].aw.bits.qos <= UInt<1>("h00") - T_8767.io.master[0].aw.bits.prot <= UInt<1>("h00") - T_8767.io.master[0].aw.bits.cache <= UInt<1>("h00") - T_8767.io.master[0].aw.bits.lock <= UInt<1>("h00") - T_8767.io.master[0].aw.bits.burst <= UInt<1>("h00") - T_8767.io.master[0].aw.bits.size <= UInt<1>("h00") - T_8767.io.master[0].aw.bits.len <= UInt<1>("h00") - T_8767.io.master[0].aw.bits.addr <= UInt<1>("h00") - T_8767.io.master[0].aw.valid <= UInt<1>("h00") - T_8767.io.master[1].r.ready <= UInt<1>("h00") - T_8767.io.master[1].ar.bits.user <= UInt<1>("h00") - T_8767.io.master[1].ar.bits.id <= UInt<1>("h00") - T_8767.io.master[1].ar.bits.region <= UInt<1>("h00") - T_8767.io.master[1].ar.bits.qos <= UInt<1>("h00") - T_8767.io.master[1].ar.bits.prot <= UInt<1>("h00") - T_8767.io.master[1].ar.bits.cache <= UInt<1>("h00") - T_8767.io.master[1].ar.bits.lock <= UInt<1>("h00") - T_8767.io.master[1].ar.bits.burst <= UInt<1>("h00") - T_8767.io.master[1].ar.bits.size <= UInt<1>("h00") - T_8767.io.master[1].ar.bits.len <= UInt<1>("h00") - T_8767.io.master[1].ar.bits.addr <= UInt<1>("h00") - T_8767.io.master[1].ar.valid <= UInt<1>("h00") - T_8767.io.master[1].b.ready <= UInt<1>("h00") - T_8767.io.master[1].w.bits.user <= UInt<1>("h00") - T_8767.io.master[1].w.bits.strb <= UInt<1>("h00") - T_8767.io.master[1].w.bits.last <= UInt<1>("h00") - T_8767.io.master[1].w.bits.data <= UInt<1>("h00") - T_8767.io.master[1].w.valid <= UInt<1>("h00") - T_8767.io.master[1].aw.bits.user <= UInt<1>("h00") - T_8767.io.master[1].aw.bits.id <= UInt<1>("h00") - T_8767.io.master[1].aw.bits.region <= UInt<1>("h00") - T_8767.io.master[1].aw.bits.qos <= UInt<1>("h00") - T_8767.io.master[1].aw.bits.prot <= UInt<1>("h00") - T_8767.io.master[1].aw.bits.cache <= UInt<1>("h00") - T_8767.io.master[1].aw.bits.lock <= UInt<1>("h00") - T_8767.io.master[1].aw.bits.burst <= UInt<1>("h00") - T_8767.io.master[1].aw.bits.size <= UInt<1>("h00") - T_8767.io.master[1].aw.bits.len <= UInt<1>("h00") - T_8767.io.master[1].aw.bits.addr <= UInt<1>("h00") - T_8767.io.master[1].aw.valid <= UInt<1>("h00") - T_8767.clk <= clk - T_8767.reset <= reset - inst T_8843 of NastiArbiter - T_8843.io.slave.r.bits.user <= UInt<1>("h00") - T_8843.io.slave.r.bits.id <= UInt<1>("h00") - T_8843.io.slave.r.bits.last <= UInt<1>("h00") - T_8843.io.slave.r.bits.data <= UInt<1>("h00") - T_8843.io.slave.r.bits.resp <= UInt<1>("h00") - T_8843.io.slave.r.valid <= UInt<1>("h00") - T_8843.io.slave.ar.ready <= UInt<1>("h00") - T_8843.io.slave.b.bits.user <= UInt<1>("h00") - T_8843.io.slave.b.bits.id <= UInt<1>("h00") - T_8843.io.slave.b.bits.resp <= UInt<1>("h00") - T_8843.io.slave.b.valid <= UInt<1>("h00") - T_8843.io.slave.w.ready <= UInt<1>("h00") - T_8843.io.slave.aw.ready <= UInt<1>("h00") - T_8843.io.master[0].r.ready <= UInt<1>("h00") - T_8843.io.master[0].ar.bits.user <= UInt<1>("h00") - T_8843.io.master[0].ar.bits.id <= UInt<1>("h00") - T_8843.io.master[0].ar.bits.region <= UInt<1>("h00") - T_8843.io.master[0].ar.bits.qos <= UInt<1>("h00") - T_8843.io.master[0].ar.bits.prot <= UInt<1>("h00") - T_8843.io.master[0].ar.bits.cache <= UInt<1>("h00") - T_8843.io.master[0].ar.bits.lock <= UInt<1>("h00") - T_8843.io.master[0].ar.bits.burst <= UInt<1>("h00") - T_8843.io.master[0].ar.bits.size <= UInt<1>("h00") - T_8843.io.master[0].ar.bits.len <= UInt<1>("h00") - T_8843.io.master[0].ar.bits.addr <= UInt<1>("h00") - T_8843.io.master[0].ar.valid <= UInt<1>("h00") - T_8843.io.master[0].b.ready <= UInt<1>("h00") - T_8843.io.master[0].w.bits.user <= UInt<1>("h00") - T_8843.io.master[0].w.bits.strb <= UInt<1>("h00") - T_8843.io.master[0].w.bits.last <= UInt<1>("h00") - T_8843.io.master[0].w.bits.data <= UInt<1>("h00") - T_8843.io.master[0].w.valid <= UInt<1>("h00") - T_8843.io.master[0].aw.bits.user <= UInt<1>("h00") - T_8843.io.master[0].aw.bits.id <= UInt<1>("h00") - T_8843.io.master[0].aw.bits.region <= UInt<1>("h00") - T_8843.io.master[0].aw.bits.qos <= UInt<1>("h00") - T_8843.io.master[0].aw.bits.prot <= UInt<1>("h00") - T_8843.io.master[0].aw.bits.cache <= UInt<1>("h00") - T_8843.io.master[0].aw.bits.lock <= UInt<1>("h00") - T_8843.io.master[0].aw.bits.burst <= UInt<1>("h00") - T_8843.io.master[0].aw.bits.size <= UInt<1>("h00") - T_8843.io.master[0].aw.bits.len <= UInt<1>("h00") - T_8843.io.master[0].aw.bits.addr <= UInt<1>("h00") - T_8843.io.master[0].aw.valid <= UInt<1>("h00") - T_8843.io.master[1].r.ready <= UInt<1>("h00") - T_8843.io.master[1].ar.bits.user <= UInt<1>("h00") - T_8843.io.master[1].ar.bits.id <= UInt<1>("h00") - T_8843.io.master[1].ar.bits.region <= UInt<1>("h00") - T_8843.io.master[1].ar.bits.qos <= UInt<1>("h00") - T_8843.io.master[1].ar.bits.prot <= UInt<1>("h00") - T_8843.io.master[1].ar.bits.cache <= UInt<1>("h00") - T_8843.io.master[1].ar.bits.lock <= UInt<1>("h00") - T_8843.io.master[1].ar.bits.burst <= UInt<1>("h00") - T_8843.io.master[1].ar.bits.size <= UInt<1>("h00") - T_8843.io.master[1].ar.bits.len <= UInt<1>("h00") - T_8843.io.master[1].ar.bits.addr <= UInt<1>("h00") - T_8843.io.master[1].ar.valid <= UInt<1>("h00") - T_8843.io.master[1].b.ready <= UInt<1>("h00") - T_8843.io.master[1].w.bits.user <= UInt<1>("h00") - T_8843.io.master[1].w.bits.strb <= UInt<1>("h00") - T_8843.io.master[1].w.bits.last <= UInt<1>("h00") - T_8843.io.master[1].w.bits.data <= UInt<1>("h00") - T_8843.io.master[1].w.valid <= UInt<1>("h00") - T_8843.io.master[1].aw.bits.user <= UInt<1>("h00") - T_8843.io.master[1].aw.bits.id <= UInt<1>("h00") - T_8843.io.master[1].aw.bits.region <= UInt<1>("h00") - T_8843.io.master[1].aw.bits.qos <= UInt<1>("h00") - T_8843.io.master[1].aw.bits.prot <= UInt<1>("h00") - T_8843.io.master[1].aw.bits.cache <= UInt<1>("h00") - T_8843.io.master[1].aw.bits.lock <= UInt<1>("h00") - T_8843.io.master[1].aw.bits.burst <= UInt<1>("h00") - T_8843.io.master[1].aw.bits.size <= UInt<1>("h00") - T_8843.io.master[1].aw.bits.len <= UInt<1>("h00") - T_8843.io.master[1].aw.bits.addr <= UInt<1>("h00") - T_8843.io.master[1].aw.valid <= UInt<1>("h00") - T_8843.clk <= clk - T_8843.reset <= reset - wire T_10672 : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}}[4] - T_10672[0] <- T_8615.io - T_10672[1] <- T_8691.io - T_10672[2] <- T_8767.io - T_10672[3] <- T_8843.io - T_4312[0].master <- io.masters[0] - T_4312[1].master <- io.masters[1] - wire T_19597 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] - T_19597[0] <- T_4312[0].slave[0] - T_19597[1] <- T_4312[1].slave[0] - T_10672[0].master <- T_19597 - io.slaves[0] <- T_10672[0].slave - wire T_20234 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] - T_20234[0] <- T_4312[0].slave[1] - T_20234[1] <- T_4312[1].slave[1] - T_10672[1].master <- T_20234 - io.slaves[1] <- T_10672[1].slave - wire T_20871 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] - T_20871[0] <- T_4312[0].slave[2] - T_20871[1] <- T_4312[1].slave[2] - T_10672[2].master <- T_20871 - io.slaves[2] <- T_10672[2].slave - wire T_21508 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] - T_21508[0] <- T_4312[0].slave[3] - T_21508[1] <- T_4312[1].slave[3] - T_10672[3].master <- T_21508 - io.slaves[3] <- T_10672[3].slave + inst T_2711 of NastiRouter_39 + T_2711.io is invalid + T_2711.clk <= clk + T_2711.reset <= reset + wire T_4146 : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[4]}[2] + T_4146[0] <- T_2710.io + T_4146[1] <- T_2711.io + inst T_8449 of NastiArbiter + T_8449.io is invalid + T_8449.clk <= clk + T_8449.reset <= reset + inst T_8450 of NastiArbiter + T_8450.io is invalid + T_8450.clk <= clk + T_8450.reset <= reset + inst T_8451 of NastiArbiter + T_8451.io is invalid + T_8451.clk <= clk + T_8451.reset <= reset + inst T_8452 of NastiArbiter + T_8452.io is invalid + T_8452.clk <= clk + T_8452.reset <= reset + wire T_10206 : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}}[4] + T_10206[0] <- T_8449.io + T_10206[1] <- T_8450.io + T_10206[2] <- T_8451.io + T_10206[3] <- T_8452.io + T_4146[0].master <- io.masters[0] + T_4146[1].master <- io.masters[1] + wire T_19131 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] + T_19131[0] <- T_4146[0].slave[0] + T_19131[1] <- T_4146[1].slave[0] + T_10206[0].master <= T_19131 + io.slaves[0] <- T_10206[0].slave + wire T_19768 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] + T_19768[0] <- T_4146[0].slave[1] + T_19768[1] <- T_4146[1].slave[1] + T_10206[1].master <= T_19768 + io.slaves[1] <- T_10206[1].slave + wire T_20405 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] + T_20405[0] <- T_4146[0].slave[2] + T_20405[1] <- T_4146[1].slave[2] + T_10206[2].master <= T_20405 + io.slaves[2] <- T_10206[2].slave + wire T_21042 : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2] + T_21042[0] <- T_4146[0].slave[3] + T_21042[1] <- T_4146[1].slave[3] + T_10206[3].master <= T_21042 + io.slaves[3] <- T_10206[3].slave module RRArbiter_62 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, chosen : UInt<2>} - io.chosen <= UInt<1>("h00") - io.out.bits.user <= UInt<1>("h00") - io.out.bits.id <= UInt<1>("h00") - io.out.bits.resp <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") - io.in[2].ready <= UInt<1>("h00") - io.in[3].ready <= UInt<1>("h00") + io is invalid wire T_174 : UInt<2> - T_174 <= UInt<1>("h00") + T_174 is invalid io.out.valid <= io.in[T_174].valid io.out.bits <- io.in[T_174].bits io.chosen <= T_174 io.in[T_174].ready <= UInt<1>("h00") - reg T_212 : UInt<2>, clk, reset, UInt<2>("h00") - node T_213 = gt(UInt<1>("h00"), T_212) - node T_214 = and(io.in[0].valid, T_213) - node T_216 = gt(UInt<1>("h01"), T_212) - node T_217 = and(io.in[1].valid, T_216) - node T_219 = gt(UInt<2>("h02"), T_212) - node T_220 = and(io.in[2].valid, T_219) - node T_222 = gt(UInt<2>("h03"), T_212) - node T_223 = and(io.in[3].valid, T_222) - node T_226 = or(UInt<1>("h00"), T_214) - node T_228 = eq(T_226, UInt<1>("h00")) - node T_230 = or(UInt<1>("h00"), T_214) - node T_231 = or(T_230, T_217) - node T_233 = eq(T_231, UInt<1>("h00")) - node T_235 = or(UInt<1>("h00"), T_214) - node T_236 = or(T_235, T_217) - node T_237 = or(T_236, T_220) - node T_239 = eq(T_237, UInt<1>("h00")) - node T_241 = or(UInt<1>("h00"), T_214) - node T_242 = or(T_241, T_217) - node T_243 = or(T_242, T_220) - node T_244 = or(T_243, T_223) - node T_246 = eq(T_244, UInt<1>("h00")) - node T_248 = or(UInt<1>("h00"), T_214) - node T_249 = or(T_248, T_217) - node T_250 = or(T_249, T_220) - node T_251 = or(T_250, T_223) - node T_252 = or(T_251, io.in[0].valid) - node T_254 = eq(T_252, UInt<1>("h00")) - node T_256 = or(UInt<1>("h00"), T_214) - node T_257 = or(T_256, T_217) - node T_258 = or(T_257, T_220) - node T_259 = or(T_258, T_223) - node T_260 = or(T_259, io.in[0].valid) - node T_261 = or(T_260, io.in[1].valid) - node T_263 = eq(T_261, UInt<1>("h00")) - node T_265 = or(UInt<1>("h00"), T_214) - node T_266 = or(T_265, T_217) - node T_267 = or(T_266, T_220) - node T_268 = or(T_267, T_223) - node T_269 = or(T_268, io.in[0].valid) - node T_270 = or(T_269, io.in[1].valid) - node T_271 = or(T_270, io.in[2].valid) - node T_273 = eq(T_271, UInt<1>("h00")) - node T_275 = gt(UInt<1>("h00"), T_212) - node T_276 = and(UInt<1>("h01"), T_275) - node T_277 = or(T_276, T_246) - node T_279 = gt(UInt<1>("h01"), T_212) - node T_280 = and(T_228, T_279) - node T_281 = or(T_280, T_254) - node T_283 = gt(UInt<2>("h02"), T_212) - node T_284 = and(T_233, T_283) - node T_285 = or(T_284, T_263) - node T_287 = gt(UInt<2>("h03"), T_212) - node T_288 = and(T_239, T_287) - node T_289 = or(T_288, T_273) - node T_291 = eq(UInt<2>("h03"), UInt<1>("h00")) - node T_292 = mux(UInt<1>("h00"), T_291, T_277) - node T_293 = and(T_292, io.out.ready) - io.in[0].ready <= T_293 - node T_295 = eq(UInt<2>("h03"), UInt<1>("h01")) - node T_296 = mux(UInt<1>("h00"), T_295, T_281) - node T_297 = and(T_296, io.out.ready) - io.in[1].ready <= T_297 - node T_299 = eq(UInt<2>("h03"), UInt<2>("h02")) - node T_300 = mux(UInt<1>("h00"), T_299, T_285) - node T_301 = and(T_300, io.out.ready) - io.in[2].ready <= T_301 - node T_303 = eq(UInt<2>("h03"), UInt<2>("h03")) - node T_304 = mux(UInt<1>("h00"), T_303, T_289) - node T_305 = and(T_304, io.out.ready) - io.in[3].ready <= T_305 - node T_308 = mux(io.in[2].valid, UInt<2>("h02"), UInt<2>("h03")) - node T_310 = mux(io.in[1].valid, UInt<1>("h01"), T_308) - node T_312 = mux(io.in[0].valid, UInt<1>("h00"), T_310) - node T_314 = gt(UInt<2>("h03"), T_212) - node T_315 = and(io.in[3].valid, T_314) - node T_317 = mux(T_315, UInt<2>("h03"), T_312) - node T_319 = gt(UInt<2>("h02"), T_212) - node T_320 = and(io.in[2].valid, T_319) - node T_322 = mux(T_320, UInt<2>("h02"), T_317) - node T_324 = gt(UInt<1>("h01"), T_212) - node T_325 = and(io.in[1].valid, T_324) - node T_327 = mux(T_325, UInt<1>("h01"), T_322) - node T_328 = mux(UInt<1>("h00"), UInt<2>("h03"), T_327) - T_174 <= T_328 - node T_329 = and(io.out.ready, io.out.valid) - when T_329 : - T_212 <= T_174 + reg T_211 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + node T_212 = gt(UInt<1>("h00"), T_211) + node T_213 = and(io.in[0].valid, T_212) + node T_215 = gt(UInt<1>("h01"), T_211) + node T_216 = and(io.in[1].valid, T_215) + node T_218 = gt(UInt<2>("h02"), T_211) + node T_219 = and(io.in[2].valid, T_218) + node T_221 = gt(UInt<2>("h03"), T_211) + node T_222 = and(io.in[3].valid, T_221) + node T_225 = or(UInt<1>("h00"), T_213) + node T_227 = eq(T_225, UInt<1>("h00")) + node T_229 = or(UInt<1>("h00"), T_213) + node T_230 = or(T_229, T_216) + node T_232 = eq(T_230, UInt<1>("h00")) + node T_234 = or(UInt<1>("h00"), T_213) + node T_235 = or(T_234, T_216) + node T_236 = or(T_235, T_219) + node T_238 = eq(T_236, UInt<1>("h00")) + node T_240 = or(UInt<1>("h00"), T_213) + node T_241 = or(T_240, T_216) + node T_242 = or(T_241, T_219) + node T_243 = or(T_242, T_222) + node T_245 = eq(T_243, UInt<1>("h00")) + node T_247 = or(UInt<1>("h00"), T_213) + node T_248 = or(T_247, T_216) + node T_249 = or(T_248, T_219) + node T_250 = or(T_249, T_222) + node T_251 = or(T_250, io.in[0].valid) + node T_253 = eq(T_251, UInt<1>("h00")) + node T_255 = or(UInt<1>("h00"), T_213) + node T_256 = or(T_255, T_216) + node T_257 = or(T_256, T_219) + node T_258 = or(T_257, T_222) + node T_259 = or(T_258, io.in[0].valid) + node T_260 = or(T_259, io.in[1].valid) + node T_262 = eq(T_260, UInt<1>("h00")) + node T_264 = or(UInt<1>("h00"), T_213) + node T_265 = or(T_264, T_216) + node T_266 = or(T_265, T_219) + node T_267 = or(T_266, T_222) + node T_268 = or(T_267, io.in[0].valid) + node T_269 = or(T_268, io.in[1].valid) + node T_270 = or(T_269, io.in[2].valid) + node T_272 = eq(T_270, UInt<1>("h00")) + node T_274 = gt(UInt<1>("h00"), T_211) + node T_275 = and(UInt<1>("h01"), T_274) + node T_276 = or(T_275, T_245) + node T_278 = gt(UInt<1>("h01"), T_211) + node T_279 = and(T_227, T_278) + node T_280 = or(T_279, T_253) + node T_282 = gt(UInt<2>("h02"), T_211) + node T_283 = and(T_232, T_282) + node T_284 = or(T_283, T_262) + node T_286 = gt(UInt<2>("h03"), T_211) + node T_287 = and(T_238, T_286) + node T_288 = or(T_287, T_272) + node T_290 = eq(UInt<2>("h03"), UInt<1>("h00")) + node T_291 = mux(UInt<1>("h00"), T_290, T_276) + node T_292 = and(T_291, io.out.ready) + io.in[0].ready <= T_292 + node T_294 = eq(UInt<2>("h03"), UInt<1>("h01")) + node T_295 = mux(UInt<1>("h00"), T_294, T_280) + node T_296 = and(T_295, io.out.ready) + io.in[1].ready <= T_296 + node T_298 = eq(UInt<2>("h03"), UInt<2>("h02")) + node T_299 = mux(UInt<1>("h00"), T_298, T_284) + node T_300 = and(T_299, io.out.ready) + io.in[2].ready <= T_300 + node T_302 = eq(UInt<2>("h03"), UInt<2>("h03")) + node T_303 = mux(UInt<1>("h00"), T_302, T_288) + node T_304 = and(T_303, io.out.ready) + io.in[3].ready <= T_304 + node T_307 = mux(io.in[2].valid, UInt<2>("h02"), UInt<2>("h03")) + node T_309 = mux(io.in[1].valid, UInt<1>("h01"), T_307) + node T_311 = mux(io.in[0].valid, UInt<1>("h00"), T_309) + node T_313 = gt(UInt<2>("h03"), T_211) + node T_314 = and(io.in[3].valid, T_313) + node T_316 = mux(T_314, UInt<2>("h03"), T_311) + node T_318 = gt(UInt<2>("h02"), T_211) + node T_319 = and(io.in[2].valid, T_318) + node T_321 = mux(T_319, UInt<2>("h02"), T_316) + node T_323 = gt(UInt<1>("h01"), T_211) + node T_324 = and(io.in[1].valid, T_323) + node T_326 = mux(T_324, UInt<1>("h01"), T_321) + node T_327 = mux(UInt<1>("h00"), UInt<2>("h03"), T_326) + T_174 <= T_327 + node T_328 = and(io.out.ready, io.out.valid) + when T_328 : + T_211 <= T_174 skip module JunctionsPeekingArbiter_63 : @@ -14281,96 +10883,105 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} - io.out.bits.user <= UInt<1>("h00") - io.out.bits.id <= UInt<1>("h00") - io.out.bits.last <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.bits.resp <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") - io.in[2].ready <= UInt<1>("h00") - io.in[3].ready <= UInt<1>("h00") - reg T_243 : UInt<2>, clk, reset, UInt<2>("h00") - reg T_245 : UInt<1>, clk, reset, UInt<1>("h00") + io is invalid + reg T_243 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + reg T_245 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) wire T_247 : UInt<1>[4] T_247[0] <= io.in[0].valid T_247[1] <= io.in[1].valid T_247[2] <= io.in[2].valid T_247[3] <= io.in[3].valid - node T_254 = addw(T_243, UInt<1>("h01")) - node T_256 = lt(T_254, UInt<3>("h04")) - node T_258 = addw(UInt<1>("h00"), T_254) - node T_261 = subw(T_254, UInt<3>("h04")) - node T_263 = mux(T_256, T_247[T_258], T_247[T_261]) - node T_265 = lt(T_254, UInt<2>("h03")) - node T_267 = addw(UInt<1>("h01"), T_254) - node T_270 = subw(T_254, UInt<2>("h03")) - node T_272 = mux(T_265, T_247[T_267], T_247[T_270]) - node T_274 = lt(T_254, UInt<2>("h02")) - node T_276 = addw(UInt<2>("h02"), T_254) - node T_279 = subw(T_254, UInt<2>("h02")) - node T_281 = mux(T_274, T_247[T_276], T_247[T_279]) - node T_283 = lt(T_254, UInt<1>("h01")) - node T_285 = addw(UInt<2>("h03"), T_254) - node T_288 = subw(T_254, UInt<1>("h01")) - node T_290 = mux(T_283, T_247[T_285], T_247[T_288]) - wire T_292 : UInt<1>[4] - T_292[0] <= T_263 - T_292[1] <= T_272 - T_292[2] <= T_281 - T_292[3] <= T_290 - wire T_303 : UInt<2>[4] - T_303[0] <= UInt<1>("h00") - T_303[1] <= UInt<1>("h01") - T_303[2] <= UInt<2>("h02") - T_303[3] <= UInt<2>("h03") - node T_310 = addw(T_243, UInt<1>("h01")) - node T_312 = lt(T_310, UInt<3>("h04")) - node T_314 = addw(UInt<1>("h00"), T_310) - node T_317 = subw(T_310, UInt<3>("h04")) - node T_319 = mux(T_312, T_303[T_314], T_303[T_317]) - node T_321 = lt(T_310, UInt<2>("h03")) - node T_323 = addw(UInt<1>("h01"), T_310) - node T_326 = subw(T_310, UInt<2>("h03")) - node T_328 = mux(T_321, T_303[T_323], T_303[T_326]) - node T_330 = lt(T_310, UInt<2>("h02")) - node T_332 = addw(UInt<2>("h02"), T_310) - node T_335 = subw(T_310, UInt<2>("h02")) - node T_337 = mux(T_330, T_303[T_332], T_303[T_335]) - node T_339 = lt(T_310, UInt<1>("h01")) - node T_341 = addw(UInt<2>("h03"), T_310) - node T_344 = subw(T_310, UInt<1>("h01")) - node T_346 = mux(T_339, T_303[T_341], T_303[T_344]) - wire T_348 : UInt<2>[4] - T_348[0] <= T_319 - T_348[1] <= T_328 - T_348[2] <= T_337 - T_348[3] <= T_346 - node T_354 = mux(T_292[2], T_348[2], T_348[3]) - node T_355 = mux(T_292[1], T_348[1], T_354) - node T_356 = mux(T_292[0], T_348[0], T_355) - node T_357 = mux(T_245, T_243, T_356) - node T_359 = eq(T_357, UInt<1>("h00")) - node T_360 = and(io.out.ready, T_359) - io.in[0].ready <= T_360 - node T_362 = eq(T_357, UInt<1>("h01")) - node T_363 = and(io.out.ready, T_362) - io.in[1].ready <= T_363 - node T_365 = eq(T_357, UInt<2>("h02")) - node T_366 = and(io.out.ready, T_365) - io.in[2].ready <= T_366 - node T_368 = eq(T_357, UInt<2>("h03")) - node T_369 = and(io.out.ready, T_368) - io.in[3].ready <= T_369 - io.out.valid <= io.in[T_357].valid - io.out.bits <- io.in[T_357].bits - node T_400 = and(io.out.ready, io.out.valid) - when T_400 : - node T_402 = eq(T_245, UInt<1>("h00")) - node T_404 = and(T_402, UInt<1>("h01")) - when T_404 : - T_243 <= T_356 + node T_254 = add(T_243, UInt<1>("h01")) + node T_255 = tail(T_254, 1) + node T_257 = lt(T_255, UInt<3>("h04")) + node T_259 = add(UInt<1>("h00"), T_255) + node T_260 = tail(T_259, 1) + node T_263 = sub(T_255, UInt<3>("h04")) + node T_264 = tail(T_263, 1) + node T_266 = mux(T_257, T_247[T_260], T_247[T_264]) + node T_268 = lt(T_255, UInt<2>("h03")) + node T_270 = add(UInt<1>("h01"), T_255) + node T_271 = tail(T_270, 1) + node T_274 = sub(T_255, UInt<2>("h03")) + node T_275 = tail(T_274, 1) + node T_277 = mux(T_268, T_247[T_271], T_247[T_275]) + node T_279 = lt(T_255, UInt<2>("h02")) + node T_281 = add(UInt<2>("h02"), T_255) + node T_282 = tail(T_281, 1) + node T_285 = sub(T_255, UInt<2>("h02")) + node T_286 = tail(T_285, 1) + node T_288 = mux(T_279, T_247[T_282], T_247[T_286]) + node T_290 = lt(T_255, UInt<1>("h01")) + node T_292 = add(UInt<2>("h03"), T_255) + node T_293 = tail(T_292, 1) + node T_296 = sub(T_255, UInt<1>("h01")) + node T_297 = tail(T_296, 1) + node T_299 = mux(T_290, T_247[T_293], T_247[T_297]) + wire T_301 : UInt<1>[4] + T_301[0] <= T_266 + T_301[1] <= T_277 + T_301[2] <= T_288 + T_301[3] <= T_299 + wire T_312 : UInt<2>[4] + T_312[0] <= UInt<1>("h00") + T_312[1] <= UInt<1>("h01") + T_312[2] <= UInt<2>("h02") + T_312[3] <= UInt<2>("h03") + node T_319 = add(T_243, UInt<1>("h01")) + node T_320 = tail(T_319, 1) + node T_322 = lt(T_320, UInt<3>("h04")) + node T_324 = add(UInt<1>("h00"), T_320) + node T_325 = tail(T_324, 1) + node T_328 = sub(T_320, UInt<3>("h04")) + node T_329 = tail(T_328, 1) + node T_331 = mux(T_322, T_312[T_325], T_312[T_329]) + node T_333 = lt(T_320, UInt<2>("h03")) + node T_335 = add(UInt<1>("h01"), T_320) + node T_336 = tail(T_335, 1) + node T_339 = sub(T_320, UInt<2>("h03")) + node T_340 = tail(T_339, 1) + node T_342 = mux(T_333, T_312[T_336], T_312[T_340]) + node T_344 = lt(T_320, UInt<2>("h02")) + node T_346 = add(UInt<2>("h02"), T_320) + node T_347 = tail(T_346, 1) + node T_350 = sub(T_320, UInt<2>("h02")) + node T_351 = tail(T_350, 1) + node T_353 = mux(T_344, T_312[T_347], T_312[T_351]) + node T_355 = lt(T_320, UInt<1>("h01")) + node T_357 = add(UInt<2>("h03"), T_320) + node T_358 = tail(T_357, 1) + node T_361 = sub(T_320, UInt<1>("h01")) + node T_362 = tail(T_361, 1) + node T_364 = mux(T_355, T_312[T_358], T_312[T_362]) + wire T_366 : UInt<2>[4] + T_366[0] <= T_331 + T_366[1] <= T_342 + T_366[2] <= T_353 + T_366[3] <= T_364 + node T_372 = mux(T_301[2], T_366[2], T_366[3]) + node T_373 = mux(T_301[1], T_366[1], T_372) + node T_374 = mux(T_301[0], T_366[0], T_373) + node T_375 = mux(T_245, T_243, T_374) + node T_377 = eq(T_375, UInt<1>("h00")) + node T_378 = and(io.out.ready, T_377) + io.in[0].ready <= T_378 + node T_380 = eq(T_375, UInt<1>("h01")) + node T_381 = and(io.out.ready, T_380) + io.in[1].ready <= T_381 + node T_383 = eq(T_375, UInt<2>("h02")) + node T_384 = and(io.out.ready, T_383) + io.in[2].ready <= T_384 + node T_386 = eq(T_375, UInt<2>("h03")) + node T_387 = and(io.out.ready, T_386) + io.in[3].ready <= T_387 + io.out.valid <= io.in[T_375].valid + io.out.bits <- io.in[T_375].bits + node T_418 = and(io.out.ready, io.out.valid) + when T_418 : + node T_420 = eq(T_245, UInt<1>("h00")) + node T_422 = and(T_420, UInt<1>("h01")) + when T_422 : + T_243 <= T_374 T_245 <= UInt<1>("h01") skip when io.out.bits.last : @@ -14383,112 +10994,7 @@ circuit Top : input reset : UInt<1> output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[3]} - io.slave[0].r.ready <= UInt<1>("h00") - io.slave[0].ar.bits.user <= UInt<1>("h00") - io.slave[0].ar.bits.id <= UInt<1>("h00") - io.slave[0].ar.bits.region <= UInt<1>("h00") - io.slave[0].ar.bits.qos <= UInt<1>("h00") - io.slave[0].ar.bits.prot <= UInt<1>("h00") - io.slave[0].ar.bits.cache <= UInt<1>("h00") - io.slave[0].ar.bits.lock <= UInt<1>("h00") - io.slave[0].ar.bits.burst <= UInt<1>("h00") - io.slave[0].ar.bits.size <= UInt<1>("h00") - io.slave[0].ar.bits.len <= UInt<1>("h00") - io.slave[0].ar.bits.addr <= UInt<1>("h00") - io.slave[0].ar.valid <= UInt<1>("h00") - io.slave[0].b.ready <= UInt<1>("h00") - io.slave[0].w.bits.user <= UInt<1>("h00") - io.slave[0].w.bits.strb <= UInt<1>("h00") - io.slave[0].w.bits.last <= UInt<1>("h00") - io.slave[0].w.bits.data <= UInt<1>("h00") - io.slave[0].w.valid <= UInt<1>("h00") - io.slave[0].aw.bits.user <= UInt<1>("h00") - io.slave[0].aw.bits.id <= UInt<1>("h00") - io.slave[0].aw.bits.region <= UInt<1>("h00") - io.slave[0].aw.bits.qos <= UInt<1>("h00") - io.slave[0].aw.bits.prot <= UInt<1>("h00") - io.slave[0].aw.bits.cache <= UInt<1>("h00") - io.slave[0].aw.bits.lock <= UInt<1>("h00") - io.slave[0].aw.bits.burst <= UInt<1>("h00") - io.slave[0].aw.bits.size <= UInt<1>("h00") - io.slave[0].aw.bits.len <= UInt<1>("h00") - io.slave[0].aw.bits.addr <= UInt<1>("h00") - io.slave[0].aw.valid <= UInt<1>("h00") - io.slave[1].r.ready <= UInt<1>("h00") - io.slave[1].ar.bits.user <= UInt<1>("h00") - io.slave[1].ar.bits.id <= UInt<1>("h00") - io.slave[1].ar.bits.region <= UInt<1>("h00") - io.slave[1].ar.bits.qos <= UInt<1>("h00") - io.slave[1].ar.bits.prot <= UInt<1>("h00") - io.slave[1].ar.bits.cache <= UInt<1>("h00") - io.slave[1].ar.bits.lock <= UInt<1>("h00") - io.slave[1].ar.bits.burst <= UInt<1>("h00") - io.slave[1].ar.bits.size <= UInt<1>("h00") - io.slave[1].ar.bits.len <= UInt<1>("h00") - io.slave[1].ar.bits.addr <= UInt<1>("h00") - io.slave[1].ar.valid <= UInt<1>("h00") - io.slave[1].b.ready <= UInt<1>("h00") - io.slave[1].w.bits.user <= UInt<1>("h00") - io.slave[1].w.bits.strb <= UInt<1>("h00") - io.slave[1].w.bits.last <= UInt<1>("h00") - io.slave[1].w.bits.data <= UInt<1>("h00") - io.slave[1].w.valid <= UInt<1>("h00") - io.slave[1].aw.bits.user <= UInt<1>("h00") - io.slave[1].aw.bits.id <= UInt<1>("h00") - io.slave[1].aw.bits.region <= UInt<1>("h00") - io.slave[1].aw.bits.qos <= UInt<1>("h00") - io.slave[1].aw.bits.prot <= UInt<1>("h00") - io.slave[1].aw.bits.cache <= UInt<1>("h00") - io.slave[1].aw.bits.lock <= UInt<1>("h00") - io.slave[1].aw.bits.burst <= UInt<1>("h00") - io.slave[1].aw.bits.size <= UInt<1>("h00") - io.slave[1].aw.bits.len <= UInt<1>("h00") - io.slave[1].aw.bits.addr <= UInt<1>("h00") - io.slave[1].aw.valid <= UInt<1>("h00") - io.slave[2].r.ready <= UInt<1>("h00") - io.slave[2].ar.bits.user <= UInt<1>("h00") - io.slave[2].ar.bits.id <= UInt<1>("h00") - io.slave[2].ar.bits.region <= UInt<1>("h00") - io.slave[2].ar.bits.qos <= UInt<1>("h00") - io.slave[2].ar.bits.prot <= UInt<1>("h00") - io.slave[2].ar.bits.cache <= UInt<1>("h00") - io.slave[2].ar.bits.lock <= UInt<1>("h00") - io.slave[2].ar.bits.burst <= UInt<1>("h00") - io.slave[2].ar.bits.size <= UInt<1>("h00") - io.slave[2].ar.bits.len <= UInt<1>("h00") - io.slave[2].ar.bits.addr <= UInt<1>("h00") - io.slave[2].ar.valid <= UInt<1>("h00") - io.slave[2].b.ready <= UInt<1>("h00") - io.slave[2].w.bits.user <= UInt<1>("h00") - io.slave[2].w.bits.strb <= UInt<1>("h00") - io.slave[2].w.bits.last <= UInt<1>("h00") - io.slave[2].w.bits.data <= UInt<1>("h00") - io.slave[2].w.valid <= UInt<1>("h00") - io.slave[2].aw.bits.user <= UInt<1>("h00") - io.slave[2].aw.bits.id <= UInt<1>("h00") - io.slave[2].aw.bits.region <= UInt<1>("h00") - io.slave[2].aw.bits.qos <= UInt<1>("h00") - io.slave[2].aw.bits.prot <= UInt<1>("h00") - io.slave[2].aw.bits.cache <= UInt<1>("h00") - io.slave[2].aw.bits.lock <= UInt<1>("h00") - io.slave[2].aw.bits.burst <= UInt<1>("h00") - io.slave[2].aw.bits.size <= UInt<1>("h00") - io.slave[2].aw.bits.len <= UInt<1>("h00") - io.slave[2].aw.bits.addr <= UInt<1>("h00") - io.slave[2].aw.valid <= UInt<1>("h00") - io.master.r.bits.user <= UInt<1>("h00") - io.master.r.bits.id <= UInt<1>("h00") - io.master.r.bits.last <= UInt<1>("h00") - io.master.r.bits.data <= UInt<1>("h00") - io.master.r.bits.resp <= UInt<1>("h00") - io.master.r.valid <= UInt<1>("h00") - io.master.ar.ready <= UInt<1>("h00") - io.master.b.bits.user <= UInt<1>("h00") - io.master.b.bits.id <= UInt<1>("h00") - io.master.b.bits.resp <= UInt<1>("h00") - io.master.b.valid <= UInt<1>("h00") - io.master.w.ready <= UInt<1>("h00") - io.master.aw.ready <= UInt<1>("h00") + io is invalid node T_1278 = geq(io.master.ar.bits.addr, UInt<31>("h040000000")) node T_1280 = lt(io.master.ar.bits.addr, UInt<31>("h040008000")) node T_1281 = and(T_1278, T_1280) @@ -14519,21 +11025,21 @@ circuit Top : T_1316[2] <= T_1314 node T_1321 = cat(T_1316[1], T_1316[0]) node aw_route = cat(T_1316[2], T_1321) - node T_1326 = bit(ar_route, 0) + node T_1326 = bits(ar_route, 0, 0) node T_1327 = and(io.master.ar.valid, T_1326) io.slave[0].ar.valid <= T_1327 io.slave[0].ar.bits <- io.master.ar.bits - node T_1328 = bit(ar_route, 0) + node T_1328 = bits(ar_route, 0, 0) node T_1329 = and(io.slave[0].ar.ready, T_1328) node T_1330 = or(UInt<1>("h00"), T_1329) - node T_1331 = bit(aw_route, 0) + node T_1331 = bits(aw_route, 0, 0) node T_1332 = and(io.master.aw.valid, T_1331) io.slave[0].aw.valid <= T_1332 io.slave[0].aw.bits <- io.master.aw.bits - node T_1333 = bit(aw_route, 0) + node T_1333 = bits(aw_route, 0, 0) node T_1334 = and(io.slave[0].aw.ready, T_1333) node T_1335 = or(UInt<1>("h00"), T_1334) - reg T_1337 : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1337 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node T_1338 = and(io.slave[0].aw.ready, io.slave[0].aw.valid) when T_1338 : T_1337 <= UInt<1>("h01") @@ -14548,21 +11054,21 @@ circuit Top : io.slave[0].w.bits <- io.master.w.bits node T_1344 = and(io.slave[0].w.ready, T_1337) node T_1345 = or(UInt<1>("h00"), T_1344) - node T_1346 = bit(ar_route, 1) + node T_1346 = bits(ar_route, 1, 1) node T_1347 = and(io.master.ar.valid, T_1346) io.slave[1].ar.valid <= T_1347 io.slave[1].ar.bits <- io.master.ar.bits - node T_1348 = bit(ar_route, 1) + node T_1348 = bits(ar_route, 1, 1) node T_1349 = and(io.slave[1].ar.ready, T_1348) node T_1350 = or(T_1330, T_1349) - node T_1351 = bit(aw_route, 1) + node T_1351 = bits(aw_route, 1, 1) node T_1352 = and(io.master.aw.valid, T_1351) io.slave[1].aw.valid <= T_1352 io.slave[1].aw.bits <- io.master.aw.bits - node T_1353 = bit(aw_route, 1) + node T_1353 = bits(aw_route, 1, 1) node T_1354 = and(io.slave[1].aw.ready, T_1353) node T_1355 = or(T_1335, T_1354) - reg T_1357 : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1357 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node T_1358 = and(io.slave[1].aw.ready, io.slave[1].aw.valid) when T_1358 : T_1357 <= UInt<1>("h01") @@ -14577,21 +11083,21 @@ circuit Top : io.slave[1].w.bits <- io.master.w.bits node T_1364 = and(io.slave[1].w.ready, T_1357) node T_1365 = or(T_1345, T_1364) - node T_1366 = bit(ar_route, 2) + node T_1366 = bits(ar_route, 2, 2) node T_1367 = and(io.master.ar.valid, T_1366) io.slave[2].ar.valid <= T_1367 io.slave[2].ar.bits <- io.master.ar.bits - node T_1368 = bit(ar_route, 2) + node T_1368 = bits(ar_route, 2, 2) node T_1369 = and(io.slave[2].ar.ready, T_1368) node ar_ready = or(T_1350, T_1369) - node T_1371 = bit(aw_route, 2) + node T_1371 = bits(aw_route, 2, 2) node T_1372 = and(io.master.aw.valid, T_1371) io.slave[2].aw.valid <= T_1372 io.slave[2].aw.bits <- io.master.aw.bits - node T_1373 = bit(aw_route, 2) + node T_1373 = bits(aw_route, 2, 2) node T_1374 = and(io.slave[2].aw.ready, T_1373) node aw_ready = or(T_1355, T_1374) - reg T_1377 : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1377 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node T_1378 = and(io.slave[2].aw.ready, io.slave[2].aw.valid) when T_1378 : T_1377 <= UInt<1>("h01") @@ -14611,101 +11117,31 @@ circuit Top : node T_1391 = neq(aw_route, UInt<1>("h00")) node w_invalid = eq(T_1391, UInt<1>("h00")) inst err_slave of NastiErrorSlave_40 - err_slave.io.r.ready <= UInt<1>("h00") - err_slave.io.ar.bits.user <= UInt<1>("h00") - err_slave.io.ar.bits.id <= UInt<1>("h00") - err_slave.io.ar.bits.region <= UInt<1>("h00") - err_slave.io.ar.bits.qos <= UInt<1>("h00") - err_slave.io.ar.bits.prot <= UInt<1>("h00") - err_slave.io.ar.bits.cache <= UInt<1>("h00") - err_slave.io.ar.bits.lock <= UInt<1>("h00") - err_slave.io.ar.bits.burst <= UInt<1>("h00") - err_slave.io.ar.bits.size <= UInt<1>("h00") - err_slave.io.ar.bits.len <= UInt<1>("h00") - err_slave.io.ar.bits.addr <= UInt<1>("h00") - err_slave.io.ar.valid <= UInt<1>("h00") - err_slave.io.b.ready <= UInt<1>("h00") - err_slave.io.w.bits.user <= UInt<1>("h00") - err_slave.io.w.bits.strb <= UInt<1>("h00") - err_slave.io.w.bits.last <= UInt<1>("h00") - err_slave.io.w.bits.data <= UInt<1>("h00") - err_slave.io.w.valid <= UInt<1>("h00") - err_slave.io.aw.bits.user <= UInt<1>("h00") - err_slave.io.aw.bits.id <= UInt<1>("h00") - err_slave.io.aw.bits.region <= UInt<1>("h00") - err_slave.io.aw.bits.qos <= UInt<1>("h00") - err_slave.io.aw.bits.prot <= UInt<1>("h00") - err_slave.io.aw.bits.cache <= UInt<1>("h00") - err_slave.io.aw.bits.lock <= UInt<1>("h00") - err_slave.io.aw.bits.burst <= UInt<1>("h00") - err_slave.io.aw.bits.size <= UInt<1>("h00") - err_slave.io.aw.bits.len <= UInt<1>("h00") - err_slave.io.aw.bits.addr <= UInt<1>("h00") - err_slave.io.aw.valid <= UInt<1>("h00") + err_slave.io is invalid err_slave.clk <= clk err_slave.reset <= reset - node T_1426 = and(r_invalid, io.master.ar.valid) - err_slave.io.ar.valid <= T_1426 + node T_1395 = and(r_invalid, io.master.ar.valid) + err_slave.io.ar.valid <= T_1395 err_slave.io.ar.bits <- io.master.ar.bits - node T_1427 = and(w_invalid, io.master.aw.valid) - err_slave.io.aw.valid <= T_1427 + node T_1396 = and(w_invalid, io.master.aw.valid) + err_slave.io.aw.valid <= T_1396 err_slave.io.aw.bits <- io.master.aw.bits err_slave.io.w.valid <= io.master.w.valid err_slave.io.w.bits <- io.master.w.bits - node T_1428 = and(r_invalid, err_slave.io.ar.ready) - node T_1429 = or(ar_ready, T_1428) - io.master.ar.ready <= T_1429 - node T_1430 = and(w_invalid, err_slave.io.aw.ready) - node T_1431 = or(aw_ready, T_1430) - io.master.aw.ready <= T_1431 - node T_1432 = or(w_ready, err_slave.io.w.ready) - io.master.w.ready <= T_1432 + node T_1397 = and(r_invalid, err_slave.io.ar.ready) + node T_1398 = or(ar_ready, T_1397) + io.master.ar.ready <= T_1398 + node T_1399 = and(w_invalid, err_slave.io.aw.ready) + node T_1400 = or(aw_ready, T_1399) + io.master.aw.ready <= T_1400 + node T_1401 = or(w_ready, err_slave.io.w.ready) + io.master.w.ready <= T_1401 inst b_arb of RRArbiter_62 - b_arb.io.out.ready <= UInt<1>("h00") - b_arb.io.in[0].bits.user <= UInt<1>("h00") - b_arb.io.in[0].bits.id <= UInt<1>("h00") - b_arb.io.in[0].bits.resp <= UInt<1>("h00") - b_arb.io.in[0].valid <= UInt<1>("h00") - b_arb.io.in[1].bits.user <= UInt<1>("h00") - b_arb.io.in[1].bits.id <= UInt<1>("h00") - b_arb.io.in[1].bits.resp <= UInt<1>("h00") - b_arb.io.in[1].valid <= UInt<1>("h00") - b_arb.io.in[2].bits.user <= UInt<1>("h00") - b_arb.io.in[2].bits.id <= UInt<1>("h00") - b_arb.io.in[2].bits.resp <= UInt<1>("h00") - b_arb.io.in[2].valid <= UInt<1>("h00") - b_arb.io.in[3].bits.user <= UInt<1>("h00") - b_arb.io.in[3].bits.id <= UInt<1>("h00") - b_arb.io.in[3].bits.resp <= UInt<1>("h00") - b_arb.io.in[3].valid <= UInt<1>("h00") + b_arb.io is invalid b_arb.clk <= clk b_arb.reset <= reset inst r_arb of JunctionsPeekingArbiter_63 - r_arb.io.out.ready <= UInt<1>("h00") - r_arb.io.in[0].bits.user <= UInt<1>("h00") - r_arb.io.in[0].bits.id <= UInt<1>("h00") - r_arb.io.in[0].bits.last <= UInt<1>("h00") - r_arb.io.in[0].bits.data <= UInt<1>("h00") - r_arb.io.in[0].bits.resp <= UInt<1>("h00") - r_arb.io.in[0].valid <= UInt<1>("h00") - r_arb.io.in[1].bits.user <= UInt<1>("h00") - r_arb.io.in[1].bits.id <= UInt<1>("h00") - r_arb.io.in[1].bits.last <= UInt<1>("h00") - r_arb.io.in[1].bits.data <= UInt<1>("h00") - r_arb.io.in[1].bits.resp <= UInt<1>("h00") - r_arb.io.in[1].valid <= UInt<1>("h00") - r_arb.io.in[2].bits.user <= UInt<1>("h00") - r_arb.io.in[2].bits.id <= UInt<1>("h00") - r_arb.io.in[2].bits.last <= UInt<1>("h00") - r_arb.io.in[2].bits.data <= UInt<1>("h00") - r_arb.io.in[2].bits.resp <= UInt<1>("h00") - r_arb.io.in[2].valid <= UInt<1>("h00") - r_arb.io.in[3].bits.user <= UInt<1>("h00") - r_arb.io.in[3].bits.id <= UInt<1>("h00") - r_arb.io.in[3].bits.last <= UInt<1>("h00") - r_arb.io.in[3].bits.data <= UInt<1>("h00") - r_arb.io.in[3].bits.resp <= UInt<1>("h00") - r_arb.io.in[3].valid <= UInt<1>("h00") + r_arb.io is invalid r_arb.clk <= clk r_arb.reset <= reset b_arb.io.in[0] <- io.slave[0].b @@ -14724,373 +11160,25 @@ circuit Top : input reset : UInt<1> output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[3]} - io.slaves[0].r.ready <= UInt<1>("h00") - io.slaves[0].ar.bits.user <= UInt<1>("h00") - io.slaves[0].ar.bits.id <= UInt<1>("h00") - io.slaves[0].ar.bits.region <= UInt<1>("h00") - io.slaves[0].ar.bits.qos <= UInt<1>("h00") - io.slaves[0].ar.bits.prot <= UInt<1>("h00") - io.slaves[0].ar.bits.cache <= UInt<1>("h00") - io.slaves[0].ar.bits.lock <= UInt<1>("h00") - io.slaves[0].ar.bits.burst <= UInt<1>("h00") - io.slaves[0].ar.bits.size <= UInt<1>("h00") - io.slaves[0].ar.bits.len <= UInt<1>("h00") - io.slaves[0].ar.bits.addr <= UInt<1>("h00") - io.slaves[0].ar.valid <= UInt<1>("h00") - io.slaves[0].b.ready <= UInt<1>("h00") - io.slaves[0].w.bits.user <= UInt<1>("h00") - io.slaves[0].w.bits.strb <= UInt<1>("h00") - io.slaves[0].w.bits.last <= UInt<1>("h00") - io.slaves[0].w.bits.data <= UInt<1>("h00") - io.slaves[0].w.valid <= UInt<1>("h00") - io.slaves[0].aw.bits.user <= UInt<1>("h00") - io.slaves[0].aw.bits.id <= UInt<1>("h00") - io.slaves[0].aw.bits.region <= UInt<1>("h00") - io.slaves[0].aw.bits.qos <= UInt<1>("h00") - io.slaves[0].aw.bits.prot <= UInt<1>("h00") - io.slaves[0].aw.bits.cache <= UInt<1>("h00") - io.slaves[0].aw.bits.lock <= UInt<1>("h00") - io.slaves[0].aw.bits.burst <= UInt<1>("h00") - io.slaves[0].aw.bits.size <= UInt<1>("h00") - io.slaves[0].aw.bits.len <= UInt<1>("h00") - io.slaves[0].aw.bits.addr <= UInt<1>("h00") - io.slaves[0].aw.valid <= UInt<1>("h00") - io.slaves[1].r.ready <= UInt<1>("h00") - io.slaves[1].ar.bits.user <= UInt<1>("h00") - io.slaves[1].ar.bits.id <= UInt<1>("h00") - io.slaves[1].ar.bits.region <= UInt<1>("h00") - io.slaves[1].ar.bits.qos <= UInt<1>("h00") - io.slaves[1].ar.bits.prot <= UInt<1>("h00") - io.slaves[1].ar.bits.cache <= UInt<1>("h00") - io.slaves[1].ar.bits.lock <= UInt<1>("h00") - io.slaves[1].ar.bits.burst <= UInt<1>("h00") - io.slaves[1].ar.bits.size <= UInt<1>("h00") - io.slaves[1].ar.bits.len <= UInt<1>("h00") - io.slaves[1].ar.bits.addr <= UInt<1>("h00") - io.slaves[1].ar.valid <= UInt<1>("h00") - io.slaves[1].b.ready <= UInt<1>("h00") - io.slaves[1].w.bits.user <= UInt<1>("h00") - io.slaves[1].w.bits.strb <= UInt<1>("h00") - io.slaves[1].w.bits.last <= UInt<1>("h00") - io.slaves[1].w.bits.data <= UInt<1>("h00") - io.slaves[1].w.valid <= UInt<1>("h00") - io.slaves[1].aw.bits.user <= UInt<1>("h00") - io.slaves[1].aw.bits.id <= UInt<1>("h00") - io.slaves[1].aw.bits.region <= UInt<1>("h00") - io.slaves[1].aw.bits.qos <= UInt<1>("h00") - io.slaves[1].aw.bits.prot <= UInt<1>("h00") - io.slaves[1].aw.bits.cache <= UInt<1>("h00") - io.slaves[1].aw.bits.lock <= UInt<1>("h00") - io.slaves[1].aw.bits.burst <= UInt<1>("h00") - io.slaves[1].aw.bits.size <= UInt<1>("h00") - io.slaves[1].aw.bits.len <= UInt<1>("h00") - io.slaves[1].aw.bits.addr <= UInt<1>("h00") - io.slaves[1].aw.valid <= UInt<1>("h00") - io.slaves[2].r.ready <= UInt<1>("h00") - io.slaves[2].ar.bits.user <= UInt<1>("h00") - io.slaves[2].ar.bits.id <= UInt<1>("h00") - io.slaves[2].ar.bits.region <= UInt<1>("h00") - io.slaves[2].ar.bits.qos <= UInt<1>("h00") - io.slaves[2].ar.bits.prot <= UInt<1>("h00") - io.slaves[2].ar.bits.cache <= UInt<1>("h00") - io.slaves[2].ar.bits.lock <= UInt<1>("h00") - io.slaves[2].ar.bits.burst <= UInt<1>("h00") - io.slaves[2].ar.bits.size <= UInt<1>("h00") - io.slaves[2].ar.bits.len <= UInt<1>("h00") - io.slaves[2].ar.bits.addr <= UInt<1>("h00") - io.slaves[2].ar.valid <= UInt<1>("h00") - io.slaves[2].b.ready <= UInt<1>("h00") - io.slaves[2].w.bits.user <= UInt<1>("h00") - io.slaves[2].w.bits.strb <= UInt<1>("h00") - io.slaves[2].w.bits.last <= UInt<1>("h00") - io.slaves[2].w.bits.data <= UInt<1>("h00") - io.slaves[2].w.valid <= UInt<1>("h00") - io.slaves[2].aw.bits.user <= UInt<1>("h00") - io.slaves[2].aw.bits.id <= UInt<1>("h00") - io.slaves[2].aw.bits.region <= UInt<1>("h00") - io.slaves[2].aw.bits.qos <= UInt<1>("h00") - io.slaves[2].aw.bits.prot <= UInt<1>("h00") - io.slaves[2].aw.bits.cache <= UInt<1>("h00") - io.slaves[2].aw.bits.lock <= UInt<1>("h00") - io.slaves[2].aw.bits.burst <= UInt<1>("h00") - io.slaves[2].aw.bits.size <= UInt<1>("h00") - io.slaves[2].aw.bits.len <= UInt<1>("h00") - io.slaves[2].aw.bits.addr <= UInt<1>("h00") - io.slaves[2].aw.valid <= UInt<1>("h00") - io.masters[0].r.bits.user <= UInt<1>("h00") - io.masters[0].r.bits.id <= UInt<1>("h00") - io.masters[0].r.bits.last <= UInt<1>("h00") - io.masters[0].r.bits.data <= UInt<1>("h00") - io.masters[0].r.bits.resp <= UInt<1>("h00") - io.masters[0].r.valid <= UInt<1>("h00") - io.masters[0].ar.ready <= UInt<1>("h00") - io.masters[0].b.bits.user <= UInt<1>("h00") - io.masters[0].b.bits.id <= UInt<1>("h00") - io.masters[0].b.bits.resp <= UInt<1>("h00") - io.masters[0].b.valid <= UInt<1>("h00") - io.masters[0].w.ready <= UInt<1>("h00") - io.masters[0].aw.ready <= UInt<1>("h00") + io is invalid inst T_2233 of NastiRouter_58 - T_2233.io.slave[0].r.bits.user <= UInt<1>("h00") - T_2233.io.slave[0].r.bits.id <= UInt<1>("h00") - T_2233.io.slave[0].r.bits.last <= UInt<1>("h00") - T_2233.io.slave[0].r.bits.data <= UInt<1>("h00") - T_2233.io.slave[0].r.bits.resp <= UInt<1>("h00") - T_2233.io.slave[0].r.valid <= UInt<1>("h00") - T_2233.io.slave[0].ar.ready <= UInt<1>("h00") - T_2233.io.slave[0].b.bits.user <= UInt<1>("h00") - T_2233.io.slave[0].b.bits.id <= UInt<1>("h00") - T_2233.io.slave[0].b.bits.resp <= UInt<1>("h00") - T_2233.io.slave[0].b.valid <= UInt<1>("h00") - T_2233.io.slave[0].w.ready <= UInt<1>("h00") - T_2233.io.slave[0].aw.ready <= UInt<1>("h00") - T_2233.io.slave[1].r.bits.user <= UInt<1>("h00") - T_2233.io.slave[1].r.bits.id <= UInt<1>("h00") - T_2233.io.slave[1].r.bits.last <= UInt<1>("h00") - T_2233.io.slave[1].r.bits.data <= UInt<1>("h00") - T_2233.io.slave[1].r.bits.resp <= UInt<1>("h00") - T_2233.io.slave[1].r.valid <= UInt<1>("h00") - T_2233.io.slave[1].ar.ready <= UInt<1>("h00") - T_2233.io.slave[1].b.bits.user <= UInt<1>("h00") - T_2233.io.slave[1].b.bits.id <= UInt<1>("h00") - T_2233.io.slave[1].b.bits.resp <= UInt<1>("h00") - T_2233.io.slave[1].b.valid <= UInt<1>("h00") - T_2233.io.slave[1].w.ready <= UInt<1>("h00") - T_2233.io.slave[1].aw.ready <= UInt<1>("h00") - T_2233.io.slave[2].r.bits.user <= UInt<1>("h00") - T_2233.io.slave[2].r.bits.id <= UInt<1>("h00") - T_2233.io.slave[2].r.bits.last <= UInt<1>("h00") - T_2233.io.slave[2].r.bits.data <= UInt<1>("h00") - T_2233.io.slave[2].r.bits.resp <= UInt<1>("h00") - T_2233.io.slave[2].r.valid <= UInt<1>("h00") - T_2233.io.slave[2].ar.ready <= UInt<1>("h00") - T_2233.io.slave[2].b.bits.user <= UInt<1>("h00") - T_2233.io.slave[2].b.bits.id <= UInt<1>("h00") - T_2233.io.slave[2].b.bits.resp <= UInt<1>("h00") - T_2233.io.slave[2].b.valid <= UInt<1>("h00") - T_2233.io.slave[2].w.ready <= UInt<1>("h00") - T_2233.io.slave[2].aw.ready <= UInt<1>("h00") - T_2233.io.master.r.ready <= UInt<1>("h00") - T_2233.io.master.ar.bits.user <= UInt<1>("h00") - T_2233.io.master.ar.bits.id <= UInt<1>("h00") - T_2233.io.master.ar.bits.region <= UInt<1>("h00") - T_2233.io.master.ar.bits.qos <= UInt<1>("h00") - T_2233.io.master.ar.bits.prot <= UInt<1>("h00") - T_2233.io.master.ar.bits.cache <= UInt<1>("h00") - T_2233.io.master.ar.bits.lock <= UInt<1>("h00") - T_2233.io.master.ar.bits.burst <= UInt<1>("h00") - T_2233.io.master.ar.bits.size <= UInt<1>("h00") - T_2233.io.master.ar.bits.len <= UInt<1>("h00") - T_2233.io.master.ar.bits.addr <= UInt<1>("h00") - T_2233.io.master.ar.valid <= UInt<1>("h00") - T_2233.io.master.b.ready <= UInt<1>("h00") - T_2233.io.master.w.bits.user <= UInt<1>("h00") - T_2233.io.master.w.bits.strb <= UInt<1>("h00") - T_2233.io.master.w.bits.last <= UInt<1>("h00") - T_2233.io.master.w.bits.data <= UInt<1>("h00") - T_2233.io.master.w.valid <= UInt<1>("h00") - T_2233.io.master.aw.bits.user <= UInt<1>("h00") - T_2233.io.master.aw.bits.id <= UInt<1>("h00") - T_2233.io.master.aw.bits.region <= UInt<1>("h00") - T_2233.io.master.aw.bits.qos <= UInt<1>("h00") - T_2233.io.master.aw.bits.prot <= UInt<1>("h00") - T_2233.io.master.aw.bits.cache <= UInt<1>("h00") - T_2233.io.master.aw.bits.lock <= UInt<1>("h00") - T_2233.io.master.aw.bits.burst <= UInt<1>("h00") - T_2233.io.master.aw.bits.size <= UInt<1>("h00") - T_2233.io.master.aw.bits.len <= UInt<1>("h00") - T_2233.io.master.aw.bits.addr <= UInt<1>("h00") - T_2233.io.master.aw.valid <= UInt<1>("h00") + T_2233.io is invalid T_2233.clk <= clk T_2233.reset <= reset T_2233.io.master <- io.masters[0] - io.slaves <- T_2233.io.slave + io.slaves <= T_2233.io.slave module NastiRecursiveInterconnect_56 : input clk : Clock input reset : UInt<1> output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[3]} - io.slaves[0].r.ready <= UInt<1>("h00") - io.slaves[0].ar.bits.user <= UInt<1>("h00") - io.slaves[0].ar.bits.id <= UInt<1>("h00") - io.slaves[0].ar.bits.region <= UInt<1>("h00") - io.slaves[0].ar.bits.qos <= UInt<1>("h00") - io.slaves[0].ar.bits.prot <= UInt<1>("h00") - io.slaves[0].ar.bits.cache <= UInt<1>("h00") - io.slaves[0].ar.bits.lock <= UInt<1>("h00") - io.slaves[0].ar.bits.burst <= UInt<1>("h00") - io.slaves[0].ar.bits.size <= UInt<1>("h00") - io.slaves[0].ar.bits.len <= UInt<1>("h00") - io.slaves[0].ar.bits.addr <= UInt<1>("h00") - io.slaves[0].ar.valid <= UInt<1>("h00") - io.slaves[0].b.ready <= UInt<1>("h00") - io.slaves[0].w.bits.user <= UInt<1>("h00") - io.slaves[0].w.bits.strb <= UInt<1>("h00") - io.slaves[0].w.bits.last <= UInt<1>("h00") - io.slaves[0].w.bits.data <= UInt<1>("h00") - io.slaves[0].w.valid <= UInt<1>("h00") - io.slaves[0].aw.bits.user <= UInt<1>("h00") - io.slaves[0].aw.bits.id <= UInt<1>("h00") - io.slaves[0].aw.bits.region <= UInt<1>("h00") - io.slaves[0].aw.bits.qos <= UInt<1>("h00") - io.slaves[0].aw.bits.prot <= UInt<1>("h00") - io.slaves[0].aw.bits.cache <= UInt<1>("h00") - io.slaves[0].aw.bits.lock <= UInt<1>("h00") - io.slaves[0].aw.bits.burst <= UInt<1>("h00") - io.slaves[0].aw.bits.size <= UInt<1>("h00") - io.slaves[0].aw.bits.len <= UInt<1>("h00") - io.slaves[0].aw.bits.addr <= UInt<1>("h00") - io.slaves[0].aw.valid <= UInt<1>("h00") - io.slaves[1].r.ready <= UInt<1>("h00") - io.slaves[1].ar.bits.user <= UInt<1>("h00") - io.slaves[1].ar.bits.id <= UInt<1>("h00") - io.slaves[1].ar.bits.region <= UInt<1>("h00") - io.slaves[1].ar.bits.qos <= UInt<1>("h00") - io.slaves[1].ar.bits.prot <= UInt<1>("h00") - io.slaves[1].ar.bits.cache <= UInt<1>("h00") - io.slaves[1].ar.bits.lock <= UInt<1>("h00") - io.slaves[1].ar.bits.burst <= UInt<1>("h00") - io.slaves[1].ar.bits.size <= UInt<1>("h00") - io.slaves[1].ar.bits.len <= UInt<1>("h00") - io.slaves[1].ar.bits.addr <= UInt<1>("h00") - io.slaves[1].ar.valid <= UInt<1>("h00") - io.slaves[1].b.ready <= UInt<1>("h00") - io.slaves[1].w.bits.user <= UInt<1>("h00") - io.slaves[1].w.bits.strb <= UInt<1>("h00") - io.slaves[1].w.bits.last <= UInt<1>("h00") - io.slaves[1].w.bits.data <= UInt<1>("h00") - io.slaves[1].w.valid <= UInt<1>("h00") - io.slaves[1].aw.bits.user <= UInt<1>("h00") - io.slaves[1].aw.bits.id <= UInt<1>("h00") - io.slaves[1].aw.bits.region <= UInt<1>("h00") - io.slaves[1].aw.bits.qos <= UInt<1>("h00") - io.slaves[1].aw.bits.prot <= UInt<1>("h00") - io.slaves[1].aw.bits.cache <= UInt<1>("h00") - io.slaves[1].aw.bits.lock <= UInt<1>("h00") - io.slaves[1].aw.bits.burst <= UInt<1>("h00") - io.slaves[1].aw.bits.size <= UInt<1>("h00") - io.slaves[1].aw.bits.len <= UInt<1>("h00") - io.slaves[1].aw.bits.addr <= UInt<1>("h00") - io.slaves[1].aw.valid <= UInt<1>("h00") - io.slaves[2].r.ready <= UInt<1>("h00") - io.slaves[2].ar.bits.user <= UInt<1>("h00") - io.slaves[2].ar.bits.id <= UInt<1>("h00") - io.slaves[2].ar.bits.region <= UInt<1>("h00") - io.slaves[2].ar.bits.qos <= UInt<1>("h00") - io.slaves[2].ar.bits.prot <= UInt<1>("h00") - io.slaves[2].ar.bits.cache <= UInt<1>("h00") - io.slaves[2].ar.bits.lock <= UInt<1>("h00") - io.slaves[2].ar.bits.burst <= UInt<1>("h00") - io.slaves[2].ar.bits.size <= UInt<1>("h00") - io.slaves[2].ar.bits.len <= UInt<1>("h00") - io.slaves[2].ar.bits.addr <= UInt<1>("h00") - io.slaves[2].ar.valid <= UInt<1>("h00") - io.slaves[2].b.ready <= UInt<1>("h00") - io.slaves[2].w.bits.user <= UInt<1>("h00") - io.slaves[2].w.bits.strb <= UInt<1>("h00") - io.slaves[2].w.bits.last <= UInt<1>("h00") - io.slaves[2].w.bits.data <= UInt<1>("h00") - io.slaves[2].w.valid <= UInt<1>("h00") - io.slaves[2].aw.bits.user <= UInt<1>("h00") - io.slaves[2].aw.bits.id <= UInt<1>("h00") - io.slaves[2].aw.bits.region <= UInt<1>("h00") - io.slaves[2].aw.bits.qos <= UInt<1>("h00") - io.slaves[2].aw.bits.prot <= UInt<1>("h00") - io.slaves[2].aw.bits.cache <= UInt<1>("h00") - io.slaves[2].aw.bits.lock <= UInt<1>("h00") - io.slaves[2].aw.bits.burst <= UInt<1>("h00") - io.slaves[2].aw.bits.size <= UInt<1>("h00") - io.slaves[2].aw.bits.len <= UInt<1>("h00") - io.slaves[2].aw.bits.addr <= UInt<1>("h00") - io.slaves[2].aw.valid <= UInt<1>("h00") - io.masters[0].r.bits.user <= UInt<1>("h00") - io.masters[0].r.bits.id <= UInt<1>("h00") - io.masters[0].r.bits.last <= UInt<1>("h00") - io.masters[0].r.bits.data <= UInt<1>("h00") - io.masters[0].r.bits.resp <= UInt<1>("h00") - io.masters[0].r.valid <= UInt<1>("h00") - io.masters[0].ar.ready <= UInt<1>("h00") - io.masters[0].b.bits.user <= UInt<1>("h00") - io.masters[0].b.bits.id <= UInt<1>("h00") - io.masters[0].b.bits.resp <= UInt<1>("h00") - io.masters[0].b.valid <= UInt<1>("h00") - io.masters[0].w.ready <= UInt<1>("h00") - io.masters[0].aw.ready <= UInt<1>("h00") + io is invalid inst xbar of NastiCrossbar_57 - xbar.io.slaves[0].r.bits.user <= UInt<1>("h00") - xbar.io.slaves[0].r.bits.id <= UInt<1>("h00") - xbar.io.slaves[0].r.bits.last <= UInt<1>("h00") - xbar.io.slaves[0].r.bits.data <= UInt<1>("h00") - xbar.io.slaves[0].r.bits.resp <= UInt<1>("h00") - xbar.io.slaves[0].r.valid <= UInt<1>("h00") - xbar.io.slaves[0].ar.ready <= UInt<1>("h00") - xbar.io.slaves[0].b.bits.user <= UInt<1>("h00") - xbar.io.slaves[0].b.bits.id <= UInt<1>("h00") - xbar.io.slaves[0].b.bits.resp <= UInt<1>("h00") - xbar.io.slaves[0].b.valid <= UInt<1>("h00") - xbar.io.slaves[0].w.ready <= UInt<1>("h00") - xbar.io.slaves[0].aw.ready <= UInt<1>("h00") - xbar.io.slaves[1].r.bits.user <= UInt<1>("h00") - xbar.io.slaves[1].r.bits.id <= UInt<1>("h00") - xbar.io.slaves[1].r.bits.last <= UInt<1>("h00") - xbar.io.slaves[1].r.bits.data <= UInt<1>("h00") - xbar.io.slaves[1].r.bits.resp <= UInt<1>("h00") - xbar.io.slaves[1].r.valid <= UInt<1>("h00") - xbar.io.slaves[1].ar.ready <= UInt<1>("h00") - xbar.io.slaves[1].b.bits.user <= UInt<1>("h00") - xbar.io.slaves[1].b.bits.id <= UInt<1>("h00") - xbar.io.slaves[1].b.bits.resp <= UInt<1>("h00") - xbar.io.slaves[1].b.valid <= UInt<1>("h00") - xbar.io.slaves[1].w.ready <= UInt<1>("h00") - xbar.io.slaves[1].aw.ready <= UInt<1>("h00") - xbar.io.slaves[2].r.bits.user <= UInt<1>("h00") - xbar.io.slaves[2].r.bits.id <= UInt<1>("h00") - xbar.io.slaves[2].r.bits.last <= UInt<1>("h00") - xbar.io.slaves[2].r.bits.data <= UInt<1>("h00") - xbar.io.slaves[2].r.bits.resp <= UInt<1>("h00") - xbar.io.slaves[2].r.valid <= UInt<1>("h00") - xbar.io.slaves[2].ar.ready <= UInt<1>("h00") - xbar.io.slaves[2].b.bits.user <= UInt<1>("h00") - xbar.io.slaves[2].b.bits.id <= UInt<1>("h00") - xbar.io.slaves[2].b.bits.resp <= UInt<1>("h00") - xbar.io.slaves[2].b.valid <= UInt<1>("h00") - xbar.io.slaves[2].w.ready <= UInt<1>("h00") - xbar.io.slaves[2].aw.ready <= UInt<1>("h00") - xbar.io.masters[0].r.ready <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.user <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.id <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.region <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.qos <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.prot <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.cache <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.lock <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.burst <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.size <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.len <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.addr <= UInt<1>("h00") - xbar.io.masters[0].ar.valid <= UInt<1>("h00") - xbar.io.masters[0].b.ready <= UInt<1>("h00") - xbar.io.masters[0].w.bits.user <= UInt<1>("h00") - xbar.io.masters[0].w.bits.strb <= UInt<1>("h00") - xbar.io.masters[0].w.bits.last <= UInt<1>("h00") - xbar.io.masters[0].w.bits.data <= UInt<1>("h00") - xbar.io.masters[0].w.valid <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.user <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.id <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.region <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.qos <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.prot <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.cache <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.lock <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.burst <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.size <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.len <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.addr <= UInt<1>("h00") - xbar.io.masters[0].aw.valid <= UInt<1>("h00") + xbar.io is invalid xbar.clk <= clk xbar.reset <= reset - xbar.io.masters <- io.masters + xbar.io.masters <= io.masters io.slaves[0] <- xbar.io.slaves[0] io.slaves[1] <- xbar.io.slaves[1] io.slaves[2] <- xbar.io.slaves[2] @@ -15100,418 +11188,26 @@ circuit Top : input reset : UInt<1> output io : {flip masters : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[2], slaves : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[5]} - io.slaves[0].r.ready <= UInt<1>("h00") - io.slaves[0].ar.bits.user <= UInt<1>("h00") - io.slaves[0].ar.bits.id <= UInt<1>("h00") - io.slaves[0].ar.bits.region <= UInt<1>("h00") - io.slaves[0].ar.bits.qos <= UInt<1>("h00") - io.slaves[0].ar.bits.prot <= UInt<1>("h00") - io.slaves[0].ar.bits.cache <= UInt<1>("h00") - io.slaves[0].ar.bits.lock <= UInt<1>("h00") - io.slaves[0].ar.bits.burst <= UInt<1>("h00") - io.slaves[0].ar.bits.size <= UInt<1>("h00") - io.slaves[0].ar.bits.len <= UInt<1>("h00") - io.slaves[0].ar.bits.addr <= UInt<1>("h00") - io.slaves[0].ar.valid <= UInt<1>("h00") - io.slaves[0].b.ready <= UInt<1>("h00") - io.slaves[0].w.bits.user <= UInt<1>("h00") - io.slaves[0].w.bits.strb <= UInt<1>("h00") - io.slaves[0].w.bits.last <= UInt<1>("h00") - io.slaves[0].w.bits.data <= UInt<1>("h00") - io.slaves[0].w.valid <= UInt<1>("h00") - io.slaves[0].aw.bits.user <= UInt<1>("h00") - io.slaves[0].aw.bits.id <= UInt<1>("h00") - io.slaves[0].aw.bits.region <= UInt<1>("h00") - io.slaves[0].aw.bits.qos <= UInt<1>("h00") - io.slaves[0].aw.bits.prot <= UInt<1>("h00") - io.slaves[0].aw.bits.cache <= UInt<1>("h00") - io.slaves[0].aw.bits.lock <= UInt<1>("h00") - io.slaves[0].aw.bits.burst <= UInt<1>("h00") - io.slaves[0].aw.bits.size <= UInt<1>("h00") - io.slaves[0].aw.bits.len <= UInt<1>("h00") - io.slaves[0].aw.bits.addr <= UInt<1>("h00") - io.slaves[0].aw.valid <= UInt<1>("h00") - io.slaves[1].r.ready <= UInt<1>("h00") - io.slaves[1].ar.bits.user <= UInt<1>("h00") - io.slaves[1].ar.bits.id <= UInt<1>("h00") - io.slaves[1].ar.bits.region <= UInt<1>("h00") - io.slaves[1].ar.bits.qos <= UInt<1>("h00") - io.slaves[1].ar.bits.prot <= UInt<1>("h00") - io.slaves[1].ar.bits.cache <= UInt<1>("h00") - io.slaves[1].ar.bits.lock <= UInt<1>("h00") - io.slaves[1].ar.bits.burst <= UInt<1>("h00") - io.slaves[1].ar.bits.size <= UInt<1>("h00") - io.slaves[1].ar.bits.len <= UInt<1>("h00") - io.slaves[1].ar.bits.addr <= UInt<1>("h00") - io.slaves[1].ar.valid <= UInt<1>("h00") - io.slaves[1].b.ready <= UInt<1>("h00") - io.slaves[1].w.bits.user <= UInt<1>("h00") - io.slaves[1].w.bits.strb <= UInt<1>("h00") - io.slaves[1].w.bits.last <= UInt<1>("h00") - io.slaves[1].w.bits.data <= UInt<1>("h00") - io.slaves[1].w.valid <= UInt<1>("h00") - io.slaves[1].aw.bits.user <= UInt<1>("h00") - io.slaves[1].aw.bits.id <= UInt<1>("h00") - io.slaves[1].aw.bits.region <= UInt<1>("h00") - io.slaves[1].aw.bits.qos <= UInt<1>("h00") - io.slaves[1].aw.bits.prot <= UInt<1>("h00") - io.slaves[1].aw.bits.cache <= UInt<1>("h00") - io.slaves[1].aw.bits.lock <= UInt<1>("h00") - io.slaves[1].aw.bits.burst <= UInt<1>("h00") - io.slaves[1].aw.bits.size <= UInt<1>("h00") - io.slaves[1].aw.bits.len <= UInt<1>("h00") - io.slaves[1].aw.bits.addr <= UInt<1>("h00") - io.slaves[1].aw.valid <= UInt<1>("h00") - io.slaves[2].r.ready <= UInt<1>("h00") - io.slaves[2].ar.bits.user <= UInt<1>("h00") - io.slaves[2].ar.bits.id <= UInt<1>("h00") - io.slaves[2].ar.bits.region <= UInt<1>("h00") - io.slaves[2].ar.bits.qos <= UInt<1>("h00") - io.slaves[2].ar.bits.prot <= UInt<1>("h00") - io.slaves[2].ar.bits.cache <= UInt<1>("h00") - io.slaves[2].ar.bits.lock <= UInt<1>("h00") - io.slaves[2].ar.bits.burst <= UInt<1>("h00") - io.slaves[2].ar.bits.size <= UInt<1>("h00") - io.slaves[2].ar.bits.len <= UInt<1>("h00") - io.slaves[2].ar.bits.addr <= UInt<1>("h00") - io.slaves[2].ar.valid <= UInt<1>("h00") - io.slaves[2].b.ready <= UInt<1>("h00") - io.slaves[2].w.bits.user <= UInt<1>("h00") - io.slaves[2].w.bits.strb <= UInt<1>("h00") - io.slaves[2].w.bits.last <= UInt<1>("h00") - io.slaves[2].w.bits.data <= UInt<1>("h00") - io.slaves[2].w.valid <= UInt<1>("h00") - io.slaves[2].aw.bits.user <= UInt<1>("h00") - io.slaves[2].aw.bits.id <= UInt<1>("h00") - io.slaves[2].aw.bits.region <= UInt<1>("h00") - io.slaves[2].aw.bits.qos <= UInt<1>("h00") - io.slaves[2].aw.bits.prot <= UInt<1>("h00") - io.slaves[2].aw.bits.cache <= UInt<1>("h00") - io.slaves[2].aw.bits.lock <= UInt<1>("h00") - io.slaves[2].aw.bits.burst <= UInt<1>("h00") - io.slaves[2].aw.bits.size <= UInt<1>("h00") - io.slaves[2].aw.bits.len <= UInt<1>("h00") - io.slaves[2].aw.bits.addr <= UInt<1>("h00") - io.slaves[2].aw.valid <= UInt<1>("h00") - io.slaves[3].r.ready <= UInt<1>("h00") - io.slaves[3].ar.bits.user <= UInt<1>("h00") - io.slaves[3].ar.bits.id <= UInt<1>("h00") - io.slaves[3].ar.bits.region <= UInt<1>("h00") - io.slaves[3].ar.bits.qos <= UInt<1>("h00") - io.slaves[3].ar.bits.prot <= UInt<1>("h00") - io.slaves[3].ar.bits.cache <= UInt<1>("h00") - io.slaves[3].ar.bits.lock <= UInt<1>("h00") - io.slaves[3].ar.bits.burst <= UInt<1>("h00") - io.slaves[3].ar.bits.size <= UInt<1>("h00") - io.slaves[3].ar.bits.len <= UInt<1>("h00") - io.slaves[3].ar.bits.addr <= UInt<1>("h00") - io.slaves[3].ar.valid <= UInt<1>("h00") - io.slaves[3].b.ready <= UInt<1>("h00") - io.slaves[3].w.bits.user <= UInt<1>("h00") - io.slaves[3].w.bits.strb <= UInt<1>("h00") - io.slaves[3].w.bits.last <= UInt<1>("h00") - io.slaves[3].w.bits.data <= UInt<1>("h00") - io.slaves[3].w.valid <= UInt<1>("h00") - io.slaves[3].aw.bits.user <= UInt<1>("h00") - io.slaves[3].aw.bits.id <= UInt<1>("h00") - io.slaves[3].aw.bits.region <= UInt<1>("h00") - io.slaves[3].aw.bits.qos <= UInt<1>("h00") - io.slaves[3].aw.bits.prot <= UInt<1>("h00") - io.slaves[3].aw.bits.cache <= UInt<1>("h00") - io.slaves[3].aw.bits.lock <= UInt<1>("h00") - io.slaves[3].aw.bits.burst <= UInt<1>("h00") - io.slaves[3].aw.bits.size <= UInt<1>("h00") - io.slaves[3].aw.bits.len <= UInt<1>("h00") - io.slaves[3].aw.bits.addr <= UInt<1>("h00") - io.slaves[3].aw.valid <= UInt<1>("h00") - io.slaves[4].r.ready <= UInt<1>("h00") - io.slaves[4].ar.bits.user <= UInt<1>("h00") - io.slaves[4].ar.bits.id <= UInt<1>("h00") - io.slaves[4].ar.bits.region <= UInt<1>("h00") - io.slaves[4].ar.bits.qos <= UInt<1>("h00") - io.slaves[4].ar.bits.prot <= UInt<1>("h00") - io.slaves[4].ar.bits.cache <= UInt<1>("h00") - io.slaves[4].ar.bits.lock <= UInt<1>("h00") - io.slaves[4].ar.bits.burst <= UInt<1>("h00") - io.slaves[4].ar.bits.size <= UInt<1>("h00") - io.slaves[4].ar.bits.len <= UInt<1>("h00") - io.slaves[4].ar.bits.addr <= UInt<1>("h00") - io.slaves[4].ar.valid <= UInt<1>("h00") - io.slaves[4].b.ready <= UInt<1>("h00") - io.slaves[4].w.bits.user <= UInt<1>("h00") - io.slaves[4].w.bits.strb <= UInt<1>("h00") - io.slaves[4].w.bits.last <= UInt<1>("h00") - io.slaves[4].w.bits.data <= UInt<1>("h00") - io.slaves[4].w.valid <= UInt<1>("h00") - io.slaves[4].aw.bits.user <= UInt<1>("h00") - io.slaves[4].aw.bits.id <= UInt<1>("h00") - io.slaves[4].aw.bits.region <= UInt<1>("h00") - io.slaves[4].aw.bits.qos <= UInt<1>("h00") - io.slaves[4].aw.bits.prot <= UInt<1>("h00") - io.slaves[4].aw.bits.cache <= UInt<1>("h00") - io.slaves[4].aw.bits.lock <= UInt<1>("h00") - io.slaves[4].aw.bits.burst <= UInt<1>("h00") - io.slaves[4].aw.bits.size <= UInt<1>("h00") - io.slaves[4].aw.bits.len <= UInt<1>("h00") - io.slaves[4].aw.bits.addr <= UInt<1>("h00") - io.slaves[4].aw.valid <= UInt<1>("h00") - io.masters[0].r.bits.user <= UInt<1>("h00") - io.masters[0].r.bits.id <= UInt<1>("h00") - io.masters[0].r.bits.last <= UInt<1>("h00") - io.masters[0].r.bits.data <= UInt<1>("h00") - io.masters[0].r.bits.resp <= UInt<1>("h00") - io.masters[0].r.valid <= UInt<1>("h00") - io.masters[0].ar.ready <= UInt<1>("h00") - io.masters[0].b.bits.user <= UInt<1>("h00") - io.masters[0].b.bits.id <= UInt<1>("h00") - io.masters[0].b.bits.resp <= UInt<1>("h00") - io.masters[0].b.valid <= UInt<1>("h00") - io.masters[0].w.ready <= UInt<1>("h00") - io.masters[0].aw.ready <= UInt<1>("h00") - io.masters[1].r.bits.user <= UInt<1>("h00") - io.masters[1].r.bits.id <= UInt<1>("h00") - io.masters[1].r.bits.last <= UInt<1>("h00") - io.masters[1].r.bits.data <= UInt<1>("h00") - io.masters[1].r.bits.resp <= UInt<1>("h00") - io.masters[1].r.valid <= UInt<1>("h00") - io.masters[1].ar.ready <= UInt<1>("h00") - io.masters[1].b.bits.user <= UInt<1>("h00") - io.masters[1].b.bits.id <= UInt<1>("h00") - io.masters[1].b.bits.resp <= UInt<1>("h00") - io.masters[1].b.valid <= UInt<1>("h00") - io.masters[1].w.ready <= UInt<1>("h00") - io.masters[1].aw.ready <= UInt<1>("h00") + io is invalid inst xbar of NastiCrossbar - xbar.io.slaves[0].r.bits.user <= UInt<1>("h00") - xbar.io.slaves[0].r.bits.id <= UInt<1>("h00") - xbar.io.slaves[0].r.bits.last <= UInt<1>("h00") - xbar.io.slaves[0].r.bits.data <= UInt<1>("h00") - xbar.io.slaves[0].r.bits.resp <= UInt<1>("h00") - xbar.io.slaves[0].r.valid <= UInt<1>("h00") - xbar.io.slaves[0].ar.ready <= UInt<1>("h00") - xbar.io.slaves[0].b.bits.user <= UInt<1>("h00") - xbar.io.slaves[0].b.bits.id <= UInt<1>("h00") - xbar.io.slaves[0].b.bits.resp <= UInt<1>("h00") - xbar.io.slaves[0].b.valid <= UInt<1>("h00") - xbar.io.slaves[0].w.ready <= UInt<1>("h00") - xbar.io.slaves[0].aw.ready <= UInt<1>("h00") - xbar.io.slaves[1].r.bits.user <= UInt<1>("h00") - xbar.io.slaves[1].r.bits.id <= UInt<1>("h00") - xbar.io.slaves[1].r.bits.last <= UInt<1>("h00") - xbar.io.slaves[1].r.bits.data <= UInt<1>("h00") - xbar.io.slaves[1].r.bits.resp <= UInt<1>("h00") - xbar.io.slaves[1].r.valid <= UInt<1>("h00") - xbar.io.slaves[1].ar.ready <= UInt<1>("h00") - xbar.io.slaves[1].b.bits.user <= UInt<1>("h00") - xbar.io.slaves[1].b.bits.id <= UInt<1>("h00") - xbar.io.slaves[1].b.bits.resp <= UInt<1>("h00") - xbar.io.slaves[1].b.valid <= UInt<1>("h00") - xbar.io.slaves[1].w.ready <= UInt<1>("h00") - xbar.io.slaves[1].aw.ready <= UInt<1>("h00") - xbar.io.slaves[2].r.bits.user <= UInt<1>("h00") - xbar.io.slaves[2].r.bits.id <= UInt<1>("h00") - xbar.io.slaves[2].r.bits.last <= UInt<1>("h00") - xbar.io.slaves[2].r.bits.data <= UInt<1>("h00") - xbar.io.slaves[2].r.bits.resp <= UInt<1>("h00") - xbar.io.slaves[2].r.valid <= UInt<1>("h00") - xbar.io.slaves[2].ar.ready <= UInt<1>("h00") - xbar.io.slaves[2].b.bits.user <= UInt<1>("h00") - xbar.io.slaves[2].b.bits.id <= UInt<1>("h00") - xbar.io.slaves[2].b.bits.resp <= UInt<1>("h00") - xbar.io.slaves[2].b.valid <= UInt<1>("h00") - xbar.io.slaves[2].w.ready <= UInt<1>("h00") - xbar.io.slaves[2].aw.ready <= UInt<1>("h00") - xbar.io.slaves[3].r.bits.user <= UInt<1>("h00") - xbar.io.slaves[3].r.bits.id <= UInt<1>("h00") - xbar.io.slaves[3].r.bits.last <= UInt<1>("h00") - xbar.io.slaves[3].r.bits.data <= UInt<1>("h00") - xbar.io.slaves[3].r.bits.resp <= UInt<1>("h00") - xbar.io.slaves[3].r.valid <= UInt<1>("h00") - xbar.io.slaves[3].ar.ready <= UInt<1>("h00") - xbar.io.slaves[3].b.bits.user <= UInt<1>("h00") - xbar.io.slaves[3].b.bits.id <= UInt<1>("h00") - xbar.io.slaves[3].b.bits.resp <= UInt<1>("h00") - xbar.io.slaves[3].b.valid <= UInt<1>("h00") - xbar.io.slaves[3].w.ready <= UInt<1>("h00") - xbar.io.slaves[3].aw.ready <= UInt<1>("h00") - xbar.io.masters[0].r.ready <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.user <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.id <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.region <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.qos <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.prot <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.cache <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.lock <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.burst <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.size <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.len <= UInt<1>("h00") - xbar.io.masters[0].ar.bits.addr <= UInt<1>("h00") - xbar.io.masters[0].ar.valid <= UInt<1>("h00") - xbar.io.masters[0].b.ready <= UInt<1>("h00") - xbar.io.masters[0].w.bits.user <= UInt<1>("h00") - xbar.io.masters[0].w.bits.strb <= UInt<1>("h00") - xbar.io.masters[0].w.bits.last <= UInt<1>("h00") - xbar.io.masters[0].w.bits.data <= UInt<1>("h00") - xbar.io.masters[0].w.valid <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.user <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.id <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.region <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.qos <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.prot <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.cache <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.lock <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.burst <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.size <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.len <= UInt<1>("h00") - xbar.io.masters[0].aw.bits.addr <= UInt<1>("h00") - xbar.io.masters[0].aw.valid <= UInt<1>("h00") - xbar.io.masters[1].r.ready <= UInt<1>("h00") - xbar.io.masters[1].ar.bits.user <= UInt<1>("h00") - xbar.io.masters[1].ar.bits.id <= UInt<1>("h00") - xbar.io.masters[1].ar.bits.region <= UInt<1>("h00") - xbar.io.masters[1].ar.bits.qos <= UInt<1>("h00") - xbar.io.masters[1].ar.bits.prot <= UInt<1>("h00") - xbar.io.masters[1].ar.bits.cache <= UInt<1>("h00") - xbar.io.masters[1].ar.bits.lock <= UInt<1>("h00") - xbar.io.masters[1].ar.bits.burst <= UInt<1>("h00") - xbar.io.masters[1].ar.bits.size <= UInt<1>("h00") - xbar.io.masters[1].ar.bits.len <= UInt<1>("h00") - xbar.io.masters[1].ar.bits.addr <= UInt<1>("h00") - xbar.io.masters[1].ar.valid <= UInt<1>("h00") - xbar.io.masters[1].b.ready <= UInt<1>("h00") - xbar.io.masters[1].w.bits.user <= UInt<1>("h00") - xbar.io.masters[1].w.bits.strb <= UInt<1>("h00") - xbar.io.masters[1].w.bits.last <= UInt<1>("h00") - xbar.io.masters[1].w.bits.data <= UInt<1>("h00") - xbar.io.masters[1].w.valid <= UInt<1>("h00") - xbar.io.masters[1].aw.bits.user <= UInt<1>("h00") - xbar.io.masters[1].aw.bits.id <= UInt<1>("h00") - xbar.io.masters[1].aw.bits.region <= UInt<1>("h00") - xbar.io.masters[1].aw.bits.qos <= UInt<1>("h00") - xbar.io.masters[1].aw.bits.prot <= UInt<1>("h00") - xbar.io.masters[1].aw.bits.cache <= UInt<1>("h00") - xbar.io.masters[1].aw.bits.lock <= UInt<1>("h00") - xbar.io.masters[1].aw.bits.burst <= UInt<1>("h00") - xbar.io.masters[1].aw.bits.size <= UInt<1>("h00") - xbar.io.masters[1].aw.bits.len <= UInt<1>("h00") - xbar.io.masters[1].aw.bits.addr <= UInt<1>("h00") - xbar.io.masters[1].aw.valid <= UInt<1>("h00") + xbar.io is invalid xbar.clk <= clk xbar.reset <= reset - xbar.io.masters <- io.masters + xbar.io.masters <= io.masters io.slaves[0] <- xbar.io.slaves[0] - inst T_2983 of NastiRecursiveInterconnect_56 - T_2983.io.slaves[0].r.bits.user <= UInt<1>("h00") - T_2983.io.slaves[0].r.bits.id <= UInt<1>("h00") - T_2983.io.slaves[0].r.bits.last <= UInt<1>("h00") - T_2983.io.slaves[0].r.bits.data <= UInt<1>("h00") - T_2983.io.slaves[0].r.bits.resp <= UInt<1>("h00") - T_2983.io.slaves[0].r.valid <= UInt<1>("h00") - T_2983.io.slaves[0].ar.ready <= UInt<1>("h00") - T_2983.io.slaves[0].b.bits.user <= UInt<1>("h00") - T_2983.io.slaves[0].b.bits.id <= UInt<1>("h00") - T_2983.io.slaves[0].b.bits.resp <= UInt<1>("h00") - T_2983.io.slaves[0].b.valid <= UInt<1>("h00") - T_2983.io.slaves[0].w.ready <= UInt<1>("h00") - T_2983.io.slaves[0].aw.ready <= UInt<1>("h00") - T_2983.io.slaves[1].r.bits.user <= UInt<1>("h00") - T_2983.io.slaves[1].r.bits.id <= UInt<1>("h00") - T_2983.io.slaves[1].r.bits.last <= UInt<1>("h00") - T_2983.io.slaves[1].r.bits.data <= UInt<1>("h00") - T_2983.io.slaves[1].r.bits.resp <= UInt<1>("h00") - T_2983.io.slaves[1].r.valid <= UInt<1>("h00") - T_2983.io.slaves[1].ar.ready <= UInt<1>("h00") - T_2983.io.slaves[1].b.bits.user <= UInt<1>("h00") - T_2983.io.slaves[1].b.bits.id <= UInt<1>("h00") - T_2983.io.slaves[1].b.bits.resp <= UInt<1>("h00") - T_2983.io.slaves[1].b.valid <= UInt<1>("h00") - T_2983.io.slaves[1].w.ready <= UInt<1>("h00") - T_2983.io.slaves[1].aw.ready <= UInt<1>("h00") - T_2983.io.slaves[2].r.bits.user <= UInt<1>("h00") - T_2983.io.slaves[2].r.bits.id <= UInt<1>("h00") - T_2983.io.slaves[2].r.bits.last <= UInt<1>("h00") - T_2983.io.slaves[2].r.bits.data <= UInt<1>("h00") - T_2983.io.slaves[2].r.bits.resp <= UInt<1>("h00") - T_2983.io.slaves[2].r.valid <= UInt<1>("h00") - T_2983.io.slaves[2].ar.ready <= UInt<1>("h00") - T_2983.io.slaves[2].b.bits.user <= UInt<1>("h00") - T_2983.io.slaves[2].b.bits.id <= UInt<1>("h00") - T_2983.io.slaves[2].b.bits.resp <= UInt<1>("h00") - T_2983.io.slaves[2].b.valid <= UInt<1>("h00") - T_2983.io.slaves[2].w.ready <= UInt<1>("h00") - T_2983.io.slaves[2].aw.ready <= UInt<1>("h00") - T_2983.io.masters[0].r.ready <= UInt<1>("h00") - T_2983.io.masters[0].ar.bits.user <= UInt<1>("h00") - T_2983.io.masters[0].ar.bits.id <= UInt<1>("h00") - T_2983.io.masters[0].ar.bits.region <= UInt<1>("h00") - T_2983.io.masters[0].ar.bits.qos <= UInt<1>("h00") - T_2983.io.masters[0].ar.bits.prot <= UInt<1>("h00") - T_2983.io.masters[0].ar.bits.cache <= UInt<1>("h00") - T_2983.io.masters[0].ar.bits.lock <= UInt<1>("h00") - T_2983.io.masters[0].ar.bits.burst <= UInt<1>("h00") - T_2983.io.masters[0].ar.bits.size <= UInt<1>("h00") - T_2983.io.masters[0].ar.bits.len <= UInt<1>("h00") - T_2983.io.masters[0].ar.bits.addr <= UInt<1>("h00") - T_2983.io.masters[0].ar.valid <= UInt<1>("h00") - T_2983.io.masters[0].b.ready <= UInt<1>("h00") - T_2983.io.masters[0].w.bits.user <= UInt<1>("h00") - T_2983.io.masters[0].w.bits.strb <= UInt<1>("h00") - T_2983.io.masters[0].w.bits.last <= UInt<1>("h00") - T_2983.io.masters[0].w.bits.data <= UInt<1>("h00") - T_2983.io.masters[0].w.valid <= UInt<1>("h00") - T_2983.io.masters[0].aw.bits.user <= UInt<1>("h00") - T_2983.io.masters[0].aw.bits.id <= UInt<1>("h00") - T_2983.io.masters[0].aw.bits.region <= UInt<1>("h00") - T_2983.io.masters[0].aw.bits.qos <= UInt<1>("h00") - T_2983.io.masters[0].aw.bits.prot <= UInt<1>("h00") - T_2983.io.masters[0].aw.bits.cache <= UInt<1>("h00") - T_2983.io.masters[0].aw.bits.lock <= UInt<1>("h00") - T_2983.io.masters[0].aw.bits.burst <= UInt<1>("h00") - T_2983.io.masters[0].aw.bits.size <= UInt<1>("h00") - T_2983.io.masters[0].aw.bits.len <= UInt<1>("h00") - T_2983.io.masters[0].aw.bits.addr <= UInt<1>("h00") - T_2983.io.masters[0].aw.valid <= UInt<1>("h00") - T_2983.clk <= clk - T_2983.reset <= reset - T_2983.io.masters[0] <- xbar.io.slaves[1] - io.slaves[1] <- T_2983.io.slaves[0] - io.slaves[2] <- T_2983.io.slaves[1] - io.slaves[3] <- T_2983.io.slaves[2] - inst T_3054 of NastiErrorSlave_40 - T_3054.io.r.ready <= UInt<1>("h00") - T_3054.io.ar.bits.user <= UInt<1>("h00") - T_3054.io.ar.bits.id <= UInt<1>("h00") - T_3054.io.ar.bits.region <= UInt<1>("h00") - T_3054.io.ar.bits.qos <= UInt<1>("h00") - T_3054.io.ar.bits.prot <= UInt<1>("h00") - T_3054.io.ar.bits.cache <= UInt<1>("h00") - T_3054.io.ar.bits.lock <= UInt<1>("h00") - T_3054.io.ar.bits.burst <= UInt<1>("h00") - T_3054.io.ar.bits.size <= UInt<1>("h00") - T_3054.io.ar.bits.len <= UInt<1>("h00") - T_3054.io.ar.bits.addr <= UInt<1>("h00") - T_3054.io.ar.valid <= UInt<1>("h00") - T_3054.io.b.ready <= UInt<1>("h00") - T_3054.io.w.bits.user <= UInt<1>("h00") - T_3054.io.w.bits.strb <= UInt<1>("h00") - T_3054.io.w.bits.last <= UInt<1>("h00") - T_3054.io.w.bits.data <= UInt<1>("h00") - T_3054.io.w.valid <= UInt<1>("h00") - T_3054.io.aw.bits.user <= UInt<1>("h00") - T_3054.io.aw.bits.id <= UInt<1>("h00") - T_3054.io.aw.bits.region <= UInt<1>("h00") - T_3054.io.aw.bits.qos <= UInt<1>("h00") - T_3054.io.aw.bits.prot <= UInt<1>("h00") - T_3054.io.aw.bits.cache <= UInt<1>("h00") - T_3054.io.aw.bits.lock <= UInt<1>("h00") - T_3054.io.aw.bits.burst <= UInt<1>("h00") - T_3054.io.aw.bits.size <= UInt<1>("h00") - T_3054.io.aw.bits.len <= UInt<1>("h00") - T_3054.io.aw.bits.addr <= UInt<1>("h00") - T_3054.io.aw.valid <= UInt<1>("h00") - T_3054.clk <= clk - T_3054.reset <= reset - T_3054.io <- xbar.io.slaves[2] + inst T_2869 of NastiRecursiveInterconnect_56 + T_2869.io is invalid + T_2869.clk <= clk + T_2869.reset <= reset + T_2869.io.masters[0] <- xbar.io.slaves[1] + io.slaves[1] <- T_2869.io.slaves[0] + io.slaves[2] <- T_2869.io.slaves[1] + io.slaves[3] <- T_2869.io.slaves[2] + inst T_2870 of NastiErrorSlave_40 + T_2870.io is invalid + T_2870.clk <= clk + T_2870.reset <= reset + T_2870.io <- xbar.io.slaves[2] io.slaves[4] <- xbar.io.slaves[3] module LockingRRArbiter_67 : @@ -15519,55 +11215,46 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, chosen : UInt<1>} - io.chosen <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.bits.union <= UInt<1>("h00") - io.out.bits.a_type <= UInt<1>("h00") - io.out.bits.is_builtin_type <= UInt<1>("h00") - io.out.bits.addr_beat <= UInt<1>("h00") - io.out.bits.client_xact_id <= UInt<1>("h00") - io.out.bits.addr_block <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") - reg T_656 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_658 : UInt<?>, clk, reset, UInt<1>("h01") + io is invalid + reg T_656 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_658 : UInt<?>, clk with : (reset => (reset, UInt<1>("h01"))) wire T_660 : UInt<1> - T_660 <= UInt<1>("h00") + T_660 is invalid io.out.valid <= io.in[T_660].valid io.out.bits <- io.in[T_660].bits io.chosen <= T_660 io.in[T_660].ready <= UInt<1>("h00") - reg last_grant : UInt<1>, clk, reset, UInt<1>("h00") - node T_843 = gt(UInt<1>("h00"), last_grant) - node T_844 = and(io.in[0].valid, T_843) - node T_846 = gt(UInt<1>("h01"), last_grant) - node T_847 = and(io.in[1].valid, T_846) - node T_850 = or(UInt<1>("h00"), T_844) - node T_852 = eq(T_850, UInt<1>("h00")) - node T_854 = or(UInt<1>("h00"), T_844) - node T_855 = or(T_854, T_847) - node T_857 = eq(T_855, UInt<1>("h00")) - node T_859 = or(UInt<1>("h00"), T_844) - node T_860 = or(T_859, T_847) - node T_861 = or(T_860, io.in[0].valid) - node T_863 = eq(T_861, UInt<1>("h00")) - node T_865 = gt(UInt<1>("h00"), last_grant) - node T_866 = and(UInt<1>("h01"), T_865) - node T_867 = or(T_866, T_857) - node T_869 = gt(UInt<1>("h01"), last_grant) - node T_870 = and(T_852, T_869) - node T_871 = or(T_870, T_863) - node T_873 = eq(T_658, UInt<1>("h00")) - node T_874 = mux(T_656, T_873, T_867) - node T_875 = and(T_874, io.out.ready) - io.in[0].ready <= T_875 - node T_877 = eq(T_658, UInt<1>("h01")) - node T_878 = mux(T_656, T_877, T_871) - node T_879 = and(T_878, io.out.ready) - io.in[1].ready <= T_879 - reg T_881 : UInt<2>, clk, reset, UInt<2>("h00") - node T_883 = addw(T_881, UInt<1>("h01")) + reg last_grant : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_842 = gt(UInt<1>("h00"), last_grant) + node T_843 = and(io.in[0].valid, T_842) + node T_845 = gt(UInt<1>("h01"), last_grant) + node T_846 = and(io.in[1].valid, T_845) + node T_849 = or(UInt<1>("h00"), T_843) + node T_851 = eq(T_849, UInt<1>("h00")) + node T_853 = or(UInt<1>("h00"), T_843) + node T_854 = or(T_853, T_846) + node T_856 = eq(T_854, UInt<1>("h00")) + node T_858 = or(UInt<1>("h00"), T_843) + node T_859 = or(T_858, T_846) + node T_860 = or(T_859, io.in[0].valid) + node T_862 = eq(T_860, UInt<1>("h00")) + node T_864 = gt(UInt<1>("h00"), last_grant) + node T_865 = and(UInt<1>("h01"), T_864) + node T_866 = or(T_865, T_856) + node T_868 = gt(UInt<1>("h01"), last_grant) + node T_869 = and(T_851, T_868) + node T_870 = or(T_869, T_862) + node T_872 = eq(T_658, UInt<1>("h00")) + node T_873 = mux(T_656, T_872, T_866) + node T_874 = and(T_873, io.out.ready) + io.in[0].ready <= T_874 + node T_876 = eq(T_658, UInt<1>("h01")) + node T_877 = mux(T_656, T_876, T_870) + node T_878 = and(T_877, io.out.ready) + io.in[1].ready <= T_878 + reg T_880 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + node T_882 = add(T_880, UInt<1>("h01")) + node T_883 = tail(T_882, 1) node T_884 = and(io.out.ready, io.out.valid) when T_884 : node T_886 = and(UInt<1>("h01"), io.out.bits.is_builtin_type) @@ -15577,7 +11264,7 @@ circuit Top : node T_894 = or(UInt<1>("h00"), T_892) node T_895 = and(T_886, T_894) when T_895 : - T_881 <= T_883 + T_880 <= T_883 node T_897 = eq(T_656, UInt<1>("h00")) when T_897 : T_656 <= UInt<1>("h01") @@ -15611,86 +11298,84 @@ circuit Top : input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<1>, tag : UInt<4>}}, deq : {flip valid : UInt<1>, flip tag : UInt<4>, data : UInt<1>, matches : UInt<1>}} - io.deq.matches <= UInt<1>("h00") - io.deq.data <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") - reg roq_data : UInt<1>[9], clk, UInt<1>("h00"), roq_data - reg roq_tags : UInt<4>[9], clk, UInt<1>("h00"), roq_tags - wire T_93 : UInt<1>[9] - T_93[0] <= UInt<1>("h01") - T_93[1] <= UInt<1>("h01") - T_93[2] <= UInt<1>("h01") - T_93[3] <= UInt<1>("h01") - T_93[4] <= UInt<1>("h01") - T_93[5] <= UInt<1>("h01") - T_93[6] <= UInt<1>("h01") - T_93[7] <= UInt<1>("h01") - T_93[8] <= UInt<1>("h01") - reg roq_free : UInt<1>[9], clk, reset, T_93 - node T_126 = mux(roq_free[7], UInt<3>("h07"), UInt<4>("h08")) - node T_127 = mux(roq_free[6], UInt<3>("h06"), T_126) - node T_128 = mux(roq_free[5], UInt<3>("h05"), T_127) - node T_129 = mux(roq_free[4], UInt<3>("h04"), T_128) - node T_130 = mux(roq_free[3], UInt<2>("h03"), T_129) - node T_131 = mux(roq_free[2], UInt<2>("h02"), T_130) - node T_132 = mux(roq_free[1], UInt<1>("h01"), T_131) - node roq_enq_addr = mux(roq_free[0], UInt<1>("h00"), T_132) - node T_134 = eq(roq_tags[0], io.deq.tag) - node T_136 = eq(roq_free[0], UInt<1>("h00")) - node T_137 = and(T_134, T_136) - node T_138 = eq(roq_tags[1], io.deq.tag) - node T_140 = eq(roq_free[1], UInt<1>("h00")) - node T_141 = and(T_138, T_140) - node T_142 = eq(roq_tags[2], io.deq.tag) - node T_144 = eq(roq_free[2], UInt<1>("h00")) - node T_145 = and(T_142, T_144) - node T_146 = eq(roq_tags[3], io.deq.tag) - node T_148 = eq(roq_free[3], UInt<1>("h00")) - node T_149 = and(T_146, T_148) - node T_150 = eq(roq_tags[4], io.deq.tag) - node T_152 = eq(roq_free[4], UInt<1>("h00")) - node T_153 = and(T_150, T_152) - node T_154 = eq(roq_tags[5], io.deq.tag) - node T_156 = eq(roq_free[5], UInt<1>("h00")) - node T_157 = and(T_154, T_156) - node T_158 = eq(roq_tags[6], io.deq.tag) - node T_160 = eq(roq_free[6], UInt<1>("h00")) - node T_161 = and(T_158, T_160) - node T_162 = eq(roq_tags[7], io.deq.tag) - node T_164 = eq(roq_free[7], UInt<1>("h00")) - node T_165 = and(T_162, T_164) - node T_166 = eq(roq_tags[8], io.deq.tag) - node T_168 = eq(roq_free[8], UInt<1>("h00")) - node T_169 = and(T_166, T_168) - node T_179 = mux(T_165, UInt<3>("h07"), UInt<4>("h08")) - node T_180 = mux(T_161, UInt<3>("h06"), T_179) - node T_181 = mux(T_157, UInt<3>("h05"), T_180) - node T_182 = mux(T_153, UInt<3>("h04"), T_181) - node T_183 = mux(T_149, UInt<2>("h03"), T_182) - node T_184 = mux(T_145, UInt<2>("h02"), T_183) - node T_185 = mux(T_141, UInt<1>("h01"), T_184) - node roq_deq_addr = mux(T_137, UInt<1>("h00"), T_185) - node T_187 = or(roq_free[0], roq_free[1]) - node T_188 = or(T_187, roq_free[2]) - node T_189 = or(T_188, roq_free[3]) - node T_190 = or(T_189, roq_free[4]) - node T_191 = or(T_190, roq_free[5]) - node T_192 = or(T_191, roq_free[6]) - node T_193 = or(T_192, roq_free[7]) - node T_194 = or(T_193, roq_free[8]) - io.enq.ready <= T_194 + io is invalid + reg roq_data : UInt<1>[9], clk + reg roq_tags : UInt<4>[9], clk + wire T_96 : UInt<1>[9] + T_96[0] <= UInt<1>("h01") + T_96[1] <= UInt<1>("h01") + T_96[2] <= UInt<1>("h01") + T_96[3] <= UInt<1>("h01") + T_96[4] <= UInt<1>("h01") + T_96[5] <= UInt<1>("h01") + T_96[6] <= UInt<1>("h01") + T_96[7] <= UInt<1>("h01") + T_96[8] <= UInt<1>("h01") + reg roq_free : UInt<1>[9], clk with : (reset => (reset, T_96)) + node T_129 = mux(roq_free[7], UInt<3>("h07"), UInt<4>("h08")) + node T_130 = mux(roq_free[6], UInt<3>("h06"), T_129) + node T_131 = mux(roq_free[5], UInt<3>("h05"), T_130) + node T_132 = mux(roq_free[4], UInt<3>("h04"), T_131) + node T_133 = mux(roq_free[3], UInt<2>("h03"), T_132) + node T_134 = mux(roq_free[2], UInt<2>("h02"), T_133) + node T_135 = mux(roq_free[1], UInt<1>("h01"), T_134) + node roq_enq_addr = mux(roq_free[0], UInt<1>("h00"), T_135) + node T_137 = eq(roq_tags[0], io.deq.tag) + node T_139 = eq(roq_free[0], UInt<1>("h00")) + node T_140 = and(T_137, T_139) + node T_141 = eq(roq_tags[1], io.deq.tag) + node T_143 = eq(roq_free[1], UInt<1>("h00")) + node T_144 = and(T_141, T_143) + node T_145 = eq(roq_tags[2], io.deq.tag) + node T_147 = eq(roq_free[2], UInt<1>("h00")) + node T_148 = and(T_145, T_147) + node T_149 = eq(roq_tags[3], io.deq.tag) + node T_151 = eq(roq_free[3], UInt<1>("h00")) + node T_152 = and(T_149, T_151) + node T_153 = eq(roq_tags[4], io.deq.tag) + node T_155 = eq(roq_free[4], UInt<1>("h00")) + node T_156 = and(T_153, T_155) + node T_157 = eq(roq_tags[5], io.deq.tag) + node T_159 = eq(roq_free[5], UInt<1>("h00")) + node T_160 = and(T_157, T_159) + node T_161 = eq(roq_tags[6], io.deq.tag) + node T_163 = eq(roq_free[6], UInt<1>("h00")) + node T_164 = and(T_161, T_163) + node T_165 = eq(roq_tags[7], io.deq.tag) + node T_167 = eq(roq_free[7], UInt<1>("h00")) + node T_168 = and(T_165, T_167) + node T_169 = eq(roq_tags[8], io.deq.tag) + node T_171 = eq(roq_free[8], UInt<1>("h00")) + node T_172 = and(T_169, T_171) + node T_182 = mux(T_168, UInt<3>("h07"), UInt<4>("h08")) + node T_183 = mux(T_164, UInt<3>("h06"), T_182) + node T_184 = mux(T_160, UInt<3>("h05"), T_183) + node T_185 = mux(T_156, UInt<3>("h04"), T_184) + node T_186 = mux(T_152, UInt<2>("h03"), T_185) + node T_187 = mux(T_148, UInt<2>("h02"), T_186) + node T_188 = mux(T_144, UInt<1>("h01"), T_187) + node roq_deq_addr = mux(T_140, UInt<1>("h00"), T_188) + node T_190 = or(roq_free[0], roq_free[1]) + node T_191 = or(T_190, roq_free[2]) + node T_192 = or(T_191, roq_free[3]) + node T_193 = or(T_192, roq_free[4]) + node T_194 = or(T_193, roq_free[5]) + node T_195 = or(T_194, roq_free[6]) + node T_196 = or(T_195, roq_free[7]) + node T_197 = or(T_196, roq_free[8]) + io.enq.ready <= T_197 io.deq.data <= roq_data[roq_deq_addr] - node T_196 = or(T_137, T_141) - node T_197 = or(T_196, T_145) - node T_198 = or(T_197, T_149) - node T_199 = or(T_198, T_153) - node T_200 = or(T_199, T_157) - node T_201 = or(T_200, T_161) - node T_202 = or(T_201, T_165) - node T_203 = or(T_202, T_169) - io.deq.matches <= T_203 - node T_204 = and(io.enq.valid, io.enq.ready) - when T_204 : + node T_199 = or(T_140, T_144) + node T_200 = or(T_199, T_148) + node T_201 = or(T_200, T_152) + node T_202 = or(T_201, T_156) + node T_203 = or(T_202, T_160) + node T_204 = or(T_203, T_164) + node T_205 = or(T_204, T_168) + node T_206 = or(T_205, T_172) + io.deq.matches <= T_206 + node T_207 = and(io.enq.valid, io.enq.ready) + when T_207 : roq_data[roq_enq_addr] <= io.enq.bits.data roq_tags[roq_enq_addr] <= io.enq.bits.tag roq_free[roq_enq_addr] <= UInt<1>("h00") @@ -15704,241 +11389,171 @@ circuit Top : input reset : UInt<1> output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}} - io.out.grant.ready <= UInt<1>("h00") - io.out.acquire.bits.data <= UInt<1>("h00") - io.out.acquire.bits.union <= UInt<1>("h00") - io.out.acquire.bits.a_type <= UInt<1>("h00") - io.out.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.out.acquire.bits.addr_beat <= UInt<1>("h00") - io.out.acquire.bits.client_xact_id <= UInt<1>("h00") - io.out.acquire.bits.addr_block <= UInt<1>("h00") - io.out.acquire.valid <= UInt<1>("h00") - io.in.release.ready <= UInt<1>("h00") - io.in.probe.bits.p_type <= UInt<1>("h00") - io.in.probe.bits.addr_block <= UInt<1>("h00") - io.in.probe.valid <= UInt<1>("h00") - io.in.grant.bits.data <= UInt<1>("h00") - io.in.grant.bits.g_type <= UInt<1>("h00") - io.in.grant.bits.is_builtin_type <= UInt<1>("h00") - io.in.grant.bits.manager_xact_id <= UInt<1>("h00") - io.in.grant.bits.client_xact_id <= UInt<1>("h00") - io.in.grant.bits.addr_beat <= UInt<1>("h00") - io.in.grant.valid <= UInt<1>("h00") - io.in.acquire.ready <= UInt<1>("h00") + io is invalid inst acqArb of LockingRRArbiter_67 - acqArb.io.out.ready <= UInt<1>("h00") - acqArb.io.in[0].bits.data <= UInt<1>("h00") - acqArb.io.in[0].bits.union <= UInt<1>("h00") - acqArb.io.in[0].bits.a_type <= UInt<1>("h00") - acqArb.io.in[0].bits.is_builtin_type <= UInt<1>("h00") - acqArb.io.in[0].bits.addr_beat <= UInt<1>("h00") - acqArb.io.in[0].bits.client_xact_id <= UInt<1>("h00") - acqArb.io.in[0].bits.addr_block <= UInt<1>("h00") - acqArb.io.in[0].valid <= UInt<1>("h00") - acqArb.io.in[1].bits.data <= UInt<1>("h00") - acqArb.io.in[1].bits.union <= UInt<1>("h00") - acqArb.io.in[1].bits.a_type <= UInt<1>("h00") - acqArb.io.in[1].bits.is_builtin_type <= UInt<1>("h00") - acqArb.io.in[1].bits.addr_beat <= UInt<1>("h00") - acqArb.io.in[1].bits.client_xact_id <= UInt<1>("h00") - acqArb.io.in[1].bits.addr_block <= UInt<1>("h00") - acqArb.io.in[1].valid <= UInt<1>("h00") + acqArb.io is invalid acqArb.clk <= clk acqArb.reset <= reset inst acqRoq of ReorderQueue - acqRoq.io.deq.tag <= UInt<1>("h00") - acqRoq.io.deq.valid <= UInt<1>("h00") - acqRoq.io.enq.bits.tag <= UInt<1>("h00") - acqRoq.io.enq.bits.data <= UInt<1>("h00") - acqRoq.io.enq.valid <= UInt<1>("h00") + acqRoq.io is invalid acqRoq.clk <= clk acqRoq.reset <= reset inst relRoq of ReorderQueue - relRoq.io.deq.tag <= UInt<1>("h00") - relRoq.io.deq.valid <= UInt<1>("h00") - relRoq.io.enq.bits.tag <= UInt<1>("h00") - relRoq.io.enq.bits.data <= UInt<1>("h00") - relRoq.io.enq.valid <= UInt<1>("h00") + relRoq.io is invalid relRoq.clk <= clk relRoq.reset <= reset - node T_1242 = and(UInt<1>("h01"), io.in.acquire.bits.is_builtin_type) - wire T_1245 : UInt<3>[1] - T_1245[0] <= UInt<3>("h03") - node T_1248 = eq(T_1245[0], io.in.acquire.bits.a_type) - node T_1250 = or(UInt<1>("h00"), T_1248) - node T_1251 = and(T_1242, T_1250) - node T_1253 = eq(T_1251, UInt<1>("h00")) - node T_1255 = eq(io.in.acquire.bits.addr_beat, UInt<1>("h00")) - node acq_roq_enq = or(T_1253, T_1255) - wire T_1259 : UInt<2>[3] - T_1259[0] <= UInt<1>("h00") - T_1259[1] <= UInt<1>("h01") - T_1259[2] <= UInt<2>("h02") - node T_1264 = eq(T_1259[0], io.in.release.bits.r_type) - node T_1265 = eq(T_1259[1], io.in.release.bits.r_type) - node T_1266 = eq(T_1259[2], io.in.release.bits.r_type) - node T_1268 = or(UInt<1>("h00"), T_1264) - node T_1269 = or(T_1268, T_1265) - node T_1270 = or(T_1269, T_1266) - node T_1271 = and(UInt<1>("h01"), T_1270) - node T_1273 = eq(T_1271, UInt<1>("h00")) - node T_1275 = eq(io.in.release.bits.addr_beat, UInt<1>("h00")) - node rel_roq_enq = or(T_1273, T_1275) - node T_1278 = eq(acq_roq_enq, UInt<1>("h00")) - node acq_roq_ready = or(T_1278, acqRoq.io.enq.ready) - node T_1281 = eq(rel_roq_enq, UInt<1>("h00")) - node rel_roq_ready = or(T_1281, relRoq.io.enq.ready) - node T_1283 = and(io.in.acquire.valid, acqArb.io.in[0].ready) - node T_1284 = and(T_1283, acq_roq_enq) - acqRoq.io.enq.valid <= T_1284 + node T_1215 = and(UInt<1>("h01"), io.in.acquire.bits.is_builtin_type) + wire T_1218 : UInt<3>[1] + T_1218[0] <= UInt<3>("h03") + node T_1221 = eq(T_1218[0], io.in.acquire.bits.a_type) + node T_1223 = or(UInt<1>("h00"), T_1221) + node T_1224 = and(T_1215, T_1223) + node T_1226 = eq(T_1224, UInt<1>("h00")) + node T_1228 = eq(io.in.acquire.bits.addr_beat, UInt<1>("h00")) + node acq_roq_enq = or(T_1226, T_1228) + wire T_1232 : UInt<2>[3] + T_1232[0] <= UInt<1>("h00") + T_1232[1] <= UInt<1>("h01") + T_1232[2] <= UInt<2>("h02") + node T_1237 = eq(T_1232[0], io.in.release.bits.r_type) + node T_1238 = eq(T_1232[1], io.in.release.bits.r_type) + node T_1239 = eq(T_1232[2], io.in.release.bits.r_type) + node T_1241 = or(UInt<1>("h00"), T_1237) + node T_1242 = or(T_1241, T_1238) + node T_1243 = or(T_1242, T_1239) + node T_1244 = and(UInt<1>("h01"), T_1243) + node T_1246 = eq(T_1244, UInt<1>("h00")) + node T_1248 = eq(io.in.release.bits.addr_beat, UInt<1>("h00")) + node rel_roq_enq = or(T_1246, T_1248) + node T_1251 = eq(acq_roq_enq, UInt<1>("h00")) + node acq_roq_ready = or(T_1251, acqRoq.io.enq.ready) + node T_1254 = eq(rel_roq_enq, UInt<1>("h00")) + node rel_roq_ready = or(T_1254, relRoq.io.enq.ready) + node T_1256 = and(io.in.acquire.valid, acqArb.io.in[0].ready) + node T_1257 = and(T_1256, acq_roq_enq) + acqRoq.io.enq.valid <= T_1257 acqRoq.io.enq.bits.data <= io.in.acquire.bits.is_builtin_type acqRoq.io.enq.bits.tag <= io.in.acquire.bits.client_xact_id - node T_1285 = and(io.in.acquire.valid, acq_roq_ready) - acqArb.io.in[0].valid <= T_1285 - node T_1288 = mux(io.in.acquire.bits.is_builtin_type, io.in.acquire.bits.a_type, UInt<3>("h01")) - node T_1290 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1291 = cat(UInt<3>("h07"), T_1290) - node T_1292 = mux(io.in.acquire.bits.is_builtin_type, io.in.acquire.bits.union, T_1291) - wire T_1321 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1321.data <= UInt<1>("h00") - T_1321.union <= UInt<1>("h00") - T_1321.a_type <= UInt<1>("h00") - T_1321.is_builtin_type <= UInt<1>("h00") - T_1321.addr_beat <= UInt<1>("h00") - T_1321.client_xact_id <= UInt<1>("h00") - T_1321.addr_block <= UInt<1>("h00") - T_1321.is_builtin_type <= UInt<1>("h01") - T_1321.a_type <= T_1288 - T_1321.client_xact_id <= io.in.acquire.bits.client_xact_id - T_1321.addr_block <= io.in.acquire.bits.addr_block - T_1321.addr_beat <= io.in.acquire.bits.addr_beat - T_1321.data <= io.in.acquire.bits.data - T_1321.union <= T_1292 - acqArb.io.in[0].bits <- T_1321 - node T_1356 = and(acq_roq_ready, acqArb.io.in[0].ready) - io.in.acquire.ready <= T_1356 - node T_1357 = and(io.in.release.valid, acqArb.io.in[1].ready) - node T_1358 = and(T_1357, rel_roq_enq) - relRoq.io.enq.valid <= T_1358 + node T_1258 = and(io.in.acquire.valid, acq_roq_ready) + acqArb.io.in[0].valid <= T_1258 + node T_1261 = mux(io.in.acquire.bits.is_builtin_type, io.in.acquire.bits.a_type, UInt<3>("h01")) + node T_1263 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1264 = cat(UInt<3>("h07"), T_1263) + node T_1265 = mux(io.in.acquire.bits.is_builtin_type, io.in.acquire.bits.union, T_1264) + wire T_1294 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} + T_1294 is invalid + T_1294.is_builtin_type <= UInt<1>("h01") + T_1294.a_type <= T_1261 + T_1294.client_xact_id <= io.in.acquire.bits.client_xact_id + T_1294.addr_block <= io.in.acquire.bits.addr_block + T_1294.addr_beat <= io.in.acquire.bits.addr_beat + T_1294.data <= io.in.acquire.bits.data + T_1294.union <= T_1265 + acqArb.io.in[0].bits <- T_1294 + node T_1322 = and(acq_roq_ready, acqArb.io.in[0].ready) + io.in.acquire.ready <= T_1322 + node T_1323 = and(io.in.release.valid, acqArb.io.in[1].ready) + node T_1324 = and(T_1323, rel_roq_enq) + relRoq.io.enq.valid <= T_1324 relRoq.io.enq.bits.data <= io.in.release.bits.voluntary relRoq.io.enq.bits.tag <= io.in.release.bits.client_xact_id - node T_1359 = and(io.in.release.valid, rel_roq_ready) - acqArb.io.in[1].valid <= T_1359 - node T_1381 = asUInt(asSInt(UInt<16>("h0ffff"))) - node T_1389 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1390 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1391 = cat(T_1389, T_1390) - node T_1393 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1394 = cat(UInt<3>("h07"), T_1393) - node T_1396 = cat(T_1381, UInt<1>("h01")) - node T_1398 = cat(T_1381, UInt<1>("h01")) - node T_1400 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1401 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1402 = cat(T_1400, T_1401) - node T_1404 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1406 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1407 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_1408 = mux(T_1407, T_1406, UInt<1>("h00")) - node T_1409 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_1410 = mux(T_1409, T_1404, T_1408) - node T_1411 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_1412 = mux(T_1411, T_1402, T_1410) - node T_1413 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_1414 = mux(T_1413, T_1398, T_1412) - node T_1415 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_1416 = mux(T_1415, T_1396, T_1414) - node T_1417 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_1418 = mux(T_1417, T_1394, T_1416) - node T_1419 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_1420 = mux(T_1419, T_1391, T_1418) - wire T_1449 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1449.data <= UInt<1>("h00") - T_1449.union <= UInt<1>("h00") - T_1449.a_type <= UInt<1>("h00") - T_1449.is_builtin_type <= UInt<1>("h00") - T_1449.addr_beat <= UInt<1>("h00") - T_1449.client_xact_id <= UInt<1>("h00") - T_1449.addr_block <= UInt<1>("h00") - T_1449.is_builtin_type <= UInt<1>("h01") - T_1449.a_type <= UInt<3>("h03") - T_1449.client_xact_id <= io.in.release.bits.client_xact_id - T_1449.addr_block <= io.in.release.bits.addr_block - T_1449.addr_beat <= io.in.release.bits.addr_beat - T_1449.data <= io.in.release.bits.data - T_1449.union <= T_1420 - acqArb.io.in[1].bits <- T_1449 - node T_1484 = and(rel_roq_ready, acqArb.io.in[1].ready) - io.in.release.ready <= T_1484 + node T_1325 = and(io.in.release.valid, rel_roq_ready) + acqArb.io.in[1].valid <= T_1325 + node T_1347 = asUInt(asSInt(UInt<16>("h0ffff"))) + node T_1355 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_1356 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_1357 = cat(T_1355, T_1356) + node T_1359 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_1360 = cat(UInt<3>("h07"), T_1359) + node T_1362 = cat(T_1347, UInt<1>("h01")) + node T_1364 = cat(T_1347, UInt<1>("h01")) + node T_1366 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_1367 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_1368 = cat(T_1366, T_1367) + node T_1370 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1372 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_1373 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_1374 = mux(T_1373, T_1372, UInt<1>("h00")) + node T_1375 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_1376 = mux(T_1375, T_1370, T_1374) + node T_1377 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_1378 = mux(T_1377, T_1368, T_1376) + node T_1379 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_1380 = mux(T_1379, T_1364, T_1378) + node T_1381 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_1382 = mux(T_1381, T_1362, T_1380) + node T_1383 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_1384 = mux(T_1383, T_1360, T_1382) + node T_1385 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_1386 = mux(T_1385, T_1357, T_1384) + wire T_1415 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} + T_1415 is invalid + T_1415.is_builtin_type <= UInt<1>("h01") + T_1415.a_type <= UInt<3>("h03") + T_1415.client_xact_id <= io.in.release.bits.client_xact_id + T_1415.addr_block <= io.in.release.bits.addr_block + T_1415.addr_beat <= io.in.release.bits.addr_beat + T_1415.data <= io.in.release.bits.data + T_1415.union <= T_1386 + acqArb.io.in[1].bits <- T_1415 + node T_1443 = and(rel_roq_ready, acqArb.io.in[1].ready) + io.in.release.ready <= T_1443 io.out.acquire <- acqArb.io.out - node T_1485 = and(io.out.grant.ready, io.out.grant.valid) - wire T_1489 : UInt<3>[1] - T_1489[0] <= UInt<3>("h05") - node T_1492 = eq(T_1489[0], io.out.grant.bits.g_type) - node T_1494 = or(UInt<1>("h00"), T_1492) - wire T_1496 : UInt<1>[1] - T_1496[0] <= UInt<1>("h00") - node T_1499 = eq(T_1496[0], io.out.grant.bits.g_type) - node T_1501 = or(UInt<1>("h00"), T_1499) - node T_1502 = mux(io.out.grant.bits.is_builtin_type, T_1494, T_1501) - node T_1503 = and(UInt<1>("h01"), T_1502) - node T_1505 = eq(T_1503, UInt<1>("h00")) - node T_1507 = eq(io.out.grant.bits.addr_beat, UInt<2>("h03")) - node T_1508 = or(T_1505, T_1507) - node T_1509 = and(T_1485, T_1508) - acqRoq.io.deq.valid <= T_1509 + node T_1444 = and(io.out.grant.ready, io.out.grant.valid) + wire T_1448 : UInt<3>[1] + T_1448[0] <= UInt<3>("h05") + node T_1451 = eq(T_1448[0], io.out.grant.bits.g_type) + node T_1453 = or(UInt<1>("h00"), T_1451) + wire T_1455 : UInt<1>[1] + T_1455[0] <= UInt<1>("h00") + node T_1458 = eq(T_1455[0], io.out.grant.bits.g_type) + node T_1460 = or(UInt<1>("h00"), T_1458) + node T_1461 = mux(io.out.grant.bits.is_builtin_type, T_1453, T_1460) + node T_1462 = and(UInt<1>("h01"), T_1461) + node T_1464 = eq(T_1462, UInt<1>("h00")) + node T_1466 = eq(io.out.grant.bits.addr_beat, UInt<2>("h03")) + node T_1467 = or(T_1464, T_1466) + node T_1468 = and(T_1444, T_1467) + acqRoq.io.deq.valid <= T_1468 acqRoq.io.deq.tag <= io.out.grant.bits.client_xact_id - node T_1510 = and(io.out.grant.ready, io.out.grant.valid) - wire T_1514 : UInt<3>[1] - T_1514[0] <= UInt<3>("h05") - node T_1517 = eq(T_1514[0], io.out.grant.bits.g_type) - node T_1519 = or(UInt<1>("h00"), T_1517) - wire T_1521 : UInt<1>[1] - T_1521[0] <= UInt<1>("h00") - node T_1524 = eq(T_1521[0], io.out.grant.bits.g_type) - node T_1526 = or(UInt<1>("h00"), T_1524) - node T_1527 = mux(io.out.grant.bits.is_builtin_type, T_1519, T_1526) - node T_1528 = and(UInt<1>("h01"), T_1527) - node T_1530 = eq(T_1528, UInt<1>("h00")) - node T_1532 = eq(io.out.grant.bits.addr_beat, UInt<2>("h03")) - node T_1533 = or(T_1530, T_1532) - node T_1534 = and(T_1510, T_1533) - relRoq.io.deq.valid <= T_1534 + node T_1469 = and(io.out.grant.ready, io.out.grant.valid) + wire T_1473 : UInt<3>[1] + T_1473[0] <= UInt<3>("h05") + node T_1476 = eq(T_1473[0], io.out.grant.bits.g_type) + node T_1478 = or(UInt<1>("h00"), T_1476) + wire T_1480 : UInt<1>[1] + T_1480[0] <= UInt<1>("h00") + node T_1483 = eq(T_1480[0], io.out.grant.bits.g_type) + node T_1485 = or(UInt<1>("h00"), T_1483) + node T_1486 = mux(io.out.grant.bits.is_builtin_type, T_1478, T_1485) + node T_1487 = and(UInt<1>("h01"), T_1486) + node T_1489 = eq(T_1487, UInt<1>("h00")) + node T_1491 = eq(io.out.grant.bits.addr_beat, UInt<2>("h03")) + node T_1492 = or(T_1489, T_1491) + node T_1493 = and(T_1469, T_1492) + relRoq.io.deq.valid <= T_1493 relRoq.io.deq.tag <= io.out.grant.bits.client_xact_id - node T_1535 = mux(acqRoq.io.deq.data, io.out.grant.bits.g_type, UInt<1>("h00")) + node T_1494 = mux(acqRoq.io.deq.data, io.out.grant.bits.g_type, UInt<1>("h00")) wire acq_grant : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - acq_grant.data <= UInt<1>("h00") - acq_grant.g_type <= UInt<1>("h00") - acq_grant.is_builtin_type <= UInt<1>("h00") - acq_grant.manager_xact_id <= UInt<1>("h00") - acq_grant.client_xact_id <= UInt<1>("h00") - acq_grant.addr_beat <= UInt<1>("h00") + acq_grant is invalid acq_grant.is_builtin_type <= acqRoq.io.deq.data - acq_grant.g_type <= T_1535 + acq_grant.g_type <= T_1494 acq_grant.client_xact_id <= io.out.grant.bits.client_xact_id acq_grant.manager_xact_id <= io.out.grant.bits.manager_xact_id acq_grant.addr_beat <= io.out.grant.bits.addr_beat acq_grant.data <= io.out.grant.bits.data - node T_1598 = mux(relRoq.io.deq.data, UInt<3>("h00"), io.out.grant.bits.g_type) + node T_1551 = mux(relRoq.io.deq.data, UInt<3>("h00"), io.out.grant.bits.g_type) wire rel_grant : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - rel_grant.data <= UInt<1>("h00") - rel_grant.g_type <= UInt<1>("h00") - rel_grant.is_builtin_type <= UInt<1>("h00") - rel_grant.manager_xact_id <= UInt<1>("h00") - rel_grant.client_xact_id <= UInt<1>("h00") - rel_grant.addr_beat <= UInt<1>("h00") + rel_grant is invalid rel_grant.is_builtin_type <= UInt<1>("h01") - rel_grant.g_type <= T_1598 + rel_grant.g_type <= T_1551 rel_grant.client_xact_id <= io.out.grant.bits.client_xact_id rel_grant.manager_xact_id <= io.out.grant.bits.manager_xact_id rel_grant.addr_beat <= io.out.grant.bits.addr_beat rel_grant.data <= io.out.grant.bits.data io.in.grant.valid <= io.out.grant.valid - wire T_1686 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - T_1686 <- rel_grant - when acqRoq.io.deq.matches : - T_1686 <- acq_grant - skip - io.in.grant.bits <- T_1686 + node T_1606 = mux(acqRoq.io.deq.matches, acq_grant, rel_grant) + io.in.grant.bits <- T_1606 io.out.grant.ready <= io.in.grant.ready io.in.probe.valid <= UInt<1>("h00") @@ -15947,33 +11562,17 @@ circuit Top : input reset : UInt<1> output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}} - io.out.grant.ready <= UInt<1>("h00") - io.out.acquire.bits.data <= UInt<1>("h00") - io.out.acquire.bits.union <= UInt<1>("h00") - io.out.acquire.bits.a_type <= UInt<1>("h00") - io.out.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.out.acquire.bits.addr_beat <= UInt<1>("h00") - io.out.acquire.bits.client_xact_id <= UInt<1>("h00") - io.out.acquire.bits.addr_block <= UInt<1>("h00") - io.out.acquire.valid <= UInt<1>("h00") - io.in.grant.bits.data <= UInt<1>("h00") - io.in.grant.bits.g_type <= UInt<1>("h00") - io.in.grant.bits.is_builtin_type <= UInt<1>("h00") - io.in.grant.bits.manager_xact_id <= UInt<1>("h00") - io.in.grant.bits.client_xact_id <= UInt<1>("h00") - io.in.grant.bits.addr_beat <= UInt<1>("h00") - io.in.grant.valid <= UInt<1>("h00") - io.in.acquire.ready <= UInt<1>("h00") + io is invalid node T_815 = eq(io.in.acquire.bits.a_type, UInt<3>("h03")) node T_817 = eq(io.in.acquire.bits.a_type, UInt<3>("h01")) node T_819 = eq(io.in.acquire.bits.a_type, UInt<3>("h02")) node T_821 = eq(io.in.acquire.bits.a_type, UInt<3>("h00")) - reg T_823 : UInt<128>, clk, UInt<1>("h00"), T_823 - reg T_825 : UInt<16>, clk, UInt<1>("h00"), T_825 - reg T_826 : UInt<4>, clk, UInt<1>("h00"), T_826 - reg T_827 : UInt<26>, clk, UInt<1>("h00"), T_827 - reg T_828 : UInt<2>, clk, UInt<1>("h00"), T_828 - reg T_830 : UInt<1>, clk, reset, UInt<1>("h00") + reg T_823 : UInt<128>, clk + reg T_825 : UInt<16>, clk + reg T_826 : UInt<4>, clk + reg T_827 : UInt<26>, clk + reg T_828 : UInt<2>, clk + reg T_830 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node T_831 = bits(io.in.acquire.bits.union, 12, 9) node T_832 = cat(io.in.acquire.bits.addr_beat, T_831) node T_833 = cat(io.in.acquire.bits.addr_block, T_832) @@ -15991,505 +11590,453 @@ circuit Top : node T_846 = dshl(UInt<1>("h01"), T_844) node T_848 = eq(io.in.acquire.bits.a_type, UInt<3>("h04")) node T_849 = and(io.in.acquire.bits.is_builtin_type, T_848) - node T_850 = bit(T_846, 0) - node T_851 = bit(T_846, 1) + node T_850 = bits(T_846, 0, 0) + node T_851 = bits(T_846, 1, 1) wire T_853 : UInt<1>[2] T_853[0] <= T_850 T_853[1] <= T_851 - node T_858 = subw(UInt<8>("h00"), T_853[0]) - node T_860 = subw(UInt<8>("h00"), T_853[1]) - wire T_862 : UInt<8>[2] - T_862[0] <= T_858 - T_862[1] <= T_860 - node T_866 = cat(T_862[1], T_862[0]) - node T_868 = eq(io.in.acquire.bits.a_type, UInt<3>("h03")) - node T_869 = and(io.in.acquire.bits.is_builtin_type, T_868) - node T_871 = eq(io.in.acquire.bits.a_type, UInt<3>("h02")) - node T_872 = and(io.in.acquire.bits.is_builtin_type, T_871) - node T_873 = or(T_869, T_872) - node T_874 = bits(io.in.acquire.bits.union, 16, 1) - node T_876 = mux(T_873, T_874, UInt<16>("h00")) - node T_877 = mux(T_849, T_866, T_876) - node T_878 = bits(T_877, 7, 0) - node T_879 = bits(io.in.acquire.bits.union, 12, 9) - node T_880 = bits(T_879, 3, 3) - node T_882 = dshl(UInt<1>("h01"), T_880) - node T_884 = eq(io.in.acquire.bits.a_type, UInt<3>("h04")) - node T_885 = and(io.in.acquire.bits.is_builtin_type, T_884) - node T_886 = bit(T_882, 0) - node T_887 = bit(T_882, 1) - wire T_889 : UInt<1>[2] - T_889[0] <= T_886 - T_889[1] <= T_887 - node T_894 = subw(UInt<8>("h00"), T_889[0]) - node T_896 = subw(UInt<8>("h00"), T_889[1]) - wire T_898 : UInt<8>[2] - T_898[0] <= T_894 - T_898[1] <= T_896 - node T_902 = cat(T_898[1], T_898[0]) - node T_904 = eq(io.in.acquire.bits.a_type, UInt<3>("h03")) - node T_905 = and(io.in.acquire.bits.is_builtin_type, T_904) - node T_907 = eq(io.in.acquire.bits.a_type, UInt<3>("h02")) - node T_908 = and(io.in.acquire.bits.is_builtin_type, T_907) - node T_909 = or(T_905, T_908) - node T_910 = bits(io.in.acquire.bits.union, 16, 1) - node T_912 = mux(T_909, T_910, UInt<16>("h00")) - node T_913 = mux(T_885, T_902, T_912) - node T_914 = bits(T_913, 15, 8) - wire T_916 : UInt<8>[2] - T_916[0] <= T_878 - T_916[1] <= T_914 - node T_920 = bits(io.in.acquire.bits.data, 63, 0) - node T_921 = bits(io.in.acquire.bits.data, 127, 64) - wire T_923 : UInt<64>[2] - T_923[0] <= T_920 - T_923[1] <= T_921 - node T_928 = neq(T_916[0], UInt<1>("h00")) - node T_930 = neq(T_916[1], UInt<1>("h00")) - node T_931 = cat(T_930, T_928) - node T_932 = bit(T_931, 0) - node T_933 = bit(T_931, 1) - node T_935 = mux(T_932, T_923[0], UInt<1>("h00")) - node T_937 = mux(T_933, T_923[1], UInt<1>("h00")) - node T_939 = or(T_935, T_937) - wire T_940 : UInt<64> - T_940 <= UInt<1>("h00") - T_940 <= T_939 - node T_942 = bit(T_931, 0) - node T_943 = bit(T_931, 1) - node T_945 = mux(T_942, T_916[0], UInt<1>("h00")) - node T_947 = mux(T_943, T_916[1], UInt<1>("h00")) - node T_949 = or(T_945, T_947) - wire T_950 : UInt<8> - T_950 <= UInt<1>("h00") - T_950 <= T_949 - node T_952 = bit(T_931, 0) - node T_953 = bit(T_931, 1) - wire T_955 : UInt<1>[2] - T_955[0] <= T_952 - T_955[1] <= T_953 - node T_961 = mux(T_955[0], UInt<1>("h00"), UInt<1>("h01")) - node T_962 = cat(io.in.acquire.bits.addr_beat, T_961) - node T_964 = eq(io.in.acquire.valid, UInt<1>("h00")) - node T_966 = eq(T_819, UInt<1>("h00")) - node T_967 = or(T_964, T_966) - node T_968 = bit(T_931, 0) - node T_969 = bit(T_931, 1) - node T_971 = cat(UInt<1>("h00"), T_969) - node T_972 = addw(T_968, T_971) - node T_974 = leq(T_972, UInt<1>("h01")) - node T_975 = or(T_967, T_974) - node T_977 = eq(reset, UInt<1>("h00")) - when T_977 : - node T_979 = eq(T_975, UInt<1>("h00")) - when T_979 : - node T_981 = eq(reset, UInt<1>("h00")) - when T_981 : + node T_858 = sub(UInt<8>("h00"), T_853[0]) + node T_859 = tail(T_858, 1) + node T_861 = sub(UInt<8>("h00"), T_853[1]) + node T_862 = tail(T_861, 1) + wire T_864 : UInt<8>[2] + T_864[0] <= T_859 + T_864[1] <= T_862 + node T_868 = cat(T_864[1], T_864[0]) + node T_870 = eq(io.in.acquire.bits.a_type, UInt<3>("h03")) + node T_871 = and(io.in.acquire.bits.is_builtin_type, T_870) + node T_873 = eq(io.in.acquire.bits.a_type, UInt<3>("h02")) + node T_874 = and(io.in.acquire.bits.is_builtin_type, T_873) + node T_875 = or(T_871, T_874) + node T_876 = bits(io.in.acquire.bits.union, 16, 1) + node T_878 = mux(T_875, T_876, UInt<16>("h00")) + node T_879 = mux(T_849, T_868, T_878) + node T_880 = bits(T_879, 7, 0) + node T_881 = bits(io.in.acquire.bits.union, 12, 9) + node T_882 = bits(T_881, 3, 3) + node T_884 = dshl(UInt<1>("h01"), T_882) + node T_886 = eq(io.in.acquire.bits.a_type, UInt<3>("h04")) + node T_887 = and(io.in.acquire.bits.is_builtin_type, T_886) + node T_888 = bits(T_884, 0, 0) + node T_889 = bits(T_884, 1, 1) + wire T_891 : UInt<1>[2] + T_891[0] <= T_888 + T_891[1] <= T_889 + node T_896 = sub(UInt<8>("h00"), T_891[0]) + node T_897 = tail(T_896, 1) + node T_899 = sub(UInt<8>("h00"), T_891[1]) + node T_900 = tail(T_899, 1) + wire T_902 : UInt<8>[2] + T_902[0] <= T_897 + T_902[1] <= T_900 + node T_906 = cat(T_902[1], T_902[0]) + node T_908 = eq(io.in.acquire.bits.a_type, UInt<3>("h03")) + node T_909 = and(io.in.acquire.bits.is_builtin_type, T_908) + node T_911 = eq(io.in.acquire.bits.a_type, UInt<3>("h02")) + node T_912 = and(io.in.acquire.bits.is_builtin_type, T_911) + node T_913 = or(T_909, T_912) + node T_914 = bits(io.in.acquire.bits.union, 16, 1) + node T_916 = mux(T_913, T_914, UInt<16>("h00")) + node T_917 = mux(T_887, T_906, T_916) + node T_918 = bits(T_917, 15, 8) + wire T_920 : UInt<8>[2] + T_920[0] <= T_880 + T_920[1] <= T_918 + node T_924 = bits(io.in.acquire.bits.data, 63, 0) + node T_925 = bits(io.in.acquire.bits.data, 127, 64) + wire T_927 : UInt<64>[2] + T_927[0] <= T_924 + T_927[1] <= T_925 + node T_932 = neq(T_920[0], UInt<1>("h00")) + node T_934 = neq(T_920[1], UInt<1>("h00")) + node T_935 = cat(T_934, T_932) + node T_936 = bits(T_935, 0, 0) + node T_937 = bits(T_935, 1, 1) + node T_939 = mux(T_936, T_927[0], UInt<1>("h00")) + node T_941 = mux(T_937, T_927[1], UInt<1>("h00")) + node T_943 = or(T_939, T_941) + wire T_944 : UInt<64> + T_944 is invalid + T_944 <= T_943 + node T_945 = bits(T_935, 0, 0) + node T_946 = bits(T_935, 1, 1) + node T_948 = mux(T_945, T_920[0], UInt<1>("h00")) + node T_950 = mux(T_946, T_920[1], UInt<1>("h00")) + node T_952 = or(T_948, T_950) + wire T_953 : UInt<8> + T_953 is invalid + T_953 <= T_952 + node T_954 = bits(T_935, 0, 0) + node T_955 = bits(T_935, 1, 1) + wire T_957 : UInt<1>[2] + T_957[0] <= T_954 + T_957[1] <= T_955 + node T_963 = mux(T_957[0], UInt<1>("h00"), UInt<1>("h01")) + node T_964 = cat(io.in.acquire.bits.addr_beat, T_963) + node T_966 = eq(io.in.acquire.valid, UInt<1>("h00")) + node T_968 = eq(T_819, UInt<1>("h00")) + node T_969 = or(T_966, T_968) + node T_970 = bits(T_935, 0, 0) + node T_971 = bits(T_935, 1, 1) + node T_973 = cat(UInt<1>("h00"), T_971) + node T_974 = add(T_970, T_973) + node T_975 = tail(T_974, 1) + node T_977 = leq(T_975, UInt<1>("h01")) + node T_978 = or(T_969, T_977) + node T_980 = eq(reset, UInt<1>("h00")) + when T_980 : + node T_982 = eq(T_978, UInt<1>("h00")) + when T_982 : + node T_984 = eq(reset, UInt<1>("h00")) + when T_984 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Can't perform Put wider than outer width") skip stop(clk, UInt<1>(1), 1) skip skip - node T_982 = bits(io.in.acquire.bits.union, 8, 6) - node T_991 = eq(UInt<3>("h07"), T_982) - node T_992 = mux(T_991, UInt<1>("h00"), UInt<1>("h00")) - node T_993 = eq(UInt<3>("h03"), T_982) - node T_994 = mux(T_993, UInt<1>("h01"), T_992) - node T_995 = eq(UInt<3>("h02"), T_982) - node T_996 = mux(T_995, UInt<1>("h01"), T_994) - node T_997 = eq(UInt<3>("h05"), T_982) - node T_998 = mux(T_997, UInt<1>("h01"), T_996) - node T_999 = eq(UInt<3>("h01"), T_982) - node T_1000 = mux(T_999, UInt<1>("h01"), T_998) - node T_1001 = eq(UInt<3>("h04"), T_982) - node T_1002 = mux(T_1001, UInt<1>("h01"), T_1000) - node T_1003 = eq(UInt<3>("h00"), T_982) - node T_1004 = mux(T_1003, UInt<1>("h01"), T_1002) - node T_1006 = eq(io.in.acquire.valid, UInt<1>("h00")) - node T_1008 = eq(T_821, UInt<1>("h00")) - node T_1009 = or(T_1006, T_1008) - node T_1010 = or(T_1009, T_1004) - node T_1012 = eq(reset, UInt<1>("h00")) - when T_1012 : - node T_1014 = eq(T_1010, UInt<1>("h00")) - when T_1014 : - node T_1016 = eq(reset, UInt<1>("h00")) - when T_1016 : + node T_985 = bits(io.in.acquire.bits.union, 8, 6) + node T_994 = eq(UInt<3>("h07"), T_985) + node T_995 = mux(T_994, UInt<1>("h00"), UInt<1>("h00")) + node T_996 = eq(UInt<3>("h03"), T_985) + node T_997 = mux(T_996, UInt<1>("h01"), T_995) + node T_998 = eq(UInt<3>("h02"), T_985) + node T_999 = mux(T_998, UInt<1>("h01"), T_997) + node T_1000 = eq(UInt<3>("h05"), T_985) + node T_1001 = mux(T_1000, UInt<1>("h01"), T_999) + node T_1002 = eq(UInt<3>("h01"), T_985) + node T_1003 = mux(T_1002, UInt<1>("h01"), T_1001) + node T_1004 = eq(UInt<3>("h04"), T_985) + node T_1005 = mux(T_1004, UInt<1>("h01"), T_1003) + node T_1006 = eq(UInt<3>("h00"), T_985) + node T_1007 = mux(T_1006, UInt<1>("h01"), T_1005) + node T_1009 = eq(io.in.acquire.valid, UInt<1>("h00")) + node T_1011 = eq(T_821, UInt<1>("h00")) + node T_1012 = or(T_1009, T_1011) + node T_1013 = or(T_1012, T_1007) + node T_1015 = eq(reset, UInt<1>("h00")) + when T_1015 : + node T_1017 = eq(T_1013, UInt<1>("h00")) + when T_1017 : + node T_1019 = eq(reset, UInt<1>("h00")) + when T_1019 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Can't perform Get wider than outer width") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1017 = bit(io.in.acquire.bits.union, 0) - node T_1026 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1027 = cat(UInt<5>("h00"), T_1017) - node T_1028 = cat(T_1026, T_1027) - node T_1030 = cat(UInt<5>("h00"), T_1017) - node T_1031 = cat(UInt<3>("h07"), T_1030) - node T_1033 = cat(UInt<1>("h00"), T_1017) - node T_1035 = cat(UInt<1>("h00"), T_1017) - node T_1037 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1038 = cat(UInt<5>("h00"), T_1017) - node T_1039 = cat(T_1037, T_1038) - node T_1041 = cat(UInt<5>("h00"), T_1017) - node T_1043 = cat(UInt<5>("h01"), T_1017) - node T_1044 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_1045 = mux(T_1044, T_1043, UInt<1>("h00")) - node T_1046 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_1047 = mux(T_1046, T_1041, T_1045) - node T_1048 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_1049 = mux(T_1048, T_1039, T_1047) - node T_1050 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_1051 = mux(T_1050, T_1035, T_1049) - node T_1052 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_1053 = mux(T_1052, T_1033, T_1051) - node T_1054 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_1055 = mux(T_1054, T_1031, T_1053) - node T_1056 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_1057 = mux(T_1056, T_1028, T_1055) - wire T_1086 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1086.data <= UInt<1>("h00") - T_1086.union <= UInt<1>("h00") - T_1086.a_type <= UInt<1>("h00") - T_1086.is_builtin_type <= UInt<1>("h00") - T_1086.addr_beat <= UInt<1>("h00") - T_1086.client_xact_id <= UInt<1>("h00") - T_1086.addr_block <= UInt<1>("h00") - T_1086.is_builtin_type <= UInt<1>("h01") - T_1086.a_type <= UInt<3>("h01") - T_1086.client_xact_id <= io.in.acquire.bits.client_xact_id - T_1086.addr_block <= io.in.acquire.bits.addr_block - T_1086.addr_beat <= UInt<1>("h00") - T_1086.data <= UInt<1>("h00") - T_1086.union <= T_1057 - node T_1121 = cat(T_828, T_830) - node T_1122 = bits(T_823, 63, 0) - node T_1123 = bits(T_825, 7, 0) - node T_1131 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1132 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1133 = cat(T_1131, T_1132) - node T_1135 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1136 = cat(UInt<3>("h07"), T_1135) - node T_1138 = cat(T_1123, UInt<1>("h01")) - node T_1140 = cat(T_1123, UInt<1>("h01")) - node T_1142 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1143 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1144 = cat(T_1142, T_1143) - node T_1146 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1148 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1149 = eq(UInt<3>("h06"), UInt<3>("h03")) - node T_1150 = mux(T_1149, T_1148, UInt<1>("h00")) - node T_1151 = eq(UInt<3>("h05"), UInt<3>("h03")) - node T_1152 = mux(T_1151, T_1146, T_1150) - node T_1153 = eq(UInt<3>("h04"), UInt<3>("h03")) - node T_1154 = mux(T_1153, T_1144, T_1152) - node T_1155 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_1156 = mux(T_1155, T_1140, T_1154) - node T_1157 = eq(UInt<3>("h02"), UInt<3>("h03")) - node T_1158 = mux(T_1157, T_1138, T_1156) - node T_1159 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_1160 = mux(T_1159, T_1136, T_1158) - node T_1161 = eq(UInt<3>("h00"), UInt<3>("h03")) - node T_1162 = mux(T_1161, T_1133, T_1160) - wire T_1191 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1191.data <= UInt<1>("h00") - T_1191.union <= UInt<1>("h00") - T_1191.a_type <= UInt<1>("h00") - T_1191.is_builtin_type <= UInt<1>("h00") - T_1191.addr_beat <= UInt<1>("h00") - T_1191.client_xact_id <= UInt<1>("h00") - T_1191.addr_block <= UInt<1>("h00") - T_1191.is_builtin_type <= UInt<1>("h01") - T_1191.a_type <= UInt<3>("h03") - T_1191.client_xact_id <= T_826 - T_1191.addr_block <= T_827 - T_1191.addr_beat <= T_1121 - T_1191.data <= T_1122 - T_1191.union <= T_1162 - node T_1226 = bits(io.in.acquire.bits.union, 8, 6) - node T_1227 = bit(io.in.acquire.bits.union, 0) - node T_1234 = cat(T_842, T_1226) - node T_1235 = cat(UInt<5>("h00"), T_1227) + node T_1020 = bits(io.in.acquire.bits.union, 0, 0) + node T_1029 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_1030 = cat(UInt<5>("h00"), T_1020) + node T_1031 = cat(T_1029, T_1030) + node T_1033 = cat(UInt<5>("h00"), T_1020) + node T_1034 = cat(UInt<3>("h07"), T_1033) + node T_1036 = cat(UInt<1>("h00"), T_1020) + node T_1038 = cat(UInt<1>("h00"), T_1020) + node T_1040 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_1041 = cat(UInt<5>("h00"), T_1020) + node T_1042 = cat(T_1040, T_1041) + node T_1044 = cat(UInt<5>("h00"), T_1020) + node T_1046 = cat(UInt<5>("h01"), T_1020) + node T_1047 = eq(UInt<3>("h06"), UInt<3>("h01")) + node T_1048 = mux(T_1047, T_1046, UInt<1>("h00")) + node T_1049 = eq(UInt<3>("h05"), UInt<3>("h01")) + node T_1050 = mux(T_1049, T_1044, T_1048) + node T_1051 = eq(UInt<3>("h04"), UInt<3>("h01")) + node T_1052 = mux(T_1051, T_1042, T_1050) + node T_1053 = eq(UInt<3>("h03"), UInt<3>("h01")) + node T_1054 = mux(T_1053, T_1038, T_1052) + node T_1055 = eq(UInt<3>("h02"), UInt<3>("h01")) + node T_1056 = mux(T_1055, T_1036, T_1054) + node T_1057 = eq(UInt<3>("h01"), UInt<3>("h01")) + node T_1058 = mux(T_1057, T_1034, T_1056) + node T_1059 = eq(UInt<3>("h00"), UInt<3>("h01")) + node T_1060 = mux(T_1059, T_1031, T_1058) + wire T_1089 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} + T_1089 is invalid + T_1089.is_builtin_type <= UInt<1>("h01") + T_1089.a_type <= UInt<3>("h01") + T_1089.client_xact_id <= io.in.acquire.bits.client_xact_id + T_1089.addr_block <= io.in.acquire.bits.addr_block + T_1089.addr_beat <= UInt<1>("h00") + T_1089.data <= UInt<1>("h00") + T_1089.union <= T_1060 + node T_1117 = cat(T_828, T_830) + node T_1118 = bits(T_823, 63, 0) + node T_1119 = bits(T_825, 7, 0) + node T_1127 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_1128 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_1129 = cat(T_1127, T_1128) + node T_1131 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_1132 = cat(UInt<3>("h07"), T_1131) + node T_1134 = cat(T_1119, UInt<1>("h01")) + node T_1136 = cat(T_1119, UInt<1>("h01")) + node T_1138 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_1139 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_1140 = cat(T_1138, T_1139) + node T_1142 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1144 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_1145 = eq(UInt<3>("h06"), UInt<3>("h03")) + node T_1146 = mux(T_1145, T_1144, UInt<1>("h00")) + node T_1147 = eq(UInt<3>("h05"), UInt<3>("h03")) + node T_1148 = mux(T_1147, T_1142, T_1146) + node T_1149 = eq(UInt<3>("h04"), UInt<3>("h03")) + node T_1150 = mux(T_1149, T_1140, T_1148) + node T_1151 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_1152 = mux(T_1151, T_1136, T_1150) + node T_1153 = eq(UInt<3>("h02"), UInt<3>("h03")) + node T_1154 = mux(T_1153, T_1134, T_1152) + node T_1155 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_1156 = mux(T_1155, T_1132, T_1154) + node T_1157 = eq(UInt<3>("h00"), UInt<3>("h03")) + node T_1158 = mux(T_1157, T_1129, T_1156) + wire T_1187 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} + T_1187 is invalid + T_1187.is_builtin_type <= UInt<1>("h01") + T_1187.a_type <= UInt<3>("h03") + T_1187.client_xact_id <= T_826 + T_1187.addr_block <= T_827 + T_1187.addr_beat <= T_1117 + T_1187.data <= T_1118 + T_1187.union <= T_1158 + node T_1215 = bits(io.in.acquire.bits.union, 8, 6) + node T_1216 = bits(io.in.acquire.bits.union, 0, 0) + node T_1223 = cat(T_842, T_1215) + node T_1224 = cat(UInt<5>("h00"), T_1216) + node T_1225 = cat(T_1223, T_1224) + node T_1227 = cat(UInt<5>("h00"), T_1216) + node T_1228 = cat(T_1215, T_1227) + node T_1230 = cat(UInt<1>("h00"), T_1216) + node T_1232 = cat(UInt<1>("h00"), T_1216) + node T_1234 = cat(T_842, T_1215) + node T_1235 = cat(UInt<5>("h00"), T_1216) node T_1236 = cat(T_1234, T_1235) - node T_1238 = cat(UInt<5>("h00"), T_1227) - node T_1239 = cat(T_1226, T_1238) - node T_1241 = cat(UInt<1>("h00"), T_1227) - node T_1243 = cat(UInt<1>("h00"), T_1227) - node T_1245 = cat(T_842, T_1226) - node T_1246 = cat(UInt<5>("h00"), T_1227) - node T_1247 = cat(T_1245, T_1246) - node T_1249 = cat(UInt<5>("h00"), T_1227) - node T_1251 = cat(UInt<5>("h01"), T_1227) - node T_1252 = eq(UInt<3>("h06"), UInt<3>("h00")) - node T_1253 = mux(T_1252, T_1251, UInt<1>("h00")) - node T_1254 = eq(UInt<3>("h05"), UInt<3>("h00")) - node T_1255 = mux(T_1254, T_1249, T_1253) - node T_1256 = eq(UInt<3>("h04"), UInt<3>("h00")) - node T_1257 = mux(T_1256, T_1247, T_1255) - node T_1258 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_1259 = mux(T_1258, T_1243, T_1257) - node T_1260 = eq(UInt<3>("h02"), UInt<3>("h00")) - node T_1261 = mux(T_1260, T_1241, T_1259) - node T_1262 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_1263 = mux(T_1262, T_1239, T_1261) - node T_1264 = eq(UInt<3>("h00"), UInt<3>("h00")) - node T_1265 = mux(T_1264, T_1236, T_1263) - wire T_1294 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1294.data <= UInt<1>("h00") - T_1294.union <= UInt<1>("h00") - T_1294.a_type <= UInt<1>("h00") - T_1294.is_builtin_type <= UInt<1>("h00") - T_1294.addr_beat <= UInt<1>("h00") - T_1294.client_xact_id <= UInt<1>("h00") - T_1294.addr_block <= UInt<1>("h00") - T_1294.is_builtin_type <= UInt<1>("h01") - T_1294.a_type <= UInt<3>("h00") - T_1294.client_xact_id <= io.in.acquire.bits.client_xact_id - T_1294.addr_block <= io.in.acquire.bits.addr_block - T_1294.addr_beat <= T_838 - T_1294.data <= UInt<1>("h00") - T_1294.union <= T_1265 - node T_1336 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1337 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1338 = cat(T_1336, T_1337) - node T_1340 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1341 = cat(UInt<3>("h07"), T_1340) - node T_1343 = cat(T_950, UInt<1>("h01")) - node T_1345 = cat(T_950, UInt<1>("h01")) - node T_1347 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1348 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1349 = cat(T_1347, T_1348) - node T_1351 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1353 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1354 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_1355 = mux(T_1354, T_1353, UInt<1>("h00")) - node T_1356 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_1357 = mux(T_1356, T_1351, T_1355) - node T_1358 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_1359 = mux(T_1358, T_1349, T_1357) - node T_1360 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_1361 = mux(T_1360, T_1345, T_1359) - node T_1362 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_1363 = mux(T_1362, T_1343, T_1361) - node T_1364 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_1365 = mux(T_1364, T_1341, T_1363) - node T_1366 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_1367 = mux(T_1366, T_1338, T_1365) - wire T_1396 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1396.data <= UInt<1>("h00") - T_1396.union <= UInt<1>("h00") - T_1396.a_type <= UInt<1>("h00") - T_1396.is_builtin_type <= UInt<1>("h00") - T_1396.addr_beat <= UInt<1>("h00") - T_1396.client_xact_id <= UInt<1>("h00") - T_1396.addr_block <= UInt<1>("h00") - T_1396.is_builtin_type <= UInt<1>("h01") - T_1396.a_type <= UInt<3>("h02") - T_1396.client_xact_id <= io.in.acquire.bits.client_xact_id - T_1396.addr_block <= io.in.acquire.bits.addr_block - T_1396.addr_beat <= T_962 - T_1396.data <= T_940 - T_1396.union <= T_1367 - reg T_1432 : UInt<1>, clk, reset, UInt<1>("h00") - node T_1434 = eq(T_815, UInt<1>("h00")) - node T_1435 = and(io.in.acquire.valid, T_1434) - node T_1437 = eq(T_821, UInt<1>("h00")) - node T_1438 = and(T_1435, T_1437) - node T_1439 = and(T_821, io.in.acquire.valid) - inst T_1440 of ReorderQueue - T_1440.io.deq.tag <= UInt<1>("h00") - T_1440.io.deq.valid <= UInt<1>("h00") - T_1440.io.enq.bits.tag <= UInt<1>("h00") - T_1440.io.enq.bits.data <= UInt<1>("h00") - T_1440.io.enq.valid <= UInt<1>("h00") - T_1440.clk <= clk - T_1440.reset <= reset - node T_1447 = eq(T_1432, UInt<1>("h00")) - node T_1448 = and(T_1439, io.out.acquire.ready) - node T_1449 = and(T_1448, T_1447) - T_1440.io.enq.valid <= T_1449 - T_1440.io.enq.bits.data <= T_834 - T_1440.io.enq.bits.tag <= io.in.acquire.bits.client_xact_id - wire T_1450 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1450 <- io.in.acquire.bits - wire T_1506 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1506 <- T_1450 - when T_821 : - T_1506 <- T_1294 - skip - wire T_1562 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1562 <- T_1506 - when T_819 : - T_1562 <- T_1396 - skip - wire T_1618 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1618 <- T_1562 - when T_817 : - T_1618 <- T_1086 - skip - wire T_1674 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} - T_1674 <- T_1618 - when T_1432 : - T_1674 <- T_1191 - skip - io.out.acquire.bits <- T_1674 - node T_1702 = or(T_1432, T_1438) - node T_1703 = and(T_1439, T_1440.io.enq.ready) - node T_1704 = or(T_1702, T_1703) - io.out.acquire.valid <= T_1704 - node T_1706 = eq(T_1432, UInt<1>("h00")) - node T_1708 = eq(T_821, UInt<1>("h00")) - node T_1709 = and(T_1708, io.out.acquire.ready) - node T_1710 = or(T_815, T_1709) - node T_1711 = and(T_1440.io.enq.ready, io.out.acquire.ready) - node T_1712 = or(T_1710, T_1711) - node T_1713 = and(T_1706, T_1712) - io.in.acquire.ready <= T_1713 - node T_1714 = and(io.in.acquire.ready, io.in.acquire.valid) - node T_1715 = and(T_1714, T_815) - when T_1715 : + node T_1238 = cat(UInt<5>("h00"), T_1216) + node T_1240 = cat(UInt<5>("h01"), T_1216) + node T_1241 = eq(UInt<3>("h06"), UInt<3>("h00")) + node T_1242 = mux(T_1241, T_1240, UInt<1>("h00")) + node T_1243 = eq(UInt<3>("h05"), UInt<3>("h00")) + node T_1244 = mux(T_1243, T_1238, T_1242) + node T_1245 = eq(UInt<3>("h04"), UInt<3>("h00")) + node T_1246 = mux(T_1245, T_1236, T_1244) + node T_1247 = eq(UInt<3>("h03"), UInt<3>("h00")) + node T_1248 = mux(T_1247, T_1232, T_1246) + node T_1249 = eq(UInt<3>("h02"), UInt<3>("h00")) + node T_1250 = mux(T_1249, T_1230, T_1248) + node T_1251 = eq(UInt<3>("h01"), UInt<3>("h00")) + node T_1252 = mux(T_1251, T_1228, T_1250) + node T_1253 = eq(UInt<3>("h00"), UInt<3>("h00")) + node T_1254 = mux(T_1253, T_1225, T_1252) + wire T_1283 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} + T_1283 is invalid + T_1283.is_builtin_type <= UInt<1>("h01") + T_1283.a_type <= UInt<3>("h00") + T_1283.client_xact_id <= io.in.acquire.bits.client_xact_id + T_1283.addr_block <= io.in.acquire.bits.addr_block + T_1283.addr_beat <= T_838 + T_1283.data <= UInt<1>("h00") + T_1283.union <= T_1254 + node T_1318 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_1319 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_1320 = cat(T_1318, T_1319) + node T_1322 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_1323 = cat(UInt<3>("h07"), T_1322) + node T_1325 = cat(T_953, UInt<1>("h01")) + node T_1327 = cat(T_953, UInt<1>("h01")) + node T_1329 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_1330 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_1331 = cat(T_1329, T_1330) + node T_1333 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_1335 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_1336 = eq(UInt<3>("h06"), UInt<3>("h02")) + node T_1337 = mux(T_1336, T_1335, UInt<1>("h00")) + node T_1338 = eq(UInt<3>("h05"), UInt<3>("h02")) + node T_1339 = mux(T_1338, T_1333, T_1337) + node T_1340 = eq(UInt<3>("h04"), UInt<3>("h02")) + node T_1341 = mux(T_1340, T_1331, T_1339) + node T_1342 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_1343 = mux(T_1342, T_1327, T_1341) + node T_1344 = eq(UInt<3>("h02"), UInt<3>("h02")) + node T_1345 = mux(T_1344, T_1325, T_1343) + node T_1346 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_1347 = mux(T_1346, T_1323, T_1345) + node T_1348 = eq(UInt<3>("h00"), UInt<3>("h02")) + node T_1349 = mux(T_1348, T_1320, T_1347) + wire T_1378 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} + T_1378 is invalid + T_1378.is_builtin_type <= UInt<1>("h01") + T_1378.a_type <= UInt<3>("h02") + T_1378.client_xact_id <= io.in.acquire.bits.client_xact_id + T_1378.addr_block <= io.in.acquire.bits.addr_block + T_1378.addr_beat <= T_964 + T_1378.data <= T_944 + T_1378.union <= T_1349 + reg T_1407 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_1409 = eq(T_815, UInt<1>("h00")) + node T_1410 = and(io.in.acquire.valid, T_1409) + node T_1412 = eq(T_821, UInt<1>("h00")) + node T_1413 = and(T_1410, T_1412) + node T_1414 = and(T_821, io.in.acquire.valid) + inst T_1415 of ReorderQueue + T_1415.io is invalid + T_1415.clk <= clk + T_1415.reset <= reset + node T_1417 = eq(T_1407, UInt<1>("h00")) + node T_1418 = and(T_1414, io.out.acquire.ready) + node T_1419 = and(T_1418, T_1417) + T_1415.io.enq.valid <= T_1419 + T_1415.io.enq.bits.data <= T_834 + T_1415.io.enq.bits.tag <= io.in.acquire.bits.client_xact_id + wire T_1420 : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>} + T_1420 <- io.in.acquire.bits + node T_1448 = mux(T_821, T_1283, T_1420) + node T_1476 = mux(T_819, T_1378, T_1448) + node T_1504 = mux(T_817, T_1089, T_1476) + node T_1532 = mux(T_1407, T_1187, T_1504) + io.out.acquire.bits <- T_1532 + node T_1560 = or(T_1407, T_1413) + node T_1561 = and(T_1414, T_1415.io.enq.ready) + node T_1562 = or(T_1560, T_1561) + io.out.acquire.valid <= T_1562 + node T_1564 = eq(T_1407, UInt<1>("h00")) + node T_1566 = eq(T_821, UInt<1>("h00")) + node T_1567 = and(T_1566, io.out.acquire.ready) + node T_1568 = or(T_815, T_1567) + node T_1569 = and(T_1415.io.enq.ready, io.out.acquire.ready) + node T_1570 = or(T_1568, T_1569) + node T_1571 = and(T_1564, T_1570) + io.in.acquire.ready <= T_1571 + node T_1572 = and(io.in.acquire.ready, io.in.acquire.valid) + node T_1573 = and(T_1572, T_815) + when T_1573 : T_823 <= io.in.acquire.bits.data - node T_1716 = bits(io.in.acquire.bits.union, 12, 9) - node T_1717 = bits(T_1716, 3, 3) - node T_1719 = dshl(UInt<1>("h01"), T_1717) - node T_1721 = eq(io.in.acquire.bits.a_type, UInt<3>("h04")) - node T_1722 = and(io.in.acquire.bits.is_builtin_type, T_1721) - node T_1723 = bit(T_1719, 0) - node T_1724 = bit(T_1719, 1) - wire T_1726 : UInt<1>[2] - T_1726[0] <= T_1723 - T_1726[1] <= T_1724 - node T_1731 = subw(UInt<8>("h00"), T_1726[0]) - node T_1733 = subw(UInt<8>("h00"), T_1726[1]) - wire T_1735 : UInt<8>[2] - T_1735[0] <= T_1731 - T_1735[1] <= T_1733 - node T_1739 = cat(T_1735[1], T_1735[0]) - node T_1741 = eq(io.in.acquire.bits.a_type, UInt<3>("h03")) - node T_1742 = and(io.in.acquire.bits.is_builtin_type, T_1741) - node T_1744 = eq(io.in.acquire.bits.a_type, UInt<3>("h02")) - node T_1745 = and(io.in.acquire.bits.is_builtin_type, T_1744) - node T_1746 = or(T_1742, T_1745) - node T_1747 = bits(io.in.acquire.bits.union, 16, 1) - node T_1749 = mux(T_1746, T_1747, UInt<16>("h00")) - node T_1750 = mux(T_1722, T_1739, T_1749) - T_825 <= T_1750 + node T_1574 = bits(io.in.acquire.bits.union, 12, 9) + node T_1575 = bits(T_1574, 3, 3) + node T_1577 = dshl(UInt<1>("h01"), T_1575) + node T_1579 = eq(io.in.acquire.bits.a_type, UInt<3>("h04")) + node T_1580 = and(io.in.acquire.bits.is_builtin_type, T_1579) + node T_1581 = bits(T_1577, 0, 0) + node T_1582 = bits(T_1577, 1, 1) + wire T_1584 : UInt<1>[2] + T_1584[0] <= T_1581 + T_1584[1] <= T_1582 + node T_1589 = sub(UInt<8>("h00"), T_1584[0]) + node T_1590 = tail(T_1589, 1) + node T_1592 = sub(UInt<8>("h00"), T_1584[1]) + node T_1593 = tail(T_1592, 1) + wire T_1595 : UInt<8>[2] + T_1595[0] <= T_1590 + T_1595[1] <= T_1593 + node T_1599 = cat(T_1595[1], T_1595[0]) + node T_1601 = eq(io.in.acquire.bits.a_type, UInt<3>("h03")) + node T_1602 = and(io.in.acquire.bits.is_builtin_type, T_1601) + node T_1604 = eq(io.in.acquire.bits.a_type, UInt<3>("h02")) + node T_1605 = and(io.in.acquire.bits.is_builtin_type, T_1604) + node T_1606 = or(T_1602, T_1605) + node T_1607 = bits(io.in.acquire.bits.union, 16, 1) + node T_1609 = mux(T_1606, T_1607, UInt<16>("h00")) + node T_1610 = mux(T_1580, T_1599, T_1609) + T_825 <= T_1610 T_826 <= io.in.acquire.bits.client_xact_id T_827 <= io.in.acquire.bits.addr_block T_828 <= io.in.acquire.bits.addr_beat - T_1432 <= UInt<1>("h01") - skip - node T_1752 = and(T_1432, io.out.acquire.ready) - when T_1752 : - node T_1753 = shr(T_823, 64) - T_823 <= T_1753 - node T_1754 = shr(T_825, 8) - T_825 <= T_1754 - node T_1756 = eq(T_830, UInt<1>("h01")) - node T_1758 = and(UInt<1>("h00"), T_1756) - node T_1761 = addw(T_830, UInt<1>("h01")) - node T_1762 = mux(T_1758, UInt<1>("h00"), T_1761) - T_830 <= T_1762 - when T_1756 : - T_1432 <= UInt<1>("h00") - skip - skip - wire T_1767 : UInt<3>[1] - T_1767[0] <= UInt<3>("h05") - node T_1770 = eq(T_1767[0], io.out.grant.bits.g_type) - node T_1772 = or(UInt<1>("h00"), T_1770) - wire T_1774 : UInt<1>[1] - T_1774[0] <= UInt<1>("h00") - node T_1777 = eq(T_1774[0], io.out.grant.bits.g_type) - node T_1779 = or(UInt<1>("h00"), T_1777) - node T_1780 = mux(io.out.grant.bits.is_builtin_type, T_1772, T_1779) - node T_1781 = and(UInt<1>("h01"), T_1780) - reg T_1790 : UInt<64>[2], clk, UInt<1>("h00"), T_1790 - reg T_1794 : UInt<4>, clk, UInt<1>("h00"), T_1794 - reg T_1795 : UInt<1>, clk, UInt<1>("h00"), T_1795 - reg T_1797 : UInt<2>, clk, reset, UInt<2>("h00") - reg T_1799 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_1801 : UInt<1>, clk, reset, UInt<1>("h00") - node T_1804 = cat(T_1790[1], T_1790[0]) - wire T_1832 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - T_1832.data <= UInt<1>("h00") - T_1832.g_type <= UInt<1>("h00") - T_1832.is_builtin_type <= UInt<1>("h00") - T_1832.manager_xact_id <= UInt<1>("h00") - T_1832.client_xact_id <= UInt<1>("h00") - T_1832.addr_beat <= UInt<1>("h00") - T_1832.is_builtin_type <= UInt<1>("h01") - T_1832.g_type <= UInt<3>("h05") - T_1832.client_xact_id <= T_1794 - T_1832.manager_xact_id <= T_1795 - T_1832.addr_beat <= T_1797 - T_1832.data <= T_1804 - node T_1866 = eq(io.out.grant.bits.g_type, UInt<3>("h04")) - node T_1868 = cat(T_1440.io.deq.data, UInt<6>("h00")) - node T_1869 = and(io.out.grant.ready, io.out.grant.valid) - node T_1870 = and(T_1869, T_1866) - T_1440.io.deq.valid <= T_1870 - T_1440.io.deq.tag <= io.out.grant.bits.client_xact_id - node T_1874 = dshr(io.out.grant.bits.addr_beat, UInt<1>("h01")) - node T_1875 = dshl(io.out.grant.bits.data, T_1868) - wire T_1903 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - T_1903.data <= UInt<1>("h00") - T_1903.g_type <= UInt<1>("h00") - T_1903.is_builtin_type <= UInt<1>("h00") - T_1903.manager_xact_id <= UInt<1>("h00") - T_1903.client_xact_id <= UInt<1>("h00") - T_1903.addr_beat <= UInt<1>("h00") - T_1903.is_builtin_type <= UInt<1>("h01") - T_1903.g_type <= UInt<3>("h04") - T_1903.client_xact_id <= io.out.grant.bits.client_xact_id - T_1903.manager_xact_id <= io.out.grant.bits.manager_xact_id - T_1903.addr_beat <= T_1874 - T_1903.data <= T_1875 - node T_1937 = eq(T_1781, UInt<1>("h00")) - node T_1938 = and(io.out.grant.valid, T_1937) - node T_1939 = or(T_1801, T_1938) - io.in.grant.valid <= T_1939 - node T_1941 = eq(T_1801, UInt<1>("h00")) - node T_1942 = or(T_1781, io.in.grant.ready) - node T_1943 = and(T_1941, T_1942) - io.out.grant.ready <= T_1943 - wire T_1944 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - T_1944 <- io.out.grant.bits - wire T_1998 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - T_1998 <- T_1944 - when T_1866 : - T_1998 <- T_1903 - skip - wire T_2052 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} - T_2052 <- T_1998 - when T_1801 : - T_2052 <- T_1832 - skip - io.in.grant.bits <- T_2052 - node T_2079 = and(io.out.grant.valid, T_1781) - node T_2081 = eq(T_1801, UInt<1>("h00")) - node T_2082 = and(T_2079, T_2081) - when T_2082 : - T_1790[T_1799] <= io.out.grant.bits.data - node T_2085 = eq(T_1799, UInt<1>("h01")) - node T_2087 = and(UInt<1>("h00"), T_2085) - node T_2090 = addw(T_1799, UInt<1>("h01")) - node T_2091 = mux(T_2087, UInt<1>("h00"), T_2090) - T_1799 <= T_2091 - when T_2085 : - T_1794 <= io.out.grant.bits.client_xact_id - T_1795 <= io.out.grant.bits.manager_xact_id - T_1801 <= UInt<1>("h01") - skip - skip - node T_2093 = and(io.in.grant.ready, T_1801) - when T_2093 : - node T_2095 = eq(T_1797, UInt<2>("h03")) - node T_2097 = and(UInt<1>("h00"), T_2095) - node T_2100 = addw(T_1797, UInt<1>("h01")) - node T_2101 = mux(T_2097, UInt<1>("h00"), T_2100) - T_1797 <= T_2101 - T_1801 <= UInt<1>("h00") + T_1407 <= UInt<1>("h01") + skip + node T_1612 = and(T_1407, io.out.acquire.ready) + when T_1612 : + node T_1613 = shr(T_823, 64) + T_823 <= T_1613 + node T_1614 = shr(T_825, 8) + T_825 <= T_1614 + node T_1616 = eq(T_830, UInt<1>("h01")) + node T_1618 = and(UInt<1>("h00"), T_1616) + node T_1621 = add(T_830, UInt<1>("h01")) + node T_1622 = tail(T_1621, 1) + node T_1623 = mux(T_1618, UInt<1>("h00"), T_1622) + T_830 <= T_1623 + when T_1616 : + T_1407 <= UInt<1>("h00") + skip + skip + wire T_1628 : UInt<3>[1] + T_1628[0] <= UInt<3>("h05") + node T_1631 = eq(T_1628[0], io.out.grant.bits.g_type) + node T_1633 = or(UInt<1>("h00"), T_1631) + wire T_1635 : UInt<1>[1] + T_1635[0] <= UInt<1>("h00") + node T_1638 = eq(T_1635[0], io.out.grant.bits.g_type) + node T_1640 = or(UInt<1>("h00"), T_1638) + node T_1641 = mux(io.out.grant.bits.is_builtin_type, T_1633, T_1640) + node T_1642 = and(UInt<1>("h01"), T_1641) + reg T_1651 : UInt<64>[2], clk + reg T_1655 : UInt<4>, clk + reg T_1656 : UInt<1>, clk + reg T_1658 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + reg T_1660 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_1662 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_1665 = cat(T_1651[1], T_1651[0]) + wire T_1693 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} + T_1693 is invalid + T_1693.is_builtin_type <= UInt<1>("h01") + T_1693.g_type <= UInt<3>("h05") + T_1693.client_xact_id <= T_1655 + T_1693.manager_xact_id <= T_1656 + T_1693.addr_beat <= T_1658 + T_1693.data <= T_1665 + node T_1721 = eq(io.out.grant.bits.g_type, UInt<3>("h04")) + node T_1723 = cat(T_1415.io.deq.data, UInt<6>("h00")) + node T_1724 = and(io.out.grant.ready, io.out.grant.valid) + node T_1725 = and(T_1724, T_1721) + T_1415.io.deq.valid <= T_1725 + T_1415.io.deq.tag <= io.out.grant.bits.client_xact_id + node T_1729 = dshr(io.out.grant.bits.addr_beat, UInt<1>("h01")) + node T_1730 = dshl(io.out.grant.bits.data, T_1723) + wire T_1758 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} + T_1758 is invalid + T_1758.is_builtin_type <= UInt<1>("h01") + T_1758.g_type <= UInt<3>("h04") + T_1758.client_xact_id <= io.out.grant.bits.client_xact_id + T_1758.manager_xact_id <= io.out.grant.bits.manager_xact_id + T_1758.addr_beat <= T_1729 + T_1758.data <= T_1730 + node T_1786 = eq(T_1642, UInt<1>("h00")) + node T_1787 = and(io.out.grant.valid, T_1786) + node T_1788 = or(T_1662, T_1787) + io.in.grant.valid <= T_1788 + node T_1790 = eq(T_1662, UInt<1>("h00")) + node T_1791 = or(T_1642, io.in.grant.ready) + node T_1792 = and(T_1790, T_1791) + io.out.grant.ready <= T_1792 + wire T_1793 : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>} + T_1793 <- io.out.grant.bits + node T_1820 = mux(T_1721, T_1758, T_1793) + node T_1847 = mux(T_1662, T_1693, T_1820) + io.in.grant.bits <- T_1847 + node T_1874 = and(io.out.grant.valid, T_1642) + node T_1876 = eq(T_1662, UInt<1>("h00")) + node T_1877 = and(T_1874, T_1876) + when T_1877 : + T_1651[T_1660] <= io.out.grant.bits.data + node T_1880 = eq(T_1660, UInt<1>("h01")) + node T_1882 = and(UInt<1>("h00"), T_1880) + node T_1885 = add(T_1660, UInt<1>("h01")) + node T_1886 = tail(T_1885, 1) + node T_1887 = mux(T_1882, UInt<1>("h00"), T_1886) + T_1660 <= T_1887 + when T_1880 : + T_1655 <= io.out.grant.bits.client_xact_id + T_1656 <= io.out.grant.bits.manager_xact_id + T_1662 <= UInt<1>("h01") + skip + skip + node T_1889 = and(io.in.grant.ready, T_1662) + when T_1889 : + node T_1891 = eq(T_1658, UInt<2>("h03")) + node T_1893 = and(UInt<1>("h00"), T_1891) + node T_1896 = add(T_1658, UInt<1>("h01")) + node T_1897 = tail(T_1896, 1) + node T_1898 = mux(T_1893, UInt<1>("h00"), T_1897) + T_1658 <= T_1898 + T_1662 <= UInt<1>("h00") skip module ReorderQueue_70 : @@ -16497,88 +12044,84 @@ circuit Top : input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : {addr_beat : UInt<3>, byteOff : UInt<3>, subblock : UInt<1>}, tag : UInt<5>}}, deq : {flip valid : UInt<1>, flip tag : UInt<5>, data : {addr_beat : UInt<3>, byteOff : UInt<3>, subblock : UInt<1>}, matches : UInt<1>}} - io.deq.matches <= UInt<1>("h00") - io.deq.data.subblock <= UInt<1>("h00") - io.deq.data.byteOff <= UInt<1>("h00") - io.deq.data.addr_beat <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") - reg roq_data : {addr_beat : UInt<3>, byteOff : UInt<3>, subblock : UInt<1>}[9], clk, UInt<1>("h00"), roq_data - reg roq_tags : UInt<5>[9], clk, UInt<1>("h00"), roq_tags - wire T_806 : UInt<1>[9] - T_806[0] <= UInt<1>("h01") - T_806[1] <= UInt<1>("h01") - T_806[2] <= UInt<1>("h01") - T_806[3] <= UInt<1>("h01") - T_806[4] <= UInt<1>("h01") - T_806[5] <= UInt<1>("h01") - T_806[6] <= UInt<1>("h01") - T_806[7] <= UInt<1>("h01") - T_806[8] <= UInt<1>("h01") - reg roq_free : UInt<1>[9], clk, reset, T_806 - node T_839 = mux(roq_free[7], UInt<3>("h07"), UInt<4>("h08")) - node T_840 = mux(roq_free[6], UInt<3>("h06"), T_839) - node T_841 = mux(roq_free[5], UInt<3>("h05"), T_840) - node T_842 = mux(roq_free[4], UInt<3>("h04"), T_841) - node T_843 = mux(roq_free[3], UInt<2>("h03"), T_842) - node T_844 = mux(roq_free[2], UInt<2>("h02"), T_843) - node T_845 = mux(roq_free[1], UInt<1>("h01"), T_844) - node roq_enq_addr = mux(roq_free[0], UInt<1>("h00"), T_845) - node T_847 = eq(roq_tags[0], io.deq.tag) - node T_849 = eq(roq_free[0], UInt<1>("h00")) - node T_850 = and(T_847, T_849) - node T_851 = eq(roq_tags[1], io.deq.tag) - node T_853 = eq(roq_free[1], UInt<1>("h00")) - node T_854 = and(T_851, T_853) - node T_855 = eq(roq_tags[2], io.deq.tag) - node T_857 = eq(roq_free[2], UInt<1>("h00")) - node T_858 = and(T_855, T_857) - node T_859 = eq(roq_tags[3], io.deq.tag) - node T_861 = eq(roq_free[3], UInt<1>("h00")) - node T_862 = and(T_859, T_861) - node T_863 = eq(roq_tags[4], io.deq.tag) - node T_865 = eq(roq_free[4], UInt<1>("h00")) - node T_866 = and(T_863, T_865) - node T_867 = eq(roq_tags[5], io.deq.tag) - node T_869 = eq(roq_free[5], UInt<1>("h00")) - node T_870 = and(T_867, T_869) - node T_871 = eq(roq_tags[6], io.deq.tag) - node T_873 = eq(roq_free[6], UInt<1>("h00")) - node T_874 = and(T_871, T_873) - node T_875 = eq(roq_tags[7], io.deq.tag) - node T_877 = eq(roq_free[7], UInt<1>("h00")) - node T_878 = and(T_875, T_877) - node T_879 = eq(roq_tags[8], io.deq.tag) - node T_881 = eq(roq_free[8], UInt<1>("h00")) - node T_882 = and(T_879, T_881) - node T_892 = mux(T_878, UInt<3>("h07"), UInt<4>("h08")) - node T_893 = mux(T_874, UInt<3>("h06"), T_892) - node T_894 = mux(T_870, UInt<3>("h05"), T_893) - node T_895 = mux(T_866, UInt<3>("h04"), T_894) - node T_896 = mux(T_862, UInt<2>("h03"), T_895) - node T_897 = mux(T_858, UInt<2>("h02"), T_896) - node T_898 = mux(T_854, UInt<1>("h01"), T_897) - node roq_deq_addr = mux(T_850, UInt<1>("h00"), T_898) - node T_900 = or(roq_free[0], roq_free[1]) - node T_901 = or(T_900, roq_free[2]) - node T_902 = or(T_901, roq_free[3]) - node T_903 = or(T_902, roq_free[4]) - node T_904 = or(T_903, roq_free[5]) - node T_905 = or(T_904, roq_free[6]) - node T_906 = or(T_905, roq_free[7]) - node T_907 = or(T_906, roq_free[8]) - io.enq.ready <= T_907 + io is invalid + reg roq_data : {addr_beat : UInt<3>, byteOff : UInt<3>, subblock : UInt<1>}[9], clk + reg roq_tags : UInt<5>[9], clk + wire T_832 : UInt<1>[9] + T_832[0] <= UInt<1>("h01") + T_832[1] <= UInt<1>("h01") + T_832[2] <= UInt<1>("h01") + T_832[3] <= UInt<1>("h01") + T_832[4] <= UInt<1>("h01") + T_832[5] <= UInt<1>("h01") + T_832[6] <= UInt<1>("h01") + T_832[7] <= UInt<1>("h01") + T_832[8] <= UInt<1>("h01") + reg roq_free : UInt<1>[9], clk with : (reset => (reset, T_832)) + node T_865 = mux(roq_free[7], UInt<3>("h07"), UInt<4>("h08")) + node T_866 = mux(roq_free[6], UInt<3>("h06"), T_865) + node T_867 = mux(roq_free[5], UInt<3>("h05"), T_866) + node T_868 = mux(roq_free[4], UInt<3>("h04"), T_867) + node T_869 = mux(roq_free[3], UInt<2>("h03"), T_868) + node T_870 = mux(roq_free[2], UInt<2>("h02"), T_869) + node T_871 = mux(roq_free[1], UInt<1>("h01"), T_870) + node roq_enq_addr = mux(roq_free[0], UInt<1>("h00"), T_871) + node T_873 = eq(roq_tags[0], io.deq.tag) + node T_875 = eq(roq_free[0], UInt<1>("h00")) + node T_876 = and(T_873, T_875) + node T_877 = eq(roq_tags[1], io.deq.tag) + node T_879 = eq(roq_free[1], UInt<1>("h00")) + node T_880 = and(T_877, T_879) + node T_881 = eq(roq_tags[2], io.deq.tag) + node T_883 = eq(roq_free[2], UInt<1>("h00")) + node T_884 = and(T_881, T_883) + node T_885 = eq(roq_tags[3], io.deq.tag) + node T_887 = eq(roq_free[3], UInt<1>("h00")) + node T_888 = and(T_885, T_887) + node T_889 = eq(roq_tags[4], io.deq.tag) + node T_891 = eq(roq_free[4], UInt<1>("h00")) + node T_892 = and(T_889, T_891) + node T_893 = eq(roq_tags[5], io.deq.tag) + node T_895 = eq(roq_free[5], UInt<1>("h00")) + node T_896 = and(T_893, T_895) + node T_897 = eq(roq_tags[6], io.deq.tag) + node T_899 = eq(roq_free[6], UInt<1>("h00")) + node T_900 = and(T_897, T_899) + node T_901 = eq(roq_tags[7], io.deq.tag) + node T_903 = eq(roq_free[7], UInt<1>("h00")) + node T_904 = and(T_901, T_903) + node T_905 = eq(roq_tags[8], io.deq.tag) + node T_907 = eq(roq_free[8], UInt<1>("h00")) + node T_908 = and(T_905, T_907) + node T_918 = mux(T_904, UInt<3>("h07"), UInt<4>("h08")) + node T_919 = mux(T_900, UInt<3>("h06"), T_918) + node T_920 = mux(T_896, UInt<3>("h05"), T_919) + node T_921 = mux(T_892, UInt<3>("h04"), T_920) + node T_922 = mux(T_888, UInt<2>("h03"), T_921) + node T_923 = mux(T_884, UInt<2>("h02"), T_922) + node T_924 = mux(T_880, UInt<1>("h01"), T_923) + node roq_deq_addr = mux(T_876, UInt<1>("h00"), T_924) + node T_926 = or(roq_free[0], roq_free[1]) + node T_927 = or(T_926, roq_free[2]) + node T_928 = or(T_927, roq_free[3]) + node T_929 = or(T_928, roq_free[4]) + node T_930 = or(T_929, roq_free[5]) + node T_931 = or(T_930, roq_free[6]) + node T_932 = or(T_931, roq_free[7]) + node T_933 = or(T_932, roq_free[8]) + io.enq.ready <= T_933 io.deq.data <- roq_data[roq_deq_addr] - node T_932 = or(T_850, T_854) - node T_933 = or(T_932, T_858) - node T_934 = or(T_933, T_862) - node T_935 = or(T_934, T_866) - node T_936 = or(T_935, T_870) - node T_937 = or(T_936, T_874) - node T_938 = or(T_937, T_878) - node T_939 = or(T_938, T_882) - io.deq.matches <= T_939 - node T_940 = and(io.enq.valid, io.enq.ready) - when T_940 : + node T_958 = or(T_876, T_880) + node T_959 = or(T_958, T_884) + node T_960 = or(T_959, T_888) + node T_961 = or(T_960, T_892) + node T_962 = or(T_961, T_896) + node T_963 = or(T_962, T_900) + node T_964 = or(T_963, T_904) + node T_965 = or(T_964, T_908) + io.deq.matches <= T_965 + node T_966 = and(io.enq.valid, io.enq.ready) + when T_966 : roq_data[roq_enq_addr] <- io.enq.bits.data roq_tags[roq_enq_addr] <= io.enq.bits.tag roq_free[roq_enq_addr] <= UInt<1>("h00") @@ -16592,81 +12135,33 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>, client_id : UInt<1>}}, chosen : UInt<1>} - io.chosen <= UInt<1>("h00") - io.out.bits.client_id <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.bits.g_type <= UInt<1>("h00") - io.out.bits.is_builtin_type <= UInt<1>("h00") - io.out.bits.manager_xact_id <= UInt<1>("h00") - io.out.bits.client_xact_id <= UInt<1>("h00") - io.out.bits.addr_beat <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") + io is invalid wire T_658 : UInt<1> - T_658 <= UInt<1>("h00") + T_658 is invalid io.out.valid <= io.in[T_658].valid io.out.bits <- io.in[T_658].bits io.chosen <= T_658 io.in[T_658].ready <= UInt<1>("h00") - node T_840 = or(UInt<1>("h00"), io.in[0].valid) - node T_842 = eq(T_840, UInt<1>("h00")) - node T_844 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_845 = mux(UInt<1>("h00"), T_844, UInt<1>("h01")) - node T_846 = and(T_845, io.out.ready) - io.in[0].ready <= T_846 - node T_848 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_849 = mux(UInt<1>("h00"), T_848, T_842) - node T_850 = and(T_849, io.out.ready) - io.in[1].ready <= T_850 - node T_853 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_854 = mux(UInt<1>("h00"), UInt<1>("h01"), T_853) - T_658 <= T_854 + node T_839 = or(UInt<1>("h00"), io.in[0].valid) + node T_841 = eq(T_839, UInt<1>("h00")) + node T_843 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_844 = mux(UInt<1>("h00"), T_843, UInt<1>("h01")) + node T_845 = and(T_844, io.out.ready) + io.in[0].ready <= T_845 + node T_847 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_848 = mux(UInt<1>("h00"), T_847, T_841) + node T_849 = and(T_848, io.out.ready) + io.in[1].ready <= T_849 + node T_852 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_853 = mux(UInt<1>("h00"), UInt<1>("h01"), T_852) + T_658 <= T_853 module NastiIOTileLinkIOConverter : input clk : Clock input reset : UInt<1> output io : {flip tl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<3>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<12>, data : UInt<64>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>}}}, nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} - io.nasti.r.ready <= UInt<1>("h00") - io.nasti.ar.bits.user <= UInt<1>("h00") - io.nasti.ar.bits.id <= UInt<1>("h00") - io.nasti.ar.bits.region <= UInt<1>("h00") - io.nasti.ar.bits.qos <= UInt<1>("h00") - io.nasti.ar.bits.prot <= UInt<1>("h00") - io.nasti.ar.bits.cache <= UInt<1>("h00") - io.nasti.ar.bits.lock <= UInt<1>("h00") - io.nasti.ar.bits.burst <= UInt<1>("h00") - io.nasti.ar.bits.size <= UInt<1>("h00") - io.nasti.ar.bits.len <= UInt<1>("h00") - io.nasti.ar.bits.addr <= UInt<1>("h00") - io.nasti.ar.valid <= UInt<1>("h00") - io.nasti.b.ready <= UInt<1>("h00") - io.nasti.w.bits.user <= UInt<1>("h00") - io.nasti.w.bits.strb <= UInt<1>("h00") - io.nasti.w.bits.last <= UInt<1>("h00") - io.nasti.w.bits.data <= UInt<1>("h00") - io.nasti.w.valid <= UInt<1>("h00") - io.nasti.aw.bits.user <= UInt<1>("h00") - io.nasti.aw.bits.id <= UInt<1>("h00") - io.nasti.aw.bits.region <= UInt<1>("h00") - io.nasti.aw.bits.qos <= UInt<1>("h00") - io.nasti.aw.bits.prot <= UInt<1>("h00") - io.nasti.aw.bits.cache <= UInt<1>("h00") - io.nasti.aw.bits.lock <= UInt<1>("h00") - io.nasti.aw.bits.burst <= UInt<1>("h00") - io.nasti.aw.bits.size <= UInt<1>("h00") - io.nasti.aw.bits.len <= UInt<1>("h00") - io.nasti.aw.bits.addr <= UInt<1>("h00") - io.nasti.aw.valid <= UInt<1>("h00") - io.tl.grant.bits.data <= UInt<1>("h00") - io.tl.grant.bits.g_type <= UInt<1>("h00") - io.tl.grant.bits.is_builtin_type <= UInt<1>("h00") - io.tl.grant.bits.manager_xact_id <= UInt<1>("h00") - io.tl.grant.bits.client_xact_id <= UInt<1>("h00") - io.tl.grant.bits.addr_beat <= UInt<1>("h00") - io.tl.grant.valid <= UInt<1>("h00") - io.tl.acquire.ready <= UInt<1>("h00") + io is invalid wire T_685 : UInt<3>[3] T_685[0] <= UInt<3>("h02") T_685[1] <= UInt<3>("h03") @@ -16697,175 +12192,149 @@ circuit Top : node is_multibeat = and(T_716, T_724) node T_726 = and(io.tl.acquire.ready, io.tl.acquire.valid) node T_727 = and(T_726, is_multibeat) - reg tl_cnt_out : UInt<3>, clk, reset, UInt<3>("h00") + reg tl_cnt_out : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) when T_727 : node T_731 = eq(tl_cnt_out, UInt<3>("h07")) node T_733 = and(UInt<1>("h00"), T_731) - node T_736 = addw(tl_cnt_out, UInt<1>("h01")) - node T_737 = mux(T_733, UInt<1>("h00"), T_736) - tl_cnt_out <= T_737 + node T_736 = add(tl_cnt_out, UInt<1>("h01")) + node T_737 = tail(T_736, 1) + node T_738 = mux(T_733, UInt<1>("h00"), T_737) + tl_cnt_out <= T_738 skip node tl_wrap_out = and(T_727, T_731) - node T_740 = eq(has_data, UInt<1>("h00")) - node get_valid = and(io.tl.acquire.valid, T_740) + node T_741 = eq(has_data, UInt<1>("h00")) + node get_valid = and(io.tl.acquire.valid, T_741) node put_valid = and(io.tl.acquire.valid, has_data) inst roq of ReorderQueue_70 - roq.io.deq.tag <= UInt<1>("h00") - roq.io.deq.valid <= UInt<1>("h00") - roq.io.enq.bits.tag <= UInt<1>("h00") - roq.io.enq.bits.data.subblock <= UInt<1>("h00") - roq.io.enq.bits.data.byteOff <= UInt<1>("h00") - roq.io.enq.bits.data.addr_beat <= UInt<1>("h00") - roq.io.enq.valid <= UInt<1>("h00") + roq.io is invalid roq.clk <= clk roq.reset <= reset - reg w_inflight : UInt<1>, clk, reset, UInt<1>("h00") + reg w_inflight : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node aw_ready = or(w_inflight, io.nasti.aw.ready) - node T_778 = and(io.nasti.r.ready, io.nasti.r.valid) - node T_780 = eq(roq.io.deq.data.subblock, UInt<1>("h00")) - node T_781 = and(T_778, T_780) - reg nasti_cnt_out : UInt<3>, clk, reset, UInt<3>("h00") - when T_781 : - node T_785 = eq(nasti_cnt_out, UInt<3>("h07")) - node T_787 = and(UInt<1>("h00"), T_785) - node T_790 = addw(nasti_cnt_out, UInt<1>("h01")) - node T_791 = mux(T_787, UInt<1>("h00"), T_790) - nasti_cnt_out <= T_791 - skip - node nasti_wrap_out = and(T_781, T_785) - node T_793 = and(get_valid, io.nasti.ar.ready) - roq.io.enq.valid <= T_793 + node T_772 = and(io.nasti.r.ready, io.nasti.r.valid) + node T_774 = eq(roq.io.deq.data.subblock, UInt<1>("h00")) + node T_775 = and(T_772, T_774) + reg nasti_cnt_out : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + when T_775 : + node T_779 = eq(nasti_cnt_out, UInt<3>("h07")) + node T_781 = and(UInt<1>("h00"), T_779) + node T_784 = add(nasti_cnt_out, UInt<1>("h01")) + node T_785 = tail(T_784, 1) + node T_786 = mux(T_781, UInt<1>("h00"), T_785) + nasti_cnt_out <= T_786 + skip + node nasti_wrap_out = and(T_775, T_779) + node T_788 = and(get_valid, io.nasti.ar.ready) + roq.io.enq.valid <= T_788 roq.io.enq.bits.tag <= io.nasti.ar.bits.id roq.io.enq.bits.data.addr_beat <= io.tl.acquire.bits.addr_beat - node T_794 = bits(io.tl.acquire.bits.union, 11, 9) - roq.io.enq.bits.data.byteOff <= T_794 + node T_789 = bits(io.tl.acquire.bits.union, 11, 9) + roq.io.enq.bits.data.byteOff <= T_789 roq.io.enq.bits.data.subblock <= is_subblock - node T_795 = and(io.nasti.r.ready, io.nasti.r.valid) - node T_796 = or(nasti_wrap_out, roq.io.deq.data.subblock) - node T_797 = and(T_795, T_796) - roq.io.deq.valid <= T_797 + node T_790 = and(io.nasti.r.ready, io.nasti.r.valid) + node T_791 = or(nasti_wrap_out, roq.io.deq.data.subblock) + node T_792 = and(T_790, T_791) + roq.io.deq.valid <= T_792 roq.io.deq.tag <= io.nasti.r.bits.id - node T_798 = and(get_valid, roq.io.enq.ready) - io.nasti.ar.valid <= T_798 - node T_799 = bits(io.tl.acquire.bits.union, 11, 9) - node T_800 = cat(io.tl.acquire.bits.addr_beat, T_799) - node T_801 = cat(io.tl.acquire.bits.addr_block, T_800) - node T_802 = bits(io.tl.acquire.bits.union, 8, 6) - node T_811 = eq(UInt<3>("h07"), T_802) - node T_812 = mux(T_811, UInt<2>("h03"), UInt<3>("h07")) - node T_813 = eq(UInt<3>("h03"), T_802) - node T_814 = mux(T_813, UInt<2>("h03"), T_812) - node T_815 = eq(UInt<3>("h02"), T_802) - node T_816 = mux(T_815, UInt<2>("h02"), T_814) - node T_817 = eq(UInt<3>("h05"), T_802) - node T_818 = mux(T_817, UInt<1>("h01"), T_816) - node T_819 = eq(UInt<3>("h01"), T_802) - node T_820 = mux(T_819, UInt<1>("h01"), T_818) - node T_821 = eq(UInt<3>("h04"), T_802) - node T_822 = mux(T_821, UInt<1>("h00"), T_820) - node T_823 = eq(UInt<3>("h00"), T_802) - node T_824 = mux(T_823, UInt<1>("h00"), T_822) - node T_826 = mux(is_subblock, T_824, UInt<2>("h03")) - node T_829 = mux(is_subblock, UInt<1>("h00"), UInt<3>("h07")) - wire T_842 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} - T_842.user <= UInt<1>("h00") - T_842.id <= UInt<1>("h00") - T_842.region <= UInt<1>("h00") - T_842.qos <= UInt<1>("h00") - T_842.prot <= UInt<1>("h00") - T_842.cache <= UInt<1>("h00") - T_842.lock <= UInt<1>("h00") - T_842.burst <= UInt<1>("h00") - T_842.size <= UInt<1>("h00") - T_842.len <= UInt<1>("h00") - T_842.addr <= UInt<1>("h00") - T_842.id <= io.tl.acquire.bits.client_xact_id - T_842.addr <= T_801 - T_842.len <= T_829 - T_842.size <= T_826 - T_842.burst <= UInt<2>("h01") - T_842.lock <= UInt<1>("h00") - T_842.cache <= UInt<1>("h00") - T_842.prot <= UInt<1>("h00") - T_842.qos <= UInt<1>("h00") - T_842.region <= UInt<1>("h00") - T_842.user <= UInt<1>("h00") - io.nasti.ar.bits <- T_842 - node T_872 = eq(w_inflight, UInt<1>("h00")) - node T_873 = and(put_valid, io.nasti.w.ready) - node T_874 = and(T_873, T_872) - io.nasti.aw.valid <= T_874 - node T_875 = bits(io.tl.acquire.bits.union, 11, 9) - node T_876 = cat(io.tl.acquire.bits.addr_beat, T_875) - node T_877 = cat(io.tl.acquire.bits.addr_block, T_876) - node T_881 = mux(is_multibeat, UInt<3>("h07"), UInt<1>("h00")) - wire T_894 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} - T_894.user <= UInt<1>("h00") - T_894.id <= UInt<1>("h00") - T_894.region <= UInt<1>("h00") - T_894.qos <= UInt<1>("h00") - T_894.prot <= UInt<1>("h00") - T_894.cache <= UInt<1>("h00") - T_894.lock <= UInt<1>("h00") - T_894.burst <= UInt<1>("h00") - T_894.size <= UInt<1>("h00") - T_894.len <= UInt<1>("h00") - T_894.addr <= UInt<1>("h00") - T_894.id <= io.tl.acquire.bits.client_xact_id - T_894.addr <= T_877 - T_894.len <= T_881 - T_894.size <= UInt<2>("h03") - T_894.burst <= UInt<2>("h01") - T_894.lock <= UInt<1>("h00") - T_894.cache <= UInt<4>("h00") - T_894.prot <= UInt<3>("h00") - T_894.qos <= UInt<4>("h00") - T_894.region <= UInt<4>("h00") - T_894.user <= UInt<1>("h00") - io.nasti.aw.bits <- T_894 - node T_923 = and(put_valid, aw_ready) - io.nasti.w.valid <= T_923 - node T_926 = eq(io.tl.acquire.bits.a_type, UInt<3>("h04")) - node T_927 = and(io.tl.acquire.bits.is_builtin_type, T_926) - wire T_930 : UInt<1>[1] - T_930[0] <= UInt<1>("h01") - node T_934 = subw(UInt<8>("h00"), T_930[0]) - wire T_936 : UInt<8>[1] - T_936[0] <= T_934 - node T_940 = eq(io.tl.acquire.bits.a_type, UInt<3>("h03")) - node T_941 = and(io.tl.acquire.bits.is_builtin_type, T_940) - node T_943 = eq(io.tl.acquire.bits.a_type, UInt<3>("h02")) - node T_944 = and(io.tl.acquire.bits.is_builtin_type, T_943) - node T_945 = or(T_941, T_944) - node T_946 = bits(io.tl.acquire.bits.union, 8, 1) - node T_948 = mux(T_945, T_946, UInt<8>("h00")) - node T_949 = mux(T_927, T_936[0], T_948) - node T_950 = and(io.tl.acquire.ready, io.tl.acquire.valid) - node T_951 = and(T_950, is_subblock) - node T_952 = or(tl_wrap_out, T_951) - wire T_958 : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>} - T_958.user <= UInt<1>("h00") - T_958.strb <= UInt<1>("h00") - T_958.last <= UInt<1>("h00") - T_958.data <= UInt<1>("h00") - node T_968 = cat(UInt<1>("h01"), UInt<1>("h01")) - node T_969 = cat(T_968, T_968) - node T_970 = cat(T_969, T_969) - T_958.strb <= T_970 - T_958.data <= io.tl.acquire.bits.data - T_958.last <= T_952 - T_958.user <= UInt<1>("h00") - T_958.strb <= T_949 - io.nasti.w.bits <- T_958 - node T_972 = and(aw_ready, io.nasti.w.ready) - node T_973 = and(roq.io.enq.ready, io.nasti.ar.ready) - node T_974 = mux(has_data, T_972, T_973) - io.tl.acquire.ready <= T_974 - node T_976 = eq(w_inflight, UInt<1>("h00")) - node T_977 = and(io.tl.acquire.ready, io.tl.acquire.valid) - node T_978 = and(T_976, T_977) - node T_979 = and(T_978, is_multibeat) - when T_979 : + node T_793 = and(get_valid, roq.io.enq.ready) + io.nasti.ar.valid <= T_793 + node T_794 = bits(io.tl.acquire.bits.union, 11, 9) + node T_795 = cat(io.tl.acquire.bits.addr_beat, T_794) + node T_796 = cat(io.tl.acquire.bits.addr_block, T_795) + node T_797 = bits(io.tl.acquire.bits.union, 8, 6) + node T_806 = eq(UInt<3>("h07"), T_797) + node T_807 = mux(T_806, UInt<2>("h03"), UInt<3>("h07")) + node T_808 = eq(UInt<3>("h03"), T_797) + node T_809 = mux(T_808, UInt<2>("h03"), T_807) + node T_810 = eq(UInt<3>("h02"), T_797) + node T_811 = mux(T_810, UInt<2>("h02"), T_809) + node T_812 = eq(UInt<3>("h05"), T_797) + node T_813 = mux(T_812, UInt<1>("h01"), T_811) + node T_814 = eq(UInt<3>("h01"), T_797) + node T_815 = mux(T_814, UInt<1>("h01"), T_813) + node T_816 = eq(UInt<3>("h04"), T_797) + node T_817 = mux(T_816, UInt<1>("h00"), T_815) + node T_818 = eq(UInt<3>("h00"), T_797) + node T_819 = mux(T_818, UInt<1>("h00"), T_817) + node T_821 = mux(is_subblock, T_819, UInt<2>("h03")) + node T_824 = mux(is_subblock, UInt<1>("h00"), UInt<3>("h07")) + wire T_837 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} + T_837 is invalid + T_837.id <= io.tl.acquire.bits.client_xact_id + T_837.addr <= T_796 + T_837.len <= T_824 + T_837.size <= T_821 + T_837.burst <= UInt<2>("h01") + T_837.lock <= UInt<1>("h00") + T_837.cache <= UInt<1>("h00") + T_837.prot <= UInt<1>("h00") + T_837.qos <= UInt<1>("h00") + T_837.region <= UInt<1>("h00") + T_837.user <= UInt<1>("h00") + io.nasti.ar.bits <- T_837 + node T_856 = eq(w_inflight, UInt<1>("h00")) + node T_857 = and(put_valid, io.nasti.w.ready) + node T_858 = and(T_857, T_856) + io.nasti.aw.valid <= T_858 + node T_859 = bits(io.tl.acquire.bits.union, 11, 9) + node T_860 = cat(io.tl.acquire.bits.addr_beat, T_859) + node T_861 = cat(io.tl.acquire.bits.addr_block, T_860) + node T_865 = mux(is_multibeat, UInt<3>("h07"), UInt<1>("h00")) + wire T_878 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} + T_878 is invalid + T_878.id <= io.tl.acquire.bits.client_xact_id + T_878.addr <= T_861 + T_878.len <= T_865 + T_878.size <= UInt<2>("h03") + T_878.burst <= UInt<2>("h01") + T_878.lock <= UInt<1>("h00") + T_878.cache <= UInt<4>("h00") + T_878.prot <= UInt<3>("h00") + T_878.qos <= UInt<4>("h00") + T_878.region <= UInt<4>("h00") + T_878.user <= UInt<1>("h00") + io.nasti.aw.bits <- T_878 + node T_896 = and(put_valid, aw_ready) + io.nasti.w.valid <= T_896 + node T_899 = eq(io.tl.acquire.bits.a_type, UInt<3>("h04")) + node T_900 = and(io.tl.acquire.bits.is_builtin_type, T_899) + wire T_903 : UInt<1>[1] + T_903[0] <= UInt<1>("h01") + node T_907 = sub(UInt<8>("h00"), T_903[0]) + node T_908 = tail(T_907, 1) + wire T_910 : UInt<8>[1] + T_910[0] <= T_908 + node T_914 = eq(io.tl.acquire.bits.a_type, UInt<3>("h03")) + node T_915 = and(io.tl.acquire.bits.is_builtin_type, T_914) + node T_917 = eq(io.tl.acquire.bits.a_type, UInt<3>("h02")) + node T_918 = and(io.tl.acquire.bits.is_builtin_type, T_917) + node T_919 = or(T_915, T_918) + node T_920 = bits(io.tl.acquire.bits.union, 8, 1) + node T_922 = mux(T_919, T_920, UInt<8>("h00")) + node T_923 = mux(T_900, T_910[0], T_922) + node T_924 = and(io.tl.acquire.ready, io.tl.acquire.valid) + node T_925 = and(T_924, is_subblock) + node T_926 = or(tl_wrap_out, T_925) + wire T_932 : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>} + T_932 is invalid + node T_938 = cat(UInt<1>("h01"), UInt<1>("h01")) + node T_939 = cat(T_938, T_938) + node T_940 = cat(T_939, T_939) + T_932.strb <= T_940 + T_932.data <= io.tl.acquire.bits.data + T_932.last <= T_926 + T_932.user <= UInt<1>("h00") + T_932.strb <= T_923 + io.nasti.w.bits <- T_932 + node T_942 = and(aw_ready, io.nasti.w.ready) + node T_943 = and(roq.io.enq.ready, io.nasti.ar.ready) + node T_944 = mux(has_data, T_942, T_943) + io.tl.acquire.ready <= T_944 + node T_946 = eq(w_inflight, UInt<1>("h00")) + node T_947 = and(io.tl.acquire.ready, io.tl.acquire.valid) + node T_948 = and(T_946, T_947) + node T_949 = and(T_948, is_multibeat) + when T_949 : w_inflight <= UInt<1>("h01") skip when w_inflight : @@ -16873,108 +12342,83 @@ circuit Top : w_inflight <= UInt<1>("h00") skip skip - node T_982 = and(io.tl.grant.ready, io.tl.grant.valid) - wire T_986 : UInt<3>[1] - T_986[0] <= UInt<3>("h05") - node T_989 = eq(T_986[0], io.tl.grant.bits.g_type) - node T_991 = or(UInt<1>("h00"), T_989) - wire T_993 : UInt<1>[1] - T_993[0] <= UInt<1>("h00") - node T_996 = eq(T_993[0], io.tl.grant.bits.g_type) - node T_998 = or(UInt<1>("h00"), T_996) - node T_999 = mux(io.tl.grant.bits.is_builtin_type, T_991, T_998) - node T_1000 = and(UInt<1>("h01"), T_999) - node T_1001 = and(T_982, T_1000) - reg tl_cnt_in : UInt<3>, clk, reset, UInt<3>("h00") - when T_1001 : - node T_1005 = eq(tl_cnt_in, UInt<3>("h07")) - node T_1007 = and(UInt<1>("h00"), T_1005) - node T_1010 = addw(tl_cnt_in, UInt<1>("h01")) - node T_1011 = mux(T_1007, UInt<1>("h00"), T_1010) - tl_cnt_in <= T_1011 - skip - node tl_wrap_in = and(T_1001, T_1005) + node T_952 = and(io.tl.grant.ready, io.tl.grant.valid) + wire T_956 : UInt<3>[1] + T_956[0] <= UInt<3>("h05") + node T_959 = eq(T_956[0], io.tl.grant.bits.g_type) + node T_961 = or(UInt<1>("h00"), T_959) + wire T_963 : UInt<1>[1] + T_963[0] <= UInt<1>("h00") + node T_966 = eq(T_963[0], io.tl.grant.bits.g_type) + node T_968 = or(UInt<1>("h00"), T_966) + node T_969 = mux(io.tl.grant.bits.is_builtin_type, T_961, T_968) + node T_970 = and(UInt<1>("h01"), T_969) + node T_971 = and(T_952, T_970) + reg tl_cnt_in : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + when T_971 : + node T_975 = eq(tl_cnt_in, UInt<3>("h07")) + node T_977 = and(UInt<1>("h00"), T_975) + node T_980 = add(tl_cnt_in, UInt<1>("h01")) + node T_981 = tail(T_980, 1) + node T_982 = mux(T_977, UInt<1>("h00"), T_981) + tl_cnt_in <= T_982 + skip + node tl_wrap_in = and(T_971, T_975) inst gnt_arb of Arbiter - gnt_arb.io.out.ready <= UInt<1>("h00") - gnt_arb.io.in[0].bits.client_id <= UInt<1>("h00") - gnt_arb.io.in[0].bits.data <= UInt<1>("h00") - gnt_arb.io.in[0].bits.g_type <= UInt<1>("h00") - gnt_arb.io.in[0].bits.is_builtin_type <= UInt<1>("h00") - gnt_arb.io.in[0].bits.manager_xact_id <= UInt<1>("h00") - gnt_arb.io.in[0].bits.client_xact_id <= UInt<1>("h00") - gnt_arb.io.in[0].bits.addr_beat <= UInt<1>("h00") - gnt_arb.io.in[0].valid <= UInt<1>("h00") - gnt_arb.io.in[1].bits.client_id <= UInt<1>("h00") - gnt_arb.io.in[1].bits.data <= UInt<1>("h00") - gnt_arb.io.in[1].bits.g_type <= UInt<1>("h00") - gnt_arb.io.in[1].bits.is_builtin_type <= UInt<1>("h00") - gnt_arb.io.in[1].bits.manager_xact_id <= UInt<1>("h00") - gnt_arb.io.in[1].bits.client_xact_id <= UInt<1>("h00") - gnt_arb.io.in[1].bits.addr_beat <= UInt<1>("h00") - gnt_arb.io.in[1].valid <= UInt<1>("h00") + gnt_arb.io is invalid gnt_arb.clk <= clk gnt_arb.reset <= reset io.tl.grant <- gnt_arb.io.out - node T_1060 = cat(roq.io.deq.data.byteOff, UInt<3>("h00")) - node T_1061 = dshl(io.nasti.r.bits.data, T_1060) - node r_aligned_data = mux(roq.io.deq.data.subblock, T_1061, io.nasti.r.bits.data) + node T_1014 = cat(roq.io.deq.data.byteOff, UInt<3>("h00")) + node T_1015 = dshl(io.nasti.r.bits.data, T_1014) + node r_aligned_data = mux(roq.io.deq.data.subblock, T_1015, io.nasti.r.bits.data) gnt_arb.io.in[0].valid <= io.nasti.r.valid io.nasti.r.ready <= gnt_arb.io.in[0].ready - node T_1066 = mux(roq.io.deq.data.subblock, UInt<3>("h04"), UInt<3>("h05")) - node T_1068 = mux(roq.io.deq.data.subblock, roq.io.deq.data.addr_beat, tl_cnt_in) - wire T_1096 : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} - T_1096.data <= UInt<1>("h00") - T_1096.g_type <= UInt<1>("h00") - T_1096.is_builtin_type <= UInt<1>("h00") - T_1096.manager_xact_id <= UInt<1>("h00") - T_1096.client_xact_id <= UInt<1>("h00") - T_1096.addr_beat <= UInt<1>("h00") - T_1096.is_builtin_type <= UInt<1>("h01") - T_1096.g_type <= T_1066 - T_1096.client_xact_id <= io.nasti.r.bits.id - T_1096.manager_xact_id <= UInt<1>("h00") - T_1096.addr_beat <= T_1068 - T_1096.data <= r_aligned_data - gnt_arb.io.in[0].bits <- T_1096 + node T_1020 = mux(roq.io.deq.data.subblock, UInt<3>("h04"), UInt<3>("h05")) + node T_1022 = mux(roq.io.deq.data.subblock, roq.io.deq.data.addr_beat, tl_cnt_in) + wire T_1050 : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} + T_1050 is invalid + T_1050.is_builtin_type <= UInt<1>("h01") + T_1050.g_type <= T_1020 + T_1050.client_xact_id <= io.nasti.r.bits.id + T_1050.manager_xact_id <= UInt<1>("h00") + T_1050.addr_beat <= T_1022 + T_1050.data <= r_aligned_data + gnt_arb.io.in[0].bits <- T_1050 gnt_arb.io.in[1].valid <= io.nasti.b.valid io.nasti.b.ready <= gnt_arb.io.in[1].ready - wire T_1161 : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} - T_1161.data <= UInt<1>("h00") - T_1161.g_type <= UInt<1>("h00") - T_1161.is_builtin_type <= UInt<1>("h00") - T_1161.manager_xact_id <= UInt<1>("h00") - T_1161.client_xact_id <= UInt<1>("h00") - T_1161.addr_beat <= UInt<1>("h00") - T_1161.is_builtin_type <= UInt<1>("h01") - T_1161.g_type <= UInt<3>("h03") - T_1161.client_xact_id <= io.nasti.b.bits.id - T_1161.manager_xact_id <= UInt<1>("h00") - T_1161.addr_beat <= UInt<1>("h00") - T_1161.data <= UInt<1>("h00") - gnt_arb.io.in[1].bits <- T_1161 - node T_1195 = eq(io.nasti.r.valid, UInt<1>("h00")) - node T_1197 = eq(io.nasti.r.bits.resp, UInt<1>("h00")) - node T_1198 = or(T_1195, T_1197) - node T_1200 = eq(reset, UInt<1>("h00")) - when T_1200 : - node T_1202 = eq(T_1198, UInt<1>("h00")) - when T_1202 : - node T_1204 = eq(reset, UInt<1>("h00")) - when T_1204 : + wire T_1109 : {addr_beat : UInt<3>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<64>} + T_1109 is invalid + T_1109.is_builtin_type <= UInt<1>("h01") + T_1109.g_type <= UInt<3>("h03") + T_1109.client_xact_id <= io.nasti.b.bits.id + T_1109.manager_xact_id <= UInt<1>("h00") + T_1109.addr_beat <= UInt<1>("h00") + T_1109.data <= UInt<1>("h00") + gnt_arb.io.in[1].bits <- T_1109 + node T_1137 = eq(io.nasti.r.valid, UInt<1>("h00")) + node T_1139 = eq(io.nasti.r.bits.resp, UInt<1>("h00")) + node T_1140 = or(T_1137, T_1139) + node T_1142 = eq(reset, UInt<1>("h00")) + when T_1142 : + node T_1144 = eq(T_1140, UInt<1>("h00")) + when T_1144 : + node T_1146 = eq(reset, UInt<1>("h00")) + when T_1146 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): NASTI read error") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1206 = eq(io.nasti.b.valid, UInt<1>("h00")) - node T_1208 = eq(io.nasti.b.bits.resp, UInt<1>("h00")) - node T_1209 = or(T_1206, T_1208) - node T_1211 = eq(reset, UInt<1>("h00")) - when T_1211 : - node T_1213 = eq(T_1209, UInt<1>("h00")) - when T_1213 : - node T_1215 = eq(reset, UInt<1>("h00")) - when T_1215 : + node T_1148 = eq(io.nasti.b.valid, UInt<1>("h00")) + node T_1150 = eq(io.nasti.b.bits.resp, UInt<1>("h00")) + node T_1151 = or(T_1148, T_1150) + node T_1153 = eq(reset, UInt<1>("h00")) + when T_1153 : + node T_1155 = eq(T_1151, UInt<1>("h00")) + when T_1155 : + node T_1157 = eq(reset, UInt<1>("h00")) + when T_1157 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): NASTI write error") skip stop(clk, UInt<1>(1), 1) @@ -16986,31 +12430,7 @@ circuit Top : input reset : UInt<1> output io : {flip in : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, out : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}} - io.out.release.bits.data <= UInt<1>("h00") - io.out.release.bits.r_type <= UInt<1>("h00") - io.out.release.bits.voluntary <= UInt<1>("h00") - io.out.release.bits.client_xact_id <= UInt<1>("h00") - io.out.release.bits.addr_block <= UInt<1>("h00") - io.out.release.bits.addr_beat <= UInt<1>("h00") - io.out.release.valid <= UInt<1>("h00") - io.out.probe.ready <= UInt<1>("h00") - io.out.grant.ready <= UInt<1>("h00") - io.out.acquire.bits.data <= UInt<1>("h00") - io.out.acquire.bits.union <= UInt<1>("h00") - io.out.acquire.bits.a_type <= UInt<1>("h00") - io.out.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.out.acquire.bits.addr_beat <= UInt<1>("h00") - io.out.acquire.bits.client_xact_id <= UInt<1>("h00") - io.out.acquire.bits.addr_block <= UInt<1>("h00") - io.out.acquire.valid <= UInt<1>("h00") - io.in.grant.bits.data <= UInt<1>("h00") - io.in.grant.bits.g_type <= UInt<1>("h00") - io.in.grant.bits.is_builtin_type <= UInt<1>("h00") - io.in.grant.bits.manager_xact_id <= UInt<1>("h00") - io.in.grant.bits.client_xact_id <= UInt<1>("h00") - io.in.grant.bits.addr_beat <= UInt<1>("h00") - io.in.grant.valid <= UInt<1>("h00") - io.in.acquire.ready <= UInt<1>("h00") + io is invalid io.out.acquire <- io.in.acquire io.in.grant <- io.out.grant io.out.probe.ready <= UInt<1>("h01") @@ -17021,35 +12441,7 @@ circuit Top : input reset : UInt<1> output io : {flip inner : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}, outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<4>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}} - io.outer.release.bits.data <= UInt<1>("h00") - io.outer.release.bits.r_type <= UInt<1>("h00") - io.outer.release.bits.voluntary <= UInt<1>("h00") - io.outer.release.bits.client_xact_id <= UInt<1>("h00") - io.outer.release.bits.addr_block <= UInt<1>("h00") - io.outer.release.bits.addr_beat <= UInt<1>("h00") - io.outer.release.valid <= UInt<1>("h00") - io.outer.probe.ready <= UInt<1>("h00") - io.outer.grant.ready <= UInt<1>("h00") - io.outer.acquire.bits.data <= UInt<1>("h00") - io.outer.acquire.bits.union <= UInt<1>("h00") - io.outer.acquire.bits.a_type <= UInt<1>("h00") - io.outer.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.outer.acquire.bits.addr_beat <= UInt<1>("h00") - io.outer.acquire.bits.client_xact_id <= UInt<1>("h00") - io.outer.acquire.bits.addr_block <= UInt<1>("h00") - io.outer.acquire.valid <= UInt<1>("h00") - io.inner.release.ready <= UInt<1>("h00") - io.inner.probe.bits.p_type <= UInt<1>("h00") - io.inner.probe.bits.addr_block <= UInt<1>("h00") - io.inner.probe.valid <= UInt<1>("h00") - io.inner.grant.bits.data <= UInt<1>("h00") - io.inner.grant.bits.g_type <= UInt<1>("h00") - io.inner.grant.bits.is_builtin_type <= UInt<1>("h00") - io.inner.grant.bits.manager_xact_id <= UInt<1>("h00") - io.inner.grant.bits.client_xact_id <= UInt<1>("h00") - io.inner.grant.bits.addr_beat <= UInt<1>("h00") - io.inner.grant.valid <= UInt<1>("h00") - io.inner.acquire.ready <= UInt<1>("h00") + io is invalid io.outer.acquire <- io.inner.acquire io.inner.probe <- io.outer.probe io.outer.release <- io.inner.release @@ -17060,17 +12452,11 @@ circuit Top : input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, count : UInt<4>} - io.count <= UInt<1>("h00") - io.deq.bits.user <= UInt<1>("h00") - io.deq.bits.strb <= UInt<1>("h00") - io.deq.bits.last <= UInt<1>("h00") - io.deq.bits.data <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}[8] - reg T_62 : UInt<3>, clk, reset, UInt<3>("h00") - reg T_64 : UInt<3>, clk, reset, UInt<3>("h00") - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg T_62 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + reg T_64 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(T_62, T_64) node T_69 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_69) @@ -17088,58 +12474,50 @@ circuit Top : T_83 <- io.enq.bits node T_89 = eq(T_62, UInt<3>("h07")) node T_91 = and(UInt<1>("h00"), T_89) - node T_94 = addw(T_62, UInt<1>("h01")) - node T_95 = mux(T_91, UInt<1>("h00"), T_94) - T_62 <= T_95 + node T_94 = add(T_62, UInt<1>("h01")) + node T_95 = tail(T_94, 1) + node T_96 = mux(T_91, UInt<1>("h00"), T_95) + T_62 <= T_96 skip when do_deq : - node T_97 = eq(T_64, UInt<3>("h07")) - node T_99 = and(UInt<1>("h00"), T_97) - node T_102 = addw(T_64, UInt<1>("h01")) - node T_103 = mux(T_99, UInt<1>("h00"), T_102) - T_64 <= T_103 - skip - node T_104 = neq(do_enq, do_deq) - when T_104 : + node T_98 = eq(T_64, UInt<3>("h07")) + node T_100 = and(UInt<1>("h00"), T_98) + node T_103 = add(T_64, UInt<1>("h01")) + node T_104 = tail(T_103, 1) + node T_105 = mux(T_100, UInt<1>("h00"), T_104) + T_64 <= T_105 + skip + node T_106 = neq(do_enq, do_deq) + when T_106 : maybe_full <= do_enq skip - node T_106 = eq(empty, UInt<1>("h00")) - node T_108 = and(UInt<1>("h00"), io.enq.valid) - node T_109 = or(T_106, T_108) - io.deq.valid <= T_109 - node T_111 = eq(full, UInt<1>("h00")) - node T_113 = and(UInt<1>("h00"), io.deq.ready) - node T_114 = or(T_111, T_113) - io.enq.ready <= T_114 - infer mport T_115 = ram[T_64], clk - wire T_125 : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>} - T_125 <- T_115 - when maybe_flow : - T_125 <- io.enq.bits - skip - io.deq.bits <- T_125 - node ptr_diff = subw(T_62, T_64) - node T_131 = and(maybe_full, ptr_match) - node T_132 = cat(T_131, ptr_diff) - io.count <= T_132 + node T_108 = eq(empty, UInt<1>("h00")) + node T_110 = and(UInt<1>("h00"), io.enq.valid) + node T_111 = or(T_108, T_110) + io.deq.valid <= T_111 + node T_113 = eq(full, UInt<1>("h00")) + node T_115 = and(UInt<1>("h00"), io.deq.ready) + node T_116 = or(T_113, T_115) + io.enq.ready <= T_116 + infer mport T_117 = ram[T_64], clk + node T_122 = mux(maybe_flow, io.enq.bits, T_117) + io.deq.bits <- T_122 + node T_127 = sub(T_62, T_64) + node ptr_diff = tail(T_127, 1) + node T_129 = and(maybe_full, ptr_match) + node T_130 = cat(T_129, ptr_diff) + io.count <= T_130 module Queue_75 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, count : UInt<4>} - io.count <= UInt<1>("h00") - io.deq.bits.user <= UInt<1>("h00") - io.deq.bits.id <= UInt<1>("h00") - io.deq.bits.last <= UInt<1>("h00") - io.deq.bits.data <= UInt<1>("h00") - io.deq.bits.resp <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}[8] - reg T_71 : UInt<3>, clk, reset, UInt<3>("h00") - reg T_73 : UInt<3>, clk, reset, UInt<3>("h00") - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg T_71 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + reg T_73 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(T_71, T_73) node T_78 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_78) @@ -17157,56 +12535,50 @@ circuit Top : T_92 <- io.enq.bits node T_99 = eq(T_71, UInt<3>("h07")) node T_101 = and(UInt<1>("h00"), T_99) - node T_104 = addw(T_71, UInt<1>("h01")) - node T_105 = mux(T_101, UInt<1>("h00"), T_104) - T_71 <= T_105 + node T_104 = add(T_71, UInt<1>("h01")) + node T_105 = tail(T_104, 1) + node T_106 = mux(T_101, UInt<1>("h00"), T_105) + T_71 <= T_106 skip when do_deq : - node T_107 = eq(T_73, UInt<3>("h07")) - node T_109 = and(UInt<1>("h00"), T_107) - node T_112 = addw(T_73, UInt<1>("h01")) - node T_113 = mux(T_109, UInt<1>("h00"), T_112) - T_73 <= T_113 - skip - node T_114 = neq(do_enq, do_deq) - when T_114 : + node T_108 = eq(T_73, UInt<3>("h07")) + node T_110 = and(UInt<1>("h00"), T_108) + node T_113 = add(T_73, UInt<1>("h01")) + node T_114 = tail(T_113, 1) + node T_115 = mux(T_110, UInt<1>("h00"), T_114) + T_73 <= T_115 + skip + node T_116 = neq(do_enq, do_deq) + when T_116 : maybe_full <= do_enq skip - node T_116 = eq(empty, UInt<1>("h00")) - node T_118 = and(UInt<1>("h00"), io.enq.valid) - node T_119 = or(T_116, T_118) - io.deq.valid <= T_119 - node T_121 = eq(full, UInt<1>("h00")) - node T_123 = and(UInt<1>("h00"), io.deq.ready) - node T_124 = or(T_121, T_123) - io.enq.ready <= T_124 - infer mport T_125 = ram[T_73], clk - wire T_137 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} - T_137 <- T_125 - when maybe_flow : - T_137 <- io.enq.bits - skip - io.deq.bits <- T_137 - node ptr_diff = subw(T_71, T_73) - node T_144 = and(maybe_full, ptr_match) - node T_145 = cat(T_144, ptr_diff) - io.count <= T_145 + node T_118 = eq(empty, UInt<1>("h00")) + node T_120 = and(UInt<1>("h00"), io.enq.valid) + node T_121 = or(T_118, T_120) + io.deq.valid <= T_121 + node T_123 = eq(full, UInt<1>("h00")) + node T_125 = and(UInt<1>("h00"), io.deq.ready) + node T_126 = or(T_123, T_125) + io.enq.ready <= T_126 + infer mport T_127 = ram[T_73], clk + node T_133 = mux(maybe_flow, io.enq.bits, T_127) + io.deq.bits <- T_133 + node T_139 = sub(T_71, T_73) + node ptr_diff = tail(T_139, 1) + node T_141 = and(maybe_full, ptr_match) + node T_142 = cat(T_141, ptr_diff) + io.count <= T_142 module Queue_76 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, count : UInt<2>} - io.count <= UInt<1>("h00") - io.deq.bits.user <= UInt<1>("h00") - io.deq.bits.id <= UInt<1>("h00") - io.deq.bits.resp <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}[2] - reg T_53 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_55 : UInt<1>, clk, reset, UInt<1>("h00") - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg T_53 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_55 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(T_53, T_55) node T_60 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_60) @@ -17224,165 +12596,123 @@ circuit Top : T_74 <- io.enq.bits node T_79 = eq(T_53, UInt<1>("h01")) node T_81 = and(UInt<1>("h00"), T_79) - node T_84 = addw(T_53, UInt<1>("h01")) - node T_85 = mux(T_81, UInt<1>("h00"), T_84) - T_53 <= T_85 + node T_84 = add(T_53, UInt<1>("h01")) + node T_85 = tail(T_84, 1) + node T_86 = mux(T_81, UInt<1>("h00"), T_85) + T_53 <= T_86 skip when do_deq : - node T_87 = eq(T_55, UInt<1>("h01")) - node T_89 = and(UInt<1>("h00"), T_87) - node T_92 = addw(T_55, UInt<1>("h01")) - node T_93 = mux(T_89, UInt<1>("h00"), T_92) - T_55 <= T_93 - skip - node T_94 = neq(do_enq, do_deq) - when T_94 : + node T_88 = eq(T_55, UInt<1>("h01")) + node T_90 = and(UInt<1>("h00"), T_88) + node T_93 = add(T_55, UInt<1>("h01")) + node T_94 = tail(T_93, 1) + node T_95 = mux(T_90, UInt<1>("h00"), T_94) + T_55 <= T_95 + skip + node T_96 = neq(do_enq, do_deq) + when T_96 : maybe_full <= do_enq skip - node T_96 = eq(empty, UInt<1>("h00")) - node T_98 = and(UInt<1>("h00"), io.enq.valid) - node T_99 = or(T_96, T_98) - io.deq.valid <= T_99 - node T_101 = eq(full, UInt<1>("h00")) - node T_103 = and(UInt<1>("h00"), io.deq.ready) - node T_104 = or(T_101, T_103) - io.enq.ready <= T_104 - infer mport T_105 = ram[T_55], clk - wire T_113 : {resp : UInt<2>, id : UInt<5>, user : UInt<1>} - T_113 <- T_105 - when maybe_flow : - T_113 <- io.enq.bits - skip - io.deq.bits <- T_113 - node ptr_diff = subw(T_53, T_55) - node T_118 = and(maybe_full, ptr_match) - node T_119 = cat(T_118, ptr_diff) - io.count <= T_119 + node T_98 = eq(empty, UInt<1>("h00")) + node T_100 = and(UInt<1>("h00"), io.enq.valid) + node T_101 = or(T_98, T_100) + io.deq.valid <= T_101 + node T_103 = eq(full, UInt<1>("h00")) + node T_105 = and(UInt<1>("h00"), io.deq.ready) + node T_106 = or(T_103, T_105) + io.enq.ready <= T_106 + infer mport T_107 = ram[T_55], clk + node T_111 = mux(maybe_flow, io.enq.bits, T_107) + io.deq.bits <- T_111 + node T_115 = sub(T_53, T_55) + node ptr_diff = tail(T_115, 1) + node T_117 = and(maybe_full, ptr_match) + node T_118 = cat(T_117, ptr_diff) + io.count <= T_118 module RTC : input clk : Clock input reset : UInt<1> output io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} - io.r.ready <= UInt<1>("h00") - io.ar.bits.user <= UInt<1>("h00") - io.ar.bits.id <= UInt<1>("h00") - io.ar.bits.region <= UInt<1>("h00") - io.ar.bits.qos <= UInt<1>("h00") - io.ar.bits.prot <= UInt<1>("h00") - io.ar.bits.cache <= UInt<1>("h00") - io.ar.bits.lock <= UInt<1>("h00") - io.ar.bits.burst <= UInt<1>("h00") - io.ar.bits.size <= UInt<1>("h00") - io.ar.bits.len <= UInt<1>("h00") - io.ar.bits.addr <= UInt<1>("h00") - io.ar.valid <= UInt<1>("h00") - io.b.ready <= UInt<1>("h00") - io.w.bits.user <= UInt<1>("h00") - io.w.bits.strb <= UInt<1>("h00") - io.w.bits.last <= UInt<1>("h00") - io.w.bits.data <= UInt<1>("h00") - io.w.valid <= UInt<1>("h00") - io.aw.bits.user <= UInt<1>("h00") - io.aw.bits.id <= UInt<1>("h00") - io.aw.bits.region <= UInt<1>("h00") - io.aw.bits.qos <= UInt<1>("h00") - io.aw.bits.prot <= UInt<1>("h00") - io.aw.bits.cache <= UInt<1>("h00") - io.aw.bits.lock <= UInt<1>("h00") - io.aw.bits.burst <= UInt<1>("h00") - io.aw.bits.size <= UInt<1>("h00") - io.aw.bits.len <= UInt<1>("h00") - io.aw.bits.addr <= UInt<1>("h00") - io.aw.valid <= UInt<1>("h00") + io is invalid wire addrTable : UInt<31>[1] addrTable[0] <= UInt<31>("h04000b808") - reg rtc : UInt<64>, clk, reset, UInt<64>("h00") - reg T_217 : UInt<7>, clk, reset, UInt<7>("h00") + reg rtc : UInt<64>, clk with : (reset => (reset, UInt<64>("h00"))) + reg T_217 : UInt<7>, clk with : (reset => (reset, UInt<7>("h00"))) node rtc_tick = eq(T_217, UInt<7>("h063")) node T_221 = and(UInt<1>("h01"), rtc_tick) - node T_224 = addw(T_217, UInt<1>("h01")) - node T_225 = mux(T_221, UInt<1>("h00"), T_224) - T_217 <= T_225 - reg sending_addr : UInt<1>, clk, reset, UInt<1>("h00") - reg sending_data : UInt<1>, clk, reset, UInt<1>("h00") - wire T_232 : UInt<1>[1] - T_232[0] <= UInt<1>("h01") - reg send_acked : UInt<1>[1], clk, reset, T_232 + node T_224 = add(T_217, UInt<1>("h01")) + node T_225 = tail(T_224, 1) + node T_226 = mux(T_221, UInt<1>("h00"), T_225) + T_217 <= T_226 + reg sending_addr : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg sending_data : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + wire T_233 : UInt<1>[1] + T_233[0] <= UInt<1>("h01") + reg send_acked : UInt<1>[1], clk with : (reset => (reset, T_233)) wire coreId : UInt<1> - coreId <= UInt<1>("h00") + coreId is invalid when rtc_tick : - node T_244 = addw(rtc, UInt<1>("h01")) - rtc <= T_244 - wire T_247 : UInt<1>[1] - T_247[0] <= UInt<1>("h00") - send_acked <= T_247 + node T_244 = add(rtc, UInt<1>("h01")) + node T_245 = tail(T_244, 1) + rtc <= T_245 + wire T_248 : UInt<1>[1] + T_248[0] <= UInt<1>("h00") + send_acked <= T_248 sending_addr <= UInt<1>("h01") sending_data <= UInt<1>("h01") skip - node T_252 = and(io.aw.ready, io.aw.valid) - when T_252 : + node T_253 = and(io.aw.ready, io.aw.valid) + when T_253 : sending_addr <= UInt<1>("h00") skip - node T_254 = and(io.w.ready, io.w.valid) - when T_254 : + node T_255 = and(io.w.ready, io.w.valid) + when T_255 : sending_addr <= UInt<1>("h00") skip coreId <= UInt<1>("h00") - node T_257 = and(io.b.ready, io.b.valid) - when T_257 : + node T_258 = and(io.b.ready, io.b.valid) + when T_258 : send_acked[io.b.bits.id] <= UInt<1>("h01") skip io.aw.valid <= sending_addr - wire T_275 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} - T_275.user <= UInt<1>("h00") - T_275.id <= UInt<1>("h00") - T_275.region <= UInt<1>("h00") - T_275.qos <= UInt<1>("h00") - T_275.prot <= UInt<1>("h00") - T_275.cache <= UInt<1>("h00") - T_275.lock <= UInt<1>("h00") - T_275.burst <= UInt<1>("h00") - T_275.size <= UInt<1>("h00") - T_275.len <= UInt<1>("h00") - T_275.addr <= UInt<1>("h00") - T_275.id <= coreId - T_275.addr <= addrTable[coreId] - T_275.len <= UInt<1>("h00") - T_275.size <= UInt<2>("h03") - T_275.burst <= UInt<2>("h01") - T_275.lock <= UInt<1>("h00") - T_275.cache <= UInt<4>("h00") - T_275.prot <= UInt<3>("h00") - T_275.qos <= UInt<4>("h00") - T_275.region <= UInt<4>("h00") - T_275.user <= UInt<1>("h00") - io.aw.bits <- T_275 + wire T_276 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} + T_276 is invalid + T_276.id <= coreId + T_276.addr <= addrTable[coreId] + T_276.len <= UInt<1>("h00") + T_276.size <= UInt<2>("h03") + T_276.burst <= UInt<2>("h01") + T_276.lock <= UInt<1>("h00") + T_276.cache <= UInt<4>("h00") + T_276.prot <= UInt<3>("h00") + T_276.qos <= UInt<4>("h00") + T_276.region <= UInt<4>("h00") + T_276.user <= UInt<1>("h00") + io.aw.bits <- T_276 io.w.valid <= sending_data - wire T_310 : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>} - T_310.user <= UInt<1>("h00") - T_310.strb <= UInt<1>("h00") - T_310.last <= UInt<1>("h00") - T_310.data <= UInt<1>("h00") - node T_320 = cat(UInt<1>("h01"), UInt<1>("h01")) - node T_321 = cat(T_320, T_320) - node T_322 = cat(T_321, T_321) - T_310.strb <= T_322 - T_310.data <= rtc - T_310.last <= UInt<1>("h01") - T_310.user <= UInt<1>("h00") - io.w.bits <- T_310 + wire T_300 : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>} + T_300 is invalid + node T_306 = cat(UInt<1>("h01"), UInt<1>("h01")) + node T_307 = cat(T_306, T_306) + node T_308 = cat(T_307, T_307) + T_300.strb <= T_308 + T_300.data <= rtc + T_300.last <= UInt<1>("h01") + T_300.user <= UInt<1>("h00") + io.w.bits <- T_300 io.b.ready <= UInt<1>("h01") io.ar.valid <= UInt<1>("h00") io.r.ready <= UInt<1>("h00") - node T_328 = eq(rtc_tick, UInt<1>("h00")) - node T_329 = or(T_328, send_acked[0]) - node T_331 = eq(reset, UInt<1>("h00")) - when T_331 : - node T_333 = eq(T_329, UInt<1>("h00")) - when T_333 : - node T_335 = eq(reset, UInt<1>("h00")) - when T_335 : + node T_314 = eq(rtc_tick, UInt<1>("h00")) + node T_315 = or(T_314, send_acked[0]) + node T_317 = eq(reset, UInt<1>("h00")) + when T_317 : + node T_319 = eq(T_315, UInt<1>("h00")) + when T_319 : + node T_321 = eq(reset, UInt<1>("h00")) + when T_321 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Not all clocks were updated for rtc tick") skip stop(clk, UInt<1>(1), 1) @@ -17394,30 +12724,19 @@ circuit Top : input reset : UInt<1> output io : {flip ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io.smi.resp.ready <= UInt<1>("h00") - io.smi.req.bits.data <= UInt<1>("h00") - io.smi.req.bits.addr <= UInt<1>("h00") - io.smi.req.bits.rw <= UInt<1>("h00") - io.smi.req.valid <= UInt<1>("h00") - io.r.bits.user <= UInt<1>("h00") - io.r.bits.id <= UInt<1>("h00") - io.r.bits.last <= UInt<1>("h00") - io.r.bits.data <= UInt<1>("h00") - io.r.bits.resp <= UInt<1>("h00") - io.r.valid <= UInt<1>("h00") - io.ar.ready <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") - reg nWords : UInt<1>, clk, UInt<1>("h00"), nWords - reg nBeats : UInt<8>, clk, UInt<1>("h00"), nBeats - reg addr : UInt<12>, clk, UInt<1>("h00"), addr - reg id : UInt<5>, clk, UInt<1>("h00"), id - reg byteOff : UInt<3>, clk, UInt<1>("h00"), byteOff - reg sendInd : UInt<1>, clk, reset, UInt<1>("h00") - reg recvInd : UInt<1>, clk, reset, UInt<1>("h00") - reg sendDone : UInt<1>, clk, reset, UInt<1>("h00") + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + reg nWords : UInt<1>, clk + reg nBeats : UInt<8>, clk + reg addr : UInt<12>, clk + reg id : UInt<5>, clk + reg byteOff : UInt<3>, clk + reg sendInd : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg recvInd : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg sendDone : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) wire T_141 : UInt<64>[1] T_141[0] <= UInt<64>("h00") - reg buffer : UInt<64>[1], clk, reset, T_141 + reg buffer : UInt<64>[1], clk with : (reset => (reset, T_141)) node T_149 = eq(state, UInt<1>("h00")) io.ar.ready <= T_149 node T_150 = eq(state, UInt<1>("h01")) @@ -17432,51 +12751,52 @@ circuit Top : io.r.valid <= T_156 node T_158 = eq(nBeats, UInt<1>("h00")) wire T_166 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} - T_166.user <= UInt<1>("h00") - T_166.id <= UInt<1>("h00") - T_166.last <= UInt<1>("h00") - T_166.data <= UInt<1>("h00") - T_166.resp <= UInt<1>("h00") + T_166 is invalid T_166.id <= id T_166.data <= buffer[0] T_166.last <= T_158 T_166.resp <= UInt<1>("h00") T_166.user <= UInt<1>("h00") io.r.bits <- T_166 - node T_178 = and(io.ar.ready, io.ar.valid) - when T_178 : - node T_180 = lt(io.ar.bits.size, UInt<2>("h03")) - when T_180 : + node T_173 = and(io.ar.ready, io.ar.valid) + when T_173 : + node T_175 = lt(io.ar.bits.size, UInt<2>("h03")) + when T_175 : nWords <= UInt<1>("h00") - node T_182 = bits(io.ar.bits.addr, 2, 0) - byteOff <= T_182 - skip - node T_184 = eq(T_180, UInt<1>("h00")) - when T_184 : - node T_187 = subw(io.ar.bits.size, UInt<2>("h03")) - node T_188 = dshl(UInt<1>("h01"), T_187) - node T_190 = subw(T_188, UInt<1>("h01")) - nWords <= T_190 + node T_177 = bits(io.ar.bits.addr, 2, 0) + byteOff <= T_177 + skip + node T_179 = eq(T_175, UInt<1>("h00")) + when T_179 : + node T_182 = sub(io.ar.bits.size, UInt<2>("h03")) + node T_183 = tail(T_182, 1) + node T_184 = dshl(UInt<1>("h01"), T_183) + node T_186 = sub(T_184, UInt<1>("h01")) + node T_187 = tail(T_186, 1) + nWords <= T_187 byteOff <= UInt<1>("h00") skip nBeats <= io.ar.bits.len - node T_192 = bits(io.ar.bits.addr, 14, 3) - addr <= T_192 + node T_189 = bits(io.ar.bits.addr, 14, 3) + addr <= T_189 id <= io.ar.bits.id state <= UInt<1>("h01") skip - node T_193 = and(io.smi.req.ready, io.smi.req.valid) - when T_193 : - node T_195 = addw(addr, UInt<1>("h01")) - addr <= T_195 - node T_197 = addw(sendInd, UInt<1>("h01")) - sendInd <= T_197 - node T_198 = eq(sendInd, nWords) - sendDone <= T_198 - skip - node T_199 = and(io.smi.resp.ready, io.smi.resp.valid) - when T_199 : - node T_201 = addw(recvInd, UInt<1>("h01")) + node T_190 = and(io.smi.req.ready, io.smi.req.valid) + when T_190 : + node T_192 = add(addr, UInt<1>("h01")) + node T_193 = tail(T_192, 1) + addr <= T_193 + node T_195 = add(sendInd, UInt<1>("h01")) + node T_196 = tail(T_195, 1) + sendInd <= T_196 + node T_197 = eq(sendInd, nWords) + sendDone <= T_197 + skip + node T_198 = and(io.smi.resp.ready, io.smi.resp.valid) + when T_198 : + node T_200 = add(recvInd, UInt<1>("h01")) + node T_201 = tail(T_200, 1) recvInd <= T_201 node T_204 = cat(byteOff, UInt<3>("h00")) node T_205 = dshr(io.smi.resp.bits, T_204) @@ -17492,10 +12812,11 @@ circuit Top : sendInd <= UInt<1>("h00") sendDone <= UInt<1>("h00") buffer[0] <= UInt<1>("h00") - node T_213 = subw(nBeats, UInt<1>("h01")) - nBeats <= T_213 - node T_214 = mux(io.r.bits.last, UInt<1>("h00"), UInt<1>("h01")) - state <= T_214 + node T_213 = sub(nBeats, UInt<1>("h01")) + node T_214 = tail(T_213, 1) + nBeats <= T_214 + node T_215 = mux(io.r.bits.last, UInt<1>("h00"), UInt<1>("h01")) + state <= T_215 skip module SmiIONastiWriteIOConverter : @@ -17503,17 +12824,7 @@ circuit Top : input reset : UInt<1> output io : {flip aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io.smi.resp.ready <= UInt<1>("h00") - io.smi.req.bits.data <= UInt<1>("h00") - io.smi.req.bits.addr <= UInt<1>("h00") - io.smi.req.bits.rw <= UInt<1>("h00") - io.smi.req.valid <= UInt<1>("h00") - io.b.bits.user <= UInt<1>("h00") - io.b.bits.id <= UInt<1>("h00") - io.b.bits.resp <= UInt<1>("h00") - io.b.valid <= UInt<1>("h00") - io.w.ready <= UInt<1>("h00") - io.aw.ready <= UInt<1>("h00") + io is invalid node T_144 = eq(io.aw.valid, UInt<1>("h00")) node T_146 = geq(io.aw.bits.size, UInt<2>("h03")) node T_147 = or(T_144, T_146) @@ -17528,19 +12839,19 @@ circuit Top : stop(clk, UInt<1>(1), 1) skip skip - reg id : UInt<5>, clk, UInt<1>("h00"), id - reg addr : UInt<12>, clk, UInt<1>("h00"), addr - reg size : UInt<3>, clk, UInt<1>("h00"), size - reg strb : UInt<1>, clk, UInt<1>("h00"), strb - reg data : UInt<64>, clk, UInt<1>("h00"), data - reg last : UInt<1>, clk, UInt<1>("h00"), last - reg state : UInt<?>, clk, reset, UInt<1>("h00") + reg id : UInt<5>, clk + reg addr : UInt<12>, clk + reg size : UInt<3>, clk + reg strb : UInt<1>, clk + reg data : UInt<64>, clk + reg last : UInt<1>, clk + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) node T_173 = eq(state, UInt<1>("h00")) io.aw.ready <= T_173 node T_174 = eq(state, UInt<1>("h01")) io.w.ready <= T_174 node T_175 = eq(state, UInt<2>("h02")) - node T_176 = bit(strb, 0) + node T_176 = bits(strb, 0, 0) node T_177 = and(T_175, T_176) io.smi.req.valid <= T_177 io.smi.req.bits.rw <= UInt<1>("h01") @@ -17552,64 +12863,64 @@ circuit Top : node T_181 = eq(state, UInt<3>("h04")) io.b.valid <= T_181 wire T_187 : {resp : UInt<2>, id : UInt<5>, user : UInt<1>} - T_187.user <= UInt<1>("h00") - T_187.id <= UInt<1>("h00") - T_187.resp <= UInt<1>("h00") + T_187 is invalid T_187.id <= id T_187.resp <= UInt<1>("h00") T_187.user <= UInt<1>("h00") io.b.bits <- T_187 - node T_196 = and(io.aw.ready, io.aw.valid) - when T_196 : - node T_197 = bits(io.aw.bits.addr, 14, 3) - addr <= T_197 + node T_193 = and(io.aw.ready, io.aw.valid) + when T_193 : + node T_194 = bits(io.aw.bits.addr, 14, 3) + addr <= T_194 id <= io.aw.bits.id size <= io.aw.bits.size last <= UInt<1>("h00") state <= UInt<1>("h01") skip - node T_199 = and(io.w.ready, io.w.valid) - when T_199 : + node T_196 = and(io.w.ready, io.w.valid) + when T_196 : last <= io.w.bits.last - node T_202 = dshl(UInt<1>("h01"), size) - node T_203 = dshl(UInt<1>("h01"), T_202) - node T_205 = subw(T_203, UInt<1>("h01")) - node T_206 = and(T_205, io.w.bits.strb) - node T_207 = bit(T_206, 0) - wire T_209 : UInt<1>[1] - T_209[0] <= T_207 - strb <= T_209[0] + node T_199 = dshl(UInt<1>("h01"), size) + node T_200 = dshl(UInt<1>("h01"), T_199) + node T_202 = sub(T_200, UInt<1>("h01")) + node T_203 = tail(T_202, 1) + node T_204 = and(T_203, io.w.bits.strb) + node T_205 = bits(T_204, 0, 0) + wire T_207 : UInt<1>[1] + T_207[0] <= T_205 + strb <= T_207[0] data <= io.w.bits.data state <= UInt<2>("h02") skip - node T_212 = eq(state, UInt<2>("h02")) - when T_212 : - node T_214 = eq(strb, UInt<1>("h00")) - when T_214 : - node T_215 = mux(last, UInt<2>("h03"), UInt<1>("h01")) - state <= T_215 - skip - node T_216 = bit(strb, 0) - node T_218 = eq(T_216, UInt<1>("h00")) - node T_219 = or(io.smi.req.ready, T_218) - node T_221 = eq(T_214, UInt<1>("h00")) - node T_222 = and(T_221, T_219) - when T_222 : - node T_223 = dshr(strb, UInt<1>("h01")) - strb <= T_223 - node T_225 = cat(UInt<1>("h01"), UInt<6>("h00")) - node T_226 = dshr(data, T_225) - data <= T_226 - node T_227 = addw(addr, UInt<1>("h01")) - addr <= T_227 - skip - skip - node T_228 = and(io.smi.resp.ready, io.smi.resp.valid) - when T_228 : + node T_210 = eq(state, UInt<2>("h02")) + when T_210 : + node T_212 = eq(strb, UInt<1>("h00")) + when T_212 : + node T_213 = mux(last, UInt<2>("h03"), UInt<1>("h01")) + state <= T_213 + skip + node T_214 = bits(strb, 0, 0) + node T_216 = eq(T_214, UInt<1>("h00")) + node T_217 = or(io.smi.req.ready, T_216) + node T_219 = eq(T_212, UInt<1>("h00")) + node T_220 = and(T_219, T_217) + when T_220 : + node T_221 = dshr(strb, UInt<1>("h01")) + strb <= T_221 + node T_223 = cat(UInt<1>("h01"), UInt<6>("h00")) + node T_224 = dshr(data, T_223) + data <= T_224 + node T_225 = add(addr, UInt<1>("h01")) + node T_226 = tail(T_225, 1) + addr <= T_226 + skip + skip + node T_227 = and(io.smi.resp.ready, io.smi.resp.valid) + when T_227 : state <= UInt<3>("h04") skip - node T_229 = and(io.b.ready, io.b.valid) - when T_229 : + node T_228 = and(io.b.ready, io.b.valid) + when T_228 : state <= UInt<1>("h00") skip @@ -17618,56 +12929,50 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, chosen : UInt<1>} - io.chosen <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.bits.addr <= UInt<1>("h00") - io.out.bits.rw <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") + io is invalid wire T_130 : UInt<1> - T_130 <= UInt<1>("h00") + T_130 is invalid io.out.valid <= io.in[T_130].valid io.out.bits <- io.in[T_130].bits io.chosen <= T_130 io.in[T_130].ready <= UInt<1>("h00") - reg T_168 : UInt<1>, clk, reset, UInt<1>("h00") - node T_169 = gt(UInt<1>("h00"), T_168) - node T_170 = and(io.in[0].valid, T_169) - node T_172 = gt(UInt<1>("h01"), T_168) - node T_173 = and(io.in[1].valid, T_172) - node T_176 = or(UInt<1>("h00"), T_170) - node T_178 = eq(T_176, UInt<1>("h00")) - node T_180 = or(UInt<1>("h00"), T_170) - node T_181 = or(T_180, T_173) - node T_183 = eq(T_181, UInt<1>("h00")) - node T_185 = or(UInt<1>("h00"), T_170) - node T_186 = or(T_185, T_173) - node T_187 = or(T_186, io.in[0].valid) - node T_189 = eq(T_187, UInt<1>("h00")) - node T_191 = gt(UInt<1>("h00"), T_168) - node T_192 = and(UInt<1>("h01"), T_191) - node T_193 = or(T_192, T_183) - node T_195 = gt(UInt<1>("h01"), T_168) - node T_196 = and(T_178, T_195) - node T_197 = or(T_196, T_189) - node T_199 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_200 = mux(UInt<1>("h00"), T_199, T_193) - node T_201 = and(T_200, io.out.ready) - io.in[0].ready <= T_201 - node T_203 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_204 = mux(UInt<1>("h00"), T_203, T_197) - node T_205 = and(T_204, io.out.ready) - io.in[1].ready <= T_205 - node T_208 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_210 = gt(UInt<1>("h01"), T_168) - node T_211 = and(io.in[1].valid, T_210) - node T_213 = mux(T_211, UInt<1>("h01"), T_208) - node T_214 = mux(UInt<1>("h00"), UInt<1>("h01"), T_213) - T_130 <= T_214 - node T_215 = and(io.out.ready, io.out.valid) - when T_215 : - T_168 <= T_130 + reg T_167 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_168 = gt(UInt<1>("h00"), T_167) + node T_169 = and(io.in[0].valid, T_168) + node T_171 = gt(UInt<1>("h01"), T_167) + node T_172 = and(io.in[1].valid, T_171) + node T_175 = or(UInt<1>("h00"), T_169) + node T_177 = eq(T_175, UInt<1>("h00")) + node T_179 = or(UInt<1>("h00"), T_169) + node T_180 = or(T_179, T_172) + node T_182 = eq(T_180, UInt<1>("h00")) + node T_184 = or(UInt<1>("h00"), T_169) + node T_185 = or(T_184, T_172) + node T_186 = or(T_185, io.in[0].valid) + node T_188 = eq(T_186, UInt<1>("h00")) + node T_190 = gt(UInt<1>("h00"), T_167) + node T_191 = and(UInt<1>("h01"), T_190) + node T_192 = or(T_191, T_182) + node T_194 = gt(UInt<1>("h01"), T_167) + node T_195 = and(T_177, T_194) + node T_196 = or(T_195, T_188) + node T_198 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_199 = mux(UInt<1>("h00"), T_198, T_192) + node T_200 = and(T_199, io.out.ready) + io.in[0].ready <= T_200 + node T_202 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_203 = mux(UInt<1>("h00"), T_202, T_196) + node T_204 = and(T_203, io.out.ready) + io.in[1].ready <= T_204 + node T_207 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_209 = gt(UInt<1>("h01"), T_167) + node T_210 = and(io.in[1].valid, T_209) + node T_212 = mux(T_210, UInt<1>("h01"), T_207) + node T_213 = mux(UInt<1>("h00"), UInt<1>("h01"), T_212) + T_130 <= T_213 + node T_214 = and(io.out.ready, io.out.valid) + when T_214 : + T_167 <= T_130 skip module SmiArbiter : @@ -17675,57 +12980,39 @@ circuit Top : input reset : UInt<1> output io : {flip in : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[2], out : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io.out.resp.ready <= UInt<1>("h00") - io.out.req.bits.data <= UInt<1>("h00") - io.out.req.bits.addr <= UInt<1>("h00") - io.out.req.bits.rw <= UInt<1>("h00") - io.out.req.valid <= UInt<1>("h00") - io.in[0].resp.bits <= UInt<1>("h00") - io.in[0].resp.valid <= UInt<1>("h00") - io.in[0].req.ready <= UInt<1>("h00") - io.in[1].resp.bits <= UInt<1>("h00") - io.in[1].resp.valid <= UInt<1>("h00") - io.in[1].req.ready <= UInt<1>("h00") - reg wait_resp : UInt<1>, clk, reset, UInt<1>("h00") - reg choice : UInt<1>, clk, UInt<1>("h00"), choice + io is invalid + reg wait_resp : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg choice : UInt<1>, clk inst req_arb of RRArbiter_77 - req_arb.io.out.ready <= UInt<1>("h00") - req_arb.io.in[0].bits.data <= UInt<1>("h00") - req_arb.io.in[0].bits.addr <= UInt<1>("h00") - req_arb.io.in[0].bits.rw <= UInt<1>("h00") - req_arb.io.in[0].valid <= UInt<1>("h00") - req_arb.io.in[1].bits.data <= UInt<1>("h00") - req_arb.io.in[1].bits.addr <= UInt<1>("h00") - req_arb.io.in[1].bits.rw <= UInt<1>("h00") - req_arb.io.in[1].valid <= UInt<1>("h00") + req_arb.io is invalid req_arb.clk <= clk req_arb.reset <= reset req_arb.io.in[0] <- io.in[0].req req_arb.io.in[1] <- io.in[1].req - node T_322 = eq(wait_resp, UInt<1>("h00")) - node T_323 = and(io.out.req.ready, T_322) - req_arb.io.out.ready <= T_323 + node T_313 = eq(wait_resp, UInt<1>("h00")) + node T_314 = and(io.out.req.ready, T_313) + req_arb.io.out.ready <= T_314 io.out.req.bits <- req_arb.io.out.bits - node T_325 = eq(wait_resp, UInt<1>("h00")) - node T_326 = and(req_arb.io.out.valid, T_325) - io.out.req.valid <= T_326 - node T_327 = and(io.out.req.ready, io.out.req.valid) - when T_327 : + node T_316 = eq(wait_resp, UInt<1>("h00")) + node T_317 = and(req_arb.io.out.valid, T_316) + io.out.req.valid <= T_317 + node T_318 = and(io.out.req.ready, io.out.req.valid) + when T_318 : choice <= req_arb.io.chosen wait_resp <= UInt<1>("h01") skip - node T_329 = and(io.out.resp.ready, io.out.resp.valid) - when T_329 : + node T_320 = and(io.out.resp.ready, io.out.resp.valid) + when T_320 : wait_resp <= UInt<1>("h00") skip io.in[0].resp.bits <= io.out.resp.bits - node T_332 = eq(choice, UInt<1>("h00")) - node T_333 = and(io.out.resp.valid, T_332) - io.in[0].resp.valid <= T_333 + node T_323 = eq(choice, UInt<1>("h00")) + node T_324 = and(io.out.resp.valid, T_323) + io.in[0].resp.valid <= T_324 io.in[1].resp.bits <= io.out.resp.bits - node T_335 = eq(choice, UInt<1>("h01")) - node T_336 = and(io.out.resp.valid, T_335) - io.in[1].resp.valid <= T_336 + node T_326 = eq(choice, UInt<1>("h01")) + node T_327 = and(io.out.resp.valid, T_326) + io.in[1].resp.valid <= T_327 io.out.resp.ready <= io.in[choice].resp.ready module SmiIONastiIOConverter : @@ -17733,86 +13020,22 @@ circuit Top : input reset : UInt<1> output io : {flip nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io.smi.resp.ready <= UInt<1>("h00") - io.smi.req.bits.data <= UInt<1>("h00") - io.smi.req.bits.addr <= UInt<1>("h00") - io.smi.req.bits.rw <= UInt<1>("h00") - io.smi.req.valid <= UInt<1>("h00") - io.nasti.r.bits.user <= UInt<1>("h00") - io.nasti.r.bits.id <= UInt<1>("h00") - io.nasti.r.bits.last <= UInt<1>("h00") - io.nasti.r.bits.data <= UInt<1>("h00") - io.nasti.r.bits.resp <= UInt<1>("h00") - io.nasti.r.valid <= UInt<1>("h00") - io.nasti.ar.ready <= UInt<1>("h00") - io.nasti.b.bits.user <= UInt<1>("h00") - io.nasti.b.bits.id <= UInt<1>("h00") - io.nasti.b.bits.resp <= UInt<1>("h00") - io.nasti.b.valid <= UInt<1>("h00") - io.nasti.w.ready <= UInt<1>("h00") - io.nasti.aw.ready <= UInt<1>("h00") + io is invalid inst reader of SmiIONastiReadIOConverter - reader.io.smi.resp.bits <= UInt<1>("h00") - reader.io.smi.resp.valid <= UInt<1>("h00") - reader.io.smi.req.ready <= UInt<1>("h00") - reader.io.r.ready <= UInt<1>("h00") - reader.io.ar.bits.user <= UInt<1>("h00") - reader.io.ar.bits.id <= UInt<1>("h00") - reader.io.ar.bits.region <= UInt<1>("h00") - reader.io.ar.bits.qos <= UInt<1>("h00") - reader.io.ar.bits.prot <= UInt<1>("h00") - reader.io.ar.bits.cache <= UInt<1>("h00") - reader.io.ar.bits.lock <= UInt<1>("h00") - reader.io.ar.bits.burst <= UInt<1>("h00") - reader.io.ar.bits.size <= UInt<1>("h00") - reader.io.ar.bits.len <= UInt<1>("h00") - reader.io.ar.bits.addr <= UInt<1>("h00") - reader.io.ar.valid <= UInt<1>("h00") + reader.io is invalid reader.clk <= clk reader.reset <= reset reader.io.ar <- io.nasti.ar io.nasti.r <- reader.io.r inst writer of SmiIONastiWriteIOConverter - writer.io.smi.resp.bits <= UInt<1>("h00") - writer.io.smi.resp.valid <= UInt<1>("h00") - writer.io.smi.req.ready <= UInt<1>("h00") - writer.io.b.ready <= UInt<1>("h00") - writer.io.w.bits.user <= UInt<1>("h00") - writer.io.w.bits.strb <= UInt<1>("h00") - writer.io.w.bits.last <= UInt<1>("h00") - writer.io.w.bits.data <= UInt<1>("h00") - writer.io.w.valid <= UInt<1>("h00") - writer.io.aw.bits.user <= UInt<1>("h00") - writer.io.aw.bits.id <= UInt<1>("h00") - writer.io.aw.bits.region <= UInt<1>("h00") - writer.io.aw.bits.qos <= UInt<1>("h00") - writer.io.aw.bits.prot <= UInt<1>("h00") - writer.io.aw.bits.cache <= UInt<1>("h00") - writer.io.aw.bits.lock <= UInt<1>("h00") - writer.io.aw.bits.burst <= UInt<1>("h00") - writer.io.aw.bits.size <= UInt<1>("h00") - writer.io.aw.bits.len <= UInt<1>("h00") - writer.io.aw.bits.addr <= UInt<1>("h00") - writer.io.aw.valid <= UInt<1>("h00") + writer.io is invalid writer.clk <= clk writer.reset <= reset writer.io.aw <- io.nasti.aw writer.io.w <- io.nasti.w io.nasti.b <- writer.io.b inst arb of SmiArbiter - arb.io.out.resp.bits <= UInt<1>("h00") - arb.io.out.resp.valid <= UInt<1>("h00") - arb.io.out.req.ready <= UInt<1>("h00") - arb.io.in[0].resp.ready <= UInt<1>("h00") - arb.io.in[0].req.bits.data <= UInt<1>("h00") - arb.io.in[0].req.bits.addr <= UInt<1>("h00") - arb.io.in[0].req.bits.rw <= UInt<1>("h00") - arb.io.in[0].req.valid <= UInt<1>("h00") - arb.io.in[1].resp.ready <= UInt<1>("h00") - arb.io.in[1].req.bits.data <= UInt<1>("h00") - arb.io.in[1].req.bits.addr <= UInt<1>("h00") - arb.io.in[1].req.bits.rw <= UInt<1>("h00") - arb.io.in[1].req.valid <= UInt<1>("h00") + arb.io is invalid arb.clk <= clk arb.reset <= reset arb.io.in[0] <- reader.io.smi @@ -17824,30 +13047,19 @@ circuit Top : input reset : UInt<1> output io : {flip ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io.smi.resp.ready <= UInt<1>("h00") - io.smi.req.bits.data <= UInt<1>("h00") - io.smi.req.bits.addr <= UInt<1>("h00") - io.smi.req.bits.rw <= UInt<1>("h00") - io.smi.req.valid <= UInt<1>("h00") - io.r.bits.user <= UInt<1>("h00") - io.r.bits.id <= UInt<1>("h00") - io.r.bits.last <= UInt<1>("h00") - io.r.bits.data <= UInt<1>("h00") - io.r.bits.resp <= UInt<1>("h00") - io.r.valid <= UInt<1>("h00") - io.ar.ready <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") - reg nWords : UInt<1>, clk, UInt<1>("h00"), nWords - reg nBeats : UInt<8>, clk, UInt<1>("h00"), nBeats - reg addr : UInt<6>, clk, UInt<1>("h00"), addr - reg id : UInt<5>, clk, UInt<1>("h00"), id - reg byteOff : UInt<3>, clk, UInt<1>("h00"), byteOff - reg sendInd : UInt<1>, clk, reset, UInt<1>("h00") - reg recvInd : UInt<1>, clk, reset, UInt<1>("h00") - reg sendDone : UInt<1>, clk, reset, UInt<1>("h00") + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + reg nWords : UInt<1>, clk + reg nBeats : UInt<8>, clk + reg addr : UInt<6>, clk + reg id : UInt<5>, clk + reg byteOff : UInt<3>, clk + reg sendInd : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg recvInd : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg sendDone : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) wire T_141 : UInt<64>[1] T_141[0] <= UInt<64>("h00") - reg buffer : UInt<64>[1], clk, reset, T_141 + reg buffer : UInt<64>[1], clk with : (reset => (reset, T_141)) node T_149 = eq(state, UInt<1>("h00")) io.ar.ready <= T_149 node T_150 = eq(state, UInt<1>("h01")) @@ -17862,51 +13074,52 @@ circuit Top : io.r.valid <= T_156 node T_158 = eq(nBeats, UInt<1>("h00")) wire T_166 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} - T_166.user <= UInt<1>("h00") - T_166.id <= UInt<1>("h00") - T_166.last <= UInt<1>("h00") - T_166.data <= UInt<1>("h00") - T_166.resp <= UInt<1>("h00") + T_166 is invalid T_166.id <= id T_166.data <= buffer[0] T_166.last <= T_158 T_166.resp <= UInt<1>("h00") T_166.user <= UInt<1>("h00") io.r.bits <- T_166 - node T_178 = and(io.ar.ready, io.ar.valid) - when T_178 : - node T_180 = lt(io.ar.bits.size, UInt<2>("h03")) - when T_180 : + node T_173 = and(io.ar.ready, io.ar.valid) + when T_173 : + node T_175 = lt(io.ar.bits.size, UInt<2>("h03")) + when T_175 : nWords <= UInt<1>("h00") - node T_182 = bits(io.ar.bits.addr, 2, 0) - byteOff <= T_182 - skip - node T_184 = eq(T_180, UInt<1>("h00")) - when T_184 : - node T_187 = subw(io.ar.bits.size, UInt<2>("h03")) - node T_188 = dshl(UInt<1>("h01"), T_187) - node T_190 = subw(T_188, UInt<1>("h01")) - nWords <= T_190 + node T_177 = bits(io.ar.bits.addr, 2, 0) + byteOff <= T_177 + skip + node T_179 = eq(T_175, UInt<1>("h00")) + when T_179 : + node T_182 = sub(io.ar.bits.size, UInt<2>("h03")) + node T_183 = tail(T_182, 1) + node T_184 = dshl(UInt<1>("h01"), T_183) + node T_186 = sub(T_184, UInt<1>("h01")) + node T_187 = tail(T_186, 1) + nWords <= T_187 byteOff <= UInt<1>("h00") skip nBeats <= io.ar.bits.len - node T_192 = bits(io.ar.bits.addr, 8, 3) - addr <= T_192 + node T_189 = bits(io.ar.bits.addr, 8, 3) + addr <= T_189 id <= io.ar.bits.id state <= UInt<1>("h01") skip - node T_193 = and(io.smi.req.ready, io.smi.req.valid) - when T_193 : - node T_195 = addw(addr, UInt<1>("h01")) - addr <= T_195 - node T_197 = addw(sendInd, UInt<1>("h01")) - sendInd <= T_197 - node T_198 = eq(sendInd, nWords) - sendDone <= T_198 - skip - node T_199 = and(io.smi.resp.ready, io.smi.resp.valid) - when T_199 : - node T_201 = addw(recvInd, UInt<1>("h01")) + node T_190 = and(io.smi.req.ready, io.smi.req.valid) + when T_190 : + node T_192 = add(addr, UInt<1>("h01")) + node T_193 = tail(T_192, 1) + addr <= T_193 + node T_195 = add(sendInd, UInt<1>("h01")) + node T_196 = tail(T_195, 1) + sendInd <= T_196 + node T_197 = eq(sendInd, nWords) + sendDone <= T_197 + skip + node T_198 = and(io.smi.resp.ready, io.smi.resp.valid) + when T_198 : + node T_200 = add(recvInd, UInt<1>("h01")) + node T_201 = tail(T_200, 1) recvInd <= T_201 node T_204 = cat(byteOff, UInt<3>("h00")) node T_205 = dshr(io.smi.resp.bits, T_204) @@ -17922,10 +13135,11 @@ circuit Top : sendInd <= UInt<1>("h00") sendDone <= UInt<1>("h00") buffer[0] <= UInt<1>("h00") - node T_213 = subw(nBeats, UInt<1>("h01")) - nBeats <= T_213 - node T_214 = mux(io.r.bits.last, UInt<1>("h00"), UInt<1>("h01")) - state <= T_214 + node T_213 = sub(nBeats, UInt<1>("h01")) + node T_214 = tail(T_213, 1) + nBeats <= T_214 + node T_215 = mux(io.r.bits.last, UInt<1>("h00"), UInt<1>("h01")) + state <= T_215 skip module SmiIONastiWriteIOConverter_80 : @@ -17933,17 +13147,7 @@ circuit Top : input reset : UInt<1> output io : {flip aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io.smi.resp.ready <= UInt<1>("h00") - io.smi.req.bits.data <= UInt<1>("h00") - io.smi.req.bits.addr <= UInt<1>("h00") - io.smi.req.bits.rw <= UInt<1>("h00") - io.smi.req.valid <= UInt<1>("h00") - io.b.bits.user <= UInt<1>("h00") - io.b.bits.id <= UInt<1>("h00") - io.b.bits.resp <= UInt<1>("h00") - io.b.valid <= UInt<1>("h00") - io.w.ready <= UInt<1>("h00") - io.aw.ready <= UInt<1>("h00") + io is invalid node T_144 = eq(io.aw.valid, UInt<1>("h00")) node T_146 = geq(io.aw.bits.size, UInt<2>("h03")) node T_147 = or(T_144, T_146) @@ -17958,19 +13162,19 @@ circuit Top : stop(clk, UInt<1>(1), 1) skip skip - reg id : UInt<5>, clk, UInt<1>("h00"), id - reg addr : UInt<6>, clk, UInt<1>("h00"), addr - reg size : UInt<3>, clk, UInt<1>("h00"), size - reg strb : UInt<1>, clk, UInt<1>("h00"), strb - reg data : UInt<64>, clk, UInt<1>("h00"), data - reg last : UInt<1>, clk, UInt<1>("h00"), last - reg state : UInt<?>, clk, reset, UInt<1>("h00") + reg id : UInt<5>, clk + reg addr : UInt<6>, clk + reg size : UInt<3>, clk + reg strb : UInt<1>, clk + reg data : UInt<64>, clk + reg last : UInt<1>, clk + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) node T_173 = eq(state, UInt<1>("h00")) io.aw.ready <= T_173 node T_174 = eq(state, UInt<1>("h01")) io.w.ready <= T_174 node T_175 = eq(state, UInt<2>("h02")) - node T_176 = bit(strb, 0) + node T_176 = bits(strb, 0, 0) node T_177 = and(T_175, T_176) io.smi.req.valid <= T_177 io.smi.req.bits.rw <= UInt<1>("h01") @@ -17982,64 +13186,64 @@ circuit Top : node T_181 = eq(state, UInt<3>("h04")) io.b.valid <= T_181 wire T_187 : {resp : UInt<2>, id : UInt<5>, user : UInt<1>} - T_187.user <= UInt<1>("h00") - T_187.id <= UInt<1>("h00") - T_187.resp <= UInt<1>("h00") + T_187 is invalid T_187.id <= id T_187.resp <= UInt<1>("h00") T_187.user <= UInt<1>("h00") io.b.bits <- T_187 - node T_196 = and(io.aw.ready, io.aw.valid) - when T_196 : - node T_197 = bits(io.aw.bits.addr, 8, 3) - addr <= T_197 + node T_193 = and(io.aw.ready, io.aw.valid) + when T_193 : + node T_194 = bits(io.aw.bits.addr, 8, 3) + addr <= T_194 id <= io.aw.bits.id size <= io.aw.bits.size last <= UInt<1>("h00") state <= UInt<1>("h01") skip - node T_199 = and(io.w.ready, io.w.valid) - when T_199 : + node T_196 = and(io.w.ready, io.w.valid) + when T_196 : last <= io.w.bits.last - node T_202 = dshl(UInt<1>("h01"), size) - node T_203 = dshl(UInt<1>("h01"), T_202) - node T_205 = subw(T_203, UInt<1>("h01")) - node T_206 = and(T_205, io.w.bits.strb) - node T_207 = bit(T_206, 0) - wire T_209 : UInt<1>[1] - T_209[0] <= T_207 - strb <= T_209[0] + node T_199 = dshl(UInt<1>("h01"), size) + node T_200 = dshl(UInt<1>("h01"), T_199) + node T_202 = sub(T_200, UInt<1>("h01")) + node T_203 = tail(T_202, 1) + node T_204 = and(T_203, io.w.bits.strb) + node T_205 = bits(T_204, 0, 0) + wire T_207 : UInt<1>[1] + T_207[0] <= T_205 + strb <= T_207[0] data <= io.w.bits.data state <= UInt<2>("h02") skip - node T_212 = eq(state, UInt<2>("h02")) - when T_212 : - node T_214 = eq(strb, UInt<1>("h00")) - when T_214 : - node T_215 = mux(last, UInt<2>("h03"), UInt<1>("h01")) - state <= T_215 - skip - node T_216 = bit(strb, 0) - node T_218 = eq(T_216, UInt<1>("h00")) - node T_219 = or(io.smi.req.ready, T_218) - node T_221 = eq(T_214, UInt<1>("h00")) - node T_222 = and(T_221, T_219) - when T_222 : - node T_223 = dshr(strb, UInt<1>("h01")) - strb <= T_223 - node T_225 = cat(UInt<1>("h01"), UInt<6>("h00")) - node T_226 = dshr(data, T_225) - data <= T_226 - node T_227 = addw(addr, UInt<1>("h01")) - addr <= T_227 - skip - skip - node T_228 = and(io.smi.resp.ready, io.smi.resp.valid) - when T_228 : + node T_210 = eq(state, UInt<2>("h02")) + when T_210 : + node T_212 = eq(strb, UInt<1>("h00")) + when T_212 : + node T_213 = mux(last, UInt<2>("h03"), UInt<1>("h01")) + state <= T_213 + skip + node T_214 = bits(strb, 0, 0) + node T_216 = eq(T_214, UInt<1>("h00")) + node T_217 = or(io.smi.req.ready, T_216) + node T_219 = eq(T_212, UInt<1>("h00")) + node T_220 = and(T_219, T_217) + when T_220 : + node T_221 = dshr(strb, UInt<1>("h01")) + strb <= T_221 + node T_223 = cat(UInt<1>("h01"), UInt<6>("h00")) + node T_224 = dshr(data, T_223) + data <= T_224 + node T_225 = add(addr, UInt<1>("h01")) + node T_226 = tail(T_225, 1) + addr <= T_226 + skip + skip + node T_227 = and(io.smi.resp.ready, io.smi.resp.valid) + when T_227 : state <= UInt<3>("h04") skip - node T_229 = and(io.b.ready, io.b.valid) - when T_229 : + node T_228 = and(io.b.ready, io.b.valid) + when T_228 : state <= UInt<1>("h00") skip @@ -18048,56 +13252,50 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, chosen : UInt<1>} - io.chosen <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.bits.addr <= UInt<1>("h00") - io.out.bits.rw <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") + io is invalid wire T_130 : UInt<1> - T_130 <= UInt<1>("h00") + T_130 is invalid io.out.valid <= io.in[T_130].valid io.out.bits <- io.in[T_130].bits io.chosen <= T_130 io.in[T_130].ready <= UInt<1>("h00") - reg T_168 : UInt<1>, clk, reset, UInt<1>("h00") - node T_169 = gt(UInt<1>("h00"), T_168) - node T_170 = and(io.in[0].valid, T_169) - node T_172 = gt(UInt<1>("h01"), T_168) - node T_173 = and(io.in[1].valid, T_172) - node T_176 = or(UInt<1>("h00"), T_170) - node T_178 = eq(T_176, UInt<1>("h00")) - node T_180 = or(UInt<1>("h00"), T_170) - node T_181 = or(T_180, T_173) - node T_183 = eq(T_181, UInt<1>("h00")) - node T_185 = or(UInt<1>("h00"), T_170) - node T_186 = or(T_185, T_173) - node T_187 = or(T_186, io.in[0].valid) - node T_189 = eq(T_187, UInt<1>("h00")) - node T_191 = gt(UInt<1>("h00"), T_168) - node T_192 = and(UInt<1>("h01"), T_191) - node T_193 = or(T_192, T_183) - node T_195 = gt(UInt<1>("h01"), T_168) - node T_196 = and(T_178, T_195) - node T_197 = or(T_196, T_189) - node T_199 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_200 = mux(UInt<1>("h00"), T_199, T_193) - node T_201 = and(T_200, io.out.ready) - io.in[0].ready <= T_201 - node T_203 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_204 = mux(UInt<1>("h00"), T_203, T_197) - node T_205 = and(T_204, io.out.ready) - io.in[1].ready <= T_205 - node T_208 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_210 = gt(UInt<1>("h01"), T_168) - node T_211 = and(io.in[1].valid, T_210) - node T_213 = mux(T_211, UInt<1>("h01"), T_208) - node T_214 = mux(UInt<1>("h00"), UInt<1>("h01"), T_213) - T_130 <= T_214 - node T_215 = and(io.out.ready, io.out.valid) - when T_215 : - T_168 <= T_130 + reg T_167 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_168 = gt(UInt<1>("h00"), T_167) + node T_169 = and(io.in[0].valid, T_168) + node T_171 = gt(UInt<1>("h01"), T_167) + node T_172 = and(io.in[1].valid, T_171) + node T_175 = or(UInt<1>("h00"), T_169) + node T_177 = eq(T_175, UInt<1>("h00")) + node T_179 = or(UInt<1>("h00"), T_169) + node T_180 = or(T_179, T_172) + node T_182 = eq(T_180, UInt<1>("h00")) + node T_184 = or(UInt<1>("h00"), T_169) + node T_185 = or(T_184, T_172) + node T_186 = or(T_185, io.in[0].valid) + node T_188 = eq(T_186, UInt<1>("h00")) + node T_190 = gt(UInt<1>("h00"), T_167) + node T_191 = and(UInt<1>("h01"), T_190) + node T_192 = or(T_191, T_182) + node T_194 = gt(UInt<1>("h01"), T_167) + node T_195 = and(T_177, T_194) + node T_196 = or(T_195, T_188) + node T_198 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_199 = mux(UInt<1>("h00"), T_198, T_192) + node T_200 = and(T_199, io.out.ready) + io.in[0].ready <= T_200 + node T_202 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_203 = mux(UInt<1>("h00"), T_202, T_196) + node T_204 = and(T_203, io.out.ready) + io.in[1].ready <= T_204 + node T_207 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_209 = gt(UInt<1>("h01"), T_167) + node T_210 = and(io.in[1].valid, T_209) + node T_212 = mux(T_210, UInt<1>("h01"), T_207) + node T_213 = mux(UInt<1>("h00"), UInt<1>("h01"), T_212) + T_130 <= T_213 + node T_214 = and(io.out.ready, io.out.valid) + when T_214 : + T_167 <= T_130 skip module SmiArbiter_81 : @@ -18105,57 +13303,39 @@ circuit Top : input reset : UInt<1> output io : {flip in : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[2], out : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io.out.resp.ready <= UInt<1>("h00") - io.out.req.bits.data <= UInt<1>("h00") - io.out.req.bits.addr <= UInt<1>("h00") - io.out.req.bits.rw <= UInt<1>("h00") - io.out.req.valid <= UInt<1>("h00") - io.in[0].resp.bits <= UInt<1>("h00") - io.in[0].resp.valid <= UInt<1>("h00") - io.in[0].req.ready <= UInt<1>("h00") - io.in[1].resp.bits <= UInt<1>("h00") - io.in[1].resp.valid <= UInt<1>("h00") - io.in[1].req.ready <= UInt<1>("h00") - reg wait_resp : UInt<1>, clk, reset, UInt<1>("h00") - reg choice : UInt<1>, clk, UInt<1>("h00"), choice + io is invalid + reg wait_resp : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg choice : UInt<1>, clk inst req_arb of RRArbiter_82 - req_arb.io.out.ready <= UInt<1>("h00") - req_arb.io.in[0].bits.data <= UInt<1>("h00") - req_arb.io.in[0].bits.addr <= UInt<1>("h00") - req_arb.io.in[0].bits.rw <= UInt<1>("h00") - req_arb.io.in[0].valid <= UInt<1>("h00") - req_arb.io.in[1].bits.data <= UInt<1>("h00") - req_arb.io.in[1].bits.addr <= UInt<1>("h00") - req_arb.io.in[1].bits.rw <= UInt<1>("h00") - req_arb.io.in[1].valid <= UInt<1>("h00") + req_arb.io is invalid req_arb.clk <= clk req_arb.reset <= reset req_arb.io.in[0] <- io.in[0].req req_arb.io.in[1] <- io.in[1].req - node T_322 = eq(wait_resp, UInt<1>("h00")) - node T_323 = and(io.out.req.ready, T_322) - req_arb.io.out.ready <= T_323 + node T_313 = eq(wait_resp, UInt<1>("h00")) + node T_314 = and(io.out.req.ready, T_313) + req_arb.io.out.ready <= T_314 io.out.req.bits <- req_arb.io.out.bits - node T_325 = eq(wait_resp, UInt<1>("h00")) - node T_326 = and(req_arb.io.out.valid, T_325) - io.out.req.valid <= T_326 - node T_327 = and(io.out.req.ready, io.out.req.valid) - when T_327 : + node T_316 = eq(wait_resp, UInt<1>("h00")) + node T_317 = and(req_arb.io.out.valid, T_316) + io.out.req.valid <= T_317 + node T_318 = and(io.out.req.ready, io.out.req.valid) + when T_318 : choice <= req_arb.io.chosen wait_resp <= UInt<1>("h01") skip - node T_329 = and(io.out.resp.ready, io.out.resp.valid) - when T_329 : + node T_320 = and(io.out.resp.ready, io.out.resp.valid) + when T_320 : wait_resp <= UInt<1>("h00") skip io.in[0].resp.bits <= io.out.resp.bits - node T_332 = eq(choice, UInt<1>("h00")) - node T_333 = and(io.out.resp.valid, T_332) - io.in[0].resp.valid <= T_333 + node T_323 = eq(choice, UInt<1>("h00")) + node T_324 = and(io.out.resp.valid, T_323) + io.in[0].resp.valid <= T_324 io.in[1].resp.bits <= io.out.resp.bits - node T_335 = eq(choice, UInt<1>("h01")) - node T_336 = and(io.out.resp.valid, T_335) - io.in[1].resp.valid <= T_336 + node T_326 = eq(choice, UInt<1>("h01")) + node T_327 = and(io.out.resp.valid, T_326) + io.in[1].resp.valid <= T_327 io.out.resp.ready <= io.in[choice].resp.ready module SmiIONastiIOConverter_78 : @@ -18163,86 +13343,22 @@ circuit Top : input reset : UInt<1> output io : {flip nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}} - io.smi.resp.ready <= UInt<1>("h00") - io.smi.req.bits.data <= UInt<1>("h00") - io.smi.req.bits.addr <= UInt<1>("h00") - io.smi.req.bits.rw <= UInt<1>("h00") - io.smi.req.valid <= UInt<1>("h00") - io.nasti.r.bits.user <= UInt<1>("h00") - io.nasti.r.bits.id <= UInt<1>("h00") - io.nasti.r.bits.last <= UInt<1>("h00") - io.nasti.r.bits.data <= UInt<1>("h00") - io.nasti.r.bits.resp <= UInt<1>("h00") - io.nasti.r.valid <= UInt<1>("h00") - io.nasti.ar.ready <= UInt<1>("h00") - io.nasti.b.bits.user <= UInt<1>("h00") - io.nasti.b.bits.id <= UInt<1>("h00") - io.nasti.b.bits.resp <= UInt<1>("h00") - io.nasti.b.valid <= UInt<1>("h00") - io.nasti.w.ready <= UInt<1>("h00") - io.nasti.aw.ready <= UInt<1>("h00") + io is invalid inst reader of SmiIONastiReadIOConverter_79 - reader.io.smi.resp.bits <= UInt<1>("h00") - reader.io.smi.resp.valid <= UInt<1>("h00") - reader.io.smi.req.ready <= UInt<1>("h00") - reader.io.r.ready <= UInt<1>("h00") - reader.io.ar.bits.user <= UInt<1>("h00") - reader.io.ar.bits.id <= UInt<1>("h00") - reader.io.ar.bits.region <= UInt<1>("h00") - reader.io.ar.bits.qos <= UInt<1>("h00") - reader.io.ar.bits.prot <= UInt<1>("h00") - reader.io.ar.bits.cache <= UInt<1>("h00") - reader.io.ar.bits.lock <= UInt<1>("h00") - reader.io.ar.bits.burst <= UInt<1>("h00") - reader.io.ar.bits.size <= UInt<1>("h00") - reader.io.ar.bits.len <= UInt<1>("h00") - reader.io.ar.bits.addr <= UInt<1>("h00") - reader.io.ar.valid <= UInt<1>("h00") + reader.io is invalid reader.clk <= clk reader.reset <= reset reader.io.ar <- io.nasti.ar io.nasti.r <- reader.io.r inst writer of SmiIONastiWriteIOConverter_80 - writer.io.smi.resp.bits <= UInt<1>("h00") - writer.io.smi.resp.valid <= UInt<1>("h00") - writer.io.smi.req.ready <= UInt<1>("h00") - writer.io.b.ready <= UInt<1>("h00") - writer.io.w.bits.user <= UInt<1>("h00") - writer.io.w.bits.strb <= UInt<1>("h00") - writer.io.w.bits.last <= UInt<1>("h00") - writer.io.w.bits.data <= UInt<1>("h00") - writer.io.w.valid <= UInt<1>("h00") - writer.io.aw.bits.user <= UInt<1>("h00") - writer.io.aw.bits.id <= UInt<1>("h00") - writer.io.aw.bits.region <= UInt<1>("h00") - writer.io.aw.bits.qos <= UInt<1>("h00") - writer.io.aw.bits.prot <= UInt<1>("h00") - writer.io.aw.bits.cache <= UInt<1>("h00") - writer.io.aw.bits.lock <= UInt<1>("h00") - writer.io.aw.bits.burst <= UInt<1>("h00") - writer.io.aw.bits.size <= UInt<1>("h00") - writer.io.aw.bits.len <= UInt<1>("h00") - writer.io.aw.bits.addr <= UInt<1>("h00") - writer.io.aw.valid <= UInt<1>("h00") + writer.io is invalid writer.clk <= clk writer.reset <= reset writer.io.aw <- io.nasti.aw writer.io.w <- io.nasti.w io.nasti.b <- writer.io.b inst arb of SmiArbiter_81 - arb.io.out.resp.bits <= UInt<1>("h00") - arb.io.out.resp.valid <= UInt<1>("h00") - arb.io.out.req.ready <= UInt<1>("h00") - arb.io.in[0].resp.ready <= UInt<1>("h00") - arb.io.in[0].req.bits.data <= UInt<1>("h00") - arb.io.in[0].req.bits.addr <= UInt<1>("h00") - arb.io.in[0].req.bits.rw <= UInt<1>("h00") - arb.io.in[0].req.valid <= UInt<1>("h00") - arb.io.in[1].resp.ready <= UInt<1>("h00") - arb.io.in[1].req.bits.data <= UInt<1>("h00") - arb.io.in[1].req.bits.addr <= UInt<1>("h00") - arb.io.in[1].req.bits.rw <= UInt<1>("h00") - arb.io.in[1].req.valid <= UInt<1>("h00") + arb.io is invalid arb.clk <= clk arb.reset <= reset arb.io.in[0] <- reader.io.smi @@ -18254,50 +13370,7 @@ circuit Top : input reset : UInt<1> output io : {flip master : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], slave : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}} - io.slave.r.ready <= UInt<1>("h00") - io.slave.ar.bits.user <= UInt<1>("h00") - io.slave.ar.bits.id <= UInt<1>("h00") - io.slave.ar.bits.region <= UInt<1>("h00") - io.slave.ar.bits.qos <= UInt<1>("h00") - io.slave.ar.bits.prot <= UInt<1>("h00") - io.slave.ar.bits.cache <= UInt<1>("h00") - io.slave.ar.bits.lock <= UInt<1>("h00") - io.slave.ar.bits.burst <= UInt<1>("h00") - io.slave.ar.bits.size <= UInt<1>("h00") - io.slave.ar.bits.len <= UInt<1>("h00") - io.slave.ar.bits.addr <= UInt<1>("h00") - io.slave.ar.valid <= UInt<1>("h00") - io.slave.b.ready <= UInt<1>("h00") - io.slave.w.bits.user <= UInt<1>("h00") - io.slave.w.bits.strb <= UInt<1>("h00") - io.slave.w.bits.last <= UInt<1>("h00") - io.slave.w.bits.data <= UInt<1>("h00") - io.slave.w.valid <= UInt<1>("h00") - io.slave.aw.bits.user <= UInt<1>("h00") - io.slave.aw.bits.id <= UInt<1>("h00") - io.slave.aw.bits.region <= UInt<1>("h00") - io.slave.aw.bits.qos <= UInt<1>("h00") - io.slave.aw.bits.prot <= UInt<1>("h00") - io.slave.aw.bits.cache <= UInt<1>("h00") - io.slave.aw.bits.lock <= UInt<1>("h00") - io.slave.aw.bits.burst <= UInt<1>("h00") - io.slave.aw.bits.size <= UInt<1>("h00") - io.slave.aw.bits.len <= UInt<1>("h00") - io.slave.aw.bits.addr <= UInt<1>("h00") - io.slave.aw.valid <= UInt<1>("h00") - io.master[0].r.bits.user <= UInt<1>("h00") - io.master[0].r.bits.id <= UInt<1>("h00") - io.master[0].r.bits.last <= UInt<1>("h00") - io.master[0].r.bits.data <= UInt<1>("h00") - io.master[0].r.bits.resp <= UInt<1>("h00") - io.master[0].r.valid <= UInt<1>("h00") - io.master[0].ar.ready <= UInt<1>("h00") - io.master[0].b.bits.user <= UInt<1>("h00") - io.master[0].b.bits.id <= UInt<1>("h00") - io.master[0].b.bits.resp <= UInt<1>("h00") - io.master[0].b.valid <= UInt<1>("h00") - io.master[0].w.ready <= UInt<1>("h00") - io.master[0].aw.ready <= UInt<1>("h00") + io is invalid io.slave <- io.master[0] module MemIONastiIOConverter : @@ -18305,144 +13378,124 @@ circuit Top : input reset : UInt<1> output io : {flip nasti : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, mem : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}}} - io.mem.resp.ready <= UInt<1>("h00") - io.mem.req_data.bits.data <= UInt<1>("h00") - io.mem.req_data.valid <= UInt<1>("h00") - io.mem.req_cmd.bits.rw <= UInt<1>("h00") - io.mem.req_cmd.bits.tag <= UInt<1>("h00") - io.mem.req_cmd.bits.addr <= UInt<1>("h00") - io.mem.req_cmd.valid <= UInt<1>("h00") - io.nasti.r.bits.user <= UInt<1>("h00") - io.nasti.r.bits.id <= UInt<1>("h00") - io.nasti.r.bits.last <= UInt<1>("h00") - io.nasti.r.bits.data <= UInt<1>("h00") - io.nasti.r.bits.resp <= UInt<1>("h00") - io.nasti.r.valid <= UInt<1>("h00") - io.nasti.ar.ready <= UInt<1>("h00") - io.nasti.b.bits.user <= UInt<1>("h00") - io.nasti.b.bits.id <= UInt<1>("h00") - io.nasti.b.bits.resp <= UInt<1>("h00") - io.nasti.b.valid <= UInt<1>("h00") - io.nasti.w.ready <= UInt<1>("h00") - io.nasti.aw.ready <= UInt<1>("h00") + io is invalid node T_368 = and(io.mem.resp.ready, io.mem.resp.valid) - reg mif_cnt_out : UInt<3>, clk, reset, UInt<3>("h00") + reg mif_cnt_out : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) when T_368 : node T_372 = eq(mif_cnt_out, UInt<3>("h07")) node T_374 = and(UInt<1>("h00"), T_372) - node T_377 = addw(mif_cnt_out, UInt<1>("h01")) - node T_378 = mux(T_374, UInt<1>("h00"), T_377) - mif_cnt_out <= T_378 + node T_377 = add(mif_cnt_out, UInt<1>("h01")) + node T_378 = tail(T_377, 1) + node T_379 = mux(T_374, UInt<1>("h00"), T_378) + mif_cnt_out <= T_379 skip node mif_wrap_out = and(T_368, T_372) - node T_381 = eq(io.nasti.aw.valid, UInt<1>("h00")) - node T_383 = eq(io.nasti.aw.bits.size, UInt<2>("h03")) - node T_384 = or(T_381, T_383) - node T_386 = eq(reset, UInt<1>("h00")) - when T_386 : - node T_388 = eq(T_384, UInt<1>("h00")) - when T_388 : - node T_390 = eq(reset, UInt<1>("h00")) - when T_390 : + node T_382 = eq(io.nasti.aw.valid, UInt<1>("h00")) + node T_384 = eq(io.nasti.aw.bits.size, UInt<2>("h03")) + node T_385 = or(T_382, T_384) + node T_387 = eq(reset, UInt<1>("h00")) + when T_387 : + node T_389 = eq(T_385, UInt<1>("h00")) + when T_389 : + node T_391 = eq(reset, UInt<1>("h00")) + when T_391 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti data size does not match MemIO data size") skip stop(clk, UInt<1>(1), 1) skip skip - node T_392 = eq(io.nasti.ar.valid, UInt<1>("h00")) - node T_394 = eq(io.nasti.ar.bits.size, UInt<2>("h03")) - node T_395 = or(T_392, T_394) - node T_397 = eq(reset, UInt<1>("h00")) - when T_397 : - node T_399 = eq(T_395, UInt<1>("h00")) - when T_399 : - node T_401 = eq(reset, UInt<1>("h00")) - when T_401 : + node T_393 = eq(io.nasti.ar.valid, UInt<1>("h00")) + node T_395 = eq(io.nasti.ar.bits.size, UInt<2>("h03")) + node T_396 = or(T_393, T_395) + node T_398 = eq(reset, UInt<1>("h00")) + when T_398 : + node T_400 = eq(T_396, UInt<1>("h00")) + when T_400 : + node T_402 = eq(reset, UInt<1>("h00")) + when T_402 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti data size does not match MemIO data size") skip stop(clk, UInt<1>(1), 1) skip skip - node T_403 = eq(io.nasti.aw.valid, UInt<1>("h00")) - node T_405 = eq(io.nasti.aw.bits.len, UInt<3>("h07")) - node T_406 = or(T_403, T_405) - node T_408 = eq(reset, UInt<1>("h00")) - when T_408 : - node T_410 = eq(T_406, UInt<1>("h00")) - when T_410 : - node T_412 = eq(reset, UInt<1>("h00")) - when T_412 : + node T_404 = eq(io.nasti.aw.valid, UInt<1>("h00")) + node T_406 = eq(io.nasti.aw.bits.len, UInt<3>("h07")) + node T_407 = or(T_404, T_406) + node T_409 = eq(reset, UInt<1>("h00")) + when T_409 : + node T_411 = eq(T_407, UInt<1>("h00")) + when T_411 : + node T_413 = eq(reset, UInt<1>("h00")) + when T_413 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti length does not match number of MemIO beats") skip stop(clk, UInt<1>(1), 1) skip skip - node T_414 = eq(io.nasti.ar.valid, UInt<1>("h00")) - node T_416 = eq(io.nasti.ar.bits.len, UInt<3>("h07")) - node T_417 = or(T_414, T_416) - node T_419 = eq(reset, UInt<1>("h00")) - when T_419 : - node T_421 = eq(T_417, UInt<1>("h00")) - when T_421 : - node T_423 = eq(reset, UInt<1>("h00")) - when T_423 : + node T_415 = eq(io.nasti.ar.valid, UInt<1>("h00")) + node T_417 = eq(io.nasti.ar.bits.len, UInt<3>("h07")) + node T_418 = or(T_415, T_417) + node T_420 = eq(reset, UInt<1>("h00")) + when T_420 : + node T_422 = eq(T_418, UInt<1>("h00")) + when T_422 : + node T_424 = eq(reset, UInt<1>("h00")) + when T_424 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Nasti length does not match number of MemIO beats") skip stop(clk, UInt<1>(1), 1) skip skip - reg b_ok : UInt<1>, clk, reset, UInt<1>("h01") - node T_426 = and(io.nasti.aw.ready, io.nasti.aw.valid) - when T_426 : + reg b_ok : UInt<1>, clk with : (reset => (reset, UInt<1>("h01"))) + node T_427 = and(io.nasti.aw.ready, io.nasti.aw.valid) + when T_427 : b_ok <= UInt<1>("h00") skip - node T_428 = and(io.nasti.w.ready, io.nasti.w.valid) - node T_429 = and(T_428, io.nasti.w.bits.last) - when T_429 : + node T_429 = and(io.nasti.w.ready, io.nasti.w.valid) + node T_430 = and(T_429, io.nasti.w.bits.last) + when T_430 : b_ok <= UInt<1>("h01") skip inst id_q of Queue_37 - id_q.io.deq.ready <= UInt<1>("h00") - id_q.io.enq.bits <= UInt<1>("h00") - id_q.io.enq.valid <= UInt<1>("h00") + id_q.io is invalid id_q.clk <= clk id_q.reset <= reset - node T_436 = and(io.nasti.aw.valid, io.mem.req_cmd.ready) - id_q.io.enq.valid <= T_436 + node T_434 = and(io.nasti.aw.valid, io.mem.req_cmd.ready) + id_q.io.enq.valid <= T_434 id_q.io.enq.bits <= io.nasti.aw.bits.id - node T_437 = and(io.nasti.b.ready, b_ok) - id_q.io.deq.ready <= T_437 - node T_438 = mux(io.nasti.aw.valid, io.nasti.aw.bits.addr, io.nasti.ar.bits.addr) - node T_440 = dshr(T_438, UInt<3>("h06")) - io.mem.req_cmd.bits.addr <= T_440 - node T_441 = mux(io.nasti.aw.valid, io.nasti.aw.bits.id, io.nasti.ar.bits.id) - io.mem.req_cmd.bits.tag <= T_441 + node T_435 = and(io.nasti.b.ready, b_ok) + id_q.io.deq.ready <= T_435 + node T_436 = mux(io.nasti.aw.valid, io.nasti.aw.bits.addr, io.nasti.ar.bits.addr) + node T_438 = dshr(T_436, UInt<3>("h06")) + io.mem.req_cmd.bits.addr <= T_438 + node T_439 = mux(io.nasti.aw.valid, io.nasti.aw.bits.id, io.nasti.ar.bits.id) + io.mem.req_cmd.bits.tag <= T_439 io.mem.req_cmd.bits.rw <= io.nasti.aw.valid - node T_442 = and(io.nasti.aw.valid, id_q.io.enq.ready) - node T_443 = or(T_442, io.nasti.ar.valid) - io.mem.req_cmd.valid <= T_443 - node T_445 = eq(io.nasti.aw.valid, UInt<1>("h00")) - node T_446 = and(io.mem.req_cmd.ready, T_445) - io.nasti.ar.ready <= T_446 - node T_447 = and(io.mem.req_cmd.ready, id_q.io.enq.ready) - io.nasti.aw.ready <= T_447 - node T_448 = and(id_q.io.deq.valid, b_ok) - io.nasti.b.valid <= T_448 + node T_440 = and(io.nasti.aw.valid, id_q.io.enq.ready) + node T_441 = or(T_440, io.nasti.ar.valid) + io.mem.req_cmd.valid <= T_441 + node T_443 = eq(io.nasti.aw.valid, UInt<1>("h00")) + node T_444 = and(io.mem.req_cmd.ready, T_443) + io.nasti.ar.ready <= T_444 + node T_445 = and(io.mem.req_cmd.ready, id_q.io.enq.ready) + io.nasti.aw.ready <= T_445 + node T_446 = and(id_q.io.deq.valid, b_ok) + io.nasti.b.valid <= T_446 io.nasti.b.bits.id <= id_q.io.deq.bits io.nasti.b.bits.resp <= UInt<1>("h00") io.nasti.w.ready <= io.mem.req_data.ready io.mem.req_data.valid <= io.nasti.w.valid io.mem.req_data.bits.data <= io.nasti.w.bits.data - node T_451 = eq(io.nasti.w.valid, UInt<1>("h00")) - node T_452 = not(io.nasti.w.bits.strb) - node T_454 = eq(T_452, UInt<1>("h00")) - node T_455 = or(T_451, T_454) - node T_457 = eq(reset, UInt<1>("h00")) - when T_457 : - node T_459 = eq(T_455, UInt<1>("h00")) - when T_459 : - node T_461 = eq(reset, UInt<1>("h00")) - when T_461 : + node T_449 = eq(io.nasti.w.valid, UInt<1>("h00")) + node T_450 = not(io.nasti.w.bits.strb) + node T_452 = eq(T_450, UInt<1>("h00")) + node T_453 = or(T_449, T_452) + node T_455 = eq(reset, UInt<1>("h00")) + when T_455 : + node T_457 = eq(T_453, UInt<1>("h00")) + when T_457 : + node T_459 = eq(reset, UInt<1>("h00")) + when T_459 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): MemIO must write full cache line") skip stop(clk, UInt<1>(1), 1) @@ -18460,1084 +13513,296 @@ circuit Top : input reset : UInt<1> output io : {flip wide : {req_cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<26>, tag : UInt<5>, rw : UInt<1>}}, req_data : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}}, narrow : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}}} - io.narrow.req.bits <= UInt<1>("h00") - io.narrow.req.valid <= UInt<1>("h00") - io.wide.resp.bits.tag <= UInt<1>("h00") - io.wide.resp.bits.data <= UInt<1>("h00") - io.wide.resp.valid <= UInt<1>("h00") - io.wide.req_data.ready <= UInt<1>("h00") - io.wide.req_cmd.ready <= UInt<1>("h00") + io is invalid node T_112 = cat(io.wide.req_cmd.bits.tag, io.wide.req_cmd.bits.rw) node T_113 = cat(io.wide.req_cmd.bits.addr, T_112) - reg out_buf : UInt<?>, clk, UInt<1>("h00"), out_buf - reg in_buf : UInt<?>, clk, UInt<1>("h00"), in_buf - reg state : UInt<?>, clk, reset, UInt<1>("h00") - reg send_cnt : UInt<2>, clk, reset, UInt<2>("h00") - reg data_send_cnt : UInt<3>, clk, reset, UInt<3>("h00") + reg out_buf : UInt<?>, clk + reg in_buf : UInt<?>, clk + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + reg send_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + reg data_send_cnt : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) node T_130 = eq(send_cnt, UInt<1>("h01")) node adone = and(io.narrow.req.ready, T_130) node T_133 = eq(send_cnt, UInt<2>("h03")) node ddone = and(io.narrow.req.ready, T_133) node T_135 = and(io.narrow.req.valid, io.narrow.req.ready) when T_135 : - node T_137 = addw(send_cnt, UInt<1>("h01")) - send_cnt <= T_137 - node T_139 = dshr(out_buf, UInt<5>("h010")) - out_buf <= T_139 - skip - node T_140 = and(io.wide.req_cmd.valid, io.wide.req_cmd.ready) - when T_140 : - node T_141 = cat(io.wide.req_cmd.bits.tag, io.wide.req_cmd.bits.rw) - node T_142 = cat(io.wide.req_cmd.bits.addr, T_141) - out_buf <= T_142 - skip - node T_143 = and(io.wide.req_data.valid, io.wide.req_data.ready) - when T_143 : + node T_137 = add(send_cnt, UInt<1>("h01")) + node T_138 = tail(T_137, 1) + send_cnt <= T_138 + node T_140 = dshr(out_buf, UInt<5>("h010")) + out_buf <= T_140 + skip + node T_141 = and(io.wide.req_cmd.valid, io.wide.req_cmd.ready) + when T_141 : + node T_142 = cat(io.wide.req_cmd.bits.tag, io.wide.req_cmd.bits.rw) + node T_143 = cat(io.wide.req_cmd.bits.addr, T_142) + out_buf <= T_143 + skip + node T_144 = and(io.wide.req_data.valid, io.wide.req_data.ready) + when T_144 : out_buf <= io.wide.req_data.bits.data skip - node T_144 = eq(state, UInt<1>("h00")) - io.wide.req_cmd.ready <= T_144 - node T_145 = eq(state, UInt<2>("h03")) - io.wide.req_data.ready <= T_145 - node T_146 = eq(state, UInt<1>("h01")) - node T_147 = eq(state, UInt<2>("h02")) - node T_148 = or(T_146, T_147) - node T_149 = eq(state, UInt<3>("h04")) - node T_150 = or(T_148, T_149) - io.narrow.req.valid <= T_150 + node T_145 = eq(state, UInt<1>("h00")) + io.wide.req_cmd.ready <= T_145 + node T_146 = eq(state, UInt<2>("h03")) + io.wide.req_data.ready <= T_146 + node T_147 = eq(state, UInt<1>("h01")) + node T_148 = eq(state, UInt<2>("h02")) + node T_149 = or(T_147, T_148) + node T_150 = eq(state, UInt<3>("h04")) + node T_151 = or(T_149, T_150) + io.narrow.req.valid <= T_151 io.narrow.req.bits <= out_buf - node T_151 = eq(state, UInt<1>("h00")) - node T_152 = and(T_151, io.wide.req_cmd.valid) - when T_152 : - node T_153 = mux(io.wide.req_cmd.bits.rw, UInt<2>("h02"), UInt<1>("h01")) - state <= T_153 - skip - node T_154 = eq(state, UInt<1>("h01")) - node T_155 = and(T_154, adone) - when T_155 : + node T_152 = eq(state, UInt<1>("h00")) + node T_153 = and(T_152, io.wide.req_cmd.valid) + when T_153 : + node T_154 = mux(io.wide.req_cmd.bits.rw, UInt<2>("h02"), UInt<1>("h01")) + state <= T_154 + skip + node T_155 = eq(state, UInt<1>("h01")) + node T_156 = and(T_155, adone) + when T_156 : state <= UInt<1>("h00") send_cnt <= UInt<1>("h00") skip - node T_157 = eq(state, UInt<2>("h02")) - node T_158 = and(T_157, adone) - when T_158 : + node T_158 = eq(state, UInt<2>("h02")) + node T_159 = and(T_158, adone) + when T_159 : state <= UInt<2>("h03") send_cnt <= UInt<1>("h00") skip - node T_160 = eq(state, UInt<2>("h03")) - node T_161 = and(T_160, io.wide.req_data.valid) - when T_161 : + node T_161 = eq(state, UInt<2>("h03")) + node T_162 = and(T_161, io.wide.req_data.valid) + when T_162 : state <= UInt<3>("h04") skip - node T_162 = eq(state, UInt<3>("h04")) - node T_163 = and(T_162, ddone) - when T_163 : - node T_165 = addw(data_send_cnt, UInt<1>("h01")) - data_send_cnt <= T_165 - node T_167 = eq(data_send_cnt, UInt<3>("h07")) - node T_168 = mux(T_167, UInt<1>("h00"), UInt<2>("h03")) - state <= T_168 + node T_163 = eq(state, UInt<3>("h04")) + node T_164 = and(T_163, ddone) + when T_164 : + node T_166 = add(data_send_cnt, UInt<1>("h01")) + node T_167 = tail(T_166, 1) + data_send_cnt <= T_167 + node T_169 = eq(data_send_cnt, UInt<3>("h07")) + node T_170 = mux(T_169, UInt<1>("h00"), UInt<2>("h03")) + state <= T_170 send_cnt <= UInt<1>("h00") skip - reg recv_cnt : UInt<3>, clk, reset, UInt<3>("h00") - reg data_recv_cnt : UInt<3>, clk, reset, UInt<3>("h00") - reg resp_val : UInt<1>, clk, reset, UInt<1>("h00") + reg recv_cnt : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + reg data_recv_cnt : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + reg resp_val : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) resp_val <= UInt<1>("h00") when io.narrow.resp.valid : - node T_178 = addw(recv_cnt, UInt<1>("h01")) - recv_cnt <= T_178 - node T_180 = eq(recv_cnt, UInt<3>("h04")) - when T_180 : + node T_180 = add(recv_cnt, UInt<1>("h01")) + node T_181 = tail(T_180, 1) + recv_cnt <= T_181 + node T_183 = eq(recv_cnt, UInt<3>("h04")) + when T_183 : recv_cnt <= UInt<1>("h00") - node T_183 = addw(data_recv_cnt, UInt<1>("h01")) - data_recv_cnt <= T_183 + node T_186 = add(data_recv_cnt, UInt<1>("h01")) + node T_187 = tail(T_186, 1) + data_recv_cnt <= T_187 resp_val <= UInt<1>("h01") skip - node T_185 = bits(in_buf, 79, 16) - node T_186 = cat(io.narrow.resp.bits, T_185) - in_buf <= T_186 + node T_189 = bits(in_buf, 79, 16) + node T_190 = cat(io.narrow.resp.bits, T_189) + in_buf <= T_190 skip io.wide.resp.valid <= resp_val - wire T_190 : {data : UInt<64>, tag : UInt<5>} - T_190.tag <= UInt<1>("h00") - T_190.data <= UInt<1>("h00") - node T_195 = bits(in_buf, 4, 0) - T_190.tag <= T_195 - node T_196 = bits(in_buf, 68, 5) - T_190.data <= T_196 - io.wide.resp.bits <- T_190 + wire T_194 : {data : UInt<64>, tag : UInt<5>} + T_194 is invalid + node T_197 = bits(in_buf, 4, 0) + T_194.tag <= T_197 + node T_198 = bits(in_buf, 68, 5) + T_194.data <= T_198 + io.wide.resp.bits <- T_194 module OuterMemorySystem : input clk : Clock input reset : UInt<1> output io : {flip tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[1], flip tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[1], flip htif_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, flip incoherent : UInt<1>[1], mem : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], mem_backup : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, flip resp : {valid : UInt<1>, bits : UInt<16>}}, flip mem_backup_en : UInt<1>, csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}[1], scr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, mmio : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, deviceTree : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, flip dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}} - io.dma.resp.bits.status <= UInt<1>("h00") - io.dma.resp.bits.client_xact_id <= UInt<1>("h00") - io.dma.resp.valid <= UInt<1>("h00") - io.dma.req.ready <= UInt<1>("h00") - io.deviceTree.r.ready <= UInt<1>("h00") - io.deviceTree.ar.bits.user <= UInt<1>("h00") - io.deviceTree.ar.bits.id <= UInt<1>("h00") - io.deviceTree.ar.bits.region <= UInt<1>("h00") - io.deviceTree.ar.bits.qos <= UInt<1>("h00") - io.deviceTree.ar.bits.prot <= UInt<1>("h00") - io.deviceTree.ar.bits.cache <= UInt<1>("h00") - io.deviceTree.ar.bits.lock <= UInt<1>("h00") - io.deviceTree.ar.bits.burst <= UInt<1>("h00") - io.deviceTree.ar.bits.size <= UInt<1>("h00") - io.deviceTree.ar.bits.len <= UInt<1>("h00") - io.deviceTree.ar.bits.addr <= UInt<1>("h00") - io.deviceTree.ar.valid <= UInt<1>("h00") - io.deviceTree.b.ready <= UInt<1>("h00") - io.deviceTree.w.bits.user <= UInt<1>("h00") - io.deviceTree.w.bits.strb <= UInt<1>("h00") - io.deviceTree.w.bits.last <= UInt<1>("h00") - io.deviceTree.w.bits.data <= UInt<1>("h00") - io.deviceTree.w.valid <= UInt<1>("h00") - io.deviceTree.aw.bits.user <= UInt<1>("h00") - io.deviceTree.aw.bits.id <= UInt<1>("h00") - io.deviceTree.aw.bits.region <= UInt<1>("h00") - io.deviceTree.aw.bits.qos <= UInt<1>("h00") - io.deviceTree.aw.bits.prot <= UInt<1>("h00") - io.deviceTree.aw.bits.cache <= UInt<1>("h00") - io.deviceTree.aw.bits.lock <= UInt<1>("h00") - io.deviceTree.aw.bits.burst <= UInt<1>("h00") - io.deviceTree.aw.bits.size <= UInt<1>("h00") - io.deviceTree.aw.bits.len <= UInt<1>("h00") - io.deviceTree.aw.bits.addr <= UInt<1>("h00") - io.deviceTree.aw.valid <= UInt<1>("h00") - io.mmio.r.ready <= UInt<1>("h00") - io.mmio.ar.bits.user <= UInt<1>("h00") - io.mmio.ar.bits.id <= UInt<1>("h00") - io.mmio.ar.bits.region <= UInt<1>("h00") - io.mmio.ar.bits.qos <= UInt<1>("h00") - io.mmio.ar.bits.prot <= UInt<1>("h00") - io.mmio.ar.bits.cache <= UInt<1>("h00") - io.mmio.ar.bits.lock <= UInt<1>("h00") - io.mmio.ar.bits.burst <= UInt<1>("h00") - io.mmio.ar.bits.size <= UInt<1>("h00") - io.mmio.ar.bits.len <= UInt<1>("h00") - io.mmio.ar.bits.addr <= UInt<1>("h00") - io.mmio.ar.valid <= UInt<1>("h00") - io.mmio.b.ready <= UInt<1>("h00") - io.mmio.w.bits.user <= UInt<1>("h00") - io.mmio.w.bits.strb <= UInt<1>("h00") - io.mmio.w.bits.last <= UInt<1>("h00") - io.mmio.w.bits.data <= UInt<1>("h00") - io.mmio.w.valid <= UInt<1>("h00") - io.mmio.aw.bits.user <= UInt<1>("h00") - io.mmio.aw.bits.id <= UInt<1>("h00") - io.mmio.aw.bits.region <= UInt<1>("h00") - io.mmio.aw.bits.qos <= UInt<1>("h00") - io.mmio.aw.bits.prot <= UInt<1>("h00") - io.mmio.aw.bits.cache <= UInt<1>("h00") - io.mmio.aw.bits.lock <= UInt<1>("h00") - io.mmio.aw.bits.burst <= UInt<1>("h00") - io.mmio.aw.bits.size <= UInt<1>("h00") - io.mmio.aw.bits.len <= UInt<1>("h00") - io.mmio.aw.bits.addr <= UInt<1>("h00") - io.mmio.aw.valid <= UInt<1>("h00") - io.scr.resp.ready <= UInt<1>("h00") - io.scr.req.bits.data <= UInt<1>("h00") - io.scr.req.bits.addr <= UInt<1>("h00") - io.scr.req.bits.rw <= UInt<1>("h00") - io.scr.req.valid <= UInt<1>("h00") - io.csr[0].resp.ready <= UInt<1>("h00") - io.csr[0].req.bits.data <= UInt<1>("h00") - io.csr[0].req.bits.addr <= UInt<1>("h00") - io.csr[0].req.bits.rw <= UInt<1>("h00") - io.csr[0].req.valid <= UInt<1>("h00") - io.mem_backup.req.bits <= UInt<1>("h00") - io.mem_backup.req.valid <= UInt<1>("h00") - io.mem[0].r.ready <= UInt<1>("h00") - io.mem[0].ar.bits.user <= UInt<1>("h00") - io.mem[0].ar.bits.id <= UInt<1>("h00") - io.mem[0].ar.bits.region <= UInt<1>("h00") - io.mem[0].ar.bits.qos <= UInt<1>("h00") - io.mem[0].ar.bits.prot <= UInt<1>("h00") - io.mem[0].ar.bits.cache <= UInt<1>("h00") - io.mem[0].ar.bits.lock <= UInt<1>("h00") - io.mem[0].ar.bits.burst <= UInt<1>("h00") - io.mem[0].ar.bits.size <= UInt<1>("h00") - io.mem[0].ar.bits.len <= UInt<1>("h00") - io.mem[0].ar.bits.addr <= UInt<1>("h00") - io.mem[0].ar.valid <= UInt<1>("h00") - io.mem[0].b.ready <= UInt<1>("h00") - io.mem[0].w.bits.user <= UInt<1>("h00") - io.mem[0].w.bits.strb <= UInt<1>("h00") - io.mem[0].w.bits.last <= UInt<1>("h00") - io.mem[0].w.bits.data <= UInt<1>("h00") - io.mem[0].w.valid <= UInt<1>("h00") - io.mem[0].aw.bits.user <= UInt<1>("h00") - io.mem[0].aw.bits.id <= UInt<1>("h00") - io.mem[0].aw.bits.region <= UInt<1>("h00") - io.mem[0].aw.bits.qos <= UInt<1>("h00") - io.mem[0].aw.bits.prot <= UInt<1>("h00") - io.mem[0].aw.bits.cache <= UInt<1>("h00") - io.mem[0].aw.bits.lock <= UInt<1>("h00") - io.mem[0].aw.bits.burst <= UInt<1>("h00") - io.mem[0].aw.bits.size <= UInt<1>("h00") - io.mem[0].aw.bits.len <= UInt<1>("h00") - io.mem[0].aw.bits.addr <= UInt<1>("h00") - io.mem[0].aw.valid <= UInt<1>("h00") - io.htif_uncached.grant.bits.data <= UInt<1>("h00") - io.htif_uncached.grant.bits.g_type <= UInt<1>("h00") - io.htif_uncached.grant.bits.is_builtin_type <= UInt<1>("h00") - io.htif_uncached.grant.bits.manager_xact_id <= UInt<1>("h00") - io.htif_uncached.grant.bits.client_xact_id <= UInt<1>("h00") - io.htif_uncached.grant.bits.addr_beat <= UInt<1>("h00") - io.htif_uncached.grant.valid <= UInt<1>("h00") - io.htif_uncached.acquire.ready <= UInt<1>("h00") - io.tiles_uncached[0].grant.bits.data <= UInt<1>("h00") - io.tiles_uncached[0].grant.bits.g_type <= UInt<1>("h00") - io.tiles_uncached[0].grant.bits.is_builtin_type <= UInt<1>("h00") - io.tiles_uncached[0].grant.bits.manager_xact_id <= UInt<1>("h00") - io.tiles_uncached[0].grant.bits.client_xact_id <= UInt<1>("h00") - io.tiles_uncached[0].grant.bits.addr_beat <= UInt<1>("h00") - io.tiles_uncached[0].grant.valid <= UInt<1>("h00") - io.tiles_uncached[0].acquire.ready <= UInt<1>("h00") - io.tiles_cached[0].release.ready <= UInt<1>("h00") - io.tiles_cached[0].probe.bits.p_type <= UInt<1>("h00") - io.tiles_cached[0].probe.bits.addr_block <= UInt<1>("h00") - io.tiles_cached[0].probe.valid <= UInt<1>("h00") - io.tiles_cached[0].grant.bits.data <= UInt<1>("h00") - io.tiles_cached[0].grant.bits.g_type <= UInt<1>("h00") - io.tiles_cached[0].grant.bits.is_builtin_type <= UInt<1>("h00") - io.tiles_cached[0].grant.bits.manager_xact_id <= UInt<1>("h00") - io.tiles_cached[0].grant.bits.client_xact_id <= UInt<1>("h00") - io.tiles_cached[0].grant.bits.addr_beat <= UInt<1>("h00") - io.tiles_cached[0].grant.valid <= UInt<1>("h00") - io.tiles_cached[0].acquire.ready <= UInt<1>("h00") + io is invalid inst T_8064 of ClientTileLinkIOWrapper - T_8064.io.out.release.ready <= UInt<1>("h00") - T_8064.io.out.probe.bits.p_type <= UInt<1>("h00") - T_8064.io.out.probe.bits.addr_block <= UInt<1>("h00") - T_8064.io.out.probe.valid <= UInt<1>("h00") - T_8064.io.out.grant.bits.data <= UInt<1>("h00") - T_8064.io.out.grant.bits.g_type <= UInt<1>("h00") - T_8064.io.out.grant.bits.is_builtin_type <= UInt<1>("h00") - T_8064.io.out.grant.bits.manager_xact_id <= UInt<1>("h00") - T_8064.io.out.grant.bits.client_xact_id <= UInt<1>("h00") - T_8064.io.out.grant.bits.addr_beat <= UInt<1>("h00") - T_8064.io.out.grant.valid <= UInt<1>("h00") - T_8064.io.out.acquire.ready <= UInt<1>("h00") - T_8064.io.in.grant.ready <= UInt<1>("h00") - T_8064.io.in.acquire.bits.data <= UInt<1>("h00") - T_8064.io.in.acquire.bits.union <= UInt<1>("h00") - T_8064.io.in.acquire.bits.a_type <= UInt<1>("h00") - T_8064.io.in.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_8064.io.in.acquire.bits.addr_beat <= UInt<1>("h00") - T_8064.io.in.acquire.bits.client_xact_id <= UInt<1>("h00") - T_8064.io.in.acquire.bits.addr_block <= UInt<1>("h00") - T_8064.io.in.acquire.valid <= UInt<1>("h00") + T_8064.io is invalid T_8064.clk <= clk T_8064.reset <= reset T_8064.io.in <- io.tiles_uncached[0] - inst T_8086 of ClientTileLinkIOWrapper - T_8086.io.out.release.ready <= UInt<1>("h00") - T_8086.io.out.probe.bits.p_type <= UInt<1>("h00") - T_8086.io.out.probe.bits.addr_block <= UInt<1>("h00") - T_8086.io.out.probe.valid <= UInt<1>("h00") - T_8086.io.out.grant.bits.data <= UInt<1>("h00") - T_8086.io.out.grant.bits.g_type <= UInt<1>("h00") - T_8086.io.out.grant.bits.is_builtin_type <= UInt<1>("h00") - T_8086.io.out.grant.bits.manager_xact_id <= UInt<1>("h00") - T_8086.io.out.grant.bits.client_xact_id <= UInt<1>("h00") - T_8086.io.out.grant.bits.addr_beat <= UInt<1>("h00") - T_8086.io.out.grant.valid <= UInt<1>("h00") - T_8086.io.out.acquire.ready <= UInt<1>("h00") - T_8086.io.in.grant.ready <= UInt<1>("h00") - T_8086.io.in.acquire.bits.data <= UInt<1>("h00") - T_8086.io.in.acquire.bits.union <= UInt<1>("h00") - T_8086.io.in.acquire.bits.a_type <= UInt<1>("h00") - T_8086.io.in.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_8086.io.in.acquire.bits.addr_beat <= UInt<1>("h00") - T_8086.io.in.acquire.bits.client_xact_id <= UInt<1>("h00") - T_8086.io.in.acquire.bits.addr_block <= UInt<1>("h00") - T_8086.io.in.acquire.valid <= UInt<1>("h00") - T_8086.clk <= clk - T_8086.reset <= reset - T_8086.io.in <- io.htif_uncached + inst T_8065 of ClientTileLinkIOWrapper + T_8065.io is invalid + T_8065.clk <= clk + T_8065.reset <= reset + T_8065.io.in <- io.htif_uncached inst l1tol2net of RocketChipTileLinkArbiter - l1tol2net.io.managers[0].release.ready <= UInt<1>("h00") - l1tol2net.io.managers[0].probe.bits.client_id <= UInt<1>("h00") - l1tol2net.io.managers[0].probe.bits.p_type <= UInt<1>("h00") - l1tol2net.io.managers[0].probe.bits.addr_block <= UInt<1>("h00") - l1tol2net.io.managers[0].probe.valid <= UInt<1>("h00") - l1tol2net.io.managers[0].finish.ready <= UInt<1>("h00") - l1tol2net.io.managers[0].grant.bits.client_id <= UInt<1>("h00") - l1tol2net.io.managers[0].grant.bits.data <= UInt<1>("h00") - l1tol2net.io.managers[0].grant.bits.g_type <= UInt<1>("h00") - l1tol2net.io.managers[0].grant.bits.is_builtin_type <= UInt<1>("h00") - l1tol2net.io.managers[0].grant.bits.manager_xact_id <= UInt<1>("h00") - l1tol2net.io.managers[0].grant.bits.client_xact_id <= UInt<1>("h00") - l1tol2net.io.managers[0].grant.bits.addr_beat <= UInt<1>("h00") - l1tol2net.io.managers[0].grant.valid <= UInt<1>("h00") - l1tol2net.io.managers[0].acquire.ready <= UInt<1>("h00") - l1tol2net.io.clients[0].release.bits.data <= UInt<1>("h00") - l1tol2net.io.clients[0].release.bits.r_type <= UInt<1>("h00") - l1tol2net.io.clients[0].release.bits.voluntary <= UInt<1>("h00") - l1tol2net.io.clients[0].release.bits.client_xact_id <= UInt<1>("h00") - l1tol2net.io.clients[0].release.bits.addr_block <= UInt<1>("h00") - l1tol2net.io.clients[0].release.bits.addr_beat <= UInt<1>("h00") - l1tol2net.io.clients[0].release.valid <= UInt<1>("h00") - l1tol2net.io.clients[0].probe.ready <= UInt<1>("h00") - l1tol2net.io.clients[0].grant.ready <= UInt<1>("h00") - l1tol2net.io.clients[0].acquire.bits.data <= UInt<1>("h00") - l1tol2net.io.clients[0].acquire.bits.union <= UInt<1>("h00") - l1tol2net.io.clients[0].acquire.bits.a_type <= UInt<1>("h00") - l1tol2net.io.clients[0].acquire.bits.is_builtin_type <= UInt<1>("h00") - l1tol2net.io.clients[0].acquire.bits.addr_beat <= UInt<1>("h00") - l1tol2net.io.clients[0].acquire.bits.client_xact_id <= UInt<1>("h00") - l1tol2net.io.clients[0].acquire.bits.addr_block <= UInt<1>("h00") - l1tol2net.io.clients[0].acquire.valid <= UInt<1>("h00") - l1tol2net.io.clients[1].release.bits.data <= UInt<1>("h00") - l1tol2net.io.clients[1].release.bits.r_type <= UInt<1>("h00") - l1tol2net.io.clients[1].release.bits.voluntary <= UInt<1>("h00") - l1tol2net.io.clients[1].release.bits.client_xact_id <= UInt<1>("h00") - l1tol2net.io.clients[1].release.bits.addr_block <= UInt<1>("h00") - l1tol2net.io.clients[1].release.bits.addr_beat <= UInt<1>("h00") - l1tol2net.io.clients[1].release.valid <= UInt<1>("h00") - l1tol2net.io.clients[1].probe.ready <= UInt<1>("h00") - l1tol2net.io.clients[1].grant.ready <= UInt<1>("h00") - l1tol2net.io.clients[1].acquire.bits.data <= UInt<1>("h00") - l1tol2net.io.clients[1].acquire.bits.union <= UInt<1>("h00") - l1tol2net.io.clients[1].acquire.bits.a_type <= UInt<1>("h00") - l1tol2net.io.clients[1].acquire.bits.is_builtin_type <= UInt<1>("h00") - l1tol2net.io.clients[1].acquire.bits.addr_beat <= UInt<1>("h00") - l1tol2net.io.clients[1].acquire.bits.client_xact_id <= UInt<1>("h00") - l1tol2net.io.clients[1].acquire.bits.addr_block <= UInt<1>("h00") - l1tol2net.io.clients[1].acquire.valid <= UInt<1>("h00") - l1tol2net.io.clients[2].release.bits.data <= UInt<1>("h00") - l1tol2net.io.clients[2].release.bits.r_type <= UInt<1>("h00") - l1tol2net.io.clients[2].release.bits.voluntary <= UInt<1>("h00") - l1tol2net.io.clients[2].release.bits.client_xact_id <= UInt<1>("h00") - l1tol2net.io.clients[2].release.bits.addr_block <= UInt<1>("h00") - l1tol2net.io.clients[2].release.bits.addr_beat <= UInt<1>("h00") - l1tol2net.io.clients[2].release.valid <= UInt<1>("h00") - l1tol2net.io.clients[2].probe.ready <= UInt<1>("h00") - l1tol2net.io.clients[2].grant.ready <= UInt<1>("h00") - l1tol2net.io.clients[2].acquire.bits.data <= UInt<1>("h00") - l1tol2net.io.clients[2].acquire.bits.union <= UInt<1>("h00") - l1tol2net.io.clients[2].acquire.bits.a_type <= UInt<1>("h00") - l1tol2net.io.clients[2].acquire.bits.is_builtin_type <= UInt<1>("h00") - l1tol2net.io.clients[2].acquire.bits.addr_beat <= UInt<1>("h00") - l1tol2net.io.clients[2].acquire.bits.client_xact_id <= UInt<1>("h00") - l1tol2net.io.clients[2].acquire.bits.addr_block <= UInt<1>("h00") - l1tol2net.io.clients[2].acquire.valid <= UInt<1>("h00") + l1tol2net.io is invalid l1tol2net.clk <= clk l1tol2net.reset <= reset - inst T_8175 of L2BroadcastHub - T_8175.io.outer.grant.bits.data <= UInt<1>("h00") - T_8175.io.outer.grant.bits.g_type <= UInt<1>("h00") - T_8175.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") - T_8175.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") - T_8175.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") - T_8175.io.outer.grant.bits.addr_beat <= UInt<1>("h00") - T_8175.io.outer.grant.valid <= UInt<1>("h00") - T_8175.io.outer.acquire.ready <= UInt<1>("h00") - T_8175.io.incoherent[0] <= UInt<1>("h00") - T_8175.io.inner.release.bits.client_id <= UInt<1>("h00") - T_8175.io.inner.release.bits.data <= UInt<1>("h00") - T_8175.io.inner.release.bits.r_type <= UInt<1>("h00") - T_8175.io.inner.release.bits.voluntary <= UInt<1>("h00") - T_8175.io.inner.release.bits.client_xact_id <= UInt<1>("h00") - T_8175.io.inner.release.bits.addr_block <= UInt<1>("h00") - T_8175.io.inner.release.bits.addr_beat <= UInt<1>("h00") - T_8175.io.inner.release.valid <= UInt<1>("h00") - T_8175.io.inner.probe.ready <= UInt<1>("h00") - T_8175.io.inner.finish.bits.manager_xact_id <= UInt<1>("h00") - T_8175.io.inner.finish.valid <= UInt<1>("h00") - T_8175.io.inner.grant.ready <= UInt<1>("h00") - T_8175.io.inner.acquire.bits.client_id <= UInt<1>("h00") - T_8175.io.inner.acquire.bits.data <= UInt<1>("h00") - T_8175.io.inner.acquire.bits.union <= UInt<1>("h00") - T_8175.io.inner.acquire.bits.a_type <= UInt<1>("h00") - T_8175.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_8175.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") - T_8175.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") - T_8175.io.inner.acquire.bits.addr_block <= UInt<1>("h00") - T_8175.io.inner.acquire.valid <= UInt<1>("h00") - T_8175.clk <= clk - T_8175.reset <= reset - T_8175.io.incoherent <= io.incoherent + inst T_8067 of L2BroadcastHub + T_8067.io is invalid + T_8067.clk <= clk + T_8067.reset <= reset + T_8067.io.incoherent <= io.incoherent l1tol2net.io.clients[0] <- io.tiles_cached[0] l1tol2net.io.clients[1] <- T_8064.io.out - l1tol2net.io.clients[2] <- T_8086.io.out - l1tol2net.io.managers[0] <- T_8175.io.inner + l1tol2net.io.clients[2] <- T_8065.io.out + l1tol2net.io.managers[0] <- T_8067.io.inner inst interconnect of NastiRecursiveInterconnect - interconnect.io.slaves[0].r.bits.user <= UInt<1>("h00") - interconnect.io.slaves[0].r.bits.id <= UInt<1>("h00") - interconnect.io.slaves[0].r.bits.last <= UInt<1>("h00") - interconnect.io.slaves[0].r.bits.data <= UInt<1>("h00") - interconnect.io.slaves[0].r.bits.resp <= UInt<1>("h00") - interconnect.io.slaves[0].r.valid <= UInt<1>("h00") - interconnect.io.slaves[0].ar.ready <= UInt<1>("h00") - interconnect.io.slaves[0].b.bits.user <= UInt<1>("h00") - interconnect.io.slaves[0].b.bits.id <= UInt<1>("h00") - interconnect.io.slaves[0].b.bits.resp <= UInt<1>("h00") - interconnect.io.slaves[0].b.valid <= UInt<1>("h00") - interconnect.io.slaves[0].w.ready <= UInt<1>("h00") - interconnect.io.slaves[0].aw.ready <= UInt<1>("h00") - interconnect.io.slaves[1].r.bits.user <= UInt<1>("h00") - interconnect.io.slaves[1].r.bits.id <= UInt<1>("h00") - interconnect.io.slaves[1].r.bits.last <= UInt<1>("h00") - interconnect.io.slaves[1].r.bits.data <= UInt<1>("h00") - interconnect.io.slaves[1].r.bits.resp <= UInt<1>("h00") - interconnect.io.slaves[1].r.valid <= UInt<1>("h00") - interconnect.io.slaves[1].ar.ready <= UInt<1>("h00") - interconnect.io.slaves[1].b.bits.user <= UInt<1>("h00") - interconnect.io.slaves[1].b.bits.id <= UInt<1>("h00") - interconnect.io.slaves[1].b.bits.resp <= UInt<1>("h00") - interconnect.io.slaves[1].b.valid <= UInt<1>("h00") - interconnect.io.slaves[1].w.ready <= UInt<1>("h00") - interconnect.io.slaves[1].aw.ready <= UInt<1>("h00") - interconnect.io.slaves[2].r.bits.user <= UInt<1>("h00") - interconnect.io.slaves[2].r.bits.id <= UInt<1>("h00") - interconnect.io.slaves[2].r.bits.last <= UInt<1>("h00") - interconnect.io.slaves[2].r.bits.data <= UInt<1>("h00") - interconnect.io.slaves[2].r.bits.resp <= UInt<1>("h00") - interconnect.io.slaves[2].r.valid <= UInt<1>("h00") - interconnect.io.slaves[2].ar.ready <= UInt<1>("h00") - interconnect.io.slaves[2].b.bits.user <= UInt<1>("h00") - interconnect.io.slaves[2].b.bits.id <= UInt<1>("h00") - interconnect.io.slaves[2].b.bits.resp <= UInt<1>("h00") - interconnect.io.slaves[2].b.valid <= UInt<1>("h00") - interconnect.io.slaves[2].w.ready <= UInt<1>("h00") - interconnect.io.slaves[2].aw.ready <= UInt<1>("h00") - interconnect.io.slaves[3].r.bits.user <= UInt<1>("h00") - interconnect.io.slaves[3].r.bits.id <= UInt<1>("h00") - interconnect.io.slaves[3].r.bits.last <= UInt<1>("h00") - interconnect.io.slaves[3].r.bits.data <= UInt<1>("h00") - interconnect.io.slaves[3].r.bits.resp <= UInt<1>("h00") - interconnect.io.slaves[3].r.valid <= UInt<1>("h00") - interconnect.io.slaves[3].ar.ready <= UInt<1>("h00") - interconnect.io.slaves[3].b.bits.user <= UInt<1>("h00") - interconnect.io.slaves[3].b.bits.id <= UInt<1>("h00") - interconnect.io.slaves[3].b.bits.resp <= UInt<1>("h00") - interconnect.io.slaves[3].b.valid <= UInt<1>("h00") - interconnect.io.slaves[3].w.ready <= UInt<1>("h00") - interconnect.io.slaves[3].aw.ready <= UInt<1>("h00") - interconnect.io.slaves[4].r.bits.user <= UInt<1>("h00") - interconnect.io.slaves[4].r.bits.id <= UInt<1>("h00") - interconnect.io.slaves[4].r.bits.last <= UInt<1>("h00") - interconnect.io.slaves[4].r.bits.data <= UInt<1>("h00") - interconnect.io.slaves[4].r.bits.resp <= UInt<1>("h00") - interconnect.io.slaves[4].r.valid <= UInt<1>("h00") - interconnect.io.slaves[4].ar.ready <= UInt<1>("h00") - interconnect.io.slaves[4].b.bits.user <= UInt<1>("h00") - interconnect.io.slaves[4].b.bits.id <= UInt<1>("h00") - interconnect.io.slaves[4].b.bits.resp <= UInt<1>("h00") - interconnect.io.slaves[4].b.valid <= UInt<1>("h00") - interconnect.io.slaves[4].w.ready <= UInt<1>("h00") - interconnect.io.slaves[4].aw.ready <= UInt<1>("h00") - interconnect.io.masters[0].r.ready <= UInt<1>("h00") - interconnect.io.masters[0].ar.bits.user <= UInt<1>("h00") - interconnect.io.masters[0].ar.bits.id <= UInt<1>("h00") - interconnect.io.masters[0].ar.bits.region <= UInt<1>("h00") - interconnect.io.masters[0].ar.bits.qos <= UInt<1>("h00") - interconnect.io.masters[0].ar.bits.prot <= UInt<1>("h00") - interconnect.io.masters[0].ar.bits.cache <= UInt<1>("h00") - interconnect.io.masters[0].ar.bits.lock <= UInt<1>("h00") - interconnect.io.masters[0].ar.bits.burst <= UInt<1>("h00") - interconnect.io.masters[0].ar.bits.size <= UInt<1>("h00") - interconnect.io.masters[0].ar.bits.len <= UInt<1>("h00") - interconnect.io.masters[0].ar.bits.addr <= UInt<1>("h00") - interconnect.io.masters[0].ar.valid <= UInt<1>("h00") - interconnect.io.masters[0].b.ready <= UInt<1>("h00") - interconnect.io.masters[0].w.bits.user <= UInt<1>("h00") - interconnect.io.masters[0].w.bits.strb <= UInt<1>("h00") - interconnect.io.masters[0].w.bits.last <= UInt<1>("h00") - interconnect.io.masters[0].w.bits.data <= UInt<1>("h00") - interconnect.io.masters[0].w.valid <= UInt<1>("h00") - interconnect.io.masters[0].aw.bits.user <= UInt<1>("h00") - interconnect.io.masters[0].aw.bits.id <= UInt<1>("h00") - interconnect.io.masters[0].aw.bits.region <= UInt<1>("h00") - interconnect.io.masters[0].aw.bits.qos <= UInt<1>("h00") - interconnect.io.masters[0].aw.bits.prot <= UInt<1>("h00") - interconnect.io.masters[0].aw.bits.cache <= UInt<1>("h00") - interconnect.io.masters[0].aw.bits.lock <= UInt<1>("h00") - interconnect.io.masters[0].aw.bits.burst <= UInt<1>("h00") - interconnect.io.masters[0].aw.bits.size <= UInt<1>("h00") - interconnect.io.masters[0].aw.bits.len <= UInt<1>("h00") - interconnect.io.masters[0].aw.bits.addr <= UInt<1>("h00") - interconnect.io.masters[0].aw.valid <= UInt<1>("h00") - interconnect.io.masters[1].r.ready <= UInt<1>("h00") - interconnect.io.masters[1].ar.bits.user <= UInt<1>("h00") - interconnect.io.masters[1].ar.bits.id <= UInt<1>("h00") - interconnect.io.masters[1].ar.bits.region <= UInt<1>("h00") - interconnect.io.masters[1].ar.bits.qos <= UInt<1>("h00") - interconnect.io.masters[1].ar.bits.prot <= UInt<1>("h00") - interconnect.io.masters[1].ar.bits.cache <= UInt<1>("h00") - interconnect.io.masters[1].ar.bits.lock <= UInt<1>("h00") - interconnect.io.masters[1].ar.bits.burst <= UInt<1>("h00") - interconnect.io.masters[1].ar.bits.size <= UInt<1>("h00") - interconnect.io.masters[1].ar.bits.len <= UInt<1>("h00") - interconnect.io.masters[1].ar.bits.addr <= UInt<1>("h00") - interconnect.io.masters[1].ar.valid <= UInt<1>("h00") - interconnect.io.masters[1].b.ready <= UInt<1>("h00") - interconnect.io.masters[1].w.bits.user <= UInt<1>("h00") - interconnect.io.masters[1].w.bits.strb <= UInt<1>("h00") - interconnect.io.masters[1].w.bits.last <= UInt<1>("h00") - interconnect.io.masters[1].w.bits.data <= UInt<1>("h00") - interconnect.io.masters[1].w.valid <= UInt<1>("h00") - interconnect.io.masters[1].aw.bits.user <= UInt<1>("h00") - interconnect.io.masters[1].aw.bits.id <= UInt<1>("h00") - interconnect.io.masters[1].aw.bits.region <= UInt<1>("h00") - interconnect.io.masters[1].aw.bits.qos <= UInt<1>("h00") - interconnect.io.masters[1].aw.bits.prot <= UInt<1>("h00") - interconnect.io.masters[1].aw.bits.cache <= UInt<1>("h00") - interconnect.io.masters[1].aw.bits.lock <= UInt<1>("h00") - interconnect.io.masters[1].aw.bits.burst <= UInt<1>("h00") - interconnect.io.masters[1].aw.bits.size <= UInt<1>("h00") - interconnect.io.masters[1].aw.bits.len <= UInt<1>("h00") - interconnect.io.masters[1].aw.bits.addr <= UInt<1>("h00") - interconnect.io.masters[1].aw.valid <= UInt<1>("h00") + interconnect.io is invalid interconnect.clk <= clk interconnect.reset <= reset - inst T_8334 of ClientTileLinkIOUnwrapper - T_8334.io.out.grant.bits.data <= UInt<1>("h00") - T_8334.io.out.grant.bits.g_type <= UInt<1>("h00") - T_8334.io.out.grant.bits.is_builtin_type <= UInt<1>("h00") - T_8334.io.out.grant.bits.manager_xact_id <= UInt<1>("h00") - T_8334.io.out.grant.bits.client_xact_id <= UInt<1>("h00") - T_8334.io.out.grant.bits.addr_beat <= UInt<1>("h00") - T_8334.io.out.grant.valid <= UInt<1>("h00") - T_8334.io.out.acquire.ready <= UInt<1>("h00") - T_8334.io.in.release.bits.data <= UInt<1>("h00") - T_8334.io.in.release.bits.r_type <= UInt<1>("h00") - T_8334.io.in.release.bits.voluntary <= UInt<1>("h00") - T_8334.io.in.release.bits.client_xact_id <= UInt<1>("h00") - T_8334.io.in.release.bits.addr_block <= UInt<1>("h00") - T_8334.io.in.release.bits.addr_beat <= UInt<1>("h00") - T_8334.io.in.release.valid <= UInt<1>("h00") - T_8334.io.in.probe.ready <= UInt<1>("h00") - T_8334.io.in.grant.ready <= UInt<1>("h00") - T_8334.io.in.acquire.bits.data <= UInt<1>("h00") - T_8334.io.in.acquire.bits.union <= UInt<1>("h00") - T_8334.io.in.acquire.bits.a_type <= UInt<1>("h00") - T_8334.io.in.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_8334.io.in.acquire.bits.addr_beat <= UInt<1>("h00") - T_8334.io.in.acquire.bits.client_xact_id <= UInt<1>("h00") - T_8334.io.in.acquire.bits.addr_block <= UInt<1>("h00") - T_8334.io.in.acquire.valid <= UInt<1>("h00") - T_8334.clk <= clk - T_8334.reset <= reset - inst T_8360 of TileLinkIONarrower - T_8360.io.out.grant.bits.data <= UInt<1>("h00") - T_8360.io.out.grant.bits.g_type <= UInt<1>("h00") - T_8360.io.out.grant.bits.is_builtin_type <= UInt<1>("h00") - T_8360.io.out.grant.bits.manager_xact_id <= UInt<1>("h00") - T_8360.io.out.grant.bits.client_xact_id <= UInt<1>("h00") - T_8360.io.out.grant.bits.addr_beat <= UInt<1>("h00") - T_8360.io.out.grant.valid <= UInt<1>("h00") - T_8360.io.out.acquire.ready <= UInt<1>("h00") - T_8360.io.in.grant.ready <= UInt<1>("h00") - T_8360.io.in.acquire.bits.data <= UInt<1>("h00") - T_8360.io.in.acquire.bits.union <= UInt<1>("h00") - T_8360.io.in.acquire.bits.a_type <= UInt<1>("h00") - T_8360.io.in.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_8360.io.in.acquire.bits.addr_beat <= UInt<1>("h00") - T_8360.io.in.acquire.bits.client_xact_id <= UInt<1>("h00") - T_8360.io.in.acquire.bits.addr_block <= UInt<1>("h00") - T_8360.io.in.acquire.valid <= UInt<1>("h00") - T_8360.clk <= clk - T_8360.reset <= reset - inst T_8378 of NastiIOTileLinkIOConverter - T_8378.io.nasti.r.bits.user <= UInt<1>("h00") - T_8378.io.nasti.r.bits.id <= UInt<1>("h00") - T_8378.io.nasti.r.bits.last <= UInt<1>("h00") - T_8378.io.nasti.r.bits.data <= UInt<1>("h00") - T_8378.io.nasti.r.bits.resp <= UInt<1>("h00") - T_8378.io.nasti.r.valid <= UInt<1>("h00") - T_8378.io.nasti.ar.ready <= UInt<1>("h00") - T_8378.io.nasti.b.bits.user <= UInt<1>("h00") - T_8378.io.nasti.b.bits.id <= UInt<1>("h00") - T_8378.io.nasti.b.bits.resp <= UInt<1>("h00") - T_8378.io.nasti.b.valid <= UInt<1>("h00") - T_8378.io.nasti.w.ready <= UInt<1>("h00") - T_8378.io.nasti.aw.ready <= UInt<1>("h00") - T_8378.io.tl.grant.ready <= UInt<1>("h00") - T_8378.io.tl.acquire.bits.data <= UInt<1>("h00") - T_8378.io.tl.acquire.bits.union <= UInt<1>("h00") - T_8378.io.tl.acquire.bits.a_type <= UInt<1>("h00") - T_8378.io.tl.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_8378.io.tl.acquire.bits.addr_beat <= UInt<1>("h00") - T_8378.io.tl.acquire.bits.client_xact_id <= UInt<1>("h00") - T_8378.io.tl.acquire.bits.addr_block <= UInt<1>("h00") - T_8378.io.tl.acquire.valid <= UInt<1>("h00") - T_8378.clk <= clk - T_8378.reset <= reset - inst T_8401 of ClientTileLinkIOWrapper_71 - T_8401.io.out.release.ready <= UInt<1>("h00") - T_8401.io.out.probe.bits.p_type <= UInt<1>("h00") - T_8401.io.out.probe.bits.addr_block <= UInt<1>("h00") - T_8401.io.out.probe.valid <= UInt<1>("h00") - T_8401.io.out.grant.bits.data <= UInt<1>("h00") - T_8401.io.out.grant.bits.g_type <= UInt<1>("h00") - T_8401.io.out.grant.bits.is_builtin_type <= UInt<1>("h00") - T_8401.io.out.grant.bits.manager_xact_id <= UInt<1>("h00") - T_8401.io.out.grant.bits.client_xact_id <= UInt<1>("h00") - T_8401.io.out.grant.bits.addr_beat <= UInt<1>("h00") - T_8401.io.out.grant.valid <= UInt<1>("h00") - T_8401.io.out.acquire.ready <= UInt<1>("h00") - T_8401.io.in.grant.ready <= UInt<1>("h00") - T_8401.io.in.acquire.bits.data <= UInt<1>("h00") - T_8401.io.in.acquire.bits.union <= UInt<1>("h00") - T_8401.io.in.acquire.bits.a_type <= UInt<1>("h00") - T_8401.io.in.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_8401.io.in.acquire.bits.addr_beat <= UInt<1>("h00") - T_8401.io.in.acquire.bits.client_xact_id <= UInt<1>("h00") - T_8401.io.in.acquire.bits.addr_block <= UInt<1>("h00") - T_8401.io.in.acquire.valid <= UInt<1>("h00") - T_8401.clk <= clk - T_8401.reset <= reset - T_8401.io.in <- T_8175.io.outer - inst T_8423 of ClientTileLinkEnqueuer - T_8423.io.outer.release.ready <= UInt<1>("h00") - T_8423.io.outer.probe.bits.p_type <= UInt<1>("h00") - T_8423.io.outer.probe.bits.addr_block <= UInt<1>("h00") - T_8423.io.outer.probe.valid <= UInt<1>("h00") - T_8423.io.outer.grant.bits.data <= UInt<1>("h00") - T_8423.io.outer.grant.bits.g_type <= UInt<1>("h00") - T_8423.io.outer.grant.bits.is_builtin_type <= UInt<1>("h00") - T_8423.io.outer.grant.bits.manager_xact_id <= UInt<1>("h00") - T_8423.io.outer.grant.bits.client_xact_id <= UInt<1>("h00") - T_8423.io.outer.grant.bits.addr_beat <= UInt<1>("h00") - T_8423.io.outer.grant.valid <= UInt<1>("h00") - T_8423.io.outer.acquire.ready <= UInt<1>("h00") - T_8423.io.inner.release.bits.data <= UInt<1>("h00") - T_8423.io.inner.release.bits.r_type <= UInt<1>("h00") - T_8423.io.inner.release.bits.voluntary <= UInt<1>("h00") - T_8423.io.inner.release.bits.client_xact_id <= UInt<1>("h00") - T_8423.io.inner.release.bits.addr_block <= UInt<1>("h00") - T_8423.io.inner.release.bits.addr_beat <= UInt<1>("h00") - T_8423.io.inner.release.valid <= UInt<1>("h00") - T_8423.io.inner.probe.ready <= UInt<1>("h00") - T_8423.io.inner.grant.ready <= UInt<1>("h00") - T_8423.io.inner.acquire.bits.data <= UInt<1>("h00") - T_8423.io.inner.acquire.bits.union <= UInt<1>("h00") - T_8423.io.inner.acquire.bits.a_type <= UInt<1>("h00") - T_8423.io.inner.acquire.bits.is_builtin_type <= UInt<1>("h00") - T_8423.io.inner.acquire.bits.addr_beat <= UInt<1>("h00") - T_8423.io.inner.acquire.bits.client_xact_id <= UInt<1>("h00") - T_8423.io.inner.acquire.bits.addr_block <= UInt<1>("h00") - T_8423.io.inner.acquire.valid <= UInt<1>("h00") - T_8423.clk <= clk - T_8423.reset <= reset - T_8423.io.inner <- T_8401.io.out - T_8334.io.in <- T_8423.io.outer - T_8360.io.in <- T_8334.io.out - T_8378.io.tl <- T_8360.io.out - inst T_8465 of Queue_36 - T_8465.io.deq.ready <= UInt<1>("h00") - T_8465.io.enq.bits.user <= UInt<1>("h00") - T_8465.io.enq.bits.id <= UInt<1>("h00") - T_8465.io.enq.bits.region <= UInt<1>("h00") - T_8465.io.enq.bits.qos <= UInt<1>("h00") - T_8465.io.enq.bits.prot <= UInt<1>("h00") - T_8465.io.enq.bits.cache <= UInt<1>("h00") - T_8465.io.enq.bits.lock <= UInt<1>("h00") - T_8465.io.enq.bits.burst <= UInt<1>("h00") - T_8465.io.enq.bits.size <= UInt<1>("h00") - T_8465.io.enq.bits.len <= UInt<1>("h00") - T_8465.io.enq.bits.addr <= UInt<1>("h00") - T_8465.io.enq.valid <= UInt<1>("h00") - T_8465.clk <= clk - T_8465.reset <= reset - T_8465.io.enq.valid <= T_8378.io.nasti.ar.valid - T_8465.io.enq.bits <- T_8378.io.nasti.ar.bits - T_8378.io.nasti.ar.ready <= T_8465.io.enq.ready - interconnect.io.masters[0].ar <- T_8465.io.deq - inst T_8491 of Queue_36 - T_8491.io.deq.ready <= UInt<1>("h00") - T_8491.io.enq.bits.user <= UInt<1>("h00") - T_8491.io.enq.bits.id <= UInt<1>("h00") - T_8491.io.enq.bits.region <= UInt<1>("h00") - T_8491.io.enq.bits.qos <= UInt<1>("h00") - T_8491.io.enq.bits.prot <= UInt<1>("h00") - T_8491.io.enq.bits.cache <= UInt<1>("h00") - T_8491.io.enq.bits.lock <= UInt<1>("h00") - T_8491.io.enq.bits.burst <= UInt<1>("h00") - T_8491.io.enq.bits.size <= UInt<1>("h00") - T_8491.io.enq.bits.len <= UInt<1>("h00") - T_8491.io.enq.bits.addr <= UInt<1>("h00") - T_8491.io.enq.valid <= UInt<1>("h00") - T_8491.clk <= clk - T_8491.reset <= reset - T_8491.io.enq.valid <= T_8378.io.nasti.aw.valid - T_8491.io.enq.bits <- T_8378.io.nasti.aw.bits - T_8378.io.nasti.aw.ready <= T_8491.io.enq.ready - interconnect.io.masters[0].aw <- T_8491.io.deq - inst T_8510 of Queue_74 - T_8510.io.deq.ready <= UInt<1>("h00") - T_8510.io.enq.bits.user <= UInt<1>("h00") - T_8510.io.enq.bits.strb <= UInt<1>("h00") - T_8510.io.enq.bits.last <= UInt<1>("h00") - T_8510.io.enq.bits.data <= UInt<1>("h00") - T_8510.io.enq.valid <= UInt<1>("h00") - T_8510.clk <= clk - T_8510.reset <= reset - T_8510.io.enq.valid <= T_8378.io.nasti.w.valid - T_8510.io.enq.bits <- T_8378.io.nasti.w.bits - T_8378.io.nasti.w.ready <= T_8510.io.enq.ready - interconnect.io.masters[0].w <- T_8510.io.deq - inst T_8523 of Queue_75 - T_8523.io.deq.ready <= UInt<1>("h00") - T_8523.io.enq.bits.user <= UInt<1>("h00") - T_8523.io.enq.bits.id <= UInt<1>("h00") - T_8523.io.enq.bits.last <= UInt<1>("h00") - T_8523.io.enq.bits.data <= UInt<1>("h00") - T_8523.io.enq.bits.resp <= UInt<1>("h00") - T_8523.io.enq.valid <= UInt<1>("h00") - T_8523.clk <= clk - T_8523.reset <= reset - T_8523.io.enq.valid <= interconnect.io.masters[0].r.valid - T_8523.io.enq.bits <- interconnect.io.masters[0].r.bits - interconnect.io.masters[0].r.ready <= T_8523.io.enq.ready - T_8378.io.nasti.r <- T_8523.io.deq - inst T_8535 of Queue_76 - T_8535.io.deq.ready <= UInt<1>("h00") - T_8535.io.enq.bits.user <= UInt<1>("h00") - T_8535.io.enq.bits.id <= UInt<1>("h00") - T_8535.io.enq.bits.resp <= UInt<1>("h00") - T_8535.io.enq.valid <= UInt<1>("h00") - T_8535.clk <= clk - T_8535.reset <= reset - T_8535.io.enq.valid <= interconnect.io.masters[0].b.valid - T_8535.io.enq.bits <- interconnect.io.masters[0].b.bits - interconnect.io.masters[0].b.ready <= T_8535.io.enq.ready - T_8378.io.nasti.b <- T_8535.io.deq + inst T_8069 of ClientTileLinkIOUnwrapper + T_8069.io is invalid + T_8069.clk <= clk + T_8069.reset <= reset + inst T_8070 of TileLinkIONarrower + T_8070.io is invalid + T_8070.clk <= clk + T_8070.reset <= reset + inst T_8071 of NastiIOTileLinkIOConverter + T_8071.io is invalid + T_8071.clk <= clk + T_8071.reset <= reset + inst T_8072 of ClientTileLinkIOWrapper_71 + T_8072.io is invalid + T_8072.clk <= clk + T_8072.reset <= reset + T_8072.io.in <- T_8067.io.outer + inst T_8073 of ClientTileLinkEnqueuer + T_8073.io is invalid + T_8073.clk <= clk + T_8073.reset <= reset + T_8073.io.inner <- T_8072.io.out + T_8069.io.in <- T_8073.io.outer + T_8070.io.in <- T_8069.io.out + T_8071.io.tl <- T_8070.io.out + inst T_8086 of Queue_36 + T_8086.io is invalid + T_8086.clk <= clk + T_8086.reset <= reset + T_8086.io.enq.valid <= T_8071.io.nasti.ar.valid + T_8086.io.enq.bits <- T_8071.io.nasti.ar.bits + T_8071.io.nasti.ar.ready <= T_8086.io.enq.ready + interconnect.io.masters[0].ar <- T_8086.io.deq + inst T_8099 of Queue_36 + T_8099.io is invalid + T_8099.clk <= clk + T_8099.reset <= reset + T_8099.io.enq.valid <= T_8071.io.nasti.aw.valid + T_8099.io.enq.bits <- T_8071.io.nasti.aw.bits + T_8071.io.nasti.aw.ready <= T_8099.io.enq.ready + interconnect.io.masters[0].aw <- T_8099.io.deq + inst T_8105 of Queue_74 + T_8105.io is invalid + T_8105.clk <= clk + T_8105.reset <= reset + T_8105.io.enq.valid <= T_8071.io.nasti.w.valid + T_8105.io.enq.bits <- T_8071.io.nasti.w.bits + T_8071.io.nasti.w.ready <= T_8105.io.enq.ready + interconnect.io.masters[0].w <- T_8105.io.deq + inst T_8112 of Queue_75 + T_8112.io is invalid + T_8112.clk <= clk + T_8112.reset <= reset + T_8112.io.enq.valid <= interconnect.io.masters[0].r.valid + T_8112.io.enq.bits <- interconnect.io.masters[0].r.bits + interconnect.io.masters[0].r.ready <= T_8112.io.enq.ready + T_8071.io.nasti.r <- T_8112.io.deq + inst T_8117 of Queue_76 + T_8117.io is invalid + T_8117.clk <= clk + T_8117.reset <= reset + T_8117.io.enq.valid <= interconnect.io.masters[0].b.valid + T_8117.io.enq.bits <- interconnect.io.masters[0].b.bits + interconnect.io.masters[0].b.ready <= T_8117.io.enq.ready + T_8071.io.nasti.b <- T_8117.io.deq inst rtc of RTC - rtc.io.r.bits.user <= UInt<1>("h00") - rtc.io.r.bits.id <= UInt<1>("h00") - rtc.io.r.bits.last <= UInt<1>("h00") - rtc.io.r.bits.data <= UInt<1>("h00") - rtc.io.r.bits.resp <= UInt<1>("h00") - rtc.io.r.valid <= UInt<1>("h00") - rtc.io.ar.ready <= UInt<1>("h00") - rtc.io.b.bits.user <= UInt<1>("h00") - rtc.io.b.bits.id <= UInt<1>("h00") - rtc.io.b.bits.resp <= UInt<1>("h00") - rtc.io.b.valid <= UInt<1>("h00") - rtc.io.w.ready <= UInt<1>("h00") - rtc.io.aw.ready <= UInt<1>("h00") + rtc.io is invalid rtc.clk <= clk rtc.reset <= reset interconnect.io.masters[1] <- rtc.io - inst T_8555 of SmiIONastiIOConverter - T_8555.io.smi.resp.bits <= UInt<1>("h00") - T_8555.io.smi.resp.valid <= UInt<1>("h00") - T_8555.io.smi.req.ready <= UInt<1>("h00") - T_8555.io.nasti.r.ready <= UInt<1>("h00") - T_8555.io.nasti.ar.bits.user <= UInt<1>("h00") - T_8555.io.nasti.ar.bits.id <= UInt<1>("h00") - T_8555.io.nasti.ar.bits.region <= UInt<1>("h00") - T_8555.io.nasti.ar.bits.qos <= UInt<1>("h00") - T_8555.io.nasti.ar.bits.prot <= UInt<1>("h00") - T_8555.io.nasti.ar.bits.cache <= UInt<1>("h00") - T_8555.io.nasti.ar.bits.lock <= UInt<1>("h00") - T_8555.io.nasti.ar.bits.burst <= UInt<1>("h00") - T_8555.io.nasti.ar.bits.size <= UInt<1>("h00") - T_8555.io.nasti.ar.bits.len <= UInt<1>("h00") - T_8555.io.nasti.ar.bits.addr <= UInt<1>("h00") - T_8555.io.nasti.ar.valid <= UInt<1>("h00") - T_8555.io.nasti.b.ready <= UInt<1>("h00") - T_8555.io.nasti.w.bits.user <= UInt<1>("h00") - T_8555.io.nasti.w.bits.strb <= UInt<1>("h00") - T_8555.io.nasti.w.bits.last <= UInt<1>("h00") - T_8555.io.nasti.w.bits.data <= UInt<1>("h00") - T_8555.io.nasti.w.valid <= UInt<1>("h00") - T_8555.io.nasti.aw.bits.user <= UInt<1>("h00") - T_8555.io.nasti.aw.bits.id <= UInt<1>("h00") - T_8555.io.nasti.aw.bits.region <= UInt<1>("h00") - T_8555.io.nasti.aw.bits.qos <= UInt<1>("h00") - T_8555.io.nasti.aw.bits.prot <= UInt<1>("h00") - T_8555.io.nasti.aw.bits.cache <= UInt<1>("h00") - T_8555.io.nasti.aw.bits.lock <= UInt<1>("h00") - T_8555.io.nasti.aw.bits.burst <= UInt<1>("h00") - T_8555.io.nasti.aw.bits.size <= UInt<1>("h00") - T_8555.io.nasti.aw.bits.len <= UInt<1>("h00") - T_8555.io.nasti.aw.bits.addr <= UInt<1>("h00") - T_8555.io.nasti.aw.valid <= UInt<1>("h00") - T_8555.clk <= clk - T_8555.reset <= reset - T_8555.io.nasti <- interconnect.io.slaves[2] - io.csr[0] <- T_8555.io.smi + inst T_8119 of SmiIONastiIOConverter + T_8119.io is invalid + T_8119.clk <= clk + T_8119.reset <= reset + T_8119.io.nasti <- interconnect.io.slaves[2] + io.csr[0] <- T_8119.io.smi inst src_conv of SmiIONastiIOConverter_78 - src_conv.io.smi.resp.bits <= UInt<1>("h00") - src_conv.io.smi.resp.valid <= UInt<1>("h00") - src_conv.io.smi.req.ready <= UInt<1>("h00") - src_conv.io.nasti.r.ready <= UInt<1>("h00") - src_conv.io.nasti.ar.bits.user <= UInt<1>("h00") - src_conv.io.nasti.ar.bits.id <= UInt<1>("h00") - src_conv.io.nasti.ar.bits.region <= UInt<1>("h00") - src_conv.io.nasti.ar.bits.qos <= UInt<1>("h00") - src_conv.io.nasti.ar.bits.prot <= UInt<1>("h00") - src_conv.io.nasti.ar.bits.cache <= UInt<1>("h00") - src_conv.io.nasti.ar.bits.lock <= UInt<1>("h00") - src_conv.io.nasti.ar.bits.burst <= UInt<1>("h00") - src_conv.io.nasti.ar.bits.size <= UInt<1>("h00") - src_conv.io.nasti.ar.bits.len <= UInt<1>("h00") - src_conv.io.nasti.ar.bits.addr <= UInt<1>("h00") - src_conv.io.nasti.ar.valid <= UInt<1>("h00") - src_conv.io.nasti.b.ready <= UInt<1>("h00") - src_conv.io.nasti.w.bits.user <= UInt<1>("h00") - src_conv.io.nasti.w.bits.strb <= UInt<1>("h00") - src_conv.io.nasti.w.bits.last <= UInt<1>("h00") - src_conv.io.nasti.w.bits.data <= UInt<1>("h00") - src_conv.io.nasti.w.valid <= UInt<1>("h00") - src_conv.io.nasti.aw.bits.user <= UInt<1>("h00") - src_conv.io.nasti.aw.bits.id <= UInt<1>("h00") - src_conv.io.nasti.aw.bits.region <= UInt<1>("h00") - src_conv.io.nasti.aw.bits.qos <= UInt<1>("h00") - src_conv.io.nasti.aw.bits.prot <= UInt<1>("h00") - src_conv.io.nasti.aw.bits.cache <= UInt<1>("h00") - src_conv.io.nasti.aw.bits.lock <= UInt<1>("h00") - src_conv.io.nasti.aw.bits.burst <= UInt<1>("h00") - src_conv.io.nasti.aw.bits.size <= UInt<1>("h00") - src_conv.io.nasti.aw.bits.len <= UInt<1>("h00") - src_conv.io.nasti.aw.bits.addr <= UInt<1>("h00") - src_conv.io.nasti.aw.valid <= UInt<1>("h00") + src_conv.io is invalid src_conv.clk <= clk src_conv.reset <= reset src_conv.io.nasti <- interconnect.io.slaves[3] io.scr <- src_conv.io.smi io.mmio <- interconnect.io.slaves[4] io.deviceTree <- interconnect.io.slaves[1] - inst T_8625 of NastiArbiter_83 - T_8625.io.slave.r.bits.user <= UInt<1>("h00") - T_8625.io.slave.r.bits.id <= UInt<1>("h00") - T_8625.io.slave.r.bits.last <= UInt<1>("h00") - T_8625.io.slave.r.bits.data <= UInt<1>("h00") - T_8625.io.slave.r.bits.resp <= UInt<1>("h00") - T_8625.io.slave.r.valid <= UInt<1>("h00") - T_8625.io.slave.ar.ready <= UInt<1>("h00") - T_8625.io.slave.b.bits.user <= UInt<1>("h00") - T_8625.io.slave.b.bits.id <= UInt<1>("h00") - T_8625.io.slave.b.bits.resp <= UInt<1>("h00") - T_8625.io.slave.b.valid <= UInt<1>("h00") - T_8625.io.slave.w.ready <= UInt<1>("h00") - T_8625.io.slave.aw.ready <= UInt<1>("h00") - T_8625.io.master[0].r.ready <= UInt<1>("h00") - T_8625.io.master[0].ar.bits.user <= UInt<1>("h00") - T_8625.io.master[0].ar.bits.id <= UInt<1>("h00") - T_8625.io.master[0].ar.bits.region <= UInt<1>("h00") - T_8625.io.master[0].ar.bits.qos <= UInt<1>("h00") - T_8625.io.master[0].ar.bits.prot <= UInt<1>("h00") - T_8625.io.master[0].ar.bits.cache <= UInt<1>("h00") - T_8625.io.master[0].ar.bits.lock <= UInt<1>("h00") - T_8625.io.master[0].ar.bits.burst <= UInt<1>("h00") - T_8625.io.master[0].ar.bits.size <= UInt<1>("h00") - T_8625.io.master[0].ar.bits.len <= UInt<1>("h00") - T_8625.io.master[0].ar.bits.addr <= UInt<1>("h00") - T_8625.io.master[0].ar.valid <= UInt<1>("h00") - T_8625.io.master[0].b.ready <= UInt<1>("h00") - T_8625.io.master[0].w.bits.user <= UInt<1>("h00") - T_8625.io.master[0].w.bits.strb <= UInt<1>("h00") - T_8625.io.master[0].w.bits.last <= UInt<1>("h00") - T_8625.io.master[0].w.bits.data <= UInt<1>("h00") - T_8625.io.master[0].w.valid <= UInt<1>("h00") - T_8625.io.master[0].aw.bits.user <= UInt<1>("h00") - T_8625.io.master[0].aw.bits.id <= UInt<1>("h00") - T_8625.io.master[0].aw.bits.region <= UInt<1>("h00") - T_8625.io.master[0].aw.bits.qos <= UInt<1>("h00") - T_8625.io.master[0].aw.bits.prot <= UInt<1>("h00") - T_8625.io.master[0].aw.bits.cache <= UInt<1>("h00") - T_8625.io.master[0].aw.bits.lock <= UInt<1>("h00") - T_8625.io.master[0].aw.bits.burst <= UInt<1>("h00") - T_8625.io.master[0].aw.bits.size <= UInt<1>("h00") - T_8625.io.master[0].aw.bits.len <= UInt<1>("h00") - T_8625.io.master[0].aw.bits.addr <= UInt<1>("h00") - T_8625.io.master[0].aw.valid <= UInt<1>("h00") - T_8625.clk <= clk - T_8625.reset <= reset - inst T_8670 of MemIONastiIOConverter - T_8670.io.mem.resp.bits.tag <= UInt<1>("h00") - T_8670.io.mem.resp.bits.data <= UInt<1>("h00") - T_8670.io.mem.resp.valid <= UInt<1>("h00") - T_8670.io.mem.req_data.ready <= UInt<1>("h00") - T_8670.io.mem.req_cmd.ready <= UInt<1>("h00") - T_8670.io.nasti.r.ready <= UInt<1>("h00") - T_8670.io.nasti.ar.bits.user <= UInt<1>("h00") - T_8670.io.nasti.ar.bits.id <= UInt<1>("h00") - T_8670.io.nasti.ar.bits.region <= UInt<1>("h00") - T_8670.io.nasti.ar.bits.qos <= UInt<1>("h00") - T_8670.io.nasti.ar.bits.prot <= UInt<1>("h00") - T_8670.io.nasti.ar.bits.cache <= UInt<1>("h00") - T_8670.io.nasti.ar.bits.lock <= UInt<1>("h00") - T_8670.io.nasti.ar.bits.burst <= UInt<1>("h00") - T_8670.io.nasti.ar.bits.size <= UInt<1>("h00") - T_8670.io.nasti.ar.bits.len <= UInt<1>("h00") - T_8670.io.nasti.ar.bits.addr <= UInt<1>("h00") - T_8670.io.nasti.ar.valid <= UInt<1>("h00") - T_8670.io.nasti.b.ready <= UInt<1>("h00") - T_8670.io.nasti.w.bits.user <= UInt<1>("h00") - T_8670.io.nasti.w.bits.strb <= UInt<1>("h00") - T_8670.io.nasti.w.bits.last <= UInt<1>("h00") - T_8670.io.nasti.w.bits.data <= UInt<1>("h00") - T_8670.io.nasti.w.valid <= UInt<1>("h00") - T_8670.io.nasti.aw.bits.user <= UInt<1>("h00") - T_8670.io.nasti.aw.bits.id <= UInt<1>("h00") - T_8670.io.nasti.aw.bits.region <= UInt<1>("h00") - T_8670.io.nasti.aw.bits.qos <= UInt<1>("h00") - T_8670.io.nasti.aw.bits.prot <= UInt<1>("h00") - T_8670.io.nasti.aw.bits.cache <= UInt<1>("h00") - T_8670.io.nasti.aw.bits.lock <= UInt<1>("h00") - T_8670.io.nasti.aw.bits.burst <= UInt<1>("h00") - T_8670.io.nasti.aw.bits.size <= UInt<1>("h00") - T_8670.io.nasti.aw.bits.len <= UInt<1>("h00") - T_8670.io.nasti.aw.bits.addr <= UInt<1>("h00") - T_8670.io.nasti.aw.valid <= UInt<1>("h00") - T_8670.clk <= clk - T_8670.reset <= reset - inst T_8707 of MemSerdes - T_8707.io.narrow.resp.bits <= UInt<1>("h00") - T_8707.io.narrow.resp.valid <= UInt<1>("h00") - T_8707.io.narrow.req.ready <= UInt<1>("h00") - T_8707.io.wide.resp.ready <= UInt<1>("h00") - T_8707.io.wide.req_data.bits.data <= UInt<1>("h00") - T_8707.io.wide.req_data.valid <= UInt<1>("h00") - T_8707.io.wide.req_cmd.bits.rw <= UInt<1>("h00") - T_8707.io.wide.req_cmd.bits.tag <= UInt<1>("h00") - T_8707.io.wide.req_cmd.bits.addr <= UInt<1>("h00") - T_8707.io.wide.req_cmd.valid <= UInt<1>("h00") - T_8707.clk <= clk - T_8707.reset <= reset - T_8670.io.nasti <- T_8625.io.slave - T_8707.io.wide <- T_8670.io.mem - io.mem_backup <- T_8707.io.narrow - node T_8718 = mux(io.mem_backup_en, T_8625.io.master[0].ar.ready, io.mem[0].ar.ready) - interconnect.io.slaves[0].ar.ready <= T_8718 - node T_8720 = eq(io.mem_backup_en, UInt<1>("h00")) - node T_8721 = and(interconnect.io.slaves[0].ar.valid, T_8720) - io.mem[0].ar.valid <= T_8721 + inst T_8121 of NastiArbiter_83 + T_8121.io is invalid + T_8121.clk <= clk + T_8121.reset <= reset + inst T_8122 of MemIONastiIOConverter + T_8122.io is invalid + T_8122.clk <= clk + T_8122.reset <= reset + inst T_8123 of MemSerdes + T_8123.io is invalid + T_8123.clk <= clk + T_8123.reset <= reset + T_8122.io.nasti <- T_8121.io.slave + T_8123.io.wide <- T_8122.io.mem + io.mem_backup <- T_8123.io.narrow + node T_8124 = mux(io.mem_backup_en, T_8121.io.master[0].ar.ready, io.mem[0].ar.ready) + interconnect.io.slaves[0].ar.ready <= T_8124 + node T_8126 = eq(io.mem_backup_en, UInt<1>("h00")) + node T_8127 = and(interconnect.io.slaves[0].ar.valid, T_8126) + io.mem[0].ar.valid <= T_8127 io.mem[0].ar.bits <- interconnect.io.slaves[0].ar.bits - node T_8722 = and(interconnect.io.slaves[0].ar.valid, io.mem_backup_en) - T_8625.io.master[0].ar.valid <= T_8722 - T_8625.io.master[0].ar.bits <- interconnect.io.slaves[0].ar.bits - node T_8723 = mux(io.mem_backup_en, T_8625.io.master[0].aw.ready, io.mem[0].aw.ready) - interconnect.io.slaves[0].aw.ready <= T_8723 - node T_8725 = eq(io.mem_backup_en, UInt<1>("h00")) - node T_8726 = and(interconnect.io.slaves[0].aw.valid, T_8725) - io.mem[0].aw.valid <= T_8726 + node T_8128 = and(interconnect.io.slaves[0].ar.valid, io.mem_backup_en) + T_8121.io.master[0].ar.valid <= T_8128 + T_8121.io.master[0].ar.bits <- interconnect.io.slaves[0].ar.bits + node T_8129 = mux(io.mem_backup_en, T_8121.io.master[0].aw.ready, io.mem[0].aw.ready) + interconnect.io.slaves[0].aw.ready <= T_8129 + node T_8131 = eq(io.mem_backup_en, UInt<1>("h00")) + node T_8132 = and(interconnect.io.slaves[0].aw.valid, T_8131) + io.mem[0].aw.valid <= T_8132 io.mem[0].aw.bits <- interconnect.io.slaves[0].aw.bits - node T_8727 = and(interconnect.io.slaves[0].aw.valid, io.mem_backup_en) - T_8625.io.master[0].aw.valid <= T_8727 - T_8625.io.master[0].aw.bits <- interconnect.io.slaves[0].aw.bits - node T_8728 = mux(io.mem_backup_en, T_8625.io.master[0].w.ready, io.mem[0].w.ready) - interconnect.io.slaves[0].w.ready <= T_8728 - node T_8730 = eq(io.mem_backup_en, UInt<1>("h00")) - node T_8731 = and(interconnect.io.slaves[0].w.valid, T_8730) - io.mem[0].w.valid <= T_8731 + node T_8133 = and(interconnect.io.slaves[0].aw.valid, io.mem_backup_en) + T_8121.io.master[0].aw.valid <= T_8133 + T_8121.io.master[0].aw.bits <- interconnect.io.slaves[0].aw.bits + node T_8134 = mux(io.mem_backup_en, T_8121.io.master[0].w.ready, io.mem[0].w.ready) + interconnect.io.slaves[0].w.ready <= T_8134 + node T_8136 = eq(io.mem_backup_en, UInt<1>("h00")) + node T_8137 = and(interconnect.io.slaves[0].w.valid, T_8136) + io.mem[0].w.valid <= T_8137 io.mem[0].w.bits <- interconnect.io.slaves[0].w.bits - node T_8732 = and(interconnect.io.slaves[0].w.valid, io.mem_backup_en) - T_8625.io.master[0].w.valid <= T_8732 - T_8625.io.master[0].w.bits <- interconnect.io.slaves[0].w.bits - node T_8733 = mux(io.mem_backup_en, T_8625.io.master[0].b.valid, io.mem[0].b.valid) - interconnect.io.slaves[0].b.valid <= T_8733 - wire T_8738 : {resp : UInt<2>, id : UInt<5>, user : UInt<1>} - T_8738 <- io.mem[0].b.bits - when io.mem_backup_en : - T_8738 <- T_8625.io.master[0].b.bits - skip - interconnect.io.slaves[0].b.bits <- T_8738 - node T_8743 = eq(io.mem_backup_en, UInt<1>("h00")) - node T_8744 = and(interconnect.io.slaves[0].b.ready, T_8743) - io.mem[0].b.ready <= T_8744 - node T_8745 = and(interconnect.io.slaves[0].b.ready, io.mem_backup_en) - T_8625.io.master[0].b.ready <= T_8745 - node T_8746 = mux(io.mem_backup_en, T_8625.io.master[0].r.valid, io.mem[0].r.valid) - interconnect.io.slaves[0].r.valid <= T_8746 - wire T_8753 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} - T_8753 <- io.mem[0].r.bits - when io.mem_backup_en : - T_8753 <- T_8625.io.master[0].r.bits - skip - interconnect.io.slaves[0].r.bits <- T_8753 - node T_8760 = eq(io.mem_backup_en, UInt<1>("h00")) - node T_8761 = and(interconnect.io.slaves[0].r.ready, T_8760) - io.mem[0].r.ready <= T_8761 - node T_8762 = and(interconnect.io.slaves[0].r.ready, io.mem_backup_en) - T_8625.io.master[0].r.ready <= T_8762 + node T_8138 = and(interconnect.io.slaves[0].w.valid, io.mem_backup_en) + T_8121.io.master[0].w.valid <= T_8138 + T_8121.io.master[0].w.bits <- interconnect.io.slaves[0].w.bits + node T_8139 = mux(io.mem_backup_en, T_8121.io.master[0].b.valid, io.mem[0].b.valid) + interconnect.io.slaves[0].b.valid <= T_8139 + node T_8140 = mux(io.mem_backup_en, T_8121.io.master[0].b.bits, io.mem[0].b.bits) + interconnect.io.slaves[0].b.bits <- T_8140 + node T_8145 = eq(io.mem_backup_en, UInt<1>("h00")) + node T_8146 = and(interconnect.io.slaves[0].b.ready, T_8145) + io.mem[0].b.ready <= T_8146 + node T_8147 = and(interconnect.io.slaves[0].b.ready, io.mem_backup_en) + T_8121.io.master[0].b.ready <= T_8147 + node T_8148 = mux(io.mem_backup_en, T_8121.io.master[0].r.valid, io.mem[0].r.valid) + interconnect.io.slaves[0].r.valid <= T_8148 + node T_8149 = mux(io.mem_backup_en, T_8121.io.master[0].r.bits, io.mem[0].r.bits) + interconnect.io.slaves[0].r.bits <- T_8149 + node T_8156 = eq(io.mem_backup_en, UInt<1>("h00")) + node T_8157 = and(interconnect.io.slaves[0].r.ready, T_8156) + io.mem[0].r.ready <= T_8157 + node T_8158 = and(interconnect.io.slaves[0].r.ready, io.mem_backup_en) + T_8121.io.master[0].r.ready <= T_8158 module SCRFile : input clk : Clock input reset : UInt<1> output io : {flip smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, scr : {flip rdata : UInt<64>[64], wen : UInt<1>, waddr : UInt<6>, wdata : UInt<64>}} - io.scr.wdata <= UInt<1>("h00") - io.scr.waddr <= UInt<1>("h00") - io.scr.wen <= UInt<1>("h00") - io.smi.resp.bits <= UInt<1>("h00") - io.smi.resp.valid <= UInt<1>("h00") - io.smi.req.ready <= UInt<1>("h00") + io is invalid wire scr_rdata : UInt<64>[64] - scr_rdata[0] <= UInt<1>("h00") - scr_rdata[1] <= UInt<1>("h00") - scr_rdata[2] <= UInt<1>("h00") - scr_rdata[3] <= UInt<1>("h00") - scr_rdata[4] <= UInt<1>("h00") - scr_rdata[5] <= UInt<1>("h00") - scr_rdata[6] <= UInt<1>("h00") - scr_rdata[7] <= UInt<1>("h00") - scr_rdata[8] <= UInt<1>("h00") - scr_rdata[9] <= UInt<1>("h00") - scr_rdata[10] <= UInt<1>("h00") - scr_rdata[11] <= UInt<1>("h00") - scr_rdata[12] <= UInt<1>("h00") - scr_rdata[13] <= UInt<1>("h00") - scr_rdata[14] <= UInt<1>("h00") - scr_rdata[15] <= UInt<1>("h00") - scr_rdata[16] <= UInt<1>("h00") - scr_rdata[17] <= UInt<1>("h00") - scr_rdata[18] <= UInt<1>("h00") - scr_rdata[19] <= UInt<1>("h00") - scr_rdata[20] <= UInt<1>("h00") - scr_rdata[21] <= UInt<1>("h00") - scr_rdata[22] <= UInt<1>("h00") - scr_rdata[23] <= UInt<1>("h00") - scr_rdata[24] <= UInt<1>("h00") - scr_rdata[25] <= UInt<1>("h00") - scr_rdata[26] <= UInt<1>("h00") - scr_rdata[27] <= UInt<1>("h00") - scr_rdata[28] <= UInt<1>("h00") - scr_rdata[29] <= UInt<1>("h00") - scr_rdata[30] <= UInt<1>("h00") - scr_rdata[31] <= UInt<1>("h00") - scr_rdata[32] <= UInt<1>("h00") - scr_rdata[33] <= UInt<1>("h00") - scr_rdata[34] <= UInt<1>("h00") - scr_rdata[35] <= UInt<1>("h00") - scr_rdata[36] <= UInt<1>("h00") - scr_rdata[37] <= UInt<1>("h00") - scr_rdata[38] <= UInt<1>("h00") - scr_rdata[39] <= UInt<1>("h00") - scr_rdata[40] <= UInt<1>("h00") - scr_rdata[41] <= UInt<1>("h00") - scr_rdata[42] <= UInt<1>("h00") - scr_rdata[43] <= UInt<1>("h00") - scr_rdata[44] <= UInt<1>("h00") - scr_rdata[45] <= UInt<1>("h00") - scr_rdata[46] <= UInt<1>("h00") - scr_rdata[47] <= UInt<1>("h00") - scr_rdata[48] <= UInt<1>("h00") - scr_rdata[49] <= UInt<1>("h00") - scr_rdata[50] <= UInt<1>("h00") - scr_rdata[51] <= UInt<1>("h00") - scr_rdata[52] <= UInt<1>("h00") - scr_rdata[53] <= UInt<1>("h00") - scr_rdata[54] <= UInt<1>("h00") - scr_rdata[55] <= UInt<1>("h00") - scr_rdata[56] <= UInt<1>("h00") - scr_rdata[57] <= UInt<1>("h00") - scr_rdata[58] <= UInt<1>("h00") - scr_rdata[59] <= UInt<1>("h00") - scr_rdata[60] <= UInt<1>("h00") - scr_rdata[61] <= UInt<1>("h00") - scr_rdata[62] <= UInt<1>("h00") - scr_rdata[63] <= UInt<1>("h00") + scr_rdata is invalid scr_rdata[0] <= io.scr.rdata[0] scr_rdata[1] <= io.scr.rdata[1] scr_rdata[2] <= io.scr.rdata[2] @@ -19604,24 +13869,24 @@ circuit Top : scr_rdata[63] <= io.scr.rdata[63] scr_rdata[0] <= UInt<1>("h01") scr_rdata[1] <= UInt<11>("h0400") - reg read_addr : UInt<6>, clk, reset, UInt<6>("h00") - reg resp_valid : UInt<1>, clk, reset, UInt<1>("h00") - node T_429 = eq(resp_valid, UInt<1>("h00")) - io.smi.req.ready <= T_429 + reg read_addr : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + reg resp_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_365 = eq(resp_valid, UInt<1>("h00")) + io.smi.req.ready <= T_365 io.smi.resp.valid <= resp_valid io.smi.resp.bits <= scr_rdata[read_addr] - node T_431 = and(io.smi.req.ready, io.smi.req.valid) - node T_432 = and(T_431, io.smi.req.bits.rw) - io.scr.wen <= T_432 + node T_367 = and(io.smi.req.ready, io.smi.req.valid) + node T_368 = and(T_367, io.smi.req.bits.rw) + io.scr.wen <= T_368 io.scr.wdata <= io.smi.req.bits.data io.scr.waddr <= io.smi.req.bits.addr - node T_433 = and(io.smi.req.ready, io.smi.req.valid) - when T_433 : + node T_369 = and(io.smi.req.ready, io.smi.req.valid) + when T_369 : read_addr <= io.smi.req.bits.addr resp_valid <= UInt<1>("h01") skip - node T_435 = and(io.smi.resp.ready, io.smi.resp.valid) - when T_435 : + node T_371 = and(io.smi.resp.ready, io.smi.resp.valid) + when T_371 : resp_valid <= UInt<1>("h00") skip @@ -19630,22 +13895,9 @@ circuit Top : input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, count : UInt<1>} - io.count <= UInt<1>("h00") - io.deq.bits.user <= UInt<1>("h00") - io.deq.bits.id <= UInt<1>("h00") - io.deq.bits.region <= UInt<1>("h00") - io.deq.bits.qos <= UInt<1>("h00") - io.deq.bits.prot <= UInt<1>("h00") - io.deq.bits.cache <= UInt<1>("h00") - io.deq.bits.lock <= UInt<1>("h00") - io.deq.bits.burst <= UInt<1>("h00") - io.deq.bits.size <= UInt<1>("h00") - io.deq.bits.len <= UInt<1>("h00") - io.deq.bits.addr <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}[1] - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) node T_130 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_130) @@ -19677,76 +13929,49 @@ circuit Top : node T_168 = or(T_165, T_167) io.enq.ready <= T_168 infer mport T_169 = ram[UInt<1>("h00")], clk - wire T_193 : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>} - T_193 <- T_169 - when maybe_flow : - T_193 <- io.enq.bits - skip - io.deq.bits <- T_193 - node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) - node T_206 = and(maybe_full, ptr_match) - node T_207 = cat(T_206, ptr_diff) - io.count <= T_207 + node T_181 = mux(maybe_flow, io.enq.bits, T_169) + io.deq.bits <- T_181 + node T_193 = sub(UInt<1>("h00"), UInt<1>("h00")) + node ptr_diff = tail(T_193, 1) + node T_195 = and(maybe_full, ptr_match) + node T_196 = cat(T_195, ptr_diff) + io.count <= T_196 module NastiROM : input clk : Clock input reset : UInt<1> input io : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}} - io.r.bits.user <= UInt<1>("h00") - io.r.bits.id <= UInt<1>("h00") - io.r.bits.last <= UInt<1>("h00") - io.r.bits.data <= UInt<1>("h00") - io.r.bits.resp <= UInt<1>("h00") - io.r.valid <= UInt<1>("h00") - io.ar.ready <= UInt<1>("h00") - io.b.bits.user <= UInt<1>("h00") - io.b.bits.id <= UInt<1>("h00") - io.b.bits.resp <= UInt<1>("h00") - io.b.valid <= UInt<1>("h00") - io.w.ready <= UInt<1>("h00") - io.aw.ready <= UInt<1>("h00") + io is invalid inst T_334 of Queue_89 - T_334.io.deq.ready <= UInt<1>("h00") - T_334.io.enq.bits.user <= UInt<1>("h00") - T_334.io.enq.bits.id <= UInt<1>("h00") - T_334.io.enq.bits.region <= UInt<1>("h00") - T_334.io.enq.bits.qos <= UInt<1>("h00") - T_334.io.enq.bits.prot <= UInt<1>("h00") - T_334.io.enq.bits.cache <= UInt<1>("h00") - T_334.io.enq.bits.lock <= UInt<1>("h00") - T_334.io.enq.bits.burst <= UInt<1>("h00") - T_334.io.enq.bits.size <= UInt<1>("h00") - T_334.io.enq.bits.len <= UInt<1>("h00") - T_334.io.enq.bits.addr <= UInt<1>("h00") - T_334.io.enq.valid <= UInt<1>("h00") + T_334.io is invalid T_334.clk <= clk T_334.reset <= reset T_334.io.enq.valid <= io.ar.valid T_334.io.enq.bits <- io.ar.bits io.ar.ready <= T_334.io.enq.ready when T_334.io.deq.valid : - node T_349 = eq(T_334.io.deq.bits.len, UInt<1>("h00")) - node T_351 = eq(reset, UInt<1>("h00")) - when T_351 : - node T_353 = eq(T_349, UInt<1>("h00")) - when T_353 : - node T_355 = eq(reset, UInt<1>("h00")) - when T_355 : + node T_336 = eq(T_334.io.deq.bits.len, UInt<1>("h00")) + node T_338 = eq(reset, UInt<1>("h00")) + when T_338 : + node T_340 = eq(T_336, UInt<1>("h00")) + when T_340 : + node T_342 = eq(reset, UInt<1>("h00")) + when T_342 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Can't burst-read from NastiROM") skip stop(clk, UInt<1>(1), 1) skip skip skip - node T_356 = or(io.aw.valid, io.w.valid) - node T_358 = eq(T_356, UInt<1>("h00")) - node T_360 = eq(reset, UInt<1>("h00")) - when T_360 : - node T_362 = eq(T_358, UInt<1>("h00")) - when T_362 : - node T_364 = eq(reset, UInt<1>("h00")) - when T_364 : + node T_343 = or(io.aw.valid, io.w.valid) + node T_345 = eq(T_343, UInt<1>("h00")) + node T_347 = eq(reset, UInt<1>("h00")) + when T_347 : + node T_349 = eq(T_345, UInt<1>("h00")) + when T_349 : + node T_351 = eq(reset, UInt<1>("h00")) + when T_351 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): Can't write to NastiROM") skip stop(clk, UInt<1>(1), 1) @@ -19823,78 +14048,74 @@ circuit Top : rom[64] <= UInt<63>("h069746365746f7270") rom[65] <= UInt<15>("h06e6f") rom[66] <= UInt<1>("h00") - node T_505 = bits(T_334.io.deq.bits.addr, 9, 3) - node T_508 = cat(UInt<1>("h01"), T_334.io.deq.bits.size) - node T_510 = bits(T_508, 1, 0) - node T_511 = asSInt(T_508) - node T_513 = geq(T_511, asSInt(UInt<1>("h00"))) - node T_514 = bit(T_334.io.deq.bits.addr, 2) - node T_515 = bits(rom[T_505], 63, 32) - node T_516 = bits(rom[T_505], 31, 0) - node T_517 = mux(T_514, T_515, T_516) - node T_519 = and(UInt<1>("h00"), UInt<1>("h00")) - node T_521 = mux(T_519, UInt<1>("h00"), T_517) - node T_523 = eq(T_510, UInt<2>("h02")) - node T_524 = or(T_523, T_519) - node T_525 = bit(T_521, 31) - node T_526 = and(T_513, T_525) - node T_528 = subw(UInt<32>("h00"), T_526) - node T_529 = bits(rom[T_505], 63, 32) - node T_530 = mux(T_524, T_528, T_529) - node T_531 = cat(T_530, T_521) - node T_532 = bit(T_334.io.deq.bits.addr, 1) - node T_533 = bits(T_531, 31, 16) - node T_534 = bits(T_531, 15, 0) - node T_535 = mux(T_532, T_533, T_534) - node T_537 = and(UInt<1>("h00"), UInt<1>("h00")) - node T_539 = mux(T_537, UInt<1>("h00"), T_535) - node T_541 = eq(T_510, UInt<1>("h01")) - node T_542 = or(T_541, T_537) - node T_543 = bit(T_539, 15) - node T_544 = and(T_513, T_543) - node T_546 = subw(UInt<48>("h00"), T_544) - node T_547 = bits(T_531, 63, 16) - node T_548 = mux(T_542, T_546, T_547) - node T_549 = cat(T_548, T_539) - node T_550 = bit(T_334.io.deq.bits.addr, 0) - node T_551 = bits(T_549, 15, 8) - node T_552 = bits(T_549, 7, 0) - node T_553 = mux(T_550, T_551, T_552) - node T_555 = and(UInt<1>("h01"), UInt<1>("h00")) - node T_557 = mux(T_555, UInt<1>("h00"), T_553) - node T_559 = eq(T_510, UInt<1>("h00")) - node T_560 = or(T_559, T_555) - node T_561 = bit(T_557, 7) - node T_562 = and(T_513, T_561) - node T_564 = subw(UInt<56>("h00"), T_562) - node T_565 = bits(T_549, 63, 8) - node T_566 = mux(T_560, T_564, T_565) - node rdata = cat(T_566, T_557) + node T_492 = bits(T_334.io.deq.bits.addr, 9, 3) + node T_495 = cat(UInt<1>("h01"), T_334.io.deq.bits.size) + node T_497 = bits(T_495, 1, 0) + node T_498 = asSInt(T_495) + node T_500 = geq(T_498, asSInt(UInt<1>("h00"))) + node T_501 = bits(T_334.io.deq.bits.addr, 2, 2) + node T_502 = bits(rom[T_492], 63, 32) + node T_503 = bits(rom[T_492], 31, 0) + node T_504 = mux(T_501, T_502, T_503) + node T_506 = and(UInt<1>("h00"), UInt<1>("h00")) + node T_508 = mux(T_506, UInt<1>("h00"), T_504) + node T_510 = eq(T_497, UInt<2>("h02")) + node T_511 = or(T_510, T_506) + node T_512 = bits(T_508, 31, 31) + node T_513 = and(T_500, T_512) + node T_515 = sub(UInt<32>("h00"), T_513) + node T_516 = tail(T_515, 1) + node T_517 = bits(rom[T_492], 63, 32) + node T_518 = mux(T_511, T_516, T_517) + node T_519 = cat(T_518, T_508) + node T_520 = bits(T_334.io.deq.bits.addr, 1, 1) + node T_521 = bits(T_519, 31, 16) + node T_522 = bits(T_519, 15, 0) + node T_523 = mux(T_520, T_521, T_522) + node T_525 = and(UInt<1>("h00"), UInt<1>("h00")) + node T_527 = mux(T_525, UInt<1>("h00"), T_523) + node T_529 = eq(T_497, UInt<1>("h01")) + node T_530 = or(T_529, T_525) + node T_531 = bits(T_527, 15, 15) + node T_532 = and(T_500, T_531) + node T_534 = sub(UInt<48>("h00"), T_532) + node T_535 = tail(T_534, 1) + node T_536 = bits(T_519, 63, 16) + node T_537 = mux(T_530, T_535, T_536) + node T_538 = cat(T_537, T_527) + node T_539 = bits(T_334.io.deq.bits.addr, 0, 0) + node T_540 = bits(T_538, 15, 8) + node T_541 = bits(T_538, 7, 0) + node T_542 = mux(T_539, T_540, T_541) + node T_544 = and(UInt<1>("h01"), UInt<1>("h00")) + node T_546 = mux(T_544, UInt<1>("h00"), T_542) + node T_548 = eq(T_497, UInt<1>("h00")) + node T_549 = or(T_548, T_544) + node T_550 = bits(T_546, 7, 7) + node T_551 = and(T_500, T_550) + node T_553 = sub(UInt<56>("h00"), T_551) + node T_554 = tail(T_553, 1) + node T_555 = bits(T_538, 63, 8) + node T_556 = mux(T_549, T_554, T_555) + node rdata = cat(T_556, T_546) io.r <- T_334.io.deq - wire T_576 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} - T_576.user <= UInt<1>("h00") - T_576.id <= UInt<1>("h00") - T_576.last <= UInt<1>("h00") - T_576.data <= UInt<1>("h00") - T_576.resp <= UInt<1>("h00") - T_576.id <= T_334.io.deq.bits.id - T_576.data <= rdata - T_576.last <= UInt<1>("h01") - T_576.resp <= UInt<1>("h00") - T_576.user <= UInt<1>("h00") - io.r.bits <- T_576 + wire T_566 : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>} + T_566 is invalid + T_566.id <= T_334.io.deq.bits.id + T_566.data <= rdata + T_566.last <= UInt<1>("h01") + T_566.resp <= UInt<1>("h00") + T_566.user <= UInt<1>("h00") + io.r.bits <- T_566 module Queue_90 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, count : UInt<1>} - io.count <= UInt<1>("h00") - io.deq.bits <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : UInt<17>[1] - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) node T_31 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_31) @@ -19928,28 +14149,22 @@ circuit Top : infer mport T_59 = ram[UInt<1>("h00")], clk node T_60 = mux(maybe_flow, io.enq.bits, T_59) io.deq.bits <= T_60 - node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) - node T_62 = and(maybe_full, ptr_match) - node T_63 = cat(T_62, ptr_diff) - io.count <= T_63 + node T_61 = sub(UInt<1>("h00"), UInt<1>("h00")) + node ptr_diff = tail(T_61, 1) + node T_63 = and(maybe_full, ptr_match) + node T_64 = cat(T_63, ptr_diff) + io.count <= T_64 module SlowIO : input clk : Clock input reset : UInt<1> output io : {flip out_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, out_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, in_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, flip in_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, clk_slow : UInt<1>, flip set_divisor : {valid : UInt<1>, bits : UInt<32>}, divisor : UInt<32>} - io.divisor <= UInt<1>("h00") - io.clk_slow <= UInt<1>("h00") - io.in_slow.ready <= UInt<1>("h00") - io.in_fast.bits <= UInt<1>("h00") - io.in_fast.valid <= UInt<1>("h00") - io.out_slow.bits <= UInt<1>("h00") - io.out_slow.valid <= UInt<1>("h00") - io.out_fast.ready <= UInt<1>("h00") - reg divisor : UInt<?>, clk, reset, UInt<9>("h01ff") - reg d_shadow : UInt<?>, clk, reset, UInt<9>("h01ff") - reg hold : UInt<?>, clk, reset, UInt<7>("h07f") - reg h_shadow : UInt<?>, clk, reset, UInt<7>("h07f") + io is invalid + reg divisor : UInt<?>, clk with : (reset => (reset, UInt<9>("h01ff"))) + reg d_shadow : UInt<?>, clk with : (reset => (reset, UInt<9>("h01ff"))) + reg hold : UInt<?>, clk with : (reset => (reset, UInt<7>("h07f"))) + reg h_shadow : UInt<?>, clk with : (reset => (reset, UInt<7>("h07f"))) when io.set_divisor.valid : node T_57 = bits(io.set_divisor.bits, 8, 0) d_shadow <= T_57 @@ -19959,16 +14174,18 @@ circuit Top : node T_59 = shl(hold, 16) node T_60 = or(T_59, divisor) io.divisor <= T_60 - reg count : UInt<9>, clk, UInt<1>("h00"), count - reg myclock : UInt<1>, clk, UInt<1>("h00"), myclock - node T_66 = addw(count, UInt<1>("h01")) - count <= T_66 - node T_67 = shr(divisor, 1) - node rising = eq(count, T_67) + reg count : UInt<9>, clk + reg myclock : UInt<1>, clk + node T_66 = add(count, UInt<1>("h01")) + node T_67 = tail(T_66, 1) + count <= T_67 + node T_68 = shr(divisor, 1) + node rising = eq(count, T_68) node falling = eq(count, divisor) - node T_70 = shr(divisor, 1) - node T_71 = addw(T_70, hold) - node held = eq(count, T_71) + node T_71 = shr(divisor, 1) + node T_72 = add(T_71, hold) + node T_73 = tail(T_72, 1) + node held = eq(count, T_73) when falling : divisor <= d_shadow hold <= h_shadow @@ -19978,36 +14195,32 @@ circuit Top : when rising : myclock <= UInt<1>("h01") skip - reg in_slow_rdy : UInt<1>, clk, reset, UInt<1>("h00") - reg out_slow_val : UInt<1>, clk, reset, UInt<1>("h00") - reg out_slow_bits : UInt<17>, clk, UInt<1>("h00"), out_slow_bits + reg in_slow_rdy : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg out_slow_val : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg out_slow_bits : UInt<17>, clk inst fromhost_q of Queue_90 - fromhost_q.io.deq.ready <= UInt<1>("h00") - fromhost_q.io.enq.bits <= UInt<1>("h00") - fromhost_q.io.enq.valid <= UInt<1>("h00") + fromhost_q.io is invalid fromhost_q.clk <= clk fromhost_q.reset <= reset - node T_87 = and(io.in_slow.valid, in_slow_rdy) - node T_88 = or(T_87, reset) - node T_89 = and(rising, T_88) - fromhost_q.io.enq.valid <= T_89 + node T_86 = and(io.in_slow.valid, in_slow_rdy) + node T_87 = or(T_86, reset) + node T_88 = and(rising, T_87) + fromhost_q.io.enq.valid <= T_88 fromhost_q.io.enq.bits <= io.in_slow.bits io.in_fast <- fromhost_q.io.deq inst tohost_q of Queue_90 - tohost_q.io.deq.ready <= UInt<1>("h00") - tohost_q.io.enq.bits <= UInt<1>("h00") - tohost_q.io.enq.valid <= UInt<1>("h00") + tohost_q.io is invalid tohost_q.clk <= clk tohost_q.reset <= reset tohost_q.io.enq <- io.out_fast - node T_95 = and(rising, io.out_slow.ready) - node T_96 = and(T_95, out_slow_val) - tohost_q.io.deq.ready <= T_96 + node T_91 = and(rising, io.out_slow.ready) + node T_92 = and(T_91, out_slow_val) + tohost_q.io.deq.ready <= T_92 when held : in_slow_rdy <= fromhost_q.io.enq.ready out_slow_val <= tohost_q.io.deq.valid - node T_97 = mux(reset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits) - out_slow_bits <= T_97 + node T_93 = mux(reset, fromhost_q.io.deq.bits, tohost_q.io.deq.bits) + out_slow_bits <= T_93 skip io.in_slow.ready <= in_slow_rdy io.out_slow.valid <= out_slow_val @@ -20019,607 +14232,114 @@ circuit Top : input reset : UInt<1> output io : {host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_csr : UInt<1>}, mem : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1], flip tiles_cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[1], flip tiles_uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[1], flip htif : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}[1], mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>}, mmio : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}, flip dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}[1]} - io.dma[0].resp.bits.status <= UInt<1>("h00") - io.dma[0].resp.bits.client_xact_id <= UInt<1>("h00") - io.dma[0].resp.valid <= UInt<1>("h00") - io.dma[0].req.ready <= UInt<1>("h00") - io.mmio.r.ready <= UInt<1>("h00") - io.mmio.ar.bits.user <= UInt<1>("h00") - io.mmio.ar.bits.id <= UInt<1>("h00") - io.mmio.ar.bits.region <= UInt<1>("h00") - io.mmio.ar.bits.qos <= UInt<1>("h00") - io.mmio.ar.bits.prot <= UInt<1>("h00") - io.mmio.ar.bits.cache <= UInt<1>("h00") - io.mmio.ar.bits.lock <= UInt<1>("h00") - io.mmio.ar.bits.burst <= UInt<1>("h00") - io.mmio.ar.bits.size <= UInt<1>("h00") - io.mmio.ar.bits.len <= UInt<1>("h00") - io.mmio.ar.bits.addr <= UInt<1>("h00") - io.mmio.ar.valid <= UInt<1>("h00") - io.mmio.b.ready <= UInt<1>("h00") - io.mmio.w.bits.user <= UInt<1>("h00") - io.mmio.w.bits.strb <= UInt<1>("h00") - io.mmio.w.bits.last <= UInt<1>("h00") - io.mmio.w.bits.data <= UInt<1>("h00") - io.mmio.w.valid <= UInt<1>("h00") - io.mmio.aw.bits.user <= UInt<1>("h00") - io.mmio.aw.bits.id <= UInt<1>("h00") - io.mmio.aw.bits.region <= UInt<1>("h00") - io.mmio.aw.bits.qos <= UInt<1>("h00") - io.mmio.aw.bits.prot <= UInt<1>("h00") - io.mmio.aw.bits.cache <= UInt<1>("h00") - io.mmio.aw.bits.lock <= UInt<1>("h00") - io.mmio.aw.bits.burst <= UInt<1>("h00") - io.mmio.aw.bits.size <= UInt<1>("h00") - io.mmio.aw.bits.len <= UInt<1>("h00") - io.mmio.aw.bits.addr <= UInt<1>("h00") - io.mmio.aw.valid <= UInt<1>("h00") - io.mem_backup_ctrl.out_valid <= UInt<1>("h00") - io.htif[0].csr.resp.ready <= UInt<1>("h00") - io.htif[0].csr.req.bits.data <= UInt<1>("h00") - io.htif[0].csr.req.bits.addr <= UInt<1>("h00") - io.htif[0].csr.req.bits.rw <= UInt<1>("h00") - io.htif[0].csr.req.valid <= UInt<1>("h00") - io.htif[0].id <= UInt<1>("h00") - io.htif[0].reset <= UInt<1>("h00") - io.tiles_uncached[0].grant.bits.data <= UInt<1>("h00") - io.tiles_uncached[0].grant.bits.g_type <= UInt<1>("h00") - io.tiles_uncached[0].grant.bits.is_builtin_type <= UInt<1>("h00") - io.tiles_uncached[0].grant.bits.manager_xact_id <= UInt<1>("h00") - io.tiles_uncached[0].grant.bits.client_xact_id <= UInt<1>("h00") - io.tiles_uncached[0].grant.bits.addr_beat <= UInt<1>("h00") - io.tiles_uncached[0].grant.valid <= UInt<1>("h00") - io.tiles_uncached[0].acquire.ready <= UInt<1>("h00") - io.tiles_cached[0].release.ready <= UInt<1>("h00") - io.tiles_cached[0].probe.bits.p_type <= UInt<1>("h00") - io.tiles_cached[0].probe.bits.addr_block <= UInt<1>("h00") - io.tiles_cached[0].probe.valid <= UInt<1>("h00") - io.tiles_cached[0].grant.bits.data <= UInt<1>("h00") - io.tiles_cached[0].grant.bits.g_type <= UInt<1>("h00") - io.tiles_cached[0].grant.bits.is_builtin_type <= UInt<1>("h00") - io.tiles_cached[0].grant.bits.manager_xact_id <= UInt<1>("h00") - io.tiles_cached[0].grant.bits.client_xact_id <= UInt<1>("h00") - io.tiles_cached[0].grant.bits.addr_beat <= UInt<1>("h00") - io.tiles_cached[0].grant.valid <= UInt<1>("h00") - io.tiles_cached[0].acquire.ready <= UInt<1>("h00") - io.mem[0].r.ready <= UInt<1>("h00") - io.mem[0].ar.bits.user <= UInt<1>("h00") - io.mem[0].ar.bits.id <= UInt<1>("h00") - io.mem[0].ar.bits.region <= UInt<1>("h00") - io.mem[0].ar.bits.qos <= UInt<1>("h00") - io.mem[0].ar.bits.prot <= UInt<1>("h00") - io.mem[0].ar.bits.cache <= UInt<1>("h00") - io.mem[0].ar.bits.lock <= UInt<1>("h00") - io.mem[0].ar.bits.burst <= UInt<1>("h00") - io.mem[0].ar.bits.size <= UInt<1>("h00") - io.mem[0].ar.bits.len <= UInt<1>("h00") - io.mem[0].ar.bits.addr <= UInt<1>("h00") - io.mem[0].ar.valid <= UInt<1>("h00") - io.mem[0].b.ready <= UInt<1>("h00") - io.mem[0].w.bits.user <= UInt<1>("h00") - io.mem[0].w.bits.strb <= UInt<1>("h00") - io.mem[0].w.bits.last <= UInt<1>("h00") - io.mem[0].w.bits.data <= UInt<1>("h00") - io.mem[0].w.valid <= UInt<1>("h00") - io.mem[0].aw.bits.user <= UInt<1>("h00") - io.mem[0].aw.bits.id <= UInt<1>("h00") - io.mem[0].aw.bits.region <= UInt<1>("h00") - io.mem[0].aw.bits.qos <= UInt<1>("h00") - io.mem[0].aw.bits.prot <= UInt<1>("h00") - io.mem[0].aw.bits.cache <= UInt<1>("h00") - io.mem[0].aw.bits.lock <= UInt<1>("h00") - io.mem[0].aw.bits.burst <= UInt<1>("h00") - io.mem[0].aw.bits.size <= UInt<1>("h00") - io.mem[0].aw.bits.len <= UInt<1>("h00") - io.mem[0].aw.bits.addr <= UInt<1>("h00") - io.mem[0].aw.valid <= UInt<1>("h00") - io.host.debug_stats_csr <= UInt<1>("h00") - io.host.out.bits <= UInt<1>("h00") - io.host.out.valid <= UInt<1>("h00") - io.host.in.ready <= UInt<1>("h00") - io.host.clk_edge <= UInt<1>("h00") - io.host.clk <= UInt<1>("h00") + io is invalid inst htif of Htif - htif.io.scr.resp.bits <= UInt<1>("h00") - htif.io.scr.resp.valid <= UInt<1>("h00") - htif.io.scr.req.ready <= UInt<1>("h00") - htif.io.mem.grant.bits.data <= UInt<1>("h00") - htif.io.mem.grant.bits.g_type <= UInt<1>("h00") - htif.io.mem.grant.bits.is_builtin_type <= UInt<1>("h00") - htif.io.mem.grant.bits.manager_xact_id <= UInt<1>("h00") - htif.io.mem.grant.bits.client_xact_id <= UInt<1>("h00") - htif.io.mem.grant.bits.addr_beat <= UInt<1>("h00") - htif.io.mem.grant.valid <= UInt<1>("h00") - htif.io.mem.acquire.ready <= UInt<1>("h00") - htif.io.cpu[0].debug_stats_csr <= UInt<1>("h00") - htif.io.cpu[0].csr.resp.bits <= UInt<1>("h00") - htif.io.cpu[0].csr.resp.valid <= UInt<1>("h00") - htif.io.cpu[0].csr.req.ready <= UInt<1>("h00") - htif.io.host.out.ready <= UInt<1>("h00") - htif.io.host.in.bits <= UInt<1>("h00") - htif.io.host.in.valid <= UInt<1>("h00") + htif.io is invalid htif.clk <= clk htif.reset <= reset inst outmemsys of OuterMemorySystem - outmemsys.io.dma.resp.ready <= UInt<1>("h00") - outmemsys.io.dma.req.bits.size <= UInt<1>("h00") - outmemsys.io.dma.req.bits.length <= UInt<1>("h00") - outmemsys.io.dma.req.bits.dest <= UInt<1>("h00") - outmemsys.io.dma.req.bits.source <= UInt<1>("h00") - outmemsys.io.dma.req.bits.cmd <= UInt<1>("h00") - outmemsys.io.dma.req.bits.client_xact_id <= UInt<1>("h00") - outmemsys.io.dma.req.valid <= UInt<1>("h00") - outmemsys.io.deviceTree.r.bits.user <= UInt<1>("h00") - outmemsys.io.deviceTree.r.bits.id <= UInt<1>("h00") - outmemsys.io.deviceTree.r.bits.last <= UInt<1>("h00") - outmemsys.io.deviceTree.r.bits.data <= UInt<1>("h00") - outmemsys.io.deviceTree.r.bits.resp <= UInt<1>("h00") - outmemsys.io.deviceTree.r.valid <= UInt<1>("h00") - outmemsys.io.deviceTree.ar.ready <= UInt<1>("h00") - outmemsys.io.deviceTree.b.bits.user <= UInt<1>("h00") - outmemsys.io.deviceTree.b.bits.id <= UInt<1>("h00") - outmemsys.io.deviceTree.b.bits.resp <= UInt<1>("h00") - outmemsys.io.deviceTree.b.valid <= UInt<1>("h00") - outmemsys.io.deviceTree.w.ready <= UInt<1>("h00") - outmemsys.io.deviceTree.aw.ready <= UInt<1>("h00") - outmemsys.io.mmio.r.bits.user <= UInt<1>("h00") - outmemsys.io.mmio.r.bits.id <= UInt<1>("h00") - outmemsys.io.mmio.r.bits.last <= UInt<1>("h00") - outmemsys.io.mmio.r.bits.data <= UInt<1>("h00") - outmemsys.io.mmio.r.bits.resp <= UInt<1>("h00") - outmemsys.io.mmio.r.valid <= UInt<1>("h00") - outmemsys.io.mmio.ar.ready <= UInt<1>("h00") - outmemsys.io.mmio.b.bits.user <= UInt<1>("h00") - outmemsys.io.mmio.b.bits.id <= UInt<1>("h00") - outmemsys.io.mmio.b.bits.resp <= UInt<1>("h00") - outmemsys.io.mmio.b.valid <= UInt<1>("h00") - outmemsys.io.mmio.w.ready <= UInt<1>("h00") - outmemsys.io.mmio.aw.ready <= UInt<1>("h00") - outmemsys.io.scr.resp.bits <= UInt<1>("h00") - outmemsys.io.scr.resp.valid <= UInt<1>("h00") - outmemsys.io.scr.req.ready <= UInt<1>("h00") - outmemsys.io.csr[0].resp.bits <= UInt<1>("h00") - outmemsys.io.csr[0].resp.valid <= UInt<1>("h00") - outmemsys.io.csr[0].req.ready <= UInt<1>("h00") - outmemsys.io.mem_backup_en <= UInt<1>("h00") - outmemsys.io.mem_backup.resp.bits <= UInt<1>("h00") - outmemsys.io.mem_backup.resp.valid <= UInt<1>("h00") - outmemsys.io.mem_backup.req.ready <= UInt<1>("h00") - outmemsys.io.mem[0].r.bits.user <= UInt<1>("h00") - outmemsys.io.mem[0].r.bits.id <= UInt<1>("h00") - outmemsys.io.mem[0].r.bits.last <= UInt<1>("h00") - outmemsys.io.mem[0].r.bits.data <= UInt<1>("h00") - outmemsys.io.mem[0].r.bits.resp <= UInt<1>("h00") - outmemsys.io.mem[0].r.valid <= UInt<1>("h00") - outmemsys.io.mem[0].ar.ready <= UInt<1>("h00") - outmemsys.io.mem[0].b.bits.user <= UInt<1>("h00") - outmemsys.io.mem[0].b.bits.id <= UInt<1>("h00") - outmemsys.io.mem[0].b.bits.resp <= UInt<1>("h00") - outmemsys.io.mem[0].b.valid <= UInt<1>("h00") - outmemsys.io.mem[0].w.ready <= UInt<1>("h00") - outmemsys.io.mem[0].aw.ready <= UInt<1>("h00") - outmemsys.io.incoherent[0] <= UInt<1>("h00") - outmemsys.io.htif_uncached.grant.ready <= UInt<1>("h00") - outmemsys.io.htif_uncached.acquire.bits.data <= UInt<1>("h00") - outmemsys.io.htif_uncached.acquire.bits.union <= UInt<1>("h00") - outmemsys.io.htif_uncached.acquire.bits.a_type <= UInt<1>("h00") - outmemsys.io.htif_uncached.acquire.bits.is_builtin_type <= UInt<1>("h00") - outmemsys.io.htif_uncached.acquire.bits.addr_beat <= UInt<1>("h00") - outmemsys.io.htif_uncached.acquire.bits.client_xact_id <= UInt<1>("h00") - outmemsys.io.htif_uncached.acquire.bits.addr_block <= UInt<1>("h00") - outmemsys.io.htif_uncached.acquire.valid <= UInt<1>("h00") - outmemsys.io.tiles_uncached[0].grant.ready <= UInt<1>("h00") - outmemsys.io.tiles_uncached[0].acquire.bits.data <= UInt<1>("h00") - outmemsys.io.tiles_uncached[0].acquire.bits.union <= UInt<1>("h00") - outmemsys.io.tiles_uncached[0].acquire.bits.a_type <= UInt<1>("h00") - outmemsys.io.tiles_uncached[0].acquire.bits.is_builtin_type <= UInt<1>("h00") - outmemsys.io.tiles_uncached[0].acquire.bits.addr_beat <= UInt<1>("h00") - outmemsys.io.tiles_uncached[0].acquire.bits.client_xact_id <= UInt<1>("h00") - outmemsys.io.tiles_uncached[0].acquire.bits.addr_block <= UInt<1>("h00") - outmemsys.io.tiles_uncached[0].acquire.valid <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].release.bits.data <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].release.bits.r_type <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].release.bits.voluntary <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].release.bits.client_xact_id <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].release.bits.addr_block <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].release.bits.addr_beat <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].release.valid <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].probe.ready <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].grant.ready <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].acquire.bits.data <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].acquire.bits.union <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].acquire.bits.a_type <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].acquire.bits.is_builtin_type <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].acquire.bits.addr_beat <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].acquire.bits.client_xact_id <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].acquire.bits.addr_block <= UInt<1>("h00") - outmemsys.io.tiles_cached[0].acquire.valid <= UInt<1>("h00") + outmemsys.io is invalid outmemsys.clk <= clk outmemsys.reset <= reset outmemsys.io.incoherent[0] <= htif.io.cpu[0].reset outmemsys.io.htif_uncached <- htif.io.mem - outmemsys.io.tiles_uncached <- io.tiles_uncached - outmemsys.io.tiles_cached <- io.tiles_cached + outmemsys.io.tiles_uncached <= io.tiles_uncached + outmemsys.io.tiles_cached <= io.tiles_cached io.htif[0].reset <= htif.io.cpu[0].reset io.htif[0].id <= htif.io.cpu[0].id htif.io.cpu[0].debug_stats_csr <= io.htif[0].debug_stats_csr - inst T_8473 of SmiArbiter - T_8473.io.out.resp.bits <= UInt<1>("h00") - T_8473.io.out.resp.valid <= UInt<1>("h00") - T_8473.io.out.req.ready <= UInt<1>("h00") - T_8473.io.in[0].resp.ready <= UInt<1>("h00") - T_8473.io.in[0].req.bits.data <= UInt<1>("h00") - T_8473.io.in[0].req.bits.addr <= UInt<1>("h00") - T_8473.io.in[0].req.bits.rw <= UInt<1>("h00") - T_8473.io.in[0].req.valid <= UInt<1>("h00") - T_8473.io.in[1].resp.ready <= UInt<1>("h00") - T_8473.io.in[1].req.bits.data <= UInt<1>("h00") - T_8473.io.in[1].req.bits.addr <= UInt<1>("h00") - T_8473.io.in[1].req.bits.rw <= UInt<1>("h00") - T_8473.io.in[1].req.valid <= UInt<1>("h00") - T_8473.clk <= clk - T_8473.reset <= reset - T_8473.io.in[0] <- htif.io.cpu[0].csr - T_8473.io.in[1] <- outmemsys.io.csr[0] - io.htif[0].csr <- T_8473.io.out + inst T_8362 of SmiArbiter + T_8362.io is invalid + T_8362.clk <= clk + T_8362.reset <= reset + T_8362.io.in[0] <- htif.io.cpu[0].csr + T_8362.io.in[1] <- outmemsys.io.csr[0] + io.htif[0].csr <- T_8362.io.out inst scrFile of SCRFile - scrFile.io.scr.rdata[0] <= UInt<1>("h00") - scrFile.io.scr.rdata[1] <= UInt<1>("h00") - scrFile.io.scr.rdata[2] <= UInt<1>("h00") - scrFile.io.scr.rdata[3] <= UInt<1>("h00") - scrFile.io.scr.rdata[4] <= UInt<1>("h00") - scrFile.io.scr.rdata[5] <= UInt<1>("h00") - scrFile.io.scr.rdata[6] <= UInt<1>("h00") - scrFile.io.scr.rdata[7] <= UInt<1>("h00") - scrFile.io.scr.rdata[8] <= UInt<1>("h00") - scrFile.io.scr.rdata[9] <= UInt<1>("h00") - scrFile.io.scr.rdata[10] <= UInt<1>("h00") - scrFile.io.scr.rdata[11] <= UInt<1>("h00") - scrFile.io.scr.rdata[12] <= UInt<1>("h00") - scrFile.io.scr.rdata[13] <= UInt<1>("h00") - scrFile.io.scr.rdata[14] <= UInt<1>("h00") - scrFile.io.scr.rdata[15] <= UInt<1>("h00") - scrFile.io.scr.rdata[16] <= UInt<1>("h00") - scrFile.io.scr.rdata[17] <= UInt<1>("h00") - scrFile.io.scr.rdata[18] <= UInt<1>("h00") - scrFile.io.scr.rdata[19] <= UInt<1>("h00") - scrFile.io.scr.rdata[20] <= UInt<1>("h00") - scrFile.io.scr.rdata[21] <= UInt<1>("h00") - scrFile.io.scr.rdata[22] <= UInt<1>("h00") - scrFile.io.scr.rdata[23] <= UInt<1>("h00") - scrFile.io.scr.rdata[24] <= UInt<1>("h00") - scrFile.io.scr.rdata[25] <= UInt<1>("h00") - scrFile.io.scr.rdata[26] <= UInt<1>("h00") - scrFile.io.scr.rdata[27] <= UInt<1>("h00") - scrFile.io.scr.rdata[28] <= UInt<1>("h00") - scrFile.io.scr.rdata[29] <= UInt<1>("h00") - scrFile.io.scr.rdata[30] <= UInt<1>("h00") - scrFile.io.scr.rdata[31] <= UInt<1>("h00") - scrFile.io.scr.rdata[32] <= UInt<1>("h00") - scrFile.io.scr.rdata[33] <= UInt<1>("h00") - scrFile.io.scr.rdata[34] <= UInt<1>("h00") - scrFile.io.scr.rdata[35] <= UInt<1>("h00") - scrFile.io.scr.rdata[36] <= UInt<1>("h00") - scrFile.io.scr.rdata[37] <= UInt<1>("h00") - scrFile.io.scr.rdata[38] <= UInt<1>("h00") - scrFile.io.scr.rdata[39] <= UInt<1>("h00") - scrFile.io.scr.rdata[40] <= UInt<1>("h00") - scrFile.io.scr.rdata[41] <= UInt<1>("h00") - scrFile.io.scr.rdata[42] <= UInt<1>("h00") - scrFile.io.scr.rdata[43] <= UInt<1>("h00") - scrFile.io.scr.rdata[44] <= UInt<1>("h00") - scrFile.io.scr.rdata[45] <= UInt<1>("h00") - scrFile.io.scr.rdata[46] <= UInt<1>("h00") - scrFile.io.scr.rdata[47] <= UInt<1>("h00") - scrFile.io.scr.rdata[48] <= UInt<1>("h00") - scrFile.io.scr.rdata[49] <= UInt<1>("h00") - scrFile.io.scr.rdata[50] <= UInt<1>("h00") - scrFile.io.scr.rdata[51] <= UInt<1>("h00") - scrFile.io.scr.rdata[52] <= UInt<1>("h00") - scrFile.io.scr.rdata[53] <= UInt<1>("h00") - scrFile.io.scr.rdata[54] <= UInt<1>("h00") - scrFile.io.scr.rdata[55] <= UInt<1>("h00") - scrFile.io.scr.rdata[56] <= UInt<1>("h00") - scrFile.io.scr.rdata[57] <= UInt<1>("h00") - scrFile.io.scr.rdata[58] <= UInt<1>("h00") - scrFile.io.scr.rdata[59] <= UInt<1>("h00") - scrFile.io.scr.rdata[60] <= UInt<1>("h00") - scrFile.io.scr.rdata[61] <= UInt<1>("h00") - scrFile.io.scr.rdata[62] <= UInt<1>("h00") - scrFile.io.scr.rdata[63] <= UInt<1>("h00") - scrFile.io.smi.resp.ready <= UInt<1>("h00") - scrFile.io.smi.req.bits.data <= UInt<1>("h00") - scrFile.io.smi.req.bits.addr <= UInt<1>("h00") - scrFile.io.smi.req.bits.rw <= UInt<1>("h00") - scrFile.io.smi.req.valid <= UInt<1>("h00") + scrFile.io is invalid scrFile.clk <= clk scrFile.reset <= reset inst scrArb of SmiArbiter_81 - scrArb.io.out.resp.bits <= UInt<1>("h00") - scrArb.io.out.resp.valid <= UInt<1>("h00") - scrArb.io.out.req.ready <= UInt<1>("h00") - scrArb.io.in[0].resp.ready <= UInt<1>("h00") - scrArb.io.in[0].req.bits.data <= UInt<1>("h00") - scrArb.io.in[0].req.bits.addr <= UInt<1>("h00") - scrArb.io.in[0].req.bits.rw <= UInt<1>("h00") - scrArb.io.in[0].req.valid <= UInt<1>("h00") - scrArb.io.in[1].resp.ready <= UInt<1>("h00") - scrArb.io.in[1].req.bits.data <= UInt<1>("h00") - scrArb.io.in[1].req.bits.addr <= UInt<1>("h00") - scrArb.io.in[1].req.bits.rw <= UInt<1>("h00") - scrArb.io.in[1].req.valid <= UInt<1>("h00") + scrArb.io is invalid scrArb.clk <= clk scrArb.reset <= reset scrArb.io.in[0] <- htif.io.scr scrArb.io.in[1] <- outmemsys.io.scr scrFile.io.smi <- scrArb.io.out inst deviceTree of NastiROM - deviceTree.io.r.ready <= UInt<1>("h00") - deviceTree.io.ar.bits.user <= UInt<1>("h00") - deviceTree.io.ar.bits.id <= UInt<1>("h00") - deviceTree.io.ar.bits.region <= UInt<1>("h00") - deviceTree.io.ar.bits.qos <= UInt<1>("h00") - deviceTree.io.ar.bits.prot <= UInt<1>("h00") - deviceTree.io.ar.bits.cache <= UInt<1>("h00") - deviceTree.io.ar.bits.lock <= UInt<1>("h00") - deviceTree.io.ar.bits.burst <= UInt<1>("h00") - deviceTree.io.ar.bits.size <= UInt<1>("h00") - deviceTree.io.ar.bits.len <= UInt<1>("h00") - deviceTree.io.ar.bits.addr <= UInt<1>("h00") - deviceTree.io.ar.valid <= UInt<1>("h00") - deviceTree.io.b.ready <= UInt<1>("h00") - deviceTree.io.w.bits.user <= UInt<1>("h00") - deviceTree.io.w.bits.strb <= UInt<1>("h00") - deviceTree.io.w.bits.last <= UInt<1>("h00") - deviceTree.io.w.bits.data <= UInt<1>("h00") - deviceTree.io.w.valid <= UInt<1>("h00") - deviceTree.io.aw.bits.user <= UInt<1>("h00") - deviceTree.io.aw.bits.id <= UInt<1>("h00") - deviceTree.io.aw.bits.region <= UInt<1>("h00") - deviceTree.io.aw.bits.qos <= UInt<1>("h00") - deviceTree.io.aw.bits.prot <= UInt<1>("h00") - deviceTree.io.aw.bits.cache <= UInt<1>("h00") - deviceTree.io.aw.bits.lock <= UInt<1>("h00") - deviceTree.io.aw.bits.burst <= UInt<1>("h00") - deviceTree.io.aw.bits.size <= UInt<1>("h00") - deviceTree.io.aw.bits.len <= UInt<1>("h00") - deviceTree.io.aw.bits.addr <= UInt<1>("h00") - deviceTree.io.aw.valid <= UInt<1>("h00") + deviceTree.io is invalid deviceTree.clk <= clk deviceTree.reset <= reset deviceTree.io <- outmemsys.io.deviceTree io.host.debug_stats_csr <= htif.io.host.debug_stats_csr - io.mem <- outmemsys.io.mem + io.mem <= outmemsys.io.mem io.mmio <- outmemsys.io.mmio outmemsys.io.mem_backup_en <= io.mem_backup_ctrl.en - inst T_8603 of SlowIO - T_8603.io.set_divisor.bits <= UInt<1>("h00") - T_8603.io.set_divisor.valid <= UInt<1>("h00") - T_8603.io.in_slow.bits <= UInt<1>("h00") - T_8603.io.in_slow.valid <= UInt<1>("h00") - T_8603.io.in_fast.ready <= UInt<1>("h00") - T_8603.io.out_slow.ready <= UInt<1>("h00") - T_8603.io.out_fast.bits <= UInt<1>("h00") - T_8603.io.out_fast.valid <= UInt<1>("h00") - T_8603.clk <= clk - T_8603.reset <= reset - node T_8613 = eq(scrFile.io.scr.waddr, UInt<6>("h03f")) - node T_8614 = and(scrFile.io.scr.wen, T_8613) - T_8603.io.set_divisor.valid <= T_8614 - T_8603.io.set_divisor.bits <= scrFile.io.scr.wdata - scrFile.io.scr.rdata[63] <= T_8603.io.divisor - node T_8615 = or(htif.io.host.out.valid, outmemsys.io.mem_backup.req.valid) - T_8603.io.out_fast.valid <= T_8615 - node T_8616 = mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits) - node T_8617 = cat(htif.io.host.out.valid, T_8616) - T_8603.io.out_fast.bits <= T_8617 - htif.io.host.out.ready <= T_8603.io.out_fast.ready - node T_8619 = eq(htif.io.host.out.valid, UInt<1>("h00")) - node T_8620 = and(T_8603.io.out_fast.ready, T_8619) - outmemsys.io.mem_backup.req.ready <= T_8620 - node T_8621 = bit(T_8603.io.out_slow.bits, 16) - node T_8622 = and(T_8603.io.out_slow.valid, T_8621) - io.host.out.valid <= T_8622 - io.host.out.bits <= T_8603.io.out_slow.bits - node T_8623 = bit(T_8603.io.out_slow.bits, 16) - node T_8625 = eq(T_8623, UInt<1>("h00")) - node T_8626 = and(T_8603.io.out_slow.valid, T_8625) - io.mem_backup_ctrl.out_valid <= T_8626 - node T_8627 = bit(T_8603.io.out_slow.bits, 16) - node T_8628 = mux(T_8627, io.host.out.ready, io.mem_backup_ctrl.out_ready) - T_8603.io.out_slow.ready <= T_8628 - node T_8629 = and(io.mem_backup_ctrl.en, io.mem_backup_ctrl.in_valid) - node T_8630 = or(T_8629, io.host.in.valid) - T_8603.io.in_slow.valid <= T_8630 - node T_8631 = cat(T_8629, io.host.in.bits) - T_8603.io.in_slow.bits <= T_8631 - io.host.in.ready <= T_8603.io.in_slow.ready - node T_8632 = bit(T_8603.io.in_fast.bits, 16) - node T_8633 = and(T_8603.io.in_fast.valid, T_8632) - outmemsys.io.mem_backup.resp.valid <= T_8633 - outmemsys.io.mem_backup.resp.bits <= T_8603.io.in_fast.bits - node T_8634 = bit(T_8603.io.in_fast.bits, 16) - node T_8636 = eq(T_8634, UInt<1>("h00")) - node T_8637 = and(T_8603.io.in_fast.valid, T_8636) - htif.io.host.in.valid <= T_8637 - htif.io.host.in.bits <= T_8603.io.in_fast.bits - node T_8638 = bit(T_8603.io.in_fast.bits, 16) - node T_8640 = mux(T_8638, UInt<1>("h01"), htif.io.host.in.ready) - T_8603.io.in_fast.ready <= T_8640 - io.host.clk <= T_8603.io.clk_slow - reg T_8641 : UInt<1>, clk, UInt<1>("h00"), T_8641 - T_8641 <= io.host.clk - node T_8643 = eq(T_8641, UInt<1>("h00")) - node T_8644 = and(io.host.clk, T_8643) - reg T_8645 : UInt<1>, clk, UInt<1>("h00"), T_8645 - T_8645 <= T_8644 - io.host.clk_edge <= T_8645 + inst T_8366 of SlowIO + T_8366.io is invalid + T_8366.clk <= clk + T_8366.reset <= reset + node T_8368 = eq(scrFile.io.scr.waddr, UInt<6>("h03f")) + node T_8369 = and(scrFile.io.scr.wen, T_8368) + T_8366.io.set_divisor.valid <= T_8369 + T_8366.io.set_divisor.bits <= scrFile.io.scr.wdata + scrFile.io.scr.rdata[63] <= T_8366.io.divisor + node T_8370 = or(htif.io.host.out.valid, outmemsys.io.mem_backup.req.valid) + T_8366.io.out_fast.valid <= T_8370 + node T_8371 = mux(htif.io.host.out.valid, htif.io.host.out.bits, outmemsys.io.mem_backup.req.bits) + node T_8372 = cat(htif.io.host.out.valid, T_8371) + T_8366.io.out_fast.bits <= T_8372 + htif.io.host.out.ready <= T_8366.io.out_fast.ready + node T_8374 = eq(htif.io.host.out.valid, UInt<1>("h00")) + node T_8375 = and(T_8366.io.out_fast.ready, T_8374) + outmemsys.io.mem_backup.req.ready <= T_8375 + node T_8376 = bits(T_8366.io.out_slow.bits, 16, 16) + node T_8377 = and(T_8366.io.out_slow.valid, T_8376) + io.host.out.valid <= T_8377 + io.host.out.bits <= T_8366.io.out_slow.bits + node T_8378 = bits(T_8366.io.out_slow.bits, 16, 16) + node T_8380 = eq(T_8378, UInt<1>("h00")) + node T_8381 = and(T_8366.io.out_slow.valid, T_8380) + io.mem_backup_ctrl.out_valid <= T_8381 + node T_8382 = bits(T_8366.io.out_slow.bits, 16, 16) + node T_8383 = mux(T_8382, io.host.out.ready, io.mem_backup_ctrl.out_ready) + T_8366.io.out_slow.ready <= T_8383 + node T_8384 = and(io.mem_backup_ctrl.en, io.mem_backup_ctrl.in_valid) + node T_8385 = or(T_8384, io.host.in.valid) + T_8366.io.in_slow.valid <= T_8385 + node T_8386 = cat(T_8384, io.host.in.bits) + T_8366.io.in_slow.bits <= T_8386 + io.host.in.ready <= T_8366.io.in_slow.ready + node T_8387 = bits(T_8366.io.in_fast.bits, 16, 16) + node T_8388 = and(T_8366.io.in_fast.valid, T_8387) + outmemsys.io.mem_backup.resp.valid <= T_8388 + outmemsys.io.mem_backup.resp.bits <= T_8366.io.in_fast.bits + node T_8389 = bits(T_8366.io.in_fast.bits, 16, 16) + node T_8391 = eq(T_8389, UInt<1>("h00")) + node T_8392 = and(T_8366.io.in_fast.valid, T_8391) + htif.io.host.in.valid <= T_8392 + htif.io.host.in.bits <= T_8366.io.in_fast.bits + node T_8393 = bits(T_8366.io.in_fast.bits, 16, 16) + node T_8395 = mux(T_8393, UInt<1>("h01"), htif.io.host.in.ready) + T_8366.io.in_fast.ready <= T_8395 + io.host.clk <= T_8366.io.clk_slow + reg T_8396 : UInt<1>, clk + T_8396 <= io.host.clk + node T_8398 = eq(T_8396, UInt<1>("h00")) + node T_8399 = and(io.host.clk, T_8398) + reg T_8400 : UInt<1>, clk + T_8400 <= T_8399 + io.host.clk_edge <= T_8400 module CSRFile : input clk : Clock input reset : UInt<1> output io : {host : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}, rw : {flip addr : UInt<12>, flip cmd : UInt<3>, rdata : UInt<64>, flip wdata : UInt<64>}, csr_stall : UInt<1>, csr_xcpt : UInt<1>, eret : UInt<1>, status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, ptbr : UInt<32>, evec : UInt<40>, flip exception : UInt<1>, flip retire : UInt<1>, flip uarch_counters : UInt<1>[16], flip custom_mrw_csrs : UInt<64>[0], flip cause : UInt<64>, flip pc : UInt<40>, fatc : UInt<1>, time : UInt<64>, fcsr_rm : UInt<3>, flip fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, autl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, utl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[0], iptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, fpu_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, flip fpu_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip exception : UInt<1>, dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}}, interrupt : UInt<1>, interrupt_cause : UInt<64>} - io.interrupt_cause <= UInt<1>("h00") - io.interrupt <= UInt<1>("h00") - io.rocc.dma.resp.bits.status <= UInt<1>("h00") - io.rocc.dma.resp.bits.client_xact_id <= UInt<1>("h00") - io.rocc.dma.resp.valid <= UInt<1>("h00") - io.rocc.dma.req.ready <= UInt<1>("h00") - io.rocc.exception <= UInt<1>("h00") - io.rocc.fpu_resp.bits.exc <= UInt<1>("h00") - io.rocc.fpu_resp.bits.data <= UInt<1>("h00") - io.rocc.fpu_resp.valid <= UInt<1>("h00") - io.rocc.fpu_req.ready <= UInt<1>("h00") - io.rocc.pptw.invalidate <= UInt<1>("h00") - io.rocc.pptw.status.ie <= UInt<1>("h00") - io.rocc.pptw.status.prv <= UInt<1>("h00") - io.rocc.pptw.status.ie1 <= UInt<1>("h00") - io.rocc.pptw.status.prv1 <= UInt<1>("h00") - io.rocc.pptw.status.ie2 <= UInt<1>("h00") - io.rocc.pptw.status.prv2 <= UInt<1>("h00") - io.rocc.pptw.status.ie3 <= UInt<1>("h00") - io.rocc.pptw.status.prv3 <= UInt<1>("h00") - io.rocc.pptw.status.fs <= UInt<1>("h00") - io.rocc.pptw.status.xs <= UInt<1>("h00") - io.rocc.pptw.status.mprv <= UInt<1>("h00") - io.rocc.pptw.status.vm <= UInt<1>("h00") - io.rocc.pptw.status.zero1 <= UInt<1>("h00") - io.rocc.pptw.status.sd_rv32 <= UInt<1>("h00") - io.rocc.pptw.status.zero2 <= UInt<1>("h00") - io.rocc.pptw.status.sd <= UInt<1>("h00") - io.rocc.pptw.resp.bits.pte.v <= UInt<1>("h00") - io.rocc.pptw.resp.bits.pte.typ <= UInt<1>("h00") - io.rocc.pptw.resp.bits.pte.r <= UInt<1>("h00") - io.rocc.pptw.resp.bits.pte.d <= UInt<1>("h00") - io.rocc.pptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") - io.rocc.pptw.resp.bits.pte.ppn <= UInt<1>("h00") - io.rocc.pptw.resp.bits.error <= UInt<1>("h00") - io.rocc.pptw.resp.valid <= UInt<1>("h00") - io.rocc.pptw.req.ready <= UInt<1>("h00") - io.rocc.dptw.invalidate <= UInt<1>("h00") - io.rocc.dptw.status.ie <= UInt<1>("h00") - io.rocc.dptw.status.prv <= UInt<1>("h00") - io.rocc.dptw.status.ie1 <= UInt<1>("h00") - io.rocc.dptw.status.prv1 <= UInt<1>("h00") - io.rocc.dptw.status.ie2 <= UInt<1>("h00") - io.rocc.dptw.status.prv2 <= UInt<1>("h00") - io.rocc.dptw.status.ie3 <= UInt<1>("h00") - io.rocc.dptw.status.prv3 <= UInt<1>("h00") - io.rocc.dptw.status.fs <= UInt<1>("h00") - io.rocc.dptw.status.xs <= UInt<1>("h00") - io.rocc.dptw.status.mprv <= UInt<1>("h00") - io.rocc.dptw.status.vm <= UInt<1>("h00") - io.rocc.dptw.status.zero1 <= UInt<1>("h00") - io.rocc.dptw.status.sd_rv32 <= UInt<1>("h00") - io.rocc.dptw.status.zero2 <= UInt<1>("h00") - io.rocc.dptw.status.sd <= UInt<1>("h00") - io.rocc.dptw.resp.bits.pte.v <= UInt<1>("h00") - io.rocc.dptw.resp.bits.pte.typ <= UInt<1>("h00") - io.rocc.dptw.resp.bits.pte.r <= UInt<1>("h00") - io.rocc.dptw.resp.bits.pte.d <= UInt<1>("h00") - io.rocc.dptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") - io.rocc.dptw.resp.bits.pte.ppn <= UInt<1>("h00") - io.rocc.dptw.resp.bits.error <= UInt<1>("h00") - io.rocc.dptw.resp.valid <= UInt<1>("h00") - io.rocc.dptw.req.ready <= UInt<1>("h00") - io.rocc.iptw.invalidate <= UInt<1>("h00") - io.rocc.iptw.status.ie <= UInt<1>("h00") - io.rocc.iptw.status.prv <= UInt<1>("h00") - io.rocc.iptw.status.ie1 <= UInt<1>("h00") - io.rocc.iptw.status.prv1 <= UInt<1>("h00") - io.rocc.iptw.status.ie2 <= UInt<1>("h00") - io.rocc.iptw.status.prv2 <= UInt<1>("h00") - io.rocc.iptw.status.ie3 <= UInt<1>("h00") - io.rocc.iptw.status.prv3 <= UInt<1>("h00") - io.rocc.iptw.status.fs <= UInt<1>("h00") - io.rocc.iptw.status.xs <= UInt<1>("h00") - io.rocc.iptw.status.mprv <= UInt<1>("h00") - io.rocc.iptw.status.vm <= UInt<1>("h00") - io.rocc.iptw.status.zero1 <= UInt<1>("h00") - io.rocc.iptw.status.sd_rv32 <= UInt<1>("h00") - io.rocc.iptw.status.zero2 <= UInt<1>("h00") - io.rocc.iptw.status.sd <= UInt<1>("h00") - io.rocc.iptw.resp.bits.pte.v <= UInt<1>("h00") - io.rocc.iptw.resp.bits.pte.typ <= UInt<1>("h00") - io.rocc.iptw.resp.bits.pte.r <= UInt<1>("h00") - io.rocc.iptw.resp.bits.pte.d <= UInt<1>("h00") - io.rocc.iptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") - io.rocc.iptw.resp.bits.pte.ppn <= UInt<1>("h00") - io.rocc.iptw.resp.bits.error <= UInt<1>("h00") - io.rocc.iptw.resp.valid <= UInt<1>("h00") - io.rocc.iptw.req.ready <= UInt<1>("h00") - io.rocc.autl.grant.bits.data <= UInt<1>("h00") - io.rocc.autl.grant.bits.g_type <= UInt<1>("h00") - io.rocc.autl.grant.bits.is_builtin_type <= UInt<1>("h00") - io.rocc.autl.grant.bits.manager_xact_id <= UInt<1>("h00") - io.rocc.autl.grant.bits.client_xact_id <= UInt<1>("h00") - io.rocc.autl.grant.bits.addr_beat <= UInt<1>("h00") - io.rocc.autl.grant.valid <= UInt<1>("h00") - io.rocc.autl.acquire.ready <= UInt<1>("h00") - io.rocc.s <= UInt<1>("h00") - io.rocc.mem.ordered <= UInt<1>("h00") - io.rocc.mem.xcpt.pf.st <= UInt<1>("h00") - io.rocc.mem.xcpt.pf.ld <= UInt<1>("h00") - io.rocc.mem.xcpt.ma.st <= UInt<1>("h00") - io.rocc.mem.xcpt.ma.ld <= UInt<1>("h00") - io.rocc.mem.replay_next.bits <= UInt<1>("h00") - io.rocc.mem.replay_next.valid <= UInt<1>("h00") - io.rocc.mem.resp.bits.store_data <= UInt<1>("h00") - io.rocc.mem.resp.bits.data_word_bypass <= UInt<1>("h00") - io.rocc.mem.resp.bits.has_data <= UInt<1>("h00") - io.rocc.mem.resp.bits.replay <= UInt<1>("h00") - io.rocc.mem.resp.bits.nack <= UInt<1>("h00") - io.rocc.mem.resp.bits.data <= UInt<1>("h00") - io.rocc.mem.resp.bits.typ <= UInt<1>("h00") - io.rocc.mem.resp.bits.cmd <= UInt<1>("h00") - io.rocc.mem.resp.bits.tag <= UInt<1>("h00") - io.rocc.mem.resp.bits.addr <= UInt<1>("h00") - io.rocc.mem.resp.valid <= UInt<1>("h00") - io.rocc.mem.req.ready <= UInt<1>("h00") - io.rocc.resp.ready <= UInt<1>("h00") - io.rocc.cmd.bits.rs2 <= UInt<1>("h00") - io.rocc.cmd.bits.rs1 <= UInt<1>("h00") - io.rocc.cmd.bits.inst.opcode <= UInt<1>("h00") - io.rocc.cmd.bits.inst.rd <= UInt<1>("h00") - io.rocc.cmd.bits.inst.xs2 <= UInt<1>("h00") - io.rocc.cmd.bits.inst.xs1 <= UInt<1>("h00") - io.rocc.cmd.bits.inst.xd <= UInt<1>("h00") - io.rocc.cmd.bits.inst.rs1 <= UInt<1>("h00") - io.rocc.cmd.bits.inst.rs2 <= UInt<1>("h00") - io.rocc.cmd.bits.inst.funct <= UInt<1>("h00") - io.rocc.cmd.valid <= UInt<1>("h00") - io.fcsr_rm <= UInt<1>("h00") - io.time <= UInt<1>("h00") - io.fatc <= UInt<1>("h00") - io.evec <= UInt<1>("h00") - io.ptbr <= UInt<1>("h00") - io.status.ie <= UInt<1>("h00") - io.status.prv <= UInt<1>("h00") - io.status.ie1 <= UInt<1>("h00") - io.status.prv1 <= UInt<1>("h00") - io.status.ie2 <= UInt<1>("h00") - io.status.prv2 <= UInt<1>("h00") - io.status.ie3 <= UInt<1>("h00") - io.status.prv3 <= UInt<1>("h00") - io.status.fs <= UInt<1>("h00") - io.status.xs <= UInt<1>("h00") - io.status.mprv <= UInt<1>("h00") - io.status.vm <= UInt<1>("h00") - io.status.zero1 <= UInt<1>("h00") - io.status.sd_rv32 <= UInt<1>("h00") - io.status.zero2 <= UInt<1>("h00") - io.status.sd <= UInt<1>("h00") - io.eret <= UInt<1>("h00") - io.csr_xcpt <= UInt<1>("h00") - io.csr_stall <= UInt<1>("h00") - io.rw.rdata <= UInt<1>("h00") - io.host.debug_stats_csr <= UInt<1>("h00") - io.host.csr.resp.bits <= UInt<1>("h00") - io.host.csr.resp.valid <= UInt<1>("h00") - io.host.csr.req.ready <= UInt<1>("h00") - reg reg_mstatus : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, clk, UInt<1>("h00"), reg_mstatus + io is invalid + reg reg_mstatus : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, clk wire T_4480 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_4480 is invalid T_4480.usip <= UInt<1>("h00") T_4480.ssip <= UInt<1>("h00") T_4480.hsip <= UInt<1>("h00") @@ -20628,427 +14348,448 @@ circuit Top : T_4480.stip <= UInt<1>("h00") T_4480.htip <= UInt<1>("h00") T_4480.mtip <= UInt<1>("h00") - T_4480.usip <= UInt<1>("h00") - T_4480.ssip <= UInt<1>("h00") - T_4480.hsip <= UInt<1>("h00") - T_4480.msip <= UInt<1>("h00") - T_4480.utip <= UInt<1>("h00") - T_4480.stip <= UInt<1>("h00") - T_4480.htip <= UInt<1>("h00") - T_4480.mtip <= UInt<1>("h00") - reg reg_mie : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clk, reset, T_4480 - wire T_4533 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_4533.usip <= UInt<1>("h00") - T_4533.ssip <= UInt<1>("h00") - T_4533.hsip <= UInt<1>("h00") - T_4533.msip <= UInt<1>("h00") - T_4533.utip <= UInt<1>("h00") - T_4533.stip <= UInt<1>("h00") - T_4533.htip <= UInt<1>("h00") - T_4533.mtip <= UInt<1>("h00") - T_4533.usip <= UInt<1>("h00") - T_4533.ssip <= UInt<1>("h00") - T_4533.hsip <= UInt<1>("h00") - T_4533.msip <= UInt<1>("h00") - T_4533.utip <= UInt<1>("h00") - T_4533.stip <= UInt<1>("h00") - T_4533.htip <= UInt<1>("h00") - T_4533.mtip <= UInt<1>("h00") - reg reg_mip : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clk, reset, T_4533 - reg reg_mepc : UInt<40>, clk, UInt<1>("h00"), reg_mepc - reg reg_mcause : UInt<64>, clk, UInt<1>("h00"), reg_mcause - reg reg_mbadaddr : UInt<40>, clk, UInt<1>("h00"), reg_mbadaddr - reg reg_mscratch : UInt<64>, clk, UInt<1>("h00"), reg_mscratch - reg reg_sepc : UInt<40>, clk, UInt<1>("h00"), reg_sepc - reg reg_scause : UInt<64>, clk, UInt<1>("h00"), reg_scause - reg reg_sbadaddr : UInt<40>, clk, UInt<1>("h00"), reg_sbadaddr - reg reg_sscratch : UInt<64>, clk, UInt<1>("h00"), reg_sscratch - reg reg_stvec : UInt<39>, clk, UInt<1>("h00"), reg_stvec - reg reg_mtimecmp : UInt<64>, clk, UInt<1>("h00"), reg_mtimecmp - reg reg_sptbr : UInt<32>, clk, UInt<1>("h00"), reg_sptbr - reg reg_wfi : UInt<1>, clk, reset, UInt<1>("h00") - reg reg_tohost : UInt<64>, clk, reset, UInt<64>("h00") - reg reg_fromhost : UInt<64>, clk, reset, UInt<64>("h00") - reg reg_stats : UInt<1>, clk, reset, UInt<1>("h00") - reg reg_time : UInt<64>, clk, UInt<1>("h00"), reg_time - reg T_4600 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4602 = neq(io.retire, UInt<1>("h00")) - node T_4604 = addw(T_4600, UInt<7>("h01")) - when T_4602 : - node T_4605 = bits(T_4604, 5, 0) - T_4600 <= T_4605 - skip - reg T_4607 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4608 = bit(T_4604, 6) - node T_4609 = and(T_4602, T_4608) - when T_4609 : - node T_4611 = addw(T_4607, UInt<1>("h01")) - T_4607 <= T_4611 - skip - node T_4612 = cat(T_4607, T_4600) - reg T_4615 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4617 = neq(UInt<1>("h01"), UInt<1>("h00")) - node T_4619 = addw(T_4615, UInt<7>("h01")) - when T_4617 : - node T_4620 = bits(T_4619, 5, 0) - T_4615 <= T_4620 - skip - reg T_4622 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4623 = bit(T_4619, 6) - node T_4624 = and(T_4617, T_4623) - when T_4624 : - node T_4626 = addw(T_4622, UInt<1>("h01")) - T_4622 <= T_4626 - skip - node T_4627 = cat(T_4622, T_4615) - reg T_4629 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4631 = neq(io.uarch_counters[0], UInt<1>("h00")) - node T_4633 = addw(T_4629, UInt<7>("h01")) - when T_4631 : - node T_4634 = bits(T_4633, 5, 0) - T_4629 <= T_4634 - skip - reg T_4636 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4637 = bit(T_4633, 6) - node T_4638 = and(T_4631, T_4637) - when T_4638 : - node T_4640 = addw(T_4636, UInt<1>("h01")) - T_4636 <= T_4640 - skip - node T_4641 = cat(T_4636, T_4629) - reg T_4643 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4645 = neq(io.uarch_counters[1], UInt<1>("h00")) - node T_4647 = addw(T_4643, UInt<7>("h01")) - when T_4645 : - node T_4648 = bits(T_4647, 5, 0) - T_4643 <= T_4648 - skip - reg T_4650 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4651 = bit(T_4647, 6) - node T_4652 = and(T_4645, T_4651) - when T_4652 : - node T_4654 = addw(T_4650, UInt<1>("h01")) - T_4650 <= T_4654 - skip - node T_4655 = cat(T_4650, T_4643) - reg T_4657 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4659 = neq(io.uarch_counters[2], UInt<1>("h00")) - node T_4661 = addw(T_4657, UInt<7>("h01")) + reg reg_mie : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clk with : (reset => (reset, T_4480)) + wire T_4525 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_4525 is invalid + T_4525.usip <= UInt<1>("h00") + T_4525.ssip <= UInt<1>("h00") + T_4525.hsip <= UInt<1>("h00") + T_4525.msip <= UInt<1>("h00") + T_4525.utip <= UInt<1>("h00") + T_4525.stip <= UInt<1>("h00") + T_4525.htip <= UInt<1>("h00") + T_4525.mtip <= UInt<1>("h00") + reg reg_mip : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>}, clk with : (reset => (reset, T_4525)) + reg reg_mepc : UInt<40>, clk + reg reg_mcause : UInt<64>, clk + reg reg_mbadaddr : UInt<40>, clk + reg reg_mscratch : UInt<64>, clk + reg reg_sepc : UInt<40>, clk + reg reg_scause : UInt<64>, clk + reg reg_sbadaddr : UInt<40>, clk + reg reg_sscratch : UInt<64>, clk + reg reg_stvec : UInt<39>, clk + reg reg_mtimecmp : UInt<64>, clk + reg reg_sptbr : UInt<32>, clk + reg reg_wfi : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg reg_tohost : UInt<64>, clk with : (reset => (reset, UInt<64>("h00"))) + reg reg_fromhost : UInt<64>, clk with : (reset => (reset, UInt<64>("h00"))) + reg reg_stats : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg reg_time : UInt<64>, clk + reg T_4584 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4586 = neq(io.retire, UInt<1>("h00")) + node T_4588 = add(T_4584, UInt<7>("h01")) + node T_4589 = tail(T_4588, 1) + when T_4586 : + node T_4590 = bits(T_4589, 5, 0) + T_4584 <= T_4590 + skip + reg T_4592 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4593 = bits(T_4589, 6, 6) + node T_4594 = and(T_4586, T_4593) + when T_4594 : + node T_4596 = add(T_4592, UInt<1>("h01")) + node T_4597 = tail(T_4596, 1) + T_4592 <= T_4597 + skip + node T_4598 = cat(T_4592, T_4584) + reg T_4601 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4603 = neq(UInt<1>("h01"), UInt<1>("h00")) + node T_4605 = add(T_4601, UInt<7>("h01")) + node T_4606 = tail(T_4605, 1) + when T_4603 : + node T_4607 = bits(T_4606, 5, 0) + T_4601 <= T_4607 + skip + reg T_4609 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4610 = bits(T_4606, 6, 6) + node T_4611 = and(T_4603, T_4610) + when T_4611 : + node T_4613 = add(T_4609, UInt<1>("h01")) + node T_4614 = tail(T_4613, 1) + T_4609 <= T_4614 + skip + node T_4615 = cat(T_4609, T_4601) + reg T_4617 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4619 = neq(io.uarch_counters[0], UInt<1>("h00")) + node T_4621 = add(T_4617, UInt<7>("h01")) + node T_4622 = tail(T_4621, 1) + when T_4619 : + node T_4623 = bits(T_4622, 5, 0) + T_4617 <= T_4623 + skip + reg T_4625 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4626 = bits(T_4622, 6, 6) + node T_4627 = and(T_4619, T_4626) + when T_4627 : + node T_4629 = add(T_4625, UInt<1>("h01")) + node T_4630 = tail(T_4629, 1) + T_4625 <= T_4630 + skip + node T_4631 = cat(T_4625, T_4617) + reg T_4633 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4635 = neq(io.uarch_counters[1], UInt<1>("h00")) + node T_4637 = add(T_4633, UInt<7>("h01")) + node T_4638 = tail(T_4637, 1) + when T_4635 : + node T_4639 = bits(T_4638, 5, 0) + T_4633 <= T_4639 + skip + reg T_4641 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4642 = bits(T_4638, 6, 6) + node T_4643 = and(T_4635, T_4642) + when T_4643 : + node T_4645 = add(T_4641, UInt<1>("h01")) + node T_4646 = tail(T_4645, 1) + T_4641 <= T_4646 + skip + node T_4647 = cat(T_4641, T_4633) + reg T_4649 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4651 = neq(io.uarch_counters[2], UInt<1>("h00")) + node T_4653 = add(T_4649, UInt<7>("h01")) + node T_4654 = tail(T_4653, 1) + when T_4651 : + node T_4655 = bits(T_4654, 5, 0) + T_4649 <= T_4655 + skip + reg T_4657 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4658 = bits(T_4654, 6, 6) + node T_4659 = and(T_4651, T_4658) when T_4659 : - node T_4662 = bits(T_4661, 5, 0) + node T_4661 = add(T_4657, UInt<1>("h01")) + node T_4662 = tail(T_4661, 1) T_4657 <= T_4662 skip - reg T_4664 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4665 = bit(T_4661, 6) - node T_4666 = and(T_4659, T_4665) - when T_4666 : - node T_4668 = addw(T_4664, UInt<1>("h01")) - T_4664 <= T_4668 - skip - node T_4669 = cat(T_4664, T_4657) - reg T_4671 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4673 = neq(io.uarch_counters[3], UInt<1>("h00")) - node T_4675 = addw(T_4671, UInt<7>("h01")) - when T_4673 : - node T_4676 = bits(T_4675, 5, 0) - T_4671 <= T_4676 - skip - reg T_4678 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4679 = bit(T_4675, 6) - node T_4680 = and(T_4673, T_4679) - when T_4680 : - node T_4682 = addw(T_4678, UInt<1>("h01")) - T_4678 <= T_4682 - skip - node T_4683 = cat(T_4678, T_4671) - reg T_4685 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4687 = neq(io.uarch_counters[4], UInt<1>("h00")) - node T_4689 = addw(T_4685, UInt<7>("h01")) - when T_4687 : - node T_4690 = bits(T_4689, 5, 0) - T_4685 <= T_4690 - skip - reg T_4692 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4693 = bit(T_4689, 6) - node T_4694 = and(T_4687, T_4693) - when T_4694 : - node T_4696 = addw(T_4692, UInt<1>("h01")) - T_4692 <= T_4696 - skip - node T_4697 = cat(T_4692, T_4685) - reg T_4699 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4701 = neq(io.uarch_counters[5], UInt<1>("h00")) - node T_4703 = addw(T_4699, UInt<7>("h01")) - when T_4701 : - node T_4704 = bits(T_4703, 5, 0) - T_4699 <= T_4704 - skip - reg T_4706 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4707 = bit(T_4703, 6) - node T_4708 = and(T_4701, T_4707) - when T_4708 : - node T_4710 = addw(T_4706, UInt<1>("h01")) - T_4706 <= T_4710 - skip - node T_4711 = cat(T_4706, T_4699) - reg T_4713 : UInt<6>, clk, reset, UInt<6>("h00") + node T_4663 = cat(T_4657, T_4649) + reg T_4665 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4667 = neq(io.uarch_counters[3], UInt<1>("h00")) + node T_4669 = add(T_4665, UInt<7>("h01")) + node T_4670 = tail(T_4669, 1) + when T_4667 : + node T_4671 = bits(T_4670, 5, 0) + T_4665 <= T_4671 + skip + reg T_4673 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4674 = bits(T_4670, 6, 6) + node T_4675 = and(T_4667, T_4674) + when T_4675 : + node T_4677 = add(T_4673, UInt<1>("h01")) + node T_4678 = tail(T_4677, 1) + T_4673 <= T_4678 + skip + node T_4679 = cat(T_4673, T_4665) + reg T_4681 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4683 = neq(io.uarch_counters[4], UInt<1>("h00")) + node T_4685 = add(T_4681, UInt<7>("h01")) + node T_4686 = tail(T_4685, 1) + when T_4683 : + node T_4687 = bits(T_4686, 5, 0) + T_4681 <= T_4687 + skip + reg T_4689 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4690 = bits(T_4686, 6, 6) + node T_4691 = and(T_4683, T_4690) + when T_4691 : + node T_4693 = add(T_4689, UInt<1>("h01")) + node T_4694 = tail(T_4693, 1) + T_4689 <= T_4694 + skip + node T_4695 = cat(T_4689, T_4681) + reg T_4697 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4699 = neq(io.uarch_counters[5], UInt<1>("h00")) + node T_4701 = add(T_4697, UInt<7>("h01")) + node T_4702 = tail(T_4701, 1) + when T_4699 : + node T_4703 = bits(T_4702, 5, 0) + T_4697 <= T_4703 + skip + reg T_4705 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4706 = bits(T_4702, 6, 6) + node T_4707 = and(T_4699, T_4706) + when T_4707 : + node T_4709 = add(T_4705, UInt<1>("h01")) + node T_4710 = tail(T_4709, 1) + T_4705 <= T_4710 + skip + node T_4711 = cat(T_4705, T_4697) + reg T_4713 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) node T_4715 = neq(io.uarch_counters[6], UInt<1>("h00")) - node T_4717 = addw(T_4713, UInt<7>("h01")) + node T_4717 = add(T_4713, UInt<7>("h01")) + node T_4718 = tail(T_4717, 1) when T_4715 : - node T_4718 = bits(T_4717, 5, 0) - T_4713 <= T_4718 - skip - reg T_4720 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4721 = bit(T_4717, 6) - node T_4722 = and(T_4715, T_4721) - when T_4722 : - node T_4724 = addw(T_4720, UInt<1>("h01")) - T_4720 <= T_4724 - skip - node T_4725 = cat(T_4720, T_4713) - reg T_4727 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4729 = neq(io.uarch_counters[7], UInt<1>("h00")) - node T_4731 = addw(T_4727, UInt<7>("h01")) - when T_4729 : - node T_4732 = bits(T_4731, 5, 0) - T_4727 <= T_4732 - skip - reg T_4734 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4735 = bit(T_4731, 6) - node T_4736 = and(T_4729, T_4735) - when T_4736 : - node T_4738 = addw(T_4734, UInt<1>("h01")) - T_4734 <= T_4738 - skip - node T_4739 = cat(T_4734, T_4727) - reg T_4741 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4743 = neq(io.uarch_counters[8], UInt<1>("h00")) - node T_4745 = addw(T_4741, UInt<7>("h01")) - when T_4743 : - node T_4746 = bits(T_4745, 5, 0) - T_4741 <= T_4746 - skip - reg T_4748 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4749 = bit(T_4745, 6) - node T_4750 = and(T_4743, T_4749) - when T_4750 : - node T_4752 = addw(T_4748, UInt<1>("h01")) - T_4748 <= T_4752 - skip - node T_4753 = cat(T_4748, T_4741) - reg T_4755 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4757 = neq(io.uarch_counters[9], UInt<1>("h00")) - node T_4759 = addw(T_4755, UInt<7>("h01")) - when T_4757 : - node T_4760 = bits(T_4759, 5, 0) - T_4755 <= T_4760 - skip - reg T_4762 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4763 = bit(T_4759, 6) - node T_4764 = and(T_4757, T_4763) - when T_4764 : - node T_4766 = addw(T_4762, UInt<1>("h01")) - T_4762 <= T_4766 - skip - node T_4767 = cat(T_4762, T_4755) - reg T_4769 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4771 = neq(io.uarch_counters[10], UInt<1>("h00")) - node T_4773 = addw(T_4769, UInt<7>("h01")) + node T_4719 = bits(T_4718, 5, 0) + T_4713 <= T_4719 + skip + reg T_4721 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4722 = bits(T_4718, 6, 6) + node T_4723 = and(T_4715, T_4722) + when T_4723 : + node T_4725 = add(T_4721, UInt<1>("h01")) + node T_4726 = tail(T_4725, 1) + T_4721 <= T_4726 + skip + node T_4727 = cat(T_4721, T_4713) + reg T_4729 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4731 = neq(io.uarch_counters[7], UInt<1>("h00")) + node T_4733 = add(T_4729, UInt<7>("h01")) + node T_4734 = tail(T_4733, 1) + when T_4731 : + node T_4735 = bits(T_4734, 5, 0) + T_4729 <= T_4735 + skip + reg T_4737 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4738 = bits(T_4734, 6, 6) + node T_4739 = and(T_4731, T_4738) + when T_4739 : + node T_4741 = add(T_4737, UInt<1>("h01")) + node T_4742 = tail(T_4741, 1) + T_4737 <= T_4742 + skip + node T_4743 = cat(T_4737, T_4729) + reg T_4745 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4747 = neq(io.uarch_counters[8], UInt<1>("h00")) + node T_4749 = add(T_4745, UInt<7>("h01")) + node T_4750 = tail(T_4749, 1) + when T_4747 : + node T_4751 = bits(T_4750, 5, 0) + T_4745 <= T_4751 + skip + reg T_4753 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4754 = bits(T_4750, 6, 6) + node T_4755 = and(T_4747, T_4754) + when T_4755 : + node T_4757 = add(T_4753, UInt<1>("h01")) + node T_4758 = tail(T_4757, 1) + T_4753 <= T_4758 + skip + node T_4759 = cat(T_4753, T_4745) + reg T_4761 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4763 = neq(io.uarch_counters[9], UInt<1>("h00")) + node T_4765 = add(T_4761, UInt<7>("h01")) + node T_4766 = tail(T_4765, 1) + when T_4763 : + node T_4767 = bits(T_4766, 5, 0) + T_4761 <= T_4767 + skip + reg T_4769 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4770 = bits(T_4766, 6, 6) + node T_4771 = and(T_4763, T_4770) when T_4771 : - node T_4774 = bits(T_4773, 5, 0) + node T_4773 = add(T_4769, UInt<1>("h01")) + node T_4774 = tail(T_4773, 1) T_4769 <= T_4774 skip - reg T_4776 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4777 = bit(T_4773, 6) - node T_4778 = and(T_4771, T_4777) - when T_4778 : - node T_4780 = addw(T_4776, UInt<1>("h01")) - T_4776 <= T_4780 - skip - node T_4781 = cat(T_4776, T_4769) - reg T_4783 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4785 = neq(io.uarch_counters[11], UInt<1>("h00")) - node T_4787 = addw(T_4783, UInt<7>("h01")) - when T_4785 : - node T_4788 = bits(T_4787, 5, 0) - T_4783 <= T_4788 - skip - reg T_4790 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4791 = bit(T_4787, 6) - node T_4792 = and(T_4785, T_4791) - when T_4792 : - node T_4794 = addw(T_4790, UInt<1>("h01")) - T_4790 <= T_4794 - skip - node T_4795 = cat(T_4790, T_4783) - reg T_4797 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4799 = neq(io.uarch_counters[12], UInt<1>("h00")) - node T_4801 = addw(T_4797, UInt<7>("h01")) - when T_4799 : - node T_4802 = bits(T_4801, 5, 0) - T_4797 <= T_4802 - skip - reg T_4804 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4805 = bit(T_4801, 6) - node T_4806 = and(T_4799, T_4805) - when T_4806 : - node T_4808 = addw(T_4804, UInt<1>("h01")) - T_4804 <= T_4808 - skip - node T_4809 = cat(T_4804, T_4797) - reg T_4811 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4813 = neq(io.uarch_counters[13], UInt<1>("h00")) - node T_4815 = addw(T_4811, UInt<7>("h01")) - when T_4813 : - node T_4816 = bits(T_4815, 5, 0) - T_4811 <= T_4816 - skip - reg T_4818 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4819 = bit(T_4815, 6) - node T_4820 = and(T_4813, T_4819) - when T_4820 : - node T_4822 = addw(T_4818, UInt<1>("h01")) - T_4818 <= T_4822 - skip - node T_4823 = cat(T_4818, T_4811) - reg T_4825 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4827 = neq(io.uarch_counters[14], UInt<1>("h00")) - node T_4829 = addw(T_4825, UInt<7>("h01")) + node T_4775 = cat(T_4769, T_4761) + reg T_4777 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4779 = neq(io.uarch_counters[10], UInt<1>("h00")) + node T_4781 = add(T_4777, UInt<7>("h01")) + node T_4782 = tail(T_4781, 1) + when T_4779 : + node T_4783 = bits(T_4782, 5, 0) + T_4777 <= T_4783 + skip + reg T_4785 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4786 = bits(T_4782, 6, 6) + node T_4787 = and(T_4779, T_4786) + when T_4787 : + node T_4789 = add(T_4785, UInt<1>("h01")) + node T_4790 = tail(T_4789, 1) + T_4785 <= T_4790 + skip + node T_4791 = cat(T_4785, T_4777) + reg T_4793 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4795 = neq(io.uarch_counters[11], UInt<1>("h00")) + node T_4797 = add(T_4793, UInt<7>("h01")) + node T_4798 = tail(T_4797, 1) + when T_4795 : + node T_4799 = bits(T_4798, 5, 0) + T_4793 <= T_4799 + skip + reg T_4801 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4802 = bits(T_4798, 6, 6) + node T_4803 = and(T_4795, T_4802) + when T_4803 : + node T_4805 = add(T_4801, UInt<1>("h01")) + node T_4806 = tail(T_4805, 1) + T_4801 <= T_4806 + skip + node T_4807 = cat(T_4801, T_4793) + reg T_4809 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4811 = neq(io.uarch_counters[12], UInt<1>("h00")) + node T_4813 = add(T_4809, UInt<7>("h01")) + node T_4814 = tail(T_4813, 1) + when T_4811 : + node T_4815 = bits(T_4814, 5, 0) + T_4809 <= T_4815 + skip + reg T_4817 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4818 = bits(T_4814, 6, 6) + node T_4819 = and(T_4811, T_4818) + when T_4819 : + node T_4821 = add(T_4817, UInt<1>("h01")) + node T_4822 = tail(T_4821, 1) + T_4817 <= T_4822 + skip + node T_4823 = cat(T_4817, T_4809) + reg T_4825 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4827 = neq(io.uarch_counters[13], UInt<1>("h00")) + node T_4829 = add(T_4825, UInt<7>("h01")) + node T_4830 = tail(T_4829, 1) when T_4827 : - node T_4830 = bits(T_4829, 5, 0) - T_4825 <= T_4830 - skip - reg T_4832 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4833 = bit(T_4829, 6) - node T_4834 = and(T_4827, T_4833) - when T_4834 : - node T_4836 = addw(T_4832, UInt<1>("h01")) - T_4832 <= T_4836 - skip - node T_4837 = cat(T_4832, T_4825) - reg T_4839 : UInt<6>, clk, reset, UInt<6>("h00") - node T_4841 = neq(io.uarch_counters[15], UInt<1>("h00")) - node T_4843 = addw(T_4839, UInt<7>("h01")) - when T_4841 : - node T_4844 = bits(T_4843, 5, 0) - T_4839 <= T_4844 - skip - reg T_4846 : UInt<58>, clk, reset, UInt<58>("h00") - node T_4847 = bit(T_4843, 6) - node T_4848 = and(T_4841, T_4847) - when T_4848 : - node T_4850 = addw(T_4846, UInt<1>("h01")) - T_4846 <= T_4850 - skip - node T_4851 = cat(T_4846, T_4839) - reg reg_fflags : UInt<5>, clk, UInt<1>("h00"), reg_fflags - reg reg_frm : UInt<3>, clk, UInt<1>("h00"), reg_frm + node T_4831 = bits(T_4830, 5, 0) + T_4825 <= T_4831 + skip + reg T_4833 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4834 = bits(T_4830, 6, 6) + node T_4835 = and(T_4827, T_4834) + when T_4835 : + node T_4837 = add(T_4833, UInt<1>("h01")) + node T_4838 = tail(T_4837, 1) + T_4833 <= T_4838 + skip + node T_4839 = cat(T_4833, T_4825) + reg T_4841 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4843 = neq(io.uarch_counters[14], UInt<1>("h00")) + node T_4845 = add(T_4841, UInt<7>("h01")) + node T_4846 = tail(T_4845, 1) + when T_4843 : + node T_4847 = bits(T_4846, 5, 0) + T_4841 <= T_4847 + skip + reg T_4849 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4850 = bits(T_4846, 6, 6) + node T_4851 = and(T_4843, T_4850) + when T_4851 : + node T_4853 = add(T_4849, UInt<1>("h01")) + node T_4854 = tail(T_4853, 1) + T_4849 <= T_4854 + skip + node T_4855 = cat(T_4849, T_4841) + reg T_4857 : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + node T_4859 = neq(io.uarch_counters[15], UInt<1>("h00")) + node T_4861 = add(T_4857, UInt<7>("h01")) + node T_4862 = tail(T_4861, 1) + when T_4859 : + node T_4863 = bits(T_4862, 5, 0) + T_4857 <= T_4863 + skip + reg T_4865 : UInt<58>, clk with : (reset => (reset, UInt<58>("h00"))) + node T_4866 = bits(T_4862, 6, 6) + node T_4867 = and(T_4859, T_4866) + when T_4867 : + node T_4869 = add(T_4865, UInt<1>("h01")) + node T_4870 = tail(T_4869, 1) + T_4865 <= T_4870 + skip + node T_4871 = cat(T_4865, T_4857) + reg reg_fflags : UInt<5>, clk + reg reg_frm : UInt<3>, clk node irq_rocc = and(UInt<1>("h00"), io.rocc.interrupt) io.interrupt_cause <= UInt<1>("h00") - node T_4859 = bit(io.interrupt_cause, 63) - io.interrupt <= T_4859 + node T_4879 = bits(io.interrupt_cause, 63, 63) + io.interrupt <= T_4879 wire some_interrupt_pending : UInt<1> some_interrupt_pending <= UInt<1>("h00") - node T_4863 = and(reg_mie.ssip, reg_mip.ssip) - node T_4864 = lt(reg_mstatus.prv, UInt<1>("h01")) - node T_4865 = eq(reg_mstatus.prv, UInt<1>("h01")) - node T_4866 = and(T_4865, reg_mstatus.ie) - node T_4867 = or(T_4864, T_4866) - node T_4868 = and(T_4863, T_4867) - when T_4868 : + node T_4883 = and(reg_mie.ssip, reg_mip.ssip) + node T_4884 = lt(reg_mstatus.prv, UInt<1>("h01")) + node T_4885 = eq(reg_mstatus.prv, UInt<1>("h01")) + node T_4886 = and(T_4885, reg_mstatus.ie) + node T_4887 = or(T_4884, T_4886) + node T_4888 = and(T_4883, T_4887) + when T_4888 : io.interrupt_cause <= UInt<64>("h08000000000000000") skip - node T_4870 = leq(reg_mstatus.prv, UInt<1>("h01")) - node T_4871 = and(T_4863, T_4870) - when T_4871 : + node T_4890 = leq(reg_mstatus.prv, UInt<1>("h01")) + node T_4891 = and(T_4883, T_4890) + when T_4891 : some_interrupt_pending <= UInt<1>("h01") skip - node T_4874 = and(reg_mie.msip, reg_mip.msip) - node T_4875 = lt(reg_mstatus.prv, UInt<2>("h03")) - node T_4876 = eq(reg_mstatus.prv, UInt<2>("h03")) - node T_4877 = and(T_4876, reg_mstatus.ie) - node T_4878 = or(T_4875, T_4877) - node T_4879 = and(T_4874, T_4878) - when T_4879 : + node T_4894 = and(reg_mie.msip, reg_mip.msip) + node T_4895 = lt(reg_mstatus.prv, UInt<2>("h03")) + node T_4896 = eq(reg_mstatus.prv, UInt<2>("h03")) + node T_4897 = and(T_4896, reg_mstatus.ie) + node T_4898 = or(T_4895, T_4897) + node T_4899 = and(T_4894, T_4898) + when T_4899 : io.interrupt_cause <= UInt<64>("h08000000000000000") skip - node T_4881 = leq(reg_mstatus.prv, UInt<2>("h03")) - node T_4882 = and(T_4874, T_4881) - when T_4882 : + node T_4901 = leq(reg_mstatus.prv, UInt<2>("h03")) + node T_4902 = and(T_4894, T_4901) + when T_4902 : some_interrupt_pending <= UInt<1>("h01") skip - node T_4885 = and(reg_mie.stip, reg_mip.stip) - node T_4886 = lt(reg_mstatus.prv, UInt<1>("h01")) - node T_4887 = eq(reg_mstatus.prv, UInt<1>("h01")) - node T_4888 = and(T_4887, reg_mstatus.ie) - node T_4889 = or(T_4886, T_4888) - node T_4890 = and(T_4885, T_4889) - when T_4890 : + node T_4905 = and(reg_mie.stip, reg_mip.stip) + node T_4906 = lt(reg_mstatus.prv, UInt<1>("h01")) + node T_4907 = eq(reg_mstatus.prv, UInt<1>("h01")) + node T_4908 = and(T_4907, reg_mstatus.ie) + node T_4909 = or(T_4906, T_4908) + node T_4910 = and(T_4905, T_4909) + when T_4910 : io.interrupt_cause <= UInt<64>("h08000000000000001") skip - node T_4892 = leq(reg_mstatus.prv, UInt<1>("h01")) - node T_4893 = and(T_4885, T_4892) - when T_4893 : + node T_4912 = leq(reg_mstatus.prv, UInt<1>("h01")) + node T_4913 = and(T_4905, T_4912) + when T_4913 : some_interrupt_pending <= UInt<1>("h01") skip - node T_4896 = and(reg_mie.mtip, reg_mip.mtip) - node T_4897 = lt(reg_mstatus.prv, UInt<2>("h03")) - node T_4898 = eq(reg_mstatus.prv, UInt<2>("h03")) - node T_4899 = and(T_4898, reg_mstatus.ie) - node T_4900 = or(T_4897, T_4899) - node T_4901 = and(T_4896, T_4900) - when T_4901 : + node T_4916 = and(reg_mie.mtip, reg_mip.mtip) + node T_4917 = lt(reg_mstatus.prv, UInt<2>("h03")) + node T_4918 = eq(reg_mstatus.prv, UInt<2>("h03")) + node T_4919 = and(T_4918, reg_mstatus.ie) + node T_4920 = or(T_4917, T_4919) + node T_4921 = and(T_4916, T_4920) + when T_4921 : io.interrupt_cause <= UInt<64>("h08000000000000001") skip - node T_4903 = leq(reg_mstatus.prv, UInt<2>("h03")) - node T_4904 = and(T_4896, T_4903) - when T_4904 : + node T_4923 = leq(reg_mstatus.prv, UInt<2>("h03")) + node T_4924 = and(T_4916, T_4923) + when T_4924 : some_interrupt_pending <= UInt<1>("h01") skip - node T_4908 = neq(reg_fromhost, UInt<1>("h00")) - node T_4909 = lt(reg_mstatus.prv, UInt<2>("h03")) - node T_4910 = eq(reg_mstatus.prv, UInt<2>("h03")) - node T_4911 = and(T_4910, reg_mstatus.ie) - node T_4912 = or(T_4909, T_4911) - node T_4913 = and(T_4908, T_4912) - when T_4913 : + node T_4928 = neq(reg_fromhost, UInt<1>("h00")) + node T_4929 = lt(reg_mstatus.prv, UInt<2>("h03")) + node T_4930 = eq(reg_mstatus.prv, UInt<2>("h03")) + node T_4931 = and(T_4930, reg_mstatus.ie) + node T_4932 = or(T_4929, T_4931) + node T_4933 = and(T_4928, T_4932) + when T_4933 : io.interrupt_cause <= UInt<64>("h08000000000000002") skip - node T_4915 = leq(reg_mstatus.prv, UInt<2>("h03")) - node T_4916 = and(T_4908, T_4915) - when T_4916 : + node T_4935 = leq(reg_mstatus.prv, UInt<2>("h03")) + node T_4936 = and(T_4928, T_4935) + when T_4936 : some_interrupt_pending <= UInt<1>("h01") skip - node T_4919 = lt(reg_mstatus.prv, UInt<2>("h03")) - node T_4920 = eq(reg_mstatus.prv, UInt<2>("h03")) - node T_4921 = and(T_4920, reg_mstatus.ie) - node T_4922 = or(T_4919, T_4921) - node T_4923 = and(irq_rocc, T_4922) - when T_4923 : + node T_4939 = lt(reg_mstatus.prv, UInt<2>("h03")) + node T_4940 = eq(reg_mstatus.prv, UInt<2>("h03")) + node T_4941 = and(T_4940, reg_mstatus.ie) + node T_4942 = or(T_4939, T_4941) + node T_4943 = and(irq_rocc, T_4942) + when T_4943 : io.interrupt_cause <= UInt<64>("h08000000000000003") skip - node T_4925 = leq(reg_mstatus.prv, UInt<2>("h03")) - node T_4926 = and(irq_rocc, T_4925) - when T_4926 : + node T_4945 = leq(reg_mstatus.prv, UInt<2>("h03")) + node T_4946 = and(irq_rocc, T_4945) + when T_4946 : some_interrupt_pending <= UInt<1>("h01") skip node system_insn = eq(io.rw.cmd, UInt<3>("h04")) - node T_4929 = neq(io.rw.cmd, UInt<3>("h00")) - node T_4931 = eq(system_insn, UInt<1>("h00")) - node cpu_ren = and(T_4929, T_4931) - reg host_csr_req_valid : UInt<1>, clk, UInt<1>("h00"), host_csr_req_valid - node T_4936 = eq(cpu_ren, UInt<1>("h00")) - node host_csr_req_fire = and(host_csr_req_valid, T_4936) - reg host_csr_rep_valid : UInt<1>, clk, UInt<1>("h00"), host_csr_rep_valid - reg host_csr_bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}, clk, UInt<1>("h00"), host_csr_bits - node T_4945 = eq(host_csr_req_valid, UInt<1>("h00")) - node T_4947 = eq(host_csr_rep_valid, UInt<1>("h00")) - node T_4948 = and(T_4945, T_4947) - io.host.csr.req.ready <= T_4948 + node T_4949 = neq(io.rw.cmd, UInt<3>("h00")) + node T_4951 = eq(system_insn, UInt<1>("h00")) + node cpu_ren = and(T_4949, T_4951) + reg host_csr_req_valid : UInt<1>, clk + node T_4956 = eq(cpu_ren, UInt<1>("h00")) + node host_csr_req_fire = and(host_csr_req_valid, T_4956) + reg host_csr_rep_valid : UInt<1>, clk + reg host_csr_bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}, clk + node T_4965 = eq(host_csr_req_valid, UInt<1>("h00")) + node T_4967 = eq(host_csr_rep_valid, UInt<1>("h00")) + node T_4968 = and(T_4965, T_4967) + io.host.csr.req.ready <= T_4968 io.host.csr.resp.valid <= host_csr_rep_valid io.host.csr.resp.bits <= host_csr_bits.data - node T_4949 = and(io.host.csr.req.ready, io.host.csr.req.valid) - when T_4949 : + node T_4969 = and(io.host.csr.req.ready, io.host.csr.req.valid) + when T_4969 : host_csr_req_valid <= UInt<1>("h01") host_csr_bits <- io.host.csr.req.bits skip @@ -21057,357 +14798,337 @@ circuit Top : host_csr_rep_valid <= UInt<1>("h01") host_csr_bits.data <= io.rw.rdata skip - node T_4953 = and(io.host.csr.resp.ready, io.host.csr.resp.valid) - when T_4953 : + node T_4973 = and(io.host.csr.resp.ready, io.host.csr.resp.valid) + when T_4973 : host_csr_rep_valid <= UInt<1>("h00") skip io.host.debug_stats_csr <= reg_stats - node T_4955 = cat(io.status.sd, io.status.zero2) - node T_4956 = cat(io.status.sd_rv32, io.status.zero1) - node T_4957 = cat(T_4955, T_4956) - node T_4958 = cat(io.status.vm, io.status.mprv) - node T_4959 = cat(io.status.xs, io.status.fs) - node T_4960 = cat(T_4958, T_4959) - node T_4961 = cat(T_4957, T_4960) - node T_4962 = cat(io.status.prv3, io.status.ie3) - node T_4963 = cat(io.status.prv2, io.status.ie2) - node T_4964 = cat(T_4962, T_4963) - node T_4965 = cat(io.status.prv1, io.status.ie1) - node T_4966 = cat(io.status.prv, io.status.ie) - node T_4967 = cat(T_4965, T_4966) - node T_4968 = cat(T_4964, T_4967) - node read_mstatus = cat(T_4961, T_4968) - node T_4970 = cat(reg_frm, reg_fflags) - node T_4978 = cat(reg_mip.mtip, reg_mip.htip) - node T_4979 = cat(reg_mip.stip, reg_mip.utip) + node T_4975 = cat(io.status.sd, io.status.zero2) + node T_4976 = cat(io.status.sd_rv32, io.status.zero1) + node T_4977 = cat(T_4975, T_4976) + node T_4978 = cat(io.status.vm, io.status.mprv) + node T_4979 = cat(io.status.xs, io.status.fs) node T_4980 = cat(T_4978, T_4979) - node T_4981 = cat(reg_mip.msip, reg_mip.hsip) - node T_4982 = cat(reg_mip.ssip, reg_mip.usip) - node T_4983 = cat(T_4981, T_4982) - node T_4984 = cat(T_4980, T_4983) - node T_4985 = cat(reg_mie.mtip, reg_mie.htip) - node T_4986 = cat(reg_mie.stip, reg_mie.utip) + node T_4981 = cat(T_4977, T_4980) + node T_4982 = cat(io.status.prv3, io.status.ie3) + node T_4983 = cat(io.status.prv2, io.status.ie2) + node T_4984 = cat(T_4982, T_4983) + node T_4985 = cat(io.status.prv1, io.status.ie1) + node T_4986 = cat(io.status.prv, io.status.ie) node T_4987 = cat(T_4985, T_4986) - node T_4988 = cat(reg_mie.msip, reg_mie.hsip) - node T_4989 = cat(reg_mie.ssip, reg_mie.usip) - node T_4990 = cat(T_4988, T_4989) - node T_4991 = cat(T_4987, T_4990) - node T_4992 = bit(reg_mepc, 39) - node T_4994 = subw(UInt<24>("h00"), T_4992) - node T_4995 = cat(T_4994, reg_mepc) - node T_4996 = bit(reg_mbadaddr, 39) - node T_4998 = subw(UInt<24>("h00"), T_4996) - node T_4999 = cat(T_4998, reg_mbadaddr) - wire T_5026 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} - T_5026.ie <= UInt<1>("h00") - T_5026.zero1 <= UInt<1>("h00") - T_5026.pie <= UInt<1>("h00") - T_5026.ps <= UInt<1>("h00") - T_5026.zero2 <= UInt<1>("h00") - T_5026.fs <= UInt<1>("h00") - T_5026.xs <= UInt<1>("h00") - T_5026.mprv <= UInt<1>("h00") - T_5026.zero3 <= UInt<1>("h00") - T_5026.sd_rv32 <= UInt<1>("h00") - T_5026.zero4 <= UInt<1>("h00") - T_5026.sd <= UInt<1>("h00") - node T_5051 = bits(read_mstatus, 0, 0) - T_5026.ie <= T_5051 - node T_5052 = bits(read_mstatus, 2, 1) - T_5026.zero1 <= T_5052 - node T_5053 = bits(read_mstatus, 3, 3) - T_5026.pie <= T_5053 - node T_5054 = bits(read_mstatus, 4, 4) - T_5026.ps <= T_5054 - node T_5055 = bits(read_mstatus, 11, 5) - T_5026.zero2 <= T_5055 - node T_5056 = bits(read_mstatus, 13, 12) - T_5026.fs <= T_5056 - node T_5057 = bits(read_mstatus, 15, 14) - T_5026.xs <= T_5057 - node T_5058 = bits(read_mstatus, 16, 16) - T_5026.mprv <= T_5058 - node T_5059 = bits(read_mstatus, 30, 17) - T_5026.zero3 <= T_5059 - node T_5060 = bits(read_mstatus, 31, 31) - T_5026.sd_rv32 <= T_5060 - node T_5061 = bits(read_mstatus, 62, 32) - T_5026.zero4 <= T_5061 - node T_5062 = bits(read_mstatus, 63, 63) - T_5026.sd <= T_5062 - wire T_5063 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} - T_5063 <- T_5026 - T_5063.zero1 <= UInt<1>("h00") - T_5063.zero2 <= UInt<1>("h00") - T_5063.zero3 <= UInt<1>("h00") - T_5063.zero4 <= UInt<1>("h00") - wire T_5099 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5099.usip <= UInt<1>("h00") - T_5099.ssip <= UInt<1>("h00") - T_5099.hsip <= UInt<1>("h00") - T_5099.msip <= UInt<1>("h00") - T_5099.utip <= UInt<1>("h00") - T_5099.stip <= UInt<1>("h00") - T_5099.htip <= UInt<1>("h00") - T_5099.mtip <= UInt<1>("h00") - T_5099.usip <= UInt<1>("h00") - T_5099.ssip <= UInt<1>("h00") - T_5099.hsip <= UInt<1>("h00") - T_5099.msip <= UInt<1>("h00") - T_5099.utip <= UInt<1>("h00") - T_5099.stip <= UInt<1>("h00") - T_5099.htip <= UInt<1>("h00") - T_5099.mtip <= UInt<1>("h00") - wire T_5124 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5124 <- T_5099 - T_5124.ssip <= reg_mip.ssip - T_5124.stip <= reg_mip.stip - wire T_5152 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5152.usip <= UInt<1>("h00") - T_5152.ssip <= UInt<1>("h00") - T_5152.hsip <= UInt<1>("h00") - T_5152.msip <= UInt<1>("h00") - T_5152.utip <= UInt<1>("h00") - T_5152.stip <= UInt<1>("h00") - T_5152.htip <= UInt<1>("h00") - T_5152.mtip <= UInt<1>("h00") - T_5152.usip <= UInt<1>("h00") - T_5152.ssip <= UInt<1>("h00") - T_5152.hsip <= UInt<1>("h00") - T_5152.msip <= UInt<1>("h00") - T_5152.utip <= UInt<1>("h00") - T_5152.stip <= UInt<1>("h00") - T_5152.htip <= UInt<1>("h00") - T_5152.mtip <= UInt<1>("h00") - wire T_5177 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5177 <- T_5152 - T_5177.ssip <= reg_mie.ssip - T_5177.stip <= reg_mie.stip - node T_5186 = cat(T_5063.zero4, T_5063.sd_rv32) - node T_5187 = cat(T_5063.sd, T_5186) - node T_5188 = cat(T_5063.mprv, T_5063.xs) - node T_5189 = cat(T_5063.zero3, T_5188) - node T_5190 = cat(T_5187, T_5189) - node T_5191 = cat(T_5063.zero2, T_5063.ps) - node T_5192 = cat(T_5063.fs, T_5191) - node T_5193 = cat(T_5063.zero1, T_5063.ie) - node T_5194 = cat(T_5063.pie, T_5193) - node T_5195 = cat(T_5192, T_5194) - node T_5196 = cat(T_5190, T_5195) - node T_5197 = cat(T_5124.mtip, T_5124.htip) - node T_5198 = cat(T_5124.stip, T_5124.utip) - node T_5199 = cat(T_5197, T_5198) - node T_5200 = cat(T_5124.msip, T_5124.hsip) - node T_5201 = cat(T_5124.ssip, T_5124.usip) - node T_5202 = cat(T_5200, T_5201) - node T_5203 = cat(T_5199, T_5202) - node T_5204 = cat(T_5177.mtip, T_5177.htip) - node T_5205 = cat(T_5177.stip, T_5177.utip) - node T_5206 = cat(T_5204, T_5205) - node T_5207 = cat(T_5177.msip, T_5177.hsip) - node T_5208 = cat(T_5177.ssip, T_5177.usip) - node T_5209 = cat(T_5207, T_5208) - node T_5210 = cat(T_5206, T_5209) - node T_5211 = bit(reg_sbadaddr, 39) - node T_5213 = subw(UInt<24>("h00"), T_5211) - node T_5214 = cat(T_5213, reg_sbadaddr) - node T_5216 = bit(reg_sepc, 39) - node T_5218 = subw(UInt<24>("h00"), T_5216) - node T_5219 = cat(T_5218, reg_sepc) - node T_5220 = bit(reg_stvec, 38) - node T_5222 = subw(UInt<25>("h00"), T_5220) - node T_5223 = cat(T_5222, reg_stvec) + node T_4988 = cat(T_4984, T_4987) + node read_mstatus = cat(T_4981, T_4988) + node T_4990 = cat(reg_frm, reg_fflags) + node T_4998 = cat(reg_mip.mtip, reg_mip.htip) + node T_4999 = cat(reg_mip.stip, reg_mip.utip) + node T_5000 = cat(T_4998, T_4999) + node T_5001 = cat(reg_mip.msip, reg_mip.hsip) + node T_5002 = cat(reg_mip.ssip, reg_mip.usip) + node T_5003 = cat(T_5001, T_5002) + node T_5004 = cat(T_5000, T_5003) + node T_5005 = cat(reg_mie.mtip, reg_mie.htip) + node T_5006 = cat(reg_mie.stip, reg_mie.utip) + node T_5007 = cat(T_5005, T_5006) + node T_5008 = cat(reg_mie.msip, reg_mie.hsip) + node T_5009 = cat(reg_mie.ssip, reg_mie.usip) + node T_5010 = cat(T_5008, T_5009) + node T_5011 = cat(T_5007, T_5010) + node T_5012 = bits(reg_mepc, 39, 39) + node T_5014 = sub(UInt<24>("h00"), T_5012) + node T_5015 = tail(T_5014, 1) + node T_5016 = cat(T_5015, reg_mepc) + node T_5017 = bits(reg_mbadaddr, 39, 39) + node T_5019 = sub(UInt<24>("h00"), T_5017) + node T_5020 = tail(T_5019, 1) + node T_5021 = cat(T_5020, reg_mbadaddr) + wire T_5048 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} + T_5048 is invalid + node T_5061 = bits(read_mstatus, 0, 0) + T_5048.ie <= T_5061 + node T_5062 = bits(read_mstatus, 2, 1) + T_5048.zero1 <= T_5062 + node T_5063 = bits(read_mstatus, 3, 3) + T_5048.pie <= T_5063 + node T_5064 = bits(read_mstatus, 4, 4) + T_5048.ps <= T_5064 + node T_5065 = bits(read_mstatus, 11, 5) + T_5048.zero2 <= T_5065 + node T_5066 = bits(read_mstatus, 13, 12) + T_5048.fs <= T_5066 + node T_5067 = bits(read_mstatus, 15, 14) + T_5048.xs <= T_5067 + node T_5068 = bits(read_mstatus, 16, 16) + T_5048.mprv <= T_5068 + node T_5069 = bits(read_mstatus, 30, 17) + T_5048.zero3 <= T_5069 + node T_5070 = bits(read_mstatus, 31, 31) + T_5048.sd_rv32 <= T_5070 + node T_5071 = bits(read_mstatus, 62, 32) + T_5048.zero4 <= T_5071 + node T_5072 = bits(read_mstatus, 63, 63) + T_5048.sd <= T_5072 + wire T_5073 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} + T_5073 <- T_5048 + T_5073.zero1 <= UInt<1>("h00") + T_5073.zero2 <= UInt<1>("h00") + T_5073.zero3 <= UInt<1>("h00") + T_5073.zero4 <= UInt<1>("h00") + wire T_5109 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_5109 is invalid + T_5109.usip <= UInt<1>("h00") + T_5109.ssip <= UInt<1>("h00") + T_5109.hsip <= UInt<1>("h00") + T_5109.msip <= UInt<1>("h00") + T_5109.utip <= UInt<1>("h00") + T_5109.stip <= UInt<1>("h00") + T_5109.htip <= UInt<1>("h00") + T_5109.mtip <= UInt<1>("h00") + wire T_5126 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_5126 <- T_5109 + T_5126.ssip <= reg_mip.ssip + T_5126.stip <= reg_mip.stip + wire T_5154 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_5154 is invalid + T_5154.usip <= UInt<1>("h00") + T_5154.ssip <= UInt<1>("h00") + T_5154.hsip <= UInt<1>("h00") + T_5154.msip <= UInt<1>("h00") + T_5154.utip <= UInt<1>("h00") + T_5154.stip <= UInt<1>("h00") + T_5154.htip <= UInt<1>("h00") + T_5154.mtip <= UInt<1>("h00") + wire T_5171 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_5171 <- T_5154 + T_5171.ssip <= reg_mie.ssip + T_5171.stip <= reg_mie.stip + node T_5180 = cat(T_5073.zero4, T_5073.sd_rv32) + node T_5181 = cat(T_5073.sd, T_5180) + node T_5182 = cat(T_5073.mprv, T_5073.xs) + node T_5183 = cat(T_5073.zero3, T_5182) + node T_5184 = cat(T_5181, T_5183) + node T_5185 = cat(T_5073.zero2, T_5073.ps) + node T_5186 = cat(T_5073.fs, T_5185) + node T_5187 = cat(T_5073.zero1, T_5073.ie) + node T_5188 = cat(T_5073.pie, T_5187) + node T_5189 = cat(T_5186, T_5188) + node T_5190 = cat(T_5184, T_5189) + node T_5191 = cat(T_5126.mtip, T_5126.htip) + node T_5192 = cat(T_5126.stip, T_5126.utip) + node T_5193 = cat(T_5191, T_5192) + node T_5194 = cat(T_5126.msip, T_5126.hsip) + node T_5195 = cat(T_5126.ssip, T_5126.usip) + node T_5196 = cat(T_5194, T_5195) + node T_5197 = cat(T_5193, T_5196) + node T_5198 = cat(T_5171.mtip, T_5171.htip) + node T_5199 = cat(T_5171.stip, T_5171.utip) + node T_5200 = cat(T_5198, T_5199) + node T_5201 = cat(T_5171.msip, T_5171.hsip) + node T_5202 = cat(T_5171.ssip, T_5171.usip) + node T_5203 = cat(T_5201, T_5202) + node T_5204 = cat(T_5200, T_5203) + node T_5205 = bits(reg_sbadaddr, 39, 39) + node T_5207 = sub(UInt<24>("h00"), T_5205) + node T_5208 = tail(T_5207, 1) + node T_5209 = cat(T_5208, reg_sbadaddr) + node T_5211 = bits(reg_sepc, 39, 39) + node T_5213 = sub(UInt<24>("h00"), T_5211) + node T_5214 = tail(T_5213, 1) + node T_5215 = cat(T_5214, reg_sepc) + node T_5216 = bits(reg_stvec, 38, 38) + node T_5218 = sub(UInt<25>("h00"), T_5216) + node T_5219 = tail(T_5218, 1) + node T_5220 = cat(T_5219, reg_stvec) node addr = mux(cpu_ren, io.rw.addr, host_csr_bits.addr) - node T_5226 = eq(addr, UInt<1>("h01")) - node T_5228 = eq(addr, UInt<2>("h02")) - node T_5230 = eq(addr, UInt<2>("h03")) - node T_5232 = eq(addr, UInt<12>("h0c00")) - node T_5234 = eq(addr, UInt<12>("h0900")) - node T_5236 = eq(addr, UInt<12>("h0c01")) - node T_5238 = eq(addr, UInt<12>("h0901")) - node T_5240 = eq(addr, UInt<12>("h0d01")) - node T_5242 = eq(addr, UInt<12>("h0a01")) - node T_5244 = eq(addr, UInt<11>("h0701")) - node T_5246 = eq(addr, UInt<12>("h0f00")) - node T_5248 = eq(addr, UInt<12>("h0f01")) - node T_5250 = eq(addr, UInt<10>("h0300")) - node T_5252 = eq(addr, UInt<10>("h0302")) - node T_5254 = eq(addr, UInt<11>("h0782")) - node T_5256 = eq(addr, UInt<10>("h0301")) - node T_5258 = eq(addr, UInt<11>("h0784")) - node T_5260 = eq(addr, UInt<11>("h0783")) - node T_5262 = eq(addr, UInt<10>("h0344")) - node T_5264 = eq(addr, UInt<10>("h0304")) - node T_5266 = eq(addr, UInt<10>("h0340")) - node T_5268 = eq(addr, UInt<10>("h0341")) - node T_5270 = eq(addr, UInt<10>("h0343")) - node T_5272 = eq(addr, UInt<10>("h0342")) - node T_5274 = eq(addr, UInt<10>("h0321")) - node T_5276 = eq(addr, UInt<12>("h0f10")) - node T_5278 = eq(addr, UInt<8>("h0c0")) - node T_5280 = eq(addr, UInt<11>("h0780")) - node T_5282 = eq(addr, UInt<11>("h0781")) - node T_5284 = eq(addr, UInt<12>("h0c02")) - node T_5286 = eq(addr, UInt<12>("h0902")) - node T_5288 = eq(addr, UInt<12>("h0cc0")) - node T_5290 = eq(addr, UInt<12>("h0cc1")) - node T_5292 = eq(addr, UInt<12>("h0cc2")) - node T_5294 = eq(addr, UInt<12>("h0cc3")) - node T_5296 = eq(addr, UInt<12>("h0cc4")) - node T_5298 = eq(addr, UInt<12>("h0cc5")) - node T_5300 = eq(addr, UInt<12>("h0cc6")) - node T_5302 = eq(addr, UInt<12>("h0cc7")) - node T_5304 = eq(addr, UInt<12>("h0cc8")) - node T_5306 = eq(addr, UInt<12>("h0cc9")) - node T_5308 = eq(addr, UInt<12>("h0cca")) - node T_5310 = eq(addr, UInt<12>("h0ccb")) - node T_5312 = eq(addr, UInt<12>("h0ccc")) - node T_5314 = eq(addr, UInt<12>("h0ccd")) - node T_5316 = eq(addr, UInt<12>("h0cce")) - node T_5318 = eq(addr, UInt<12>("h0ccf")) - node T_5320 = eq(addr, UInt<9>("h0100")) - node T_5322 = eq(addr, UInt<9>("h0144")) - node T_5324 = eq(addr, UInt<9>("h0104")) - node T_5326 = eq(addr, UInt<9>("h0140")) - node T_5328 = eq(addr, UInt<12>("h0d42")) - node T_5330 = eq(addr, UInt<12>("h0d43")) - node T_5332 = eq(addr, UInt<9>("h0180")) - node T_5334 = eq(addr, UInt<9>("h0181")) - node T_5336 = eq(addr, UInt<9>("h0141")) - node T_5338 = eq(addr, UInt<9>("h0101")) - node T_5339 = or(T_5226, T_5228) - node T_5340 = or(T_5339, T_5230) - node T_5341 = or(T_5340, T_5232) - node T_5342 = or(T_5341, T_5234) - node T_5343 = or(T_5342, T_5236) - node T_5344 = or(T_5343, T_5238) - node T_5345 = or(T_5344, T_5240) - node T_5346 = or(T_5345, T_5242) - node T_5347 = or(T_5346, T_5244) - node T_5348 = or(T_5347, T_5246) - node T_5349 = or(T_5348, T_5248) - node T_5350 = or(T_5349, T_5250) - node T_5351 = or(T_5350, T_5252) - node T_5352 = or(T_5351, T_5254) - node T_5353 = or(T_5352, T_5256) - node T_5354 = or(T_5353, T_5258) - node T_5355 = or(T_5354, T_5260) - node T_5356 = or(T_5355, T_5262) - node T_5357 = or(T_5356, T_5264) - node T_5358 = or(T_5357, T_5266) - node T_5359 = or(T_5358, T_5268) - node T_5360 = or(T_5359, T_5270) - node T_5361 = or(T_5360, T_5272) - node T_5362 = or(T_5361, T_5274) - node T_5363 = or(T_5362, T_5276) - node T_5364 = or(T_5363, T_5278) - node T_5365 = or(T_5364, T_5280) - node T_5366 = or(T_5365, T_5282) - node T_5367 = or(T_5366, T_5284) - node T_5368 = or(T_5367, T_5286) - node T_5369 = or(T_5368, T_5288) - node T_5370 = or(T_5369, T_5290) - node T_5371 = or(T_5370, T_5292) - node T_5372 = or(T_5371, T_5294) - node T_5373 = or(T_5372, T_5296) - node T_5374 = or(T_5373, T_5298) - node T_5375 = or(T_5374, T_5300) - node T_5376 = or(T_5375, T_5302) - node T_5377 = or(T_5376, T_5304) - node T_5378 = or(T_5377, T_5306) - node T_5379 = or(T_5378, T_5308) - node T_5380 = or(T_5379, T_5310) - node T_5381 = or(T_5380, T_5312) - node T_5382 = or(T_5381, T_5314) - node T_5383 = or(T_5382, T_5316) - node T_5384 = or(T_5383, T_5318) - node T_5385 = or(T_5384, T_5320) - node T_5386 = or(T_5385, T_5322) - node T_5387 = or(T_5386, T_5324) - node T_5388 = or(T_5387, T_5326) - node T_5389 = or(T_5388, T_5328) - node T_5390 = or(T_5389, T_5330) - node T_5391 = or(T_5390, T_5332) - node T_5392 = or(T_5391, T_5334) - node T_5393 = or(T_5392, T_5336) - node addr_valid = or(T_5393, T_5338) - node T_5395 = or(T_5226, T_5228) - node fp_csr = or(T_5395, T_5230) + node T_5223 = eq(addr, UInt<1>("h01")) + node T_5225 = eq(addr, UInt<2>("h02")) + node T_5227 = eq(addr, UInt<2>("h03")) + node T_5229 = eq(addr, UInt<12>("h0c00")) + node T_5231 = eq(addr, UInt<12>("h0900")) + node T_5233 = eq(addr, UInt<12>("h0c01")) + node T_5235 = eq(addr, UInt<12>("h0901")) + node T_5237 = eq(addr, UInt<12>("h0d01")) + node T_5239 = eq(addr, UInt<12>("h0a01")) + node T_5241 = eq(addr, UInt<11>("h0701")) + node T_5243 = eq(addr, UInt<12>("h0f00")) + node T_5245 = eq(addr, UInt<12>("h0f01")) + node T_5247 = eq(addr, UInt<10>("h0300")) + node T_5249 = eq(addr, UInt<10>("h0302")) + node T_5251 = eq(addr, UInt<11>("h0782")) + node T_5253 = eq(addr, UInt<10>("h0301")) + node T_5255 = eq(addr, UInt<11>("h0784")) + node T_5257 = eq(addr, UInt<11>("h0783")) + node T_5259 = eq(addr, UInt<10>("h0344")) + node T_5261 = eq(addr, UInt<10>("h0304")) + node T_5263 = eq(addr, UInt<10>("h0340")) + node T_5265 = eq(addr, UInt<10>("h0341")) + node T_5267 = eq(addr, UInt<10>("h0343")) + node T_5269 = eq(addr, UInt<10>("h0342")) + node T_5271 = eq(addr, UInt<10>("h0321")) + node T_5273 = eq(addr, UInt<12>("h0f10")) + node T_5275 = eq(addr, UInt<8>("h0c0")) + node T_5277 = eq(addr, UInt<11>("h0780")) + node T_5279 = eq(addr, UInt<11>("h0781")) + node T_5281 = eq(addr, UInt<12>("h0c02")) + node T_5283 = eq(addr, UInt<12>("h0902")) + node T_5285 = eq(addr, UInt<12>("h0cc0")) + node T_5287 = eq(addr, UInt<12>("h0cc1")) + node T_5289 = eq(addr, UInt<12>("h0cc2")) + node T_5291 = eq(addr, UInt<12>("h0cc3")) + node T_5293 = eq(addr, UInt<12>("h0cc4")) + node T_5295 = eq(addr, UInt<12>("h0cc5")) + node T_5297 = eq(addr, UInt<12>("h0cc6")) + node T_5299 = eq(addr, UInt<12>("h0cc7")) + node T_5301 = eq(addr, UInt<12>("h0cc8")) + node T_5303 = eq(addr, UInt<12>("h0cc9")) + node T_5305 = eq(addr, UInt<12>("h0cca")) + node T_5307 = eq(addr, UInt<12>("h0ccb")) + node T_5309 = eq(addr, UInt<12>("h0ccc")) + node T_5311 = eq(addr, UInt<12>("h0ccd")) + node T_5313 = eq(addr, UInt<12>("h0cce")) + node T_5315 = eq(addr, UInt<12>("h0ccf")) + node T_5317 = eq(addr, UInt<9>("h0100")) + node T_5319 = eq(addr, UInt<9>("h0144")) + node T_5321 = eq(addr, UInt<9>("h0104")) + node T_5323 = eq(addr, UInt<9>("h0140")) + node T_5325 = eq(addr, UInt<12>("h0d42")) + node T_5327 = eq(addr, UInt<12>("h0d43")) + node T_5329 = eq(addr, UInt<9>("h0180")) + node T_5331 = eq(addr, UInt<9>("h0181")) + node T_5333 = eq(addr, UInt<9>("h0141")) + node T_5335 = eq(addr, UInt<9>("h0101")) + node T_5336 = or(T_5223, T_5225) + node T_5337 = or(T_5336, T_5227) + node T_5338 = or(T_5337, T_5229) + node T_5339 = or(T_5338, T_5231) + node T_5340 = or(T_5339, T_5233) + node T_5341 = or(T_5340, T_5235) + node T_5342 = or(T_5341, T_5237) + node T_5343 = or(T_5342, T_5239) + node T_5344 = or(T_5343, T_5241) + node T_5345 = or(T_5344, T_5243) + node T_5346 = or(T_5345, T_5245) + node T_5347 = or(T_5346, T_5247) + node T_5348 = or(T_5347, T_5249) + node T_5349 = or(T_5348, T_5251) + node T_5350 = or(T_5349, T_5253) + node T_5351 = or(T_5350, T_5255) + node T_5352 = or(T_5351, T_5257) + node T_5353 = or(T_5352, T_5259) + node T_5354 = or(T_5353, T_5261) + node T_5355 = or(T_5354, T_5263) + node T_5356 = or(T_5355, T_5265) + node T_5357 = or(T_5356, T_5267) + node T_5358 = or(T_5357, T_5269) + node T_5359 = or(T_5358, T_5271) + node T_5360 = or(T_5359, T_5273) + node T_5361 = or(T_5360, T_5275) + node T_5362 = or(T_5361, T_5277) + node T_5363 = or(T_5362, T_5279) + node T_5364 = or(T_5363, T_5281) + node T_5365 = or(T_5364, T_5283) + node T_5366 = or(T_5365, T_5285) + node T_5367 = or(T_5366, T_5287) + node T_5368 = or(T_5367, T_5289) + node T_5369 = or(T_5368, T_5291) + node T_5370 = or(T_5369, T_5293) + node T_5371 = or(T_5370, T_5295) + node T_5372 = or(T_5371, T_5297) + node T_5373 = or(T_5372, T_5299) + node T_5374 = or(T_5373, T_5301) + node T_5375 = or(T_5374, T_5303) + node T_5376 = or(T_5375, T_5305) + node T_5377 = or(T_5376, T_5307) + node T_5378 = or(T_5377, T_5309) + node T_5379 = or(T_5378, T_5311) + node T_5380 = or(T_5379, T_5313) + node T_5381 = or(T_5380, T_5315) + node T_5382 = or(T_5381, T_5317) + node T_5383 = or(T_5382, T_5319) + node T_5384 = or(T_5383, T_5321) + node T_5385 = or(T_5384, T_5323) + node T_5386 = or(T_5385, T_5325) + node T_5387 = or(T_5386, T_5327) + node T_5388 = or(T_5387, T_5329) + node T_5389 = or(T_5388, T_5331) + node T_5390 = or(T_5389, T_5333) + node addr_valid = or(T_5390, T_5335) + node T_5392 = or(T_5223, T_5225) + node fp_csr = or(T_5392, T_5227) node csr_addr_priv = bits(io.rw.addr, 9, 8) node priv_sufficient = geq(reg_mstatus.prv, csr_addr_priv) - node T_5399 = bits(io.rw.addr, 11, 10) - node T_5400 = not(T_5399) - node read_only = eq(T_5400, UInt<1>("h00")) - node T_5403 = neq(io.rw.cmd, UInt<3>("h05")) - node T_5404 = and(cpu_ren, T_5403) - node cpu_wen = and(T_5404, priv_sufficient) - node T_5407 = eq(read_only, UInt<1>("h00")) - node T_5408 = and(cpu_wen, T_5407) - node T_5409 = and(host_csr_req_fire, host_csr_bits.rw) - node wen = or(T_5408, T_5409) - node T_5411 = eq(io.rw.cmd, UInt<3>("h01")) - node T_5412 = eq(io.rw.cmd, UInt<3>("h03")) - node T_5413 = not(io.rw.wdata) - node T_5414 = and(io.rw.rdata, T_5413) - node T_5415 = eq(io.rw.cmd, UInt<3>("h02")) - node T_5416 = or(io.rw.rdata, io.rw.wdata) - node T_5417 = mux(T_5415, T_5416, host_csr_bits.data) - node T_5418 = mux(T_5412, T_5414, T_5417) - node wdata = mux(T_5411, io.rw.wdata, T_5418) - node T_5420 = bit(io.rw.addr, 8) + node T_5396 = bits(io.rw.addr, 11, 10) + node T_5397 = not(T_5396) + node read_only = eq(T_5397, UInt<1>("h00")) + node T_5400 = neq(io.rw.cmd, UInt<3>("h05")) + node T_5401 = and(cpu_ren, T_5400) + node cpu_wen = and(T_5401, priv_sufficient) + node T_5404 = eq(read_only, UInt<1>("h00")) + node T_5405 = and(cpu_wen, T_5404) + node T_5406 = and(host_csr_req_fire, host_csr_bits.rw) + node wen = or(T_5405, T_5406) + node T_5408 = eq(io.rw.cmd, UInt<3>("h01")) + node T_5409 = eq(io.rw.cmd, UInt<3>("h03")) + node T_5410 = not(io.rw.wdata) + node T_5411 = and(io.rw.rdata, T_5410) + node T_5412 = eq(io.rw.cmd, UInt<3>("h02")) + node T_5413 = or(io.rw.rdata, io.rw.wdata) + node T_5414 = mux(T_5412, T_5413, host_csr_bits.data) + node T_5415 = mux(T_5409, T_5411, T_5414) + node wdata = mux(T_5408, io.rw.wdata, T_5415) + node T_5417 = bits(io.rw.addr, 8, 8) + node T_5419 = eq(T_5417, UInt<1>("h00")) + node T_5420 = bits(io.rw.addr, 0, 0) node T_5422 = eq(T_5420, UInt<1>("h00")) - node T_5423 = bit(io.rw.addr, 0) - node T_5425 = eq(T_5423, UInt<1>("h00")) - node T_5426 = and(T_5422, T_5425) - node insn_call = and(T_5426, system_insn) - node T_5428 = bit(io.rw.addr, 8) - node T_5430 = eq(T_5428, UInt<1>("h00")) - node T_5431 = bit(io.rw.addr, 0) - node T_5432 = and(T_5430, T_5431) - node insn_break = and(T_5432, system_insn) - node T_5434 = bit(io.rw.addr, 8) - node T_5435 = bit(io.rw.addr, 1) - node T_5437 = eq(T_5435, UInt<1>("h00")) - node T_5438 = and(T_5434, T_5437) - node T_5439 = bit(io.rw.addr, 0) - node T_5441 = eq(T_5439, UInt<1>("h00")) - node T_5442 = and(T_5438, T_5441) - node T_5443 = and(T_5442, system_insn) - node insn_ret = and(T_5443, priv_sufficient) - node T_5445 = bit(io.rw.addr, 8) - node T_5446 = bit(io.rw.addr, 1) - node T_5448 = eq(T_5446, UInt<1>("h00")) - node T_5449 = and(T_5445, T_5448) - node T_5450 = bit(io.rw.addr, 0) - node T_5451 = and(T_5449, T_5450) - node T_5452 = and(T_5451, system_insn) - node insn_sfence_vm = and(T_5452, priv_sufficient) - node T_5454 = bit(io.rw.addr, 2) - node maybe_insn_redirect_trap = and(T_5454, system_insn) + node T_5423 = and(T_5419, T_5422) + node insn_call = and(T_5423, system_insn) + node T_5425 = bits(io.rw.addr, 8, 8) + node T_5427 = eq(T_5425, UInt<1>("h00")) + node T_5428 = bits(io.rw.addr, 0, 0) + node T_5429 = and(T_5427, T_5428) + node insn_break = and(T_5429, system_insn) + node T_5431 = bits(io.rw.addr, 8, 8) + node T_5432 = bits(io.rw.addr, 1, 1) + node T_5434 = eq(T_5432, UInt<1>("h00")) + node T_5435 = and(T_5431, T_5434) + node T_5436 = bits(io.rw.addr, 0, 0) + node T_5438 = eq(T_5436, UInt<1>("h00")) + node T_5439 = and(T_5435, T_5438) + node T_5440 = and(T_5439, system_insn) + node insn_ret = and(T_5440, priv_sufficient) + node T_5442 = bits(io.rw.addr, 8, 8) + node T_5443 = bits(io.rw.addr, 1, 1) + node T_5445 = eq(T_5443, UInt<1>("h00")) + node T_5446 = and(T_5442, T_5445) + node T_5447 = bits(io.rw.addr, 0, 0) + node T_5448 = and(T_5446, T_5447) + node T_5449 = and(T_5448, system_insn) + node insn_sfence_vm = and(T_5449, priv_sufficient) + node T_5451 = bits(io.rw.addr, 2, 2) + node maybe_insn_redirect_trap = and(T_5451, system_insn) node insn_redirect_trap = and(maybe_insn_redirect_trap, priv_sufficient) - node T_5457 = bit(io.rw.addr, 8) - node T_5458 = bit(io.rw.addr, 1) - node T_5459 = and(T_5457, T_5458) - node T_5460 = bit(io.rw.addr, 0) - node T_5462 = eq(T_5460, UInt<1>("h00")) - node T_5463 = and(T_5459, T_5462) - node T_5464 = and(T_5463, system_insn) - node insn_wfi = and(T_5464, priv_sufficient) - node T_5466 = and(cpu_wen, read_only) - node T_5468 = eq(priv_sufficient, UInt<1>("h00")) - node T_5470 = eq(addr_valid, UInt<1>("h00")) - node T_5471 = or(T_5468, T_5470) - node T_5473 = neq(io.status.fs, UInt<1>("h00")) - node T_5475 = eq(T_5473, UInt<1>("h00")) - node T_5476 = and(fp_csr, T_5475) - node T_5477 = or(T_5471, T_5476) - node T_5478 = and(cpu_ren, T_5477) - node T_5479 = or(T_5466, T_5478) - node T_5481 = eq(priv_sufficient, UInt<1>("h00")) - node T_5482 = and(system_insn, T_5481) - node T_5483 = or(T_5479, T_5482) - node T_5484 = or(T_5483, insn_call) - node csr_xcpt = or(T_5484, insn_break) + node T_5454 = bits(io.rw.addr, 8, 8) + node T_5455 = bits(io.rw.addr, 1, 1) + node T_5456 = and(T_5454, T_5455) + node T_5457 = bits(io.rw.addr, 0, 0) + node T_5459 = eq(T_5457, UInt<1>("h00")) + node T_5460 = and(T_5456, T_5459) + node T_5461 = and(T_5460, system_insn) + node insn_wfi = and(T_5461, priv_sufficient) + node T_5463 = and(cpu_wen, read_only) + node T_5465 = eq(priv_sufficient, UInt<1>("h00")) + node T_5467 = eq(addr_valid, UInt<1>("h00")) + node T_5468 = or(T_5465, T_5467) + node T_5470 = neq(io.status.fs, UInt<1>("h00")) + node T_5472 = eq(T_5470, UInt<1>("h00")) + node T_5473 = and(fp_csr, T_5472) + node T_5474 = or(T_5468, T_5473) + node T_5475 = and(cpu_ren, T_5474) + node T_5476 = or(T_5463, T_5475) + node T_5478 = eq(priv_sufficient, UInt<1>("h00")) + node T_5479 = and(system_insn, T_5478) + node T_5480 = or(T_5476, T_5479) + node T_5481 = or(T_5480, insn_call) + node csr_xcpt = or(T_5481, insn_break) when insn_wfi : reg_wfi <= UInt<1>("h01") skip @@ -21415,27 +15136,30 @@ circuit Top : reg_wfi <= UInt<1>("h00") skip io.fatc <= insn_sfence_vm - node T_5488 = or(io.exception, csr_xcpt) - node T_5489 = shl(reg_mstatus.prv, 6) - node T_5491 = addw(T_5489, UInt<9>("h0100")) - node T_5492 = bit(reg_stvec, 38) - node T_5493 = cat(T_5492, reg_stvec) - node T_5494 = bit(reg_mstatus.prv, 1) - node T_5496 = or(T_5494, UInt<1>("h00")) - node T_5497 = mux(T_5496, reg_mepc, reg_sepc) - node T_5498 = mux(maybe_insn_redirect_trap, T_5493, T_5497) - node T_5499 = mux(T_5488, T_5491, T_5498) - io.evec <= T_5499 + node T_5485 = or(io.exception, csr_xcpt) + node T_5486 = shl(reg_mstatus.prv, 6) + node T_5488 = add(T_5486, UInt<9>("h0100")) + node T_5489 = tail(T_5488, 1) + node T_5490 = bits(reg_stvec, 38, 38) + node T_5491 = cat(T_5490, reg_stvec) + node T_5492 = bits(reg_mstatus.prv, 1, 1) + node T_5494 = or(T_5492, UInt<1>("h00")) + node T_5495 = mux(T_5494, reg_mepc, reg_sepc) + node T_5496 = mux(maybe_insn_redirect_trap, T_5491, T_5495) + node T_5497 = mux(T_5485, T_5489, T_5496) + io.evec <= T_5497 io.ptbr <= reg_sptbr io.csr_xcpt <= csr_xcpt - node T_5500 = or(insn_ret, insn_redirect_trap) - io.eret <= T_5500 + node T_5498 = or(insn_ret, insn_redirect_trap) + io.eret <= T_5498 io.status <- reg_mstatus - node T_5502 = neq(reg_mstatus.fs, UInt<1>("h00")) - node T_5504 = subw(UInt<2>("h00"), T_5502) - io.status.fs <= T_5504 - node T_5506 = neq(reg_mstatus.xs, UInt<1>("h00")) - node T_5508 = subw(UInt<2>("h00"), T_5506) + node T_5500 = neq(reg_mstatus.fs, UInt<1>("h00")) + node T_5502 = sub(UInt<2>("h00"), T_5500) + node T_5503 = tail(T_5502, 1) + io.status.fs <= T_5503 + node T_5505 = neq(reg_mstatus.xs, UInt<1>("h00")) + node T_5507 = sub(UInt<2>("h00"), T_5505) + node T_5508 = tail(T_5507, 1) io.status.xs <= T_5508 node T_5509 = not(io.status.fs) node T_5511 = eq(T_5509, UInt<1>("h00")) @@ -21463,29 +15187,30 @@ circuit Top : reg_mcause <= UInt<2>("h03") skip when insn_call : - node T_5527 = addw(reg_mstatus.prv, UInt<4>("h08")) - reg_mcause <= T_5527 + node T_5527 = add(reg_mstatus.prv, UInt<4>("h08")) + node T_5528 = tail(T_5527, 1) + reg_mcause <= T_5528 skip skip reg_mbadaddr <= io.pc - node T_5529 = eq(io.cause, UInt<3>("h05")) - node T_5531 = eq(io.cause, UInt<3>("h04")) - node T_5532 = or(T_5529, T_5531) - node T_5534 = eq(io.cause, UInt<3>("h07")) - node T_5535 = or(T_5532, T_5534) - node T_5537 = eq(io.cause, UInt<3>("h06")) - node T_5538 = or(T_5535, T_5537) - when T_5538 : - node T_5539 = bits(io.rw.wdata, 63, 39) - node T_5540 = bits(io.rw.wdata, 38, 0) - node T_5541 = asSInt(T_5540) - node T_5543 = lt(T_5541, asSInt(UInt<1>("h00"))) - node T_5544 = not(T_5539) - node T_5546 = eq(T_5544, UInt<1>("h00")) - node T_5548 = neq(T_5539, UInt<1>("h00")) - node T_5549 = mux(T_5543, T_5546, T_5548) - node T_5550 = cat(T_5549, T_5540) - reg_mbadaddr <= T_5550 + node T_5530 = eq(io.cause, UInt<3>("h05")) + node T_5532 = eq(io.cause, UInt<3>("h04")) + node T_5533 = or(T_5530, T_5532) + node T_5535 = eq(io.cause, UInt<3>("h07")) + node T_5536 = or(T_5533, T_5535) + node T_5538 = eq(io.cause, UInt<3>("h06")) + node T_5539 = or(T_5536, T_5538) + when T_5539 : + node T_5540 = bits(io.rw.wdata, 63, 39) + node T_5541 = bits(io.rw.wdata, 38, 0) + node T_5542 = asSInt(T_5541) + node T_5544 = lt(T_5542, asSInt(UInt<1>("h00"))) + node T_5545 = not(T_5540) + node T_5547 = eq(T_5545, UInt<1>("h00")) + node T_5549 = neq(T_5540, UInt<1>("h00")) + node T_5550 = mux(T_5544, T_5547, T_5549) + node T_5551 = cat(T_5550, T_5541) + reg_mbadaddr <= T_5551 skip skip when insn_ret : @@ -21502,501 +15227,450 @@ circuit Top : reg_scause <= reg_mcause reg_sepc <= reg_mepc skip - node T_5555 = cat(UInt<1>("h00"), insn_redirect_trap) - node T_5556 = addw(insn_ret, T_5555) - node T_5559 = cat(UInt<1>("h00"), csr_xcpt) - node T_5560 = addw(io.exception, T_5559) - node T_5561 = cat(UInt<1>("h00"), T_5560) - node T_5562 = addw(T_5556, T_5561) - node T_5564 = leq(T_5562, UInt<1>("h01")) - node T_5566 = eq(reset, UInt<1>("h00")) - when T_5566 : - node T_5568 = eq(T_5564, UInt<1>("h00")) - when T_5568 : - node T_5570 = eq(reset, UInt<1>("h00")) - when T_5570 : + node T_5556 = cat(UInt<1>("h00"), insn_redirect_trap) + node T_5557 = add(insn_ret, T_5556) + node T_5558 = tail(T_5557, 1) + node T_5561 = cat(UInt<1>("h00"), csr_xcpt) + node T_5562 = add(io.exception, T_5561) + node T_5563 = tail(T_5562, 1) + node T_5564 = cat(UInt<1>("h00"), T_5563) + node T_5565 = add(T_5558, T_5564) + node T_5566 = tail(T_5565, 1) + node T_5568 = leq(T_5566, UInt<1>("h01")) + node T_5570 = eq(reset, UInt<1>("h00")) + when T_5570 : + node T_5572 = eq(T_5568, UInt<1>("h00")) + when T_5572 : + node T_5574 = eq(reset, UInt<1>("h00")) + when T_5574 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): these conditions must be mutually exclusive") skip stop(clk, UInt<1>(1), 1) skip skip - node T_5571 = geq(reg_time, reg_mtimecmp) - when T_5571 : + node T_5575 = geq(reg_time, reg_mtimecmp) + when T_5575 : reg_mip.mtip <= UInt<1>("h01") skip - io.time <= T_4627 + io.time <= T_4615 io.csr_stall <= reg_wfi - node T_5574 = eq(host_csr_bits.rw, UInt<1>("h00")) - node T_5575 = and(host_csr_req_fire, T_5574) - node T_5576 = and(T_5575, T_5280) - when T_5576 : + node T_5578 = eq(host_csr_bits.rw, UInt<1>("h00")) + node T_5579 = and(host_csr_req_fire, T_5578) + node T_5580 = and(T_5579, T_5277) + when T_5580 : reg_tohost <= UInt<1>("h00") skip - node T_5579 = mux(T_5226, reg_fflags, UInt<1>("h00")) - node T_5581 = mux(T_5228, reg_frm, UInt<1>("h00")) - node T_5583 = mux(T_5230, T_4970, UInt<1>("h00")) - node T_5585 = mux(T_5232, T_4627, UInt<1>("h00")) - node T_5587 = mux(T_5234, T_4627, UInt<1>("h00")) - node T_5589 = mux(T_5236, reg_time, UInt<1>("h00")) - node T_5591 = mux(T_5238, reg_time, UInt<1>("h00")) - node T_5593 = mux(T_5240, reg_time, UInt<1>("h00")) - node T_5595 = mux(T_5242, reg_time, UInt<1>("h00")) - node T_5597 = mux(T_5244, reg_time, UInt<1>("h00")) - node T_5599 = mux(T_5246, UInt<64>("h08000000000041129"), UInt<1>("h00")) - node T_5601 = mux(T_5248, UInt<1>("h01"), UInt<1>("h00")) - node T_5603 = mux(T_5250, read_mstatus, UInt<1>("h00")) - node T_5605 = mux(T_5252, UInt<1>("h00"), UInt<1>("h00")) - node T_5607 = mux(T_5254, UInt<1>("h00"), UInt<1>("h00")) - node T_5609 = mux(T_5256, UInt<9>("h0100"), UInt<1>("h00")) - node T_5611 = mux(T_5258, UInt<31>("h040000000"), UInt<1>("h00")) - node T_5613 = mux(T_5260, UInt<1>("h00"), UInt<1>("h00")) - node T_5615 = mux(T_5262, T_4984, UInt<1>("h00")) - node T_5617 = mux(T_5264, T_4991, UInt<1>("h00")) - node T_5619 = mux(T_5266, reg_mscratch, UInt<1>("h00")) - node T_5621 = mux(T_5268, T_4995, UInt<1>("h00")) - node T_5623 = mux(T_5270, T_4999, UInt<1>("h00")) - node T_5625 = mux(T_5272, reg_mcause, UInt<1>("h00")) - node T_5627 = mux(T_5274, reg_mtimecmp, UInt<1>("h00")) - node T_5629 = mux(T_5276, io.host.id, UInt<1>("h00")) - node T_5631 = shl(reg_stats, 0) - node T_5632 = mux(T_5278, T_5631, UInt<1>("h00")) - node T_5634 = mux(T_5280, reg_tohost, UInt<1>("h00")) - node T_5636 = mux(T_5282, reg_fromhost, UInt<1>("h00")) - node T_5638 = mux(T_5284, T_4612, UInt<1>("h00")) - node T_5640 = mux(T_5286, T_4612, UInt<1>("h00")) - node T_5642 = mux(T_5288, T_4641, UInt<1>("h00")) - node T_5644 = mux(T_5290, T_4655, UInt<1>("h00")) - node T_5646 = mux(T_5292, T_4669, UInt<1>("h00")) - node T_5648 = mux(T_5294, T_4683, UInt<1>("h00")) - node T_5650 = mux(T_5296, T_4697, UInt<1>("h00")) - node T_5652 = mux(T_5298, T_4711, UInt<1>("h00")) - node T_5654 = mux(T_5300, T_4725, UInt<1>("h00")) - node T_5656 = mux(T_5302, T_4739, UInt<1>("h00")) - node T_5658 = mux(T_5304, T_4753, UInt<1>("h00")) - node T_5660 = mux(T_5306, T_4767, UInt<1>("h00")) - node T_5662 = mux(T_5308, T_4781, UInt<1>("h00")) - node T_5664 = mux(T_5310, T_4795, UInt<1>("h00")) - node T_5666 = mux(T_5312, T_4809, UInt<1>("h00")) - node T_5668 = mux(T_5314, T_4823, UInt<1>("h00")) - node T_5670 = mux(T_5316, T_4837, UInt<1>("h00")) - node T_5672 = mux(T_5318, T_4851, UInt<1>("h00")) - node T_5674 = mux(T_5320, T_5196, UInt<1>("h00")) - node T_5676 = mux(T_5322, T_5203, UInt<1>("h00")) - node T_5678 = mux(T_5324, T_5210, UInt<1>("h00")) - node T_5680 = mux(T_5326, reg_sscratch, UInt<1>("h00")) - node T_5682 = mux(T_5328, reg_scause, UInt<1>("h00")) - node T_5684 = mux(T_5330, T_5214, UInt<1>("h00")) - node T_5686 = mux(T_5332, reg_sptbr, UInt<1>("h00")) - node T_5688 = mux(T_5334, UInt<1>("h00"), UInt<1>("h00")) - node T_5690 = mux(T_5336, T_5219, UInt<1>("h00")) - node T_5692 = mux(T_5338, T_5223, UInt<1>("h00")) - node T_5694 = or(T_5579, T_5581) - node T_5695 = or(T_5694, T_5583) - node T_5696 = or(T_5695, T_5585) - node T_5697 = or(T_5696, T_5587) - node T_5698 = or(T_5697, T_5589) - node T_5699 = or(T_5698, T_5591) - node T_5700 = or(T_5699, T_5593) - node T_5701 = or(T_5700, T_5595) - node T_5702 = or(T_5701, T_5597) - node T_5703 = or(T_5702, T_5599) - node T_5704 = or(T_5703, T_5601) - node T_5705 = or(T_5704, T_5603) - node T_5706 = or(T_5705, T_5605) - node T_5707 = or(T_5706, T_5607) - node T_5708 = or(T_5707, T_5609) - node T_5709 = or(T_5708, T_5611) - node T_5710 = or(T_5709, T_5613) - node T_5711 = or(T_5710, T_5615) - node T_5712 = or(T_5711, T_5617) - node T_5713 = or(T_5712, T_5619) - node T_5714 = or(T_5713, T_5621) - node T_5715 = or(T_5714, T_5623) - node T_5716 = or(T_5715, T_5625) - node T_5717 = or(T_5716, T_5627) - node T_5718 = or(T_5717, T_5629) - node T_5719 = or(T_5718, T_5632) - node T_5720 = or(T_5719, T_5634) - node T_5721 = or(T_5720, T_5636) - node T_5722 = or(T_5721, T_5638) - node T_5723 = or(T_5722, T_5640) - node T_5724 = or(T_5723, T_5642) - node T_5725 = or(T_5724, T_5644) - node T_5726 = or(T_5725, T_5646) - node T_5727 = or(T_5726, T_5648) - node T_5728 = or(T_5727, T_5650) - node T_5729 = or(T_5728, T_5652) - node T_5730 = or(T_5729, T_5654) - node T_5731 = or(T_5730, T_5656) - node T_5732 = or(T_5731, T_5658) - node T_5733 = or(T_5732, T_5660) - node T_5734 = or(T_5733, T_5662) - node T_5735 = or(T_5734, T_5664) - node T_5736 = or(T_5735, T_5666) - node T_5737 = or(T_5736, T_5668) - node T_5738 = or(T_5737, T_5670) - node T_5739 = or(T_5738, T_5672) - node T_5740 = or(T_5739, T_5674) - node T_5741 = or(T_5740, T_5676) - node T_5742 = or(T_5741, T_5678) - node T_5743 = or(T_5742, T_5680) - node T_5744 = or(T_5743, T_5682) - node T_5745 = or(T_5744, T_5684) - node T_5746 = or(T_5745, T_5686) - node T_5747 = or(T_5746, T_5688) - node T_5748 = or(T_5747, T_5690) - node T_5749 = or(T_5748, T_5692) - wire T_5750 : UInt<64> - T_5750 <= UInt<1>("h00") - T_5750 <= T_5749 - io.rw.rdata <= T_5750 + node T_5583 = mux(T_5223, reg_fflags, UInt<1>("h00")) + node T_5585 = mux(T_5225, reg_frm, UInt<1>("h00")) + node T_5587 = mux(T_5227, T_4990, UInt<1>("h00")) + node T_5589 = mux(T_5229, T_4615, UInt<1>("h00")) + node T_5591 = mux(T_5231, T_4615, UInt<1>("h00")) + node T_5593 = mux(T_5233, reg_time, UInt<1>("h00")) + node T_5595 = mux(T_5235, reg_time, UInt<1>("h00")) + node T_5597 = mux(T_5237, reg_time, UInt<1>("h00")) + node T_5599 = mux(T_5239, reg_time, UInt<1>("h00")) + node T_5601 = mux(T_5241, reg_time, UInt<1>("h00")) + node T_5603 = mux(T_5243, UInt<64>("h08000000000041129"), UInt<1>("h00")) + node T_5605 = mux(T_5245, UInt<1>("h01"), UInt<1>("h00")) + node T_5607 = mux(T_5247, read_mstatus, UInt<1>("h00")) + node T_5609 = mux(T_5249, UInt<1>("h00"), UInt<1>("h00")) + node T_5611 = mux(T_5251, UInt<1>("h00"), UInt<1>("h00")) + node T_5613 = mux(T_5253, UInt<9>("h0100"), UInt<1>("h00")) + node T_5615 = mux(T_5255, UInt<31>("h040000000"), UInt<1>("h00")) + node T_5617 = mux(T_5257, UInt<1>("h00"), UInt<1>("h00")) + node T_5619 = mux(T_5259, T_5004, UInt<1>("h00")) + node T_5621 = mux(T_5261, T_5011, UInt<1>("h00")) + node T_5623 = mux(T_5263, reg_mscratch, UInt<1>("h00")) + node T_5625 = mux(T_5265, T_5016, UInt<1>("h00")) + node T_5627 = mux(T_5267, T_5021, UInt<1>("h00")) + node T_5629 = mux(T_5269, reg_mcause, UInt<1>("h00")) + node T_5631 = mux(T_5271, reg_mtimecmp, UInt<1>("h00")) + node T_5633 = mux(T_5273, io.host.id, UInt<1>("h00")) + node T_5635 = shl(reg_stats, 0) + node T_5636 = mux(T_5275, T_5635, UInt<1>("h00")) + node T_5638 = mux(T_5277, reg_tohost, UInt<1>("h00")) + node T_5640 = mux(T_5279, reg_fromhost, UInt<1>("h00")) + node T_5642 = mux(T_5281, T_4598, UInt<1>("h00")) + node T_5644 = mux(T_5283, T_4598, UInt<1>("h00")) + node T_5646 = mux(T_5285, T_4631, UInt<1>("h00")) + node T_5648 = mux(T_5287, T_4647, UInt<1>("h00")) + node T_5650 = mux(T_5289, T_4663, UInt<1>("h00")) + node T_5652 = mux(T_5291, T_4679, UInt<1>("h00")) + node T_5654 = mux(T_5293, T_4695, UInt<1>("h00")) + node T_5656 = mux(T_5295, T_4711, UInt<1>("h00")) + node T_5658 = mux(T_5297, T_4727, UInt<1>("h00")) + node T_5660 = mux(T_5299, T_4743, UInt<1>("h00")) + node T_5662 = mux(T_5301, T_4759, UInt<1>("h00")) + node T_5664 = mux(T_5303, T_4775, UInt<1>("h00")) + node T_5666 = mux(T_5305, T_4791, UInt<1>("h00")) + node T_5668 = mux(T_5307, T_4807, UInt<1>("h00")) + node T_5670 = mux(T_5309, T_4823, UInt<1>("h00")) + node T_5672 = mux(T_5311, T_4839, UInt<1>("h00")) + node T_5674 = mux(T_5313, T_4855, UInt<1>("h00")) + node T_5676 = mux(T_5315, T_4871, UInt<1>("h00")) + node T_5678 = mux(T_5317, T_5190, UInt<1>("h00")) + node T_5680 = mux(T_5319, T_5197, UInt<1>("h00")) + node T_5682 = mux(T_5321, T_5204, UInt<1>("h00")) + node T_5684 = mux(T_5323, reg_sscratch, UInt<1>("h00")) + node T_5686 = mux(T_5325, reg_scause, UInt<1>("h00")) + node T_5688 = mux(T_5327, T_5209, UInt<1>("h00")) + node T_5690 = mux(T_5329, reg_sptbr, UInt<1>("h00")) + node T_5692 = mux(T_5331, UInt<1>("h00"), UInt<1>("h00")) + node T_5694 = mux(T_5333, T_5215, UInt<1>("h00")) + node T_5696 = mux(T_5335, T_5220, UInt<1>("h00")) + node T_5698 = or(T_5583, T_5585) + node T_5699 = or(T_5698, T_5587) + node T_5700 = or(T_5699, T_5589) + node T_5701 = or(T_5700, T_5591) + node T_5702 = or(T_5701, T_5593) + node T_5703 = or(T_5702, T_5595) + node T_5704 = or(T_5703, T_5597) + node T_5705 = or(T_5704, T_5599) + node T_5706 = or(T_5705, T_5601) + node T_5707 = or(T_5706, T_5603) + node T_5708 = or(T_5707, T_5605) + node T_5709 = or(T_5708, T_5607) + node T_5710 = or(T_5709, T_5609) + node T_5711 = or(T_5710, T_5611) + node T_5712 = or(T_5711, T_5613) + node T_5713 = or(T_5712, T_5615) + node T_5714 = or(T_5713, T_5617) + node T_5715 = or(T_5714, T_5619) + node T_5716 = or(T_5715, T_5621) + node T_5717 = or(T_5716, T_5623) + node T_5718 = or(T_5717, T_5625) + node T_5719 = or(T_5718, T_5627) + node T_5720 = or(T_5719, T_5629) + node T_5721 = or(T_5720, T_5631) + node T_5722 = or(T_5721, T_5633) + node T_5723 = or(T_5722, T_5636) + node T_5724 = or(T_5723, T_5638) + node T_5725 = or(T_5724, T_5640) + node T_5726 = or(T_5725, T_5642) + node T_5727 = or(T_5726, T_5644) + node T_5728 = or(T_5727, T_5646) + node T_5729 = or(T_5728, T_5648) + node T_5730 = or(T_5729, T_5650) + node T_5731 = or(T_5730, T_5652) + node T_5732 = or(T_5731, T_5654) + node T_5733 = or(T_5732, T_5656) + node T_5734 = or(T_5733, T_5658) + node T_5735 = or(T_5734, T_5660) + node T_5736 = or(T_5735, T_5662) + node T_5737 = or(T_5736, T_5664) + node T_5738 = or(T_5737, T_5666) + node T_5739 = or(T_5738, T_5668) + node T_5740 = or(T_5739, T_5670) + node T_5741 = or(T_5740, T_5672) + node T_5742 = or(T_5741, T_5674) + node T_5743 = or(T_5742, T_5676) + node T_5744 = or(T_5743, T_5678) + node T_5745 = or(T_5744, T_5680) + node T_5746 = or(T_5745, T_5682) + node T_5747 = or(T_5746, T_5684) + node T_5748 = or(T_5747, T_5686) + node T_5749 = or(T_5748, T_5688) + node T_5750 = or(T_5749, T_5690) + node T_5751 = or(T_5750, T_5692) + node T_5752 = or(T_5751, T_5694) + node T_5753 = or(T_5752, T_5696) + wire T_5754 : UInt<64> + T_5754 is invalid + T_5754 <= T_5753 + io.rw.rdata <= T_5754 io.fcsr_rm <= reg_frm when io.fcsr_flags.valid : - node T_5752 = or(reg_fflags, io.fcsr_flags.bits) - reg_fflags <= T_5752 + node T_5755 = or(reg_fflags, io.fcsr_flags.bits) + reg_fflags <= T_5755 skip when wen : - when T_5250 : - wire T_5787 : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>} - T_5787.ie <= UInt<1>("h00") - T_5787.prv <= UInt<1>("h00") - T_5787.ie1 <= UInt<1>("h00") - T_5787.prv1 <= UInt<1>("h00") - T_5787.ie2 <= UInt<1>("h00") - T_5787.prv2 <= UInt<1>("h00") - T_5787.ie3 <= UInt<1>("h00") - T_5787.prv3 <= UInt<1>("h00") - T_5787.fs <= UInt<1>("h00") - T_5787.xs <= UInt<1>("h00") - T_5787.mprv <= UInt<1>("h00") - T_5787.vm <= UInt<1>("h00") - T_5787.zero1 <= UInt<1>("h00") - T_5787.sd_rv32 <= UInt<1>("h00") - T_5787.zero2 <= UInt<1>("h00") - T_5787.sd <= UInt<1>("h00") - node T_5820 = bits(wdata, 0, 0) - T_5787.ie <= T_5820 - node T_5821 = bits(wdata, 2, 1) - T_5787.prv <= T_5821 - node T_5822 = bits(wdata, 3, 3) - T_5787.ie1 <= T_5822 - node T_5823 = bits(wdata, 5, 4) - T_5787.prv1 <= T_5823 - node T_5824 = bits(wdata, 6, 6) - T_5787.ie2 <= T_5824 - node T_5825 = bits(wdata, 8, 7) - T_5787.prv2 <= T_5825 - node T_5826 = bits(wdata, 9, 9) - T_5787.ie3 <= T_5826 - node T_5827 = bits(wdata, 11, 10) - T_5787.prv3 <= T_5827 - node T_5828 = bits(wdata, 13, 12) - T_5787.fs <= T_5828 - node T_5829 = bits(wdata, 15, 14) - T_5787.xs <= T_5829 - node T_5830 = bits(wdata, 16, 16) - T_5787.mprv <= T_5830 - node T_5831 = bits(wdata, 21, 17) - T_5787.vm <= T_5831 - node T_5832 = bits(wdata, 30, 22) - T_5787.zero1 <= T_5832 - node T_5833 = bits(wdata, 31, 31) - T_5787.sd_rv32 <= T_5833 - node T_5834 = bits(wdata, 62, 32) - T_5787.zero2 <= T_5834 - node T_5835 = bits(wdata, 63, 63) - T_5787.sd <= T_5835 - reg_mstatus.ie <= T_5787.ie - reg_mstatus.ie1 <= T_5787.ie1 - wire T_5840 : UInt<2>[3] - T_5840[0] <= UInt<2>("h03") - T_5840[1] <= UInt<1>("h00") - T_5840[2] <= UInt<1>("h01") - reg_mstatus.mprv <= T_5787.mprv - node T_5845 = eq(T_5840[0], T_5787.prv) - node T_5846 = eq(T_5840[1], T_5787.prv) - node T_5847 = eq(T_5840[2], T_5787.prv) - node T_5849 = or(UInt<1>("h00"), T_5845) - node T_5850 = or(T_5849, T_5846) - node T_5851 = or(T_5850, T_5847) - when T_5851 : - reg_mstatus.prv <= T_5787.prv + when T_5247 : + wire T_5790 : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>} + T_5790 is invalid + node T_5807 = bits(wdata, 0, 0) + T_5790.ie <= T_5807 + node T_5808 = bits(wdata, 2, 1) + T_5790.prv <= T_5808 + node T_5809 = bits(wdata, 3, 3) + T_5790.ie1 <= T_5809 + node T_5810 = bits(wdata, 5, 4) + T_5790.prv1 <= T_5810 + node T_5811 = bits(wdata, 6, 6) + T_5790.ie2 <= T_5811 + node T_5812 = bits(wdata, 8, 7) + T_5790.prv2 <= T_5812 + node T_5813 = bits(wdata, 9, 9) + T_5790.ie3 <= T_5813 + node T_5814 = bits(wdata, 11, 10) + T_5790.prv3 <= T_5814 + node T_5815 = bits(wdata, 13, 12) + T_5790.fs <= T_5815 + node T_5816 = bits(wdata, 15, 14) + T_5790.xs <= T_5816 + node T_5817 = bits(wdata, 16, 16) + T_5790.mprv <= T_5817 + node T_5818 = bits(wdata, 21, 17) + T_5790.vm <= T_5818 + node T_5819 = bits(wdata, 30, 22) + T_5790.zero1 <= T_5819 + node T_5820 = bits(wdata, 31, 31) + T_5790.sd_rv32 <= T_5820 + node T_5821 = bits(wdata, 62, 32) + T_5790.zero2 <= T_5821 + node T_5822 = bits(wdata, 63, 63) + T_5790.sd <= T_5822 + reg_mstatus.ie <= T_5790.ie + reg_mstatus.ie1 <= T_5790.ie1 + wire T_5827 : UInt<2>[3] + T_5827[0] <= UInt<2>("h03") + T_5827[1] <= UInt<1>("h00") + T_5827[2] <= UInt<1>("h01") + reg_mstatus.mprv <= T_5790.mprv + node T_5832 = eq(T_5827[0], T_5790.prv) + node T_5833 = eq(T_5827[1], T_5790.prv) + node T_5834 = eq(T_5827[2], T_5790.prv) + node T_5836 = or(UInt<1>("h00"), T_5832) + node T_5837 = or(T_5836, T_5833) + node T_5838 = or(T_5837, T_5834) + when T_5838 : + reg_mstatus.prv <= T_5790.prv skip - node T_5852 = eq(T_5840[0], T_5787.prv1) - node T_5853 = eq(T_5840[1], T_5787.prv1) - node T_5854 = eq(T_5840[2], T_5787.prv1) - node T_5856 = or(UInt<1>("h00"), T_5852) - node T_5857 = or(T_5856, T_5853) - node T_5858 = or(T_5857, T_5854) - when T_5858 : - reg_mstatus.prv1 <= T_5787.prv1 + node T_5839 = eq(T_5827[0], T_5790.prv1) + node T_5840 = eq(T_5827[1], T_5790.prv1) + node T_5841 = eq(T_5827[2], T_5790.prv1) + node T_5843 = or(UInt<1>("h00"), T_5839) + node T_5844 = or(T_5843, T_5840) + node T_5845 = or(T_5844, T_5841) + when T_5845 : + reg_mstatus.prv1 <= T_5790.prv1 skip - node T_5859 = eq(T_5840[0], T_5787.prv2) - node T_5860 = eq(T_5840[1], T_5787.prv2) - node T_5861 = eq(T_5840[2], T_5787.prv2) - node T_5863 = or(UInt<1>("h00"), T_5859) - node T_5864 = or(T_5863, T_5860) - node T_5865 = or(T_5864, T_5861) - when T_5865 : - reg_mstatus.prv2 <= T_5787.prv2 + node T_5846 = eq(T_5827[0], T_5790.prv2) + node T_5847 = eq(T_5827[1], T_5790.prv2) + node T_5848 = eq(T_5827[2], T_5790.prv2) + node T_5850 = or(UInt<1>("h00"), T_5846) + node T_5851 = or(T_5850, T_5847) + node T_5852 = or(T_5851, T_5848) + when T_5852 : + reg_mstatus.prv2 <= T_5790.prv2 skip - reg_mstatus.ie2 <= T_5787.ie2 - node T_5867 = eq(T_5787.vm, UInt<1>("h00")) - when T_5867 : + reg_mstatus.ie2 <= T_5790.ie2 + node T_5854 = eq(T_5790.vm, UInt<1>("h00")) + when T_5854 : reg_mstatus.vm <= UInt<1>("h00") skip - node T_5870 = eq(T_5787.vm, UInt<4>("h09")) - when T_5870 : + node T_5857 = eq(T_5790.vm, UInt<4>("h09")) + when T_5857 : reg_mstatus.vm <= UInt<4>("h09") skip - reg_mstatus.fs <= T_5787.fs - skip - when T_5262 : - wire T_5890 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5890.usip <= UInt<1>("h00") - T_5890.ssip <= UInt<1>("h00") - T_5890.hsip <= UInt<1>("h00") - T_5890.msip <= UInt<1>("h00") - T_5890.utip <= UInt<1>("h00") - T_5890.stip <= UInt<1>("h00") - T_5890.htip <= UInt<1>("h00") - T_5890.mtip <= UInt<1>("h00") - node T_5907 = bits(wdata, 0, 0) - T_5890.usip <= T_5907 - node T_5908 = bits(wdata, 1, 1) - T_5890.ssip <= T_5908 - node T_5909 = bits(wdata, 2, 2) - T_5890.hsip <= T_5909 - node T_5910 = bits(wdata, 3, 3) - T_5890.msip <= T_5910 - node T_5911 = bits(wdata, 4, 4) - T_5890.utip <= T_5911 - node T_5912 = bits(wdata, 5, 5) - T_5890.stip <= T_5912 - node T_5913 = bits(wdata, 6, 6) - T_5890.htip <= T_5913 - node T_5914 = bits(wdata, 7, 7) - T_5890.mtip <= T_5914 - reg_mip.ssip <= T_5890.ssip - reg_mip.stip <= T_5890.stip - reg_mip.msip <= T_5890.msip - skip - when T_5260 : - node T_5915 = bit(wdata, 0) - reg_mip.msip <= T_5915 - skip - when T_5264 : - wire T_5934 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_5934.usip <= UInt<1>("h00") - T_5934.ssip <= UInt<1>("h00") - T_5934.hsip <= UInt<1>("h00") - T_5934.msip <= UInt<1>("h00") - T_5934.utip <= UInt<1>("h00") - T_5934.stip <= UInt<1>("h00") - T_5934.htip <= UInt<1>("h00") - T_5934.mtip <= UInt<1>("h00") - node T_5951 = bits(wdata, 0, 0) - T_5934.usip <= T_5951 - node T_5952 = bits(wdata, 1, 1) - T_5934.ssip <= T_5952 - node T_5953 = bits(wdata, 2, 2) - T_5934.hsip <= T_5953 - node T_5954 = bits(wdata, 3, 3) - T_5934.msip <= T_5954 - node T_5955 = bits(wdata, 4, 4) - T_5934.utip <= T_5955 - node T_5956 = bits(wdata, 5, 5) - T_5934.stip <= T_5956 - node T_5957 = bits(wdata, 6, 6) - T_5934.htip <= T_5957 - node T_5958 = bits(wdata, 7, 7) - T_5934.mtip <= T_5958 - reg_mie.ssip <= T_5934.ssip - reg_mie.stip <= T_5934.stip - reg_mie.msip <= T_5934.msip - reg_mie.mtip <= T_5934.mtip - skip - when T_5226 : + reg_mstatus.fs <= T_5790.fs + skip + when T_5259 : + wire T_5877 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_5877 is invalid + node T_5886 = bits(wdata, 0, 0) + T_5877.usip <= T_5886 + node T_5887 = bits(wdata, 1, 1) + T_5877.ssip <= T_5887 + node T_5888 = bits(wdata, 2, 2) + T_5877.hsip <= T_5888 + node T_5889 = bits(wdata, 3, 3) + T_5877.msip <= T_5889 + node T_5890 = bits(wdata, 4, 4) + T_5877.utip <= T_5890 + node T_5891 = bits(wdata, 5, 5) + T_5877.stip <= T_5891 + node T_5892 = bits(wdata, 6, 6) + T_5877.htip <= T_5892 + node T_5893 = bits(wdata, 7, 7) + T_5877.mtip <= T_5893 + reg_mip.ssip <= T_5877.ssip + reg_mip.stip <= T_5877.stip + reg_mip.msip <= T_5877.msip + skip + when T_5257 : + node T_5894 = bits(wdata, 0, 0) + reg_mip.msip <= T_5894 + skip + when T_5261 : + wire T_5913 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_5913 is invalid + node T_5922 = bits(wdata, 0, 0) + T_5913.usip <= T_5922 + node T_5923 = bits(wdata, 1, 1) + T_5913.ssip <= T_5923 + node T_5924 = bits(wdata, 2, 2) + T_5913.hsip <= T_5924 + node T_5925 = bits(wdata, 3, 3) + T_5913.msip <= T_5925 + node T_5926 = bits(wdata, 4, 4) + T_5913.utip <= T_5926 + node T_5927 = bits(wdata, 5, 5) + T_5913.stip <= T_5927 + node T_5928 = bits(wdata, 6, 6) + T_5913.htip <= T_5928 + node T_5929 = bits(wdata, 7, 7) + T_5913.mtip <= T_5929 + reg_mie.ssip <= T_5913.ssip + reg_mie.stip <= T_5913.stip + reg_mie.msip <= T_5913.msip + reg_mie.mtip <= T_5913.mtip + skip + when T_5223 : reg_fflags <= wdata skip - when T_5228 : + when T_5225 : reg_frm <= wdata skip - when T_5230 : + when T_5227 : reg_fflags <= wdata - node T_5959 = shr(wdata, 5) - reg_frm <= T_5959 + node T_5930 = shr(wdata, 5) + reg_frm <= T_5930 skip - when T_5268 : - node T_5960 = not(wdata) - node T_5962 = or(T_5960, UInt<2>("h03")) - node T_5963 = not(T_5962) - reg_mepc <= T_5963 + when T_5265 : + node T_5931 = not(wdata) + node T_5933 = or(T_5931, UInt<2>("h03")) + node T_5934 = not(T_5933) + reg_mepc <= T_5934 skip - when T_5266 : + when T_5263 : reg_mscratch <= wdata skip - when T_5272 : - node T_5965 = and(wdata, UInt<64>("h0800000000000001f")) - reg_mcause <= T_5965 + when T_5269 : + node T_5936 = and(wdata, UInt<64>("h0800000000000001f")) + reg_mcause <= T_5936 skip - when T_5270 : - node T_5966 = bits(wdata, 39, 0) - reg_mbadaddr <= T_5966 + when T_5267 : + node T_5937 = bits(wdata, 39, 0) + reg_mbadaddr <= T_5937 skip - when T_5286 : - node T_5967 = bits(wdata, 5, 0) - T_4600 <= T_5967 - node T_5968 = bits(wdata, 63, 6) - T_4607 <= T_5968 + when T_5283 : + node T_5938 = bits(wdata, 5, 0) + T_4584 <= T_5938 + node T_5939 = bits(wdata, 63, 6) + T_4592 <= T_5939 skip - when T_5274 : + when T_5271 : reg_mtimecmp <= wdata reg_mip.mtip <= UInt<1>("h00") skip - when T_5244 : + when T_5241 : reg_time <= wdata skip - when T_5282 : - node T_5971 = eq(reg_fromhost, UInt<1>("h00")) - node T_5973 = eq(host_csr_req_fire, UInt<1>("h00")) - node T_5974 = or(T_5971, T_5973) - when T_5974 : + when T_5279 : + node T_5942 = eq(reg_fromhost, UInt<1>("h00")) + node T_5944 = eq(host_csr_req_fire, UInt<1>("h00")) + node T_5945 = or(T_5942, T_5944) + when T_5945 : reg_fromhost <= wdata skip skip - when T_5280 : - node T_5976 = eq(reg_tohost, UInt<1>("h00")) - node T_5977 = or(T_5976, host_csr_req_fire) - when T_5977 : + when T_5277 : + node T_5947 = eq(reg_tohost, UInt<1>("h00")) + node T_5948 = or(T_5947, host_csr_req_fire) + when T_5948 : reg_tohost <= wdata skip skip - when T_5278 : - node T_5978 = bit(wdata, 0) - reg_stats <= T_5978 - skip - when T_5320 : - wire T_6005 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} - T_6005.ie <= UInt<1>("h00") - T_6005.zero1 <= UInt<1>("h00") - T_6005.pie <= UInt<1>("h00") - T_6005.ps <= UInt<1>("h00") - T_6005.zero2 <= UInt<1>("h00") - T_6005.fs <= UInt<1>("h00") - T_6005.xs <= UInt<1>("h00") - T_6005.mprv <= UInt<1>("h00") - T_6005.zero3 <= UInt<1>("h00") - T_6005.sd_rv32 <= UInt<1>("h00") - T_6005.zero4 <= UInt<1>("h00") - T_6005.sd <= UInt<1>("h00") - node T_6030 = bits(wdata, 0, 0) - T_6005.ie <= T_6030 - node T_6031 = bits(wdata, 2, 1) - T_6005.zero1 <= T_6031 - node T_6032 = bits(wdata, 3, 3) - T_6005.pie <= T_6032 - node T_6033 = bits(wdata, 4, 4) - T_6005.ps <= T_6033 - node T_6034 = bits(wdata, 11, 5) - T_6005.zero2 <= T_6034 - node T_6035 = bits(wdata, 13, 12) - T_6005.fs <= T_6035 - node T_6036 = bits(wdata, 15, 14) - T_6005.xs <= T_6036 - node T_6037 = bits(wdata, 16, 16) - T_6005.mprv <= T_6037 - node T_6038 = bits(wdata, 30, 17) - T_6005.zero3 <= T_6038 - node T_6039 = bits(wdata, 31, 31) - T_6005.sd_rv32 <= T_6039 - node T_6040 = bits(wdata, 62, 32) - T_6005.zero4 <= T_6040 - node T_6041 = bits(wdata, 63, 63) - T_6005.sd <= T_6041 - reg_mstatus.ie <= T_6005.ie - reg_mstatus.ie1 <= T_6005.pie - node T_6044 = mux(T_6005.ps, UInt<1>("h01"), UInt<1>("h00")) - reg_mstatus.prv1 <= T_6044 - reg_mstatus.mprv <= T_6005.mprv - reg_mstatus.fs <= T_6005.fs - skip - when T_5322 : - wire T_6063 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_6063.usip <= UInt<1>("h00") - T_6063.ssip <= UInt<1>("h00") - T_6063.hsip <= UInt<1>("h00") - T_6063.msip <= UInt<1>("h00") - T_6063.utip <= UInt<1>("h00") - T_6063.stip <= UInt<1>("h00") - T_6063.htip <= UInt<1>("h00") - T_6063.mtip <= UInt<1>("h00") - node T_6080 = bits(wdata, 0, 0) - T_6063.usip <= T_6080 - node T_6081 = bits(wdata, 1, 1) - T_6063.ssip <= T_6081 - node T_6082 = bits(wdata, 2, 2) - T_6063.hsip <= T_6082 - node T_6083 = bits(wdata, 3, 3) - T_6063.msip <= T_6083 - node T_6084 = bits(wdata, 4, 4) - T_6063.utip <= T_6084 - node T_6085 = bits(wdata, 5, 5) - T_6063.stip <= T_6085 - node T_6086 = bits(wdata, 6, 6) - T_6063.htip <= T_6086 - node T_6087 = bits(wdata, 7, 7) - T_6063.mtip <= T_6087 - reg_mip.ssip <= T_6063.ssip - skip - when T_5324 : - wire T_6106 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} - T_6106.usip <= UInt<1>("h00") - T_6106.ssip <= UInt<1>("h00") - T_6106.hsip <= UInt<1>("h00") - T_6106.msip <= UInt<1>("h00") - T_6106.utip <= UInt<1>("h00") - T_6106.stip <= UInt<1>("h00") - T_6106.htip <= UInt<1>("h00") - T_6106.mtip <= UInt<1>("h00") - node T_6123 = bits(wdata, 0, 0) - T_6106.usip <= T_6123 - node T_6124 = bits(wdata, 1, 1) - T_6106.ssip <= T_6124 - node T_6125 = bits(wdata, 2, 2) - T_6106.hsip <= T_6125 - node T_6126 = bits(wdata, 3, 3) - T_6106.msip <= T_6126 - node T_6127 = bits(wdata, 4, 4) - T_6106.utip <= T_6127 - node T_6128 = bits(wdata, 5, 5) - T_6106.stip <= T_6128 - node T_6129 = bits(wdata, 6, 6) - T_6106.htip <= T_6129 - node T_6130 = bits(wdata, 7, 7) - T_6106.mtip <= T_6130 - reg_mie.ssip <= T_6106.ssip - reg_mie.stip <= T_6106.stip - skip - when T_5326 : + when T_5275 : + node T_5949 = bits(wdata, 0, 0) + reg_stats <= T_5949 + skip + when T_5317 : + wire T_5976 : {sd : UInt<1>, zero4 : UInt<31>, sd_rv32 : UInt<1>, zero3 : UInt<14>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, zero2 : UInt<7>, ps : UInt<1>, pie : UInt<1>, zero1 : UInt<2>, ie : UInt<1>} + T_5976 is invalid + node T_5989 = bits(wdata, 0, 0) + T_5976.ie <= T_5989 + node T_5990 = bits(wdata, 2, 1) + T_5976.zero1 <= T_5990 + node T_5991 = bits(wdata, 3, 3) + T_5976.pie <= T_5991 + node T_5992 = bits(wdata, 4, 4) + T_5976.ps <= T_5992 + node T_5993 = bits(wdata, 11, 5) + T_5976.zero2 <= T_5993 + node T_5994 = bits(wdata, 13, 12) + T_5976.fs <= T_5994 + node T_5995 = bits(wdata, 15, 14) + T_5976.xs <= T_5995 + node T_5996 = bits(wdata, 16, 16) + T_5976.mprv <= T_5996 + node T_5997 = bits(wdata, 30, 17) + T_5976.zero3 <= T_5997 + node T_5998 = bits(wdata, 31, 31) + T_5976.sd_rv32 <= T_5998 + node T_5999 = bits(wdata, 62, 32) + T_5976.zero4 <= T_5999 + node T_6000 = bits(wdata, 63, 63) + T_5976.sd <= T_6000 + reg_mstatus.ie <= T_5976.ie + reg_mstatus.ie1 <= T_5976.pie + node T_6003 = mux(T_5976.ps, UInt<1>("h01"), UInt<1>("h00")) + reg_mstatus.prv1 <= T_6003 + reg_mstatus.mprv <= T_5976.mprv + reg_mstatus.fs <= T_5976.fs + skip + when T_5319 : + wire T_6022 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_6022 is invalid + node T_6031 = bits(wdata, 0, 0) + T_6022.usip <= T_6031 + node T_6032 = bits(wdata, 1, 1) + T_6022.ssip <= T_6032 + node T_6033 = bits(wdata, 2, 2) + T_6022.hsip <= T_6033 + node T_6034 = bits(wdata, 3, 3) + T_6022.msip <= T_6034 + node T_6035 = bits(wdata, 4, 4) + T_6022.utip <= T_6035 + node T_6036 = bits(wdata, 5, 5) + T_6022.stip <= T_6036 + node T_6037 = bits(wdata, 6, 6) + T_6022.htip <= T_6037 + node T_6038 = bits(wdata, 7, 7) + T_6022.mtip <= T_6038 + reg_mip.ssip <= T_6022.ssip + skip + when T_5321 : + wire T_6057 : {mtip : UInt<1>, htip : UInt<1>, stip : UInt<1>, utip : UInt<1>, msip : UInt<1>, hsip : UInt<1>, ssip : UInt<1>, usip : UInt<1>} + T_6057 is invalid + node T_6066 = bits(wdata, 0, 0) + T_6057.usip <= T_6066 + node T_6067 = bits(wdata, 1, 1) + T_6057.ssip <= T_6067 + node T_6068 = bits(wdata, 2, 2) + T_6057.hsip <= T_6068 + node T_6069 = bits(wdata, 3, 3) + T_6057.msip <= T_6069 + node T_6070 = bits(wdata, 4, 4) + T_6057.utip <= T_6070 + node T_6071 = bits(wdata, 5, 5) + T_6057.stip <= T_6071 + node T_6072 = bits(wdata, 6, 6) + T_6057.htip <= T_6072 + node T_6073 = bits(wdata, 7, 7) + T_6057.mtip <= T_6073 + reg_mie.ssip <= T_6057.ssip + reg_mie.stip <= T_6057.stip + skip + when T_5323 : reg_sscratch <= wdata skip - when T_5332 : - node T_6131 = bits(wdata, 31, 12) - node T_6133 = cat(T_6131, UInt<12>("h00")) - reg_sptbr <= T_6133 + when T_5329 : + node T_6074 = bits(wdata, 31, 12) + node T_6076 = cat(T_6074, UInt<12>("h00")) + reg_sptbr <= T_6076 skip - when T_5336 : - node T_6134 = not(wdata) - node T_6136 = or(T_6134, UInt<2>("h03")) - node T_6137 = not(T_6136) - reg_sepc <= T_6137 + when T_5333 : + node T_6077 = not(wdata) + node T_6079 = or(T_6077, UInt<2>("h03")) + node T_6080 = not(T_6079) + reg_sepc <= T_6080 skip - when T_5338 : - node T_6138 = not(wdata) - node T_6140 = or(T_6138, UInt<2>("h03")) - node T_6141 = not(T_6140) - reg_stvec <= T_6141 + when T_5335 : + node T_6081 = not(wdata) + node T_6083 = or(T_6081, UInt<2>("h03")) + node T_6084 = not(T_6083) + reg_stvec <= T_6084 skip skip when reset : @@ -22023,216 +15697,218 @@ circuit Top : input reset : UInt<1> output io : {flip dw : UInt<1>, flip fn : UInt<4>, flip in2 : UInt<64>, flip in1 : UInt<64>, out : UInt<64>, adder_out : UInt<64>, cmp_out : UInt<1>} - io.cmp_out <= UInt<1>("h00") - io.adder_out <= UInt<1>("h00") - io.out <= UInt<1>("h00") - node T_11 = bit(io.fn, 3) + io is invalid + node T_11 = bits(io.fn, 3, 3) node T_12 = not(io.in2) node in2_inv = mux(T_11, T_12, io.in2) node in1_xor_in2 = xor(io.in1, in2_inv) - node T_15 = addw(io.in1, in2_inv) - node T_16 = bit(io.fn, 3) - node T_17 = addw(T_15, T_16) - io.adder_out <= T_17 - node T_18 = bit(io.fn, 0) - node T_19 = bit(io.fn, 3) - node T_21 = eq(T_19, UInt<1>("h00")) - node T_23 = eq(in1_xor_in2, UInt<1>("h00")) - node T_24 = bit(io.in1, 63) - node T_25 = bit(io.in2, 63) - node T_26 = eq(T_24, T_25) - node T_27 = bit(io.adder_out, 63) - node T_28 = bit(io.fn, 1) - node T_29 = bit(io.in2, 63) - node T_30 = bit(io.in1, 63) - node T_31 = mux(T_28, T_29, T_30) - node T_32 = mux(T_26, T_27, T_31) - node T_33 = mux(T_21, T_23, T_32) - node T_34 = xor(T_18, T_33) - io.cmp_out <= T_34 - node T_35 = bit(io.fn, 3) - node T_36 = bit(io.in1, 31) - node T_37 = and(T_35, T_36) - node T_39 = subw(UInt<32>("h00"), T_37) - node T_42 = and(io.dw, UInt<1>("h01")) - node T_43 = eq(UInt<1>("h01"), T_42) - node T_44 = bits(io.in1, 63, 32) - node T_45 = mux(T_43, T_44, T_39) - node T_46 = bit(io.in2, 5) - node T_49 = and(io.dw, UInt<1>("h01")) - node T_50 = eq(UInt<1>("h01"), T_49) - node T_51 = and(T_46, T_50) - node T_52 = bits(io.in2, 4, 0) - node shamt = cat(T_51, T_52) - node T_54 = bits(io.in1, 31, 0) - node shin_r = cat(T_45, T_54) - node T_56 = eq(io.fn, UInt<3>("h05")) - node T_57 = eq(io.fn, UInt<4>("h0b")) - node T_58 = or(T_56, T_57) - node T_61 = shl(UInt<32>("h0ffffffff"), 32) - node T_62 = xor(UInt<64>("h0ffffffffffffffff"), T_61) - node T_63 = shr(shin_r, 32) - node T_64 = and(T_63, T_62) - node T_65 = bits(shin_r, 31, 0) - node T_66 = shl(T_65, 32) - node T_67 = not(T_62) - node T_68 = and(T_66, T_67) - node T_69 = or(T_64, T_68) - node T_70 = bits(T_62, 47, 0) - node T_71 = shl(T_70, 16) - node T_72 = xor(T_62, T_71) - node T_73 = shr(T_69, 16) - node T_74 = and(T_73, T_72) - node T_75 = bits(T_69, 47, 0) - node T_76 = shl(T_75, 16) - node T_77 = not(T_72) - node T_78 = and(T_76, T_77) - node T_79 = or(T_74, T_78) - node T_80 = bits(T_72, 55, 0) - node T_81 = shl(T_80, 8) - node T_82 = xor(T_72, T_81) - node T_83 = shr(T_79, 8) - node T_84 = and(T_83, T_82) - node T_85 = bits(T_79, 55, 0) - node T_86 = shl(T_85, 8) - node T_87 = not(T_82) - node T_88 = and(T_86, T_87) - node T_89 = or(T_84, T_88) - node T_90 = bits(T_82, 59, 0) - node T_91 = shl(T_90, 4) - node T_92 = xor(T_82, T_91) - node T_93 = shr(T_89, 4) - node T_94 = and(T_93, T_92) - node T_95 = bits(T_89, 59, 0) - node T_96 = shl(T_95, 4) - node T_97 = not(T_92) - node T_98 = and(T_96, T_97) - node T_99 = or(T_94, T_98) - node T_100 = bits(T_92, 61, 0) - node T_101 = shl(T_100, 2) - node T_102 = xor(T_92, T_101) - node T_103 = shr(T_99, 2) - node T_104 = and(T_103, T_102) - node T_105 = bits(T_99, 61, 0) - node T_106 = shl(T_105, 2) - node T_107 = not(T_102) - node T_108 = and(T_106, T_107) - node T_109 = or(T_104, T_108) - node T_110 = bits(T_102, 62, 0) - node T_111 = shl(T_110, 1) - node T_112 = xor(T_102, T_111) - node T_113 = shr(T_109, 1) - node T_114 = and(T_113, T_112) - node T_115 = bits(T_109, 62, 0) - node T_116 = shl(T_115, 1) - node T_117 = not(T_112) - node T_118 = and(T_116, T_117) - node T_119 = or(T_114, T_118) - node shin = mux(T_58, shin_r, T_119) - node T_121 = bit(io.fn, 3) - node T_122 = bit(shin, 63) - node T_123 = and(T_121, T_122) - node T_124 = cat(T_123, shin) - node T_125 = asSInt(T_124) - node T_126 = dshr(T_125, shamt) - node shout_r = bits(T_126, 63, 0) - node T_130 = shl(UInt<32>("h0ffffffff"), 32) - node T_131 = xor(UInt<64>("h0ffffffffffffffff"), T_130) - node T_132 = shr(shout_r, 32) - node T_133 = and(T_132, T_131) - node T_134 = bits(shout_r, 31, 0) - node T_135 = shl(T_134, 32) - node T_136 = not(T_131) - node T_137 = and(T_135, T_136) - node T_138 = or(T_133, T_137) - node T_139 = bits(T_131, 47, 0) - node T_140 = shl(T_139, 16) - node T_141 = xor(T_131, T_140) - node T_142 = shr(T_138, 16) - node T_143 = and(T_142, T_141) - node T_144 = bits(T_138, 47, 0) - node T_145 = shl(T_144, 16) - node T_146 = not(T_141) - node T_147 = and(T_145, T_146) - node T_148 = or(T_143, T_147) - node T_149 = bits(T_141, 55, 0) - node T_150 = shl(T_149, 8) - node T_151 = xor(T_141, T_150) - node T_152 = shr(T_148, 8) - node T_153 = and(T_152, T_151) - node T_154 = bits(T_148, 55, 0) - node T_155 = shl(T_154, 8) - node T_156 = not(T_151) - node T_157 = and(T_155, T_156) - node T_158 = or(T_153, T_157) - node T_159 = bits(T_151, 59, 0) - node T_160 = shl(T_159, 4) - node T_161 = xor(T_151, T_160) - node T_162 = shr(T_158, 4) - node T_163 = and(T_162, T_161) - node T_164 = bits(T_158, 59, 0) - node T_165 = shl(T_164, 4) - node T_166 = not(T_161) - node T_167 = and(T_165, T_166) - node T_168 = or(T_163, T_167) - node T_169 = bits(T_161, 61, 0) - node T_170 = shl(T_169, 2) - node T_171 = xor(T_161, T_170) - node T_172 = shr(T_168, 2) - node T_173 = and(T_172, T_171) - node T_174 = bits(T_168, 61, 0) - node T_175 = shl(T_174, 2) - node T_176 = not(T_171) - node T_177 = and(T_175, T_176) - node T_178 = or(T_173, T_177) - node T_179 = bits(T_171, 62, 0) - node T_180 = shl(T_179, 1) - node T_181 = xor(T_171, T_180) - node T_182 = shr(T_178, 1) - node T_183 = and(T_182, T_181) - node T_184 = bits(T_178, 62, 0) - node T_185 = shl(T_184, 1) - node T_186 = not(T_181) - node T_187 = and(T_185, T_186) - node shout_l = or(T_183, T_187) - node T_189 = eq(io.fn, UInt<3>("h05")) - node T_190 = eq(io.fn, UInt<4>("h0b")) - node T_191 = or(T_189, T_190) - node T_193 = mux(T_191, shout_r, UInt<1>("h00")) - node T_194 = eq(io.fn, UInt<1>("h01")) - node T_196 = mux(T_194, shout_l, UInt<1>("h00")) - node shout = or(T_193, T_196) - node T_198 = eq(io.fn, UInt<3>("h04")) - node T_199 = eq(io.fn, UInt<3>("h06")) - node T_200 = or(T_198, T_199) - node T_202 = mux(T_200, in1_xor_in2, UInt<1>("h00")) - node T_203 = eq(io.fn, UInt<3>("h06")) - node T_204 = eq(io.fn, UInt<3>("h07")) - node T_205 = or(T_203, T_204) - node T_206 = and(io.in1, io.in2) - node T_208 = mux(T_205, T_206, UInt<1>("h00")) - node logic = or(T_202, T_208) - node T_210 = eq(io.fn, UInt<2>("h02")) - node T_211 = eq(io.fn, UInt<2>("h03")) - node T_212 = or(T_210, T_211) - node T_213 = geq(io.fn, UInt<4>("h0c")) - node T_214 = or(T_212, T_213) - node T_215 = and(T_214, io.cmp_out) - node T_216 = or(T_215, logic) - node shift_logic = or(T_216, shout) - node T_218 = eq(io.fn, UInt<1>("h00")) - node T_219 = eq(io.fn, UInt<4>("h0a")) - node T_220 = or(T_218, T_219) - node out = mux(T_220, io.adder_out, shift_logic) + node T_15 = add(io.in1, in2_inv) + node T_16 = tail(T_15, 1) + node T_17 = bits(io.fn, 3, 3) + node T_18 = add(T_16, T_17) + node T_19 = tail(T_18, 1) + io.adder_out <= T_19 + node T_20 = bits(io.fn, 0, 0) + node T_21 = bits(io.fn, 3, 3) + node T_23 = eq(T_21, UInt<1>("h00")) + node T_25 = eq(in1_xor_in2, UInt<1>("h00")) + node T_26 = bits(io.in1, 63, 63) + node T_27 = bits(io.in2, 63, 63) + node T_28 = eq(T_26, T_27) + node T_29 = bits(io.adder_out, 63, 63) + node T_30 = bits(io.fn, 1, 1) + node T_31 = bits(io.in2, 63, 63) + node T_32 = bits(io.in1, 63, 63) + node T_33 = mux(T_30, T_31, T_32) + node T_34 = mux(T_28, T_29, T_33) + node T_35 = mux(T_23, T_25, T_34) + node T_36 = xor(T_20, T_35) + io.cmp_out <= T_36 + node T_37 = bits(io.fn, 3, 3) + node T_38 = bits(io.in1, 31, 31) + node T_39 = and(T_37, T_38) + node T_41 = sub(UInt<32>("h00"), T_39) + node T_42 = tail(T_41, 1) + node T_45 = and(io.dw, UInt<1>("h01")) + node T_46 = eq(UInt<1>("h01"), T_45) + node T_47 = bits(io.in1, 63, 32) + node T_48 = mux(T_46, T_47, T_42) + node T_49 = bits(io.in2, 5, 5) + node T_52 = and(io.dw, UInt<1>("h01")) + node T_53 = eq(UInt<1>("h01"), T_52) + node T_54 = and(T_49, T_53) + node T_55 = bits(io.in2, 4, 0) + node shamt = cat(T_54, T_55) + node T_57 = bits(io.in1, 31, 0) + node shin_r = cat(T_48, T_57) + node T_59 = eq(io.fn, UInt<3>("h05")) + node T_60 = eq(io.fn, UInt<4>("h0b")) + node T_61 = or(T_59, T_60) + node T_64 = shl(UInt<32>("h0ffffffff"), 32) + node T_65 = xor(UInt<64>("h0ffffffffffffffff"), T_64) + node T_66 = shr(shin_r, 32) + node T_67 = and(T_66, T_65) + node T_68 = bits(shin_r, 31, 0) + node T_69 = shl(T_68, 32) + node T_70 = not(T_65) + node T_71 = and(T_69, T_70) + node T_72 = or(T_67, T_71) + node T_73 = bits(T_65, 47, 0) + node T_74 = shl(T_73, 16) + node T_75 = xor(T_65, T_74) + node T_76 = shr(T_72, 16) + node T_77 = and(T_76, T_75) + node T_78 = bits(T_72, 47, 0) + node T_79 = shl(T_78, 16) + node T_80 = not(T_75) + node T_81 = and(T_79, T_80) + node T_82 = or(T_77, T_81) + node T_83 = bits(T_75, 55, 0) + node T_84 = shl(T_83, 8) + node T_85 = xor(T_75, T_84) + node T_86 = shr(T_82, 8) + node T_87 = and(T_86, T_85) + node T_88 = bits(T_82, 55, 0) + node T_89 = shl(T_88, 8) + node T_90 = not(T_85) + node T_91 = and(T_89, T_90) + node T_92 = or(T_87, T_91) + node T_93 = bits(T_85, 59, 0) + node T_94 = shl(T_93, 4) + node T_95 = xor(T_85, T_94) + node T_96 = shr(T_92, 4) + node T_97 = and(T_96, T_95) + node T_98 = bits(T_92, 59, 0) + node T_99 = shl(T_98, 4) + node T_100 = not(T_95) + node T_101 = and(T_99, T_100) + node T_102 = or(T_97, T_101) + node T_103 = bits(T_95, 61, 0) + node T_104 = shl(T_103, 2) + node T_105 = xor(T_95, T_104) + node T_106 = shr(T_102, 2) + node T_107 = and(T_106, T_105) + node T_108 = bits(T_102, 61, 0) + node T_109 = shl(T_108, 2) + node T_110 = not(T_105) + node T_111 = and(T_109, T_110) + node T_112 = or(T_107, T_111) + node T_113 = bits(T_105, 62, 0) + node T_114 = shl(T_113, 1) + node T_115 = xor(T_105, T_114) + node T_116 = shr(T_112, 1) + node T_117 = and(T_116, T_115) + node T_118 = bits(T_112, 62, 0) + node T_119 = shl(T_118, 1) + node T_120 = not(T_115) + node T_121 = and(T_119, T_120) + node T_122 = or(T_117, T_121) + node shin = mux(T_61, shin_r, T_122) + node T_124 = bits(io.fn, 3, 3) + node T_125 = bits(shin, 63, 63) + node T_126 = and(T_124, T_125) + node T_127 = cat(T_126, shin) + node T_128 = asSInt(T_127) + node T_129 = dshr(T_128, shamt) + node shout_r = bits(T_129, 63, 0) + node T_133 = shl(UInt<32>("h0ffffffff"), 32) + node T_134 = xor(UInt<64>("h0ffffffffffffffff"), T_133) + node T_135 = shr(shout_r, 32) + node T_136 = and(T_135, T_134) + node T_137 = bits(shout_r, 31, 0) + node T_138 = shl(T_137, 32) + node T_139 = not(T_134) + node T_140 = and(T_138, T_139) + node T_141 = or(T_136, T_140) + node T_142 = bits(T_134, 47, 0) + node T_143 = shl(T_142, 16) + node T_144 = xor(T_134, T_143) + node T_145 = shr(T_141, 16) + node T_146 = and(T_145, T_144) + node T_147 = bits(T_141, 47, 0) + node T_148 = shl(T_147, 16) + node T_149 = not(T_144) + node T_150 = and(T_148, T_149) + node T_151 = or(T_146, T_150) + node T_152 = bits(T_144, 55, 0) + node T_153 = shl(T_152, 8) + node T_154 = xor(T_144, T_153) + node T_155 = shr(T_151, 8) + node T_156 = and(T_155, T_154) + node T_157 = bits(T_151, 55, 0) + node T_158 = shl(T_157, 8) + node T_159 = not(T_154) + node T_160 = and(T_158, T_159) + node T_161 = or(T_156, T_160) + node T_162 = bits(T_154, 59, 0) + node T_163 = shl(T_162, 4) + node T_164 = xor(T_154, T_163) + node T_165 = shr(T_161, 4) + node T_166 = and(T_165, T_164) + node T_167 = bits(T_161, 59, 0) + node T_168 = shl(T_167, 4) + node T_169 = not(T_164) + node T_170 = and(T_168, T_169) + node T_171 = or(T_166, T_170) + node T_172 = bits(T_164, 61, 0) + node T_173 = shl(T_172, 2) + node T_174 = xor(T_164, T_173) + node T_175 = shr(T_171, 2) + node T_176 = and(T_175, T_174) + node T_177 = bits(T_171, 61, 0) + node T_178 = shl(T_177, 2) + node T_179 = not(T_174) + node T_180 = and(T_178, T_179) + node T_181 = or(T_176, T_180) + node T_182 = bits(T_174, 62, 0) + node T_183 = shl(T_182, 1) + node T_184 = xor(T_174, T_183) + node T_185 = shr(T_181, 1) + node T_186 = and(T_185, T_184) + node T_187 = bits(T_181, 62, 0) + node T_188 = shl(T_187, 1) + node T_189 = not(T_184) + node T_190 = and(T_188, T_189) + node shout_l = or(T_186, T_190) + node T_192 = eq(io.fn, UInt<3>("h05")) + node T_193 = eq(io.fn, UInt<4>("h0b")) + node T_194 = or(T_192, T_193) + node T_196 = mux(T_194, shout_r, UInt<1>("h00")) + node T_197 = eq(io.fn, UInt<1>("h01")) + node T_199 = mux(T_197, shout_l, UInt<1>("h00")) + node shout = or(T_196, T_199) + node T_201 = eq(io.fn, UInt<3>("h04")) + node T_202 = eq(io.fn, UInt<3>("h06")) + node T_203 = or(T_201, T_202) + node T_205 = mux(T_203, in1_xor_in2, UInt<1>("h00")) + node T_206 = eq(io.fn, UInt<3>("h06")) + node T_207 = eq(io.fn, UInt<3>("h07")) + node T_208 = or(T_206, T_207) + node T_209 = and(io.in1, io.in2) + node T_211 = mux(T_208, T_209, UInt<1>("h00")) + node logic = or(T_205, T_211) + node T_213 = eq(io.fn, UInt<2>("h02")) + node T_214 = eq(io.fn, UInt<2>("h03")) + node T_215 = or(T_213, T_214) + node T_216 = geq(io.fn, UInt<4>("h0c")) + node T_217 = or(T_215, T_216) + node T_218 = and(T_217, io.cmp_out) + node T_219 = or(T_218, logic) + node shift_logic = or(T_219, shout) + node T_221 = eq(io.fn, UInt<1>("h00")) + node T_222 = eq(io.fn, UInt<4>("h0a")) + node T_223 = or(T_221, T_222) + node out = mux(T_223, io.adder_out, shift_logic) io.out <= out - node T_224 = and(io.dw, UInt<1>("h01")) - node T_225 = eq(UInt<1>("h00"), T_224) - when T_225 : - node T_226 = bit(out, 31) - node T_228 = subw(UInt<32>("h00"), T_226) - node T_229 = bits(out, 31, 0) - node T_230 = cat(T_228, T_229) - io.out <= T_230 + node T_227 = and(io.dw, UInt<1>("h01")) + node T_228 = eq(UInt<1>("h00"), T_227) + when T_228 : + node T_229 = bits(out, 31, 31) + node T_231 = sub(UInt<32>("h00"), T_229) + node T_232 = tail(T_231, 1) + node T_233 = bits(out, 31, 0) + node T_234 = cat(T_232, T_233) + io.out <= T_234 skip module MulDiv : @@ -22240,18 +15916,15 @@ circuit Top : input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}} - io.resp.bits.tag <= UInt<1>("h00") - io.resp.bits.data <= UInt<1>("h00") - io.resp.valid <= UInt<1>("h00") - io.req.ready <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") - reg req : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clk, UInt<1>("h00"), req - reg count : UInt<7>, clk, UInt<1>("h00"), count - reg neg_out : UInt<1>, clk, UInt<1>("h00"), neg_out - reg isMul : UInt<1>, clk, UInt<1>("h00"), isMul - reg isHi : UInt<1>, clk, UInt<1>("h00"), isHi - reg divisor : UInt<65>, clk, UInt<1>("h00"), divisor - reg remainder : UInt<130>, clk, UInt<1>("h00"), remainder + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + reg req : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clk + reg count : UInt<7>, clk + reg neg_out : UInt<1>, clk + reg isMul : UInt<1>, clk + reg isHi : UInt<1>, clk + reg divisor : UInt<65>, clk + reg remainder : UInt<130>, clk node T_81 = and(io.req.bits.fn, UInt<4>("h04")) node T_83 = eq(T_81, UInt<4>("h00")) node T_85 = and(io.req.bits.fn, UInt<4>("h08")) @@ -22274,1812 +15947,1456 @@ circuit Top : node T_114 = or(T_113, T_110) node T_116 = or(UInt<1>("h00"), T_106) node T_117 = or(T_116, T_83) - node cmdMul = bit(T_90, 0) - node cmdHi = bit(T_102, 0) - node lhsSigned = bit(T_114, 0) - node rhsSigned = bit(T_117, 0) + node cmdMul = bits(T_90, 0, 0) + node cmdHi = bits(T_102, 0, 0) + node lhsSigned = bits(T_114, 0, 0) + node rhsSigned = bits(T_117, 0, 0) node T_124 = and(io.req.bits.dw, UInt<1>("h01")) node T_125 = eq(UInt<1>("h01"), T_124) - node T_126 = bit(io.req.bits.in1, 63) - node T_127 = bit(io.req.bits.in1, 31) + node T_126 = bits(io.req.bits.in1, 63, 63) + node T_127 = bits(io.req.bits.in1, 31, 31) node T_128 = mux(T_125, T_126, T_127) node lhs_sign = and(lhsSigned, T_128) node T_132 = and(io.req.bits.dw, UInt<1>("h01")) node T_133 = eq(UInt<1>("h01"), T_132) node T_134 = bits(io.req.bits.in1, 63, 32) - node T_136 = subw(UInt<32>("h00"), lhs_sign) - node T_137 = mux(T_133, T_134, T_136) - node T_138 = bits(io.req.bits.in1, 31, 0) - node lhs_in = cat(T_137, T_138) - node T_142 = and(io.req.bits.dw, UInt<1>("h01")) - node T_143 = eq(UInt<1>("h01"), T_142) - node T_144 = bit(io.req.bits.in2, 63) - node T_145 = bit(io.req.bits.in2, 31) - node T_146 = mux(T_143, T_144, T_145) - node rhs_sign = and(rhsSigned, T_146) - node T_150 = and(io.req.bits.dw, UInt<1>("h01")) - node T_151 = eq(UInt<1>("h01"), T_150) - node T_152 = bits(io.req.bits.in2, 63, 32) - node T_154 = subw(UInt<32>("h00"), rhs_sign) - node T_155 = mux(T_151, T_152, T_154) - node T_156 = bits(io.req.bits.in2, 31, 0) - node rhs_in = cat(T_155, T_156) - node T_158 = bits(remainder, 128, 64) - node T_159 = bits(divisor, 64, 0) - node subtractor = subw(T_158, T_159) - node less = bit(subtractor, 64) - node T_162 = bits(remainder, 63, 0) - node negated_remainder = subw(UInt<1>("h00"), T_162) - node T_165 = eq(state, UInt<1>("h01")) - when T_165 : - node T_166 = bit(remainder, 63) - node T_167 = or(T_166, isMul) - when T_167 : + node T_136 = sub(UInt<32>("h00"), lhs_sign) + node T_137 = tail(T_136, 1) + node T_138 = mux(T_133, T_134, T_137) + node T_139 = bits(io.req.bits.in1, 31, 0) + node lhs_in = cat(T_138, T_139) + node T_143 = and(io.req.bits.dw, UInt<1>("h01")) + node T_144 = eq(UInt<1>("h01"), T_143) + node T_145 = bits(io.req.bits.in2, 63, 63) + node T_146 = bits(io.req.bits.in2, 31, 31) + node T_147 = mux(T_144, T_145, T_146) + node rhs_sign = and(rhsSigned, T_147) + node T_151 = and(io.req.bits.dw, UInt<1>("h01")) + node T_152 = eq(UInt<1>("h01"), T_151) + node T_153 = bits(io.req.bits.in2, 63, 32) + node T_155 = sub(UInt<32>("h00"), rhs_sign) + node T_156 = tail(T_155, 1) + node T_157 = mux(T_152, T_153, T_156) + node T_158 = bits(io.req.bits.in2, 31, 0) + node rhs_in = cat(T_157, T_158) + node T_160 = bits(remainder, 128, 64) + node T_161 = bits(divisor, 64, 0) + node T_162 = sub(T_160, T_161) + node subtractor = tail(T_162, 1) + node less = bits(subtractor, 64, 64) + node T_165 = bits(remainder, 63, 0) + node T_167 = sub(UInt<1>("h00"), T_165) + node negated_remainder = tail(T_167, 1) + node T_169 = eq(state, UInt<1>("h01")) + when T_169 : + node T_170 = bits(remainder, 63, 63) + node T_171 = or(T_170, isMul) + when T_171 : remainder <= negated_remainder skip - node T_168 = bit(divisor, 63) - node T_169 = or(T_168, isMul) - when T_169 : + node T_172 = bits(divisor, 63, 63) + node T_173 = or(T_172, isMul) + when T_173 : divisor <= subtractor skip state <= UInt<2>("h02") skip - node T_170 = eq(state, UInt<3>("h04")) - when T_170 : + node T_174 = eq(state, UInt<3>("h04")) + when T_174 : remainder <= negated_remainder state <= UInt<3>("h05") skip - node T_171 = eq(state, UInt<2>("h03")) - when T_171 : - node T_172 = bits(remainder, 128, 65) - remainder <= T_172 - node T_173 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) - state <= T_173 - skip - node T_174 = eq(state, UInt<2>("h02")) - node T_175 = and(T_174, isMul) + node T_175 = eq(state, UInt<2>("h03")) when T_175 : - node T_176 = bits(remainder, 129, 65) - node T_177 = bits(remainder, 63, 0) - node T_178 = cat(T_176, T_177) - node T_179 = bits(T_178, 63, 0) - node T_180 = bits(T_178, 128, 64) - node T_181 = asSInt(T_180) - node T_182 = asSInt(divisor) - node T_183 = bits(T_179, 7, 0) - node T_184 = mul(T_182, T_183) - node T_185 = addw(T_184, T_181) - node T_186 = bits(T_179, 63, 8) - node T_187 = asUInt(T_185) - node T_188 = cat(T_187, T_186) - node T_191 = mul(count, UInt<4>("h08")) - node T_192 = bits(T_191, 5, 0) - node T_193 = dshr(asSInt(UInt<65>("h010000000000000000")), T_192) - node T_194 = bits(T_193, 63, 0) - node T_197 = neq(count, UInt<3>("h07")) - node T_198 = and(UInt<1>("h01"), T_197) - node T_200 = neq(count, UInt<1>("h00")) - node T_201 = and(T_198, T_200) - node T_203 = eq(isHi, UInt<1>("h00")) - node T_204 = and(T_201, T_203) - node T_205 = not(T_194) - node T_206 = and(T_179, T_205) - node T_208 = eq(T_206, UInt<1>("h00")) - node T_209 = and(T_204, T_208) - node T_212 = mul(count, UInt<4>("h08")) - node T_213 = subw(UInt<7>("h040"), T_212) - node T_214 = bits(T_213, 5, 0) - node T_215 = dshr(T_178, T_214) - node T_216 = bits(T_188, 128, 64) - node T_217 = mux(T_209, T_215, T_188) - node T_218 = bits(T_217, 63, 0) - node T_219 = cat(T_216, T_218) - node T_220 = shr(T_219, 64) - node T_222 = bits(T_219, 63, 0) - node T_223 = cat(UInt<1>("h00"), T_222) - node T_224 = cat(T_220, T_223) - remainder <= T_224 - node T_226 = addw(count, UInt<1>("h01")) - count <= T_226 - node T_228 = eq(count, UInt<3>("h07")) - node T_229 = or(T_209, T_228) - when T_229 : - node T_230 = mux(isHi, UInt<2>("h03"), UInt<3>("h05")) - state <= T_230 - skip - skip - node T_231 = eq(state, UInt<2>("h02")) - node T_233 = eq(isMul, UInt<1>("h00")) - node T_234 = and(T_231, T_233) - when T_234 : - node T_236 = eq(count, UInt<7>("h040")) - when T_236 : - node T_237 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) - node T_238 = mux(isHi, UInt<2>("h03"), T_237) + node T_176 = bits(remainder, 128, 65) + remainder <= T_176 + node T_177 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) + state <= T_177 + skip + node T_178 = eq(state, UInt<2>("h02")) + node T_179 = and(T_178, isMul) + when T_179 : + node T_180 = bits(remainder, 129, 65) + node T_181 = bits(remainder, 63, 0) + node T_182 = cat(T_180, T_181) + node T_183 = bits(T_182, 63, 0) + node T_184 = bits(T_182, 128, 64) + node T_185 = asSInt(T_184) + node T_186 = asSInt(divisor) + node T_187 = bits(T_183, 7, 0) + node T_188 = mul(T_186, T_187) + node T_189 = add(T_188, T_185) + node T_190 = tail(T_189, 1) + node T_191 = asSInt(T_190) + node T_192 = bits(T_183, 63, 8) + node T_193 = asUInt(T_191) + node T_194 = cat(T_193, T_192) + node T_197 = mul(count, UInt<4>("h08")) + node T_198 = bits(T_197, 5, 0) + node T_199 = dshr(asSInt(UInt<65>("h010000000000000000")), T_198) + node T_200 = bits(T_199, 63, 0) + node T_203 = neq(count, UInt<3>("h07")) + node T_204 = and(UInt<1>("h01"), T_203) + node T_206 = neq(count, UInt<1>("h00")) + node T_207 = and(T_204, T_206) + node T_209 = eq(isHi, UInt<1>("h00")) + node T_210 = and(T_207, T_209) + node T_211 = not(T_200) + node T_212 = and(T_183, T_211) + node T_214 = eq(T_212, UInt<1>("h00")) + node T_215 = and(T_210, T_214) + node T_218 = mul(count, UInt<4>("h08")) + node T_219 = sub(UInt<7>("h040"), T_218) + node T_220 = tail(T_219, 1) + node T_221 = bits(T_220, 5, 0) + node T_222 = dshr(T_182, T_221) + node T_223 = bits(T_194, 128, 64) + node T_224 = mux(T_215, T_222, T_194) + node T_225 = bits(T_224, 63, 0) + node T_226 = cat(T_223, T_225) + node T_227 = shr(T_226, 64) + node T_229 = bits(T_226, 63, 0) + node T_230 = cat(UInt<1>("h00"), T_229) + node T_231 = cat(T_227, T_230) + remainder <= T_231 + node T_233 = add(count, UInt<1>("h01")) + node T_234 = tail(T_233, 1) + count <= T_234 + node T_236 = eq(count, UInt<3>("h07")) + node T_237 = or(T_215, T_236) + when T_237 : + node T_238 = mux(isHi, UInt<2>("h03"), UInt<3>("h05")) state <= T_238 skip - node T_240 = addw(count, UInt<1>("h01")) - count <= T_240 - node T_241 = bits(remainder, 127, 64) - node T_242 = bits(subtractor, 63, 0) - node T_243 = mux(less, T_241, T_242) - node T_244 = bits(remainder, 63, 0) - node T_246 = eq(less, UInt<1>("h00")) - node T_247 = cat(T_244, T_246) - node T_248 = cat(T_243, T_247) - remainder <= T_248 - node T_249 = bits(divisor, 63, 0) - node T_250 = bit(T_249, 63) - node T_252 = bit(T_249, 62) - node T_254 = bit(T_249, 61) - node T_256 = bit(T_249, 60) - node T_258 = bit(T_249, 59) - node T_260 = bit(T_249, 58) - node T_262 = bit(T_249, 57) - node T_264 = bit(T_249, 56) - node T_266 = bit(T_249, 55) - node T_268 = bit(T_249, 54) - node T_270 = bit(T_249, 53) - node T_272 = bit(T_249, 52) - node T_274 = bit(T_249, 51) - node T_276 = bit(T_249, 50) - node T_278 = bit(T_249, 49) - node T_280 = bit(T_249, 48) - node T_282 = bit(T_249, 47) - node T_284 = bit(T_249, 46) - node T_286 = bit(T_249, 45) - node T_288 = bit(T_249, 44) - node T_290 = bit(T_249, 43) - node T_292 = bit(T_249, 42) - node T_294 = bit(T_249, 41) - node T_296 = bit(T_249, 40) - node T_298 = bit(T_249, 39) - node T_300 = bit(T_249, 38) - node T_302 = bit(T_249, 37) - node T_304 = bit(T_249, 36) - node T_306 = bit(T_249, 35) - node T_308 = bit(T_249, 34) - node T_310 = bit(T_249, 33) - node T_312 = bit(T_249, 32) - node T_314 = bit(T_249, 31) - node T_316 = bit(T_249, 30) - node T_318 = bit(T_249, 29) - node T_320 = bit(T_249, 28) - node T_322 = bit(T_249, 27) - node T_324 = bit(T_249, 26) - node T_326 = bit(T_249, 25) - node T_328 = bit(T_249, 24) - node T_330 = bit(T_249, 23) - node T_332 = bit(T_249, 22) - node T_334 = bit(T_249, 21) - node T_336 = bit(T_249, 20) - node T_338 = bit(T_249, 19) - node T_340 = bit(T_249, 18) - node T_342 = bit(T_249, 17) - node T_344 = bit(T_249, 16) - node T_346 = bit(T_249, 15) - node T_348 = bit(T_249, 14) - node T_350 = bit(T_249, 13) - node T_352 = bit(T_249, 12) - node T_354 = bit(T_249, 11) - node T_356 = bit(T_249, 10) - node T_358 = bit(T_249, 9) - node T_360 = bit(T_249, 8) - node T_362 = bit(T_249, 7) - node T_364 = bit(T_249, 6) - node T_366 = bit(T_249, 5) - node T_368 = bit(T_249, 4) - node T_370 = bit(T_249, 3) - node T_372 = bit(T_249, 2) - node T_374 = bit(T_249, 1) - node T_375 = shl(T_374, 0) - node T_376 = mux(T_372, UInt<2>("h02"), T_375) - node T_377 = mux(T_370, UInt<2>("h03"), T_376) - node T_378 = mux(T_368, UInt<3>("h04"), T_377) - node T_379 = mux(T_366, UInt<3>("h05"), T_378) - node T_380 = mux(T_364, UInt<3>("h06"), T_379) - node T_381 = mux(T_362, UInt<3>("h07"), T_380) - node T_382 = mux(T_360, UInt<4>("h08"), T_381) - node T_383 = mux(T_358, UInt<4>("h09"), T_382) - node T_384 = mux(T_356, UInt<4>("h0a"), T_383) - node T_385 = mux(T_354, UInt<4>("h0b"), T_384) - node T_386 = mux(T_352, UInt<4>("h0c"), T_385) - node T_387 = mux(T_350, UInt<4>("h0d"), T_386) - node T_388 = mux(T_348, UInt<4>("h0e"), T_387) - node T_389 = mux(T_346, UInt<4>("h0f"), T_388) - node T_390 = mux(T_344, UInt<5>("h010"), T_389) - node T_391 = mux(T_342, UInt<5>("h011"), T_390) - node T_392 = mux(T_340, UInt<5>("h012"), T_391) - node T_393 = mux(T_338, UInt<5>("h013"), T_392) - node T_394 = mux(T_336, UInt<5>("h014"), T_393) - node T_395 = mux(T_334, UInt<5>("h015"), T_394) - node T_396 = mux(T_332, UInt<5>("h016"), T_395) - node T_397 = mux(T_330, UInt<5>("h017"), T_396) - node T_398 = mux(T_328, UInt<5>("h018"), T_397) - node T_399 = mux(T_326, UInt<5>("h019"), T_398) - node T_400 = mux(T_324, UInt<5>("h01a"), T_399) - node T_401 = mux(T_322, UInt<5>("h01b"), T_400) - node T_402 = mux(T_320, UInt<5>("h01c"), T_401) - node T_403 = mux(T_318, UInt<5>("h01d"), T_402) - node T_404 = mux(T_316, UInt<5>("h01e"), T_403) - node T_405 = mux(T_314, UInt<5>("h01f"), T_404) - node T_406 = mux(T_312, UInt<6>("h020"), T_405) - node T_407 = mux(T_310, UInt<6>("h021"), T_406) - node T_408 = mux(T_308, UInt<6>("h022"), T_407) - node T_409 = mux(T_306, UInt<6>("h023"), T_408) - node T_410 = mux(T_304, UInt<6>("h024"), T_409) - node T_411 = mux(T_302, UInt<6>("h025"), T_410) - node T_412 = mux(T_300, UInt<6>("h026"), T_411) - node T_413 = mux(T_298, UInt<6>("h027"), T_412) - node T_414 = mux(T_296, UInt<6>("h028"), T_413) - node T_415 = mux(T_294, UInt<6>("h029"), T_414) - node T_416 = mux(T_292, UInt<6>("h02a"), T_415) - node T_417 = mux(T_290, UInt<6>("h02b"), T_416) - node T_418 = mux(T_288, UInt<6>("h02c"), T_417) - node T_419 = mux(T_286, UInt<6>("h02d"), T_418) - node T_420 = mux(T_284, UInt<6>("h02e"), T_419) - node T_421 = mux(T_282, UInt<6>("h02f"), T_420) - node T_422 = mux(T_280, UInt<6>("h030"), T_421) - node T_423 = mux(T_278, UInt<6>("h031"), T_422) - node T_424 = mux(T_276, UInt<6>("h032"), T_423) - node T_425 = mux(T_274, UInt<6>("h033"), T_424) - node T_426 = mux(T_272, UInt<6>("h034"), T_425) - node T_427 = mux(T_270, UInt<6>("h035"), T_426) - node T_428 = mux(T_268, UInt<6>("h036"), T_427) - node T_429 = mux(T_266, UInt<6>("h037"), T_428) - node T_430 = mux(T_264, UInt<6>("h038"), T_429) - node T_431 = mux(T_262, UInt<6>("h039"), T_430) - node T_432 = mux(T_260, UInt<6>("h03a"), T_431) - node T_433 = mux(T_258, UInt<6>("h03b"), T_432) - node T_434 = mux(T_256, UInt<6>("h03c"), T_433) - node T_435 = mux(T_254, UInt<6>("h03d"), T_434) - node T_436 = mux(T_252, UInt<6>("h03e"), T_435) - node T_437 = mux(T_250, UInt<6>("h03f"), T_436) - node T_438 = bits(remainder, 63, 0) - node T_439 = bit(T_438, 63) - node T_441 = bit(T_438, 62) - node T_443 = bit(T_438, 61) - node T_445 = bit(T_438, 60) - node T_447 = bit(T_438, 59) - node T_449 = bit(T_438, 58) - node T_451 = bit(T_438, 57) - node T_453 = bit(T_438, 56) - node T_455 = bit(T_438, 55) - node T_457 = bit(T_438, 54) - node T_459 = bit(T_438, 53) - node T_461 = bit(T_438, 52) - node T_463 = bit(T_438, 51) - node T_465 = bit(T_438, 50) - node T_467 = bit(T_438, 49) - node T_469 = bit(T_438, 48) - node T_471 = bit(T_438, 47) - node T_473 = bit(T_438, 46) - node T_475 = bit(T_438, 45) - node T_477 = bit(T_438, 44) - node T_479 = bit(T_438, 43) - node T_481 = bit(T_438, 42) - node T_483 = bit(T_438, 41) - node T_485 = bit(T_438, 40) - node T_487 = bit(T_438, 39) - node T_489 = bit(T_438, 38) - node T_491 = bit(T_438, 37) - node T_493 = bit(T_438, 36) - node T_495 = bit(T_438, 35) - node T_497 = bit(T_438, 34) - node T_499 = bit(T_438, 33) - node T_501 = bit(T_438, 32) - node T_503 = bit(T_438, 31) - node T_505 = bit(T_438, 30) - node T_507 = bit(T_438, 29) - node T_509 = bit(T_438, 28) - node T_511 = bit(T_438, 27) - node T_513 = bit(T_438, 26) - node T_515 = bit(T_438, 25) - node T_517 = bit(T_438, 24) - node T_519 = bit(T_438, 23) - node T_521 = bit(T_438, 22) - node T_523 = bit(T_438, 21) - node T_525 = bit(T_438, 20) - node T_527 = bit(T_438, 19) - node T_529 = bit(T_438, 18) - node T_531 = bit(T_438, 17) - node T_533 = bit(T_438, 16) - node T_535 = bit(T_438, 15) - node T_537 = bit(T_438, 14) - node T_539 = bit(T_438, 13) - node T_541 = bit(T_438, 12) - node T_543 = bit(T_438, 11) - node T_545 = bit(T_438, 10) - node T_547 = bit(T_438, 9) - node T_549 = bit(T_438, 8) - node T_551 = bit(T_438, 7) - node T_553 = bit(T_438, 6) - node T_555 = bit(T_438, 5) - node T_557 = bit(T_438, 4) - node T_559 = bit(T_438, 3) - node T_561 = bit(T_438, 2) - node T_563 = bit(T_438, 1) - node T_564 = shl(T_563, 0) - node T_565 = mux(T_561, UInt<2>("h02"), T_564) - node T_566 = mux(T_559, UInt<2>("h03"), T_565) - node T_567 = mux(T_557, UInt<3>("h04"), T_566) - node T_568 = mux(T_555, UInt<3>("h05"), T_567) - node T_569 = mux(T_553, UInt<3>("h06"), T_568) - node T_570 = mux(T_551, UInt<3>("h07"), T_569) - node T_571 = mux(T_549, UInt<4>("h08"), T_570) - node T_572 = mux(T_547, UInt<4>("h09"), T_571) - node T_573 = mux(T_545, UInt<4>("h0a"), T_572) - node T_574 = mux(T_543, UInt<4>("h0b"), T_573) - node T_575 = mux(T_541, UInt<4>("h0c"), T_574) - node T_576 = mux(T_539, UInt<4>("h0d"), T_575) - node T_577 = mux(T_537, UInt<4>("h0e"), T_576) - node T_578 = mux(T_535, UInt<4>("h0f"), T_577) - node T_579 = mux(T_533, UInt<5>("h010"), T_578) - node T_580 = mux(T_531, UInt<5>("h011"), T_579) - node T_581 = mux(T_529, UInt<5>("h012"), T_580) - node T_582 = mux(T_527, UInt<5>("h013"), T_581) - node T_583 = mux(T_525, UInt<5>("h014"), T_582) - node T_584 = mux(T_523, UInt<5>("h015"), T_583) - node T_585 = mux(T_521, UInt<5>("h016"), T_584) - node T_586 = mux(T_519, UInt<5>("h017"), T_585) - node T_587 = mux(T_517, UInt<5>("h018"), T_586) - node T_588 = mux(T_515, UInt<5>("h019"), T_587) - node T_589 = mux(T_513, UInt<5>("h01a"), T_588) - node T_590 = mux(T_511, UInt<5>("h01b"), T_589) - node T_591 = mux(T_509, UInt<5>("h01c"), T_590) - node T_592 = mux(T_507, UInt<5>("h01d"), T_591) - node T_593 = mux(T_505, UInt<5>("h01e"), T_592) - node T_594 = mux(T_503, UInt<5>("h01f"), T_593) - node T_595 = mux(T_501, UInt<6>("h020"), T_594) - node T_596 = mux(T_499, UInt<6>("h021"), T_595) - node T_597 = mux(T_497, UInt<6>("h022"), T_596) - node T_598 = mux(T_495, UInt<6>("h023"), T_597) - node T_599 = mux(T_493, UInt<6>("h024"), T_598) - node T_600 = mux(T_491, UInt<6>("h025"), T_599) - node T_601 = mux(T_489, UInt<6>("h026"), T_600) - node T_602 = mux(T_487, UInt<6>("h027"), T_601) - node T_603 = mux(T_485, UInt<6>("h028"), T_602) - node T_604 = mux(T_483, UInt<6>("h029"), T_603) - node T_605 = mux(T_481, UInt<6>("h02a"), T_604) - node T_606 = mux(T_479, UInt<6>("h02b"), T_605) - node T_607 = mux(T_477, UInt<6>("h02c"), T_606) - node T_608 = mux(T_475, UInt<6>("h02d"), T_607) - node T_609 = mux(T_473, UInt<6>("h02e"), T_608) - node T_610 = mux(T_471, UInt<6>("h02f"), T_609) - node T_611 = mux(T_469, UInt<6>("h030"), T_610) - node T_612 = mux(T_467, UInt<6>("h031"), T_611) - node T_613 = mux(T_465, UInt<6>("h032"), T_612) - node T_614 = mux(T_463, UInt<6>("h033"), T_613) - node T_615 = mux(T_461, UInt<6>("h034"), T_614) - node T_616 = mux(T_459, UInt<6>("h035"), T_615) - node T_617 = mux(T_457, UInt<6>("h036"), T_616) - node T_618 = mux(T_455, UInt<6>("h037"), T_617) - node T_619 = mux(T_453, UInt<6>("h038"), T_618) - node T_620 = mux(T_451, UInt<6>("h039"), T_619) - node T_621 = mux(T_449, UInt<6>("h03a"), T_620) - node T_622 = mux(T_447, UInt<6>("h03b"), T_621) - node T_623 = mux(T_445, UInt<6>("h03c"), T_622) - node T_624 = mux(T_443, UInt<6>("h03d"), T_623) - node T_625 = mux(T_441, UInt<6>("h03e"), T_624) - node T_626 = mux(T_439, UInt<6>("h03f"), T_625) - node T_628 = addw(UInt<6>("h03f"), T_437) - node T_629 = subw(T_628, T_626) - node T_630 = gt(T_437, T_626) - node T_632 = eq(count, UInt<1>("h00")) - node T_633 = and(T_632, less) - node T_635 = gt(T_629, UInt<1>("h00")) - node T_636 = or(T_635, T_630) - node T_637 = and(T_633, T_636) - node T_639 = and(UInt<1>("h01"), T_637) - when T_639 : - node T_641 = bits(T_629, 5, 0) - node T_642 = mux(T_630, UInt<6>("h03f"), T_641) - node T_643 = bits(remainder, 63, 0) - node T_644 = dshl(T_643, T_642) - remainder <= T_644 - count <= T_642 - skip - node T_646 = eq(count, UInt<1>("h00")) - node T_648 = eq(less, UInt<1>("h00")) - node T_649 = and(T_646, T_648) - node T_651 = eq(isHi, UInt<1>("h00")) - node T_652 = and(T_649, T_651) - when T_652 : + skip + node T_239 = eq(state, UInt<2>("h02")) + node T_241 = eq(isMul, UInt<1>("h00")) + node T_242 = and(T_239, T_241) + when T_242 : + node T_244 = eq(count, UInt<7>("h040")) + when T_244 : + node T_245 = mux(neg_out, UInt<3>("h04"), UInt<3>("h05")) + node T_246 = mux(isHi, UInt<2>("h03"), T_245) + state <= T_246 + skip + node T_248 = add(count, UInt<1>("h01")) + node T_249 = tail(T_248, 1) + count <= T_249 + node T_250 = bits(remainder, 127, 64) + node T_251 = bits(subtractor, 63, 0) + node T_252 = mux(less, T_250, T_251) + node T_253 = bits(remainder, 63, 0) + node T_255 = eq(less, UInt<1>("h00")) + node T_256 = cat(T_253, T_255) + node T_257 = cat(T_252, T_256) + remainder <= T_257 + node T_258 = bits(divisor, 63, 0) + node T_259 = bits(T_258, 63, 63) + node T_261 = bits(T_258, 62, 62) + node T_263 = bits(T_258, 61, 61) + node T_265 = bits(T_258, 60, 60) + node T_267 = bits(T_258, 59, 59) + node T_269 = bits(T_258, 58, 58) + node T_271 = bits(T_258, 57, 57) + node T_273 = bits(T_258, 56, 56) + node T_275 = bits(T_258, 55, 55) + node T_277 = bits(T_258, 54, 54) + node T_279 = bits(T_258, 53, 53) + node T_281 = bits(T_258, 52, 52) + node T_283 = bits(T_258, 51, 51) + node T_285 = bits(T_258, 50, 50) + node T_287 = bits(T_258, 49, 49) + node T_289 = bits(T_258, 48, 48) + node T_291 = bits(T_258, 47, 47) + node T_293 = bits(T_258, 46, 46) + node T_295 = bits(T_258, 45, 45) + node T_297 = bits(T_258, 44, 44) + node T_299 = bits(T_258, 43, 43) + node T_301 = bits(T_258, 42, 42) + node T_303 = bits(T_258, 41, 41) + node T_305 = bits(T_258, 40, 40) + node T_307 = bits(T_258, 39, 39) + node T_309 = bits(T_258, 38, 38) + node T_311 = bits(T_258, 37, 37) + node T_313 = bits(T_258, 36, 36) + node T_315 = bits(T_258, 35, 35) + node T_317 = bits(T_258, 34, 34) + node T_319 = bits(T_258, 33, 33) + node T_321 = bits(T_258, 32, 32) + node T_323 = bits(T_258, 31, 31) + node T_325 = bits(T_258, 30, 30) + node T_327 = bits(T_258, 29, 29) + node T_329 = bits(T_258, 28, 28) + node T_331 = bits(T_258, 27, 27) + node T_333 = bits(T_258, 26, 26) + node T_335 = bits(T_258, 25, 25) + node T_337 = bits(T_258, 24, 24) + node T_339 = bits(T_258, 23, 23) + node T_341 = bits(T_258, 22, 22) + node T_343 = bits(T_258, 21, 21) + node T_345 = bits(T_258, 20, 20) + node T_347 = bits(T_258, 19, 19) + node T_349 = bits(T_258, 18, 18) + node T_351 = bits(T_258, 17, 17) + node T_353 = bits(T_258, 16, 16) + node T_355 = bits(T_258, 15, 15) + node T_357 = bits(T_258, 14, 14) + node T_359 = bits(T_258, 13, 13) + node T_361 = bits(T_258, 12, 12) + node T_363 = bits(T_258, 11, 11) + node T_365 = bits(T_258, 10, 10) + node T_367 = bits(T_258, 9, 9) + node T_369 = bits(T_258, 8, 8) + node T_371 = bits(T_258, 7, 7) + node T_373 = bits(T_258, 6, 6) + node T_375 = bits(T_258, 5, 5) + node T_377 = bits(T_258, 4, 4) + node T_379 = bits(T_258, 3, 3) + node T_381 = bits(T_258, 2, 2) + node T_383 = bits(T_258, 1, 1) + node T_384 = shl(T_383, 0) + node T_385 = mux(T_381, UInt<2>("h02"), T_384) + node T_386 = mux(T_379, UInt<2>("h03"), T_385) + node T_387 = mux(T_377, UInt<3>("h04"), T_386) + node T_388 = mux(T_375, UInt<3>("h05"), T_387) + node T_389 = mux(T_373, UInt<3>("h06"), T_388) + node T_390 = mux(T_371, UInt<3>("h07"), T_389) + node T_391 = mux(T_369, UInt<4>("h08"), T_390) + node T_392 = mux(T_367, UInt<4>("h09"), T_391) + node T_393 = mux(T_365, UInt<4>("h0a"), T_392) + node T_394 = mux(T_363, UInt<4>("h0b"), T_393) + node T_395 = mux(T_361, UInt<4>("h0c"), T_394) + node T_396 = mux(T_359, UInt<4>("h0d"), T_395) + node T_397 = mux(T_357, UInt<4>("h0e"), T_396) + node T_398 = mux(T_355, UInt<4>("h0f"), T_397) + node T_399 = mux(T_353, UInt<5>("h010"), T_398) + node T_400 = mux(T_351, UInt<5>("h011"), T_399) + node T_401 = mux(T_349, UInt<5>("h012"), T_400) + node T_402 = mux(T_347, UInt<5>("h013"), T_401) + node T_403 = mux(T_345, UInt<5>("h014"), T_402) + node T_404 = mux(T_343, UInt<5>("h015"), T_403) + node T_405 = mux(T_341, UInt<5>("h016"), T_404) + node T_406 = mux(T_339, UInt<5>("h017"), T_405) + node T_407 = mux(T_337, UInt<5>("h018"), T_406) + node T_408 = mux(T_335, UInt<5>("h019"), T_407) + node T_409 = mux(T_333, UInt<5>("h01a"), T_408) + node T_410 = mux(T_331, UInt<5>("h01b"), T_409) + node T_411 = mux(T_329, UInt<5>("h01c"), T_410) + node T_412 = mux(T_327, UInt<5>("h01d"), T_411) + node T_413 = mux(T_325, UInt<5>("h01e"), T_412) + node T_414 = mux(T_323, UInt<5>("h01f"), T_413) + node T_415 = mux(T_321, UInt<6>("h020"), T_414) + node T_416 = mux(T_319, UInt<6>("h021"), T_415) + node T_417 = mux(T_317, UInt<6>("h022"), T_416) + node T_418 = mux(T_315, UInt<6>("h023"), T_417) + node T_419 = mux(T_313, UInt<6>("h024"), T_418) + node T_420 = mux(T_311, UInt<6>("h025"), T_419) + node T_421 = mux(T_309, UInt<6>("h026"), T_420) + node T_422 = mux(T_307, UInt<6>("h027"), T_421) + node T_423 = mux(T_305, UInt<6>("h028"), T_422) + node T_424 = mux(T_303, UInt<6>("h029"), T_423) + node T_425 = mux(T_301, UInt<6>("h02a"), T_424) + node T_426 = mux(T_299, UInt<6>("h02b"), T_425) + node T_427 = mux(T_297, UInt<6>("h02c"), T_426) + node T_428 = mux(T_295, UInt<6>("h02d"), T_427) + node T_429 = mux(T_293, UInt<6>("h02e"), T_428) + node T_430 = mux(T_291, UInt<6>("h02f"), T_429) + node T_431 = mux(T_289, UInt<6>("h030"), T_430) + node T_432 = mux(T_287, UInt<6>("h031"), T_431) + node T_433 = mux(T_285, UInt<6>("h032"), T_432) + node T_434 = mux(T_283, UInt<6>("h033"), T_433) + node T_435 = mux(T_281, UInt<6>("h034"), T_434) + node T_436 = mux(T_279, UInt<6>("h035"), T_435) + node T_437 = mux(T_277, UInt<6>("h036"), T_436) + node T_438 = mux(T_275, UInt<6>("h037"), T_437) + node T_439 = mux(T_273, UInt<6>("h038"), T_438) + node T_440 = mux(T_271, UInt<6>("h039"), T_439) + node T_441 = mux(T_269, UInt<6>("h03a"), T_440) + node T_442 = mux(T_267, UInt<6>("h03b"), T_441) + node T_443 = mux(T_265, UInt<6>("h03c"), T_442) + node T_444 = mux(T_263, UInt<6>("h03d"), T_443) + node T_445 = mux(T_261, UInt<6>("h03e"), T_444) + node T_446 = mux(T_259, UInt<6>("h03f"), T_445) + node T_447 = bits(remainder, 63, 0) + node T_448 = bits(T_447, 63, 63) + node T_450 = bits(T_447, 62, 62) + node T_452 = bits(T_447, 61, 61) + node T_454 = bits(T_447, 60, 60) + node T_456 = bits(T_447, 59, 59) + node T_458 = bits(T_447, 58, 58) + node T_460 = bits(T_447, 57, 57) + node T_462 = bits(T_447, 56, 56) + node T_464 = bits(T_447, 55, 55) + node T_466 = bits(T_447, 54, 54) + node T_468 = bits(T_447, 53, 53) + node T_470 = bits(T_447, 52, 52) + node T_472 = bits(T_447, 51, 51) + node T_474 = bits(T_447, 50, 50) + node T_476 = bits(T_447, 49, 49) + node T_478 = bits(T_447, 48, 48) + node T_480 = bits(T_447, 47, 47) + node T_482 = bits(T_447, 46, 46) + node T_484 = bits(T_447, 45, 45) + node T_486 = bits(T_447, 44, 44) + node T_488 = bits(T_447, 43, 43) + node T_490 = bits(T_447, 42, 42) + node T_492 = bits(T_447, 41, 41) + node T_494 = bits(T_447, 40, 40) + node T_496 = bits(T_447, 39, 39) + node T_498 = bits(T_447, 38, 38) + node T_500 = bits(T_447, 37, 37) + node T_502 = bits(T_447, 36, 36) + node T_504 = bits(T_447, 35, 35) + node T_506 = bits(T_447, 34, 34) + node T_508 = bits(T_447, 33, 33) + node T_510 = bits(T_447, 32, 32) + node T_512 = bits(T_447, 31, 31) + node T_514 = bits(T_447, 30, 30) + node T_516 = bits(T_447, 29, 29) + node T_518 = bits(T_447, 28, 28) + node T_520 = bits(T_447, 27, 27) + node T_522 = bits(T_447, 26, 26) + node T_524 = bits(T_447, 25, 25) + node T_526 = bits(T_447, 24, 24) + node T_528 = bits(T_447, 23, 23) + node T_530 = bits(T_447, 22, 22) + node T_532 = bits(T_447, 21, 21) + node T_534 = bits(T_447, 20, 20) + node T_536 = bits(T_447, 19, 19) + node T_538 = bits(T_447, 18, 18) + node T_540 = bits(T_447, 17, 17) + node T_542 = bits(T_447, 16, 16) + node T_544 = bits(T_447, 15, 15) + node T_546 = bits(T_447, 14, 14) + node T_548 = bits(T_447, 13, 13) + node T_550 = bits(T_447, 12, 12) + node T_552 = bits(T_447, 11, 11) + node T_554 = bits(T_447, 10, 10) + node T_556 = bits(T_447, 9, 9) + node T_558 = bits(T_447, 8, 8) + node T_560 = bits(T_447, 7, 7) + node T_562 = bits(T_447, 6, 6) + node T_564 = bits(T_447, 5, 5) + node T_566 = bits(T_447, 4, 4) + node T_568 = bits(T_447, 3, 3) + node T_570 = bits(T_447, 2, 2) + node T_572 = bits(T_447, 1, 1) + node T_573 = shl(T_572, 0) + node T_574 = mux(T_570, UInt<2>("h02"), T_573) + node T_575 = mux(T_568, UInt<2>("h03"), T_574) + node T_576 = mux(T_566, UInt<3>("h04"), T_575) + node T_577 = mux(T_564, UInt<3>("h05"), T_576) + node T_578 = mux(T_562, UInt<3>("h06"), T_577) + node T_579 = mux(T_560, UInt<3>("h07"), T_578) + node T_580 = mux(T_558, UInt<4>("h08"), T_579) + node T_581 = mux(T_556, UInt<4>("h09"), T_580) + node T_582 = mux(T_554, UInt<4>("h0a"), T_581) + node T_583 = mux(T_552, UInt<4>("h0b"), T_582) + node T_584 = mux(T_550, UInt<4>("h0c"), T_583) + node T_585 = mux(T_548, UInt<4>("h0d"), T_584) + node T_586 = mux(T_546, UInt<4>("h0e"), T_585) + node T_587 = mux(T_544, UInt<4>("h0f"), T_586) + node T_588 = mux(T_542, UInt<5>("h010"), T_587) + node T_589 = mux(T_540, UInt<5>("h011"), T_588) + node T_590 = mux(T_538, UInt<5>("h012"), T_589) + node T_591 = mux(T_536, UInt<5>("h013"), T_590) + node T_592 = mux(T_534, UInt<5>("h014"), T_591) + node T_593 = mux(T_532, UInt<5>("h015"), T_592) + node T_594 = mux(T_530, UInt<5>("h016"), T_593) + node T_595 = mux(T_528, UInt<5>("h017"), T_594) + node T_596 = mux(T_526, UInt<5>("h018"), T_595) + node T_597 = mux(T_524, UInt<5>("h019"), T_596) + node T_598 = mux(T_522, UInt<5>("h01a"), T_597) + node T_599 = mux(T_520, UInt<5>("h01b"), T_598) + node T_600 = mux(T_518, UInt<5>("h01c"), T_599) + node T_601 = mux(T_516, UInt<5>("h01d"), T_600) + node T_602 = mux(T_514, UInt<5>("h01e"), T_601) + node T_603 = mux(T_512, UInt<5>("h01f"), T_602) + node T_604 = mux(T_510, UInt<6>("h020"), T_603) + node T_605 = mux(T_508, UInt<6>("h021"), T_604) + node T_606 = mux(T_506, UInt<6>("h022"), T_605) + node T_607 = mux(T_504, UInt<6>("h023"), T_606) + node T_608 = mux(T_502, UInt<6>("h024"), T_607) + node T_609 = mux(T_500, UInt<6>("h025"), T_608) + node T_610 = mux(T_498, UInt<6>("h026"), T_609) + node T_611 = mux(T_496, UInt<6>("h027"), T_610) + node T_612 = mux(T_494, UInt<6>("h028"), T_611) + node T_613 = mux(T_492, UInt<6>("h029"), T_612) + node T_614 = mux(T_490, UInt<6>("h02a"), T_613) + node T_615 = mux(T_488, UInt<6>("h02b"), T_614) + node T_616 = mux(T_486, UInt<6>("h02c"), T_615) + node T_617 = mux(T_484, UInt<6>("h02d"), T_616) + node T_618 = mux(T_482, UInt<6>("h02e"), T_617) + node T_619 = mux(T_480, UInt<6>("h02f"), T_618) + node T_620 = mux(T_478, UInt<6>("h030"), T_619) + node T_621 = mux(T_476, UInt<6>("h031"), T_620) + node T_622 = mux(T_474, UInt<6>("h032"), T_621) + node T_623 = mux(T_472, UInt<6>("h033"), T_622) + node T_624 = mux(T_470, UInt<6>("h034"), T_623) + node T_625 = mux(T_468, UInt<6>("h035"), T_624) + node T_626 = mux(T_466, UInt<6>("h036"), T_625) + node T_627 = mux(T_464, UInt<6>("h037"), T_626) + node T_628 = mux(T_462, UInt<6>("h038"), T_627) + node T_629 = mux(T_460, UInt<6>("h039"), T_628) + node T_630 = mux(T_458, UInt<6>("h03a"), T_629) + node T_631 = mux(T_456, UInt<6>("h03b"), T_630) + node T_632 = mux(T_454, UInt<6>("h03c"), T_631) + node T_633 = mux(T_452, UInt<6>("h03d"), T_632) + node T_634 = mux(T_450, UInt<6>("h03e"), T_633) + node T_635 = mux(T_448, UInt<6>("h03f"), T_634) + node T_637 = add(UInt<6>("h03f"), T_446) + node T_638 = tail(T_637, 1) + node T_639 = sub(T_638, T_635) + node T_640 = tail(T_639, 1) + node T_641 = gt(T_446, T_635) + node T_643 = eq(count, UInt<1>("h00")) + node T_644 = and(T_643, less) + node T_646 = gt(T_640, UInt<1>("h00")) + node T_647 = or(T_646, T_641) + node T_648 = and(T_644, T_647) + node T_650 = and(UInt<1>("h01"), T_648) + when T_650 : + node T_652 = bits(T_640, 5, 0) + node T_653 = mux(T_641, UInt<6>("h03f"), T_652) + node T_654 = bits(remainder, 63, 0) + node T_655 = dshl(T_654, T_653) + remainder <= T_655 + count <= T_653 + skip + node T_657 = eq(count, UInt<1>("h00")) + node T_659 = eq(less, UInt<1>("h00")) + node T_660 = and(T_657, T_659) + node T_662 = eq(isHi, UInt<1>("h00")) + node T_663 = and(T_660, T_662) + when T_663 : neg_out <= UInt<1>("h00") skip skip - node T_654 = and(io.resp.ready, io.resp.valid) - node T_655 = or(T_654, io.kill) - when T_655 : + node T_665 = and(io.resp.ready, io.resp.valid) + node T_666 = or(T_665, io.kill) + when T_666 : state <= UInt<1>("h00") skip - node T_656 = and(io.req.ready, io.req.valid) - when T_656 : - node T_658 = eq(cmdMul, UInt<1>("h00")) - node T_659 = and(rhs_sign, T_658) - node T_660 = or(lhs_sign, T_659) - node T_661 = mux(T_660, UInt<1>("h01"), UInt<2>("h02")) - state <= T_661 + node T_667 = and(io.req.ready, io.req.valid) + when T_667 : + node T_669 = eq(cmdMul, UInt<1>("h00")) + node T_670 = and(rhs_sign, T_669) + node T_671 = or(lhs_sign, T_670) + node T_672 = mux(T_671, UInt<1>("h01"), UInt<2>("h02")) + state <= T_672 isMul <= cmdMul isHi <= cmdHi count <= UInt<1>("h00") - node T_664 = eq(cmdMul, UInt<1>("h00")) - node T_665 = neq(lhs_sign, rhs_sign) - node T_666 = mux(cmdHi, lhs_sign, T_665) - node T_667 = and(T_664, T_666) - neg_out <= T_667 - node T_668 = cat(rhs_sign, rhs_in) - divisor <= T_668 + node T_675 = eq(cmdMul, UInt<1>("h00")) + node T_676 = neq(lhs_sign, rhs_sign) + node T_677 = mux(cmdHi, lhs_sign, T_676) + node T_678 = and(T_675, T_677) + neg_out <= T_678 + node T_679 = cat(rhs_sign, rhs_in) + divisor <= T_679 remainder <= lhs_in req <- io.req.bits skip io.resp.bits <- req - node T_671 = and(req.dw, UInt<1>("h01")) - node T_672 = eq(UInt<1>("h00"), T_671) - node T_673 = bit(remainder, 31) - node T_675 = subw(UInt<32>("h00"), T_673) - node T_676 = bits(remainder, 31, 0) - node T_677 = cat(T_675, T_676) - node T_678 = bits(remainder, 63, 0) - node T_679 = mux(T_672, T_677, T_678) - io.resp.bits.data <= T_679 - node T_680 = eq(state, UInt<3>("h05")) - io.resp.valid <= T_680 - node T_681 = eq(state, UInt<1>("h00")) - io.req.ready <= T_681 + node T_682 = and(req.dw, UInt<1>("h01")) + node T_683 = eq(UInt<1>("h00"), T_682) + node T_684 = bits(remainder, 31, 31) + node T_686 = sub(UInt<32>("h00"), T_684) + node T_687 = tail(T_686, 1) + node T_688 = bits(remainder, 31, 0) + node T_689 = cat(T_687, T_688) + node T_690 = bits(remainder, 63, 0) + node T_691 = mux(T_683, T_689, T_690) + io.resp.bits.data <= T_691 + node T_692 = eq(state, UInt<3>("h05")) + io.resp.valid <= T_692 + node T_693 = eq(state, UInt<1>("h00")) + io.req.ready <= T_693 module Rocket : input clk : Clock input reset : UInt<1> output io : {host : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}, imem : {req : {valid : UInt<1>, bits : {pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>}, dmem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, flip ptw : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}}, flip fpu : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}}, flip rocc : {flip cmd : {flip ready : UInt<1>, valid : UInt<1>, bits : {inst : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>}, rs1 : UInt<64>, rs2 : UInt<64>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {rd : UInt<5>, data : UInt<64>}}, mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, busy : UInt<1>, flip s : UInt<1>, interrupt : UInt<1>, autl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}, utl : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[0], iptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, dptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, pptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, fpu_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, flip fpu_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip exception : UInt<1>, dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}}} - io.rocc.dma.resp.bits.status <= UInt<1>("h00") - io.rocc.dma.resp.bits.client_xact_id <= UInt<1>("h00") - io.rocc.dma.resp.valid <= UInt<1>("h00") - io.rocc.dma.req.ready <= UInt<1>("h00") - io.rocc.exception <= UInt<1>("h00") - io.rocc.fpu_resp.bits.exc <= UInt<1>("h00") - io.rocc.fpu_resp.bits.data <= UInt<1>("h00") - io.rocc.fpu_resp.valid <= UInt<1>("h00") - io.rocc.fpu_req.ready <= UInt<1>("h00") - io.rocc.pptw.invalidate <= UInt<1>("h00") - io.rocc.pptw.status.ie <= UInt<1>("h00") - io.rocc.pptw.status.prv <= UInt<1>("h00") - io.rocc.pptw.status.ie1 <= UInt<1>("h00") - io.rocc.pptw.status.prv1 <= UInt<1>("h00") - io.rocc.pptw.status.ie2 <= UInt<1>("h00") - io.rocc.pptw.status.prv2 <= UInt<1>("h00") - io.rocc.pptw.status.ie3 <= UInt<1>("h00") - io.rocc.pptw.status.prv3 <= UInt<1>("h00") - io.rocc.pptw.status.fs <= UInt<1>("h00") - io.rocc.pptw.status.xs <= UInt<1>("h00") - io.rocc.pptw.status.mprv <= UInt<1>("h00") - io.rocc.pptw.status.vm <= UInt<1>("h00") - io.rocc.pptw.status.zero1 <= UInt<1>("h00") - io.rocc.pptw.status.sd_rv32 <= UInt<1>("h00") - io.rocc.pptw.status.zero2 <= UInt<1>("h00") - io.rocc.pptw.status.sd <= UInt<1>("h00") - io.rocc.pptw.resp.bits.pte.v <= UInt<1>("h00") - io.rocc.pptw.resp.bits.pte.typ <= UInt<1>("h00") - io.rocc.pptw.resp.bits.pte.r <= UInt<1>("h00") - io.rocc.pptw.resp.bits.pte.d <= UInt<1>("h00") - io.rocc.pptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") - io.rocc.pptw.resp.bits.pte.ppn <= UInt<1>("h00") - io.rocc.pptw.resp.bits.error <= UInt<1>("h00") - io.rocc.pptw.resp.valid <= UInt<1>("h00") - io.rocc.pptw.req.ready <= UInt<1>("h00") - io.rocc.dptw.invalidate <= UInt<1>("h00") - io.rocc.dptw.status.ie <= UInt<1>("h00") - io.rocc.dptw.status.prv <= UInt<1>("h00") - io.rocc.dptw.status.ie1 <= UInt<1>("h00") - io.rocc.dptw.status.prv1 <= UInt<1>("h00") - io.rocc.dptw.status.ie2 <= UInt<1>("h00") - io.rocc.dptw.status.prv2 <= UInt<1>("h00") - io.rocc.dptw.status.ie3 <= UInt<1>("h00") - io.rocc.dptw.status.prv3 <= UInt<1>("h00") - io.rocc.dptw.status.fs <= UInt<1>("h00") - io.rocc.dptw.status.xs <= UInt<1>("h00") - io.rocc.dptw.status.mprv <= UInt<1>("h00") - io.rocc.dptw.status.vm <= UInt<1>("h00") - io.rocc.dptw.status.zero1 <= UInt<1>("h00") - io.rocc.dptw.status.sd_rv32 <= UInt<1>("h00") - io.rocc.dptw.status.zero2 <= UInt<1>("h00") - io.rocc.dptw.status.sd <= UInt<1>("h00") - io.rocc.dptw.resp.bits.pte.v <= UInt<1>("h00") - io.rocc.dptw.resp.bits.pte.typ <= UInt<1>("h00") - io.rocc.dptw.resp.bits.pte.r <= UInt<1>("h00") - io.rocc.dptw.resp.bits.pte.d <= UInt<1>("h00") - io.rocc.dptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") - io.rocc.dptw.resp.bits.pte.ppn <= UInt<1>("h00") - io.rocc.dptw.resp.bits.error <= UInt<1>("h00") - io.rocc.dptw.resp.valid <= UInt<1>("h00") - io.rocc.dptw.req.ready <= UInt<1>("h00") - io.rocc.iptw.invalidate <= UInt<1>("h00") - io.rocc.iptw.status.ie <= UInt<1>("h00") - io.rocc.iptw.status.prv <= UInt<1>("h00") - io.rocc.iptw.status.ie1 <= UInt<1>("h00") - io.rocc.iptw.status.prv1 <= UInt<1>("h00") - io.rocc.iptw.status.ie2 <= UInt<1>("h00") - io.rocc.iptw.status.prv2 <= UInt<1>("h00") - io.rocc.iptw.status.ie3 <= UInt<1>("h00") - io.rocc.iptw.status.prv3 <= UInt<1>("h00") - io.rocc.iptw.status.fs <= UInt<1>("h00") - io.rocc.iptw.status.xs <= UInt<1>("h00") - io.rocc.iptw.status.mprv <= UInt<1>("h00") - io.rocc.iptw.status.vm <= UInt<1>("h00") - io.rocc.iptw.status.zero1 <= UInt<1>("h00") - io.rocc.iptw.status.sd_rv32 <= UInt<1>("h00") - io.rocc.iptw.status.zero2 <= UInt<1>("h00") - io.rocc.iptw.status.sd <= UInt<1>("h00") - io.rocc.iptw.resp.bits.pte.v <= UInt<1>("h00") - io.rocc.iptw.resp.bits.pte.typ <= UInt<1>("h00") - io.rocc.iptw.resp.bits.pte.r <= UInt<1>("h00") - io.rocc.iptw.resp.bits.pte.d <= UInt<1>("h00") - io.rocc.iptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") - io.rocc.iptw.resp.bits.pte.ppn <= UInt<1>("h00") - io.rocc.iptw.resp.bits.error <= UInt<1>("h00") - io.rocc.iptw.resp.valid <= UInt<1>("h00") - io.rocc.iptw.req.ready <= UInt<1>("h00") - io.rocc.autl.grant.bits.data <= UInt<1>("h00") - io.rocc.autl.grant.bits.g_type <= UInt<1>("h00") - io.rocc.autl.grant.bits.is_builtin_type <= UInt<1>("h00") - io.rocc.autl.grant.bits.manager_xact_id <= UInt<1>("h00") - io.rocc.autl.grant.bits.client_xact_id <= UInt<1>("h00") - io.rocc.autl.grant.bits.addr_beat <= UInt<1>("h00") - io.rocc.autl.grant.valid <= UInt<1>("h00") - io.rocc.autl.acquire.ready <= UInt<1>("h00") - io.rocc.s <= UInt<1>("h00") - io.rocc.mem.ordered <= UInt<1>("h00") - io.rocc.mem.xcpt.pf.st <= UInt<1>("h00") - io.rocc.mem.xcpt.pf.ld <= UInt<1>("h00") - io.rocc.mem.xcpt.ma.st <= UInt<1>("h00") - io.rocc.mem.xcpt.ma.ld <= UInt<1>("h00") - io.rocc.mem.replay_next.bits <= UInt<1>("h00") - io.rocc.mem.replay_next.valid <= UInt<1>("h00") - io.rocc.mem.resp.bits.store_data <= UInt<1>("h00") - io.rocc.mem.resp.bits.data_word_bypass <= UInt<1>("h00") - io.rocc.mem.resp.bits.has_data <= UInt<1>("h00") - io.rocc.mem.resp.bits.replay <= UInt<1>("h00") - io.rocc.mem.resp.bits.nack <= UInt<1>("h00") - io.rocc.mem.resp.bits.data <= UInt<1>("h00") - io.rocc.mem.resp.bits.typ <= UInt<1>("h00") - io.rocc.mem.resp.bits.cmd <= UInt<1>("h00") - io.rocc.mem.resp.bits.tag <= UInt<1>("h00") - io.rocc.mem.resp.bits.addr <= UInt<1>("h00") - io.rocc.mem.resp.valid <= UInt<1>("h00") - io.rocc.mem.req.ready <= UInt<1>("h00") - io.rocc.resp.ready <= UInt<1>("h00") - io.rocc.cmd.bits.rs2 <= UInt<1>("h00") - io.rocc.cmd.bits.rs1 <= UInt<1>("h00") - io.rocc.cmd.bits.inst.opcode <= UInt<1>("h00") - io.rocc.cmd.bits.inst.rd <= UInt<1>("h00") - io.rocc.cmd.bits.inst.xs2 <= UInt<1>("h00") - io.rocc.cmd.bits.inst.xs1 <= UInt<1>("h00") - io.rocc.cmd.bits.inst.xd <= UInt<1>("h00") - io.rocc.cmd.bits.inst.rs1 <= UInt<1>("h00") - io.rocc.cmd.bits.inst.rs2 <= UInt<1>("h00") - io.rocc.cmd.bits.inst.funct <= UInt<1>("h00") - io.rocc.cmd.valid <= UInt<1>("h00") - io.fpu.cp_resp.ready <= UInt<1>("h00") - io.fpu.cp_req.bits.in3 <= UInt<1>("h00") - io.fpu.cp_req.bits.in2 <= UInt<1>("h00") - io.fpu.cp_req.bits.in1 <= UInt<1>("h00") - io.fpu.cp_req.bits.typ <= UInt<1>("h00") - io.fpu.cp_req.bits.rm <= UInt<1>("h00") - io.fpu.cp_req.bits.wflags <= UInt<1>("h00") - io.fpu.cp_req.bits.round <= UInt<1>("h00") - io.fpu.cp_req.bits.sqrt <= UInt<1>("h00") - io.fpu.cp_req.bits.div <= UInt<1>("h00") - io.fpu.cp_req.bits.fma <= UInt<1>("h00") - io.fpu.cp_req.bits.fastpipe <= UInt<1>("h00") - io.fpu.cp_req.bits.toint <= UInt<1>("h00") - io.fpu.cp_req.bits.fromint <= UInt<1>("h00") - io.fpu.cp_req.bits.single <= UInt<1>("h00") - io.fpu.cp_req.bits.swap23 <= UInt<1>("h00") - io.fpu.cp_req.bits.swap12 <= UInt<1>("h00") - io.fpu.cp_req.bits.ren3 <= UInt<1>("h00") - io.fpu.cp_req.bits.ren2 <= UInt<1>("h00") - io.fpu.cp_req.bits.ren1 <= UInt<1>("h00") - io.fpu.cp_req.bits.wen <= UInt<1>("h00") - io.fpu.cp_req.bits.ldst <= UInt<1>("h00") - io.fpu.cp_req.bits.cmd <= UInt<1>("h00") - io.fpu.cp_req.valid <= UInt<1>("h00") - io.fpu.killm <= UInt<1>("h00") - io.fpu.killx <= UInt<1>("h00") - io.fpu.valid <= UInt<1>("h00") - io.fpu.dmem_resp_data <= UInt<1>("h00") - io.fpu.dmem_resp_tag <= UInt<1>("h00") - io.fpu.dmem_resp_type <= UInt<1>("h00") - io.fpu.dmem_resp_val <= UInt<1>("h00") - io.fpu.fcsr_rm <= UInt<1>("h00") - io.fpu.fromint_data <= UInt<1>("h00") - io.fpu.inst <= UInt<1>("h00") - io.ptw.status.ie <= UInt<1>("h00") - io.ptw.status.prv <= UInt<1>("h00") - io.ptw.status.ie1 <= UInt<1>("h00") - io.ptw.status.prv1 <= UInt<1>("h00") - io.ptw.status.ie2 <= UInt<1>("h00") - io.ptw.status.prv2 <= UInt<1>("h00") - io.ptw.status.ie3 <= UInt<1>("h00") - io.ptw.status.prv3 <= UInt<1>("h00") - io.ptw.status.fs <= UInt<1>("h00") - io.ptw.status.xs <= UInt<1>("h00") - io.ptw.status.mprv <= UInt<1>("h00") - io.ptw.status.vm <= UInt<1>("h00") - io.ptw.status.zero1 <= UInt<1>("h00") - io.ptw.status.sd_rv32 <= UInt<1>("h00") - io.ptw.status.zero2 <= UInt<1>("h00") - io.ptw.status.sd <= UInt<1>("h00") - io.ptw.invalidate <= UInt<1>("h00") - io.ptw.ptbr <= UInt<1>("h00") - io.dmem.invalidate_lr <= UInt<1>("h00") - io.dmem.req.bits.data <= UInt<1>("h00") - io.dmem.req.bits.phys <= UInt<1>("h00") - io.dmem.req.bits.kill <= UInt<1>("h00") - io.dmem.req.bits.typ <= UInt<1>("h00") - io.dmem.req.bits.cmd <= UInt<1>("h00") - io.dmem.req.bits.tag <= UInt<1>("h00") - io.dmem.req.bits.addr <= UInt<1>("h00") - io.dmem.req.valid <= UInt<1>("h00") - io.imem.invalidate <= UInt<1>("h00") - io.imem.ras_update.bits.prediction.bits.bht.value <= UInt<1>("h00") - io.imem.ras_update.bits.prediction.bits.bht.history <= UInt<1>("h00") - io.imem.ras_update.bits.prediction.bits.entry <= UInt<1>("h00") - io.imem.ras_update.bits.prediction.bits.target <= UInt<1>("h00") - io.imem.ras_update.bits.prediction.bits.bridx <= UInt<1>("h00") - io.imem.ras_update.bits.prediction.bits.mask <= UInt<1>("h00") - io.imem.ras_update.bits.prediction.bits.taken <= UInt<1>("h00") - io.imem.ras_update.bits.prediction.valid <= UInt<1>("h00") - io.imem.ras_update.bits.returnAddr <= UInt<1>("h00") - io.imem.ras_update.bits.isReturn <= UInt<1>("h00") - io.imem.ras_update.bits.isCall <= UInt<1>("h00") - io.imem.ras_update.valid <= UInt<1>("h00") - io.imem.bht_update.bits.mispredict <= UInt<1>("h00") - io.imem.bht_update.bits.taken <= UInt<1>("h00") - io.imem.bht_update.bits.pc <= UInt<1>("h00") - io.imem.bht_update.bits.prediction.bits.bht.value <= UInt<1>("h00") - io.imem.bht_update.bits.prediction.bits.bht.history <= UInt<1>("h00") - io.imem.bht_update.bits.prediction.bits.entry <= UInt<1>("h00") - io.imem.bht_update.bits.prediction.bits.target <= UInt<1>("h00") - io.imem.bht_update.bits.prediction.bits.bridx <= UInt<1>("h00") - io.imem.bht_update.bits.prediction.bits.mask <= UInt<1>("h00") - io.imem.bht_update.bits.prediction.bits.taken <= UInt<1>("h00") - io.imem.bht_update.bits.prediction.valid <= UInt<1>("h00") - io.imem.bht_update.valid <= UInt<1>("h00") - io.imem.btb_update.bits.br_pc <= UInt<1>("h00") - io.imem.btb_update.bits.isReturn <= UInt<1>("h00") - io.imem.btb_update.bits.isJump <= UInt<1>("h00") - io.imem.btb_update.bits.taken <= UInt<1>("h00") - io.imem.btb_update.bits.target <= UInt<1>("h00") - io.imem.btb_update.bits.pc <= UInt<1>("h00") - io.imem.btb_update.bits.prediction.bits.bht.value <= UInt<1>("h00") - io.imem.btb_update.bits.prediction.bits.bht.history <= UInt<1>("h00") - io.imem.btb_update.bits.prediction.bits.entry <= UInt<1>("h00") - io.imem.btb_update.bits.prediction.bits.target <= UInt<1>("h00") - io.imem.btb_update.bits.prediction.bits.bridx <= UInt<1>("h00") - io.imem.btb_update.bits.prediction.bits.mask <= UInt<1>("h00") - io.imem.btb_update.bits.prediction.bits.taken <= UInt<1>("h00") - io.imem.btb_update.bits.prediction.valid <= UInt<1>("h00") - io.imem.btb_update.valid <= UInt<1>("h00") - io.imem.resp.ready <= UInt<1>("h00") - io.imem.req.bits.pc <= UInt<1>("h00") - io.imem.req.valid <= UInt<1>("h00") - io.host.debug_stats_csr <= UInt<1>("h00") - io.host.csr.resp.bits <= UInt<1>("h00") - io.host.csr.resp.valid <= UInt<1>("h00") - io.host.csr.req.ready <= UInt<1>("h00") - reg ex_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk, UInt<1>("h00"), ex_ctrl - reg mem_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk, UInt<1>("h00"), mem_ctrl - reg wb_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk, UInt<1>("h00"), wb_ctrl - reg ex_reg_xcpt_interrupt : UInt<1>, clk, UInt<1>("h00"), ex_reg_xcpt_interrupt - reg ex_reg_valid : UInt<1>, clk, UInt<1>("h00"), ex_reg_valid - reg ex_reg_btb_hit : UInt<1>, clk, UInt<1>("h00"), ex_reg_btb_hit - reg ex_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk, UInt<1>("h00"), ex_reg_btb_resp - reg ex_reg_xcpt : UInt<1>, clk, UInt<1>("h00"), ex_reg_xcpt - reg ex_reg_flush_pipe : UInt<1>, clk, UInt<1>("h00"), ex_reg_flush_pipe - reg ex_reg_load_use : UInt<1>, clk, UInt<1>("h00"), ex_reg_load_use - reg ex_reg_cause : UInt<?>, clk, UInt<1>("h00"), ex_reg_cause - reg ex_reg_pc : UInt<?>, clk, UInt<1>("h00"), ex_reg_pc - reg ex_reg_inst : UInt<?>, clk, UInt<1>("h00"), ex_reg_inst - reg mem_reg_xcpt_interrupt : UInt<1>, clk, UInt<1>("h00"), mem_reg_xcpt_interrupt - reg mem_reg_valid : UInt<1>, clk, UInt<1>("h00"), mem_reg_valid - reg mem_reg_btb_hit : UInt<1>, clk, UInt<1>("h00"), mem_reg_btb_hit - reg mem_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk, UInt<1>("h00"), mem_reg_btb_resp - reg mem_reg_xcpt : UInt<1>, clk, UInt<1>("h00"), mem_reg_xcpt - reg mem_reg_replay : UInt<1>, clk, UInt<1>("h00"), mem_reg_replay - reg mem_reg_flush_pipe : UInt<1>, clk, UInt<1>("h00"), mem_reg_flush_pipe - reg mem_reg_cause : UInt<?>, clk, UInt<1>("h00"), mem_reg_cause - reg mem_reg_slow_bypass : UInt<1>, clk, UInt<1>("h00"), mem_reg_slow_bypass - reg mem_reg_pc : UInt<?>, clk, UInt<1>("h00"), mem_reg_pc - reg mem_reg_inst : UInt<?>, clk, UInt<1>("h00"), mem_reg_inst - reg mem_reg_wdata : UInt<?>, clk, UInt<1>("h00"), mem_reg_wdata - reg mem_reg_rs2 : UInt<?>, clk, UInt<1>("h00"), mem_reg_rs2 + io is invalid + reg ex_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk + reg mem_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk + reg wb_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>}, clk + reg ex_reg_xcpt_interrupt : UInt<1>, clk + reg ex_reg_valid : UInt<1>, clk + reg ex_reg_btb_hit : UInt<1>, clk + reg ex_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk + reg ex_reg_xcpt : UInt<1>, clk + reg ex_reg_flush_pipe : UInt<1>, clk + reg ex_reg_load_use : UInt<1>, clk + reg ex_reg_cause : UInt<?>, clk + reg ex_reg_pc : UInt<?>, clk + reg ex_reg_inst : UInt<?>, clk + reg mem_reg_xcpt_interrupt : UInt<1>, clk + reg mem_reg_valid : UInt<1>, clk + reg mem_reg_btb_hit : UInt<1>, clk + reg mem_reg_btb_resp : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk + reg mem_reg_xcpt : UInt<1>, clk + reg mem_reg_replay : UInt<1>, clk + reg mem_reg_flush_pipe : UInt<1>, clk + reg mem_reg_cause : UInt<?>, clk + reg mem_reg_slow_bypass : UInt<1>, clk + reg mem_reg_pc : UInt<?>, clk + reg mem_reg_inst : UInt<?>, clk + reg mem_reg_wdata : UInt<?>, clk + reg mem_reg_rs2 : UInt<?>, clk wire take_pc_mem : UInt<1> - take_pc_mem <= UInt<1>("h00") - reg wb_reg_valid : UInt<1>, clk, UInt<1>("h00"), wb_reg_valid - reg wb_reg_xcpt : UInt<1>, clk, UInt<1>("h00"), wb_reg_xcpt - reg wb_reg_replay : UInt<1>, clk, UInt<1>("h00"), wb_reg_replay - reg wb_reg_cause : UInt<?>, clk, UInt<1>("h00"), wb_reg_cause - reg wb_reg_rocc_pending : UInt<1>, clk, reset, UInt<1>("h00") - reg wb_reg_pc : UInt<?>, clk, UInt<1>("h00"), wb_reg_pc - reg wb_reg_inst : UInt<?>, clk, UInt<1>("h00"), wb_reg_inst - reg wb_reg_wdata : UInt<?>, clk, UInt<1>("h00"), wb_reg_wdata - reg wb_reg_rs2 : UInt<?>, clk, UInt<1>("h00"), wb_reg_rs2 + take_pc_mem is invalid + reg wb_reg_valid : UInt<1>, clk + reg wb_reg_xcpt : UInt<1>, clk + reg wb_reg_replay : UInt<1>, clk + reg wb_reg_cause : UInt<?>, clk + reg wb_reg_rocc_pending : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg wb_reg_pc : UInt<?>, clk + reg wb_reg_inst : UInt<?>, clk + reg wb_reg_wdata : UInt<?>, clk + reg wb_reg_rs2 : UInt<?>, clk wire take_pc_wb : UInt<1> - take_pc_wb <= UInt<1>("h00") + take_pc_wb is invalid node take_pc_mem_wb = or(take_pc_wb, take_pc_mem) wire id_ctrl : {legal : UInt<1>, fp : UInt<1>, rocc : UInt<1>, branch : UInt<1>, jal : UInt<1>, jalr : UInt<1>, rxs2 : UInt<1>, rxs1 : UInt<1>, sel_alu2 : UInt<2>, sel_alu1 : UInt<2>, sel_imm : UInt<3>, alu_dw : UInt<1>, alu_fn : UInt<4>, mem : UInt<1>, mem_cmd : UInt<5>, mem_type : UInt<3>, rfs1 : UInt<1>, rfs2 : UInt<1>, rfs3 : UInt<1>, wfd : UInt<1>, div : UInt<1>, wxd : UInt<1>, csr : UInt<3>, fence_i : UInt<1>, fence : UInt<1>, amo : UInt<1>} - id_ctrl.amo <= UInt<1>("h00") - id_ctrl.fence <= UInt<1>("h00") - id_ctrl.fence_i <= UInt<1>("h00") - id_ctrl.csr <= UInt<1>("h00") - id_ctrl.wxd <= UInt<1>("h00") - id_ctrl.div <= UInt<1>("h00") - id_ctrl.wfd <= UInt<1>("h00") - id_ctrl.rfs3 <= UInt<1>("h00") - id_ctrl.rfs2 <= UInt<1>("h00") - id_ctrl.rfs1 <= UInt<1>("h00") - id_ctrl.mem_type <= UInt<1>("h00") - id_ctrl.mem_cmd <= UInt<1>("h00") - id_ctrl.mem <= UInt<1>("h00") - id_ctrl.alu_fn <= UInt<1>("h00") - id_ctrl.alu_dw <= UInt<1>("h00") - id_ctrl.sel_imm <= UInt<1>("h00") - id_ctrl.sel_alu1 <= UInt<1>("h00") - id_ctrl.sel_alu2 <= UInt<1>("h00") - id_ctrl.rxs1 <= UInt<1>("h00") - id_ctrl.rxs2 <= UInt<1>("h00") - id_ctrl.jalr <= UInt<1>("h00") - id_ctrl.jal <= UInt<1>("h00") - id_ctrl.branch <= UInt<1>("h00") + id_ctrl is invalid + node T_6071 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f")) + node T_6073 = eq(T_6071, UInt<32>("h03")) + node T_6075 = and(io.imem.resp.bits.data[0], UInt<32>("h0106f")) + node T_6077 = eq(T_6075, UInt<32>("h03")) + node T_6079 = and(io.imem.resp.bits.data[0], UInt<32>("h0607f")) + node T_6081 = eq(T_6079, UInt<32>("h0f")) + node T_6083 = and(io.imem.resp.bits.data[0], UInt<32>("h07077")) + node T_6085 = eq(T_6083, UInt<32>("h013")) + node T_6087 = and(io.imem.resp.bits.data[0], UInt<32>("h05f")) + node T_6089 = eq(T_6087, UInt<32>("h017")) + node T_6091 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc00007f")) + node T_6093 = eq(T_6091, UInt<32>("h033")) + node T_6095 = and(io.imem.resp.bits.data[0], UInt<32>("h0be007077")) + node T_6097 = eq(T_6095, UInt<32>("h033")) + node T_6099 = and(io.imem.resp.bits.data[0], UInt<32>("h04000073")) + node T_6101 = eq(T_6099, UInt<32>("h043")) + node T_6103 = and(io.imem.resp.bits.data[0], UInt<32>("h0e400007f")) + node T_6105 = eq(T_6103, UInt<32>("h053")) + node T_6107 = and(io.imem.resp.bits.data[0], UInt<32>("h0707b")) + node T_6109 = eq(T_6107, UInt<32>("h063")) + node T_6111 = and(io.imem.resp.bits.data[0], UInt<32>("h07f")) + node T_6113 = eq(T_6111, UInt<32>("h06f")) + node T_6115 = and(io.imem.resp.bits.data[0], UInt<32>("h0ffefffff")) + node T_6117 = eq(T_6115, UInt<32>("h073")) + node T_6119 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc00305f")) + node T_6121 = eq(T_6119, UInt<32>("h01013")) + node T_6123 = and(io.imem.resp.bits.data[0], UInt<32>("h0fe00305f")) + node T_6125 = eq(T_6123, UInt<32>("h0101b")) + node T_6127 = and(io.imem.resp.bits.data[0], UInt<32>("h0605b")) + node T_6129 = eq(T_6127, UInt<32>("h02003")) + node T_6131 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f")) + node T_6133 = eq(T_6131, UInt<32>("h02013")) + node T_6135 = and(io.imem.resp.bits.data[0], UInt<32>("h01800607f")) + node T_6137 = eq(T_6135, UInt<32>("h0202f")) + node T_6139 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f")) + node T_6141 = eq(T_6139, UInt<32>("h02073")) + node T_6143 = and(io.imem.resp.bits.data[0], UInt<32>("h0bc00707f")) + node T_6145 = eq(T_6143, UInt<32>("h05013")) + node T_6147 = and(io.imem.resp.bits.data[0], UInt<32>("h0be00705f")) + node T_6149 = eq(T_6147, UInt<32>("h0501b")) + node T_6151 = and(io.imem.resp.bits.data[0], UInt<32>("h0be007077")) + node T_6153 = eq(T_6151, UInt<32>("h05033")) + node T_6155 = and(io.imem.resp.bits.data[0], UInt<32>("h0fe004077")) + node T_6157 = eq(T_6155, UInt<32>("h02004033")) + node T_6159 = and(io.imem.resp.bits.data[0], UInt<32>("h0e800607f")) + node T_6161 = eq(T_6159, UInt<32>("h0800202f")) + node T_6163 = and(io.imem.resp.bits.data[0], UInt<32>("h0ffdfffff")) + node T_6165 = eq(T_6163, UInt<32>("h010000073")) + node T_6167 = and(io.imem.resp.bits.data[0], UInt<32>("h0f9f0607f")) + node T_6169 = eq(T_6167, UInt<32>("h01000202f")) + node T_6171 = and(io.imem.resp.bits.data[0], UInt<32>("h0fff07fff")) + node T_6173 = eq(T_6171, UInt<32>("h010100073")) + node T_6175 = and(io.imem.resp.bits.data[0], UInt<32>("h0f400607f")) + node T_6177 = eq(T_6175, UInt<32>("h020000053")) + node T_6179 = and(io.imem.resp.bits.data[0], UInt<32>("h07c00607f")) + node T_6181 = eq(T_6179, UInt<32>("h020000053")) + node T_6183 = and(io.imem.resp.bits.data[0], UInt<32>("h07c00507f")) + node T_6185 = eq(T_6183, UInt<32>("h020000053")) + node T_6187 = eq(io.imem.resp.bits.data[0], UInt<32>("h030500073")) + node T_6189 = and(io.imem.resp.bits.data[0], UInt<32>("h07ff0007f")) + node T_6191 = eq(T_6189, UInt<32>("h040100053")) + node T_6193 = and(io.imem.resp.bits.data[0], UInt<32>("h07ff0007f")) + node T_6195 = eq(T_6193, UInt<32>("h042000053")) + node T_6197 = and(io.imem.resp.bits.data[0], UInt<32>("h0fdf0007f")) + node T_6199 = eq(T_6197, UInt<32>("h058000053")) + node T_6201 = and(io.imem.resp.bits.data[0], UInt<32>("h0edc0007f")) + node T_6203 = eq(T_6201, UInt<32>("h0c0000053")) + node T_6205 = and(io.imem.resp.bits.data[0], UInt<32>("h0fdf0607f")) + node T_6207 = eq(T_6205, UInt<32>("h0e0000053")) + node T_6209 = and(io.imem.resp.bits.data[0], UInt<32>("h0edf0707f")) + node T_6211 = eq(T_6209, UInt<32>("h0e0000053")) + node T_6213 = and(io.imem.resp.bits.data[0], UInt<32>("h0603f")) + node T_6215 = eq(T_6213, UInt<32>("h023")) + node T_6217 = and(io.imem.resp.bits.data[0], UInt<32>("h0306f")) + node T_6219 = eq(T_6217, UInt<32>("h01063")) + node T_6221 = and(io.imem.resp.bits.data[0], UInt<32>("h0407f")) + node T_6223 = eq(T_6221, UInt<32>("h04063")) + node T_6225 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc007077")) + node T_6227 = eq(T_6225, UInt<32>("h033")) + node T_6229 = or(UInt<1>("h00"), T_6073) + node T_6230 = or(T_6229, T_6077) + node T_6231 = or(T_6230, T_6081) + node T_6232 = or(T_6231, T_6085) + node T_6233 = or(T_6232, T_6089) + node T_6234 = or(T_6233, T_6093) + node T_6235 = or(T_6234, T_6097) + node T_6236 = or(T_6235, T_6101) + node T_6237 = or(T_6236, T_6105) + node T_6238 = or(T_6237, T_6109) + node T_6239 = or(T_6238, T_6113) + node T_6240 = or(T_6239, T_6117) + node T_6241 = or(T_6240, T_6121) + node T_6242 = or(T_6241, T_6125) + node T_6243 = or(T_6242, T_6129) + node T_6244 = or(T_6243, T_6133) + node T_6245 = or(T_6244, T_6137) + node T_6246 = or(T_6245, T_6141) + node T_6247 = or(T_6246, T_6145) + node T_6248 = or(T_6247, T_6149) + node T_6249 = or(T_6248, T_6153) + node T_6250 = or(T_6249, T_6157) + node T_6251 = or(T_6250, T_6161) + node T_6252 = or(T_6251, T_6165) + node T_6253 = or(T_6252, T_6169) + node T_6254 = or(T_6253, T_6173) + node T_6255 = or(T_6254, T_6177) + node T_6256 = or(T_6255, T_6181) + node T_6257 = or(T_6256, T_6185) + node T_6258 = or(T_6257, T_6187) + node T_6259 = or(T_6258, T_6191) + node T_6260 = or(T_6259, T_6195) + node T_6261 = or(T_6260, T_6199) + node T_6262 = or(T_6261, T_6203) + node T_6263 = or(T_6262, T_6207) + node T_6264 = or(T_6263, T_6211) + node T_6265 = or(T_6264, T_6215) + node T_6266 = or(T_6265, T_6219) + node T_6267 = or(T_6266, T_6223) + node T_6268 = or(T_6267, T_6227) + node T_6270 = and(io.imem.resp.bits.data[0], UInt<32>("h05c")) + node T_6272 = eq(T_6270, UInt<32>("h04")) + node T_6274 = and(io.imem.resp.bits.data[0], UInt<32>("h060")) + node T_6276 = eq(T_6274, UInt<32>("h040")) + node T_6278 = or(UInt<1>("h00"), T_6272) + node T_6279 = or(T_6278, T_6276) + node T_6282 = and(io.imem.resp.bits.data[0], UInt<32>("h074")) + node T_6284 = eq(T_6282, UInt<32>("h060")) + node T_6286 = or(UInt<1>("h00"), T_6284) + node T_6288 = and(io.imem.resp.bits.data[0], UInt<32>("h068")) + node T_6290 = eq(T_6288, UInt<32>("h068")) + node T_6292 = or(UInt<1>("h00"), T_6290) + node T_6294 = and(io.imem.resp.bits.data[0], UInt<32>("h0203c")) + node T_6296 = eq(T_6294, UInt<32>("h024")) + node T_6298 = or(UInt<1>("h00"), T_6296) + node T_6300 = and(io.imem.resp.bits.data[0], UInt<32>("h064")) + node T_6302 = eq(T_6300, UInt<32>("h020")) + node T_6304 = and(io.imem.resp.bits.data[0], UInt<32>("h034")) + node T_6306 = eq(T_6304, UInt<32>("h020")) + node T_6308 = and(io.imem.resp.bits.data[0], UInt<32>("h02048")) + node T_6310 = eq(T_6308, UInt<32>("h02008")) + node T_6312 = or(UInt<1>("h00"), T_6302) + node T_6313 = or(T_6312, T_6306) + node T_6314 = or(T_6313, T_6310) + node T_6316 = and(io.imem.resp.bits.data[0], UInt<32>("h044")) + node T_6318 = eq(T_6316, UInt<32>("h00")) + node T_6320 = and(io.imem.resp.bits.data[0], UInt<32>("h04024")) + node T_6322 = eq(T_6320, UInt<32>("h020")) + node T_6324 = and(io.imem.resp.bits.data[0], UInt<32>("h038")) + node T_6326 = eq(T_6324, UInt<32>("h020")) + node T_6328 = and(io.imem.resp.bits.data[0], UInt<32>("h02050")) + node T_6330 = eq(T_6328, UInt<32>("h02000")) + node T_6332 = and(io.imem.resp.bits.data[0], UInt<32>("h090000034")) + node T_6334 = eq(T_6332, UInt<32>("h090000010")) + node T_6336 = or(UInt<1>("h00"), T_6318) + node T_6337 = or(T_6336, T_6322) + node T_6338 = or(T_6337, T_6326) + node T_6339 = or(T_6338, T_6330) + node T_6340 = or(T_6339, T_6334) + node T_6342 = and(io.imem.resp.bits.data[0], UInt<32>("h058")) + node T_6344 = eq(T_6342, UInt<32>("h00")) + node T_6346 = and(io.imem.resp.bits.data[0], UInt<32>("h020")) + node T_6348 = eq(T_6346, UInt<32>("h00")) + node T_6350 = and(io.imem.resp.bits.data[0], UInt<32>("h0c")) + node T_6352 = eq(T_6350, UInt<32>("h04")) + node T_6354 = and(io.imem.resp.bits.data[0], UInt<32>("h048")) + node T_6356 = eq(T_6354, UInt<32>("h048")) + node T_6358 = and(io.imem.resp.bits.data[0], UInt<32>("h04050")) + node T_6360 = eq(T_6358, UInt<32>("h04050")) + node T_6362 = or(UInt<1>("h00"), T_6344) + node T_6363 = or(T_6362, T_6348) + node T_6364 = or(T_6363, T_6352) + node T_6365 = or(T_6364, T_6356) + node T_6366 = or(T_6365, T_6360) + node T_6368 = and(io.imem.resp.bits.data[0], UInt<32>("h048")) + node T_6370 = eq(T_6368, UInt<32>("h00")) + node T_6372 = and(io.imem.resp.bits.data[0], UInt<32>("h018")) + node T_6374 = eq(T_6372, UInt<32>("h00")) + node T_6376 = and(io.imem.resp.bits.data[0], UInt<32>("h04008")) + node T_6378 = eq(T_6376, UInt<32>("h04000")) + node T_6380 = or(UInt<1>("h00"), T_6370) + node T_6381 = or(T_6380, T_6318) + node T_6382 = or(T_6381, T_6374) + node T_6383 = or(T_6382, T_6378) + node T_6384 = cat(T_6383, T_6366) + node T_6386 = and(io.imem.resp.bits.data[0], UInt<32>("h04004")) + node T_6388 = eq(T_6386, UInt<32>("h00")) + node T_6390 = and(io.imem.resp.bits.data[0], UInt<32>("h050")) + node T_6392 = eq(T_6390, UInt<32>("h00")) + node T_6394 = and(io.imem.resp.bits.data[0], UInt<32>("h024")) + node T_6396 = eq(T_6394, UInt<32>("h00")) + node T_6398 = or(UInt<1>("h00"), T_6388) + node T_6399 = or(T_6398, T_6392) + node T_6400 = or(T_6399, T_6318) + node T_6401 = or(T_6400, T_6396) + node T_6402 = or(T_6401, T_6374) + node T_6404 = and(io.imem.resp.bits.data[0], UInt<32>("h034")) + node T_6406 = eq(T_6404, UInt<32>("h014")) + node T_6408 = or(UInt<1>("h00"), T_6406) + node T_6409 = or(T_6408, T_6356) + node T_6410 = cat(T_6409, T_6402) + node T_6412 = and(io.imem.resp.bits.data[0], UInt<32>("h018")) + node T_6414 = eq(T_6412, UInt<32>("h08")) + node T_6416 = and(io.imem.resp.bits.data[0], UInt<32>("h044")) + node T_6418 = eq(T_6416, UInt<32>("h040")) + node T_6420 = or(UInt<1>("h00"), T_6414) + node T_6421 = or(T_6420, T_6418) + node T_6423 = and(io.imem.resp.bits.data[0], UInt<32>("h014")) + node T_6425 = eq(T_6423, UInt<32>("h014")) + node T_6427 = or(UInt<1>("h00"), T_6414) + node T_6428 = or(T_6427, T_6425) + node T_6430 = and(io.imem.resp.bits.data[0], UInt<32>("h030")) + node T_6432 = eq(T_6430, UInt<32>("h00")) + node T_6434 = and(io.imem.resp.bits.data[0], UInt<32>("h0201c")) + node T_6436 = eq(T_6434, UInt<32>("h04")) + node T_6438 = and(io.imem.resp.bits.data[0], UInt<32>("h014")) + node T_6440 = eq(T_6438, UInt<32>("h010")) + node T_6442 = or(UInt<1>("h00"), T_6432) + node T_6443 = or(T_6442, T_6436) + node T_6444 = or(T_6443, T_6440) + node T_6445 = cat(T_6428, T_6421) + node T_6446 = cat(T_6444, T_6445) + node T_6448 = and(io.imem.resp.bits.data[0], UInt<32>("h010")) + node T_6450 = eq(T_6448, UInt<32>("h00")) + node T_6452 = and(io.imem.resp.bits.data[0], UInt<32>("h08")) + node T_6454 = eq(T_6452, UInt<32>("h00")) + node T_6456 = or(UInt<1>("h00"), T_6450) + node T_6457 = or(T_6456, T_6454) + node T_6459 = and(io.imem.resp.bits.data[0], UInt<32>("h03054")) + node T_6461 = eq(T_6459, UInt<32>("h01010")) + node T_6463 = and(io.imem.resp.bits.data[0], UInt<32>("h01058")) + node T_6465 = eq(T_6463, UInt<32>("h01040")) + node T_6467 = and(io.imem.resp.bits.data[0], UInt<32>("h07044")) + node T_6469 = eq(T_6467, UInt<32>("h07000")) + node T_6471 = or(UInt<1>("h00"), T_6461) + node T_6472 = or(T_6471, T_6465) + node T_6473 = or(T_6472, T_6469) + node T_6475 = and(io.imem.resp.bits.data[0], UInt<32>("h04054")) + node T_6477 = eq(T_6475, UInt<32>("h040")) + node T_6479 = and(io.imem.resp.bits.data[0], UInt<32>("h02058")) + node T_6481 = eq(T_6479, UInt<32>("h02040")) + node T_6483 = and(io.imem.resp.bits.data[0], UInt<32>("h03054")) + node T_6485 = eq(T_6483, UInt<32>("h03010")) + node T_6487 = and(io.imem.resp.bits.data[0], UInt<32>("h06054")) + node T_6489 = eq(T_6487, UInt<32>("h06010")) + node T_6491 = and(io.imem.resp.bits.data[0], UInt<32>("h040003034")) + node T_6493 = eq(T_6491, UInt<32>("h040000030")) + node T_6495 = and(io.imem.resp.bits.data[0], UInt<32>("h040001054")) + node T_6497 = eq(T_6495, UInt<32>("h040001010")) + node T_6499 = or(UInt<1>("h00"), T_6477) + node T_6500 = or(T_6499, T_6481) + node T_6501 = or(T_6500, T_6485) + node T_6502 = or(T_6501, T_6489) + node T_6503 = or(T_6502, T_6493) + node T_6504 = or(T_6503, T_6497) + node T_6506 = and(io.imem.resp.bits.data[0], UInt<32>("h02054")) + node T_6508 = eq(T_6506, UInt<32>("h02010")) + node T_6510 = and(io.imem.resp.bits.data[0], UInt<32>("h040004054")) + node T_6512 = eq(T_6510, UInt<32>("h04010")) + node T_6514 = and(io.imem.resp.bits.data[0], UInt<32>("h05054")) + node T_6516 = eq(T_6514, UInt<32>("h04010")) + node T_6518 = and(io.imem.resp.bits.data[0], UInt<32>("h04058")) + node T_6520 = eq(T_6518, UInt<32>("h04040")) + node T_6522 = or(UInt<1>("h00"), T_6508) + node T_6523 = or(T_6522, T_6512) + node T_6524 = or(T_6523, T_6516) + node T_6525 = or(T_6524, T_6520) + node T_6527 = and(io.imem.resp.bits.data[0], UInt<32>("h06054")) + node T_6529 = eq(T_6527, UInt<32>("h02010")) + node T_6531 = and(io.imem.resp.bits.data[0], UInt<32>("h040003054")) + node T_6533 = eq(T_6531, UInt<32>("h040001010")) + node T_6535 = or(UInt<1>("h00"), T_6529) + node T_6536 = or(T_6535, T_6520) + node T_6537 = or(T_6536, T_6493) + node T_6538 = or(T_6537, T_6533) + node T_6539 = cat(T_6504, T_6473) + node T_6540 = cat(T_6525, T_6539) + node T_6541 = cat(T_6538, T_6540) + node T_6543 = and(io.imem.resp.bits.data[0], UInt<32>("h0405f")) + node T_6545 = eq(T_6543, UInt<32>("h03")) + node T_6547 = and(io.imem.resp.bits.data[0], UInt<32>("h0107f")) + node T_6549 = eq(T_6547, UInt<32>("h03")) + node T_6551 = or(UInt<1>("h00"), T_6545) + node T_6552 = or(T_6551, T_6073) + node T_6553 = or(T_6552, T_6549) + node T_6554 = or(T_6553, T_6129) + node T_6555 = or(T_6554, T_6137) + node T_6556 = or(T_6555, T_6161) + node T_6557 = or(T_6556, T_6169) + node T_6559 = and(io.imem.resp.bits.data[0], UInt<32>("h028")) + node T_6561 = eq(T_6559, UInt<32>("h020")) + node T_6563 = and(io.imem.resp.bits.data[0], UInt<32>("h018000020")) + node T_6565 = eq(T_6563, UInt<32>("h018000020")) + node T_6567 = and(io.imem.resp.bits.data[0], UInt<32>("h020000020")) + node T_6569 = eq(T_6567, UInt<32>("h020000020")) + node T_6571 = or(UInt<1>("h00"), T_6561) + node T_6572 = or(T_6571, T_6565) + node T_6573 = or(T_6572, T_6569) + node T_6575 = and(io.imem.resp.bits.data[0], UInt<32>("h010000008")) + node T_6577 = eq(T_6575, UInt<32>("h010000008")) + node T_6579 = and(io.imem.resp.bits.data[0], UInt<32>("h040000008")) + node T_6581 = eq(T_6579, UInt<32>("h040000008")) + node T_6583 = or(UInt<1>("h00"), T_6577) + node T_6584 = or(T_6583, T_6581) + node T_6586 = and(io.imem.resp.bits.data[0], UInt<32>("h08000008")) + node T_6588 = eq(T_6586, UInt<32>("h08000008")) + node T_6590 = and(io.imem.resp.bits.data[0], UInt<32>("h080000008")) + node T_6592 = eq(T_6590, UInt<32>("h080000008")) + node T_6594 = or(UInt<1>("h00"), T_6588) + node T_6595 = or(T_6594, T_6577) + node T_6596 = or(T_6595, T_6592) + node T_6598 = and(io.imem.resp.bits.data[0], UInt<32>("h018000008")) + node T_6600 = eq(T_6598, UInt<32>("h08")) + node T_6602 = or(UInt<1>("h00"), T_6600) + node T_6604 = cat(T_6584, T_6573) + node T_6605 = cat(T_6596, T_6604) + node T_6606 = cat(T_6602, T_6605) + node T_6607 = cat(UInt<1>("h00"), T_6606) + node T_6609 = and(io.imem.resp.bits.data[0], UInt<32>("h01000")) + node T_6611 = eq(T_6609, UInt<32>("h01000")) + node T_6613 = or(UInt<1>("h00"), T_6611) + node T_6615 = and(io.imem.resp.bits.data[0], UInt<32>("h02000")) + node T_6617 = eq(T_6615, UInt<32>("h02000")) + node T_6619 = or(UInt<1>("h00"), T_6617) + node T_6621 = and(io.imem.resp.bits.data[0], UInt<32>("h04000")) + node T_6623 = eq(T_6621, UInt<32>("h04000")) + node T_6625 = or(UInt<1>("h00"), T_6623) + node T_6626 = cat(T_6619, T_6613) + node T_6627 = cat(T_6625, T_6626) + node T_6629 = and(io.imem.resp.bits.data[0], UInt<32>("h080000060")) + node T_6631 = eq(T_6629, UInt<32>("h040")) + node T_6633 = and(io.imem.resp.bits.data[0], UInt<32>("h010000060")) + node T_6635 = eq(T_6633, UInt<32>("h040")) + node T_6637 = and(io.imem.resp.bits.data[0], UInt<32>("h070")) + node T_6639 = eq(T_6637, UInt<32>("h040")) + node T_6641 = or(UInt<1>("h00"), T_6631) + node T_6642 = or(T_6641, T_6635) + node T_6643 = or(T_6642, T_6639) + node T_6645 = and(io.imem.resp.bits.data[0], UInt<32>("h07c")) + node T_6647 = eq(T_6645, UInt<32>("h024")) + node T_6649 = and(io.imem.resp.bits.data[0], UInt<32>("h040000060")) + node T_6651 = eq(T_6649, UInt<32>("h040")) + node T_6653 = and(io.imem.resp.bits.data[0], UInt<32>("h090000060")) + node T_6655 = eq(T_6653, UInt<32>("h010000040")) + node T_6657 = or(UInt<1>("h00"), T_6647) + node T_6658 = or(T_6657, T_6651) + node T_6659 = or(T_6658, T_6639) + node T_6660 = or(T_6659, T_6655) + node T_6662 = or(UInt<1>("h00"), T_6639) + node T_6664 = and(io.imem.resp.bits.data[0], UInt<32>("h03c")) + node T_6666 = eq(T_6664, UInt<32>("h04")) + node T_6668 = and(io.imem.resp.bits.data[0], UInt<32>("h010000060")) + node T_6670 = eq(T_6668, UInt<32>("h010000040")) + node T_6672 = or(UInt<1>("h00"), T_6666) + node T_6673 = or(T_6672, T_6631) + node T_6674 = or(T_6673, T_6639) + node T_6675 = or(T_6674, T_6670) + node T_6677 = and(io.imem.resp.bits.data[0], UInt<32>("h02000074")) + node T_6679 = eq(T_6677, UInt<32>("h02000030")) + node T_6681 = or(UInt<1>("h00"), T_6679) + node T_6683 = and(io.imem.resp.bits.data[0], UInt<32>("h064")) + node T_6685 = eq(T_6683, UInt<32>("h00")) + node T_6687 = and(io.imem.resp.bits.data[0], UInt<32>("h050")) + node T_6689 = eq(T_6687, UInt<32>("h010")) + node T_6691 = and(io.imem.resp.bits.data[0], UInt<32>("h02024")) + node T_6693 = eq(T_6691, UInt<32>("h024")) + node T_6695 = and(io.imem.resp.bits.data[0], UInt<32>("h028")) + node T_6697 = eq(T_6695, UInt<32>("h028")) + node T_6699 = and(io.imem.resp.bits.data[0], UInt<32>("h01030")) + node T_6701 = eq(T_6699, UInt<32>("h01030")) + node T_6703 = and(io.imem.resp.bits.data[0], UInt<32>("h02030")) + node T_6705 = eq(T_6703, UInt<32>("h02030")) + node T_6707 = and(io.imem.resp.bits.data[0], UInt<32>("h090000010")) + node T_6709 = eq(T_6707, UInt<32>("h080000010")) + node T_6711 = or(UInt<1>("h00"), T_6685) + node T_6712 = or(T_6711, T_6689) + node T_6713 = or(T_6712, T_6693) + node T_6714 = or(T_6713, T_6697) + node T_6715 = or(T_6714, T_6701) + node T_6716 = or(T_6715, T_6705) + node T_6717 = or(T_6716, T_6709) + node T_6719 = and(io.imem.resp.bits.data[0], UInt<32>("h01070")) + node T_6721 = eq(T_6719, UInt<32>("h01070")) + node T_6723 = or(UInt<1>("h00"), T_6721) + node T_6725 = and(io.imem.resp.bits.data[0], UInt<32>("h02070")) + node T_6727 = eq(T_6725, UInt<32>("h02070")) + node T_6729 = or(UInt<1>("h00"), T_6727) + node T_6731 = and(io.imem.resp.bits.data[0], UInt<32>("h03070")) + node T_6733 = eq(T_6731, UInt<32>("h070")) + node T_6735 = or(UInt<1>("h00"), T_6733) + node T_6736 = cat(T_6729, T_6723) + node T_6737 = cat(T_6735, T_6736) + node T_6739 = and(io.imem.resp.bits.data[0], UInt<32>("h03058")) + node T_6741 = eq(T_6739, UInt<32>("h01008")) + node T_6743 = or(UInt<1>("h00"), T_6741) + node T_6745 = and(io.imem.resp.bits.data[0], UInt<32>("h03058")) + node T_6747 = eq(T_6745, UInt<32>("h08")) + node T_6749 = or(UInt<1>("h00"), T_6747) + node T_6751 = and(io.imem.resp.bits.data[0], UInt<32>("h06048")) + node T_6753 = eq(T_6751, UInt<32>("h02008")) + node T_6755 = or(UInt<1>("h00"), T_6753) + id_ctrl.legal <= T_6268 + id_ctrl.fp <= T_6279 id_ctrl.rocc <= UInt<1>("h00") - id_ctrl.fp <= UInt<1>("h00") - id_ctrl.legal <= UInt<1>("h00") - node T_6099 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f")) - node T_6101 = eq(T_6099, UInt<32>("h03")) - node T_6103 = and(io.imem.resp.bits.data[0], UInt<32>("h0106f")) - node T_6105 = eq(T_6103, UInt<32>("h03")) - node T_6107 = and(io.imem.resp.bits.data[0], UInt<32>("h0607f")) - node T_6109 = eq(T_6107, UInt<32>("h0f")) - node T_6111 = and(io.imem.resp.bits.data[0], UInt<32>("h07077")) - node T_6113 = eq(T_6111, UInt<32>("h013")) - node T_6115 = and(io.imem.resp.bits.data[0], UInt<32>("h05f")) - node T_6117 = eq(T_6115, UInt<32>("h017")) - node T_6119 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc00007f")) - node T_6121 = eq(T_6119, UInt<32>("h033")) - node T_6123 = and(io.imem.resp.bits.data[0], UInt<32>("h0be007077")) - node T_6125 = eq(T_6123, UInt<32>("h033")) - node T_6127 = and(io.imem.resp.bits.data[0], UInt<32>("h04000073")) - node T_6129 = eq(T_6127, UInt<32>("h043")) - node T_6131 = and(io.imem.resp.bits.data[0], UInt<32>("h0e400007f")) - node T_6133 = eq(T_6131, UInt<32>("h053")) - node T_6135 = and(io.imem.resp.bits.data[0], UInt<32>("h0707b")) - node T_6137 = eq(T_6135, UInt<32>("h063")) - node T_6139 = and(io.imem.resp.bits.data[0], UInt<32>("h07f")) - node T_6141 = eq(T_6139, UInt<32>("h06f")) - node T_6143 = and(io.imem.resp.bits.data[0], UInt<32>("h0ffefffff")) - node T_6145 = eq(T_6143, UInt<32>("h073")) - node T_6147 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc00305f")) - node T_6149 = eq(T_6147, UInt<32>("h01013")) - node T_6151 = and(io.imem.resp.bits.data[0], UInt<32>("h0fe00305f")) - node T_6153 = eq(T_6151, UInt<32>("h0101b")) - node T_6155 = and(io.imem.resp.bits.data[0], UInt<32>("h0605b")) - node T_6157 = eq(T_6155, UInt<32>("h02003")) - node T_6159 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f")) - node T_6161 = eq(T_6159, UInt<32>("h02013")) - node T_6163 = and(io.imem.resp.bits.data[0], UInt<32>("h01800607f")) - node T_6165 = eq(T_6163, UInt<32>("h0202f")) - node T_6167 = and(io.imem.resp.bits.data[0], UInt<32>("h0207f")) - node T_6169 = eq(T_6167, UInt<32>("h02073")) - node T_6171 = and(io.imem.resp.bits.data[0], UInt<32>("h0bc00707f")) - node T_6173 = eq(T_6171, UInt<32>("h05013")) - node T_6175 = and(io.imem.resp.bits.data[0], UInt<32>("h0be00705f")) - node T_6177 = eq(T_6175, UInt<32>("h0501b")) - node T_6179 = and(io.imem.resp.bits.data[0], UInt<32>("h0be007077")) - node T_6181 = eq(T_6179, UInt<32>("h05033")) - node T_6183 = and(io.imem.resp.bits.data[0], UInt<32>("h0fe004077")) - node T_6185 = eq(T_6183, UInt<32>("h02004033")) - node T_6187 = and(io.imem.resp.bits.data[0], UInt<32>("h0e800607f")) - node T_6189 = eq(T_6187, UInt<32>("h0800202f")) - node T_6191 = and(io.imem.resp.bits.data[0], UInt<32>("h0ffdfffff")) - node T_6193 = eq(T_6191, UInt<32>("h010000073")) - node T_6195 = and(io.imem.resp.bits.data[0], UInt<32>("h0f9f0607f")) - node T_6197 = eq(T_6195, UInt<32>("h01000202f")) - node T_6199 = and(io.imem.resp.bits.data[0], UInt<32>("h0fff07fff")) - node T_6201 = eq(T_6199, UInt<32>("h010100073")) - node T_6203 = and(io.imem.resp.bits.data[0], UInt<32>("h0f400607f")) - node T_6205 = eq(T_6203, UInt<32>("h020000053")) - node T_6207 = and(io.imem.resp.bits.data[0], UInt<32>("h07c00607f")) - node T_6209 = eq(T_6207, UInt<32>("h020000053")) - node T_6211 = and(io.imem.resp.bits.data[0], UInt<32>("h07c00507f")) - node T_6213 = eq(T_6211, UInt<32>("h020000053")) - node T_6215 = eq(io.imem.resp.bits.data[0], UInt<32>("h030500073")) - node T_6217 = and(io.imem.resp.bits.data[0], UInt<32>("h07ff0007f")) - node T_6219 = eq(T_6217, UInt<32>("h040100053")) - node T_6221 = and(io.imem.resp.bits.data[0], UInt<32>("h07ff0007f")) - node T_6223 = eq(T_6221, UInt<32>("h042000053")) - node T_6225 = and(io.imem.resp.bits.data[0], UInt<32>("h0fdf0007f")) - node T_6227 = eq(T_6225, UInt<32>("h058000053")) - node T_6229 = and(io.imem.resp.bits.data[0], UInt<32>("h0edc0007f")) - node T_6231 = eq(T_6229, UInt<32>("h0c0000053")) - node T_6233 = and(io.imem.resp.bits.data[0], UInt<32>("h0fdf0607f")) - node T_6235 = eq(T_6233, UInt<32>("h0e0000053")) - node T_6237 = and(io.imem.resp.bits.data[0], UInt<32>("h0edf0707f")) - node T_6239 = eq(T_6237, UInt<32>("h0e0000053")) - node T_6241 = and(io.imem.resp.bits.data[0], UInt<32>("h0603f")) - node T_6243 = eq(T_6241, UInt<32>("h023")) - node T_6245 = and(io.imem.resp.bits.data[0], UInt<32>("h0306f")) - node T_6247 = eq(T_6245, UInt<32>("h01063")) - node T_6249 = and(io.imem.resp.bits.data[0], UInt<32>("h0407f")) - node T_6251 = eq(T_6249, UInt<32>("h04063")) - node T_6253 = and(io.imem.resp.bits.data[0], UInt<32>("h0fc007077")) - node T_6255 = eq(T_6253, UInt<32>("h033")) - node T_6257 = or(UInt<1>("h00"), T_6101) - node T_6258 = or(T_6257, T_6105) - node T_6259 = or(T_6258, T_6109) - node T_6260 = or(T_6259, T_6113) - node T_6261 = or(T_6260, T_6117) - node T_6262 = or(T_6261, T_6121) - node T_6263 = or(T_6262, T_6125) - node T_6264 = or(T_6263, T_6129) - node T_6265 = or(T_6264, T_6133) - node T_6266 = or(T_6265, T_6137) - node T_6267 = or(T_6266, T_6141) - node T_6268 = or(T_6267, T_6145) - node T_6269 = or(T_6268, T_6149) - node T_6270 = or(T_6269, T_6153) - node T_6271 = or(T_6270, T_6157) - node T_6272 = or(T_6271, T_6161) - node T_6273 = or(T_6272, T_6165) - node T_6274 = or(T_6273, T_6169) - node T_6275 = or(T_6274, T_6173) - node T_6276 = or(T_6275, T_6177) - node T_6277 = or(T_6276, T_6181) - node T_6278 = or(T_6277, T_6185) - node T_6279 = or(T_6278, T_6189) - node T_6280 = or(T_6279, T_6193) - node T_6281 = or(T_6280, T_6197) - node T_6282 = or(T_6281, T_6201) - node T_6283 = or(T_6282, T_6205) - node T_6284 = or(T_6283, T_6209) - node T_6285 = or(T_6284, T_6213) - node T_6286 = or(T_6285, T_6215) - node T_6287 = or(T_6286, T_6219) - node T_6288 = or(T_6287, T_6223) - node T_6289 = or(T_6288, T_6227) - node T_6290 = or(T_6289, T_6231) - node T_6291 = or(T_6290, T_6235) - node T_6292 = or(T_6291, T_6239) - node T_6293 = or(T_6292, T_6243) - node T_6294 = or(T_6293, T_6247) - node T_6295 = or(T_6294, T_6251) - node T_6296 = or(T_6295, T_6255) - node T_6298 = and(io.imem.resp.bits.data[0], UInt<32>("h05c")) - node T_6300 = eq(T_6298, UInt<32>("h04")) - node T_6302 = and(io.imem.resp.bits.data[0], UInt<32>("h060")) - node T_6304 = eq(T_6302, UInt<32>("h040")) - node T_6306 = or(UInt<1>("h00"), T_6300) - node T_6307 = or(T_6306, T_6304) - node T_6310 = and(io.imem.resp.bits.data[0], UInt<32>("h074")) - node T_6312 = eq(T_6310, UInt<32>("h060")) - node T_6314 = or(UInt<1>("h00"), T_6312) - node T_6316 = and(io.imem.resp.bits.data[0], UInt<32>("h068")) - node T_6318 = eq(T_6316, UInt<32>("h068")) - node T_6320 = or(UInt<1>("h00"), T_6318) - node T_6322 = and(io.imem.resp.bits.data[0], UInt<32>("h0203c")) - node T_6324 = eq(T_6322, UInt<32>("h024")) - node T_6326 = or(UInt<1>("h00"), T_6324) - node T_6328 = and(io.imem.resp.bits.data[0], UInt<32>("h064")) - node T_6330 = eq(T_6328, UInt<32>("h020")) - node T_6332 = and(io.imem.resp.bits.data[0], UInt<32>("h034")) - node T_6334 = eq(T_6332, UInt<32>("h020")) - node T_6336 = and(io.imem.resp.bits.data[0], UInt<32>("h02048")) - node T_6338 = eq(T_6336, UInt<32>("h02008")) - node T_6340 = or(UInt<1>("h00"), T_6330) - node T_6341 = or(T_6340, T_6334) - node T_6342 = or(T_6341, T_6338) - node T_6344 = and(io.imem.resp.bits.data[0], UInt<32>("h044")) - node T_6346 = eq(T_6344, UInt<32>("h00")) - node T_6348 = and(io.imem.resp.bits.data[0], UInt<32>("h04024")) - node T_6350 = eq(T_6348, UInt<32>("h020")) - node T_6352 = and(io.imem.resp.bits.data[0], UInt<32>("h038")) - node T_6354 = eq(T_6352, UInt<32>("h020")) - node T_6356 = and(io.imem.resp.bits.data[0], UInt<32>("h02050")) - node T_6358 = eq(T_6356, UInt<32>("h02000")) - node T_6360 = and(io.imem.resp.bits.data[0], UInt<32>("h090000034")) - node T_6362 = eq(T_6360, UInt<32>("h090000010")) - node T_6364 = or(UInt<1>("h00"), T_6346) - node T_6365 = or(T_6364, T_6350) - node T_6366 = or(T_6365, T_6354) - node T_6367 = or(T_6366, T_6358) - node T_6368 = or(T_6367, T_6362) - node T_6370 = and(io.imem.resp.bits.data[0], UInt<32>("h058")) - node T_6372 = eq(T_6370, UInt<32>("h00")) - node T_6374 = and(io.imem.resp.bits.data[0], UInt<32>("h020")) - node T_6376 = eq(T_6374, UInt<32>("h00")) - node T_6378 = and(io.imem.resp.bits.data[0], UInt<32>("h0c")) - node T_6380 = eq(T_6378, UInt<32>("h04")) - node T_6382 = and(io.imem.resp.bits.data[0], UInt<32>("h048")) - node T_6384 = eq(T_6382, UInt<32>("h048")) - node T_6386 = and(io.imem.resp.bits.data[0], UInt<32>("h04050")) - node T_6388 = eq(T_6386, UInt<32>("h04050")) - node T_6390 = or(UInt<1>("h00"), T_6372) - node T_6391 = or(T_6390, T_6376) - node T_6392 = or(T_6391, T_6380) - node T_6393 = or(T_6392, T_6384) - node T_6394 = or(T_6393, T_6388) - node T_6396 = and(io.imem.resp.bits.data[0], UInt<32>("h048")) - node T_6398 = eq(T_6396, UInt<32>("h00")) - node T_6400 = and(io.imem.resp.bits.data[0], UInt<32>("h018")) - node T_6402 = eq(T_6400, UInt<32>("h00")) - node T_6404 = and(io.imem.resp.bits.data[0], UInt<32>("h04008")) - node T_6406 = eq(T_6404, UInt<32>("h04000")) - node T_6408 = or(UInt<1>("h00"), T_6398) - node T_6409 = or(T_6408, T_6346) - node T_6410 = or(T_6409, T_6402) - node T_6411 = or(T_6410, T_6406) - node T_6412 = cat(T_6411, T_6394) - node T_6414 = and(io.imem.resp.bits.data[0], UInt<32>("h04004")) - node T_6416 = eq(T_6414, UInt<32>("h00")) - node T_6418 = and(io.imem.resp.bits.data[0], UInt<32>("h050")) - node T_6420 = eq(T_6418, UInt<32>("h00")) - node T_6422 = and(io.imem.resp.bits.data[0], UInt<32>("h024")) - node T_6424 = eq(T_6422, UInt<32>("h00")) - node T_6426 = or(UInt<1>("h00"), T_6416) - node T_6427 = or(T_6426, T_6420) - node T_6428 = or(T_6427, T_6346) - node T_6429 = or(T_6428, T_6424) - node T_6430 = or(T_6429, T_6402) - node T_6432 = and(io.imem.resp.bits.data[0], UInt<32>("h034")) - node T_6434 = eq(T_6432, UInt<32>("h014")) - node T_6436 = or(UInt<1>("h00"), T_6434) - node T_6437 = or(T_6436, T_6384) - node T_6438 = cat(T_6437, T_6430) - node T_6440 = and(io.imem.resp.bits.data[0], UInt<32>("h018")) - node T_6442 = eq(T_6440, UInt<32>("h08")) - node T_6444 = and(io.imem.resp.bits.data[0], UInt<32>("h044")) - node T_6446 = eq(T_6444, UInt<32>("h040")) - node T_6448 = or(UInt<1>("h00"), T_6442) - node T_6449 = or(T_6448, T_6446) - node T_6451 = and(io.imem.resp.bits.data[0], UInt<32>("h014")) - node T_6453 = eq(T_6451, UInt<32>("h014")) - node T_6455 = or(UInt<1>("h00"), T_6442) - node T_6456 = or(T_6455, T_6453) - node T_6458 = and(io.imem.resp.bits.data[0], UInt<32>("h030")) - node T_6460 = eq(T_6458, UInt<32>("h00")) - node T_6462 = and(io.imem.resp.bits.data[0], UInt<32>("h0201c")) - node T_6464 = eq(T_6462, UInt<32>("h04")) - node T_6466 = and(io.imem.resp.bits.data[0], UInt<32>("h014")) - node T_6468 = eq(T_6466, UInt<32>("h010")) - node T_6470 = or(UInt<1>("h00"), T_6460) - node T_6471 = or(T_6470, T_6464) - node T_6472 = or(T_6471, T_6468) - node T_6473 = cat(T_6456, T_6449) - node T_6474 = cat(T_6472, T_6473) - node T_6476 = and(io.imem.resp.bits.data[0], UInt<32>("h010")) - node T_6478 = eq(T_6476, UInt<32>("h00")) - node T_6480 = and(io.imem.resp.bits.data[0], UInt<32>("h08")) - node T_6482 = eq(T_6480, UInt<32>("h00")) - node T_6484 = or(UInt<1>("h00"), T_6478) - node T_6485 = or(T_6484, T_6482) - node T_6487 = and(io.imem.resp.bits.data[0], UInt<32>("h03054")) - node T_6489 = eq(T_6487, UInt<32>("h01010")) - node T_6491 = and(io.imem.resp.bits.data[0], UInt<32>("h01058")) - node T_6493 = eq(T_6491, UInt<32>("h01040")) - node T_6495 = and(io.imem.resp.bits.data[0], UInt<32>("h07044")) - node T_6497 = eq(T_6495, UInt<32>("h07000")) - node T_6499 = or(UInt<1>("h00"), T_6489) - node T_6500 = or(T_6499, T_6493) - node T_6501 = or(T_6500, T_6497) - node T_6503 = and(io.imem.resp.bits.data[0], UInt<32>("h04054")) - node T_6505 = eq(T_6503, UInt<32>("h040")) - node T_6507 = and(io.imem.resp.bits.data[0], UInt<32>("h02058")) - node T_6509 = eq(T_6507, UInt<32>("h02040")) - node T_6511 = and(io.imem.resp.bits.data[0], UInt<32>("h03054")) - node T_6513 = eq(T_6511, UInt<32>("h03010")) - node T_6515 = and(io.imem.resp.bits.data[0], UInt<32>("h06054")) - node T_6517 = eq(T_6515, UInt<32>("h06010")) - node T_6519 = and(io.imem.resp.bits.data[0], UInt<32>("h040003034")) - node T_6521 = eq(T_6519, UInt<32>("h040000030")) - node T_6523 = and(io.imem.resp.bits.data[0], UInt<32>("h040001054")) - node T_6525 = eq(T_6523, UInt<32>("h040001010")) - node T_6527 = or(UInt<1>("h00"), T_6505) - node T_6528 = or(T_6527, T_6509) - node T_6529 = or(T_6528, T_6513) - node T_6530 = or(T_6529, T_6517) - node T_6531 = or(T_6530, T_6521) - node T_6532 = or(T_6531, T_6525) - node T_6534 = and(io.imem.resp.bits.data[0], UInt<32>("h02054")) - node T_6536 = eq(T_6534, UInt<32>("h02010")) - node T_6538 = and(io.imem.resp.bits.data[0], UInt<32>("h040004054")) - node T_6540 = eq(T_6538, UInt<32>("h04010")) - node T_6542 = and(io.imem.resp.bits.data[0], UInt<32>("h05054")) - node T_6544 = eq(T_6542, UInt<32>("h04010")) - node T_6546 = and(io.imem.resp.bits.data[0], UInt<32>("h04058")) - node T_6548 = eq(T_6546, UInt<32>("h04040")) - node T_6550 = or(UInt<1>("h00"), T_6536) - node T_6551 = or(T_6550, T_6540) - node T_6552 = or(T_6551, T_6544) - node T_6553 = or(T_6552, T_6548) - node T_6555 = and(io.imem.resp.bits.data[0], UInt<32>("h06054")) - node T_6557 = eq(T_6555, UInt<32>("h02010")) - node T_6559 = and(io.imem.resp.bits.data[0], UInt<32>("h040003054")) - node T_6561 = eq(T_6559, UInt<32>("h040001010")) - node T_6563 = or(UInt<1>("h00"), T_6557) - node T_6564 = or(T_6563, T_6548) - node T_6565 = or(T_6564, T_6521) - node T_6566 = or(T_6565, T_6561) - node T_6567 = cat(T_6532, T_6501) - node T_6568 = cat(T_6553, T_6567) - node T_6569 = cat(T_6566, T_6568) - node T_6571 = and(io.imem.resp.bits.data[0], UInt<32>("h0405f")) - node T_6573 = eq(T_6571, UInt<32>("h03")) - node T_6575 = and(io.imem.resp.bits.data[0], UInt<32>("h0107f")) - node T_6577 = eq(T_6575, UInt<32>("h03")) - node T_6579 = or(UInt<1>("h00"), T_6573) - node T_6580 = or(T_6579, T_6101) - node T_6581 = or(T_6580, T_6577) - node T_6582 = or(T_6581, T_6157) - node T_6583 = or(T_6582, T_6165) - node T_6584 = or(T_6583, T_6189) - node T_6585 = or(T_6584, T_6197) - node T_6587 = and(io.imem.resp.bits.data[0], UInt<32>("h028")) - node T_6589 = eq(T_6587, UInt<32>("h020")) - node T_6591 = and(io.imem.resp.bits.data[0], UInt<32>("h018000020")) - node T_6593 = eq(T_6591, UInt<32>("h018000020")) - node T_6595 = and(io.imem.resp.bits.data[0], UInt<32>("h020000020")) - node T_6597 = eq(T_6595, UInt<32>("h020000020")) - node T_6599 = or(UInt<1>("h00"), T_6589) - node T_6600 = or(T_6599, T_6593) - node T_6601 = or(T_6600, T_6597) - node T_6603 = and(io.imem.resp.bits.data[0], UInt<32>("h010000008")) - node T_6605 = eq(T_6603, UInt<32>("h010000008")) - node T_6607 = and(io.imem.resp.bits.data[0], UInt<32>("h040000008")) - node T_6609 = eq(T_6607, UInt<32>("h040000008")) - node T_6611 = or(UInt<1>("h00"), T_6605) - node T_6612 = or(T_6611, T_6609) - node T_6614 = and(io.imem.resp.bits.data[0], UInt<32>("h08000008")) - node T_6616 = eq(T_6614, UInt<32>("h08000008")) - node T_6618 = and(io.imem.resp.bits.data[0], UInt<32>("h080000008")) - node T_6620 = eq(T_6618, UInt<32>("h080000008")) - node T_6622 = or(UInt<1>("h00"), T_6616) - node T_6623 = or(T_6622, T_6605) - node T_6624 = or(T_6623, T_6620) - node T_6626 = and(io.imem.resp.bits.data[0], UInt<32>("h018000008")) - node T_6628 = eq(T_6626, UInt<32>("h08")) - node T_6630 = or(UInt<1>("h00"), T_6628) - node T_6632 = cat(T_6612, T_6601) - node T_6633 = cat(T_6624, T_6632) - node T_6634 = cat(T_6630, T_6633) - node T_6635 = cat(UInt<1>("h00"), T_6634) - node T_6637 = and(io.imem.resp.bits.data[0], UInt<32>("h01000")) - node T_6639 = eq(T_6637, UInt<32>("h01000")) - node T_6641 = or(UInt<1>("h00"), T_6639) - node T_6643 = and(io.imem.resp.bits.data[0], UInt<32>("h02000")) - node T_6645 = eq(T_6643, UInt<32>("h02000")) - node T_6647 = or(UInt<1>("h00"), T_6645) - node T_6649 = and(io.imem.resp.bits.data[0], UInt<32>("h04000")) - node T_6651 = eq(T_6649, UInt<32>("h04000")) - node T_6653 = or(UInt<1>("h00"), T_6651) - node T_6654 = cat(T_6647, T_6641) - node T_6655 = cat(T_6653, T_6654) - node T_6657 = and(io.imem.resp.bits.data[0], UInt<32>("h080000060")) - node T_6659 = eq(T_6657, UInt<32>("h040")) - node T_6661 = and(io.imem.resp.bits.data[0], UInt<32>("h010000060")) - node T_6663 = eq(T_6661, UInt<32>("h040")) - node T_6665 = and(io.imem.resp.bits.data[0], UInt<32>("h070")) - node T_6667 = eq(T_6665, UInt<32>("h040")) - node T_6669 = or(UInt<1>("h00"), T_6659) - node T_6670 = or(T_6669, T_6663) - node T_6671 = or(T_6670, T_6667) - node T_6673 = and(io.imem.resp.bits.data[0], UInt<32>("h07c")) - node T_6675 = eq(T_6673, UInt<32>("h024")) - node T_6677 = and(io.imem.resp.bits.data[0], UInt<32>("h040000060")) - node T_6679 = eq(T_6677, UInt<32>("h040")) - node T_6681 = and(io.imem.resp.bits.data[0], UInt<32>("h090000060")) - node T_6683 = eq(T_6681, UInt<32>("h010000040")) - node T_6685 = or(UInt<1>("h00"), T_6675) - node T_6686 = or(T_6685, T_6679) - node T_6687 = or(T_6686, T_6667) - node T_6688 = or(T_6687, T_6683) - node T_6690 = or(UInt<1>("h00"), T_6667) - node T_6692 = and(io.imem.resp.bits.data[0], UInt<32>("h03c")) - node T_6694 = eq(T_6692, UInt<32>("h04")) - node T_6696 = and(io.imem.resp.bits.data[0], UInt<32>("h010000060")) - node T_6698 = eq(T_6696, UInt<32>("h010000040")) - node T_6700 = or(UInt<1>("h00"), T_6694) - node T_6701 = or(T_6700, T_6659) - node T_6702 = or(T_6701, T_6667) - node T_6703 = or(T_6702, T_6698) - node T_6705 = and(io.imem.resp.bits.data[0], UInt<32>("h02000074")) - node T_6707 = eq(T_6705, UInt<32>("h02000030")) - node T_6709 = or(UInt<1>("h00"), T_6707) - node T_6711 = and(io.imem.resp.bits.data[0], UInt<32>("h064")) - node T_6713 = eq(T_6711, UInt<32>("h00")) - node T_6715 = and(io.imem.resp.bits.data[0], UInt<32>("h050")) - node T_6717 = eq(T_6715, UInt<32>("h010")) - node T_6719 = and(io.imem.resp.bits.data[0], UInt<32>("h02024")) - node T_6721 = eq(T_6719, UInt<32>("h024")) - node T_6723 = and(io.imem.resp.bits.data[0], UInt<32>("h028")) - node T_6725 = eq(T_6723, UInt<32>("h028")) - node T_6727 = and(io.imem.resp.bits.data[0], UInt<32>("h01030")) - node T_6729 = eq(T_6727, UInt<32>("h01030")) - node T_6731 = and(io.imem.resp.bits.data[0], UInt<32>("h02030")) - node T_6733 = eq(T_6731, UInt<32>("h02030")) - node T_6735 = and(io.imem.resp.bits.data[0], UInt<32>("h090000010")) - node T_6737 = eq(T_6735, UInt<32>("h080000010")) - node T_6739 = or(UInt<1>("h00"), T_6713) - node T_6740 = or(T_6739, T_6717) - node T_6741 = or(T_6740, T_6721) - node T_6742 = or(T_6741, T_6725) - node T_6743 = or(T_6742, T_6729) - node T_6744 = or(T_6743, T_6733) - node T_6745 = or(T_6744, T_6737) - node T_6747 = and(io.imem.resp.bits.data[0], UInt<32>("h01070")) - node T_6749 = eq(T_6747, UInt<32>("h01070")) - node T_6751 = or(UInt<1>("h00"), T_6749) - node T_6753 = and(io.imem.resp.bits.data[0], UInt<32>("h02070")) - node T_6755 = eq(T_6753, UInt<32>("h02070")) - node T_6757 = or(UInt<1>("h00"), T_6755) - node T_6759 = and(io.imem.resp.bits.data[0], UInt<32>("h03070")) - node T_6761 = eq(T_6759, UInt<32>("h070")) - node T_6763 = or(UInt<1>("h00"), T_6761) - node T_6764 = cat(T_6757, T_6751) - node T_6765 = cat(T_6763, T_6764) - node T_6767 = and(io.imem.resp.bits.data[0], UInt<32>("h03058")) - node T_6769 = eq(T_6767, UInt<32>("h01008")) - node T_6771 = or(UInt<1>("h00"), T_6769) - node T_6773 = and(io.imem.resp.bits.data[0], UInt<32>("h03058")) - node T_6775 = eq(T_6773, UInt<32>("h08")) - node T_6777 = or(UInt<1>("h00"), T_6775) - node T_6779 = and(io.imem.resp.bits.data[0], UInt<32>("h06048")) - node T_6781 = eq(T_6779, UInt<32>("h02008")) - node T_6783 = or(UInt<1>("h00"), T_6781) - id_ctrl.legal <= T_6296 - id_ctrl.fp <= T_6307 - id_ctrl.rocc <= UInt<1>("h00") - id_ctrl.branch <= T_6314 - id_ctrl.jal <= T_6320 - id_ctrl.jalr <= T_6326 - id_ctrl.rxs2 <= T_6342 - id_ctrl.rxs1 <= T_6368 - id_ctrl.sel_alu2 <= T_6412 - id_ctrl.sel_alu1 <= T_6438 - id_ctrl.sel_imm <= T_6474 - id_ctrl.alu_dw <= T_6485 - id_ctrl.alu_fn <= T_6569 - id_ctrl.mem <= T_6585 - id_ctrl.mem_cmd <= T_6635 - id_ctrl.mem_type <= T_6655 - id_ctrl.rfs1 <= T_6671 - id_ctrl.rfs2 <= T_6688 - id_ctrl.rfs3 <= T_6690 - id_ctrl.wfd <= T_6703 - id_ctrl.div <= T_6709 - id_ctrl.wxd <= T_6745 - id_ctrl.csr <= T_6765 - id_ctrl.fence_i <= T_6771 - id_ctrl.fence <= T_6777 - id_ctrl.amo <= T_6783 + id_ctrl.branch <= T_6286 + id_ctrl.jal <= T_6292 + id_ctrl.jalr <= T_6298 + id_ctrl.rxs2 <= T_6314 + id_ctrl.rxs1 <= T_6340 + id_ctrl.sel_alu2 <= T_6384 + id_ctrl.sel_alu1 <= T_6410 + id_ctrl.sel_imm <= T_6446 + id_ctrl.alu_dw <= T_6457 + id_ctrl.alu_fn <= T_6541 + id_ctrl.mem <= T_6557 + id_ctrl.mem_cmd <= T_6607 + id_ctrl.mem_type <= T_6627 + id_ctrl.rfs1 <= T_6643 + id_ctrl.rfs2 <= T_6660 + id_ctrl.rfs3 <= T_6662 + id_ctrl.wfd <= T_6675 + id_ctrl.div <= T_6681 + id_ctrl.wxd <= T_6717 + id_ctrl.csr <= T_6737 + id_ctrl.fence_i <= T_6743 + id_ctrl.fence <= T_6749 + id_ctrl.amo <= T_6755 node id_raddr3 = bits(io.imem.resp.bits.data[0], 31, 27) node id_raddr2 = bits(io.imem.resp.bits.data[0], 24, 20) node id_raddr1 = bits(io.imem.resp.bits.data[0], 19, 15) node id_waddr = bits(io.imem.resp.bits.data[0], 11, 7) wire id_load_use : UInt<1> - id_load_use <= UInt<1>("h00") - reg id_reg_fence : UInt<1>, clk, reset, UInt<1>("h00") - cmem T_6795 : UInt<64>[31] - wire T_6797 : UInt<?> - T_6797 <= UInt<1>("h00") - node T_6801 = eq(id_raddr1, UInt<1>("h00")) - node T_6802 = and(UInt<1>("h00"), T_6801) - node T_6804 = bits(id_raddr1, 4, 0) - node T_6805 = not(T_6804) - infer mport T_6806 = T_6795[T_6805], clk - node T_6807 = mux(T_6802, UInt<1>("h00"), T_6806) - T_6797 <= T_6807 - wire T_6809 : UInt<?> - T_6809 <= UInt<1>("h00") - node T_6813 = eq(id_raddr2, UInt<1>("h00")) - node T_6814 = and(UInt<1>("h00"), T_6813) - node T_6816 = bits(id_raddr2, 4, 0) - node T_6817 = not(T_6816) - infer mport T_6818 = T_6795[T_6817], clk - node T_6819 = mux(T_6814, UInt<1>("h00"), T_6818) - T_6809 <= T_6819 + id_load_use is invalid + reg id_reg_fence : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + cmem T_6766 : UInt<64>[31] + wire T_6768 : UInt<?> + T_6768 is invalid + node T_6771 = eq(id_raddr1, UInt<1>("h00")) + node T_6772 = and(UInt<1>("h00"), T_6771) + node T_6774 = bits(id_raddr1, 4, 0) + node T_6775 = not(T_6774) + infer mport T_6776 = T_6766[T_6775], clk + node T_6777 = mux(T_6772, UInt<1>("h00"), T_6776) + T_6768 <= T_6777 + wire T_6779 : UInt<?> + T_6779 is invalid + node T_6782 = eq(id_raddr2, UInt<1>("h00")) + node T_6783 = and(UInt<1>("h00"), T_6782) + node T_6785 = bits(id_raddr2, 4, 0) + node T_6786 = not(T_6785) + infer mport T_6787 = T_6766[T_6786], clk + node T_6788 = mux(T_6783, UInt<1>("h00"), T_6787) + T_6779 <= T_6788 wire ctrl_killd : UInt<1> - ctrl_killd <= UInt<1>("h00") + ctrl_killd is invalid inst csr of CSRFile - csr.io.rocc.dma.resp.ready <= UInt<1>("h00") - csr.io.rocc.dma.req.bits.size <= UInt<1>("h00") - csr.io.rocc.dma.req.bits.length <= UInt<1>("h00") - csr.io.rocc.dma.req.bits.dest <= UInt<1>("h00") - csr.io.rocc.dma.req.bits.source <= UInt<1>("h00") - csr.io.rocc.dma.req.bits.cmd <= UInt<1>("h00") - csr.io.rocc.dma.req.bits.client_xact_id <= UInt<1>("h00") - csr.io.rocc.dma.req.valid <= UInt<1>("h00") - csr.io.rocc.fpu_resp.ready <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.in3 <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.in2 <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.in1 <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.typ <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.rm <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.wflags <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.round <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.sqrt <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.div <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.fma <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.fastpipe <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.toint <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.fromint <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.single <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.swap23 <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.swap12 <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.ren3 <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.ren2 <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.ren1 <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.wen <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.ldst <= UInt<1>("h00") - csr.io.rocc.fpu_req.bits.cmd <= UInt<1>("h00") - csr.io.rocc.fpu_req.valid <= UInt<1>("h00") - csr.io.rocc.pptw.req.bits.fetch <= UInt<1>("h00") - csr.io.rocc.pptw.req.bits.store <= UInt<1>("h00") - csr.io.rocc.pptw.req.bits.prv <= UInt<1>("h00") - csr.io.rocc.pptw.req.bits.addr <= UInt<1>("h00") - csr.io.rocc.pptw.req.valid <= UInt<1>("h00") - csr.io.rocc.dptw.req.bits.fetch <= UInt<1>("h00") - csr.io.rocc.dptw.req.bits.store <= UInt<1>("h00") - csr.io.rocc.dptw.req.bits.prv <= UInt<1>("h00") - csr.io.rocc.dptw.req.bits.addr <= UInt<1>("h00") - csr.io.rocc.dptw.req.valid <= UInt<1>("h00") - csr.io.rocc.iptw.req.bits.fetch <= UInt<1>("h00") - csr.io.rocc.iptw.req.bits.store <= UInt<1>("h00") - csr.io.rocc.iptw.req.bits.prv <= UInt<1>("h00") - csr.io.rocc.iptw.req.bits.addr <= UInt<1>("h00") - csr.io.rocc.iptw.req.valid <= UInt<1>("h00") - csr.io.rocc.autl.grant.ready <= UInt<1>("h00") - csr.io.rocc.autl.acquire.bits.data <= UInt<1>("h00") - csr.io.rocc.autl.acquire.bits.union <= UInt<1>("h00") - csr.io.rocc.autl.acquire.bits.a_type <= UInt<1>("h00") - csr.io.rocc.autl.acquire.bits.is_builtin_type <= UInt<1>("h00") - csr.io.rocc.autl.acquire.bits.addr_beat <= UInt<1>("h00") - csr.io.rocc.autl.acquire.bits.client_xact_id <= UInt<1>("h00") - csr.io.rocc.autl.acquire.bits.addr_block <= UInt<1>("h00") - csr.io.rocc.autl.acquire.valid <= UInt<1>("h00") - csr.io.rocc.interrupt <= UInt<1>("h00") - csr.io.rocc.busy <= UInt<1>("h00") - csr.io.rocc.mem.invalidate_lr <= UInt<1>("h00") - csr.io.rocc.mem.req.bits.data <= UInt<1>("h00") - csr.io.rocc.mem.req.bits.phys <= UInt<1>("h00") - csr.io.rocc.mem.req.bits.kill <= UInt<1>("h00") - csr.io.rocc.mem.req.bits.typ <= UInt<1>("h00") - csr.io.rocc.mem.req.bits.cmd <= UInt<1>("h00") - csr.io.rocc.mem.req.bits.tag <= UInt<1>("h00") - csr.io.rocc.mem.req.bits.addr <= UInt<1>("h00") - csr.io.rocc.mem.req.valid <= UInt<1>("h00") - csr.io.rocc.resp.bits.data <= UInt<1>("h00") - csr.io.rocc.resp.bits.rd <= UInt<1>("h00") - csr.io.rocc.resp.valid <= UInt<1>("h00") - csr.io.rocc.cmd.ready <= UInt<1>("h00") - csr.io.fcsr_flags.bits <= UInt<1>("h00") - csr.io.fcsr_flags.valid <= UInt<1>("h00") - csr.io.pc <= UInt<1>("h00") - csr.io.cause <= UInt<1>("h00") - csr.io.uarch_counters[0] <= UInt<1>("h00") - csr.io.uarch_counters[1] <= UInt<1>("h00") - csr.io.uarch_counters[2] <= UInt<1>("h00") - csr.io.uarch_counters[3] <= UInt<1>("h00") - csr.io.uarch_counters[4] <= UInt<1>("h00") - csr.io.uarch_counters[5] <= UInt<1>("h00") - csr.io.uarch_counters[6] <= UInt<1>("h00") - csr.io.uarch_counters[7] <= UInt<1>("h00") - csr.io.uarch_counters[8] <= UInt<1>("h00") - csr.io.uarch_counters[9] <= UInt<1>("h00") - csr.io.uarch_counters[10] <= UInt<1>("h00") - csr.io.uarch_counters[11] <= UInt<1>("h00") - csr.io.uarch_counters[12] <= UInt<1>("h00") - csr.io.uarch_counters[13] <= UInt<1>("h00") - csr.io.uarch_counters[14] <= UInt<1>("h00") - csr.io.uarch_counters[15] <= UInt<1>("h00") - csr.io.retire <= UInt<1>("h00") - csr.io.exception <= UInt<1>("h00") - csr.io.rw.wdata <= UInt<1>("h00") - csr.io.rw.cmd <= UInt<1>("h00") - csr.io.rw.addr <= UInt<1>("h00") - csr.io.host.csr.resp.ready <= UInt<1>("h00") - csr.io.host.csr.req.bits.data <= UInt<1>("h00") - csr.io.host.csr.req.bits.addr <= UInt<1>("h00") - csr.io.host.csr.req.bits.rw <= UInt<1>("h00") - csr.io.host.csr.req.valid <= UInt<1>("h00") - csr.io.host.id <= UInt<1>("h00") - csr.io.host.reset <= UInt<1>("h00") + csr.io is invalid csr.clk <= clk csr.reset <= reset node id_csr_en = neq(id_ctrl.csr, UInt<3>("h00")) node id_system_insn = eq(id_ctrl.csr, UInt<3>("h04")) - node T_6929 = eq(id_ctrl.csr, UInt<3>("h02")) - node T_6930 = eq(id_ctrl.csr, UInt<3>("h03")) - node T_6931 = or(T_6929, T_6930) - node T_6933 = eq(id_raddr1, UInt<1>("h00")) - node id_csr_ren = and(T_6931, T_6933) + node T_6794 = eq(id_ctrl.csr, UInt<3>("h02")) + node T_6795 = eq(id_ctrl.csr, UInt<3>("h03")) + node T_6796 = or(T_6794, T_6795) + node T_6798 = eq(id_raddr1, UInt<1>("h00")) + node id_csr_ren = and(T_6796, T_6798) node id_csr = mux(id_csr_ren, UInt<3>("h05"), id_ctrl.csr) node id_csr_addr = bits(io.imem.resp.bits.data[0], 31, 20) - node T_6938 = eq(id_csr_ren, UInt<1>("h00")) - node T_6939 = and(id_csr_en, T_6938) - node T_6998 = and(id_csr_addr, UInt<12>("h08c4")) - node T_7000 = eq(T_6998, UInt<12>("h040")) - node T_7002 = or(UInt<1>("h00"), T_7000) - node T_7003 = bit(T_7002, 0) - node T_7005 = eq(T_7003, UInt<1>("h00")) - node T_7006 = and(T_6939, T_7005) - node id_csr_flush = or(id_system_insn, T_7006) - node T_7009 = eq(id_ctrl.legal, UInt<1>("h00")) - node T_7011 = neq(csr.io.status.fs, UInt<1>("h00")) - node T_7013 = eq(T_7011, UInt<1>("h00")) - node T_7014 = and(id_ctrl.fp, T_7013) - node T_7015 = or(T_7009, T_7014) - node T_7017 = neq(csr.io.status.xs, UInt<1>("h00")) - node T_7019 = eq(T_7017, UInt<1>("h00")) - node T_7020 = and(id_ctrl.rocc, T_7019) - node id_illegal_insn = or(T_7015, T_7020) - node id_amo_aq = bit(io.imem.resp.bits.data[0], 26) - node id_amo_rl = bit(io.imem.resp.bits.data[0], 25) - node T_7024 = and(id_ctrl.amo, id_amo_rl) - node id_fence_next = or(id_ctrl.fence, T_7024) - node T_7027 = eq(io.dmem.ordered, UInt<1>("h00")) - node id_mem_busy = or(T_7027, io.dmem.req.valid) - node T_7030 = and(ex_reg_valid, ex_ctrl.rocc) - node T_7031 = or(io.rocc.busy, T_7030) - node T_7032 = and(mem_reg_valid, mem_ctrl.rocc) - node T_7033 = or(T_7031, T_7032) - node T_7034 = and(wb_reg_valid, wb_ctrl.rocc) - node T_7035 = or(T_7033, T_7034) - node id_rocc_busy = and(UInt<1>("h00"), T_7035) - node T_7037 = and(id_reg_fence, id_mem_busy) - node T_7038 = or(id_fence_next, T_7037) - id_reg_fence <= T_7038 - node T_7039 = and(id_rocc_busy, id_ctrl.fence) - node T_7040 = and(id_ctrl.amo, id_amo_aq) - node T_7041 = or(T_7040, id_ctrl.fence_i) - node T_7042 = or(id_ctrl.mem, id_ctrl.rocc) - node T_7043 = and(id_reg_fence, T_7042) - node T_7044 = or(T_7041, T_7043) - node T_7045 = or(T_7044, id_csr_en) - node T_7046 = and(id_mem_busy, T_7045) - node id_do_fence = or(T_7039, T_7046) - node T_7050 = or(csr.io.interrupt, io.imem.resp.bits.xcpt_if) - node id_xcpt = or(T_7050, id_illegal_insn) - node T_7052 = mux(io.imem.resp.bits.xcpt_if, UInt<1>("h01"), UInt<2>("h02")) - node id_cause = mux(csr.io.interrupt, csr.io.interrupt_cause, T_7052) + node T_6803 = eq(id_csr_ren, UInt<1>("h00")) + node T_6804 = and(id_csr_en, T_6803) + node T_6863 = and(id_csr_addr, UInt<12>("h08c4")) + node T_6865 = eq(T_6863, UInt<12>("h040")) + node T_6867 = or(UInt<1>("h00"), T_6865) + node T_6868 = bits(T_6867, 0, 0) + node T_6870 = eq(T_6868, UInt<1>("h00")) + node T_6871 = and(T_6804, T_6870) + node id_csr_flush = or(id_system_insn, T_6871) + node T_6874 = eq(id_ctrl.legal, UInt<1>("h00")) + node T_6876 = neq(csr.io.status.fs, UInt<1>("h00")) + node T_6878 = eq(T_6876, UInt<1>("h00")) + node T_6879 = and(id_ctrl.fp, T_6878) + node T_6880 = or(T_6874, T_6879) + node T_6882 = neq(csr.io.status.xs, UInt<1>("h00")) + node T_6884 = eq(T_6882, UInt<1>("h00")) + node T_6885 = and(id_ctrl.rocc, T_6884) + node id_illegal_insn = or(T_6880, T_6885) + node id_amo_aq = bits(io.imem.resp.bits.data[0], 26, 26) + node id_amo_rl = bits(io.imem.resp.bits.data[0], 25, 25) + node T_6889 = and(id_ctrl.amo, id_amo_rl) + node id_fence_next = or(id_ctrl.fence, T_6889) + node T_6892 = eq(io.dmem.ordered, UInt<1>("h00")) + node id_mem_busy = or(T_6892, io.dmem.req.valid) + node T_6895 = and(ex_reg_valid, ex_ctrl.rocc) + node T_6896 = or(io.rocc.busy, T_6895) + node T_6897 = and(mem_reg_valid, mem_ctrl.rocc) + node T_6898 = or(T_6896, T_6897) + node T_6899 = and(wb_reg_valid, wb_ctrl.rocc) + node T_6900 = or(T_6898, T_6899) + node id_rocc_busy = and(UInt<1>("h00"), T_6900) + node T_6902 = and(id_reg_fence, id_mem_busy) + node T_6903 = or(id_fence_next, T_6902) + id_reg_fence <= T_6903 + node T_6904 = and(id_rocc_busy, id_ctrl.fence) + node T_6905 = and(id_ctrl.amo, id_amo_aq) + node T_6906 = or(T_6905, id_ctrl.fence_i) + node T_6907 = or(id_ctrl.mem, id_ctrl.rocc) + node T_6908 = and(id_reg_fence, T_6907) + node T_6909 = or(T_6906, T_6908) + node T_6910 = or(T_6909, id_csr_en) + node T_6911 = and(id_mem_busy, T_6910) + node id_do_fence = or(T_6904, T_6911) + node T_6915 = or(csr.io.interrupt, io.imem.resp.bits.xcpt_if) + node id_xcpt = or(T_6915, id_illegal_insn) + node T_6917 = mux(io.imem.resp.bits.xcpt_if, UInt<1>("h01"), UInt<2>("h02")) + node id_cause = mux(csr.io.interrupt, csr.io.interrupt_cause, T_6917) node ex_waddr = bits(ex_reg_inst, 11, 7) node mem_waddr = bits(mem_reg_inst, 11, 7) node wb_waddr = bits(wb_reg_inst, 11, 7) - node T_7060 = and(ex_reg_valid, ex_ctrl.wxd) - node T_7061 = and(mem_reg_valid, mem_ctrl.wxd) - node T_7063 = eq(mem_ctrl.mem, UInt<1>("h00")) - node T_7064 = and(T_7061, T_7063) - node T_7065 = and(mem_reg_valid, mem_ctrl.wxd) - node T_7066 = eq(UInt<1>("h00"), id_raddr1) - node T_7067 = and(UInt<1>("h01"), T_7066) - node T_7068 = eq(ex_waddr, id_raddr1) - node T_7069 = and(T_7060, T_7068) - node T_7070 = eq(mem_waddr, id_raddr1) - node T_7071 = and(T_7064, T_7070) - node T_7072 = eq(mem_waddr, id_raddr1) - node T_7073 = and(T_7065, T_7072) - node T_7074 = eq(UInt<1>("h00"), id_raddr2) - node T_7075 = and(UInt<1>("h01"), T_7074) - node T_7076 = eq(ex_waddr, id_raddr2) - node T_7077 = and(T_7060, T_7076) - node T_7078 = eq(mem_waddr, id_raddr2) - node T_7079 = and(T_7064, T_7078) - node T_7080 = eq(mem_waddr, id_raddr2) - node T_7081 = and(T_7065, T_7080) + node T_6925 = and(ex_reg_valid, ex_ctrl.wxd) + node T_6926 = and(mem_reg_valid, mem_ctrl.wxd) + node T_6928 = eq(mem_ctrl.mem, UInt<1>("h00")) + node T_6929 = and(T_6926, T_6928) + node T_6930 = and(mem_reg_valid, mem_ctrl.wxd) + node T_6931 = eq(UInt<1>("h00"), id_raddr1) + node T_6932 = and(UInt<1>("h01"), T_6931) + node T_6933 = eq(ex_waddr, id_raddr1) + node T_6934 = and(T_6925, T_6933) + node T_6935 = eq(mem_waddr, id_raddr1) + node T_6936 = and(T_6929, T_6935) + node T_6937 = eq(mem_waddr, id_raddr1) + node T_6938 = and(T_6930, T_6937) + node T_6939 = eq(UInt<1>("h00"), id_raddr2) + node T_6940 = and(UInt<1>("h01"), T_6939) + node T_6941 = eq(ex_waddr, id_raddr2) + node T_6942 = and(T_6925, T_6941) + node T_6943 = eq(mem_waddr, id_raddr2) + node T_6944 = and(T_6929, T_6943) + node T_6945 = eq(mem_waddr, id_raddr2) + node T_6946 = and(T_6930, T_6945) wire bypass_mux : UInt<?>[4] bypass_mux[0] <= UInt<1>("h00") bypass_mux[1] <= mem_reg_wdata bypass_mux[2] <= wb_reg_wdata bypass_mux[3] <= io.dmem.resp.bits.data_word_bypass - reg ex_reg_rs_bypass : UInt<1>[2], clk, UInt<1>("h00"), ex_reg_rs_bypass - reg ex_reg_rs_lsb : UInt<?>[2], clk, UInt<1>("h00"), ex_reg_rs_lsb - reg ex_reg_rs_msb : UInt<?>[2], clk, UInt<1>("h00"), ex_reg_rs_msb - node T_7126 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0]) - node T_7127 = mux(ex_reg_rs_bypass[0], bypass_mux[ex_reg_rs_lsb[0]], T_7126) - node T_7129 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1]) - node T_7130 = mux(ex_reg_rs_bypass[1], bypass_mux[ex_reg_rs_lsb[1]], T_7129) - node T_7131 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) - node T_7133 = bit(ex_reg_inst, 31) - node T_7134 = asSInt(T_7133) - node T_7135 = mux(T_7131, asSInt(UInt<1>("h00")), T_7134) - node T_7136 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) - node T_7137 = bits(ex_reg_inst, 30, 20) - node T_7138 = asSInt(T_7137) - node T_7139 = mux(T_7136, T_7138, T_7135) - node T_7140 = neq(ex_ctrl.sel_imm, UInt<3>("h02")) - node T_7141 = neq(ex_ctrl.sel_imm, UInt<3>("h03")) - node T_7142 = and(T_7140, T_7141) - node T_7143 = bits(ex_reg_inst, 19, 12) - node T_7144 = asSInt(T_7143) - node T_7145 = mux(T_7142, T_7135, T_7144) - node T_7146 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) - node T_7147 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) - node T_7148 = or(T_7146, T_7147) - node T_7150 = eq(ex_ctrl.sel_imm, UInt<3>("h03")) - node T_7151 = bit(ex_reg_inst, 20) - node T_7152 = asSInt(T_7151) - node T_7153 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) - node T_7154 = bit(ex_reg_inst, 7) - node T_7155 = asSInt(T_7154) - node T_7156 = mux(T_7153, T_7155, T_7135) - node T_7157 = mux(T_7150, T_7152, T_7156) - node T_7158 = mux(T_7148, asSInt(UInt<1>("h00")), T_7157) - node T_7159 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) - node T_7160 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) - node T_7161 = or(T_7159, T_7160) - node T_7163 = bits(ex_reg_inst, 30, 25) - node T_7164 = mux(T_7161, UInt<1>("h00"), T_7163) - node T_7165 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) - node T_7167 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) - node T_7168 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) - node T_7169 = or(T_7167, T_7168) - node T_7170 = bits(ex_reg_inst, 11, 8) - node T_7171 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) - node T_7172 = bits(ex_reg_inst, 19, 16) - node T_7173 = bits(ex_reg_inst, 24, 21) - node T_7174 = mux(T_7171, T_7172, T_7173) - node T_7175 = mux(T_7169, T_7170, T_7174) - node T_7176 = mux(T_7165, UInt<1>("h00"), T_7175) - node T_7177 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) - node T_7178 = bit(ex_reg_inst, 7) - node T_7179 = eq(ex_ctrl.sel_imm, UInt<3>("h04")) - node T_7180 = bit(ex_reg_inst, 20) - node T_7181 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) - node T_7182 = bit(ex_reg_inst, 15) - node T_7184 = shl(T_7182, 0) - node T_7185 = mux(T_7181, T_7184, UInt<1>("h00")) - node T_7186 = shl(T_7180, 0) - node T_7187 = mux(T_7179, T_7186, T_7185) - node T_7188 = shl(T_7178, 0) - node T_7189 = mux(T_7177, T_7188, T_7187) - node T_7190 = asUInt(T_7135) - node T_7191 = asUInt(T_7139) - node T_7192 = asUInt(T_7145) - node T_7193 = cat(T_7191, T_7192) - node T_7194 = cat(T_7190, T_7193) - node T_7195 = asUInt(T_7158) - node T_7196 = cat(T_7195, T_7164) - node T_7197 = cat(T_7176, T_7189) - node T_7198 = cat(T_7196, T_7197) - node T_7199 = cat(T_7194, T_7198) - node ex_imm = asSInt(T_7199) - node T_7202 = asSInt(T_7127) - node T_7203 = asSInt(ex_reg_pc) - node T_7204 = eq(UInt<2>("h02"), ex_ctrl.sel_alu1) - node T_7205 = mux(T_7204, T_7203, asSInt(UInt<1>("h00"))) - node T_7206 = eq(UInt<2>("h01"), ex_ctrl.sel_alu1) - node ex_op1 = mux(T_7206, T_7202, T_7205) - node T_7209 = asSInt(T_7130) - node T_7211 = eq(UInt<2>("h01"), ex_ctrl.sel_alu2) - node T_7212 = mux(T_7211, asSInt(UInt<4>("h04")), asSInt(UInt<1>("h00"))) - node T_7213 = eq(UInt<2>("h03"), ex_ctrl.sel_alu2) - node T_7214 = mux(T_7213, ex_imm, T_7212) - node T_7215 = eq(UInt<2>("h02"), ex_ctrl.sel_alu2) - node ex_op2 = mux(T_7215, T_7209, T_7214) + reg ex_reg_rs_bypass : UInt<1>[2], clk + reg ex_reg_rs_lsb : UInt<?>[2], clk + reg ex_reg_rs_msb : UInt<?>[2], clk + node T_6991 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0]) + node T_6992 = mux(ex_reg_rs_bypass[0], bypass_mux[ex_reg_rs_lsb[0]], T_6991) + node T_6994 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1]) + node T_6995 = mux(ex_reg_rs_bypass[1], bypass_mux[ex_reg_rs_lsb[1]], T_6994) + node T_6996 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) + node T_6998 = bits(ex_reg_inst, 31, 31) + node T_6999 = asSInt(T_6998) + node T_7000 = mux(T_6996, asSInt(UInt<1>("h00")), T_6999) + node T_7001 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) + node T_7002 = bits(ex_reg_inst, 30, 20) + node T_7003 = asSInt(T_7002) + node T_7004 = mux(T_7001, T_7003, T_7000) + node T_7005 = neq(ex_ctrl.sel_imm, UInt<3>("h02")) + node T_7006 = neq(ex_ctrl.sel_imm, UInt<3>("h03")) + node T_7007 = and(T_7005, T_7006) + node T_7008 = bits(ex_reg_inst, 19, 12) + node T_7009 = asSInt(T_7008) + node T_7010 = mux(T_7007, T_7000, T_7009) + node T_7011 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) + node T_7012 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) + node T_7013 = or(T_7011, T_7012) + node T_7015 = eq(ex_ctrl.sel_imm, UInt<3>("h03")) + node T_7016 = bits(ex_reg_inst, 20, 20) + node T_7017 = asSInt(T_7016) + node T_7018 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) + node T_7019 = bits(ex_reg_inst, 7, 7) + node T_7020 = asSInt(T_7019) + node T_7021 = mux(T_7018, T_7020, T_7000) + node T_7022 = mux(T_7015, T_7017, T_7021) + node T_7023 = mux(T_7013, asSInt(UInt<1>("h00")), T_7022) + node T_7024 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) + node T_7025 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) + node T_7026 = or(T_7024, T_7025) + node T_7028 = bits(ex_reg_inst, 30, 25) + node T_7029 = mux(T_7026, UInt<1>("h00"), T_7028) + node T_7030 = eq(ex_ctrl.sel_imm, UInt<3>("h02")) + node T_7032 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) + node T_7033 = eq(ex_ctrl.sel_imm, UInt<3>("h01")) + node T_7034 = or(T_7032, T_7033) + node T_7035 = bits(ex_reg_inst, 11, 8) + node T_7036 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) + node T_7037 = bits(ex_reg_inst, 19, 16) + node T_7038 = bits(ex_reg_inst, 24, 21) + node T_7039 = mux(T_7036, T_7037, T_7038) + node T_7040 = mux(T_7034, T_7035, T_7039) + node T_7041 = mux(T_7030, UInt<1>("h00"), T_7040) + node T_7042 = eq(ex_ctrl.sel_imm, UInt<3>("h00")) + node T_7043 = bits(ex_reg_inst, 7, 7) + node T_7044 = eq(ex_ctrl.sel_imm, UInt<3>("h04")) + node T_7045 = bits(ex_reg_inst, 20, 20) + node T_7046 = eq(ex_ctrl.sel_imm, UInt<3>("h05")) + node T_7047 = bits(ex_reg_inst, 15, 15) + node T_7049 = shl(T_7047, 0) + node T_7050 = mux(T_7046, T_7049, UInt<1>("h00")) + node T_7051 = shl(T_7045, 0) + node T_7052 = mux(T_7044, T_7051, T_7050) + node T_7053 = shl(T_7043, 0) + node T_7054 = mux(T_7042, T_7053, T_7052) + node T_7055 = asUInt(T_7000) + node T_7056 = asUInt(T_7004) + node T_7057 = asUInt(T_7010) + node T_7058 = cat(T_7056, T_7057) + node T_7059 = cat(T_7055, T_7058) + node T_7060 = asUInt(T_7023) + node T_7061 = cat(T_7060, T_7029) + node T_7062 = cat(T_7041, T_7054) + node T_7063 = cat(T_7061, T_7062) + node T_7064 = cat(T_7059, T_7063) + node ex_imm = asSInt(T_7064) + node T_7067 = asSInt(T_6992) + node T_7068 = asSInt(ex_reg_pc) + node T_7069 = eq(UInt<2>("h02"), ex_ctrl.sel_alu1) + node T_7070 = mux(T_7069, T_7068, asSInt(UInt<1>("h00"))) + node T_7071 = eq(UInt<2>("h01"), ex_ctrl.sel_alu1) + node ex_op1 = mux(T_7071, T_7067, T_7070) + node T_7074 = asSInt(T_6995) + node T_7076 = eq(UInt<2>("h01"), ex_ctrl.sel_alu2) + node T_7077 = mux(T_7076, asSInt(UInt<4>("h04")), asSInt(UInt<1>("h00"))) + node T_7078 = eq(UInt<2>("h03"), ex_ctrl.sel_alu2) + node T_7079 = mux(T_7078, ex_imm, T_7077) + node T_7080 = eq(UInt<2>("h02"), ex_ctrl.sel_alu2) + node ex_op2 = mux(T_7080, T_7074, T_7079) inst alu of ALU - alu.io.in1 <= UInt<1>("h00") - alu.io.in2 <= UInt<1>("h00") - alu.io.fn <= UInt<1>("h00") - alu.io.dw <= UInt<1>("h00") + alu.io is invalid alu.clk <= clk alu.reset <= reset alu.io.dw <= ex_ctrl.alu_dw alu.io.fn <= ex_ctrl.alu_fn - node T_7222 = asUInt(ex_op2) - alu.io.in2 <= T_7222 - node T_7223 = asUInt(ex_op1) - alu.io.in1 <= T_7223 + node T_7083 = asUInt(ex_op2) + alu.io.in2 <= T_7083 + node T_7084 = asUInt(ex_op1) + alu.io.in1 <= T_7084 inst div of MulDiv - div.io.resp.ready <= UInt<1>("h00") - div.io.kill <= UInt<1>("h00") - div.io.req.bits.tag <= UInt<1>("h00") - div.io.req.bits.in2 <= UInt<1>("h00") - div.io.req.bits.in1 <= UInt<1>("h00") - div.io.req.bits.dw <= UInt<1>("h00") - div.io.req.bits.fn <= UInt<1>("h00") - div.io.req.valid <= UInt<1>("h00") + div.io is invalid div.clk <= clk div.reset <= reset - node T_7233 = and(ex_reg_valid, ex_ctrl.div) - div.io.req.valid <= T_7233 + node T_7086 = and(ex_reg_valid, ex_ctrl.div) + div.io.req.valid <= T_7086 div.io.req.bits.dw <= ex_ctrl.alu_dw div.io.req.bits.fn <= ex_ctrl.alu_fn - div.io.req.bits.in1 <= T_7127 - div.io.req.bits.in2 <= T_7130 + div.io.req.bits.in1 <= T_6992 + div.io.req.bits.in2 <= T_6995 div.io.req.bits.tag <= ex_waddr - node T_7235 = eq(ctrl_killd, UInt<1>("h00")) - ex_reg_valid <= T_7235 - node T_7237 = eq(ctrl_killd, UInt<1>("h00")) - node T_7238 = and(T_7237, id_xcpt) - ex_reg_xcpt <= T_7238 - node T_7240 = eq(take_pc_mem_wb, UInt<1>("h00")) - node T_7241 = and(csr.io.interrupt, T_7240) - node T_7242 = and(T_7241, io.imem.resp.valid) - ex_reg_xcpt_interrupt <= T_7242 + node T_7088 = eq(ctrl_killd, UInt<1>("h00")) + ex_reg_valid <= T_7088 + node T_7090 = eq(ctrl_killd, UInt<1>("h00")) + node T_7091 = and(T_7090, id_xcpt) + ex_reg_xcpt <= T_7091 + node T_7093 = eq(take_pc_mem_wb, UInt<1>("h00")) + node T_7094 = and(csr.io.interrupt, T_7093) + node T_7095 = and(T_7094, io.imem.resp.valid) + ex_reg_xcpt_interrupt <= T_7095 when id_xcpt : ex_reg_cause <= id_cause skip - node T_7244 = eq(ctrl_killd, UInt<1>("h00")) - when T_7244 : + node T_7097 = eq(ctrl_killd, UInt<1>("h00")) + when T_7097 : ex_ctrl <- id_ctrl ex_ctrl.csr <= id_csr ex_reg_btb_hit <= io.imem.btb_resp.valid when io.imem.btb_resp.valid : ex_reg_btb_resp <- io.imem.btb_resp.bits skip - node T_7245 = or(id_ctrl.fence_i, id_csr_flush) - ex_reg_flush_pipe <= T_7245 + node T_7098 = or(id_ctrl.fence_i, id_csr_flush) + ex_reg_flush_pipe <= T_7098 ex_reg_load_use <= id_load_use - node T_7246 = or(T_7067, T_7069) - node T_7247 = or(T_7246, T_7071) - node T_7248 = or(T_7247, T_7073) - node T_7253 = mux(T_7071, UInt<2>("h02"), UInt<2>("h03")) - node T_7254 = mux(T_7069, UInt<1>("h01"), T_7253) - node T_7255 = mux(T_7067, UInt<1>("h00"), T_7254) - ex_reg_rs_bypass[0] <= T_7248 - ex_reg_rs_lsb[0] <= T_7255 - node T_7257 = eq(T_7248, UInt<1>("h00")) - node T_7258 = and(id_ctrl.rxs1, T_7257) - when T_7258 : - node T_7259 = bits(T_6797, 1, 0) - ex_reg_rs_lsb[0] <= T_7259 - node T_7260 = shr(T_6797, 2) - ex_reg_rs_msb[0] <= T_7260 - skip - node T_7261 = or(T_7075, T_7077) - node T_7262 = or(T_7261, T_7079) - node T_7263 = or(T_7262, T_7081) - node T_7268 = mux(T_7079, UInt<2>("h02"), UInt<2>("h03")) - node T_7269 = mux(T_7077, UInt<1>("h01"), T_7268) - node T_7270 = mux(T_7075, UInt<1>("h00"), T_7269) - ex_reg_rs_bypass[1] <= T_7263 - ex_reg_rs_lsb[1] <= T_7270 - node T_7272 = eq(T_7263, UInt<1>("h00")) - node T_7273 = and(id_ctrl.rxs2, T_7272) - when T_7273 : - node T_7274 = bits(T_6809, 1, 0) - ex_reg_rs_lsb[1] <= T_7274 - node T_7275 = shr(T_6809, 2) - ex_reg_rs_msb[1] <= T_7275 - skip - skip - node T_7277 = eq(ctrl_killd, UInt<1>("h00")) - node T_7278 = or(T_7277, csr.io.interrupt) - when T_7278 : + node T_7099 = or(T_6932, T_6934) + node T_7100 = or(T_7099, T_6936) + node T_7101 = or(T_7100, T_6938) + node T_7106 = mux(T_6936, UInt<2>("h02"), UInt<2>("h03")) + node T_7107 = mux(T_6934, UInt<1>("h01"), T_7106) + node T_7108 = mux(T_6932, UInt<1>("h00"), T_7107) + ex_reg_rs_bypass[0] <= T_7101 + ex_reg_rs_lsb[0] <= T_7108 + node T_7110 = eq(T_7101, UInt<1>("h00")) + node T_7111 = and(id_ctrl.rxs1, T_7110) + when T_7111 : + node T_7112 = bits(T_6768, 1, 0) + ex_reg_rs_lsb[0] <= T_7112 + node T_7113 = shr(T_6768, 2) + ex_reg_rs_msb[0] <= T_7113 + skip + node T_7114 = or(T_6940, T_6942) + node T_7115 = or(T_7114, T_6944) + node T_7116 = or(T_7115, T_6946) + node T_7121 = mux(T_6944, UInt<2>("h02"), UInt<2>("h03")) + node T_7122 = mux(T_6942, UInt<1>("h01"), T_7121) + node T_7123 = mux(T_6940, UInt<1>("h00"), T_7122) + ex_reg_rs_bypass[1] <= T_7116 + ex_reg_rs_lsb[1] <= T_7123 + node T_7125 = eq(T_7116, UInt<1>("h00")) + node T_7126 = and(id_ctrl.rxs2, T_7125) + when T_7126 : + node T_7127 = bits(T_6779, 1, 0) + ex_reg_rs_lsb[1] <= T_7127 + node T_7128 = shr(T_6779, 2) + ex_reg_rs_msb[1] <= T_7128 + skip + skip + node T_7130 = eq(ctrl_killd, UInt<1>("h00")) + node T_7131 = or(T_7130, csr.io.interrupt) + when T_7131 : ex_reg_inst <= io.imem.resp.bits.data[0] ex_reg_pc <= io.imem.resp.bits.pc skip - node T_7280 = eq(io.dmem.resp.valid, UInt<1>("h00")) - node wb_dcache_miss = and(wb_ctrl.mem, T_7280) - node T_7283 = eq(io.dmem.req.ready, UInt<1>("h00")) - node T_7284 = and(ex_ctrl.mem, T_7283) - node T_7286 = eq(div.io.req.ready, UInt<1>("h00")) - node T_7287 = and(ex_ctrl.div, T_7286) - node replay_ex_structural = or(T_7284, T_7287) + node T_7133 = eq(io.dmem.resp.valid, UInt<1>("h00")) + node wb_dcache_miss = and(wb_ctrl.mem, T_7133) + node T_7136 = eq(io.dmem.req.ready, UInt<1>("h00")) + node T_7137 = and(ex_ctrl.mem, T_7136) + node T_7139 = eq(div.io.req.ready, UInt<1>("h00")) + node T_7140 = and(ex_ctrl.div, T_7139) + node replay_ex_structural = or(T_7137, T_7140) node replay_ex_load_use = and(wb_dcache_miss, ex_reg_load_use) - node T_7290 = or(replay_ex_structural, replay_ex_load_use) - node replay_ex = and(ex_reg_valid, T_7290) - node T_7292 = or(take_pc_mem_wb, replay_ex) - node T_7294 = eq(ex_reg_valid, UInt<1>("h00")) - node ctrl_killx = or(T_7292, T_7294) - node T_7296 = eq(ex_ctrl.mem_cmd, UInt<5>("h07")) - wire T_7298 : UInt<3>[4] - T_7298[0] <= UInt<3>("h00") - T_7298[1] <= UInt<3>("h04") - T_7298[2] <= UInt<3>("h01") - T_7298[3] <= UInt<3>("h05") - node T_7304 = eq(T_7298[0], ex_ctrl.mem_type) - node T_7305 = eq(T_7298[1], ex_ctrl.mem_type) - node T_7306 = eq(T_7298[2], ex_ctrl.mem_type) - node T_7307 = eq(T_7298[3], ex_ctrl.mem_type) - node T_7309 = or(UInt<1>("h00"), T_7304) - node T_7310 = or(T_7309, T_7305) - node T_7311 = or(T_7310, T_7306) - node T_7312 = or(T_7311, T_7307) - node ex_slow_bypass = or(T_7296, T_7312) - node T_7314 = or(ex_reg_xcpt_interrupt, ex_reg_xcpt) - node T_7315 = and(ex_ctrl.fp, io.fpu.illegal_rm) - node ex_xcpt = or(T_7314, T_7315) - node ex_cause = mux(T_7314, ex_reg_cause, UInt<2>("h02")) - node mem_br_taken = bit(mem_reg_wdata, 0) - node T_7320 = asSInt(mem_reg_pc) - node T_7321 = and(mem_ctrl.branch, mem_br_taken) - node T_7322 = eq(UInt<3>("h01"), UInt<3>("h05")) - node T_7324 = bit(mem_reg_inst, 31) - node T_7325 = asSInt(T_7324) - node T_7326 = mux(T_7322, asSInt(UInt<1>("h00")), T_7325) - node T_7327 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_7328 = bits(mem_reg_inst, 30, 20) - node T_7329 = asSInt(T_7328) - node T_7330 = mux(T_7327, T_7329, T_7326) - node T_7331 = neq(UInt<3>("h01"), UInt<3>("h02")) - node T_7332 = neq(UInt<3>("h01"), UInt<3>("h03")) - node T_7333 = and(T_7331, T_7332) - node T_7334 = bits(mem_reg_inst, 19, 12) - node T_7335 = asSInt(T_7334) - node T_7336 = mux(T_7333, T_7326, T_7335) - node T_7337 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_7338 = eq(UInt<3>("h01"), UInt<3>("h05")) - node T_7339 = or(T_7337, T_7338) - node T_7341 = eq(UInt<3>("h01"), UInt<3>("h03")) - node T_7342 = bit(mem_reg_inst, 20) - node T_7343 = asSInt(T_7342) - node T_7344 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_7345 = bit(mem_reg_inst, 7) - node T_7346 = asSInt(T_7345) - node T_7347 = mux(T_7344, T_7346, T_7326) - node T_7348 = mux(T_7341, T_7343, T_7347) - node T_7349 = mux(T_7339, asSInt(UInt<1>("h00")), T_7348) - node T_7350 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_7351 = eq(UInt<3>("h01"), UInt<3>("h05")) - node T_7352 = or(T_7350, T_7351) - node T_7354 = bits(mem_reg_inst, 30, 25) - node T_7355 = mux(T_7352, UInt<1>("h00"), T_7354) - node T_7356 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_7358 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_7359 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_7360 = or(T_7358, T_7359) - node T_7361 = bits(mem_reg_inst, 11, 8) - node T_7362 = eq(UInt<3>("h01"), UInt<3>("h05")) - node T_7363 = bits(mem_reg_inst, 19, 16) - node T_7364 = bits(mem_reg_inst, 24, 21) - node T_7365 = mux(T_7362, T_7363, T_7364) - node T_7366 = mux(T_7360, T_7361, T_7365) - node T_7367 = mux(T_7356, UInt<1>("h00"), T_7366) - node T_7368 = eq(UInt<3>("h01"), UInt<3>("h00")) - node T_7369 = bit(mem_reg_inst, 7) - node T_7370 = eq(UInt<3>("h01"), UInt<3>("h04")) - node T_7371 = bit(mem_reg_inst, 20) - node T_7372 = eq(UInt<3>("h01"), UInt<3>("h05")) - node T_7373 = bit(mem_reg_inst, 15) - node T_7375 = shl(T_7373, 0) - node T_7376 = mux(T_7372, T_7375, UInt<1>("h00")) - node T_7377 = shl(T_7371, 0) - node T_7378 = mux(T_7370, T_7377, T_7376) - node T_7379 = shl(T_7369, 0) - node T_7380 = mux(T_7368, T_7379, T_7378) - node T_7381 = asUInt(T_7326) - node T_7382 = asUInt(T_7330) - node T_7383 = asUInt(T_7336) - node T_7384 = cat(T_7382, T_7383) - node T_7385 = cat(T_7381, T_7384) - node T_7386 = asUInt(T_7349) - node T_7387 = cat(T_7386, T_7355) - node T_7388 = cat(T_7367, T_7380) - node T_7389 = cat(T_7387, T_7388) - node T_7390 = cat(T_7385, T_7389) - node T_7391 = asSInt(T_7390) - node T_7392 = eq(UInt<3>("h03"), UInt<3>("h05")) - node T_7394 = bit(mem_reg_inst, 31) - node T_7395 = asSInt(T_7394) - node T_7396 = mux(T_7392, asSInt(UInt<1>("h00")), T_7395) - node T_7397 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_7398 = bits(mem_reg_inst, 30, 20) - node T_7399 = asSInt(T_7398) - node T_7400 = mux(T_7397, T_7399, T_7396) - node T_7401 = neq(UInt<3>("h03"), UInt<3>("h02")) - node T_7402 = neq(UInt<3>("h03"), UInt<3>("h03")) - node T_7403 = and(T_7401, T_7402) - node T_7404 = bits(mem_reg_inst, 19, 12) - node T_7405 = asSInt(T_7404) - node T_7406 = mux(T_7403, T_7396, T_7405) - node T_7407 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_7408 = eq(UInt<3>("h03"), UInt<3>("h05")) - node T_7409 = or(T_7407, T_7408) - node T_7411 = eq(UInt<3>("h03"), UInt<3>("h03")) - node T_7412 = bit(mem_reg_inst, 20) - node T_7413 = asSInt(T_7412) - node T_7414 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_7415 = bit(mem_reg_inst, 7) - node T_7416 = asSInt(T_7415) - node T_7417 = mux(T_7414, T_7416, T_7396) - node T_7418 = mux(T_7411, T_7413, T_7417) - node T_7419 = mux(T_7409, asSInt(UInt<1>("h00")), T_7418) - node T_7420 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_7421 = eq(UInt<3>("h03"), UInt<3>("h05")) - node T_7422 = or(T_7420, T_7421) - node T_7424 = bits(mem_reg_inst, 30, 25) - node T_7425 = mux(T_7422, UInt<1>("h00"), T_7424) - node T_7426 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_7428 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_7429 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_7430 = or(T_7428, T_7429) - node T_7431 = bits(mem_reg_inst, 11, 8) - node T_7432 = eq(UInt<3>("h03"), UInt<3>("h05")) - node T_7433 = bits(mem_reg_inst, 19, 16) - node T_7434 = bits(mem_reg_inst, 24, 21) - node T_7435 = mux(T_7432, T_7433, T_7434) - node T_7436 = mux(T_7430, T_7431, T_7435) - node T_7437 = mux(T_7426, UInt<1>("h00"), T_7436) - node T_7438 = eq(UInt<3>("h03"), UInt<3>("h00")) - node T_7439 = bit(mem_reg_inst, 7) - node T_7440 = eq(UInt<3>("h03"), UInt<3>("h04")) - node T_7441 = bit(mem_reg_inst, 20) - node T_7442 = eq(UInt<3>("h03"), UInt<3>("h05")) - node T_7443 = bit(mem_reg_inst, 15) - node T_7445 = shl(T_7443, 0) - node T_7446 = mux(T_7442, T_7445, UInt<1>("h00")) - node T_7447 = shl(T_7441, 0) - node T_7448 = mux(T_7440, T_7447, T_7446) - node T_7449 = shl(T_7439, 0) - node T_7450 = mux(T_7438, T_7449, T_7448) - node T_7451 = asUInt(T_7396) - node T_7452 = asUInt(T_7400) - node T_7453 = asUInt(T_7406) - node T_7454 = cat(T_7452, T_7453) - node T_7455 = cat(T_7451, T_7454) - node T_7456 = asUInt(T_7419) - node T_7457 = cat(T_7456, T_7425) - node T_7458 = cat(T_7437, T_7450) - node T_7459 = cat(T_7457, T_7458) - node T_7460 = cat(T_7455, T_7459) - node T_7461 = asSInt(T_7460) - node T_7463 = mux(mem_ctrl.jal, T_7461, asSInt(UInt<4>("h04"))) - node T_7464 = mux(T_7321, T_7391, T_7463) - node mem_br_target = addw(T_7320, T_7464) - node T_7466 = asSInt(mem_reg_wdata) - node T_7467 = mux(mem_ctrl.jalr, mem_br_target, T_7466) - node mem_int_wdata = asUInt(T_7467) - node T_7469 = shr(mem_reg_wdata, 38) - node T_7470 = bits(mem_reg_wdata, 39, 38) - node T_7472 = eq(T_7469, UInt<1>("h00")) - node T_7474 = eq(T_7469, UInt<1>("h01")) - node T_7475 = or(T_7472, T_7474) - node T_7477 = neq(T_7470, UInt<1>("h00")) - node T_7478 = asSInt(T_7469) - node T_7480 = eq(T_7478, asSInt(UInt<1>("h01"))) - node T_7481 = asSInt(T_7469) - node T_7483 = eq(T_7481, asSInt(UInt<2>("h02"))) - node T_7484 = or(T_7480, T_7483) - node T_7485 = asSInt(T_7470) - node T_7487 = eq(T_7485, asSInt(UInt<1>("h01"))) - node T_7488 = bit(T_7470, 0) - node T_7489 = mux(T_7484, T_7487, T_7488) - node T_7490 = mux(T_7475, T_7477, T_7489) - node T_7491 = bits(mem_reg_wdata, 38, 0) - node T_7492 = cat(T_7490, T_7491) - node T_7493 = asSInt(T_7492) - node T_7494 = mux(mem_ctrl.jalr, T_7493, mem_br_target) - node T_7496 = and(T_7494, asSInt(UInt<2>("h02"))) - node mem_npc = asUInt(T_7496) - node T_7498 = neq(mem_npc, ex_reg_pc) - node T_7500 = eq(ex_reg_valid, UInt<1>("h00")) - node mem_wrong_npc = or(T_7498, T_7500) - node mem_npc_misaligned = bit(mem_npc, 1) - node T_7503 = and(mem_wrong_npc, mem_reg_valid) - node T_7504 = or(mem_ctrl.branch, mem_ctrl.jalr) - node T_7505 = or(T_7504, mem_ctrl.jal) - node mem_misprediction = and(T_7503, T_7505) - node T_7507 = or(mem_misprediction, mem_reg_flush_pipe) - node want_take_pc_mem = and(mem_reg_valid, T_7507) - node T_7510 = eq(mem_npc_misaligned, UInt<1>("h00")) - node T_7511 = and(want_take_pc_mem, T_7510) - take_pc_mem <= T_7511 - node T_7513 = eq(ctrl_killx, UInt<1>("h00")) - mem_reg_valid <= T_7513 - node T_7515 = eq(take_pc_mem_wb, UInt<1>("h00")) - node T_7516 = and(T_7515, replay_ex) - mem_reg_replay <= T_7516 - node T_7518 = eq(ctrl_killx, UInt<1>("h00")) - node T_7519 = and(T_7518, ex_xcpt) - mem_reg_xcpt <= T_7519 - node T_7521 = eq(take_pc_mem_wb, UInt<1>("h00")) - node T_7522 = and(T_7521, ex_reg_xcpt_interrupt) - mem_reg_xcpt_interrupt <= T_7522 + node T_7143 = or(replay_ex_structural, replay_ex_load_use) + node replay_ex = and(ex_reg_valid, T_7143) + node T_7145 = or(take_pc_mem_wb, replay_ex) + node T_7147 = eq(ex_reg_valid, UInt<1>("h00")) + node ctrl_killx = or(T_7145, T_7147) + node T_7149 = eq(ex_ctrl.mem_cmd, UInt<5>("h07")) + wire T_7151 : UInt<3>[4] + T_7151[0] <= UInt<3>("h00") + T_7151[1] <= UInt<3>("h04") + T_7151[2] <= UInt<3>("h01") + T_7151[3] <= UInt<3>("h05") + node T_7157 = eq(T_7151[0], ex_ctrl.mem_type) + node T_7158 = eq(T_7151[1], ex_ctrl.mem_type) + node T_7159 = eq(T_7151[2], ex_ctrl.mem_type) + node T_7160 = eq(T_7151[3], ex_ctrl.mem_type) + node T_7162 = or(UInt<1>("h00"), T_7157) + node T_7163 = or(T_7162, T_7158) + node T_7164 = or(T_7163, T_7159) + node T_7165 = or(T_7164, T_7160) + node ex_slow_bypass = or(T_7149, T_7165) + node T_7167 = or(ex_reg_xcpt_interrupt, ex_reg_xcpt) + node T_7168 = and(ex_ctrl.fp, io.fpu.illegal_rm) + node ex_xcpt = or(T_7167, T_7168) + node ex_cause = mux(T_7167, ex_reg_cause, UInt<2>("h02")) + node mem_br_taken = bits(mem_reg_wdata, 0, 0) + node T_7173 = asSInt(mem_reg_pc) + node T_7174 = and(mem_ctrl.branch, mem_br_taken) + node T_7175 = eq(UInt<3>("h01"), UInt<3>("h05")) + node T_7177 = bits(mem_reg_inst, 31, 31) + node T_7178 = asSInt(T_7177) + node T_7179 = mux(T_7175, asSInt(UInt<1>("h00")), T_7178) + node T_7180 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_7181 = bits(mem_reg_inst, 30, 20) + node T_7182 = asSInt(T_7181) + node T_7183 = mux(T_7180, T_7182, T_7179) + node T_7184 = neq(UInt<3>("h01"), UInt<3>("h02")) + node T_7185 = neq(UInt<3>("h01"), UInt<3>("h03")) + node T_7186 = and(T_7184, T_7185) + node T_7187 = bits(mem_reg_inst, 19, 12) + node T_7188 = asSInt(T_7187) + node T_7189 = mux(T_7186, T_7179, T_7188) + node T_7190 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_7191 = eq(UInt<3>("h01"), UInt<3>("h05")) + node T_7192 = or(T_7190, T_7191) + node T_7194 = eq(UInt<3>("h01"), UInt<3>("h03")) + node T_7195 = bits(mem_reg_inst, 20, 20) + node T_7196 = asSInt(T_7195) + node T_7197 = eq(UInt<3>("h01"), UInt<3>("h01")) + node T_7198 = bits(mem_reg_inst, 7, 7) + node T_7199 = asSInt(T_7198) + node T_7200 = mux(T_7197, T_7199, T_7179) + node T_7201 = mux(T_7194, T_7196, T_7200) + node T_7202 = mux(T_7192, asSInt(UInt<1>("h00")), T_7201) + node T_7203 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_7204 = eq(UInt<3>("h01"), UInt<3>("h05")) + node T_7205 = or(T_7203, T_7204) + node T_7207 = bits(mem_reg_inst, 30, 25) + node T_7208 = mux(T_7205, UInt<1>("h00"), T_7207) + node T_7209 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_7211 = eq(UInt<3>("h01"), UInt<3>("h00")) + node T_7212 = eq(UInt<3>("h01"), UInt<3>("h01")) + node T_7213 = or(T_7211, T_7212) + node T_7214 = bits(mem_reg_inst, 11, 8) + node T_7215 = eq(UInt<3>("h01"), UInt<3>("h05")) + node T_7216 = bits(mem_reg_inst, 19, 16) + node T_7217 = bits(mem_reg_inst, 24, 21) + node T_7218 = mux(T_7215, T_7216, T_7217) + node T_7219 = mux(T_7213, T_7214, T_7218) + node T_7220 = mux(T_7209, UInt<1>("h00"), T_7219) + node T_7221 = eq(UInt<3>("h01"), UInt<3>("h00")) + node T_7222 = bits(mem_reg_inst, 7, 7) + node T_7223 = eq(UInt<3>("h01"), UInt<3>("h04")) + node T_7224 = bits(mem_reg_inst, 20, 20) + node T_7225 = eq(UInt<3>("h01"), UInt<3>("h05")) + node T_7226 = bits(mem_reg_inst, 15, 15) + node T_7228 = shl(T_7226, 0) + node T_7229 = mux(T_7225, T_7228, UInt<1>("h00")) + node T_7230 = shl(T_7224, 0) + node T_7231 = mux(T_7223, T_7230, T_7229) + node T_7232 = shl(T_7222, 0) + node T_7233 = mux(T_7221, T_7232, T_7231) + node T_7234 = asUInt(T_7179) + node T_7235 = asUInt(T_7183) + node T_7236 = asUInt(T_7189) + node T_7237 = cat(T_7235, T_7236) + node T_7238 = cat(T_7234, T_7237) + node T_7239 = asUInt(T_7202) + node T_7240 = cat(T_7239, T_7208) + node T_7241 = cat(T_7220, T_7233) + node T_7242 = cat(T_7240, T_7241) + node T_7243 = cat(T_7238, T_7242) + node T_7244 = asSInt(T_7243) + node T_7245 = eq(UInt<3>("h03"), UInt<3>("h05")) + node T_7247 = bits(mem_reg_inst, 31, 31) + node T_7248 = asSInt(T_7247) + node T_7249 = mux(T_7245, asSInt(UInt<1>("h00")), T_7248) + node T_7250 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_7251 = bits(mem_reg_inst, 30, 20) + node T_7252 = asSInt(T_7251) + node T_7253 = mux(T_7250, T_7252, T_7249) + node T_7254 = neq(UInt<3>("h03"), UInt<3>("h02")) + node T_7255 = neq(UInt<3>("h03"), UInt<3>("h03")) + node T_7256 = and(T_7254, T_7255) + node T_7257 = bits(mem_reg_inst, 19, 12) + node T_7258 = asSInt(T_7257) + node T_7259 = mux(T_7256, T_7249, T_7258) + node T_7260 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_7261 = eq(UInt<3>("h03"), UInt<3>("h05")) + node T_7262 = or(T_7260, T_7261) + node T_7264 = eq(UInt<3>("h03"), UInt<3>("h03")) + node T_7265 = bits(mem_reg_inst, 20, 20) + node T_7266 = asSInt(T_7265) + node T_7267 = eq(UInt<3>("h03"), UInt<3>("h01")) + node T_7268 = bits(mem_reg_inst, 7, 7) + node T_7269 = asSInt(T_7268) + node T_7270 = mux(T_7267, T_7269, T_7249) + node T_7271 = mux(T_7264, T_7266, T_7270) + node T_7272 = mux(T_7262, asSInt(UInt<1>("h00")), T_7271) + node T_7273 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_7274 = eq(UInt<3>("h03"), UInt<3>("h05")) + node T_7275 = or(T_7273, T_7274) + node T_7277 = bits(mem_reg_inst, 30, 25) + node T_7278 = mux(T_7275, UInt<1>("h00"), T_7277) + node T_7279 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_7281 = eq(UInt<3>("h03"), UInt<3>("h00")) + node T_7282 = eq(UInt<3>("h03"), UInt<3>("h01")) + node T_7283 = or(T_7281, T_7282) + node T_7284 = bits(mem_reg_inst, 11, 8) + node T_7285 = eq(UInt<3>("h03"), UInt<3>("h05")) + node T_7286 = bits(mem_reg_inst, 19, 16) + node T_7287 = bits(mem_reg_inst, 24, 21) + node T_7288 = mux(T_7285, T_7286, T_7287) + node T_7289 = mux(T_7283, T_7284, T_7288) + node T_7290 = mux(T_7279, UInt<1>("h00"), T_7289) + node T_7291 = eq(UInt<3>("h03"), UInt<3>("h00")) + node T_7292 = bits(mem_reg_inst, 7, 7) + node T_7293 = eq(UInt<3>("h03"), UInt<3>("h04")) + node T_7294 = bits(mem_reg_inst, 20, 20) + node T_7295 = eq(UInt<3>("h03"), UInt<3>("h05")) + node T_7296 = bits(mem_reg_inst, 15, 15) + node T_7298 = shl(T_7296, 0) + node T_7299 = mux(T_7295, T_7298, UInt<1>("h00")) + node T_7300 = shl(T_7294, 0) + node T_7301 = mux(T_7293, T_7300, T_7299) + node T_7302 = shl(T_7292, 0) + node T_7303 = mux(T_7291, T_7302, T_7301) + node T_7304 = asUInt(T_7249) + node T_7305 = asUInt(T_7253) + node T_7306 = asUInt(T_7259) + node T_7307 = cat(T_7305, T_7306) + node T_7308 = cat(T_7304, T_7307) + node T_7309 = asUInt(T_7272) + node T_7310 = cat(T_7309, T_7278) + node T_7311 = cat(T_7290, T_7303) + node T_7312 = cat(T_7310, T_7311) + node T_7313 = cat(T_7308, T_7312) + node T_7314 = asSInt(T_7313) + node T_7316 = mux(mem_ctrl.jal, T_7314, asSInt(UInt<4>("h04"))) + node T_7317 = mux(T_7174, T_7244, T_7316) + node T_7318 = add(T_7173, T_7317) + node T_7319 = tail(T_7318, 1) + node mem_br_target = asSInt(T_7319) + node T_7321 = asSInt(mem_reg_wdata) + node T_7322 = mux(mem_ctrl.jalr, mem_br_target, T_7321) + node mem_int_wdata = asUInt(T_7322) + node T_7324 = shr(mem_reg_wdata, 38) + node T_7325 = bits(mem_reg_wdata, 39, 38) + node T_7327 = eq(T_7324, UInt<1>("h00")) + node T_7329 = eq(T_7324, UInt<1>("h01")) + node T_7330 = or(T_7327, T_7329) + node T_7332 = neq(T_7325, UInt<1>("h00")) + node T_7333 = asSInt(T_7324) + node T_7335 = eq(T_7333, asSInt(UInt<1>("h01"))) + node T_7336 = asSInt(T_7324) + node T_7338 = eq(T_7336, asSInt(UInt<2>("h02"))) + node T_7339 = or(T_7335, T_7338) + node T_7340 = asSInt(T_7325) + node T_7342 = eq(T_7340, asSInt(UInt<1>("h01"))) + node T_7343 = bits(T_7325, 0, 0) + node T_7344 = mux(T_7339, T_7342, T_7343) + node T_7345 = mux(T_7330, T_7332, T_7344) + node T_7346 = bits(mem_reg_wdata, 38, 0) + node T_7347 = cat(T_7345, T_7346) + node T_7348 = asSInt(T_7347) + node T_7349 = mux(mem_ctrl.jalr, T_7348, mem_br_target) + node T_7351 = and(T_7349, asSInt(UInt<2>("h02"))) + node T_7352 = asSInt(T_7351) + node mem_npc = asUInt(T_7352) + node T_7354 = neq(mem_npc, ex_reg_pc) + node T_7356 = eq(ex_reg_valid, UInt<1>("h00")) + node mem_wrong_npc = or(T_7354, T_7356) + node mem_npc_misaligned = bits(mem_npc, 1, 1) + node T_7359 = and(mem_wrong_npc, mem_reg_valid) + node T_7360 = or(mem_ctrl.branch, mem_ctrl.jalr) + node T_7361 = or(T_7360, mem_ctrl.jal) + node mem_misprediction = and(T_7359, T_7361) + node T_7363 = or(mem_misprediction, mem_reg_flush_pipe) + node want_take_pc_mem = and(mem_reg_valid, T_7363) + node T_7366 = eq(mem_npc_misaligned, UInt<1>("h00")) + node T_7367 = and(want_take_pc_mem, T_7366) + take_pc_mem <= T_7367 + node T_7369 = eq(ctrl_killx, UInt<1>("h00")) + mem_reg_valid <= T_7369 + node T_7371 = eq(take_pc_mem_wb, UInt<1>("h00")) + node T_7372 = and(T_7371, replay_ex) + mem_reg_replay <= T_7372 + node T_7374 = eq(ctrl_killx, UInt<1>("h00")) + node T_7375 = and(T_7374, ex_xcpt) + mem_reg_xcpt <= T_7375 + node T_7377 = eq(take_pc_mem_wb, UInt<1>("h00")) + node T_7378 = and(T_7377, ex_reg_xcpt_interrupt) + mem_reg_xcpt_interrupt <= T_7378 when ex_xcpt : mem_reg_cause <= ex_cause skip - node T_7523 = or(ex_reg_valid, ex_reg_xcpt_interrupt) - when T_7523 : + node T_7379 = or(ex_reg_valid, ex_reg_xcpt_interrupt) + when T_7379 : mem_ctrl <- ex_ctrl mem_reg_btb_hit <= ex_reg_btb_hit when ex_reg_btb_hit : @@ -24090,144 +17407,144 @@ circuit Top : mem_reg_inst <= ex_reg_inst mem_reg_pc <= ex_reg_pc mem_reg_wdata <= alu.io.out - node T_7524 = or(ex_ctrl.mem, ex_ctrl.rocc) - node T_7525 = and(ex_ctrl.rxs2, T_7524) - when T_7525 : - mem_reg_rs2 <= T_7130 - skip - skip - node T_7526 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt) - node T_7527 = and(want_take_pc_mem, mem_npc_misaligned) - node T_7529 = and(mem_reg_valid, mem_ctrl.mem) - node T_7530 = and(T_7529, io.dmem.xcpt.ma.st) - node T_7532 = and(mem_reg_valid, mem_ctrl.mem) - node T_7533 = and(T_7532, io.dmem.xcpt.ma.ld) - node T_7535 = and(mem_reg_valid, mem_ctrl.mem) - node T_7536 = and(T_7535, io.dmem.xcpt.pf.st) - node T_7538 = and(mem_reg_valid, mem_ctrl.mem) - node T_7539 = and(T_7538, io.dmem.xcpt.pf.ld) - node T_7541 = or(T_7526, T_7527) - node T_7542 = or(T_7541, T_7530) - node T_7543 = or(T_7542, T_7533) - node T_7544 = or(T_7543, T_7536) - node mem_xcpt = or(T_7544, T_7539) - node T_7546 = mux(T_7536, UInt<3>("h07"), UInt<3>("h05")) - node T_7547 = mux(T_7533, UInt<3>("h04"), T_7546) - node T_7548 = mux(T_7530, UInt<3>("h06"), T_7547) - node T_7549 = mux(T_7527, UInt<1>("h00"), T_7548) - node mem_cause = mux(T_7526, mem_reg_cause, T_7549) - node T_7551 = and(mem_reg_valid, mem_ctrl.wxd) - node dcache_kill_mem = and(T_7551, io.dmem.replay_next.valid) - node T_7553 = and(mem_reg_valid, mem_ctrl.fp) - node fpu_kill_mem = and(T_7553, io.fpu.nack_mem) - node T_7555 = or(dcache_kill_mem, mem_reg_replay) - node replay_mem = or(T_7555, fpu_kill_mem) - node T_7557 = or(dcache_kill_mem, take_pc_wb) - node T_7558 = or(T_7557, mem_reg_xcpt) - node T_7560 = eq(mem_reg_valid, UInt<1>("h00")) - node killm_common = or(T_7558, T_7560) - node T_7562 = and(div.io.req.ready, div.io.req.valid) - reg T_7563 : UInt<1>, clk, UInt<1>("h00"), T_7563 - T_7563 <= T_7562 - node T_7564 = and(killm_common, T_7563) - div.io.kill <= T_7564 - node T_7565 = or(killm_common, mem_xcpt) - node ctrl_killm = or(T_7565, fpu_kill_mem) - node T_7568 = eq(ctrl_killm, UInt<1>("h00")) - wb_reg_valid <= T_7568 - node T_7570 = eq(take_pc_wb, UInt<1>("h00")) - node T_7571 = and(replay_mem, T_7570) - wb_reg_replay <= T_7571 - node T_7573 = eq(take_pc_wb, UInt<1>("h00")) - node T_7574 = and(mem_xcpt, T_7573) - wb_reg_xcpt <= T_7574 + node T_7380 = or(ex_ctrl.mem, ex_ctrl.rocc) + node T_7381 = and(ex_ctrl.rxs2, T_7380) + when T_7381 : + mem_reg_rs2 <= T_6995 + skip + skip + node T_7382 = or(mem_reg_xcpt_interrupt, mem_reg_xcpt) + node T_7383 = and(want_take_pc_mem, mem_npc_misaligned) + node T_7385 = and(mem_reg_valid, mem_ctrl.mem) + node T_7386 = and(T_7385, io.dmem.xcpt.ma.st) + node T_7388 = and(mem_reg_valid, mem_ctrl.mem) + node T_7389 = and(T_7388, io.dmem.xcpt.ma.ld) + node T_7391 = and(mem_reg_valid, mem_ctrl.mem) + node T_7392 = and(T_7391, io.dmem.xcpt.pf.st) + node T_7394 = and(mem_reg_valid, mem_ctrl.mem) + node T_7395 = and(T_7394, io.dmem.xcpt.pf.ld) + node T_7397 = or(T_7382, T_7383) + node T_7398 = or(T_7397, T_7386) + node T_7399 = or(T_7398, T_7389) + node T_7400 = or(T_7399, T_7392) + node mem_xcpt = or(T_7400, T_7395) + node T_7402 = mux(T_7392, UInt<3>("h07"), UInt<3>("h05")) + node T_7403 = mux(T_7389, UInt<3>("h04"), T_7402) + node T_7404 = mux(T_7386, UInt<3>("h06"), T_7403) + node T_7405 = mux(T_7383, UInt<1>("h00"), T_7404) + node mem_cause = mux(T_7382, mem_reg_cause, T_7405) + node T_7407 = and(mem_reg_valid, mem_ctrl.wxd) + node dcache_kill_mem = and(T_7407, io.dmem.replay_next.valid) + node T_7409 = and(mem_reg_valid, mem_ctrl.fp) + node fpu_kill_mem = and(T_7409, io.fpu.nack_mem) + node T_7411 = or(dcache_kill_mem, mem_reg_replay) + node replay_mem = or(T_7411, fpu_kill_mem) + node T_7413 = or(dcache_kill_mem, take_pc_wb) + node T_7414 = or(T_7413, mem_reg_xcpt) + node T_7416 = eq(mem_reg_valid, UInt<1>("h00")) + node killm_common = or(T_7414, T_7416) + node T_7418 = and(div.io.req.ready, div.io.req.valid) + reg T_7419 : UInt<1>, clk + T_7419 <= T_7418 + node T_7420 = and(killm_common, T_7419) + div.io.kill <= T_7420 + node T_7421 = or(killm_common, mem_xcpt) + node ctrl_killm = or(T_7421, fpu_kill_mem) + node T_7424 = eq(ctrl_killm, UInt<1>("h00")) + wb_reg_valid <= T_7424 + node T_7426 = eq(take_pc_wb, UInt<1>("h00")) + node T_7427 = and(replay_mem, T_7426) + wb_reg_replay <= T_7427 + node T_7429 = eq(take_pc_wb, UInt<1>("h00")) + node T_7430 = and(mem_xcpt, T_7429) + wb_reg_xcpt <= T_7430 when mem_xcpt : wb_reg_cause <= mem_cause skip - node T_7575 = or(mem_reg_valid, mem_reg_replay) - node T_7576 = or(T_7575, mem_reg_xcpt_interrupt) - when T_7576 : + node T_7431 = or(mem_reg_valid, mem_reg_replay) + node T_7432 = or(T_7431, mem_reg_xcpt_interrupt) + when T_7432 : wb_ctrl <- mem_ctrl - node T_7577 = and(mem_ctrl.fp, mem_ctrl.wxd) - node T_7578 = mux(T_7577, io.fpu.toint_data, mem_int_wdata) - wb_reg_wdata <= T_7578 + node T_7433 = and(mem_ctrl.fp, mem_ctrl.wxd) + node T_7434 = mux(T_7433, io.fpu.toint_data, mem_int_wdata) + wb_reg_wdata <= T_7434 when mem_ctrl.rocc : wb_reg_rs2 <= mem_reg_rs2 skip wb_reg_inst <= mem_reg_inst wb_reg_pc <= mem_reg_pc skip - node T_7579 = or(wb_ctrl.div, wb_dcache_miss) - node wb_set_sboard = or(T_7579, wb_ctrl.rocc) + node T_7435 = or(wb_ctrl.div, wb_dcache_miss) + node wb_set_sboard = or(T_7435, wb_ctrl.rocc) node replay_wb_common = or(io.dmem.resp.bits.nack, wb_reg_replay) - node T_7582 = and(wb_reg_valid, wb_ctrl.rocc) - node T_7584 = eq(replay_wb_common, UInt<1>("h00")) - node wb_rocc_val = and(T_7582, T_7584) - node T_7586 = and(wb_reg_valid, wb_ctrl.rocc) - node T_7588 = eq(io.rocc.cmd.ready, UInt<1>("h00")) - node T_7589 = and(T_7586, T_7588) - node replay_wb = or(replay_wb_common, T_7589) + node T_7438 = and(wb_reg_valid, wb_ctrl.rocc) + node T_7440 = eq(replay_wb_common, UInt<1>("h00")) + node wb_rocc_val = and(T_7438, T_7440) + node T_7442 = and(wb_reg_valid, wb_ctrl.rocc) + node T_7444 = eq(io.rocc.cmd.ready, UInt<1>("h00")) + node T_7445 = and(T_7442, T_7444) + node replay_wb = or(replay_wb_common, T_7445) node wb_xcpt = or(wb_reg_xcpt, csr.io.csr_xcpt) - node T_7592 = or(replay_wb, wb_xcpt) - node T_7593 = or(T_7592, csr.io.eret) - take_pc_wb <= T_7593 + node T_7448 = or(replay_wb, wb_xcpt) + node T_7449 = or(T_7448, csr.io.eret) + take_pc_wb <= T_7449 when wb_rocc_val : - node T_7595 = eq(io.rocc.cmd.ready, UInt<1>("h00")) - wb_reg_rocc_pending <= T_7595 + node T_7451 = eq(io.rocc.cmd.ready, UInt<1>("h00")) + wb_reg_rocc_pending <= T_7451 skip when wb_reg_xcpt : wb_reg_rocc_pending <= UInt<1>("h00") skip - node T_7597 = bit(io.dmem.resp.bits.tag, 0) - node T_7598 = bit(T_7597, 0) - node dmem_resp_xpu = eq(T_7598, UInt<1>("h00")) - node T_7601 = bit(io.dmem.resp.bits.tag, 0) - node dmem_resp_fpu = bit(T_7601, 0) + node T_7453 = bits(io.dmem.resp.bits.tag, 0, 0) + node T_7454 = bits(T_7453, 0, 0) + node dmem_resp_xpu = eq(T_7454, UInt<1>("h00")) + node T_7457 = bits(io.dmem.resp.bits.tag, 0, 0) + node dmem_resp_fpu = bits(T_7457, 0, 0) node dmem_resp_waddr = bits(io.dmem.resp.bits.tag, 5, 1) node dmem_resp_valid = and(io.dmem.resp.valid, io.dmem.resp.bits.has_data) node dmem_resp_replay = and(io.dmem.resp.bits.replay, io.dmem.resp.bits.has_data) - node T_7606 = and(wb_reg_valid, wb_ctrl.wxd) - node T_7608 = eq(T_7606, UInt<1>("h00")) - div.io.resp.ready <= T_7608 + node T_7462 = and(wb_reg_valid, wb_ctrl.wxd) + node T_7464 = eq(T_7462, UInt<1>("h00")) + div.io.resp.ready <= T_7464 wire ll_wdata : UInt<?> ll_wdata <= div.io.resp.bits.data wire ll_waddr : UInt<?> ll_waddr <= div.io.resp.bits.tag - node T_7611 = and(div.io.resp.ready, div.io.resp.valid) + node T_7467 = and(div.io.resp.ready, div.io.resp.valid) wire ll_wen : UInt<1> - ll_wen <= T_7611 - node T_7613 = and(dmem_resp_replay, dmem_resp_xpu) - when T_7613 : + ll_wen <= T_7467 + node T_7469 = and(dmem_resp_replay, dmem_resp_xpu) + when T_7469 : div.io.resp.ready <= UInt<1>("h00") ll_waddr <= dmem_resp_waddr ll_wen <= UInt<1>("h01") skip - node T_7617 = eq(replay_wb, UInt<1>("h00")) - node T_7618 = and(wb_reg_valid, T_7617) - node T_7620 = eq(csr.io.csr_xcpt, UInt<1>("h00")) - node wb_valid = and(T_7618, T_7620) + node T_7473 = eq(replay_wb, UInt<1>("h00")) + node T_7474 = and(wb_reg_valid, T_7473) + node T_7476 = eq(csr.io.csr_xcpt, UInt<1>("h00")) + node wb_valid = and(T_7474, T_7476) node wb_wen = and(wb_valid, wb_ctrl.wxd) node rf_wen = or(wb_wen, ll_wen) node rf_waddr = mux(ll_wen, ll_waddr, wb_waddr) - node T_7625 = and(dmem_resp_valid, dmem_resp_xpu) - node T_7626 = neq(wb_ctrl.csr, UInt<3>("h00")) - node T_7627 = mux(T_7626, csr.io.rw.rdata, wb_reg_wdata) - node T_7628 = mux(ll_wen, ll_wdata, T_7627) - node rf_wdata = mux(T_7625, io.dmem.resp.bits.data, T_7628) + node T_7481 = and(dmem_resp_valid, dmem_resp_xpu) + node T_7482 = neq(wb_ctrl.csr, UInt<3>("h00")) + node T_7483 = mux(T_7482, csr.io.rw.rdata, wb_reg_wdata) + node T_7484 = mux(ll_wen, ll_wdata, T_7483) + node rf_wdata = mux(T_7481, io.dmem.resp.bits.data, T_7484) when rf_wen : - node T_7631 = neq(rf_waddr, UInt<1>("h00")) - when T_7631 : - node T_7632 = bits(rf_waddr, 4, 0) - node T_7633 = not(T_7632) - infer mport T_7634 = T_6795[T_7633], clk - T_7634 <= rf_wdata - node T_7635 = eq(rf_waddr, id_raddr1) - when T_7635 : - T_6797 <= rf_wdata + node T_7487 = neq(rf_waddr, UInt<1>("h00")) + when T_7487 : + node T_7488 = bits(rf_waddr, 4, 0) + node T_7489 = not(T_7488) + infer mport T_7490 = T_6766[T_7489], clk + T_7490 <= rf_wdata + node T_7491 = eq(rf_waddr, id_raddr1) + when T_7491 : + T_6768 <= rf_wdata skip - node T_7636 = eq(rf_waddr, id_raddr2) - when T_7636 : - T_6809 <= rf_wdata + node T_7492 = eq(rf_waddr, id_raddr2) + when T_7492 : + T_6779 <= rf_wdata skip skip skip @@ -24258,344 +17575,337 @@ circuit Top : io.ptw.ptbr <= csr.io.ptbr io.ptw.invalidate <= csr.io.fatc io.ptw.status <- csr.io.status - node T_7653 = bits(wb_reg_inst, 31, 20) - csr.io.rw.addr <= T_7653 - node T_7654 = mux(wb_reg_valid, wb_ctrl.csr, UInt<3>("h00")) - csr.io.rw.cmd <= T_7654 + node T_7509 = bits(wb_reg_inst, 31, 20) + csr.io.rw.addr <= T_7509 + node T_7510 = mux(wb_reg_valid, wb_ctrl.csr, UInt<3>("h00")) + csr.io.rw.cmd <= T_7510 csr.io.rw.wdata <= wb_reg_wdata - node T_7656 = neq(id_raddr1, UInt<1>("h00")) - node T_7657 = and(id_ctrl.rxs1, T_7656) - node T_7659 = neq(id_raddr2, UInt<1>("h00")) - node T_7660 = and(id_ctrl.rxs2, T_7659) - node T_7662 = neq(id_waddr, UInt<1>("h00")) - node T_7663 = and(id_ctrl.wxd, T_7662) - reg T_7665 : UInt<32>, clk, reset, UInt<32>("h00") - node T_7668 = dshl(UInt<1>("h01"), ll_waddr) - node T_7670 = mux(ll_wen, T_7668, UInt<1>("h00")) - node T_7671 = not(T_7670) - node T_7672 = and(T_7665, T_7671) - node T_7673 = or(UInt<1>("h00"), ll_wen) - when T_7673 : - T_7665 <= T_7672 - skip - node T_7674 = dshr(T_7672, id_raddr1) - node T_7675 = bit(T_7674, 0) - node T_7676 = and(T_7657, T_7675) - node T_7677 = dshr(T_7672, id_raddr2) - node T_7678 = bit(T_7677, 0) - node T_7679 = and(T_7660, T_7678) - node T_7680 = dshr(T_7672, id_waddr) - node T_7681 = bit(T_7680, 0) - node T_7682 = and(T_7663, T_7681) - node T_7683 = or(T_7676, T_7679) - node id_sboard_hazard = or(T_7683, T_7682) - node T_7685 = and(wb_set_sboard, wb_wen) - node T_7687 = dshl(UInt<1>("h01"), wb_waddr) - node T_7689 = mux(T_7685, T_7687, UInt<1>("h00")) - node T_7690 = or(T_7672, T_7689) - node T_7691 = or(T_7673, T_7685) - when T_7691 : - T_7665 <= T_7690 - skip - node T_7692 = neq(ex_ctrl.csr, UInt<3>("h00")) - node T_7693 = or(T_7692, ex_ctrl.jalr) - node T_7694 = or(T_7693, ex_ctrl.mem) - node T_7695 = or(T_7694, ex_ctrl.div) - node T_7696 = or(T_7695, ex_ctrl.fp) - node ex_cannot_bypass = or(T_7696, ex_ctrl.rocc) - node T_7698 = eq(id_raddr1, ex_waddr) - node T_7699 = and(T_7657, T_7698) - node T_7700 = eq(id_raddr2, ex_waddr) - node T_7701 = and(T_7660, T_7700) - node T_7702 = eq(id_waddr, ex_waddr) - node T_7703 = and(T_7663, T_7702) - node T_7704 = or(T_7699, T_7701) - node T_7705 = or(T_7704, T_7703) - node data_hazard_ex = and(ex_ctrl.wxd, T_7705) - node T_7707 = eq(id_raddr1, ex_waddr) - node T_7708 = and(io.fpu.dec.ren1, T_7707) - node T_7709 = eq(id_raddr2, ex_waddr) - node T_7710 = and(io.fpu.dec.ren2, T_7709) - node T_7711 = eq(id_raddr3, ex_waddr) - node T_7712 = and(io.fpu.dec.ren3, T_7711) - node T_7713 = eq(id_waddr, ex_waddr) - node T_7714 = and(io.fpu.dec.wen, T_7713) - node T_7715 = or(T_7708, T_7710) - node T_7716 = or(T_7715, T_7712) - node T_7717 = or(T_7716, T_7714) - node fp_data_hazard_ex = and(ex_ctrl.wfd, T_7717) - node T_7719 = and(data_hazard_ex, ex_cannot_bypass) - node T_7720 = or(T_7719, fp_data_hazard_ex) - node id_ex_hazard = and(ex_reg_valid, T_7720) + node T_7512 = neq(id_raddr1, UInt<1>("h00")) + node T_7513 = and(id_ctrl.rxs1, T_7512) + node T_7515 = neq(id_raddr2, UInt<1>("h00")) + node T_7516 = and(id_ctrl.rxs2, T_7515) + node T_7518 = neq(id_waddr, UInt<1>("h00")) + node T_7519 = and(id_ctrl.wxd, T_7518) + reg T_7521 : UInt<32>, clk with : (reset => (reset, UInt<32>("h00"))) + node T_7524 = dshl(UInt<1>("h01"), ll_waddr) + node T_7526 = mux(ll_wen, T_7524, UInt<1>("h00")) + node T_7527 = not(T_7526) + node T_7528 = and(T_7521, T_7527) + node T_7529 = or(UInt<1>("h00"), ll_wen) + when T_7529 : + T_7521 <= T_7528 + skip + node T_7530 = dshr(T_7528, id_raddr1) + node T_7531 = bits(T_7530, 0, 0) + node T_7532 = and(T_7513, T_7531) + node T_7533 = dshr(T_7528, id_raddr2) + node T_7534 = bits(T_7533, 0, 0) + node T_7535 = and(T_7516, T_7534) + node T_7536 = dshr(T_7528, id_waddr) + node T_7537 = bits(T_7536, 0, 0) + node T_7538 = and(T_7519, T_7537) + node T_7539 = or(T_7532, T_7535) + node id_sboard_hazard = or(T_7539, T_7538) + node T_7541 = and(wb_set_sboard, wb_wen) + node T_7543 = dshl(UInt<1>("h01"), wb_waddr) + node T_7545 = mux(T_7541, T_7543, UInt<1>("h00")) + node T_7546 = or(T_7528, T_7545) + node T_7547 = or(T_7529, T_7541) + when T_7547 : + T_7521 <= T_7546 + skip + node T_7548 = neq(ex_ctrl.csr, UInt<3>("h00")) + node T_7549 = or(T_7548, ex_ctrl.jalr) + node T_7550 = or(T_7549, ex_ctrl.mem) + node T_7551 = or(T_7550, ex_ctrl.div) + node T_7552 = or(T_7551, ex_ctrl.fp) + node ex_cannot_bypass = or(T_7552, ex_ctrl.rocc) + node T_7554 = eq(id_raddr1, ex_waddr) + node T_7555 = and(T_7513, T_7554) + node T_7556 = eq(id_raddr2, ex_waddr) + node T_7557 = and(T_7516, T_7556) + node T_7558 = eq(id_waddr, ex_waddr) + node T_7559 = and(T_7519, T_7558) + node T_7560 = or(T_7555, T_7557) + node T_7561 = or(T_7560, T_7559) + node data_hazard_ex = and(ex_ctrl.wxd, T_7561) + node T_7563 = eq(id_raddr1, ex_waddr) + node T_7564 = and(io.fpu.dec.ren1, T_7563) + node T_7565 = eq(id_raddr2, ex_waddr) + node T_7566 = and(io.fpu.dec.ren2, T_7565) + node T_7567 = eq(id_raddr3, ex_waddr) + node T_7568 = and(io.fpu.dec.ren3, T_7567) + node T_7569 = eq(id_waddr, ex_waddr) + node T_7570 = and(io.fpu.dec.wen, T_7569) + node T_7571 = or(T_7564, T_7566) + node T_7572 = or(T_7571, T_7568) + node T_7573 = or(T_7572, T_7570) + node fp_data_hazard_ex = and(ex_ctrl.wfd, T_7573) + node T_7575 = and(data_hazard_ex, ex_cannot_bypass) + node T_7576 = or(T_7575, fp_data_hazard_ex) + node id_ex_hazard = and(ex_reg_valid, T_7576) node mem_mem_cmd_bh = and(UInt<1>("h01"), mem_reg_slow_bypass) - node T_7724 = neq(mem_ctrl.csr, UInt<3>("h00")) - node T_7725 = and(mem_ctrl.mem, mem_mem_cmd_bh) - node T_7726 = or(T_7724, T_7725) - node T_7727 = or(T_7726, mem_ctrl.div) - node T_7728 = or(T_7727, mem_ctrl.fp) - node mem_cannot_bypass = or(T_7728, mem_ctrl.rocc) - node T_7730 = eq(id_raddr1, mem_waddr) - node T_7731 = and(T_7657, T_7730) - node T_7732 = eq(id_raddr2, mem_waddr) - node T_7733 = and(T_7660, T_7732) - node T_7734 = eq(id_waddr, mem_waddr) - node T_7735 = and(T_7663, T_7734) - node T_7736 = or(T_7731, T_7733) - node T_7737 = or(T_7736, T_7735) - node data_hazard_mem = and(mem_ctrl.wxd, T_7737) - node T_7739 = eq(id_raddr1, mem_waddr) - node T_7740 = and(io.fpu.dec.ren1, T_7739) - node T_7741 = eq(id_raddr2, mem_waddr) - node T_7742 = and(io.fpu.dec.ren2, T_7741) - node T_7743 = eq(id_raddr3, mem_waddr) - node T_7744 = and(io.fpu.dec.ren3, T_7743) - node T_7745 = eq(id_waddr, mem_waddr) - node T_7746 = and(io.fpu.dec.wen, T_7745) - node T_7747 = or(T_7740, T_7742) - node T_7748 = or(T_7747, T_7744) - node T_7749 = or(T_7748, T_7746) - node fp_data_hazard_mem = and(mem_ctrl.wfd, T_7749) - node T_7751 = and(data_hazard_mem, mem_cannot_bypass) - node T_7752 = or(T_7751, fp_data_hazard_mem) - node id_mem_hazard = and(mem_reg_valid, T_7752) - node T_7754 = and(mem_reg_valid, data_hazard_mem) - node T_7755 = and(T_7754, mem_ctrl.mem) - id_load_use <= T_7755 - node T_7756 = eq(id_raddr1, wb_waddr) - node T_7757 = and(T_7657, T_7756) - node T_7758 = eq(id_raddr2, wb_waddr) - node T_7759 = and(T_7660, T_7758) - node T_7760 = eq(id_waddr, wb_waddr) - node T_7761 = and(T_7663, T_7760) - node T_7762 = or(T_7757, T_7759) - node T_7763 = or(T_7762, T_7761) - node data_hazard_wb = and(wb_ctrl.wxd, T_7763) - node T_7765 = eq(id_raddr1, wb_waddr) - node T_7766 = and(io.fpu.dec.ren1, T_7765) - node T_7767 = eq(id_raddr2, wb_waddr) - node T_7768 = and(io.fpu.dec.ren2, T_7767) - node T_7769 = eq(id_raddr3, wb_waddr) - node T_7770 = and(io.fpu.dec.ren3, T_7769) - node T_7771 = eq(id_waddr, wb_waddr) - node T_7772 = and(io.fpu.dec.wen, T_7771) - node T_7773 = or(T_7766, T_7768) - node T_7774 = or(T_7773, T_7770) - node T_7775 = or(T_7774, T_7772) - node fp_data_hazard_wb = and(wb_ctrl.wfd, T_7775) - node T_7777 = and(data_hazard_wb, wb_set_sboard) - node T_7778 = or(T_7777, fp_data_hazard_wb) - node id_wb_hazard = and(wb_reg_valid, T_7778) - reg T_7781 : UInt<32>, clk, reset, UInt<32>("h00") - node T_7783 = and(wb_dcache_miss, wb_ctrl.wfd) - node T_7784 = or(T_7783, io.fpu.sboard_set) - node T_7785 = and(T_7784, wb_valid) - node T_7787 = dshl(UInt<1>("h01"), wb_waddr) - node T_7789 = mux(T_7785, T_7787, UInt<1>("h00")) - node T_7790 = or(T_7781, T_7789) - node T_7791 = or(UInt<1>("h00"), T_7785) - when T_7791 : - T_7781 <= T_7790 - skip - node T_7792 = and(dmem_resp_replay, dmem_resp_fpu) - node T_7794 = dshl(UInt<1>("h01"), dmem_resp_waddr) - node T_7796 = mux(T_7792, T_7794, UInt<1>("h00")) - node T_7797 = not(T_7796) - node T_7798 = and(T_7790, T_7797) - node T_7799 = or(T_7791, T_7792) - when T_7799 : - T_7781 <= T_7798 - skip - node T_7801 = dshl(UInt<1>("h01"), io.fpu.sboard_clra) - node T_7803 = mux(io.fpu.sboard_clr, T_7801, UInt<1>("h00")) - node T_7804 = not(T_7803) - node T_7805 = and(T_7798, T_7804) - node T_7806 = or(T_7799, io.fpu.sboard_clr) - when T_7806 : - T_7781 <= T_7805 - skip - node T_7808 = eq(io.fpu.fcsr_rdy, UInt<1>("h00")) - node T_7809 = and(id_csr_en, T_7808) - node T_7810 = dshr(T_7781, id_raddr1) - node T_7811 = bit(T_7810, 0) - node T_7812 = and(io.fpu.dec.ren1, T_7811) - node T_7813 = dshr(T_7781, id_raddr2) - node T_7814 = bit(T_7813, 0) - node T_7815 = and(io.fpu.dec.ren2, T_7814) - node T_7816 = dshr(T_7781, id_raddr3) - node T_7817 = bit(T_7816, 0) - node T_7818 = and(io.fpu.dec.ren3, T_7817) - node T_7819 = dshr(T_7781, id_waddr) - node T_7820 = bit(T_7819, 0) - node T_7821 = and(io.fpu.dec.wen, T_7820) - node T_7822 = or(T_7812, T_7815) - node T_7823 = or(T_7822, T_7818) - node T_7824 = or(T_7823, T_7821) - node id_stall_fpu = or(T_7809, T_7824) - node T_7826 = or(id_ex_hazard, id_mem_hazard) - node T_7827 = or(T_7826, id_wb_hazard) - node T_7828 = or(T_7827, id_sboard_hazard) - node T_7829 = and(id_ctrl.fp, id_stall_fpu) - node T_7830 = or(T_7828, T_7829) - node T_7832 = eq(io.dmem.req.ready, UInt<1>("h00")) - node T_7833 = and(id_ctrl.mem, T_7832) - node T_7834 = or(T_7830, T_7833) - node T_7836 = and(UInt<1>("h00"), wb_reg_rocc_pending) - node T_7837 = and(T_7836, id_ctrl.rocc) - node T_7839 = eq(io.rocc.cmd.ready, UInt<1>("h00")) - node T_7840 = and(T_7837, T_7839) - node T_7841 = or(T_7834, T_7840) - node T_7842 = or(T_7841, id_do_fence) - node ctrl_stalld = or(T_7842, csr.io.csr_stall) - node T_7845 = eq(io.imem.resp.valid, UInt<1>("h00")) - node T_7846 = or(T_7845, take_pc_mem_wb) - node T_7847 = or(T_7846, ctrl_stalld) - node T_7848 = or(T_7847, csr.io.interrupt) - ctrl_killd <= T_7848 + node T_7580 = neq(mem_ctrl.csr, UInt<3>("h00")) + node T_7581 = and(mem_ctrl.mem, mem_mem_cmd_bh) + node T_7582 = or(T_7580, T_7581) + node T_7583 = or(T_7582, mem_ctrl.div) + node T_7584 = or(T_7583, mem_ctrl.fp) + node mem_cannot_bypass = or(T_7584, mem_ctrl.rocc) + node T_7586 = eq(id_raddr1, mem_waddr) + node T_7587 = and(T_7513, T_7586) + node T_7588 = eq(id_raddr2, mem_waddr) + node T_7589 = and(T_7516, T_7588) + node T_7590 = eq(id_waddr, mem_waddr) + node T_7591 = and(T_7519, T_7590) + node T_7592 = or(T_7587, T_7589) + node T_7593 = or(T_7592, T_7591) + node data_hazard_mem = and(mem_ctrl.wxd, T_7593) + node T_7595 = eq(id_raddr1, mem_waddr) + node T_7596 = and(io.fpu.dec.ren1, T_7595) + node T_7597 = eq(id_raddr2, mem_waddr) + node T_7598 = and(io.fpu.dec.ren2, T_7597) + node T_7599 = eq(id_raddr3, mem_waddr) + node T_7600 = and(io.fpu.dec.ren3, T_7599) + node T_7601 = eq(id_waddr, mem_waddr) + node T_7602 = and(io.fpu.dec.wen, T_7601) + node T_7603 = or(T_7596, T_7598) + node T_7604 = or(T_7603, T_7600) + node T_7605 = or(T_7604, T_7602) + node fp_data_hazard_mem = and(mem_ctrl.wfd, T_7605) + node T_7607 = and(data_hazard_mem, mem_cannot_bypass) + node T_7608 = or(T_7607, fp_data_hazard_mem) + node id_mem_hazard = and(mem_reg_valid, T_7608) + node T_7610 = and(mem_reg_valid, data_hazard_mem) + node T_7611 = and(T_7610, mem_ctrl.mem) + id_load_use <= T_7611 + node T_7612 = eq(id_raddr1, wb_waddr) + node T_7613 = and(T_7513, T_7612) + node T_7614 = eq(id_raddr2, wb_waddr) + node T_7615 = and(T_7516, T_7614) + node T_7616 = eq(id_waddr, wb_waddr) + node T_7617 = and(T_7519, T_7616) + node T_7618 = or(T_7613, T_7615) + node T_7619 = or(T_7618, T_7617) + node data_hazard_wb = and(wb_ctrl.wxd, T_7619) + node T_7621 = eq(id_raddr1, wb_waddr) + node T_7622 = and(io.fpu.dec.ren1, T_7621) + node T_7623 = eq(id_raddr2, wb_waddr) + node T_7624 = and(io.fpu.dec.ren2, T_7623) + node T_7625 = eq(id_raddr3, wb_waddr) + node T_7626 = and(io.fpu.dec.ren3, T_7625) + node T_7627 = eq(id_waddr, wb_waddr) + node T_7628 = and(io.fpu.dec.wen, T_7627) + node T_7629 = or(T_7622, T_7624) + node T_7630 = or(T_7629, T_7626) + node T_7631 = or(T_7630, T_7628) + node fp_data_hazard_wb = and(wb_ctrl.wfd, T_7631) + node T_7633 = and(data_hazard_wb, wb_set_sboard) + node T_7634 = or(T_7633, fp_data_hazard_wb) + node id_wb_hazard = and(wb_reg_valid, T_7634) + reg T_7637 : UInt<32>, clk with : (reset => (reset, UInt<32>("h00"))) + node T_7639 = and(wb_dcache_miss, wb_ctrl.wfd) + node T_7640 = or(T_7639, io.fpu.sboard_set) + node T_7641 = and(T_7640, wb_valid) + node T_7643 = dshl(UInt<1>("h01"), wb_waddr) + node T_7645 = mux(T_7641, T_7643, UInt<1>("h00")) + node T_7646 = or(T_7637, T_7645) + node T_7647 = or(UInt<1>("h00"), T_7641) + when T_7647 : + T_7637 <= T_7646 + skip + node T_7648 = and(dmem_resp_replay, dmem_resp_fpu) + node T_7650 = dshl(UInt<1>("h01"), dmem_resp_waddr) + node T_7652 = mux(T_7648, T_7650, UInt<1>("h00")) + node T_7653 = not(T_7652) + node T_7654 = and(T_7646, T_7653) + node T_7655 = or(T_7647, T_7648) + when T_7655 : + T_7637 <= T_7654 + skip + node T_7657 = dshl(UInt<1>("h01"), io.fpu.sboard_clra) + node T_7659 = mux(io.fpu.sboard_clr, T_7657, UInt<1>("h00")) + node T_7660 = not(T_7659) + node T_7661 = and(T_7654, T_7660) + node T_7662 = or(T_7655, io.fpu.sboard_clr) + when T_7662 : + T_7637 <= T_7661 + skip + node T_7664 = eq(io.fpu.fcsr_rdy, UInt<1>("h00")) + node T_7665 = and(id_csr_en, T_7664) + node T_7666 = dshr(T_7637, id_raddr1) + node T_7667 = bits(T_7666, 0, 0) + node T_7668 = and(io.fpu.dec.ren1, T_7667) + node T_7669 = dshr(T_7637, id_raddr2) + node T_7670 = bits(T_7669, 0, 0) + node T_7671 = and(io.fpu.dec.ren2, T_7670) + node T_7672 = dshr(T_7637, id_raddr3) + node T_7673 = bits(T_7672, 0, 0) + node T_7674 = and(io.fpu.dec.ren3, T_7673) + node T_7675 = dshr(T_7637, id_waddr) + node T_7676 = bits(T_7675, 0, 0) + node T_7677 = and(io.fpu.dec.wen, T_7676) + node T_7678 = or(T_7668, T_7671) + node T_7679 = or(T_7678, T_7674) + node T_7680 = or(T_7679, T_7677) + node id_stall_fpu = or(T_7665, T_7680) + node T_7682 = or(id_ex_hazard, id_mem_hazard) + node T_7683 = or(T_7682, id_wb_hazard) + node T_7684 = or(T_7683, id_sboard_hazard) + node T_7685 = and(id_ctrl.fp, id_stall_fpu) + node T_7686 = or(T_7684, T_7685) + node T_7688 = eq(io.dmem.req.ready, UInt<1>("h00")) + node T_7689 = and(id_ctrl.mem, T_7688) + node T_7690 = or(T_7686, T_7689) + node T_7692 = and(UInt<1>("h00"), wb_reg_rocc_pending) + node T_7693 = and(T_7692, id_ctrl.rocc) + node T_7695 = eq(io.rocc.cmd.ready, UInt<1>("h00")) + node T_7696 = and(T_7693, T_7695) + node T_7697 = or(T_7690, T_7696) + node T_7698 = or(T_7697, id_do_fence) + node ctrl_stalld = or(T_7698, csr.io.csr_stall) + node T_7701 = eq(io.imem.resp.valid, UInt<1>("h00")) + node T_7702 = or(T_7701, take_pc_mem_wb) + node T_7703 = or(T_7702, ctrl_stalld) + node T_7704 = or(T_7703, csr.io.interrupt) + ctrl_killd <= T_7704 io.imem.req.valid <= take_pc_mem_wb - node T_7849 = or(wb_xcpt, csr.io.eret) - node T_7850 = mux(replay_wb, wb_reg_pc, mem_npc) - node T_7851 = mux(T_7849, csr.io.evec, T_7850) - io.imem.req.bits.pc <= T_7851 - node T_7852 = and(wb_reg_valid, wb_ctrl.fence_i) - io.imem.invalidate <= T_7852 - node T_7854 = eq(ctrl_stalld, UInt<1>("h00")) - node T_7855 = or(T_7854, csr.io.interrupt) - io.imem.resp.ready <= T_7855 - node T_7857 = eq(mem_npc_misaligned, UInt<1>("h00")) - node T_7858 = and(mem_reg_valid, T_7857) - node T_7859 = and(T_7858, mem_wrong_npc) - node T_7860 = and(mem_ctrl.branch, mem_br_taken) - node T_7861 = or(T_7860, mem_ctrl.jalr) - node T_7862 = or(T_7861, mem_ctrl.jal) - node T_7863 = and(T_7859, T_7862) - node T_7865 = eq(take_pc_wb, UInt<1>("h00")) - node T_7866 = and(T_7863, T_7865) - io.imem.btb_update.valid <= T_7866 - node T_7867 = or(mem_ctrl.jal, mem_ctrl.jalr) - io.imem.btb_update.bits.isJump <= T_7867 - node T_7868 = bits(mem_reg_inst, 19, 15) - node T_7871 = and(T_7868, UInt<5>("h019")) - node T_7872 = eq(UInt<1>("h01"), T_7871) - node T_7873 = and(mem_ctrl.jalr, T_7872) - io.imem.btb_update.bits.isReturn <= T_7873 + node T_7705 = or(wb_xcpt, csr.io.eret) + node T_7706 = mux(replay_wb, wb_reg_pc, mem_npc) + node T_7707 = mux(T_7705, csr.io.evec, T_7706) + io.imem.req.bits.pc <= T_7707 + node T_7708 = and(wb_reg_valid, wb_ctrl.fence_i) + io.imem.invalidate <= T_7708 + node T_7710 = eq(ctrl_stalld, UInt<1>("h00")) + node T_7711 = or(T_7710, csr.io.interrupt) + io.imem.resp.ready <= T_7711 + node T_7713 = eq(mem_npc_misaligned, UInt<1>("h00")) + node T_7714 = and(mem_reg_valid, T_7713) + node T_7715 = and(T_7714, mem_wrong_npc) + node T_7716 = and(mem_ctrl.branch, mem_br_taken) + node T_7717 = or(T_7716, mem_ctrl.jalr) + node T_7718 = or(T_7717, mem_ctrl.jal) + node T_7719 = and(T_7715, T_7718) + node T_7721 = eq(take_pc_wb, UInt<1>("h00")) + node T_7722 = and(T_7719, T_7721) + io.imem.btb_update.valid <= T_7722 + node T_7723 = or(mem_ctrl.jal, mem_ctrl.jalr) + io.imem.btb_update.bits.isJump <= T_7723 + node T_7724 = bits(mem_reg_inst, 19, 15) + node T_7727 = and(T_7724, UInt<5>("h019")) + node T_7728 = eq(UInt<1>("h01"), T_7727) + node T_7729 = and(mem_ctrl.jalr, T_7728) + io.imem.btb_update.bits.isReturn <= T_7729 io.imem.btb_update.bits.pc <= mem_reg_pc io.imem.btb_update.bits.target <= io.imem.req.bits.pc io.imem.btb_update.bits.br_pc <= mem_reg_pc io.imem.btb_update.bits.prediction.valid <= mem_reg_btb_hit io.imem.btb_update.bits.prediction.bits <- mem_reg_btb_resp - node T_7874 = and(mem_reg_valid, mem_ctrl.branch) - node T_7876 = eq(take_pc_wb, UInt<1>("h00")) - node T_7877 = and(T_7874, T_7876) - io.imem.bht_update.valid <= T_7877 + node T_7730 = and(mem_reg_valid, mem_ctrl.branch) + node T_7732 = eq(take_pc_wb, UInt<1>("h00")) + node T_7733 = and(T_7730, T_7732) + io.imem.bht_update.valid <= T_7733 io.imem.bht_update.bits.pc <= mem_reg_pc io.imem.bht_update.bits.taken <= mem_br_taken io.imem.bht_update.bits.mispredict <= mem_wrong_npc io.imem.bht_update.bits.prediction <- io.imem.btb_update.bits.prediction - node T_7878 = and(mem_reg_valid, io.imem.btb_update.bits.isJump) - node T_7880 = eq(mem_npc_misaligned, UInt<1>("h00")) - node T_7881 = and(T_7878, T_7880) - node T_7883 = eq(take_pc_wb, UInt<1>("h00")) - node T_7884 = and(T_7881, T_7883) - io.imem.ras_update.valid <= T_7884 + node T_7734 = and(mem_reg_valid, io.imem.btb_update.bits.isJump) + node T_7736 = eq(mem_npc_misaligned, UInt<1>("h00")) + node T_7737 = and(T_7734, T_7736) + node T_7739 = eq(take_pc_wb, UInt<1>("h00")) + node T_7740 = and(T_7737, T_7739) + io.imem.ras_update.valid <= T_7740 io.imem.ras_update.bits.returnAddr <= mem_int_wdata - node T_7885 = bit(mem_waddr, 0) - node T_7886 = and(mem_ctrl.wxd, T_7885) - io.imem.ras_update.bits.isCall <= T_7886 + node T_7741 = bits(mem_waddr, 0, 0) + node T_7742 = and(mem_ctrl.wxd, T_7741) + io.imem.ras_update.bits.isCall <= T_7742 io.imem.ras_update.bits.isReturn <= io.imem.btb_update.bits.isReturn io.imem.ras_update.bits.prediction <- io.imem.btb_update.bits.prediction - node T_7888 = eq(ctrl_killd, UInt<1>("h00")) - node T_7889 = and(T_7888, id_ctrl.fp) - io.fpu.valid <= T_7889 + node T_7744 = eq(ctrl_killd, UInt<1>("h00")) + node T_7745 = and(T_7744, id_ctrl.fp) + io.fpu.valid <= T_7745 io.fpu.killx <= ctrl_killx io.fpu.killm <= killm_common io.fpu.inst <= io.imem.resp.bits.data[0] - io.fpu.fromint_data <= T_7127 - node T_7890 = and(dmem_resp_valid, dmem_resp_fpu) - io.fpu.dmem_resp_val <= T_7890 + io.fpu.fromint_data <= T_6992 + node T_7746 = and(dmem_resp_valid, dmem_resp_fpu) + io.fpu.dmem_resp_val <= T_7746 io.fpu.dmem_resp_data <= io.dmem.resp.bits.data_word_bypass io.fpu.dmem_resp_type <= io.dmem.resp.bits.typ io.fpu.dmem_resp_tag <= dmem_resp_waddr - node T_7891 = and(ex_reg_valid, ex_ctrl.mem) - io.dmem.req.valid <= T_7891 - node T_7892 = or(killm_common, mem_xcpt) - io.dmem.req.bits.kill <= T_7892 + node T_7747 = and(ex_reg_valid, ex_ctrl.mem) + io.dmem.req.valid <= T_7747 + node T_7748 = or(killm_common, mem_xcpt) + io.dmem.req.bits.kill <= T_7748 io.dmem.req.bits.cmd <= ex_ctrl.mem_cmd io.dmem.req.bits.typ <= ex_ctrl.mem_type io.dmem.req.bits.phys <= UInt<1>("h00") - node T_7894 = shr(T_7127, 38) - node T_7895 = bits(alu.io.adder_out, 39, 38) - node T_7897 = eq(T_7894, UInt<1>("h00")) - node T_7899 = eq(T_7894, UInt<1>("h01")) - node T_7900 = or(T_7897, T_7899) - node T_7902 = neq(T_7895, UInt<1>("h00")) - node T_7903 = asSInt(T_7894) - node T_7905 = eq(T_7903, asSInt(UInt<1>("h01"))) - node T_7906 = asSInt(T_7894) - node T_7908 = eq(T_7906, asSInt(UInt<2>("h02"))) - node T_7909 = or(T_7905, T_7908) - node T_7910 = asSInt(T_7895) - node T_7912 = eq(T_7910, asSInt(UInt<1>("h01"))) - node T_7913 = bit(T_7895, 0) - node T_7914 = mux(T_7909, T_7912, T_7913) - node T_7915 = mux(T_7900, T_7902, T_7914) - node T_7916 = bits(alu.io.adder_out, 38, 0) - node T_7917 = cat(T_7915, T_7916) - io.dmem.req.bits.addr <= T_7917 - node T_7918 = cat(ex_waddr, ex_ctrl.fp) - io.dmem.req.bits.tag <= T_7918 - node T_7919 = mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2) - io.dmem.req.bits.data <= T_7919 + node T_7750 = shr(T_6992, 38) + node T_7751 = bits(alu.io.adder_out, 39, 38) + node T_7753 = eq(T_7750, UInt<1>("h00")) + node T_7755 = eq(T_7750, UInt<1>("h01")) + node T_7756 = or(T_7753, T_7755) + node T_7758 = neq(T_7751, UInt<1>("h00")) + node T_7759 = asSInt(T_7750) + node T_7761 = eq(T_7759, asSInt(UInt<1>("h01"))) + node T_7762 = asSInt(T_7750) + node T_7764 = eq(T_7762, asSInt(UInt<2>("h02"))) + node T_7765 = or(T_7761, T_7764) + node T_7766 = asSInt(T_7751) + node T_7768 = eq(T_7766, asSInt(UInt<1>("h01"))) + node T_7769 = bits(T_7751, 0, 0) + node T_7770 = mux(T_7765, T_7768, T_7769) + node T_7771 = mux(T_7756, T_7758, T_7770) + node T_7772 = bits(alu.io.adder_out, 38, 0) + node T_7773 = cat(T_7771, T_7772) + io.dmem.req.bits.addr <= T_7773 + node T_7774 = cat(ex_waddr, ex_ctrl.fp) + io.dmem.req.bits.tag <= T_7774 + node T_7775 = mux(mem_ctrl.fp, io.fpu.store_data, mem_reg_rs2) + io.dmem.req.bits.data <= T_7775 io.dmem.invalidate_lr <= wb_xcpt io.rocc.cmd.valid <= wb_rocc_val - node T_7921 = neq(csr.io.status.xs, UInt<1>("h00")) - node T_7922 = and(wb_xcpt, T_7921) - io.rocc.exception <= T_7922 - node T_7924 = neq(csr.io.status.prv, UInt<1>("h00")) - io.rocc.s <= T_7924 - wire T_7943 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} - T_7943.opcode <= UInt<1>("h00") - T_7943.rd <= UInt<1>("h00") - T_7943.xs2 <= UInt<1>("h00") - T_7943.xs1 <= UInt<1>("h00") - T_7943.xd <= UInt<1>("h00") - T_7943.rs1 <= UInt<1>("h00") - T_7943.rs2 <= UInt<1>("h00") - T_7943.funct <= UInt<1>("h00") - node T_7960 = bits(wb_reg_inst, 6, 0) - T_7943.opcode <= T_7960 - node T_7961 = bits(wb_reg_inst, 11, 7) - T_7943.rd <= T_7961 - node T_7962 = bits(wb_reg_inst, 12, 12) - T_7943.xs2 <= T_7962 - node T_7963 = bits(wb_reg_inst, 13, 13) - T_7943.xs1 <= T_7963 - node T_7964 = bits(wb_reg_inst, 14, 14) - T_7943.xd <= T_7964 - node T_7965 = bits(wb_reg_inst, 19, 15) - T_7943.rs1 <= T_7965 - node T_7966 = bits(wb_reg_inst, 24, 20) - T_7943.rs2 <= T_7966 - node T_7967 = bits(wb_reg_inst, 31, 25) - T_7943.funct <= T_7967 - io.rocc.cmd.bits.inst <- T_7943 + node T_7777 = neq(csr.io.status.xs, UInt<1>("h00")) + node T_7778 = and(wb_xcpt, T_7777) + io.rocc.exception <= T_7778 + node T_7780 = neq(csr.io.status.prv, UInt<1>("h00")) + io.rocc.s <= T_7780 + wire T_7799 : {funct : UInt<7>, rs2 : UInt<5>, rs1 : UInt<5>, xd : UInt<1>, xs1 : UInt<1>, xs2 : UInt<1>, rd : UInt<5>, opcode : UInt<7>} + T_7799 is invalid + node T_7808 = bits(wb_reg_inst, 6, 0) + T_7799.opcode <= T_7808 + node T_7809 = bits(wb_reg_inst, 11, 7) + T_7799.rd <= T_7809 + node T_7810 = bits(wb_reg_inst, 12, 12) + T_7799.xs2 <= T_7810 + node T_7811 = bits(wb_reg_inst, 13, 13) + T_7799.xs1 <= T_7811 + node T_7812 = bits(wb_reg_inst, 14, 14) + T_7799.xd <= T_7812 + node T_7813 = bits(wb_reg_inst, 19, 15) + T_7799.rs1 <= T_7813 + node T_7814 = bits(wb_reg_inst, 24, 20) + T_7799.rs2 <= T_7814 + node T_7815 = bits(wb_reg_inst, 31, 25) + T_7799.funct <= T_7815 + io.rocc.cmd.bits.inst <- T_7799 io.rocc.cmd.bits.rs1 <= wb_reg_wdata io.rocc.cmd.bits.rs2 <= wb_reg_rs2 - node T_7968 = bits(csr.io.time, 32, 0) - node T_7970 = mux(rf_wen, rf_waddr, UInt<1>("h00")) - node T_7971 = bits(wb_reg_inst, 19, 15) - reg T_7972 : UInt<?>, clk, UInt<1>("h00"), T_7972 - T_7972 <= T_7127 - reg T_7973 : UInt<?>, clk, UInt<1>("h00"), T_7973 - T_7973 <= T_7972 - node T_7974 = bits(wb_reg_inst, 24, 20) - reg T_7975 : UInt<?>, clk, UInt<1>("h00"), T_7975 - T_7975 <= T_7130 - reg T_7976 : UInt<?>, clk, UInt<1>("h00"), T_7976 - T_7976 <= T_7975 - node T_7978 = eq(reset, UInt<1>("h00")) - when T_7978 : + node T_7816 = bits(csr.io.time, 32, 0) + node T_7818 = mux(rf_wen, rf_waddr, UInt<1>("h00")) + node T_7819 = bits(wb_reg_inst, 19, 15) + reg T_7820 : UInt<?>, clk + T_7820 <= T_6992 + reg T_7821 : UInt<?>, clk + T_7821 <= T_7820 + node T_7822 = bits(wb_reg_inst, 24, 20) + reg T_7823 : UInt<?>, clk + T_7823 <= T_6995 + reg T_7824 : UInt<?>, clk + T_7824 <= T_7823 + node T_7826 = eq(reset, UInt<1>("h00")) + when T_7826 : printf(clk, UInt<1>(1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x) -", io.host.id, T_7968, wb_valid, wb_reg_pc, T_7970, rf_wdata, rf_wen, T_7971, T_7973, T_7974, T_7976, wb_reg_inst, wb_reg_inst) +", io.host.id, T_7816, wb_valid, wb_reg_pc, T_7818, rf_wdata, rf_wen, T_7819, T_7821, T_7822, T_7824, wb_reg_inst, wb_reg_inst) skip module BTB : @@ -24603,21 +17913,14 @@ circuit Top : input reset : UInt<1> output io : {flip req : {valid : UInt<1>, bits : {addr : UInt<39>}}, resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, flip btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, flip bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, flip ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, flip invalidate : UInt<1>} - io.resp.bits.bht.value <= UInt<1>("h00") - io.resp.bits.bht.history <= UInt<1>("h00") - io.resp.bits.entry <= UInt<1>("h00") - io.resp.bits.target <= UInt<1>("h00") - io.resp.bits.bridx <= UInt<1>("h00") - io.resp.bits.mask <= UInt<1>("h00") - io.resp.bits.taken <= UInt<1>("h00") - io.resp.valid <= UInt<1>("h00") - reg idxValid : UInt<62>, clk, reset, UInt<62>("h00") + io is invalid + reg idxValid : UInt<62>, clk with : (reset => (reset, UInt<62>("h00"))) cmem idxs : UInt<12>[62] cmem idxPages : UInt<3>[62] cmem tgts : UInt<12>[62] cmem tgtPages : UInt<3>[62] cmem pages : UInt<27>[6] - reg pageValid : UInt<6>, clk, reset, UInt<6>("h00") + reg pageValid : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) infer mport T_590 = idxPages[UInt<1>("h00")], clk node T_592 = dshl(UInt<1>("h01"), T_590) node T_593 = bits(T_592, 5, 0) @@ -24990,2654 +18293,2645 @@ circuit Top : infer mport T_1205 = tgtPages[UInt<6>("h03d")], clk node T_1207 = dshl(UInt<1>("h01"), T_1205) node T_1208 = bits(T_1207, 5, 0) - reg useRAS : UInt<1>[62], clk, UInt<1>("h00"), useRAS - reg isJump : UInt<1>[62], clk, UInt<1>("h00"), isJump + reg useRAS : UInt<1>[62], clk + reg isJump : UInt<1>[62], clk cmem brIdx : UInt<1>[62] - reg T_1478 : UInt<1>, clk, reset, UInt<1>("h00") + reg T_1478 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) T_1478 <= io.btb_update.valid - reg T_1479 : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}, clk, UInt<1>("h00"), T_1479 + reg T_1479 : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}, clk when io.btb_update.valid : T_1479 <- io.btb_update.bits skip wire r_btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}} - r_btb_update.bits.br_pc <= UInt<1>("h00") - r_btb_update.bits.isReturn <= UInt<1>("h00") - r_btb_update.bits.isJump <= UInt<1>("h00") - r_btb_update.bits.taken <= UInt<1>("h00") - r_btb_update.bits.target <= UInt<1>("h00") - r_btb_update.bits.pc <= UInt<1>("h00") - r_btb_update.bits.prediction.bits.bht.value <= UInt<1>("h00") - r_btb_update.bits.prediction.bits.bht.history <= UInt<1>("h00") - r_btb_update.bits.prediction.bits.entry <= UInt<1>("h00") - r_btb_update.bits.prediction.bits.target <= UInt<1>("h00") - r_btb_update.bits.prediction.bits.bridx <= UInt<1>("h00") - r_btb_update.bits.prediction.bits.mask <= UInt<1>("h00") - r_btb_update.bits.prediction.bits.taken <= UInt<1>("h00") - r_btb_update.bits.prediction.valid <= UInt<1>("h00") - r_btb_update.valid <= UInt<1>("h00") + r_btb_update is invalid r_btb_update.valid <= T_1478 r_btb_update.bits <- T_1479 - node T_1678 = shr(io.req.bits.addr, 12) - infer mport T_1680 = pages[UInt<1>("h00")], clk - node T_1681 = eq(T_1680, T_1678) - infer mport T_1683 = pages[UInt<1>("h01")], clk - node T_1684 = eq(T_1683, T_1678) - infer mport T_1686 = pages[UInt<2>("h02")], clk - node T_1687 = eq(T_1686, T_1678) - infer mport T_1689 = pages[UInt<2>("h03")], clk - node T_1690 = eq(T_1689, T_1678) - infer mport T_1692 = pages[UInt<3>("h04")], clk - node T_1693 = eq(T_1692, T_1678) - infer mport T_1695 = pages[UInt<3>("h05")], clk - node T_1696 = eq(T_1695, T_1678) - wire T_1698 : UInt<1>[6] - T_1698[0] <= T_1681 - T_1698[1] <= T_1684 - T_1698[2] <= T_1687 - T_1698[3] <= T_1690 - T_1698[4] <= T_1693 - T_1698[5] <= T_1696 - node T_1706 = cat(T_1698[4], T_1698[3]) - node T_1707 = cat(T_1698[5], T_1706) - node T_1708 = cat(T_1698[1], T_1698[0]) - node T_1709 = cat(T_1698[2], T_1708) - node T_1710 = cat(T_1707, T_1709) - node pageHit = and(T_1710, pageValid) - node T_1712 = bits(io.req.bits.addr, 11, 0) - infer mport T_1714 = idxs[UInt<1>("h00")], clk - node T_1715 = eq(T_1714, T_1712) - infer mport T_1717 = idxs[UInt<1>("h01")], clk - node T_1718 = eq(T_1717, T_1712) - infer mport T_1720 = idxs[UInt<2>("h02")], clk - node T_1721 = eq(T_1720, T_1712) - infer mport T_1723 = idxs[UInt<2>("h03")], clk - node T_1724 = eq(T_1723, T_1712) - infer mport T_1726 = idxs[UInt<3>("h04")], clk - node T_1727 = eq(T_1726, T_1712) - infer mport T_1729 = idxs[UInt<3>("h05")], clk - node T_1730 = eq(T_1729, T_1712) - infer mport T_1732 = idxs[UInt<3>("h06")], clk - node T_1733 = eq(T_1732, T_1712) - infer mport T_1735 = idxs[UInt<3>("h07")], clk - node T_1736 = eq(T_1735, T_1712) - infer mport T_1738 = idxs[UInt<4>("h08")], clk - node T_1739 = eq(T_1738, T_1712) - infer mport T_1741 = idxs[UInt<4>("h09")], clk - node T_1742 = eq(T_1741, T_1712) - infer mport T_1744 = idxs[UInt<4>("h0a")], clk - node T_1745 = eq(T_1744, T_1712) - infer mport T_1747 = idxs[UInt<4>("h0b")], clk - node T_1748 = eq(T_1747, T_1712) - infer mport T_1750 = idxs[UInt<4>("h0c")], clk - node T_1751 = eq(T_1750, T_1712) - infer mport T_1753 = idxs[UInt<4>("h0d")], clk - node T_1754 = eq(T_1753, T_1712) - infer mport T_1756 = idxs[UInt<4>("h0e")], clk - node T_1757 = eq(T_1756, T_1712) - infer mport T_1759 = idxs[UInt<4>("h0f")], clk - node T_1760 = eq(T_1759, T_1712) - infer mport T_1762 = idxs[UInt<5>("h010")], clk - node T_1763 = eq(T_1762, T_1712) - infer mport T_1765 = idxs[UInt<5>("h011")], clk - node T_1766 = eq(T_1765, T_1712) - infer mport T_1768 = idxs[UInt<5>("h012")], clk - node T_1769 = eq(T_1768, T_1712) - infer mport T_1771 = idxs[UInt<5>("h013")], clk - node T_1772 = eq(T_1771, T_1712) - infer mport T_1774 = idxs[UInt<5>("h014")], clk - node T_1775 = eq(T_1774, T_1712) - infer mport T_1777 = idxs[UInt<5>("h015")], clk - node T_1778 = eq(T_1777, T_1712) - infer mport T_1780 = idxs[UInt<5>("h016")], clk - node T_1781 = eq(T_1780, T_1712) - infer mport T_1783 = idxs[UInt<5>("h017")], clk - node T_1784 = eq(T_1783, T_1712) - infer mport T_1786 = idxs[UInt<5>("h018")], clk - node T_1787 = eq(T_1786, T_1712) - infer mport T_1789 = idxs[UInt<5>("h019")], clk - node T_1790 = eq(T_1789, T_1712) - infer mport T_1792 = idxs[UInt<5>("h01a")], clk - node T_1793 = eq(T_1792, T_1712) - infer mport T_1795 = idxs[UInt<5>("h01b")], clk - node T_1796 = eq(T_1795, T_1712) - infer mport T_1798 = idxs[UInt<5>("h01c")], clk - node T_1799 = eq(T_1798, T_1712) - infer mport T_1801 = idxs[UInt<5>("h01d")], clk - node T_1802 = eq(T_1801, T_1712) - infer mport T_1804 = idxs[UInt<5>("h01e")], clk - node T_1805 = eq(T_1804, T_1712) - infer mport T_1807 = idxs[UInt<5>("h01f")], clk - node T_1808 = eq(T_1807, T_1712) - infer mport T_1810 = idxs[UInt<6>("h020")], clk - node T_1811 = eq(T_1810, T_1712) - infer mport T_1813 = idxs[UInt<6>("h021")], clk - node T_1814 = eq(T_1813, T_1712) - infer mport T_1816 = idxs[UInt<6>("h022")], clk - node T_1817 = eq(T_1816, T_1712) - infer mport T_1819 = idxs[UInt<6>("h023")], clk - node T_1820 = eq(T_1819, T_1712) - infer mport T_1822 = idxs[UInt<6>("h024")], clk - node T_1823 = eq(T_1822, T_1712) - infer mport T_1825 = idxs[UInt<6>("h025")], clk - node T_1826 = eq(T_1825, T_1712) - infer mport T_1828 = idxs[UInt<6>("h026")], clk - node T_1829 = eq(T_1828, T_1712) - infer mport T_1831 = idxs[UInt<6>("h027")], clk - node T_1832 = eq(T_1831, T_1712) - infer mport T_1834 = idxs[UInt<6>("h028")], clk - node T_1835 = eq(T_1834, T_1712) - infer mport T_1837 = idxs[UInt<6>("h029")], clk - node T_1838 = eq(T_1837, T_1712) - infer mport T_1840 = idxs[UInt<6>("h02a")], clk - node T_1841 = eq(T_1840, T_1712) - infer mport T_1843 = idxs[UInt<6>("h02b")], clk - node T_1844 = eq(T_1843, T_1712) - infer mport T_1846 = idxs[UInt<6>("h02c")], clk - node T_1847 = eq(T_1846, T_1712) - infer mport T_1849 = idxs[UInt<6>("h02d")], clk - node T_1850 = eq(T_1849, T_1712) - infer mport T_1852 = idxs[UInt<6>("h02e")], clk - node T_1853 = eq(T_1852, T_1712) - infer mport T_1855 = idxs[UInt<6>("h02f")], clk - node T_1856 = eq(T_1855, T_1712) - infer mport T_1858 = idxs[UInt<6>("h030")], clk - node T_1859 = eq(T_1858, T_1712) - infer mport T_1861 = idxs[UInt<6>("h031")], clk - node T_1862 = eq(T_1861, T_1712) - infer mport T_1864 = idxs[UInt<6>("h032")], clk - node T_1865 = eq(T_1864, T_1712) - infer mport T_1867 = idxs[UInt<6>("h033")], clk - node T_1868 = eq(T_1867, T_1712) - infer mport T_1870 = idxs[UInt<6>("h034")], clk - node T_1871 = eq(T_1870, T_1712) - infer mport T_1873 = idxs[UInt<6>("h035")], clk - node T_1874 = eq(T_1873, T_1712) - infer mport T_1876 = idxs[UInt<6>("h036")], clk - node T_1877 = eq(T_1876, T_1712) - infer mport T_1879 = idxs[UInt<6>("h037")], clk - node T_1880 = eq(T_1879, T_1712) - infer mport T_1882 = idxs[UInt<6>("h038")], clk - node T_1883 = eq(T_1882, T_1712) - infer mport T_1885 = idxs[UInt<6>("h039")], clk - node T_1886 = eq(T_1885, T_1712) - infer mport T_1888 = idxs[UInt<6>("h03a")], clk - node T_1889 = eq(T_1888, T_1712) - infer mport T_1891 = idxs[UInt<6>("h03b")], clk - node T_1892 = eq(T_1891, T_1712) - infer mport T_1894 = idxs[UInt<6>("h03c")], clk - node T_1895 = eq(T_1894, T_1712) - infer mport T_1897 = idxs[UInt<6>("h03d")], clk - node T_1898 = eq(T_1897, T_1712) - wire T_1900 : UInt<1>[62] - T_1900[0] <= T_1715 - T_1900[1] <= T_1718 - T_1900[2] <= T_1721 - T_1900[3] <= T_1724 - T_1900[4] <= T_1727 - T_1900[5] <= T_1730 - T_1900[6] <= T_1733 - T_1900[7] <= T_1736 - T_1900[8] <= T_1739 - T_1900[9] <= T_1742 - T_1900[10] <= T_1745 - T_1900[11] <= T_1748 - T_1900[12] <= T_1751 - T_1900[13] <= T_1754 - T_1900[14] <= T_1757 - T_1900[15] <= T_1760 - T_1900[16] <= T_1763 - T_1900[17] <= T_1766 - T_1900[18] <= T_1769 - T_1900[19] <= T_1772 - T_1900[20] <= T_1775 - T_1900[21] <= T_1778 - T_1900[22] <= T_1781 - T_1900[23] <= T_1784 - T_1900[24] <= T_1787 - T_1900[25] <= T_1790 - T_1900[26] <= T_1793 - T_1900[27] <= T_1796 - T_1900[28] <= T_1799 - T_1900[29] <= T_1802 - T_1900[30] <= T_1805 - T_1900[31] <= T_1808 - T_1900[32] <= T_1811 - T_1900[33] <= T_1814 - T_1900[34] <= T_1817 - T_1900[35] <= T_1820 - T_1900[36] <= T_1823 - T_1900[37] <= T_1826 - T_1900[38] <= T_1829 - T_1900[39] <= T_1832 - T_1900[40] <= T_1835 - T_1900[41] <= T_1838 - T_1900[42] <= T_1841 - T_1900[43] <= T_1844 - T_1900[44] <= T_1847 - T_1900[45] <= T_1850 - T_1900[46] <= T_1853 - T_1900[47] <= T_1856 - T_1900[48] <= T_1859 - T_1900[49] <= T_1862 - T_1900[50] <= T_1865 - T_1900[51] <= T_1868 - T_1900[52] <= T_1871 - T_1900[53] <= T_1874 - T_1900[54] <= T_1877 - T_1900[55] <= T_1880 - T_1900[56] <= T_1883 - T_1900[57] <= T_1886 - T_1900[58] <= T_1889 - T_1900[59] <= T_1892 - T_1900[60] <= T_1895 - T_1900[61] <= T_1898 - node T_1964 = cat(T_1900[60], T_1900[59]) - node T_1965 = cat(T_1900[61], T_1964) - node T_1966 = cat(T_1900[58], T_1900[57]) - node T_1967 = cat(T_1900[56], T_1900[55]) + node T_1663 = shr(io.req.bits.addr, 12) + infer mport T_1665 = pages[UInt<1>("h00")], clk + node T_1666 = eq(T_1665, T_1663) + infer mport T_1668 = pages[UInt<1>("h01")], clk + node T_1669 = eq(T_1668, T_1663) + infer mport T_1671 = pages[UInt<2>("h02")], clk + node T_1672 = eq(T_1671, T_1663) + infer mport T_1674 = pages[UInt<2>("h03")], clk + node T_1675 = eq(T_1674, T_1663) + infer mport T_1677 = pages[UInt<3>("h04")], clk + node T_1678 = eq(T_1677, T_1663) + infer mport T_1680 = pages[UInt<3>("h05")], clk + node T_1681 = eq(T_1680, T_1663) + wire T_1683 : UInt<1>[6] + T_1683[0] <= T_1666 + T_1683[1] <= T_1669 + T_1683[2] <= T_1672 + T_1683[3] <= T_1675 + T_1683[4] <= T_1678 + T_1683[5] <= T_1681 + node T_1691 = cat(T_1683[4], T_1683[3]) + node T_1692 = cat(T_1683[5], T_1691) + node T_1693 = cat(T_1683[1], T_1683[0]) + node T_1694 = cat(T_1683[2], T_1693) + node T_1695 = cat(T_1692, T_1694) + node pageHit = and(T_1695, pageValid) + node T_1697 = bits(io.req.bits.addr, 11, 0) + infer mport T_1699 = idxs[UInt<1>("h00")], clk + node T_1700 = eq(T_1699, T_1697) + infer mport T_1702 = idxs[UInt<1>("h01")], clk + node T_1703 = eq(T_1702, T_1697) + infer mport T_1705 = idxs[UInt<2>("h02")], clk + node T_1706 = eq(T_1705, T_1697) + infer mport T_1708 = idxs[UInt<2>("h03")], clk + node T_1709 = eq(T_1708, T_1697) + infer mport T_1711 = idxs[UInt<3>("h04")], clk + node T_1712 = eq(T_1711, T_1697) + infer mport T_1714 = idxs[UInt<3>("h05")], clk + node T_1715 = eq(T_1714, T_1697) + infer mport T_1717 = idxs[UInt<3>("h06")], clk + node T_1718 = eq(T_1717, T_1697) + infer mport T_1720 = idxs[UInt<3>("h07")], clk + node T_1721 = eq(T_1720, T_1697) + infer mport T_1723 = idxs[UInt<4>("h08")], clk + node T_1724 = eq(T_1723, T_1697) + infer mport T_1726 = idxs[UInt<4>("h09")], clk + node T_1727 = eq(T_1726, T_1697) + infer mport T_1729 = idxs[UInt<4>("h0a")], clk + node T_1730 = eq(T_1729, T_1697) + infer mport T_1732 = idxs[UInt<4>("h0b")], clk + node T_1733 = eq(T_1732, T_1697) + infer mport T_1735 = idxs[UInt<4>("h0c")], clk + node T_1736 = eq(T_1735, T_1697) + infer mport T_1738 = idxs[UInt<4>("h0d")], clk + node T_1739 = eq(T_1738, T_1697) + infer mport T_1741 = idxs[UInt<4>("h0e")], clk + node T_1742 = eq(T_1741, T_1697) + infer mport T_1744 = idxs[UInt<4>("h0f")], clk + node T_1745 = eq(T_1744, T_1697) + infer mport T_1747 = idxs[UInt<5>("h010")], clk + node T_1748 = eq(T_1747, T_1697) + infer mport T_1750 = idxs[UInt<5>("h011")], clk + node T_1751 = eq(T_1750, T_1697) + infer mport T_1753 = idxs[UInt<5>("h012")], clk + node T_1754 = eq(T_1753, T_1697) + infer mport T_1756 = idxs[UInt<5>("h013")], clk + node T_1757 = eq(T_1756, T_1697) + infer mport T_1759 = idxs[UInt<5>("h014")], clk + node T_1760 = eq(T_1759, T_1697) + infer mport T_1762 = idxs[UInt<5>("h015")], clk + node T_1763 = eq(T_1762, T_1697) + infer mport T_1765 = idxs[UInt<5>("h016")], clk + node T_1766 = eq(T_1765, T_1697) + infer mport T_1768 = idxs[UInt<5>("h017")], clk + node T_1769 = eq(T_1768, T_1697) + infer mport T_1771 = idxs[UInt<5>("h018")], clk + node T_1772 = eq(T_1771, T_1697) + infer mport T_1774 = idxs[UInt<5>("h019")], clk + node T_1775 = eq(T_1774, T_1697) + infer mport T_1777 = idxs[UInt<5>("h01a")], clk + node T_1778 = eq(T_1777, T_1697) + infer mport T_1780 = idxs[UInt<5>("h01b")], clk + node T_1781 = eq(T_1780, T_1697) + infer mport T_1783 = idxs[UInt<5>("h01c")], clk + node T_1784 = eq(T_1783, T_1697) + infer mport T_1786 = idxs[UInt<5>("h01d")], clk + node T_1787 = eq(T_1786, T_1697) + infer mport T_1789 = idxs[UInt<5>("h01e")], clk + node T_1790 = eq(T_1789, T_1697) + infer mport T_1792 = idxs[UInt<5>("h01f")], clk + node T_1793 = eq(T_1792, T_1697) + infer mport T_1795 = idxs[UInt<6>("h020")], clk + node T_1796 = eq(T_1795, T_1697) + infer mport T_1798 = idxs[UInt<6>("h021")], clk + node T_1799 = eq(T_1798, T_1697) + infer mport T_1801 = idxs[UInt<6>("h022")], clk + node T_1802 = eq(T_1801, T_1697) + infer mport T_1804 = idxs[UInt<6>("h023")], clk + node T_1805 = eq(T_1804, T_1697) + infer mport T_1807 = idxs[UInt<6>("h024")], clk + node T_1808 = eq(T_1807, T_1697) + infer mport T_1810 = idxs[UInt<6>("h025")], clk + node T_1811 = eq(T_1810, T_1697) + infer mport T_1813 = idxs[UInt<6>("h026")], clk + node T_1814 = eq(T_1813, T_1697) + infer mport T_1816 = idxs[UInt<6>("h027")], clk + node T_1817 = eq(T_1816, T_1697) + infer mport T_1819 = idxs[UInt<6>("h028")], clk + node T_1820 = eq(T_1819, T_1697) + infer mport T_1822 = idxs[UInt<6>("h029")], clk + node T_1823 = eq(T_1822, T_1697) + infer mport T_1825 = idxs[UInt<6>("h02a")], clk + node T_1826 = eq(T_1825, T_1697) + infer mport T_1828 = idxs[UInt<6>("h02b")], clk + node T_1829 = eq(T_1828, T_1697) + infer mport T_1831 = idxs[UInt<6>("h02c")], clk + node T_1832 = eq(T_1831, T_1697) + infer mport T_1834 = idxs[UInt<6>("h02d")], clk + node T_1835 = eq(T_1834, T_1697) + infer mport T_1837 = idxs[UInt<6>("h02e")], clk + node T_1838 = eq(T_1837, T_1697) + infer mport T_1840 = idxs[UInt<6>("h02f")], clk + node T_1841 = eq(T_1840, T_1697) + infer mport T_1843 = idxs[UInt<6>("h030")], clk + node T_1844 = eq(T_1843, T_1697) + infer mport T_1846 = idxs[UInt<6>("h031")], clk + node T_1847 = eq(T_1846, T_1697) + infer mport T_1849 = idxs[UInt<6>("h032")], clk + node T_1850 = eq(T_1849, T_1697) + infer mport T_1852 = idxs[UInt<6>("h033")], clk + node T_1853 = eq(T_1852, T_1697) + infer mport T_1855 = idxs[UInt<6>("h034")], clk + node T_1856 = eq(T_1855, T_1697) + infer mport T_1858 = idxs[UInt<6>("h035")], clk + node T_1859 = eq(T_1858, T_1697) + infer mport T_1861 = idxs[UInt<6>("h036")], clk + node T_1862 = eq(T_1861, T_1697) + infer mport T_1864 = idxs[UInt<6>("h037")], clk + node T_1865 = eq(T_1864, T_1697) + infer mport T_1867 = idxs[UInt<6>("h038")], clk + node T_1868 = eq(T_1867, T_1697) + infer mport T_1870 = idxs[UInt<6>("h039")], clk + node T_1871 = eq(T_1870, T_1697) + infer mport T_1873 = idxs[UInt<6>("h03a")], clk + node T_1874 = eq(T_1873, T_1697) + infer mport T_1876 = idxs[UInt<6>("h03b")], clk + node T_1877 = eq(T_1876, T_1697) + infer mport T_1879 = idxs[UInt<6>("h03c")], clk + node T_1880 = eq(T_1879, T_1697) + infer mport T_1882 = idxs[UInt<6>("h03d")], clk + node T_1883 = eq(T_1882, T_1697) + wire T_1885 : UInt<1>[62] + T_1885[0] <= T_1700 + T_1885[1] <= T_1703 + T_1885[2] <= T_1706 + T_1885[3] <= T_1709 + T_1885[4] <= T_1712 + T_1885[5] <= T_1715 + T_1885[6] <= T_1718 + T_1885[7] <= T_1721 + T_1885[8] <= T_1724 + T_1885[9] <= T_1727 + T_1885[10] <= T_1730 + T_1885[11] <= T_1733 + T_1885[12] <= T_1736 + T_1885[13] <= T_1739 + T_1885[14] <= T_1742 + T_1885[15] <= T_1745 + T_1885[16] <= T_1748 + T_1885[17] <= T_1751 + T_1885[18] <= T_1754 + T_1885[19] <= T_1757 + T_1885[20] <= T_1760 + T_1885[21] <= T_1763 + T_1885[22] <= T_1766 + T_1885[23] <= T_1769 + T_1885[24] <= T_1772 + T_1885[25] <= T_1775 + T_1885[26] <= T_1778 + T_1885[27] <= T_1781 + T_1885[28] <= T_1784 + T_1885[29] <= T_1787 + T_1885[30] <= T_1790 + T_1885[31] <= T_1793 + T_1885[32] <= T_1796 + T_1885[33] <= T_1799 + T_1885[34] <= T_1802 + T_1885[35] <= T_1805 + T_1885[36] <= T_1808 + T_1885[37] <= T_1811 + T_1885[38] <= T_1814 + T_1885[39] <= T_1817 + T_1885[40] <= T_1820 + T_1885[41] <= T_1823 + T_1885[42] <= T_1826 + T_1885[43] <= T_1829 + T_1885[44] <= T_1832 + T_1885[45] <= T_1835 + T_1885[46] <= T_1838 + T_1885[47] <= T_1841 + T_1885[48] <= T_1844 + T_1885[49] <= T_1847 + T_1885[50] <= T_1850 + T_1885[51] <= T_1853 + T_1885[52] <= T_1856 + T_1885[53] <= T_1859 + T_1885[54] <= T_1862 + T_1885[55] <= T_1865 + T_1885[56] <= T_1868 + T_1885[57] <= T_1871 + T_1885[58] <= T_1874 + T_1885[59] <= T_1877 + T_1885[60] <= T_1880 + T_1885[61] <= T_1883 + node T_1949 = cat(T_1885[60], T_1885[59]) + node T_1950 = cat(T_1885[61], T_1949) + node T_1951 = cat(T_1885[58], T_1885[57]) + node T_1952 = cat(T_1885[56], T_1885[55]) + node T_1953 = cat(T_1951, T_1952) + node T_1954 = cat(T_1950, T_1953) + node T_1955 = cat(T_1885[54], T_1885[53]) + node T_1956 = cat(T_1885[52], T_1885[51]) + node T_1957 = cat(T_1955, T_1956) + node T_1958 = cat(T_1885[50], T_1885[49]) + node T_1959 = cat(T_1885[48], T_1885[47]) + node T_1960 = cat(T_1958, T_1959) + node T_1961 = cat(T_1957, T_1960) + node T_1962 = cat(T_1954, T_1961) + node T_1963 = cat(T_1885[46], T_1885[45]) + node T_1964 = cat(T_1885[44], T_1885[43]) + node T_1965 = cat(T_1963, T_1964) + node T_1966 = cat(T_1885[42], T_1885[41]) + node T_1967 = cat(T_1885[40], T_1885[39]) node T_1968 = cat(T_1966, T_1967) node T_1969 = cat(T_1965, T_1968) - node T_1970 = cat(T_1900[54], T_1900[53]) - node T_1971 = cat(T_1900[52], T_1900[51]) + node T_1970 = cat(T_1885[38], T_1885[37]) + node T_1971 = cat(T_1885[36], T_1885[35]) node T_1972 = cat(T_1970, T_1971) - node T_1973 = cat(T_1900[50], T_1900[49]) - node T_1974 = cat(T_1900[48], T_1900[47]) + node T_1973 = cat(T_1885[34], T_1885[33]) + node T_1974 = cat(T_1885[32], T_1885[31]) node T_1975 = cat(T_1973, T_1974) node T_1976 = cat(T_1972, T_1975) node T_1977 = cat(T_1969, T_1976) - node T_1978 = cat(T_1900[46], T_1900[45]) - node T_1979 = cat(T_1900[44], T_1900[43]) - node T_1980 = cat(T_1978, T_1979) - node T_1981 = cat(T_1900[42], T_1900[41]) - node T_1982 = cat(T_1900[40], T_1900[39]) + node T_1978 = cat(T_1962, T_1977) + node T_1979 = cat(T_1885[29], T_1885[28]) + node T_1980 = cat(T_1885[30], T_1979) + node T_1981 = cat(T_1885[27], T_1885[26]) + node T_1982 = cat(T_1885[25], T_1885[24]) node T_1983 = cat(T_1981, T_1982) node T_1984 = cat(T_1980, T_1983) - node T_1985 = cat(T_1900[38], T_1900[37]) - node T_1986 = cat(T_1900[36], T_1900[35]) + node T_1985 = cat(T_1885[23], T_1885[22]) + node T_1986 = cat(T_1885[21], T_1885[20]) node T_1987 = cat(T_1985, T_1986) - node T_1988 = cat(T_1900[34], T_1900[33]) - node T_1989 = cat(T_1900[32], T_1900[31]) + node T_1988 = cat(T_1885[19], T_1885[18]) + node T_1989 = cat(T_1885[17], T_1885[16]) node T_1990 = cat(T_1988, T_1989) node T_1991 = cat(T_1987, T_1990) node T_1992 = cat(T_1984, T_1991) - node T_1993 = cat(T_1977, T_1992) - node T_1994 = cat(T_1900[29], T_1900[28]) - node T_1995 = cat(T_1900[30], T_1994) - node T_1996 = cat(T_1900[27], T_1900[26]) - node T_1997 = cat(T_1900[25], T_1900[24]) + node T_1993 = cat(T_1885[15], T_1885[14]) + node T_1994 = cat(T_1885[13], T_1885[12]) + node T_1995 = cat(T_1993, T_1994) + node T_1996 = cat(T_1885[11], T_1885[10]) + node T_1997 = cat(T_1885[9], T_1885[8]) node T_1998 = cat(T_1996, T_1997) node T_1999 = cat(T_1995, T_1998) - node T_2000 = cat(T_1900[23], T_1900[22]) - node T_2001 = cat(T_1900[21], T_1900[20]) + node T_2000 = cat(T_1885[7], T_1885[6]) + node T_2001 = cat(T_1885[5], T_1885[4]) node T_2002 = cat(T_2000, T_2001) - node T_2003 = cat(T_1900[19], T_1900[18]) - node T_2004 = cat(T_1900[17], T_1900[16]) + node T_2003 = cat(T_1885[3], T_1885[2]) + node T_2004 = cat(T_1885[1], T_1885[0]) node T_2005 = cat(T_2003, T_2004) node T_2006 = cat(T_2002, T_2005) node T_2007 = cat(T_1999, T_2006) - node T_2008 = cat(T_1900[15], T_1900[14]) - node T_2009 = cat(T_1900[13], T_1900[12]) - node T_2010 = cat(T_2008, T_2009) - node T_2011 = cat(T_1900[11], T_1900[10]) - node T_2012 = cat(T_1900[9], T_1900[8]) - node T_2013 = cat(T_2011, T_2012) - node T_2014 = cat(T_2010, T_2013) - node T_2015 = cat(T_1900[7], T_1900[6]) - node T_2016 = cat(T_1900[5], T_1900[4]) - node T_2017 = cat(T_2015, T_2016) - node T_2018 = cat(T_1900[3], T_1900[2]) - node T_2019 = cat(T_1900[1], T_1900[0]) - node T_2020 = cat(T_2018, T_2019) - node T_2021 = cat(T_2017, T_2020) - node T_2022 = cat(T_2014, T_2021) - node T_2023 = cat(T_2007, T_2022) - node T_2024 = cat(T_1993, T_2023) - node T_2025 = and(T_593, pageHit) - node T_2026 = and(T_598, pageHit) - node T_2027 = and(T_603, pageHit) - node T_2028 = and(T_608, pageHit) - node T_2029 = and(T_613, pageHit) - node T_2030 = and(T_618, pageHit) - node T_2031 = and(T_623, pageHit) - node T_2032 = and(T_628, pageHit) - node T_2033 = and(T_633, pageHit) - node T_2034 = and(T_638, pageHit) - node T_2035 = and(T_643, pageHit) - node T_2036 = and(T_648, pageHit) - node T_2037 = and(T_653, pageHit) - node T_2038 = and(T_658, pageHit) - node T_2039 = and(T_663, pageHit) - node T_2040 = and(T_668, pageHit) - node T_2041 = and(T_673, pageHit) - node T_2042 = and(T_678, pageHit) - node T_2043 = and(T_683, pageHit) - node T_2044 = and(T_688, pageHit) - node T_2045 = and(T_693, pageHit) - node T_2046 = and(T_698, pageHit) - node T_2047 = and(T_703, pageHit) - node T_2048 = and(T_708, pageHit) - node T_2049 = and(T_713, pageHit) - node T_2050 = and(T_718, pageHit) - node T_2051 = and(T_723, pageHit) - node T_2052 = and(T_728, pageHit) - node T_2053 = and(T_733, pageHit) - node T_2054 = and(T_738, pageHit) - node T_2055 = and(T_743, pageHit) - node T_2056 = and(T_748, pageHit) - node T_2057 = and(T_753, pageHit) - node T_2058 = and(T_758, pageHit) - node T_2059 = and(T_763, pageHit) - node T_2060 = and(T_768, pageHit) - node T_2061 = and(T_773, pageHit) - node T_2062 = and(T_778, pageHit) - node T_2063 = and(T_783, pageHit) - node T_2064 = and(T_788, pageHit) - node T_2065 = and(T_793, pageHit) - node T_2066 = and(T_798, pageHit) - node T_2067 = and(T_803, pageHit) - node T_2068 = and(T_808, pageHit) - node T_2069 = and(T_813, pageHit) - node T_2070 = and(T_818, pageHit) - node T_2071 = and(T_823, pageHit) - node T_2072 = and(T_828, pageHit) - node T_2073 = and(T_833, pageHit) - node T_2074 = and(T_838, pageHit) - node T_2075 = and(T_843, pageHit) - node T_2076 = and(T_848, pageHit) - node T_2077 = and(T_853, pageHit) - node T_2078 = and(T_858, pageHit) - node T_2079 = and(T_863, pageHit) - node T_2080 = and(T_868, pageHit) - node T_2081 = and(T_873, pageHit) - node T_2082 = and(T_878, pageHit) - node T_2083 = and(T_883, pageHit) - node T_2084 = and(T_888, pageHit) - node T_2085 = and(T_893, pageHit) - node T_2086 = and(T_898, pageHit) - node T_2088 = neq(T_2025, UInt<1>("h00")) - node T_2090 = neq(T_2026, UInt<1>("h00")) - node T_2092 = neq(T_2027, UInt<1>("h00")) - node T_2094 = neq(T_2028, UInt<1>("h00")) - node T_2096 = neq(T_2029, UInt<1>("h00")) - node T_2098 = neq(T_2030, UInt<1>("h00")) - node T_2100 = neq(T_2031, UInt<1>("h00")) - node T_2102 = neq(T_2032, UInt<1>("h00")) - node T_2104 = neq(T_2033, UInt<1>("h00")) - node T_2106 = neq(T_2034, UInt<1>("h00")) - node T_2108 = neq(T_2035, UInt<1>("h00")) - node T_2110 = neq(T_2036, UInt<1>("h00")) - node T_2112 = neq(T_2037, UInt<1>("h00")) - node T_2114 = neq(T_2038, UInt<1>("h00")) - node T_2116 = neq(T_2039, UInt<1>("h00")) - node T_2118 = neq(T_2040, UInt<1>("h00")) - node T_2120 = neq(T_2041, UInt<1>("h00")) - node T_2122 = neq(T_2042, UInt<1>("h00")) - node T_2124 = neq(T_2043, UInt<1>("h00")) - node T_2126 = neq(T_2044, UInt<1>("h00")) - node T_2128 = neq(T_2045, UInt<1>("h00")) - node T_2130 = neq(T_2046, UInt<1>("h00")) - node T_2132 = neq(T_2047, UInt<1>("h00")) - node T_2134 = neq(T_2048, UInt<1>("h00")) - node T_2136 = neq(T_2049, UInt<1>("h00")) - node T_2138 = neq(T_2050, UInt<1>("h00")) - node T_2140 = neq(T_2051, UInt<1>("h00")) - node T_2142 = neq(T_2052, UInt<1>("h00")) - node T_2144 = neq(T_2053, UInt<1>("h00")) - node T_2146 = neq(T_2054, UInt<1>("h00")) - node T_2148 = neq(T_2055, UInt<1>("h00")) - node T_2150 = neq(T_2056, UInt<1>("h00")) - node T_2152 = neq(T_2057, UInt<1>("h00")) - node T_2154 = neq(T_2058, UInt<1>("h00")) - node T_2156 = neq(T_2059, UInt<1>("h00")) - node T_2158 = neq(T_2060, UInt<1>("h00")) - node T_2160 = neq(T_2061, UInt<1>("h00")) - node T_2162 = neq(T_2062, UInt<1>("h00")) - node T_2164 = neq(T_2063, UInt<1>("h00")) - node T_2166 = neq(T_2064, UInt<1>("h00")) - node T_2168 = neq(T_2065, UInt<1>("h00")) - node T_2170 = neq(T_2066, UInt<1>("h00")) - node T_2172 = neq(T_2067, UInt<1>("h00")) - node T_2174 = neq(T_2068, UInt<1>("h00")) - node T_2176 = neq(T_2069, UInt<1>("h00")) - node T_2178 = neq(T_2070, UInt<1>("h00")) - node T_2180 = neq(T_2071, UInt<1>("h00")) - node T_2182 = neq(T_2072, UInt<1>("h00")) - node T_2184 = neq(T_2073, UInt<1>("h00")) - node T_2186 = neq(T_2074, UInt<1>("h00")) - node T_2188 = neq(T_2075, UInt<1>("h00")) - node T_2190 = neq(T_2076, UInt<1>("h00")) - node T_2192 = neq(T_2077, UInt<1>("h00")) - node T_2194 = neq(T_2078, UInt<1>("h00")) - node T_2196 = neq(T_2079, UInt<1>("h00")) - node T_2198 = neq(T_2080, UInt<1>("h00")) - node T_2200 = neq(T_2081, UInt<1>("h00")) - node T_2202 = neq(T_2082, UInt<1>("h00")) - node T_2204 = neq(T_2083, UInt<1>("h00")) - node T_2206 = neq(T_2084, UInt<1>("h00")) - node T_2208 = neq(T_2085, UInt<1>("h00")) - node T_2210 = neq(T_2086, UInt<1>("h00")) - wire T_2212 : UInt<1>[62] - T_2212[0] <= T_2088 - T_2212[1] <= T_2090 - T_2212[2] <= T_2092 - T_2212[3] <= T_2094 - T_2212[4] <= T_2096 - T_2212[5] <= T_2098 - T_2212[6] <= T_2100 - T_2212[7] <= T_2102 - T_2212[8] <= T_2104 - T_2212[9] <= T_2106 - T_2212[10] <= T_2108 - T_2212[11] <= T_2110 - T_2212[12] <= T_2112 - T_2212[13] <= T_2114 - T_2212[14] <= T_2116 - T_2212[15] <= T_2118 - T_2212[16] <= T_2120 - T_2212[17] <= T_2122 - T_2212[18] <= T_2124 - T_2212[19] <= T_2126 - T_2212[20] <= T_2128 - T_2212[21] <= T_2130 - T_2212[22] <= T_2132 - T_2212[23] <= T_2134 - T_2212[24] <= T_2136 - T_2212[25] <= T_2138 - T_2212[26] <= T_2140 - T_2212[27] <= T_2142 - T_2212[28] <= T_2144 - T_2212[29] <= T_2146 - T_2212[30] <= T_2148 - T_2212[31] <= T_2150 - T_2212[32] <= T_2152 - T_2212[33] <= T_2154 - T_2212[34] <= T_2156 - T_2212[35] <= T_2158 - T_2212[36] <= T_2160 - T_2212[37] <= T_2162 - T_2212[38] <= T_2164 - T_2212[39] <= T_2166 - T_2212[40] <= T_2168 - T_2212[41] <= T_2170 - T_2212[42] <= T_2172 - T_2212[43] <= T_2174 - T_2212[44] <= T_2176 - T_2212[45] <= T_2178 - T_2212[46] <= T_2180 - T_2212[47] <= T_2182 - T_2212[48] <= T_2184 - T_2212[49] <= T_2186 - T_2212[50] <= T_2188 - T_2212[51] <= T_2190 - T_2212[52] <= T_2192 - T_2212[53] <= T_2194 - T_2212[54] <= T_2196 - T_2212[55] <= T_2198 - T_2212[56] <= T_2200 - T_2212[57] <= T_2202 - T_2212[58] <= T_2204 - T_2212[59] <= T_2206 - T_2212[60] <= T_2208 - T_2212[61] <= T_2210 - node T_2276 = cat(T_2212[60], T_2212[59]) - node T_2277 = cat(T_2212[61], T_2276) - node T_2278 = cat(T_2212[58], T_2212[57]) - node T_2279 = cat(T_2212[56], T_2212[55]) + node T_2008 = cat(T_1992, T_2007) + node T_2009 = cat(T_1978, T_2008) + node T_2010 = and(T_593, pageHit) + node T_2011 = and(T_598, pageHit) + node T_2012 = and(T_603, pageHit) + node T_2013 = and(T_608, pageHit) + node T_2014 = and(T_613, pageHit) + node T_2015 = and(T_618, pageHit) + node T_2016 = and(T_623, pageHit) + node T_2017 = and(T_628, pageHit) + node T_2018 = and(T_633, pageHit) + node T_2019 = and(T_638, pageHit) + node T_2020 = and(T_643, pageHit) + node T_2021 = and(T_648, pageHit) + node T_2022 = and(T_653, pageHit) + node T_2023 = and(T_658, pageHit) + node T_2024 = and(T_663, pageHit) + node T_2025 = and(T_668, pageHit) + node T_2026 = and(T_673, pageHit) + node T_2027 = and(T_678, pageHit) + node T_2028 = and(T_683, pageHit) + node T_2029 = and(T_688, pageHit) + node T_2030 = and(T_693, pageHit) + node T_2031 = and(T_698, pageHit) + node T_2032 = and(T_703, pageHit) + node T_2033 = and(T_708, pageHit) + node T_2034 = and(T_713, pageHit) + node T_2035 = and(T_718, pageHit) + node T_2036 = and(T_723, pageHit) + node T_2037 = and(T_728, pageHit) + node T_2038 = and(T_733, pageHit) + node T_2039 = and(T_738, pageHit) + node T_2040 = and(T_743, pageHit) + node T_2041 = and(T_748, pageHit) + node T_2042 = and(T_753, pageHit) + node T_2043 = and(T_758, pageHit) + node T_2044 = and(T_763, pageHit) + node T_2045 = and(T_768, pageHit) + node T_2046 = and(T_773, pageHit) + node T_2047 = and(T_778, pageHit) + node T_2048 = and(T_783, pageHit) + node T_2049 = and(T_788, pageHit) + node T_2050 = and(T_793, pageHit) + node T_2051 = and(T_798, pageHit) + node T_2052 = and(T_803, pageHit) + node T_2053 = and(T_808, pageHit) + node T_2054 = and(T_813, pageHit) + node T_2055 = and(T_818, pageHit) + node T_2056 = and(T_823, pageHit) + node T_2057 = and(T_828, pageHit) + node T_2058 = and(T_833, pageHit) + node T_2059 = and(T_838, pageHit) + node T_2060 = and(T_843, pageHit) + node T_2061 = and(T_848, pageHit) + node T_2062 = and(T_853, pageHit) + node T_2063 = and(T_858, pageHit) + node T_2064 = and(T_863, pageHit) + node T_2065 = and(T_868, pageHit) + node T_2066 = and(T_873, pageHit) + node T_2067 = and(T_878, pageHit) + node T_2068 = and(T_883, pageHit) + node T_2069 = and(T_888, pageHit) + node T_2070 = and(T_893, pageHit) + node T_2071 = and(T_898, pageHit) + node T_2073 = neq(T_2010, UInt<1>("h00")) + node T_2075 = neq(T_2011, UInt<1>("h00")) + node T_2077 = neq(T_2012, UInt<1>("h00")) + node T_2079 = neq(T_2013, UInt<1>("h00")) + node T_2081 = neq(T_2014, UInt<1>("h00")) + node T_2083 = neq(T_2015, UInt<1>("h00")) + node T_2085 = neq(T_2016, UInt<1>("h00")) + node T_2087 = neq(T_2017, UInt<1>("h00")) + node T_2089 = neq(T_2018, UInt<1>("h00")) + node T_2091 = neq(T_2019, UInt<1>("h00")) + node T_2093 = neq(T_2020, UInt<1>("h00")) + node T_2095 = neq(T_2021, UInt<1>("h00")) + node T_2097 = neq(T_2022, UInt<1>("h00")) + node T_2099 = neq(T_2023, UInt<1>("h00")) + node T_2101 = neq(T_2024, UInt<1>("h00")) + node T_2103 = neq(T_2025, UInt<1>("h00")) + node T_2105 = neq(T_2026, UInt<1>("h00")) + node T_2107 = neq(T_2027, UInt<1>("h00")) + node T_2109 = neq(T_2028, UInt<1>("h00")) + node T_2111 = neq(T_2029, UInt<1>("h00")) + node T_2113 = neq(T_2030, UInt<1>("h00")) + node T_2115 = neq(T_2031, UInt<1>("h00")) + node T_2117 = neq(T_2032, UInt<1>("h00")) + node T_2119 = neq(T_2033, UInt<1>("h00")) + node T_2121 = neq(T_2034, UInt<1>("h00")) + node T_2123 = neq(T_2035, UInt<1>("h00")) + node T_2125 = neq(T_2036, UInt<1>("h00")) + node T_2127 = neq(T_2037, UInt<1>("h00")) + node T_2129 = neq(T_2038, UInt<1>("h00")) + node T_2131 = neq(T_2039, UInt<1>("h00")) + node T_2133 = neq(T_2040, UInt<1>("h00")) + node T_2135 = neq(T_2041, UInt<1>("h00")) + node T_2137 = neq(T_2042, UInt<1>("h00")) + node T_2139 = neq(T_2043, UInt<1>("h00")) + node T_2141 = neq(T_2044, UInt<1>("h00")) + node T_2143 = neq(T_2045, UInt<1>("h00")) + node T_2145 = neq(T_2046, UInt<1>("h00")) + node T_2147 = neq(T_2047, UInt<1>("h00")) + node T_2149 = neq(T_2048, UInt<1>("h00")) + node T_2151 = neq(T_2049, UInt<1>("h00")) + node T_2153 = neq(T_2050, UInt<1>("h00")) + node T_2155 = neq(T_2051, UInt<1>("h00")) + node T_2157 = neq(T_2052, UInt<1>("h00")) + node T_2159 = neq(T_2053, UInt<1>("h00")) + node T_2161 = neq(T_2054, UInt<1>("h00")) + node T_2163 = neq(T_2055, UInt<1>("h00")) + node T_2165 = neq(T_2056, UInt<1>("h00")) + node T_2167 = neq(T_2057, UInt<1>("h00")) + node T_2169 = neq(T_2058, UInt<1>("h00")) + node T_2171 = neq(T_2059, UInt<1>("h00")) + node T_2173 = neq(T_2060, UInt<1>("h00")) + node T_2175 = neq(T_2061, UInt<1>("h00")) + node T_2177 = neq(T_2062, UInt<1>("h00")) + node T_2179 = neq(T_2063, UInt<1>("h00")) + node T_2181 = neq(T_2064, UInt<1>("h00")) + node T_2183 = neq(T_2065, UInt<1>("h00")) + node T_2185 = neq(T_2066, UInt<1>("h00")) + node T_2187 = neq(T_2067, UInt<1>("h00")) + node T_2189 = neq(T_2068, UInt<1>("h00")) + node T_2191 = neq(T_2069, UInt<1>("h00")) + node T_2193 = neq(T_2070, UInt<1>("h00")) + node T_2195 = neq(T_2071, UInt<1>("h00")) + wire T_2197 : UInt<1>[62] + T_2197[0] <= T_2073 + T_2197[1] <= T_2075 + T_2197[2] <= T_2077 + T_2197[3] <= T_2079 + T_2197[4] <= T_2081 + T_2197[5] <= T_2083 + T_2197[6] <= T_2085 + T_2197[7] <= T_2087 + T_2197[8] <= T_2089 + T_2197[9] <= T_2091 + T_2197[10] <= T_2093 + T_2197[11] <= T_2095 + T_2197[12] <= T_2097 + T_2197[13] <= T_2099 + T_2197[14] <= T_2101 + T_2197[15] <= T_2103 + T_2197[16] <= T_2105 + T_2197[17] <= T_2107 + T_2197[18] <= T_2109 + T_2197[19] <= T_2111 + T_2197[20] <= T_2113 + T_2197[21] <= T_2115 + T_2197[22] <= T_2117 + T_2197[23] <= T_2119 + T_2197[24] <= T_2121 + T_2197[25] <= T_2123 + T_2197[26] <= T_2125 + T_2197[27] <= T_2127 + T_2197[28] <= T_2129 + T_2197[29] <= T_2131 + T_2197[30] <= T_2133 + T_2197[31] <= T_2135 + T_2197[32] <= T_2137 + T_2197[33] <= T_2139 + T_2197[34] <= T_2141 + T_2197[35] <= T_2143 + T_2197[36] <= T_2145 + T_2197[37] <= T_2147 + T_2197[38] <= T_2149 + T_2197[39] <= T_2151 + T_2197[40] <= T_2153 + T_2197[41] <= T_2155 + T_2197[42] <= T_2157 + T_2197[43] <= T_2159 + T_2197[44] <= T_2161 + T_2197[45] <= T_2163 + T_2197[46] <= T_2165 + T_2197[47] <= T_2167 + T_2197[48] <= T_2169 + T_2197[49] <= T_2171 + T_2197[50] <= T_2173 + T_2197[51] <= T_2175 + T_2197[52] <= T_2177 + T_2197[53] <= T_2179 + T_2197[54] <= T_2181 + T_2197[55] <= T_2183 + T_2197[56] <= T_2185 + T_2197[57] <= T_2187 + T_2197[58] <= T_2189 + T_2197[59] <= T_2191 + T_2197[60] <= T_2193 + T_2197[61] <= T_2195 + node T_2261 = cat(T_2197[60], T_2197[59]) + node T_2262 = cat(T_2197[61], T_2261) + node T_2263 = cat(T_2197[58], T_2197[57]) + node T_2264 = cat(T_2197[56], T_2197[55]) + node T_2265 = cat(T_2263, T_2264) + node T_2266 = cat(T_2262, T_2265) + node T_2267 = cat(T_2197[54], T_2197[53]) + node T_2268 = cat(T_2197[52], T_2197[51]) + node T_2269 = cat(T_2267, T_2268) + node T_2270 = cat(T_2197[50], T_2197[49]) + node T_2271 = cat(T_2197[48], T_2197[47]) + node T_2272 = cat(T_2270, T_2271) + node T_2273 = cat(T_2269, T_2272) + node T_2274 = cat(T_2266, T_2273) + node T_2275 = cat(T_2197[46], T_2197[45]) + node T_2276 = cat(T_2197[44], T_2197[43]) + node T_2277 = cat(T_2275, T_2276) + node T_2278 = cat(T_2197[42], T_2197[41]) + node T_2279 = cat(T_2197[40], T_2197[39]) node T_2280 = cat(T_2278, T_2279) node T_2281 = cat(T_2277, T_2280) - node T_2282 = cat(T_2212[54], T_2212[53]) - node T_2283 = cat(T_2212[52], T_2212[51]) + node T_2282 = cat(T_2197[38], T_2197[37]) + node T_2283 = cat(T_2197[36], T_2197[35]) node T_2284 = cat(T_2282, T_2283) - node T_2285 = cat(T_2212[50], T_2212[49]) - node T_2286 = cat(T_2212[48], T_2212[47]) + node T_2285 = cat(T_2197[34], T_2197[33]) + node T_2286 = cat(T_2197[32], T_2197[31]) node T_2287 = cat(T_2285, T_2286) node T_2288 = cat(T_2284, T_2287) node T_2289 = cat(T_2281, T_2288) - node T_2290 = cat(T_2212[46], T_2212[45]) - node T_2291 = cat(T_2212[44], T_2212[43]) - node T_2292 = cat(T_2290, T_2291) - node T_2293 = cat(T_2212[42], T_2212[41]) - node T_2294 = cat(T_2212[40], T_2212[39]) + node T_2290 = cat(T_2274, T_2289) + node T_2291 = cat(T_2197[29], T_2197[28]) + node T_2292 = cat(T_2197[30], T_2291) + node T_2293 = cat(T_2197[27], T_2197[26]) + node T_2294 = cat(T_2197[25], T_2197[24]) node T_2295 = cat(T_2293, T_2294) node T_2296 = cat(T_2292, T_2295) - node T_2297 = cat(T_2212[38], T_2212[37]) - node T_2298 = cat(T_2212[36], T_2212[35]) + node T_2297 = cat(T_2197[23], T_2197[22]) + node T_2298 = cat(T_2197[21], T_2197[20]) node T_2299 = cat(T_2297, T_2298) - node T_2300 = cat(T_2212[34], T_2212[33]) - node T_2301 = cat(T_2212[32], T_2212[31]) + node T_2300 = cat(T_2197[19], T_2197[18]) + node T_2301 = cat(T_2197[17], T_2197[16]) node T_2302 = cat(T_2300, T_2301) node T_2303 = cat(T_2299, T_2302) node T_2304 = cat(T_2296, T_2303) - node T_2305 = cat(T_2289, T_2304) - node T_2306 = cat(T_2212[29], T_2212[28]) - node T_2307 = cat(T_2212[30], T_2306) - node T_2308 = cat(T_2212[27], T_2212[26]) - node T_2309 = cat(T_2212[25], T_2212[24]) + node T_2305 = cat(T_2197[15], T_2197[14]) + node T_2306 = cat(T_2197[13], T_2197[12]) + node T_2307 = cat(T_2305, T_2306) + node T_2308 = cat(T_2197[11], T_2197[10]) + node T_2309 = cat(T_2197[9], T_2197[8]) node T_2310 = cat(T_2308, T_2309) node T_2311 = cat(T_2307, T_2310) - node T_2312 = cat(T_2212[23], T_2212[22]) - node T_2313 = cat(T_2212[21], T_2212[20]) + node T_2312 = cat(T_2197[7], T_2197[6]) + node T_2313 = cat(T_2197[5], T_2197[4]) node T_2314 = cat(T_2312, T_2313) - node T_2315 = cat(T_2212[19], T_2212[18]) - node T_2316 = cat(T_2212[17], T_2212[16]) + node T_2315 = cat(T_2197[3], T_2197[2]) + node T_2316 = cat(T_2197[1], T_2197[0]) node T_2317 = cat(T_2315, T_2316) node T_2318 = cat(T_2314, T_2317) node T_2319 = cat(T_2311, T_2318) - node T_2320 = cat(T_2212[15], T_2212[14]) - node T_2321 = cat(T_2212[13], T_2212[12]) - node T_2322 = cat(T_2320, T_2321) - node T_2323 = cat(T_2212[11], T_2212[10]) - node T_2324 = cat(T_2212[9], T_2212[8]) - node T_2325 = cat(T_2323, T_2324) - node T_2326 = cat(T_2322, T_2325) - node T_2327 = cat(T_2212[7], T_2212[6]) - node T_2328 = cat(T_2212[5], T_2212[4]) - node T_2329 = cat(T_2327, T_2328) - node T_2330 = cat(T_2212[3], T_2212[2]) - node T_2331 = cat(T_2212[1], T_2212[0]) - node T_2332 = cat(T_2330, T_2331) - node T_2333 = cat(T_2329, T_2332) - node T_2334 = cat(T_2326, T_2333) - node T_2335 = cat(T_2319, T_2334) - node T_2336 = cat(T_2305, T_2335) - node T_2337 = and(idxValid, T_2024) - node hits = and(T_2337, T_2336) - node T_2339 = shr(r_btb_update.bits.pc, 12) - infer mport T_2341 = pages[UInt<1>("h00")], clk - node T_2342 = eq(T_2341, T_2339) - infer mport T_2344 = pages[UInt<1>("h01")], clk - node T_2345 = eq(T_2344, T_2339) - infer mport T_2347 = pages[UInt<2>("h02")], clk - node T_2348 = eq(T_2347, T_2339) - infer mport T_2350 = pages[UInt<2>("h03")], clk - node T_2351 = eq(T_2350, T_2339) - infer mport T_2353 = pages[UInt<3>("h04")], clk - node T_2354 = eq(T_2353, T_2339) - infer mport T_2356 = pages[UInt<3>("h05")], clk - node T_2357 = eq(T_2356, T_2339) - wire T_2359 : UInt<1>[6] - T_2359[0] <= T_2342 - T_2359[1] <= T_2345 - T_2359[2] <= T_2348 - T_2359[3] <= T_2351 - T_2359[4] <= T_2354 - T_2359[5] <= T_2357 - node T_2367 = cat(T_2359[4], T_2359[3]) - node T_2368 = cat(T_2359[5], T_2367) - node T_2369 = cat(T_2359[1], T_2359[0]) - node T_2370 = cat(T_2359[2], T_2369) - node T_2371 = cat(T_2368, T_2370) - node updatePageHit = and(T_2371, pageValid) - node T_2373 = bits(r_btb_update.bits.pc, 11, 0) - infer mport T_2375 = idxs[UInt<1>("h00")], clk - node T_2376 = eq(T_2375, T_2373) - infer mport T_2378 = idxs[UInt<1>("h01")], clk - node T_2379 = eq(T_2378, T_2373) - infer mport T_2381 = idxs[UInt<2>("h02")], clk - node T_2382 = eq(T_2381, T_2373) - infer mport T_2384 = idxs[UInt<2>("h03")], clk - node T_2385 = eq(T_2384, T_2373) - infer mport T_2387 = idxs[UInt<3>("h04")], clk - node T_2388 = eq(T_2387, T_2373) - infer mport T_2390 = idxs[UInt<3>("h05")], clk - node T_2391 = eq(T_2390, T_2373) - infer mport T_2393 = idxs[UInt<3>("h06")], clk - node T_2394 = eq(T_2393, T_2373) - infer mport T_2396 = idxs[UInt<3>("h07")], clk - node T_2397 = eq(T_2396, T_2373) - infer mport T_2399 = idxs[UInt<4>("h08")], clk - node T_2400 = eq(T_2399, T_2373) - infer mport T_2402 = idxs[UInt<4>("h09")], clk - node T_2403 = eq(T_2402, T_2373) - infer mport T_2405 = idxs[UInt<4>("h0a")], clk - node T_2406 = eq(T_2405, T_2373) - infer mport T_2408 = idxs[UInt<4>("h0b")], clk - node T_2409 = eq(T_2408, T_2373) - infer mport T_2411 = idxs[UInt<4>("h0c")], clk - node T_2412 = eq(T_2411, T_2373) - infer mport T_2414 = idxs[UInt<4>("h0d")], clk - node T_2415 = eq(T_2414, T_2373) - infer mport T_2417 = idxs[UInt<4>("h0e")], clk - node T_2418 = eq(T_2417, T_2373) - infer mport T_2420 = idxs[UInt<4>("h0f")], clk - node T_2421 = eq(T_2420, T_2373) - infer mport T_2423 = idxs[UInt<5>("h010")], clk - node T_2424 = eq(T_2423, T_2373) - infer mport T_2426 = idxs[UInt<5>("h011")], clk - node T_2427 = eq(T_2426, T_2373) - infer mport T_2429 = idxs[UInt<5>("h012")], clk - node T_2430 = eq(T_2429, T_2373) - infer mport T_2432 = idxs[UInt<5>("h013")], clk - node T_2433 = eq(T_2432, T_2373) - infer mport T_2435 = idxs[UInt<5>("h014")], clk - node T_2436 = eq(T_2435, T_2373) - infer mport T_2438 = idxs[UInt<5>("h015")], clk - node T_2439 = eq(T_2438, T_2373) - infer mport T_2441 = idxs[UInt<5>("h016")], clk - node T_2442 = eq(T_2441, T_2373) - infer mport T_2444 = idxs[UInt<5>("h017")], clk - node T_2445 = eq(T_2444, T_2373) - infer mport T_2447 = idxs[UInt<5>("h018")], clk - node T_2448 = eq(T_2447, T_2373) - infer mport T_2450 = idxs[UInt<5>("h019")], clk - node T_2451 = eq(T_2450, T_2373) - infer mport T_2453 = idxs[UInt<5>("h01a")], clk - node T_2454 = eq(T_2453, T_2373) - infer mport T_2456 = idxs[UInt<5>("h01b")], clk - node T_2457 = eq(T_2456, T_2373) - infer mport T_2459 = idxs[UInt<5>("h01c")], clk - node T_2460 = eq(T_2459, T_2373) - infer mport T_2462 = idxs[UInt<5>("h01d")], clk - node T_2463 = eq(T_2462, T_2373) - infer mport T_2465 = idxs[UInt<5>("h01e")], clk - node T_2466 = eq(T_2465, T_2373) - infer mport T_2468 = idxs[UInt<5>("h01f")], clk - node T_2469 = eq(T_2468, T_2373) - infer mport T_2471 = idxs[UInt<6>("h020")], clk - node T_2472 = eq(T_2471, T_2373) - infer mport T_2474 = idxs[UInt<6>("h021")], clk - node T_2475 = eq(T_2474, T_2373) - infer mport T_2477 = idxs[UInt<6>("h022")], clk - node T_2478 = eq(T_2477, T_2373) - infer mport T_2480 = idxs[UInt<6>("h023")], clk - node T_2481 = eq(T_2480, T_2373) - infer mport T_2483 = idxs[UInt<6>("h024")], clk - node T_2484 = eq(T_2483, T_2373) - infer mport T_2486 = idxs[UInt<6>("h025")], clk - node T_2487 = eq(T_2486, T_2373) - infer mport T_2489 = idxs[UInt<6>("h026")], clk - node T_2490 = eq(T_2489, T_2373) - infer mport T_2492 = idxs[UInt<6>("h027")], clk - node T_2493 = eq(T_2492, T_2373) - infer mport T_2495 = idxs[UInt<6>("h028")], clk - node T_2496 = eq(T_2495, T_2373) - infer mport T_2498 = idxs[UInt<6>("h029")], clk - node T_2499 = eq(T_2498, T_2373) - infer mport T_2501 = idxs[UInt<6>("h02a")], clk - node T_2502 = eq(T_2501, T_2373) - infer mport T_2504 = idxs[UInt<6>("h02b")], clk - node T_2505 = eq(T_2504, T_2373) - infer mport T_2507 = idxs[UInt<6>("h02c")], clk - node T_2508 = eq(T_2507, T_2373) - infer mport T_2510 = idxs[UInt<6>("h02d")], clk - node T_2511 = eq(T_2510, T_2373) - infer mport T_2513 = idxs[UInt<6>("h02e")], clk - node T_2514 = eq(T_2513, T_2373) - infer mport T_2516 = idxs[UInt<6>("h02f")], clk - node T_2517 = eq(T_2516, T_2373) - infer mport T_2519 = idxs[UInt<6>("h030")], clk - node T_2520 = eq(T_2519, T_2373) - infer mport T_2522 = idxs[UInt<6>("h031")], clk - node T_2523 = eq(T_2522, T_2373) - infer mport T_2525 = idxs[UInt<6>("h032")], clk - node T_2526 = eq(T_2525, T_2373) - infer mport T_2528 = idxs[UInt<6>("h033")], clk - node T_2529 = eq(T_2528, T_2373) - infer mport T_2531 = idxs[UInt<6>("h034")], clk - node T_2532 = eq(T_2531, T_2373) - infer mport T_2534 = idxs[UInt<6>("h035")], clk - node T_2535 = eq(T_2534, T_2373) - infer mport T_2537 = idxs[UInt<6>("h036")], clk - node T_2538 = eq(T_2537, T_2373) - infer mport T_2540 = idxs[UInt<6>("h037")], clk - node T_2541 = eq(T_2540, T_2373) - infer mport T_2543 = idxs[UInt<6>("h038")], clk - node T_2544 = eq(T_2543, T_2373) - infer mport T_2546 = idxs[UInt<6>("h039")], clk - node T_2547 = eq(T_2546, T_2373) - infer mport T_2549 = idxs[UInt<6>("h03a")], clk - node T_2550 = eq(T_2549, T_2373) - infer mport T_2552 = idxs[UInt<6>("h03b")], clk - node T_2553 = eq(T_2552, T_2373) - infer mport T_2555 = idxs[UInt<6>("h03c")], clk - node T_2556 = eq(T_2555, T_2373) - infer mport T_2558 = idxs[UInt<6>("h03d")], clk - node T_2559 = eq(T_2558, T_2373) - wire T_2561 : UInt<1>[62] - T_2561[0] <= T_2376 - T_2561[1] <= T_2379 - T_2561[2] <= T_2382 - T_2561[3] <= T_2385 - T_2561[4] <= T_2388 - T_2561[5] <= T_2391 - T_2561[6] <= T_2394 - T_2561[7] <= T_2397 - T_2561[8] <= T_2400 - T_2561[9] <= T_2403 - T_2561[10] <= T_2406 - T_2561[11] <= T_2409 - T_2561[12] <= T_2412 - T_2561[13] <= T_2415 - T_2561[14] <= T_2418 - T_2561[15] <= T_2421 - T_2561[16] <= T_2424 - T_2561[17] <= T_2427 - T_2561[18] <= T_2430 - T_2561[19] <= T_2433 - T_2561[20] <= T_2436 - T_2561[21] <= T_2439 - T_2561[22] <= T_2442 - T_2561[23] <= T_2445 - T_2561[24] <= T_2448 - T_2561[25] <= T_2451 - T_2561[26] <= T_2454 - T_2561[27] <= T_2457 - T_2561[28] <= T_2460 - T_2561[29] <= T_2463 - T_2561[30] <= T_2466 - T_2561[31] <= T_2469 - T_2561[32] <= T_2472 - T_2561[33] <= T_2475 - T_2561[34] <= T_2478 - T_2561[35] <= T_2481 - T_2561[36] <= T_2484 - T_2561[37] <= T_2487 - T_2561[38] <= T_2490 - T_2561[39] <= T_2493 - T_2561[40] <= T_2496 - T_2561[41] <= T_2499 - T_2561[42] <= T_2502 - T_2561[43] <= T_2505 - T_2561[44] <= T_2508 - T_2561[45] <= T_2511 - T_2561[46] <= T_2514 - T_2561[47] <= T_2517 - T_2561[48] <= T_2520 - T_2561[49] <= T_2523 - T_2561[50] <= T_2526 - T_2561[51] <= T_2529 - T_2561[52] <= T_2532 - T_2561[53] <= T_2535 - T_2561[54] <= T_2538 - T_2561[55] <= T_2541 - T_2561[56] <= T_2544 - T_2561[57] <= T_2547 - T_2561[58] <= T_2550 - T_2561[59] <= T_2553 - T_2561[60] <= T_2556 - T_2561[61] <= T_2559 - node T_2625 = cat(T_2561[60], T_2561[59]) - node T_2626 = cat(T_2561[61], T_2625) - node T_2627 = cat(T_2561[58], T_2561[57]) - node T_2628 = cat(T_2561[56], T_2561[55]) + node T_2320 = cat(T_2304, T_2319) + node T_2321 = cat(T_2290, T_2320) + node T_2322 = and(idxValid, T_2009) + node hits = and(T_2322, T_2321) + node T_2324 = shr(r_btb_update.bits.pc, 12) + infer mport T_2326 = pages[UInt<1>("h00")], clk + node T_2327 = eq(T_2326, T_2324) + infer mport T_2329 = pages[UInt<1>("h01")], clk + node T_2330 = eq(T_2329, T_2324) + infer mport T_2332 = pages[UInt<2>("h02")], clk + node T_2333 = eq(T_2332, T_2324) + infer mport T_2335 = pages[UInt<2>("h03")], clk + node T_2336 = eq(T_2335, T_2324) + infer mport T_2338 = pages[UInt<3>("h04")], clk + node T_2339 = eq(T_2338, T_2324) + infer mport T_2341 = pages[UInt<3>("h05")], clk + node T_2342 = eq(T_2341, T_2324) + wire T_2344 : UInt<1>[6] + T_2344[0] <= T_2327 + T_2344[1] <= T_2330 + T_2344[2] <= T_2333 + T_2344[3] <= T_2336 + T_2344[4] <= T_2339 + T_2344[5] <= T_2342 + node T_2352 = cat(T_2344[4], T_2344[3]) + node T_2353 = cat(T_2344[5], T_2352) + node T_2354 = cat(T_2344[1], T_2344[0]) + node T_2355 = cat(T_2344[2], T_2354) + node T_2356 = cat(T_2353, T_2355) + node updatePageHit = and(T_2356, pageValid) + node T_2358 = bits(r_btb_update.bits.pc, 11, 0) + infer mport T_2360 = idxs[UInt<1>("h00")], clk + node T_2361 = eq(T_2360, T_2358) + infer mport T_2363 = idxs[UInt<1>("h01")], clk + node T_2364 = eq(T_2363, T_2358) + infer mport T_2366 = idxs[UInt<2>("h02")], clk + node T_2367 = eq(T_2366, T_2358) + infer mport T_2369 = idxs[UInt<2>("h03")], clk + node T_2370 = eq(T_2369, T_2358) + infer mport T_2372 = idxs[UInt<3>("h04")], clk + node T_2373 = eq(T_2372, T_2358) + infer mport T_2375 = idxs[UInt<3>("h05")], clk + node T_2376 = eq(T_2375, T_2358) + infer mport T_2378 = idxs[UInt<3>("h06")], clk + node T_2379 = eq(T_2378, T_2358) + infer mport T_2381 = idxs[UInt<3>("h07")], clk + node T_2382 = eq(T_2381, T_2358) + infer mport T_2384 = idxs[UInt<4>("h08")], clk + node T_2385 = eq(T_2384, T_2358) + infer mport T_2387 = idxs[UInt<4>("h09")], clk + node T_2388 = eq(T_2387, T_2358) + infer mport T_2390 = idxs[UInt<4>("h0a")], clk + node T_2391 = eq(T_2390, T_2358) + infer mport T_2393 = idxs[UInt<4>("h0b")], clk + node T_2394 = eq(T_2393, T_2358) + infer mport T_2396 = idxs[UInt<4>("h0c")], clk + node T_2397 = eq(T_2396, T_2358) + infer mport T_2399 = idxs[UInt<4>("h0d")], clk + node T_2400 = eq(T_2399, T_2358) + infer mport T_2402 = idxs[UInt<4>("h0e")], clk + node T_2403 = eq(T_2402, T_2358) + infer mport T_2405 = idxs[UInt<4>("h0f")], clk + node T_2406 = eq(T_2405, T_2358) + infer mport T_2408 = idxs[UInt<5>("h010")], clk + node T_2409 = eq(T_2408, T_2358) + infer mport T_2411 = idxs[UInt<5>("h011")], clk + node T_2412 = eq(T_2411, T_2358) + infer mport T_2414 = idxs[UInt<5>("h012")], clk + node T_2415 = eq(T_2414, T_2358) + infer mport T_2417 = idxs[UInt<5>("h013")], clk + node T_2418 = eq(T_2417, T_2358) + infer mport T_2420 = idxs[UInt<5>("h014")], clk + node T_2421 = eq(T_2420, T_2358) + infer mport T_2423 = idxs[UInt<5>("h015")], clk + node T_2424 = eq(T_2423, T_2358) + infer mport T_2426 = idxs[UInt<5>("h016")], clk + node T_2427 = eq(T_2426, T_2358) + infer mport T_2429 = idxs[UInt<5>("h017")], clk + node T_2430 = eq(T_2429, T_2358) + infer mport T_2432 = idxs[UInt<5>("h018")], clk + node T_2433 = eq(T_2432, T_2358) + infer mport T_2435 = idxs[UInt<5>("h019")], clk + node T_2436 = eq(T_2435, T_2358) + infer mport T_2438 = idxs[UInt<5>("h01a")], clk + node T_2439 = eq(T_2438, T_2358) + infer mport T_2441 = idxs[UInt<5>("h01b")], clk + node T_2442 = eq(T_2441, T_2358) + infer mport T_2444 = idxs[UInt<5>("h01c")], clk + node T_2445 = eq(T_2444, T_2358) + infer mport T_2447 = idxs[UInt<5>("h01d")], clk + node T_2448 = eq(T_2447, T_2358) + infer mport T_2450 = idxs[UInt<5>("h01e")], clk + node T_2451 = eq(T_2450, T_2358) + infer mport T_2453 = idxs[UInt<5>("h01f")], clk + node T_2454 = eq(T_2453, T_2358) + infer mport T_2456 = idxs[UInt<6>("h020")], clk + node T_2457 = eq(T_2456, T_2358) + infer mport T_2459 = idxs[UInt<6>("h021")], clk + node T_2460 = eq(T_2459, T_2358) + infer mport T_2462 = idxs[UInt<6>("h022")], clk + node T_2463 = eq(T_2462, T_2358) + infer mport T_2465 = idxs[UInt<6>("h023")], clk + node T_2466 = eq(T_2465, T_2358) + infer mport T_2468 = idxs[UInt<6>("h024")], clk + node T_2469 = eq(T_2468, T_2358) + infer mport T_2471 = idxs[UInt<6>("h025")], clk + node T_2472 = eq(T_2471, T_2358) + infer mport T_2474 = idxs[UInt<6>("h026")], clk + node T_2475 = eq(T_2474, T_2358) + infer mport T_2477 = idxs[UInt<6>("h027")], clk + node T_2478 = eq(T_2477, T_2358) + infer mport T_2480 = idxs[UInt<6>("h028")], clk + node T_2481 = eq(T_2480, T_2358) + infer mport T_2483 = idxs[UInt<6>("h029")], clk + node T_2484 = eq(T_2483, T_2358) + infer mport T_2486 = idxs[UInt<6>("h02a")], clk + node T_2487 = eq(T_2486, T_2358) + infer mport T_2489 = idxs[UInt<6>("h02b")], clk + node T_2490 = eq(T_2489, T_2358) + infer mport T_2492 = idxs[UInt<6>("h02c")], clk + node T_2493 = eq(T_2492, T_2358) + infer mport T_2495 = idxs[UInt<6>("h02d")], clk + node T_2496 = eq(T_2495, T_2358) + infer mport T_2498 = idxs[UInt<6>("h02e")], clk + node T_2499 = eq(T_2498, T_2358) + infer mport T_2501 = idxs[UInt<6>("h02f")], clk + node T_2502 = eq(T_2501, T_2358) + infer mport T_2504 = idxs[UInt<6>("h030")], clk + node T_2505 = eq(T_2504, T_2358) + infer mport T_2507 = idxs[UInt<6>("h031")], clk + node T_2508 = eq(T_2507, T_2358) + infer mport T_2510 = idxs[UInt<6>("h032")], clk + node T_2511 = eq(T_2510, T_2358) + infer mport T_2513 = idxs[UInt<6>("h033")], clk + node T_2514 = eq(T_2513, T_2358) + infer mport T_2516 = idxs[UInt<6>("h034")], clk + node T_2517 = eq(T_2516, T_2358) + infer mport T_2519 = idxs[UInt<6>("h035")], clk + node T_2520 = eq(T_2519, T_2358) + infer mport T_2522 = idxs[UInt<6>("h036")], clk + node T_2523 = eq(T_2522, T_2358) + infer mport T_2525 = idxs[UInt<6>("h037")], clk + node T_2526 = eq(T_2525, T_2358) + infer mport T_2528 = idxs[UInt<6>("h038")], clk + node T_2529 = eq(T_2528, T_2358) + infer mport T_2531 = idxs[UInt<6>("h039")], clk + node T_2532 = eq(T_2531, T_2358) + infer mport T_2534 = idxs[UInt<6>("h03a")], clk + node T_2535 = eq(T_2534, T_2358) + infer mport T_2537 = idxs[UInt<6>("h03b")], clk + node T_2538 = eq(T_2537, T_2358) + infer mport T_2540 = idxs[UInt<6>("h03c")], clk + node T_2541 = eq(T_2540, T_2358) + infer mport T_2543 = idxs[UInt<6>("h03d")], clk + node T_2544 = eq(T_2543, T_2358) + wire T_2546 : UInt<1>[62] + T_2546[0] <= T_2361 + T_2546[1] <= T_2364 + T_2546[2] <= T_2367 + T_2546[3] <= T_2370 + T_2546[4] <= T_2373 + T_2546[5] <= T_2376 + T_2546[6] <= T_2379 + T_2546[7] <= T_2382 + T_2546[8] <= T_2385 + T_2546[9] <= T_2388 + T_2546[10] <= T_2391 + T_2546[11] <= T_2394 + T_2546[12] <= T_2397 + T_2546[13] <= T_2400 + T_2546[14] <= T_2403 + T_2546[15] <= T_2406 + T_2546[16] <= T_2409 + T_2546[17] <= T_2412 + T_2546[18] <= T_2415 + T_2546[19] <= T_2418 + T_2546[20] <= T_2421 + T_2546[21] <= T_2424 + T_2546[22] <= T_2427 + T_2546[23] <= T_2430 + T_2546[24] <= T_2433 + T_2546[25] <= T_2436 + T_2546[26] <= T_2439 + T_2546[27] <= T_2442 + T_2546[28] <= T_2445 + T_2546[29] <= T_2448 + T_2546[30] <= T_2451 + T_2546[31] <= T_2454 + T_2546[32] <= T_2457 + T_2546[33] <= T_2460 + T_2546[34] <= T_2463 + T_2546[35] <= T_2466 + T_2546[36] <= T_2469 + T_2546[37] <= T_2472 + T_2546[38] <= T_2475 + T_2546[39] <= T_2478 + T_2546[40] <= T_2481 + T_2546[41] <= T_2484 + T_2546[42] <= T_2487 + T_2546[43] <= T_2490 + T_2546[44] <= T_2493 + T_2546[45] <= T_2496 + T_2546[46] <= T_2499 + T_2546[47] <= T_2502 + T_2546[48] <= T_2505 + T_2546[49] <= T_2508 + T_2546[50] <= T_2511 + T_2546[51] <= T_2514 + T_2546[52] <= T_2517 + T_2546[53] <= T_2520 + T_2546[54] <= T_2523 + T_2546[55] <= T_2526 + T_2546[56] <= T_2529 + T_2546[57] <= T_2532 + T_2546[58] <= T_2535 + T_2546[59] <= T_2538 + T_2546[60] <= T_2541 + T_2546[61] <= T_2544 + node T_2610 = cat(T_2546[60], T_2546[59]) + node T_2611 = cat(T_2546[61], T_2610) + node T_2612 = cat(T_2546[58], T_2546[57]) + node T_2613 = cat(T_2546[56], T_2546[55]) + node T_2614 = cat(T_2612, T_2613) + node T_2615 = cat(T_2611, T_2614) + node T_2616 = cat(T_2546[54], T_2546[53]) + node T_2617 = cat(T_2546[52], T_2546[51]) + node T_2618 = cat(T_2616, T_2617) + node T_2619 = cat(T_2546[50], T_2546[49]) + node T_2620 = cat(T_2546[48], T_2546[47]) + node T_2621 = cat(T_2619, T_2620) + node T_2622 = cat(T_2618, T_2621) + node T_2623 = cat(T_2615, T_2622) + node T_2624 = cat(T_2546[46], T_2546[45]) + node T_2625 = cat(T_2546[44], T_2546[43]) + node T_2626 = cat(T_2624, T_2625) + node T_2627 = cat(T_2546[42], T_2546[41]) + node T_2628 = cat(T_2546[40], T_2546[39]) node T_2629 = cat(T_2627, T_2628) node T_2630 = cat(T_2626, T_2629) - node T_2631 = cat(T_2561[54], T_2561[53]) - node T_2632 = cat(T_2561[52], T_2561[51]) + node T_2631 = cat(T_2546[38], T_2546[37]) + node T_2632 = cat(T_2546[36], T_2546[35]) node T_2633 = cat(T_2631, T_2632) - node T_2634 = cat(T_2561[50], T_2561[49]) - node T_2635 = cat(T_2561[48], T_2561[47]) + node T_2634 = cat(T_2546[34], T_2546[33]) + node T_2635 = cat(T_2546[32], T_2546[31]) node T_2636 = cat(T_2634, T_2635) node T_2637 = cat(T_2633, T_2636) node T_2638 = cat(T_2630, T_2637) - node T_2639 = cat(T_2561[46], T_2561[45]) - node T_2640 = cat(T_2561[44], T_2561[43]) - node T_2641 = cat(T_2639, T_2640) - node T_2642 = cat(T_2561[42], T_2561[41]) - node T_2643 = cat(T_2561[40], T_2561[39]) + node T_2639 = cat(T_2623, T_2638) + node T_2640 = cat(T_2546[29], T_2546[28]) + node T_2641 = cat(T_2546[30], T_2640) + node T_2642 = cat(T_2546[27], T_2546[26]) + node T_2643 = cat(T_2546[25], T_2546[24]) node T_2644 = cat(T_2642, T_2643) node T_2645 = cat(T_2641, T_2644) - node T_2646 = cat(T_2561[38], T_2561[37]) - node T_2647 = cat(T_2561[36], T_2561[35]) + node T_2646 = cat(T_2546[23], T_2546[22]) + node T_2647 = cat(T_2546[21], T_2546[20]) node T_2648 = cat(T_2646, T_2647) - node T_2649 = cat(T_2561[34], T_2561[33]) - node T_2650 = cat(T_2561[32], T_2561[31]) + node T_2649 = cat(T_2546[19], T_2546[18]) + node T_2650 = cat(T_2546[17], T_2546[16]) node T_2651 = cat(T_2649, T_2650) node T_2652 = cat(T_2648, T_2651) node T_2653 = cat(T_2645, T_2652) - node T_2654 = cat(T_2638, T_2653) - node T_2655 = cat(T_2561[29], T_2561[28]) - node T_2656 = cat(T_2561[30], T_2655) - node T_2657 = cat(T_2561[27], T_2561[26]) - node T_2658 = cat(T_2561[25], T_2561[24]) + node T_2654 = cat(T_2546[15], T_2546[14]) + node T_2655 = cat(T_2546[13], T_2546[12]) + node T_2656 = cat(T_2654, T_2655) + node T_2657 = cat(T_2546[11], T_2546[10]) + node T_2658 = cat(T_2546[9], T_2546[8]) node T_2659 = cat(T_2657, T_2658) node T_2660 = cat(T_2656, T_2659) - node T_2661 = cat(T_2561[23], T_2561[22]) - node T_2662 = cat(T_2561[21], T_2561[20]) + node T_2661 = cat(T_2546[7], T_2546[6]) + node T_2662 = cat(T_2546[5], T_2546[4]) node T_2663 = cat(T_2661, T_2662) - node T_2664 = cat(T_2561[19], T_2561[18]) - node T_2665 = cat(T_2561[17], T_2561[16]) + node T_2664 = cat(T_2546[3], T_2546[2]) + node T_2665 = cat(T_2546[1], T_2546[0]) node T_2666 = cat(T_2664, T_2665) node T_2667 = cat(T_2663, T_2666) node T_2668 = cat(T_2660, T_2667) - node T_2669 = cat(T_2561[15], T_2561[14]) - node T_2670 = cat(T_2561[13], T_2561[12]) - node T_2671 = cat(T_2669, T_2670) - node T_2672 = cat(T_2561[11], T_2561[10]) - node T_2673 = cat(T_2561[9], T_2561[8]) - node T_2674 = cat(T_2672, T_2673) - node T_2675 = cat(T_2671, T_2674) - node T_2676 = cat(T_2561[7], T_2561[6]) - node T_2677 = cat(T_2561[5], T_2561[4]) - node T_2678 = cat(T_2676, T_2677) - node T_2679 = cat(T_2561[3], T_2561[2]) - node T_2680 = cat(T_2561[1], T_2561[0]) - node T_2681 = cat(T_2679, T_2680) - node T_2682 = cat(T_2678, T_2681) - node T_2683 = cat(T_2675, T_2682) - node T_2684 = cat(T_2668, T_2683) - node T_2685 = cat(T_2654, T_2684) - node T_2686 = and(T_593, updatePageHit) - node T_2687 = and(T_598, updatePageHit) - node T_2688 = and(T_603, updatePageHit) - node T_2689 = and(T_608, updatePageHit) - node T_2690 = and(T_613, updatePageHit) - node T_2691 = and(T_618, updatePageHit) - node T_2692 = and(T_623, updatePageHit) - node T_2693 = and(T_628, updatePageHit) - node T_2694 = and(T_633, updatePageHit) - node T_2695 = and(T_638, updatePageHit) - node T_2696 = and(T_643, updatePageHit) - node T_2697 = and(T_648, updatePageHit) - node T_2698 = and(T_653, updatePageHit) - node T_2699 = and(T_658, updatePageHit) - node T_2700 = and(T_663, updatePageHit) - node T_2701 = and(T_668, updatePageHit) - node T_2702 = and(T_673, updatePageHit) - node T_2703 = and(T_678, updatePageHit) - node T_2704 = and(T_683, updatePageHit) - node T_2705 = and(T_688, updatePageHit) - node T_2706 = and(T_693, updatePageHit) - node T_2707 = and(T_698, updatePageHit) - node T_2708 = and(T_703, updatePageHit) - node T_2709 = and(T_708, updatePageHit) - node T_2710 = and(T_713, updatePageHit) - node T_2711 = and(T_718, updatePageHit) - node T_2712 = and(T_723, updatePageHit) - node T_2713 = and(T_728, updatePageHit) - node T_2714 = and(T_733, updatePageHit) - node T_2715 = and(T_738, updatePageHit) - node T_2716 = and(T_743, updatePageHit) - node T_2717 = and(T_748, updatePageHit) - node T_2718 = and(T_753, updatePageHit) - node T_2719 = and(T_758, updatePageHit) - node T_2720 = and(T_763, updatePageHit) - node T_2721 = and(T_768, updatePageHit) - node T_2722 = and(T_773, updatePageHit) - node T_2723 = and(T_778, updatePageHit) - node T_2724 = and(T_783, updatePageHit) - node T_2725 = and(T_788, updatePageHit) - node T_2726 = and(T_793, updatePageHit) - node T_2727 = and(T_798, updatePageHit) - node T_2728 = and(T_803, updatePageHit) - node T_2729 = and(T_808, updatePageHit) - node T_2730 = and(T_813, updatePageHit) - node T_2731 = and(T_818, updatePageHit) - node T_2732 = and(T_823, updatePageHit) - node T_2733 = and(T_828, updatePageHit) - node T_2734 = and(T_833, updatePageHit) - node T_2735 = and(T_838, updatePageHit) - node T_2736 = and(T_843, updatePageHit) - node T_2737 = and(T_848, updatePageHit) - node T_2738 = and(T_853, updatePageHit) - node T_2739 = and(T_858, updatePageHit) - node T_2740 = and(T_863, updatePageHit) - node T_2741 = and(T_868, updatePageHit) - node T_2742 = and(T_873, updatePageHit) - node T_2743 = and(T_878, updatePageHit) - node T_2744 = and(T_883, updatePageHit) - node T_2745 = and(T_888, updatePageHit) - node T_2746 = and(T_893, updatePageHit) - node T_2747 = and(T_898, updatePageHit) - node T_2749 = neq(T_2686, UInt<1>("h00")) - node T_2751 = neq(T_2687, UInt<1>("h00")) - node T_2753 = neq(T_2688, UInt<1>("h00")) - node T_2755 = neq(T_2689, UInt<1>("h00")) - node T_2757 = neq(T_2690, UInt<1>("h00")) - node T_2759 = neq(T_2691, UInt<1>("h00")) - node T_2761 = neq(T_2692, UInt<1>("h00")) - node T_2763 = neq(T_2693, UInt<1>("h00")) - node T_2765 = neq(T_2694, UInt<1>("h00")) - node T_2767 = neq(T_2695, UInt<1>("h00")) - node T_2769 = neq(T_2696, UInt<1>("h00")) - node T_2771 = neq(T_2697, UInt<1>("h00")) - node T_2773 = neq(T_2698, UInt<1>("h00")) - node T_2775 = neq(T_2699, UInt<1>("h00")) - node T_2777 = neq(T_2700, UInt<1>("h00")) - node T_2779 = neq(T_2701, UInt<1>("h00")) - node T_2781 = neq(T_2702, UInt<1>("h00")) - node T_2783 = neq(T_2703, UInt<1>("h00")) - node T_2785 = neq(T_2704, UInt<1>("h00")) - node T_2787 = neq(T_2705, UInt<1>("h00")) - node T_2789 = neq(T_2706, UInt<1>("h00")) - node T_2791 = neq(T_2707, UInt<1>("h00")) - node T_2793 = neq(T_2708, UInt<1>("h00")) - node T_2795 = neq(T_2709, UInt<1>("h00")) - node T_2797 = neq(T_2710, UInt<1>("h00")) - node T_2799 = neq(T_2711, UInt<1>("h00")) - node T_2801 = neq(T_2712, UInt<1>("h00")) - node T_2803 = neq(T_2713, UInt<1>("h00")) - node T_2805 = neq(T_2714, UInt<1>("h00")) - node T_2807 = neq(T_2715, UInt<1>("h00")) - node T_2809 = neq(T_2716, UInt<1>("h00")) - node T_2811 = neq(T_2717, UInt<1>("h00")) - node T_2813 = neq(T_2718, UInt<1>("h00")) - node T_2815 = neq(T_2719, UInt<1>("h00")) - node T_2817 = neq(T_2720, UInt<1>("h00")) - node T_2819 = neq(T_2721, UInt<1>("h00")) - node T_2821 = neq(T_2722, UInt<1>("h00")) - node T_2823 = neq(T_2723, UInt<1>("h00")) - node T_2825 = neq(T_2724, UInt<1>("h00")) - node T_2827 = neq(T_2725, UInt<1>("h00")) - node T_2829 = neq(T_2726, UInt<1>("h00")) - node T_2831 = neq(T_2727, UInt<1>("h00")) - node T_2833 = neq(T_2728, UInt<1>("h00")) - node T_2835 = neq(T_2729, UInt<1>("h00")) - node T_2837 = neq(T_2730, UInt<1>("h00")) - node T_2839 = neq(T_2731, UInt<1>("h00")) - node T_2841 = neq(T_2732, UInt<1>("h00")) - node T_2843 = neq(T_2733, UInt<1>("h00")) - node T_2845 = neq(T_2734, UInt<1>("h00")) - node T_2847 = neq(T_2735, UInt<1>("h00")) - node T_2849 = neq(T_2736, UInt<1>("h00")) - node T_2851 = neq(T_2737, UInt<1>("h00")) - node T_2853 = neq(T_2738, UInt<1>("h00")) - node T_2855 = neq(T_2739, UInt<1>("h00")) - node T_2857 = neq(T_2740, UInt<1>("h00")) - node T_2859 = neq(T_2741, UInt<1>("h00")) - node T_2861 = neq(T_2742, UInt<1>("h00")) - node T_2863 = neq(T_2743, UInt<1>("h00")) - node T_2865 = neq(T_2744, UInt<1>("h00")) - node T_2867 = neq(T_2745, UInt<1>("h00")) - node T_2869 = neq(T_2746, UInt<1>("h00")) - node T_2871 = neq(T_2747, UInt<1>("h00")) - wire T_2873 : UInt<1>[62] - T_2873[0] <= T_2749 - T_2873[1] <= T_2751 - T_2873[2] <= T_2753 - T_2873[3] <= T_2755 - T_2873[4] <= T_2757 - T_2873[5] <= T_2759 - T_2873[6] <= T_2761 - T_2873[7] <= T_2763 - T_2873[8] <= T_2765 - T_2873[9] <= T_2767 - T_2873[10] <= T_2769 - T_2873[11] <= T_2771 - T_2873[12] <= T_2773 - T_2873[13] <= T_2775 - T_2873[14] <= T_2777 - T_2873[15] <= T_2779 - T_2873[16] <= T_2781 - T_2873[17] <= T_2783 - T_2873[18] <= T_2785 - T_2873[19] <= T_2787 - T_2873[20] <= T_2789 - T_2873[21] <= T_2791 - T_2873[22] <= T_2793 - T_2873[23] <= T_2795 - T_2873[24] <= T_2797 - T_2873[25] <= T_2799 - T_2873[26] <= T_2801 - T_2873[27] <= T_2803 - T_2873[28] <= T_2805 - T_2873[29] <= T_2807 - T_2873[30] <= T_2809 - T_2873[31] <= T_2811 - T_2873[32] <= T_2813 - T_2873[33] <= T_2815 - T_2873[34] <= T_2817 - T_2873[35] <= T_2819 - T_2873[36] <= T_2821 - T_2873[37] <= T_2823 - T_2873[38] <= T_2825 - T_2873[39] <= T_2827 - T_2873[40] <= T_2829 - T_2873[41] <= T_2831 - T_2873[42] <= T_2833 - T_2873[43] <= T_2835 - T_2873[44] <= T_2837 - T_2873[45] <= T_2839 - T_2873[46] <= T_2841 - T_2873[47] <= T_2843 - T_2873[48] <= T_2845 - T_2873[49] <= T_2847 - T_2873[50] <= T_2849 - T_2873[51] <= T_2851 - T_2873[52] <= T_2853 - T_2873[53] <= T_2855 - T_2873[54] <= T_2857 - T_2873[55] <= T_2859 - T_2873[56] <= T_2861 - T_2873[57] <= T_2863 - T_2873[58] <= T_2865 - T_2873[59] <= T_2867 - T_2873[60] <= T_2869 - T_2873[61] <= T_2871 - node T_2937 = cat(T_2873[60], T_2873[59]) - node T_2938 = cat(T_2873[61], T_2937) - node T_2939 = cat(T_2873[58], T_2873[57]) - node T_2940 = cat(T_2873[56], T_2873[55]) + node T_2669 = cat(T_2653, T_2668) + node T_2670 = cat(T_2639, T_2669) + node T_2671 = and(T_593, updatePageHit) + node T_2672 = and(T_598, updatePageHit) + node T_2673 = and(T_603, updatePageHit) + node T_2674 = and(T_608, updatePageHit) + node T_2675 = and(T_613, updatePageHit) + node T_2676 = and(T_618, updatePageHit) + node T_2677 = and(T_623, updatePageHit) + node T_2678 = and(T_628, updatePageHit) + node T_2679 = and(T_633, updatePageHit) + node T_2680 = and(T_638, updatePageHit) + node T_2681 = and(T_643, updatePageHit) + node T_2682 = and(T_648, updatePageHit) + node T_2683 = and(T_653, updatePageHit) + node T_2684 = and(T_658, updatePageHit) + node T_2685 = and(T_663, updatePageHit) + node T_2686 = and(T_668, updatePageHit) + node T_2687 = and(T_673, updatePageHit) + node T_2688 = and(T_678, updatePageHit) + node T_2689 = and(T_683, updatePageHit) + node T_2690 = and(T_688, updatePageHit) + node T_2691 = and(T_693, updatePageHit) + node T_2692 = and(T_698, updatePageHit) + node T_2693 = and(T_703, updatePageHit) + node T_2694 = and(T_708, updatePageHit) + node T_2695 = and(T_713, updatePageHit) + node T_2696 = and(T_718, updatePageHit) + node T_2697 = and(T_723, updatePageHit) + node T_2698 = and(T_728, updatePageHit) + node T_2699 = and(T_733, updatePageHit) + node T_2700 = and(T_738, updatePageHit) + node T_2701 = and(T_743, updatePageHit) + node T_2702 = and(T_748, updatePageHit) + node T_2703 = and(T_753, updatePageHit) + node T_2704 = and(T_758, updatePageHit) + node T_2705 = and(T_763, updatePageHit) + node T_2706 = and(T_768, updatePageHit) + node T_2707 = and(T_773, updatePageHit) + node T_2708 = and(T_778, updatePageHit) + node T_2709 = and(T_783, updatePageHit) + node T_2710 = and(T_788, updatePageHit) + node T_2711 = and(T_793, updatePageHit) + node T_2712 = and(T_798, updatePageHit) + node T_2713 = and(T_803, updatePageHit) + node T_2714 = and(T_808, updatePageHit) + node T_2715 = and(T_813, updatePageHit) + node T_2716 = and(T_818, updatePageHit) + node T_2717 = and(T_823, updatePageHit) + node T_2718 = and(T_828, updatePageHit) + node T_2719 = and(T_833, updatePageHit) + node T_2720 = and(T_838, updatePageHit) + node T_2721 = and(T_843, updatePageHit) + node T_2722 = and(T_848, updatePageHit) + node T_2723 = and(T_853, updatePageHit) + node T_2724 = and(T_858, updatePageHit) + node T_2725 = and(T_863, updatePageHit) + node T_2726 = and(T_868, updatePageHit) + node T_2727 = and(T_873, updatePageHit) + node T_2728 = and(T_878, updatePageHit) + node T_2729 = and(T_883, updatePageHit) + node T_2730 = and(T_888, updatePageHit) + node T_2731 = and(T_893, updatePageHit) + node T_2732 = and(T_898, updatePageHit) + node T_2734 = neq(T_2671, UInt<1>("h00")) + node T_2736 = neq(T_2672, UInt<1>("h00")) + node T_2738 = neq(T_2673, UInt<1>("h00")) + node T_2740 = neq(T_2674, UInt<1>("h00")) + node T_2742 = neq(T_2675, UInt<1>("h00")) + node T_2744 = neq(T_2676, UInt<1>("h00")) + node T_2746 = neq(T_2677, UInt<1>("h00")) + node T_2748 = neq(T_2678, UInt<1>("h00")) + node T_2750 = neq(T_2679, UInt<1>("h00")) + node T_2752 = neq(T_2680, UInt<1>("h00")) + node T_2754 = neq(T_2681, UInt<1>("h00")) + node T_2756 = neq(T_2682, UInt<1>("h00")) + node T_2758 = neq(T_2683, UInt<1>("h00")) + node T_2760 = neq(T_2684, UInt<1>("h00")) + node T_2762 = neq(T_2685, UInt<1>("h00")) + node T_2764 = neq(T_2686, UInt<1>("h00")) + node T_2766 = neq(T_2687, UInt<1>("h00")) + node T_2768 = neq(T_2688, UInt<1>("h00")) + node T_2770 = neq(T_2689, UInt<1>("h00")) + node T_2772 = neq(T_2690, UInt<1>("h00")) + node T_2774 = neq(T_2691, UInt<1>("h00")) + node T_2776 = neq(T_2692, UInt<1>("h00")) + node T_2778 = neq(T_2693, UInt<1>("h00")) + node T_2780 = neq(T_2694, UInt<1>("h00")) + node T_2782 = neq(T_2695, UInt<1>("h00")) + node T_2784 = neq(T_2696, UInt<1>("h00")) + node T_2786 = neq(T_2697, UInt<1>("h00")) + node T_2788 = neq(T_2698, UInt<1>("h00")) + node T_2790 = neq(T_2699, UInt<1>("h00")) + node T_2792 = neq(T_2700, UInt<1>("h00")) + node T_2794 = neq(T_2701, UInt<1>("h00")) + node T_2796 = neq(T_2702, UInt<1>("h00")) + node T_2798 = neq(T_2703, UInt<1>("h00")) + node T_2800 = neq(T_2704, UInt<1>("h00")) + node T_2802 = neq(T_2705, UInt<1>("h00")) + node T_2804 = neq(T_2706, UInt<1>("h00")) + node T_2806 = neq(T_2707, UInt<1>("h00")) + node T_2808 = neq(T_2708, UInt<1>("h00")) + node T_2810 = neq(T_2709, UInt<1>("h00")) + node T_2812 = neq(T_2710, UInt<1>("h00")) + node T_2814 = neq(T_2711, UInt<1>("h00")) + node T_2816 = neq(T_2712, UInt<1>("h00")) + node T_2818 = neq(T_2713, UInt<1>("h00")) + node T_2820 = neq(T_2714, UInt<1>("h00")) + node T_2822 = neq(T_2715, UInt<1>("h00")) + node T_2824 = neq(T_2716, UInt<1>("h00")) + node T_2826 = neq(T_2717, UInt<1>("h00")) + node T_2828 = neq(T_2718, UInt<1>("h00")) + node T_2830 = neq(T_2719, UInt<1>("h00")) + node T_2832 = neq(T_2720, UInt<1>("h00")) + node T_2834 = neq(T_2721, UInt<1>("h00")) + node T_2836 = neq(T_2722, UInt<1>("h00")) + node T_2838 = neq(T_2723, UInt<1>("h00")) + node T_2840 = neq(T_2724, UInt<1>("h00")) + node T_2842 = neq(T_2725, UInt<1>("h00")) + node T_2844 = neq(T_2726, UInt<1>("h00")) + node T_2846 = neq(T_2727, UInt<1>("h00")) + node T_2848 = neq(T_2728, UInt<1>("h00")) + node T_2850 = neq(T_2729, UInt<1>("h00")) + node T_2852 = neq(T_2730, UInt<1>("h00")) + node T_2854 = neq(T_2731, UInt<1>("h00")) + node T_2856 = neq(T_2732, UInt<1>("h00")) + wire T_2858 : UInt<1>[62] + T_2858[0] <= T_2734 + T_2858[1] <= T_2736 + T_2858[2] <= T_2738 + T_2858[3] <= T_2740 + T_2858[4] <= T_2742 + T_2858[5] <= T_2744 + T_2858[6] <= T_2746 + T_2858[7] <= T_2748 + T_2858[8] <= T_2750 + T_2858[9] <= T_2752 + T_2858[10] <= T_2754 + T_2858[11] <= T_2756 + T_2858[12] <= T_2758 + T_2858[13] <= T_2760 + T_2858[14] <= T_2762 + T_2858[15] <= T_2764 + T_2858[16] <= T_2766 + T_2858[17] <= T_2768 + T_2858[18] <= T_2770 + T_2858[19] <= T_2772 + T_2858[20] <= T_2774 + T_2858[21] <= T_2776 + T_2858[22] <= T_2778 + T_2858[23] <= T_2780 + T_2858[24] <= T_2782 + T_2858[25] <= T_2784 + T_2858[26] <= T_2786 + T_2858[27] <= T_2788 + T_2858[28] <= T_2790 + T_2858[29] <= T_2792 + T_2858[30] <= T_2794 + T_2858[31] <= T_2796 + T_2858[32] <= T_2798 + T_2858[33] <= T_2800 + T_2858[34] <= T_2802 + T_2858[35] <= T_2804 + T_2858[36] <= T_2806 + T_2858[37] <= T_2808 + T_2858[38] <= T_2810 + T_2858[39] <= T_2812 + T_2858[40] <= T_2814 + T_2858[41] <= T_2816 + T_2858[42] <= T_2818 + T_2858[43] <= T_2820 + T_2858[44] <= T_2822 + T_2858[45] <= T_2824 + T_2858[46] <= T_2826 + T_2858[47] <= T_2828 + T_2858[48] <= T_2830 + T_2858[49] <= T_2832 + T_2858[50] <= T_2834 + T_2858[51] <= T_2836 + T_2858[52] <= T_2838 + T_2858[53] <= T_2840 + T_2858[54] <= T_2842 + T_2858[55] <= T_2844 + T_2858[56] <= T_2846 + T_2858[57] <= T_2848 + T_2858[58] <= T_2850 + T_2858[59] <= T_2852 + T_2858[60] <= T_2854 + T_2858[61] <= T_2856 + node T_2922 = cat(T_2858[60], T_2858[59]) + node T_2923 = cat(T_2858[61], T_2922) + node T_2924 = cat(T_2858[58], T_2858[57]) + node T_2925 = cat(T_2858[56], T_2858[55]) + node T_2926 = cat(T_2924, T_2925) + node T_2927 = cat(T_2923, T_2926) + node T_2928 = cat(T_2858[54], T_2858[53]) + node T_2929 = cat(T_2858[52], T_2858[51]) + node T_2930 = cat(T_2928, T_2929) + node T_2931 = cat(T_2858[50], T_2858[49]) + node T_2932 = cat(T_2858[48], T_2858[47]) + node T_2933 = cat(T_2931, T_2932) + node T_2934 = cat(T_2930, T_2933) + node T_2935 = cat(T_2927, T_2934) + node T_2936 = cat(T_2858[46], T_2858[45]) + node T_2937 = cat(T_2858[44], T_2858[43]) + node T_2938 = cat(T_2936, T_2937) + node T_2939 = cat(T_2858[42], T_2858[41]) + node T_2940 = cat(T_2858[40], T_2858[39]) node T_2941 = cat(T_2939, T_2940) node T_2942 = cat(T_2938, T_2941) - node T_2943 = cat(T_2873[54], T_2873[53]) - node T_2944 = cat(T_2873[52], T_2873[51]) + node T_2943 = cat(T_2858[38], T_2858[37]) + node T_2944 = cat(T_2858[36], T_2858[35]) node T_2945 = cat(T_2943, T_2944) - node T_2946 = cat(T_2873[50], T_2873[49]) - node T_2947 = cat(T_2873[48], T_2873[47]) + node T_2946 = cat(T_2858[34], T_2858[33]) + node T_2947 = cat(T_2858[32], T_2858[31]) node T_2948 = cat(T_2946, T_2947) node T_2949 = cat(T_2945, T_2948) node T_2950 = cat(T_2942, T_2949) - node T_2951 = cat(T_2873[46], T_2873[45]) - node T_2952 = cat(T_2873[44], T_2873[43]) - node T_2953 = cat(T_2951, T_2952) - node T_2954 = cat(T_2873[42], T_2873[41]) - node T_2955 = cat(T_2873[40], T_2873[39]) + node T_2951 = cat(T_2935, T_2950) + node T_2952 = cat(T_2858[29], T_2858[28]) + node T_2953 = cat(T_2858[30], T_2952) + node T_2954 = cat(T_2858[27], T_2858[26]) + node T_2955 = cat(T_2858[25], T_2858[24]) node T_2956 = cat(T_2954, T_2955) node T_2957 = cat(T_2953, T_2956) - node T_2958 = cat(T_2873[38], T_2873[37]) - node T_2959 = cat(T_2873[36], T_2873[35]) + node T_2958 = cat(T_2858[23], T_2858[22]) + node T_2959 = cat(T_2858[21], T_2858[20]) node T_2960 = cat(T_2958, T_2959) - node T_2961 = cat(T_2873[34], T_2873[33]) - node T_2962 = cat(T_2873[32], T_2873[31]) + node T_2961 = cat(T_2858[19], T_2858[18]) + node T_2962 = cat(T_2858[17], T_2858[16]) node T_2963 = cat(T_2961, T_2962) node T_2964 = cat(T_2960, T_2963) node T_2965 = cat(T_2957, T_2964) - node T_2966 = cat(T_2950, T_2965) - node T_2967 = cat(T_2873[29], T_2873[28]) - node T_2968 = cat(T_2873[30], T_2967) - node T_2969 = cat(T_2873[27], T_2873[26]) - node T_2970 = cat(T_2873[25], T_2873[24]) + node T_2966 = cat(T_2858[15], T_2858[14]) + node T_2967 = cat(T_2858[13], T_2858[12]) + node T_2968 = cat(T_2966, T_2967) + node T_2969 = cat(T_2858[11], T_2858[10]) + node T_2970 = cat(T_2858[9], T_2858[8]) node T_2971 = cat(T_2969, T_2970) node T_2972 = cat(T_2968, T_2971) - node T_2973 = cat(T_2873[23], T_2873[22]) - node T_2974 = cat(T_2873[21], T_2873[20]) + node T_2973 = cat(T_2858[7], T_2858[6]) + node T_2974 = cat(T_2858[5], T_2858[4]) node T_2975 = cat(T_2973, T_2974) - node T_2976 = cat(T_2873[19], T_2873[18]) - node T_2977 = cat(T_2873[17], T_2873[16]) + node T_2976 = cat(T_2858[3], T_2858[2]) + node T_2977 = cat(T_2858[1], T_2858[0]) node T_2978 = cat(T_2976, T_2977) node T_2979 = cat(T_2975, T_2978) node T_2980 = cat(T_2972, T_2979) - node T_2981 = cat(T_2873[15], T_2873[14]) - node T_2982 = cat(T_2873[13], T_2873[12]) - node T_2983 = cat(T_2981, T_2982) - node T_2984 = cat(T_2873[11], T_2873[10]) - node T_2985 = cat(T_2873[9], T_2873[8]) - node T_2986 = cat(T_2984, T_2985) - node T_2987 = cat(T_2983, T_2986) - node T_2988 = cat(T_2873[7], T_2873[6]) - node T_2989 = cat(T_2873[5], T_2873[4]) - node T_2990 = cat(T_2988, T_2989) - node T_2991 = cat(T_2873[3], T_2873[2]) - node T_2992 = cat(T_2873[1], T_2873[0]) - node T_2993 = cat(T_2991, T_2992) - node T_2994 = cat(T_2990, T_2993) - node T_2995 = cat(T_2987, T_2994) - node T_2996 = cat(T_2980, T_2995) - node T_2997 = cat(T_2966, T_2996) - node T_2998 = and(idxValid, T_2685) - node updateHits = and(T_2998, T_2997) - reg T_3001 : UInt<16>, clk, reset, UInt<16>("h01") + node T_2981 = cat(T_2965, T_2980) + node T_2982 = cat(T_2951, T_2981) + node T_2983 = and(idxValid, T_2670) + node updateHits = and(T_2983, T_2982) + reg T_2986 : UInt<16>, clk with : (reset => (reset, UInt<16>("h01"))) when r_btb_update.valid : - node T_3002 = bit(T_3001, 0) - node T_3003 = bit(T_3001, 2) - node T_3004 = xor(T_3002, T_3003) - node T_3005 = bit(T_3001, 3) - node T_3006 = xor(T_3004, T_3005) - node T_3007 = bit(T_3001, 5) - node T_3008 = xor(T_3006, T_3007) - node T_3009 = bits(T_3001, 15, 1) - node T_3010 = cat(T_3008, T_3009) - T_3001 <= T_3010 - skip - node T_3012 = eq(r_btb_update.bits.prediction.valid, UInt<1>("h00")) - node T_3013 = and(r_btb_update.valid, T_3012) - reg nextRepl : UInt<6>, clk, reset, UInt<6>("h00") - when T_3013 : - node T_3017 = eq(nextRepl, UInt<6>("h03d")) - node T_3019 = and(UInt<1>("h01"), T_3017) - node T_3022 = addw(nextRepl, UInt<1>("h01")) - node T_3023 = mux(T_3019, UInt<1>("h00"), T_3022) - nextRepl <= T_3023 - skip - node T_3024 = and(T_3013, T_3017) + node T_2987 = bits(T_2986, 0, 0) + node T_2988 = bits(T_2986, 2, 2) + node T_2989 = xor(T_2987, T_2988) + node T_2990 = bits(T_2986, 3, 3) + node T_2991 = xor(T_2989, T_2990) + node T_2992 = bits(T_2986, 5, 5) + node T_2993 = xor(T_2991, T_2992) + node T_2994 = bits(T_2986, 15, 1) + node T_2995 = cat(T_2993, T_2994) + T_2986 <= T_2995 + skip + node T_2997 = eq(r_btb_update.bits.prediction.valid, UInt<1>("h00")) + node T_2998 = and(r_btb_update.valid, T_2997) + reg nextRepl : UInt<6>, clk with : (reset => (reset, UInt<6>("h00"))) + when T_2998 : + node T_3002 = eq(nextRepl, UInt<6>("h03d")) + node T_3004 = and(UInt<1>("h01"), T_3002) + node T_3007 = add(nextRepl, UInt<1>("h01")) + node T_3008 = tail(T_3007, 1) + node T_3009 = mux(T_3004, UInt<1>("h00"), T_3008) + nextRepl <= T_3009 + skip + node T_3010 = and(T_2998, T_3002) node useUpdatePageHit = neq(updatePageHit, UInt<1>("h00")) node doIdxPageRepl = eq(useUpdatePageHit, UInt<1>("h00")) wire idxPageRepl : UInt<6> - idxPageRepl <= UInt<1>("h00") + idxPageRepl is invalid node idxPageUpdateOH = mux(useUpdatePageHit, updatePageHit, idxPageRepl) - node T_3033 = bits(idxPageUpdateOH, 5, 4) - node T_3034 = bits(idxPageUpdateOH, 3, 0) - node T_3036 = neq(T_3033, UInt<1>("h00")) - node T_3037 = or(T_3033, T_3034) - node T_3038 = bits(T_3037, 3, 2) - node T_3039 = bits(T_3037, 1, 0) - node T_3041 = neq(T_3038, UInt<1>("h00")) - node T_3042 = or(T_3038, T_3039) - node T_3043 = bit(T_3042, 1) - node T_3044 = cat(T_3041, T_3043) - node idxPageUpdate = cat(T_3036, T_3044) + node T_3018 = bits(idxPageUpdateOH, 5, 4) + node T_3019 = bits(idxPageUpdateOH, 3, 0) + node T_3021 = neq(T_3018, UInt<1>("h00")) + node T_3022 = or(T_3018, T_3019) + node T_3023 = bits(T_3022, 3, 2) + node T_3024 = bits(T_3022, 1, 0) + node T_3026 = neq(T_3023, UInt<1>("h00")) + node T_3027 = or(T_3023, T_3024) + node T_3028 = bits(T_3027, 1, 1) + node T_3029 = cat(T_3026, T_3028) + node idxPageUpdate = cat(T_3021, T_3029) node idxPageReplEn = mux(doIdxPageRepl, idxPageRepl, UInt<1>("h00")) - node T_3048 = shr(r_btb_update.bits.pc, 12) - node T_3049 = shr(io.req.bits.addr, 12) - node samePage = eq(T_3048, T_3049) - node T_3051 = not(idxPageReplEn) - node T_3052 = and(pageHit, T_3051) - node usePageHit = neq(T_3052, UInt<1>("h00")) - node T_3056 = eq(samePage, UInt<1>("h00")) - node T_3058 = eq(usePageHit, UInt<1>("h00")) - node doTgtPageRepl = and(T_3056, T_3058) - node T_3060 = bits(idxPageUpdateOH, 4, 0) - node T_3061 = shl(T_3060, 1) - node T_3062 = bit(idxPageUpdateOH, 5) - node T_3063 = or(T_3061, T_3062) - node tgtPageRepl = mux(samePage, idxPageUpdateOH, T_3063) - node T_3065 = mux(usePageHit, pageHit, tgtPageRepl) - node T_3066 = bits(T_3065, 5, 4) - node T_3067 = bits(T_3065, 3, 0) - node T_3069 = neq(T_3066, UInt<1>("h00")) - node T_3070 = or(T_3066, T_3067) - node T_3071 = bits(T_3070, 3, 2) - node T_3072 = bits(T_3070, 1, 0) - node T_3074 = neq(T_3071, UInt<1>("h00")) - node T_3075 = or(T_3071, T_3072) - node T_3076 = bit(T_3075, 1) - node T_3077 = cat(T_3074, T_3076) - node tgtPageUpdate = cat(T_3069, T_3077) + node T_3033 = shr(r_btb_update.bits.pc, 12) + node T_3034 = shr(io.req.bits.addr, 12) + node samePage = eq(T_3033, T_3034) + node T_3036 = not(idxPageReplEn) + node T_3037 = and(pageHit, T_3036) + node usePageHit = neq(T_3037, UInt<1>("h00")) + node T_3041 = eq(samePage, UInt<1>("h00")) + node T_3043 = eq(usePageHit, UInt<1>("h00")) + node doTgtPageRepl = and(T_3041, T_3043) + node T_3045 = bits(idxPageUpdateOH, 4, 0) + node T_3046 = shl(T_3045, 1) + node T_3047 = bits(idxPageUpdateOH, 5, 5) + node T_3048 = or(T_3046, T_3047) + node tgtPageRepl = mux(samePage, idxPageUpdateOH, T_3048) + node T_3050 = mux(usePageHit, pageHit, tgtPageRepl) + node T_3051 = bits(T_3050, 5, 4) + node T_3052 = bits(T_3050, 3, 0) + node T_3054 = neq(T_3051, UInt<1>("h00")) + node T_3055 = or(T_3051, T_3052) + node T_3056 = bits(T_3055, 3, 2) + node T_3057 = bits(T_3055, 1, 0) + node T_3059 = neq(T_3056, UInt<1>("h00")) + node T_3060 = or(T_3056, T_3057) + node T_3061 = bits(T_3060, 1, 1) + node T_3062 = cat(T_3059, T_3061) + node tgtPageUpdate = cat(T_3054, T_3062) node tgtPageReplEn = mux(doTgtPageRepl, tgtPageRepl, UInt<1>("h00")) node doPageRepl = or(doIdxPageRepl, doTgtPageRepl) node pageReplEn = or(idxPageReplEn, tgtPageReplEn) - node T_3083 = and(r_btb_update.valid, doPageRepl) - reg T_3085 : UInt<3>, clk, reset, UInt<3>("h00") - when T_3083 : - node T_3087 = eq(T_3085, UInt<3>("h05")) - node T_3089 = and(UInt<1>("h01"), T_3087) - node T_3092 = addw(T_3085, UInt<1>("h01")) - node T_3093 = mux(T_3089, UInt<1>("h00"), T_3092) - T_3085 <= T_3093 - skip - node T_3094 = and(T_3083, T_3087) - node T_3096 = dshl(UInt<1>("h01"), T_3085) - idxPageRepl <= T_3096 + node T_3068 = and(r_btb_update.valid, doPageRepl) + reg T_3070 : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + when T_3068 : + node T_3072 = eq(T_3070, UInt<3>("h05")) + node T_3074 = and(UInt<1>("h01"), T_3072) + node T_3077 = add(T_3070, UInt<1>("h01")) + node T_3078 = tail(T_3077, 1) + node T_3079 = mux(T_3074, UInt<1>("h00"), T_3078) + T_3070 <= T_3079 + skip + node T_3080 = and(T_3068, T_3072) + node T_3082 = dshl(UInt<1>("h01"), T_3070) + idxPageRepl <= T_3082 when r_btb_update.valid : - node T_3097 = eq(io.req.bits.addr, r_btb_update.bits.target) - node T_3099 = eq(reset, UInt<1>("h00")) - when T_3099 : - node T_3101 = eq(T_3097, UInt<1>("h00")) - when T_3101 : - node T_3103 = eq(reset, UInt<1>("h00")) - when T_3103 : + node T_3083 = eq(io.req.bits.addr, r_btb_update.bits.target) + node T_3085 = eq(reset, UInt<1>("h00")) + when T_3085 : + node T_3087 = eq(T_3083, UInt<1>("h00")) + when T_3087 : + node T_3089 = eq(reset, UInt<1>("h00")) + when T_3089 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): BTB request != I$ target") skip stop(clk, UInt<1>(1), 1) skip skip - node T_3104 = mux(r_btb_update.bits.prediction.valid, r_btb_update.bits.prediction.bits.entry, nextRepl) - node T_3105 = or(T_593, T_903) - node T_3106 = and(pageReplEn, T_3105) - node T_3108 = neq(T_3106, UInt<1>("h00")) - node T_3109 = or(T_598, T_908) - node T_3110 = and(pageReplEn, T_3109) - node T_3112 = neq(T_3110, UInt<1>("h00")) - node T_3113 = or(T_603, T_913) - node T_3114 = and(pageReplEn, T_3113) - node T_3116 = neq(T_3114, UInt<1>("h00")) - node T_3117 = or(T_608, T_918) - node T_3118 = and(pageReplEn, T_3117) - node T_3120 = neq(T_3118, UInt<1>("h00")) - node T_3121 = or(T_613, T_923) - node T_3122 = and(pageReplEn, T_3121) - node T_3124 = neq(T_3122, UInt<1>("h00")) - node T_3125 = or(T_618, T_928) - node T_3126 = and(pageReplEn, T_3125) - node T_3128 = neq(T_3126, UInt<1>("h00")) - node T_3129 = or(T_623, T_933) - node T_3130 = and(pageReplEn, T_3129) - node T_3132 = neq(T_3130, UInt<1>("h00")) - node T_3133 = or(T_628, T_938) - node T_3134 = and(pageReplEn, T_3133) - node T_3136 = neq(T_3134, UInt<1>("h00")) - node T_3137 = or(T_633, T_943) - node T_3138 = and(pageReplEn, T_3137) - node T_3140 = neq(T_3138, UInt<1>("h00")) - node T_3141 = or(T_638, T_948) - node T_3142 = and(pageReplEn, T_3141) - node T_3144 = neq(T_3142, UInt<1>("h00")) - node T_3145 = or(T_643, T_953) - node T_3146 = and(pageReplEn, T_3145) - node T_3148 = neq(T_3146, UInt<1>("h00")) - node T_3149 = or(T_648, T_958) - node T_3150 = and(pageReplEn, T_3149) - node T_3152 = neq(T_3150, UInt<1>("h00")) - node T_3153 = or(T_653, T_963) - node T_3154 = and(pageReplEn, T_3153) - node T_3156 = neq(T_3154, UInt<1>("h00")) - node T_3157 = or(T_658, T_968) - node T_3158 = and(pageReplEn, T_3157) - node T_3160 = neq(T_3158, UInt<1>("h00")) - node T_3161 = or(T_663, T_973) - node T_3162 = and(pageReplEn, T_3161) - node T_3164 = neq(T_3162, UInt<1>("h00")) - node T_3165 = or(T_668, T_978) - node T_3166 = and(pageReplEn, T_3165) - node T_3168 = neq(T_3166, UInt<1>("h00")) - node T_3169 = or(T_673, T_983) - node T_3170 = and(pageReplEn, T_3169) - node T_3172 = neq(T_3170, UInt<1>("h00")) - node T_3173 = or(T_678, T_988) - node T_3174 = and(pageReplEn, T_3173) - node T_3176 = neq(T_3174, UInt<1>("h00")) - node T_3177 = or(T_683, T_993) - node T_3178 = and(pageReplEn, T_3177) - node T_3180 = neq(T_3178, UInt<1>("h00")) - node T_3181 = or(T_688, T_998) - node T_3182 = and(pageReplEn, T_3181) - node T_3184 = neq(T_3182, UInt<1>("h00")) - node T_3185 = or(T_693, T_1003) - node T_3186 = and(pageReplEn, T_3185) - node T_3188 = neq(T_3186, UInt<1>("h00")) - node T_3189 = or(T_698, T_1008) - node T_3190 = and(pageReplEn, T_3189) - node T_3192 = neq(T_3190, UInt<1>("h00")) - node T_3193 = or(T_703, T_1013) - node T_3194 = and(pageReplEn, T_3193) - node T_3196 = neq(T_3194, UInt<1>("h00")) - node T_3197 = or(T_708, T_1018) - node T_3198 = and(pageReplEn, T_3197) - node T_3200 = neq(T_3198, UInt<1>("h00")) - node T_3201 = or(T_713, T_1023) - node T_3202 = and(pageReplEn, T_3201) - node T_3204 = neq(T_3202, UInt<1>("h00")) - node T_3205 = or(T_718, T_1028) - node T_3206 = and(pageReplEn, T_3205) - node T_3208 = neq(T_3206, UInt<1>("h00")) - node T_3209 = or(T_723, T_1033) - node T_3210 = and(pageReplEn, T_3209) - node T_3212 = neq(T_3210, UInt<1>("h00")) - node T_3213 = or(T_728, T_1038) - node T_3214 = and(pageReplEn, T_3213) - node T_3216 = neq(T_3214, UInt<1>("h00")) - node T_3217 = or(T_733, T_1043) - node T_3218 = and(pageReplEn, T_3217) - node T_3220 = neq(T_3218, UInt<1>("h00")) - node T_3221 = or(T_738, T_1048) - node T_3222 = and(pageReplEn, T_3221) - node T_3224 = neq(T_3222, UInt<1>("h00")) - node T_3225 = or(T_743, T_1053) - node T_3226 = and(pageReplEn, T_3225) - node T_3228 = neq(T_3226, UInt<1>("h00")) - node T_3229 = or(T_748, T_1058) - node T_3230 = and(pageReplEn, T_3229) - node T_3232 = neq(T_3230, UInt<1>("h00")) - node T_3233 = or(T_753, T_1063) - node T_3234 = and(pageReplEn, T_3233) - node T_3236 = neq(T_3234, UInt<1>("h00")) - node T_3237 = or(T_758, T_1068) - node T_3238 = and(pageReplEn, T_3237) - node T_3240 = neq(T_3238, UInt<1>("h00")) - node T_3241 = or(T_763, T_1073) - node T_3242 = and(pageReplEn, T_3241) - node T_3244 = neq(T_3242, UInt<1>("h00")) - node T_3245 = or(T_768, T_1078) - node T_3246 = and(pageReplEn, T_3245) - node T_3248 = neq(T_3246, UInt<1>("h00")) - node T_3249 = or(T_773, T_1083) - node T_3250 = and(pageReplEn, T_3249) - node T_3252 = neq(T_3250, UInt<1>("h00")) - node T_3253 = or(T_778, T_1088) - node T_3254 = and(pageReplEn, T_3253) - node T_3256 = neq(T_3254, UInt<1>("h00")) - node T_3257 = or(T_783, T_1093) - node T_3258 = and(pageReplEn, T_3257) - node T_3260 = neq(T_3258, UInt<1>("h00")) - node T_3261 = or(T_788, T_1098) - node T_3262 = and(pageReplEn, T_3261) - node T_3264 = neq(T_3262, UInt<1>("h00")) - node T_3265 = or(T_793, T_1103) - node T_3266 = and(pageReplEn, T_3265) - node T_3268 = neq(T_3266, UInt<1>("h00")) - node T_3269 = or(T_798, T_1108) - node T_3270 = and(pageReplEn, T_3269) - node T_3272 = neq(T_3270, UInt<1>("h00")) - node T_3273 = or(T_803, T_1113) - node T_3274 = and(pageReplEn, T_3273) - node T_3276 = neq(T_3274, UInt<1>("h00")) - node T_3277 = or(T_808, T_1118) - node T_3278 = and(pageReplEn, T_3277) - node T_3280 = neq(T_3278, UInt<1>("h00")) - node T_3281 = or(T_813, T_1123) - node T_3282 = and(pageReplEn, T_3281) - node T_3284 = neq(T_3282, UInt<1>("h00")) - node T_3285 = or(T_818, T_1128) - node T_3286 = and(pageReplEn, T_3285) - node T_3288 = neq(T_3286, UInt<1>("h00")) - node T_3289 = or(T_823, T_1133) - node T_3290 = and(pageReplEn, T_3289) - node T_3292 = neq(T_3290, UInt<1>("h00")) - node T_3293 = or(T_828, T_1138) - node T_3294 = and(pageReplEn, T_3293) - node T_3296 = neq(T_3294, UInt<1>("h00")) - node T_3297 = or(T_833, T_1143) - node T_3298 = and(pageReplEn, T_3297) - node T_3300 = neq(T_3298, UInt<1>("h00")) - node T_3301 = or(T_838, T_1148) - node T_3302 = and(pageReplEn, T_3301) - node T_3304 = neq(T_3302, UInt<1>("h00")) - node T_3305 = or(T_843, T_1153) - node T_3306 = and(pageReplEn, T_3305) - node T_3308 = neq(T_3306, UInt<1>("h00")) - node T_3309 = or(T_848, T_1158) - node T_3310 = and(pageReplEn, T_3309) - node T_3312 = neq(T_3310, UInt<1>("h00")) - node T_3313 = or(T_853, T_1163) - node T_3314 = and(pageReplEn, T_3313) - node T_3316 = neq(T_3314, UInt<1>("h00")) - node T_3317 = or(T_858, T_1168) - node T_3318 = and(pageReplEn, T_3317) - node T_3320 = neq(T_3318, UInt<1>("h00")) - node T_3321 = or(T_863, T_1173) - node T_3322 = and(pageReplEn, T_3321) - node T_3324 = neq(T_3322, UInt<1>("h00")) - node T_3325 = or(T_868, T_1178) - node T_3326 = and(pageReplEn, T_3325) - node T_3328 = neq(T_3326, UInt<1>("h00")) - node T_3329 = or(T_873, T_1183) - node T_3330 = and(pageReplEn, T_3329) - node T_3332 = neq(T_3330, UInt<1>("h00")) - node T_3333 = or(T_878, T_1188) - node T_3334 = and(pageReplEn, T_3333) - node T_3336 = neq(T_3334, UInt<1>("h00")) - node T_3337 = or(T_883, T_1193) - node T_3338 = and(pageReplEn, T_3337) - node T_3340 = neq(T_3338, UInt<1>("h00")) - node T_3341 = or(T_888, T_1198) - node T_3342 = and(pageReplEn, T_3341) - node T_3344 = neq(T_3342, UInt<1>("h00")) - node T_3345 = or(T_893, T_1203) - node T_3346 = and(pageReplEn, T_3345) - node T_3348 = neq(T_3346, UInt<1>("h00")) - node T_3349 = or(T_898, T_1208) - node T_3350 = and(pageReplEn, T_3349) - node T_3352 = neq(T_3350, UInt<1>("h00")) - wire T_3354 : UInt<1>[62] - T_3354[0] <= T_3108 - T_3354[1] <= T_3112 - T_3354[2] <= T_3116 - T_3354[3] <= T_3120 - T_3354[4] <= T_3124 - T_3354[5] <= T_3128 - T_3354[6] <= T_3132 - T_3354[7] <= T_3136 - T_3354[8] <= T_3140 - T_3354[9] <= T_3144 - T_3354[10] <= T_3148 - T_3354[11] <= T_3152 - T_3354[12] <= T_3156 - T_3354[13] <= T_3160 - T_3354[14] <= T_3164 - T_3354[15] <= T_3168 - T_3354[16] <= T_3172 - T_3354[17] <= T_3176 - T_3354[18] <= T_3180 - T_3354[19] <= T_3184 - T_3354[20] <= T_3188 - T_3354[21] <= T_3192 - T_3354[22] <= T_3196 - T_3354[23] <= T_3200 - T_3354[24] <= T_3204 - T_3354[25] <= T_3208 - T_3354[26] <= T_3212 - T_3354[27] <= T_3216 - T_3354[28] <= T_3220 - T_3354[29] <= T_3224 - T_3354[30] <= T_3228 - T_3354[31] <= T_3232 - T_3354[32] <= T_3236 - T_3354[33] <= T_3240 - T_3354[34] <= T_3244 - T_3354[35] <= T_3248 - T_3354[36] <= T_3252 - T_3354[37] <= T_3256 - T_3354[38] <= T_3260 - T_3354[39] <= T_3264 - T_3354[40] <= T_3268 - T_3354[41] <= T_3272 - T_3354[42] <= T_3276 - T_3354[43] <= T_3280 - T_3354[44] <= T_3284 - T_3354[45] <= T_3288 - T_3354[46] <= T_3292 - T_3354[47] <= T_3296 - T_3354[48] <= T_3300 - T_3354[49] <= T_3304 - T_3354[50] <= T_3308 - T_3354[51] <= T_3312 - T_3354[52] <= T_3316 - T_3354[53] <= T_3320 - T_3354[54] <= T_3324 - T_3354[55] <= T_3328 - T_3354[56] <= T_3332 - T_3354[57] <= T_3336 - T_3354[58] <= T_3340 - T_3354[59] <= T_3344 - T_3354[60] <= T_3348 - T_3354[61] <= T_3352 - node T_3418 = cat(T_3354[60], T_3354[59]) - node T_3419 = cat(T_3354[61], T_3418) - node T_3420 = cat(T_3354[58], T_3354[57]) - node T_3421 = cat(T_3354[56], T_3354[55]) - node T_3422 = cat(T_3420, T_3421) - node T_3423 = cat(T_3419, T_3422) - node T_3424 = cat(T_3354[54], T_3354[53]) - node T_3425 = cat(T_3354[52], T_3354[51]) - node T_3426 = cat(T_3424, T_3425) - node T_3427 = cat(T_3354[50], T_3354[49]) - node T_3428 = cat(T_3354[48], T_3354[47]) - node T_3429 = cat(T_3427, T_3428) - node T_3430 = cat(T_3426, T_3429) - node T_3431 = cat(T_3423, T_3430) - node T_3432 = cat(T_3354[46], T_3354[45]) - node T_3433 = cat(T_3354[44], T_3354[43]) - node T_3434 = cat(T_3432, T_3433) - node T_3435 = cat(T_3354[42], T_3354[41]) - node T_3436 = cat(T_3354[40], T_3354[39]) - node T_3437 = cat(T_3435, T_3436) - node T_3438 = cat(T_3434, T_3437) - node T_3439 = cat(T_3354[38], T_3354[37]) - node T_3440 = cat(T_3354[36], T_3354[35]) - node T_3441 = cat(T_3439, T_3440) - node T_3442 = cat(T_3354[34], T_3354[33]) - node T_3443 = cat(T_3354[32], T_3354[31]) - node T_3444 = cat(T_3442, T_3443) - node T_3445 = cat(T_3441, T_3444) - node T_3446 = cat(T_3438, T_3445) - node T_3447 = cat(T_3431, T_3446) - node T_3448 = cat(T_3354[29], T_3354[28]) - node T_3449 = cat(T_3354[30], T_3448) - node T_3450 = cat(T_3354[27], T_3354[26]) - node T_3451 = cat(T_3354[25], T_3354[24]) - node T_3452 = cat(T_3450, T_3451) - node T_3453 = cat(T_3449, T_3452) - node T_3454 = cat(T_3354[23], T_3354[22]) - node T_3455 = cat(T_3354[21], T_3354[20]) - node T_3456 = cat(T_3454, T_3455) - node T_3457 = cat(T_3354[19], T_3354[18]) - node T_3458 = cat(T_3354[17], T_3354[16]) - node T_3459 = cat(T_3457, T_3458) - node T_3460 = cat(T_3456, T_3459) - node T_3461 = cat(T_3453, T_3460) - node T_3462 = cat(T_3354[15], T_3354[14]) - node T_3463 = cat(T_3354[13], T_3354[12]) - node T_3464 = cat(T_3462, T_3463) - node T_3465 = cat(T_3354[11], T_3354[10]) - node T_3466 = cat(T_3354[9], T_3354[8]) - node T_3467 = cat(T_3465, T_3466) - node T_3468 = cat(T_3464, T_3467) - node T_3469 = cat(T_3354[7], T_3354[6]) - node T_3470 = cat(T_3354[5], T_3354[4]) - node T_3471 = cat(T_3469, T_3470) - node T_3472 = cat(T_3354[3], T_3354[2]) - node T_3473 = cat(T_3354[1], T_3354[0]) - node T_3474 = cat(T_3472, T_3473) - node T_3475 = cat(T_3471, T_3474) - node T_3476 = cat(T_3468, T_3475) - node T_3477 = cat(T_3461, T_3476) - node T_3478 = cat(T_3447, T_3477) - node T_3480 = dshl(UInt<1>("h01"), T_3104) - node T_3481 = not(T_3478) - node T_3482 = and(idxValid, T_3481) - node T_3483 = or(T_3482, T_3480) - idxValid <= T_3483 - infer mport T_3484 = idxs[T_3104], clk - T_3484 <= r_btb_update.bits.pc - infer mport T_3485 = tgts[T_3104], clk - T_3485 <= io.req.bits.addr - infer mport T_3486 = idxPages[T_3104], clk - T_3486 <= idxPageUpdate - infer mport T_3487 = tgtPages[T_3104], clk - T_3487 <= tgtPageUpdate - useRAS[T_3104] <= r_btb_update.bits.isReturn - isJump[T_3104] <= r_btb_update.bits.isJump - infer mport T_3490 = brIdx[T_3104], clk - T_3490 <= UInt<1>("h00") - node T_3493 = cat(UInt<2>("h01"), UInt<2>("h01")) - node T_3494 = cat(UInt<2>("h01"), T_3493) - node T_3495 = and(idxPageUpdateOH, T_3494) - node T_3497 = neq(T_3495, UInt<1>("h00")) - node T_3498 = mux(T_3497, doIdxPageRepl, doTgtPageRepl) - node T_3499 = shr(r_btb_update.bits.pc, 12) - node T_3500 = shr(io.req.bits.addr, 12) - node T_3501 = mux(T_3497, T_3499, T_3500) - node T_3502 = bit(pageReplEn, 0) - node T_3503 = and(T_3498, T_3502) - when T_3503 : - infer mport T_3505 = pages[UInt<1>("h00")], clk - T_3505 <= T_3501 - skip - node T_3506 = bit(pageReplEn, 2) - node T_3507 = and(T_3498, T_3506) - when T_3507 : - infer mport T_3509 = pages[UInt<2>("h02")], clk - T_3509 <= T_3501 - skip - node T_3510 = bit(pageReplEn, 4) - node T_3511 = and(T_3498, T_3510) - when T_3511 : - infer mport T_3513 = pages[UInt<3>("h04")], clk - T_3513 <= T_3501 - skip - node T_3514 = mux(T_3497, doTgtPageRepl, doIdxPageRepl) - node T_3515 = shr(io.req.bits.addr, 12) - node T_3516 = shr(r_btb_update.bits.pc, 12) - node T_3517 = mux(T_3497, T_3515, T_3516) - node T_3518 = bit(pageReplEn, 1) - node T_3519 = and(T_3514, T_3518) - when T_3519 : - infer mport T_3521 = pages[UInt<1>("h01")], clk - T_3521 <= T_3517 - skip - node T_3522 = bit(pageReplEn, 3) - node T_3523 = and(T_3514, T_3522) - when T_3523 : - infer mport T_3525 = pages[UInt<2>("h03")], clk - T_3525 <= T_3517 - skip - node T_3526 = bit(pageReplEn, 5) - node T_3527 = and(T_3514, T_3526) - when T_3527 : - infer mport T_3529 = pages[UInt<3>("h05")], clk - T_3529 <= T_3517 + node T_3090 = mux(r_btb_update.bits.prediction.valid, r_btb_update.bits.prediction.bits.entry, nextRepl) + node T_3091 = or(T_593, T_903) + node T_3092 = and(pageReplEn, T_3091) + node T_3094 = neq(T_3092, UInt<1>("h00")) + node T_3095 = or(T_598, T_908) + node T_3096 = and(pageReplEn, T_3095) + node T_3098 = neq(T_3096, UInt<1>("h00")) + node T_3099 = or(T_603, T_913) + node T_3100 = and(pageReplEn, T_3099) + node T_3102 = neq(T_3100, UInt<1>("h00")) + node T_3103 = or(T_608, T_918) + node T_3104 = and(pageReplEn, T_3103) + node T_3106 = neq(T_3104, UInt<1>("h00")) + node T_3107 = or(T_613, T_923) + node T_3108 = and(pageReplEn, T_3107) + node T_3110 = neq(T_3108, UInt<1>("h00")) + node T_3111 = or(T_618, T_928) + node T_3112 = and(pageReplEn, T_3111) + node T_3114 = neq(T_3112, UInt<1>("h00")) + node T_3115 = or(T_623, T_933) + node T_3116 = and(pageReplEn, T_3115) + node T_3118 = neq(T_3116, UInt<1>("h00")) + node T_3119 = or(T_628, T_938) + node T_3120 = and(pageReplEn, T_3119) + node T_3122 = neq(T_3120, UInt<1>("h00")) + node T_3123 = or(T_633, T_943) + node T_3124 = and(pageReplEn, T_3123) + node T_3126 = neq(T_3124, UInt<1>("h00")) + node T_3127 = or(T_638, T_948) + node T_3128 = and(pageReplEn, T_3127) + node T_3130 = neq(T_3128, UInt<1>("h00")) + node T_3131 = or(T_643, T_953) + node T_3132 = and(pageReplEn, T_3131) + node T_3134 = neq(T_3132, UInt<1>("h00")) + node T_3135 = or(T_648, T_958) + node T_3136 = and(pageReplEn, T_3135) + node T_3138 = neq(T_3136, UInt<1>("h00")) + node T_3139 = or(T_653, T_963) + node T_3140 = and(pageReplEn, T_3139) + node T_3142 = neq(T_3140, UInt<1>("h00")) + node T_3143 = or(T_658, T_968) + node T_3144 = and(pageReplEn, T_3143) + node T_3146 = neq(T_3144, UInt<1>("h00")) + node T_3147 = or(T_663, T_973) + node T_3148 = and(pageReplEn, T_3147) + node T_3150 = neq(T_3148, UInt<1>("h00")) + node T_3151 = or(T_668, T_978) + node T_3152 = and(pageReplEn, T_3151) + node T_3154 = neq(T_3152, UInt<1>("h00")) + node T_3155 = or(T_673, T_983) + node T_3156 = and(pageReplEn, T_3155) + node T_3158 = neq(T_3156, UInt<1>("h00")) + node T_3159 = or(T_678, T_988) + node T_3160 = and(pageReplEn, T_3159) + node T_3162 = neq(T_3160, UInt<1>("h00")) + node T_3163 = or(T_683, T_993) + node T_3164 = and(pageReplEn, T_3163) + node T_3166 = neq(T_3164, UInt<1>("h00")) + node T_3167 = or(T_688, T_998) + node T_3168 = and(pageReplEn, T_3167) + node T_3170 = neq(T_3168, UInt<1>("h00")) + node T_3171 = or(T_693, T_1003) + node T_3172 = and(pageReplEn, T_3171) + node T_3174 = neq(T_3172, UInt<1>("h00")) + node T_3175 = or(T_698, T_1008) + node T_3176 = and(pageReplEn, T_3175) + node T_3178 = neq(T_3176, UInt<1>("h00")) + node T_3179 = or(T_703, T_1013) + node T_3180 = and(pageReplEn, T_3179) + node T_3182 = neq(T_3180, UInt<1>("h00")) + node T_3183 = or(T_708, T_1018) + node T_3184 = and(pageReplEn, T_3183) + node T_3186 = neq(T_3184, UInt<1>("h00")) + node T_3187 = or(T_713, T_1023) + node T_3188 = and(pageReplEn, T_3187) + node T_3190 = neq(T_3188, UInt<1>("h00")) + node T_3191 = or(T_718, T_1028) + node T_3192 = and(pageReplEn, T_3191) + node T_3194 = neq(T_3192, UInt<1>("h00")) + node T_3195 = or(T_723, T_1033) + node T_3196 = and(pageReplEn, T_3195) + node T_3198 = neq(T_3196, UInt<1>("h00")) + node T_3199 = or(T_728, T_1038) + node T_3200 = and(pageReplEn, T_3199) + node T_3202 = neq(T_3200, UInt<1>("h00")) + node T_3203 = or(T_733, T_1043) + node T_3204 = and(pageReplEn, T_3203) + node T_3206 = neq(T_3204, UInt<1>("h00")) + node T_3207 = or(T_738, T_1048) + node T_3208 = and(pageReplEn, T_3207) + node T_3210 = neq(T_3208, UInt<1>("h00")) + node T_3211 = or(T_743, T_1053) + node T_3212 = and(pageReplEn, T_3211) + node T_3214 = neq(T_3212, UInt<1>("h00")) + node T_3215 = or(T_748, T_1058) + node T_3216 = and(pageReplEn, T_3215) + node T_3218 = neq(T_3216, UInt<1>("h00")) + node T_3219 = or(T_753, T_1063) + node T_3220 = and(pageReplEn, T_3219) + node T_3222 = neq(T_3220, UInt<1>("h00")) + node T_3223 = or(T_758, T_1068) + node T_3224 = and(pageReplEn, T_3223) + node T_3226 = neq(T_3224, UInt<1>("h00")) + node T_3227 = or(T_763, T_1073) + node T_3228 = and(pageReplEn, T_3227) + node T_3230 = neq(T_3228, UInt<1>("h00")) + node T_3231 = or(T_768, T_1078) + node T_3232 = and(pageReplEn, T_3231) + node T_3234 = neq(T_3232, UInt<1>("h00")) + node T_3235 = or(T_773, T_1083) + node T_3236 = and(pageReplEn, T_3235) + node T_3238 = neq(T_3236, UInt<1>("h00")) + node T_3239 = or(T_778, T_1088) + node T_3240 = and(pageReplEn, T_3239) + node T_3242 = neq(T_3240, UInt<1>("h00")) + node T_3243 = or(T_783, T_1093) + node T_3244 = and(pageReplEn, T_3243) + node T_3246 = neq(T_3244, UInt<1>("h00")) + node T_3247 = or(T_788, T_1098) + node T_3248 = and(pageReplEn, T_3247) + node T_3250 = neq(T_3248, UInt<1>("h00")) + node T_3251 = or(T_793, T_1103) + node T_3252 = and(pageReplEn, T_3251) + node T_3254 = neq(T_3252, UInt<1>("h00")) + node T_3255 = or(T_798, T_1108) + node T_3256 = and(pageReplEn, T_3255) + node T_3258 = neq(T_3256, UInt<1>("h00")) + node T_3259 = or(T_803, T_1113) + node T_3260 = and(pageReplEn, T_3259) + node T_3262 = neq(T_3260, UInt<1>("h00")) + node T_3263 = or(T_808, T_1118) + node T_3264 = and(pageReplEn, T_3263) + node T_3266 = neq(T_3264, UInt<1>("h00")) + node T_3267 = or(T_813, T_1123) + node T_3268 = and(pageReplEn, T_3267) + node T_3270 = neq(T_3268, UInt<1>("h00")) + node T_3271 = or(T_818, T_1128) + node T_3272 = and(pageReplEn, T_3271) + node T_3274 = neq(T_3272, UInt<1>("h00")) + node T_3275 = or(T_823, T_1133) + node T_3276 = and(pageReplEn, T_3275) + node T_3278 = neq(T_3276, UInt<1>("h00")) + node T_3279 = or(T_828, T_1138) + node T_3280 = and(pageReplEn, T_3279) + node T_3282 = neq(T_3280, UInt<1>("h00")) + node T_3283 = or(T_833, T_1143) + node T_3284 = and(pageReplEn, T_3283) + node T_3286 = neq(T_3284, UInt<1>("h00")) + node T_3287 = or(T_838, T_1148) + node T_3288 = and(pageReplEn, T_3287) + node T_3290 = neq(T_3288, UInt<1>("h00")) + node T_3291 = or(T_843, T_1153) + node T_3292 = and(pageReplEn, T_3291) + node T_3294 = neq(T_3292, UInt<1>("h00")) + node T_3295 = or(T_848, T_1158) + node T_3296 = and(pageReplEn, T_3295) + node T_3298 = neq(T_3296, UInt<1>("h00")) + node T_3299 = or(T_853, T_1163) + node T_3300 = and(pageReplEn, T_3299) + node T_3302 = neq(T_3300, UInt<1>("h00")) + node T_3303 = or(T_858, T_1168) + node T_3304 = and(pageReplEn, T_3303) + node T_3306 = neq(T_3304, UInt<1>("h00")) + node T_3307 = or(T_863, T_1173) + node T_3308 = and(pageReplEn, T_3307) + node T_3310 = neq(T_3308, UInt<1>("h00")) + node T_3311 = or(T_868, T_1178) + node T_3312 = and(pageReplEn, T_3311) + node T_3314 = neq(T_3312, UInt<1>("h00")) + node T_3315 = or(T_873, T_1183) + node T_3316 = and(pageReplEn, T_3315) + node T_3318 = neq(T_3316, UInt<1>("h00")) + node T_3319 = or(T_878, T_1188) + node T_3320 = and(pageReplEn, T_3319) + node T_3322 = neq(T_3320, UInt<1>("h00")) + node T_3323 = or(T_883, T_1193) + node T_3324 = and(pageReplEn, T_3323) + node T_3326 = neq(T_3324, UInt<1>("h00")) + node T_3327 = or(T_888, T_1198) + node T_3328 = and(pageReplEn, T_3327) + node T_3330 = neq(T_3328, UInt<1>("h00")) + node T_3331 = or(T_893, T_1203) + node T_3332 = and(pageReplEn, T_3331) + node T_3334 = neq(T_3332, UInt<1>("h00")) + node T_3335 = or(T_898, T_1208) + node T_3336 = and(pageReplEn, T_3335) + node T_3338 = neq(T_3336, UInt<1>("h00")) + wire T_3340 : UInt<1>[62] + T_3340[0] <= T_3094 + T_3340[1] <= T_3098 + T_3340[2] <= T_3102 + T_3340[3] <= T_3106 + T_3340[4] <= T_3110 + T_3340[5] <= T_3114 + T_3340[6] <= T_3118 + T_3340[7] <= T_3122 + T_3340[8] <= T_3126 + T_3340[9] <= T_3130 + T_3340[10] <= T_3134 + T_3340[11] <= T_3138 + T_3340[12] <= T_3142 + T_3340[13] <= T_3146 + T_3340[14] <= T_3150 + T_3340[15] <= T_3154 + T_3340[16] <= T_3158 + T_3340[17] <= T_3162 + T_3340[18] <= T_3166 + T_3340[19] <= T_3170 + T_3340[20] <= T_3174 + T_3340[21] <= T_3178 + T_3340[22] <= T_3182 + T_3340[23] <= T_3186 + T_3340[24] <= T_3190 + T_3340[25] <= T_3194 + T_3340[26] <= T_3198 + T_3340[27] <= T_3202 + T_3340[28] <= T_3206 + T_3340[29] <= T_3210 + T_3340[30] <= T_3214 + T_3340[31] <= T_3218 + T_3340[32] <= T_3222 + T_3340[33] <= T_3226 + T_3340[34] <= T_3230 + T_3340[35] <= T_3234 + T_3340[36] <= T_3238 + T_3340[37] <= T_3242 + T_3340[38] <= T_3246 + T_3340[39] <= T_3250 + T_3340[40] <= T_3254 + T_3340[41] <= T_3258 + T_3340[42] <= T_3262 + T_3340[43] <= T_3266 + T_3340[44] <= T_3270 + T_3340[45] <= T_3274 + T_3340[46] <= T_3278 + T_3340[47] <= T_3282 + T_3340[48] <= T_3286 + T_3340[49] <= T_3290 + T_3340[50] <= T_3294 + T_3340[51] <= T_3298 + T_3340[52] <= T_3302 + T_3340[53] <= T_3306 + T_3340[54] <= T_3310 + T_3340[55] <= T_3314 + T_3340[56] <= T_3318 + T_3340[57] <= T_3322 + T_3340[58] <= T_3326 + T_3340[59] <= T_3330 + T_3340[60] <= T_3334 + T_3340[61] <= T_3338 + node T_3404 = cat(T_3340[60], T_3340[59]) + node T_3405 = cat(T_3340[61], T_3404) + node T_3406 = cat(T_3340[58], T_3340[57]) + node T_3407 = cat(T_3340[56], T_3340[55]) + node T_3408 = cat(T_3406, T_3407) + node T_3409 = cat(T_3405, T_3408) + node T_3410 = cat(T_3340[54], T_3340[53]) + node T_3411 = cat(T_3340[52], T_3340[51]) + node T_3412 = cat(T_3410, T_3411) + node T_3413 = cat(T_3340[50], T_3340[49]) + node T_3414 = cat(T_3340[48], T_3340[47]) + node T_3415 = cat(T_3413, T_3414) + node T_3416 = cat(T_3412, T_3415) + node T_3417 = cat(T_3409, T_3416) + node T_3418 = cat(T_3340[46], T_3340[45]) + node T_3419 = cat(T_3340[44], T_3340[43]) + node T_3420 = cat(T_3418, T_3419) + node T_3421 = cat(T_3340[42], T_3340[41]) + node T_3422 = cat(T_3340[40], T_3340[39]) + node T_3423 = cat(T_3421, T_3422) + node T_3424 = cat(T_3420, T_3423) + node T_3425 = cat(T_3340[38], T_3340[37]) + node T_3426 = cat(T_3340[36], T_3340[35]) + node T_3427 = cat(T_3425, T_3426) + node T_3428 = cat(T_3340[34], T_3340[33]) + node T_3429 = cat(T_3340[32], T_3340[31]) + node T_3430 = cat(T_3428, T_3429) + node T_3431 = cat(T_3427, T_3430) + node T_3432 = cat(T_3424, T_3431) + node T_3433 = cat(T_3417, T_3432) + node T_3434 = cat(T_3340[29], T_3340[28]) + node T_3435 = cat(T_3340[30], T_3434) + node T_3436 = cat(T_3340[27], T_3340[26]) + node T_3437 = cat(T_3340[25], T_3340[24]) + node T_3438 = cat(T_3436, T_3437) + node T_3439 = cat(T_3435, T_3438) + node T_3440 = cat(T_3340[23], T_3340[22]) + node T_3441 = cat(T_3340[21], T_3340[20]) + node T_3442 = cat(T_3440, T_3441) + node T_3443 = cat(T_3340[19], T_3340[18]) + node T_3444 = cat(T_3340[17], T_3340[16]) + node T_3445 = cat(T_3443, T_3444) + node T_3446 = cat(T_3442, T_3445) + node T_3447 = cat(T_3439, T_3446) + node T_3448 = cat(T_3340[15], T_3340[14]) + node T_3449 = cat(T_3340[13], T_3340[12]) + node T_3450 = cat(T_3448, T_3449) + node T_3451 = cat(T_3340[11], T_3340[10]) + node T_3452 = cat(T_3340[9], T_3340[8]) + node T_3453 = cat(T_3451, T_3452) + node T_3454 = cat(T_3450, T_3453) + node T_3455 = cat(T_3340[7], T_3340[6]) + node T_3456 = cat(T_3340[5], T_3340[4]) + node T_3457 = cat(T_3455, T_3456) + node T_3458 = cat(T_3340[3], T_3340[2]) + node T_3459 = cat(T_3340[1], T_3340[0]) + node T_3460 = cat(T_3458, T_3459) + node T_3461 = cat(T_3457, T_3460) + node T_3462 = cat(T_3454, T_3461) + node T_3463 = cat(T_3447, T_3462) + node T_3464 = cat(T_3433, T_3463) + node T_3466 = dshl(UInt<1>("h01"), T_3090) + node T_3467 = not(T_3464) + node T_3468 = and(idxValid, T_3467) + node T_3469 = or(T_3468, T_3466) + idxValid <= T_3469 + infer mport T_3470 = idxs[T_3090], clk + T_3470 <= r_btb_update.bits.pc + infer mport T_3471 = tgts[T_3090], clk + T_3471 <= io.req.bits.addr + infer mport T_3472 = idxPages[T_3090], clk + T_3472 <= idxPageUpdate + infer mport T_3473 = tgtPages[T_3090], clk + T_3473 <= tgtPageUpdate + useRAS[T_3090] <= r_btb_update.bits.isReturn + isJump[T_3090] <= r_btb_update.bits.isJump + infer mport T_3476 = brIdx[T_3090], clk + T_3476 <= UInt<1>("h00") + node T_3479 = cat(UInt<2>("h01"), UInt<2>("h01")) + node T_3480 = cat(UInt<2>("h01"), T_3479) + node T_3481 = and(idxPageUpdateOH, T_3480) + node T_3483 = neq(T_3481, UInt<1>("h00")) + node T_3484 = mux(T_3483, doIdxPageRepl, doTgtPageRepl) + node T_3485 = shr(r_btb_update.bits.pc, 12) + node T_3486 = shr(io.req.bits.addr, 12) + node T_3487 = mux(T_3483, T_3485, T_3486) + node T_3488 = bits(pageReplEn, 0, 0) + node T_3489 = and(T_3484, T_3488) + when T_3489 : + infer mport T_3491 = pages[UInt<1>("h00")], clk + T_3491 <= T_3487 + skip + node T_3492 = bits(pageReplEn, 2, 2) + node T_3493 = and(T_3484, T_3492) + when T_3493 : + infer mport T_3495 = pages[UInt<2>("h02")], clk + T_3495 <= T_3487 + skip + node T_3496 = bits(pageReplEn, 4, 4) + node T_3497 = and(T_3484, T_3496) + when T_3497 : + infer mport T_3499 = pages[UInt<3>("h04")], clk + T_3499 <= T_3487 + skip + node T_3500 = mux(T_3483, doTgtPageRepl, doIdxPageRepl) + node T_3501 = shr(io.req.bits.addr, 12) + node T_3502 = shr(r_btb_update.bits.pc, 12) + node T_3503 = mux(T_3483, T_3501, T_3502) + node T_3504 = bits(pageReplEn, 1, 1) + node T_3505 = and(T_3500, T_3504) + when T_3505 : + infer mport T_3507 = pages[UInt<1>("h01")], clk + T_3507 <= T_3503 + skip + node T_3508 = bits(pageReplEn, 3, 3) + node T_3509 = and(T_3500, T_3508) + when T_3509 : + infer mport T_3511 = pages[UInt<2>("h03")], clk + T_3511 <= T_3503 + skip + node T_3512 = bits(pageReplEn, 5, 5) + node T_3513 = and(T_3500, T_3512) + when T_3513 : + infer mport T_3515 = pages[UInt<3>("h05")], clk + T_3515 <= T_3503 skip when doPageRepl : - node T_3530 = or(pageValid, pageReplEn) - pageValid <= T_3530 + node T_3516 = or(pageValid, pageReplEn) + pageValid <= T_3516 skip skip when io.invalidate : idxValid <= UInt<1>("h00") pageValid <= UInt<1>("h00") skip - node T_3534 = neq(hits, UInt<1>("h00")) - io.resp.valid <= T_3534 + node T_3520 = neq(hits, UInt<1>("h00")) + io.resp.valid <= T_3520 io.resp.bits.taken <= io.resp.valid - node T_3535 = bit(hits, 0) - node T_3536 = bit(hits, 1) - node T_3537 = bit(hits, 2) - node T_3538 = bit(hits, 3) - node T_3539 = bit(hits, 4) - node T_3540 = bit(hits, 5) - node T_3541 = bit(hits, 6) - node T_3542 = bit(hits, 7) - node T_3543 = bit(hits, 8) - node T_3544 = bit(hits, 9) - node T_3545 = bit(hits, 10) - node T_3546 = bit(hits, 11) - node T_3547 = bit(hits, 12) - node T_3548 = bit(hits, 13) - node T_3549 = bit(hits, 14) - node T_3550 = bit(hits, 15) - node T_3551 = bit(hits, 16) - node T_3552 = bit(hits, 17) - node T_3553 = bit(hits, 18) - node T_3554 = bit(hits, 19) - node T_3555 = bit(hits, 20) - node T_3556 = bit(hits, 21) - node T_3557 = bit(hits, 22) - node T_3558 = bit(hits, 23) - node T_3559 = bit(hits, 24) - node T_3560 = bit(hits, 25) - node T_3561 = bit(hits, 26) - node T_3562 = bit(hits, 27) - node T_3563 = bit(hits, 28) - node T_3564 = bit(hits, 29) - node T_3565 = bit(hits, 30) - node T_3566 = bit(hits, 31) - node T_3567 = bit(hits, 32) - node T_3568 = bit(hits, 33) - node T_3569 = bit(hits, 34) - node T_3570 = bit(hits, 35) - node T_3571 = bit(hits, 36) - node T_3572 = bit(hits, 37) - node T_3573 = bit(hits, 38) - node T_3574 = bit(hits, 39) - node T_3575 = bit(hits, 40) - node T_3576 = bit(hits, 41) - node T_3577 = bit(hits, 42) - node T_3578 = bit(hits, 43) - node T_3579 = bit(hits, 44) - node T_3580 = bit(hits, 45) - node T_3581 = bit(hits, 46) - node T_3582 = bit(hits, 47) - node T_3583 = bit(hits, 48) - node T_3584 = bit(hits, 49) - node T_3585 = bit(hits, 50) - node T_3586 = bit(hits, 51) - node T_3587 = bit(hits, 52) - node T_3588 = bit(hits, 53) - node T_3589 = bit(hits, 54) - node T_3590 = bit(hits, 55) - node T_3591 = bit(hits, 56) - node T_3592 = bit(hits, 57) - node T_3593 = bit(hits, 58) - node T_3594 = bit(hits, 59) - node T_3595 = bit(hits, 60) - node T_3596 = bit(hits, 61) - node T_3598 = mux(T_3535, T_903, UInt<1>("h00")) - node T_3600 = mux(T_3536, T_908, UInt<1>("h00")) - node T_3602 = mux(T_3537, T_913, UInt<1>("h00")) - node T_3604 = mux(T_3538, T_918, UInt<1>("h00")) - node T_3606 = mux(T_3539, T_923, UInt<1>("h00")) - node T_3608 = mux(T_3540, T_928, UInt<1>("h00")) - node T_3610 = mux(T_3541, T_933, UInt<1>("h00")) - node T_3612 = mux(T_3542, T_938, UInt<1>("h00")) - node T_3614 = mux(T_3543, T_943, UInt<1>("h00")) - node T_3616 = mux(T_3544, T_948, UInt<1>("h00")) - node T_3618 = mux(T_3545, T_953, UInt<1>("h00")) - node T_3620 = mux(T_3546, T_958, UInt<1>("h00")) - node T_3622 = mux(T_3547, T_963, UInt<1>("h00")) - node T_3624 = mux(T_3548, T_968, UInt<1>("h00")) - node T_3626 = mux(T_3549, T_973, UInt<1>("h00")) - node T_3628 = mux(T_3550, T_978, UInt<1>("h00")) - node T_3630 = mux(T_3551, T_983, UInt<1>("h00")) - node T_3632 = mux(T_3552, T_988, UInt<1>("h00")) - node T_3634 = mux(T_3553, T_993, UInt<1>("h00")) - node T_3636 = mux(T_3554, T_998, UInt<1>("h00")) - node T_3638 = mux(T_3555, T_1003, UInt<1>("h00")) - node T_3640 = mux(T_3556, T_1008, UInt<1>("h00")) - node T_3642 = mux(T_3557, T_1013, UInt<1>("h00")) - node T_3644 = mux(T_3558, T_1018, UInt<1>("h00")) - node T_3646 = mux(T_3559, T_1023, UInt<1>("h00")) - node T_3648 = mux(T_3560, T_1028, UInt<1>("h00")) - node T_3650 = mux(T_3561, T_1033, UInt<1>("h00")) - node T_3652 = mux(T_3562, T_1038, UInt<1>("h00")) - node T_3654 = mux(T_3563, T_1043, UInt<1>("h00")) - node T_3656 = mux(T_3564, T_1048, UInt<1>("h00")) - node T_3658 = mux(T_3565, T_1053, UInt<1>("h00")) - node T_3660 = mux(T_3566, T_1058, UInt<1>("h00")) - node T_3662 = mux(T_3567, T_1063, UInt<1>("h00")) - node T_3664 = mux(T_3568, T_1068, UInt<1>("h00")) - node T_3666 = mux(T_3569, T_1073, UInt<1>("h00")) - node T_3668 = mux(T_3570, T_1078, UInt<1>("h00")) - node T_3670 = mux(T_3571, T_1083, UInt<1>("h00")) - node T_3672 = mux(T_3572, T_1088, UInt<1>("h00")) - node T_3674 = mux(T_3573, T_1093, UInt<1>("h00")) - node T_3676 = mux(T_3574, T_1098, UInt<1>("h00")) - node T_3678 = mux(T_3575, T_1103, UInt<1>("h00")) - node T_3680 = mux(T_3576, T_1108, UInt<1>("h00")) - node T_3682 = mux(T_3577, T_1113, UInt<1>("h00")) - node T_3684 = mux(T_3578, T_1118, UInt<1>("h00")) - node T_3686 = mux(T_3579, T_1123, UInt<1>("h00")) - node T_3688 = mux(T_3580, T_1128, UInt<1>("h00")) - node T_3690 = mux(T_3581, T_1133, UInt<1>("h00")) - node T_3692 = mux(T_3582, T_1138, UInt<1>("h00")) - node T_3694 = mux(T_3583, T_1143, UInt<1>("h00")) - node T_3696 = mux(T_3584, T_1148, UInt<1>("h00")) - node T_3698 = mux(T_3585, T_1153, UInt<1>("h00")) - node T_3700 = mux(T_3586, T_1158, UInt<1>("h00")) - node T_3702 = mux(T_3587, T_1163, UInt<1>("h00")) - node T_3704 = mux(T_3588, T_1168, UInt<1>("h00")) - node T_3706 = mux(T_3589, T_1173, UInt<1>("h00")) - node T_3708 = mux(T_3590, T_1178, UInt<1>("h00")) - node T_3710 = mux(T_3591, T_1183, UInt<1>("h00")) - node T_3712 = mux(T_3592, T_1188, UInt<1>("h00")) - node T_3714 = mux(T_3593, T_1193, UInt<1>("h00")) - node T_3716 = mux(T_3594, T_1198, UInt<1>("h00")) - node T_3718 = mux(T_3595, T_1203, UInt<1>("h00")) - node T_3720 = mux(T_3596, T_1208, UInt<1>("h00")) - node T_3722 = or(T_3598, T_3600) - node T_3723 = or(T_3722, T_3602) - node T_3724 = or(T_3723, T_3604) - node T_3725 = or(T_3724, T_3606) - node T_3726 = or(T_3725, T_3608) - node T_3727 = or(T_3726, T_3610) - node T_3728 = or(T_3727, T_3612) - node T_3729 = or(T_3728, T_3614) - node T_3730 = or(T_3729, T_3616) - node T_3731 = or(T_3730, T_3618) - node T_3732 = or(T_3731, T_3620) - node T_3733 = or(T_3732, T_3622) - node T_3734 = or(T_3733, T_3624) - node T_3735 = or(T_3734, T_3626) - node T_3736 = or(T_3735, T_3628) - node T_3737 = or(T_3736, T_3630) - node T_3738 = or(T_3737, T_3632) - node T_3739 = or(T_3738, T_3634) - node T_3740 = or(T_3739, T_3636) - node T_3741 = or(T_3740, T_3638) - node T_3742 = or(T_3741, T_3640) - node T_3743 = or(T_3742, T_3642) - node T_3744 = or(T_3743, T_3644) - node T_3745 = or(T_3744, T_3646) - node T_3746 = or(T_3745, T_3648) - node T_3747 = or(T_3746, T_3650) - node T_3748 = or(T_3747, T_3652) - node T_3749 = or(T_3748, T_3654) - node T_3750 = or(T_3749, T_3656) - node T_3751 = or(T_3750, T_3658) - node T_3752 = or(T_3751, T_3660) - node T_3753 = or(T_3752, T_3662) - node T_3754 = or(T_3753, T_3664) - node T_3755 = or(T_3754, T_3666) - node T_3756 = or(T_3755, T_3668) - node T_3757 = or(T_3756, T_3670) - node T_3758 = or(T_3757, T_3672) - node T_3759 = or(T_3758, T_3674) - node T_3760 = or(T_3759, T_3676) - node T_3761 = or(T_3760, T_3678) - node T_3762 = or(T_3761, T_3680) - node T_3763 = or(T_3762, T_3682) - node T_3764 = or(T_3763, T_3684) - node T_3765 = or(T_3764, T_3686) - node T_3766 = or(T_3765, T_3688) - node T_3767 = or(T_3766, T_3690) - node T_3768 = or(T_3767, T_3692) - node T_3769 = or(T_3768, T_3694) - node T_3770 = or(T_3769, T_3696) - node T_3771 = or(T_3770, T_3698) - node T_3772 = or(T_3771, T_3700) - node T_3773 = or(T_3772, T_3702) - node T_3774 = or(T_3773, T_3704) - node T_3775 = or(T_3774, T_3706) - node T_3776 = or(T_3775, T_3708) - node T_3777 = or(T_3776, T_3710) - node T_3778 = or(T_3777, T_3712) - node T_3779 = or(T_3778, T_3714) - node T_3780 = or(T_3779, T_3716) - node T_3781 = or(T_3780, T_3718) - node T_3782 = or(T_3781, T_3720) - wire T_3783 : UInt<6> - T_3783 <= UInt<1>("h00") - T_3783 <= T_3782 - node T_3785 = bit(T_3783, 0) - node T_3786 = bit(T_3783, 1) - node T_3787 = bit(T_3783, 2) - node T_3788 = bit(T_3783, 3) - node T_3789 = bit(T_3783, 4) - node T_3790 = bit(T_3783, 5) - infer mport T_3792 = pages[UInt<1>("h00")], clk - infer mport T_3794 = pages[UInt<1>("h01")], clk - infer mport T_3796 = pages[UInt<2>("h02")], clk - infer mport T_3798 = pages[UInt<2>("h03")], clk - infer mport T_3800 = pages[UInt<3>("h04")], clk - infer mport T_3802 = pages[UInt<3>("h05")], clk - node T_3804 = mux(T_3785, T_3792, UInt<1>("h00")) - node T_3806 = mux(T_3786, T_3794, UInt<1>("h00")) - node T_3808 = mux(T_3787, T_3796, UInt<1>("h00")) - node T_3810 = mux(T_3788, T_3798, UInt<1>("h00")) - node T_3812 = mux(T_3789, T_3800, UInt<1>("h00")) - node T_3814 = mux(T_3790, T_3802, UInt<1>("h00")) - node T_3816 = or(T_3804, T_3806) - node T_3817 = or(T_3816, T_3808) - node T_3818 = or(T_3817, T_3810) - node T_3819 = or(T_3818, T_3812) - node T_3820 = or(T_3819, T_3814) - wire T_3821 : UInt<27> - T_3821 <= UInt<1>("h00") - T_3821 <= T_3820 - node T_3823 = bit(hits, 0) - node T_3824 = bit(hits, 1) - node T_3825 = bit(hits, 2) - node T_3826 = bit(hits, 3) - node T_3827 = bit(hits, 4) - node T_3828 = bit(hits, 5) - node T_3829 = bit(hits, 6) - node T_3830 = bit(hits, 7) - node T_3831 = bit(hits, 8) - node T_3832 = bit(hits, 9) - node T_3833 = bit(hits, 10) - node T_3834 = bit(hits, 11) - node T_3835 = bit(hits, 12) - node T_3836 = bit(hits, 13) - node T_3837 = bit(hits, 14) - node T_3838 = bit(hits, 15) - node T_3839 = bit(hits, 16) - node T_3840 = bit(hits, 17) - node T_3841 = bit(hits, 18) - node T_3842 = bit(hits, 19) - node T_3843 = bit(hits, 20) - node T_3844 = bit(hits, 21) - node T_3845 = bit(hits, 22) - node T_3846 = bit(hits, 23) - node T_3847 = bit(hits, 24) - node T_3848 = bit(hits, 25) - node T_3849 = bit(hits, 26) - node T_3850 = bit(hits, 27) - node T_3851 = bit(hits, 28) - node T_3852 = bit(hits, 29) - node T_3853 = bit(hits, 30) - node T_3854 = bit(hits, 31) - node T_3855 = bit(hits, 32) - node T_3856 = bit(hits, 33) - node T_3857 = bit(hits, 34) - node T_3858 = bit(hits, 35) - node T_3859 = bit(hits, 36) - node T_3860 = bit(hits, 37) - node T_3861 = bit(hits, 38) - node T_3862 = bit(hits, 39) - node T_3863 = bit(hits, 40) - node T_3864 = bit(hits, 41) - node T_3865 = bit(hits, 42) - node T_3866 = bit(hits, 43) - node T_3867 = bit(hits, 44) - node T_3868 = bit(hits, 45) - node T_3869 = bit(hits, 46) - node T_3870 = bit(hits, 47) - node T_3871 = bit(hits, 48) - node T_3872 = bit(hits, 49) - node T_3873 = bit(hits, 50) - node T_3874 = bit(hits, 51) - node T_3875 = bit(hits, 52) - node T_3876 = bit(hits, 53) - node T_3877 = bit(hits, 54) - node T_3878 = bit(hits, 55) - node T_3879 = bit(hits, 56) - node T_3880 = bit(hits, 57) - node T_3881 = bit(hits, 58) - node T_3882 = bit(hits, 59) - node T_3883 = bit(hits, 60) - node T_3884 = bit(hits, 61) - infer mport T_3886 = tgts[UInt<1>("h00")], clk - infer mport T_3888 = tgts[UInt<1>("h01")], clk - infer mport T_3890 = tgts[UInt<2>("h02")], clk - infer mport T_3892 = tgts[UInt<2>("h03")], clk - infer mport T_3894 = tgts[UInt<3>("h04")], clk - infer mport T_3896 = tgts[UInt<3>("h05")], clk - infer mport T_3898 = tgts[UInt<3>("h06")], clk - infer mport T_3900 = tgts[UInt<3>("h07")], clk - infer mport T_3902 = tgts[UInt<4>("h08")], clk - infer mport T_3904 = tgts[UInt<4>("h09")], clk - infer mport T_3906 = tgts[UInt<4>("h0a")], clk - infer mport T_3908 = tgts[UInt<4>("h0b")], clk - infer mport T_3910 = tgts[UInt<4>("h0c")], clk - infer mport T_3912 = tgts[UInt<4>("h0d")], clk - infer mport T_3914 = tgts[UInt<4>("h0e")], clk - infer mport T_3916 = tgts[UInt<4>("h0f")], clk - infer mport T_3918 = tgts[UInt<5>("h010")], clk - infer mport T_3920 = tgts[UInt<5>("h011")], clk - infer mport T_3922 = tgts[UInt<5>("h012")], clk - infer mport T_3924 = tgts[UInt<5>("h013")], clk - infer mport T_3926 = tgts[UInt<5>("h014")], clk - infer mport T_3928 = tgts[UInt<5>("h015")], clk - infer mport T_3930 = tgts[UInt<5>("h016")], clk - infer mport T_3932 = tgts[UInt<5>("h017")], clk - infer mport T_3934 = tgts[UInt<5>("h018")], clk - infer mport T_3936 = tgts[UInt<5>("h019")], clk - infer mport T_3938 = tgts[UInt<5>("h01a")], clk - infer mport T_3940 = tgts[UInt<5>("h01b")], clk - infer mport T_3942 = tgts[UInt<5>("h01c")], clk - infer mport T_3944 = tgts[UInt<5>("h01d")], clk - infer mport T_3946 = tgts[UInt<5>("h01e")], clk - infer mport T_3948 = tgts[UInt<5>("h01f")], clk - infer mport T_3950 = tgts[UInt<6>("h020")], clk - infer mport T_3952 = tgts[UInt<6>("h021")], clk - infer mport T_3954 = tgts[UInt<6>("h022")], clk - infer mport T_3956 = tgts[UInt<6>("h023")], clk - infer mport T_3958 = tgts[UInt<6>("h024")], clk - infer mport T_3960 = tgts[UInt<6>("h025")], clk - infer mport T_3962 = tgts[UInt<6>("h026")], clk - infer mport T_3964 = tgts[UInt<6>("h027")], clk - infer mport T_3966 = tgts[UInt<6>("h028")], clk - infer mport T_3968 = tgts[UInt<6>("h029")], clk - infer mport T_3970 = tgts[UInt<6>("h02a")], clk - infer mport T_3972 = tgts[UInt<6>("h02b")], clk - infer mport T_3974 = tgts[UInt<6>("h02c")], clk - infer mport T_3976 = tgts[UInt<6>("h02d")], clk - infer mport T_3978 = tgts[UInt<6>("h02e")], clk - infer mport T_3980 = tgts[UInt<6>("h02f")], clk - infer mport T_3982 = tgts[UInt<6>("h030")], clk - infer mport T_3984 = tgts[UInt<6>("h031")], clk - infer mport T_3986 = tgts[UInt<6>("h032")], clk - infer mport T_3988 = tgts[UInt<6>("h033")], clk - infer mport T_3990 = tgts[UInt<6>("h034")], clk - infer mport T_3992 = tgts[UInt<6>("h035")], clk - infer mport T_3994 = tgts[UInt<6>("h036")], clk - infer mport T_3996 = tgts[UInt<6>("h037")], clk - infer mport T_3998 = tgts[UInt<6>("h038")], clk - infer mport T_4000 = tgts[UInt<6>("h039")], clk - infer mport T_4002 = tgts[UInt<6>("h03a")], clk - infer mport T_4004 = tgts[UInt<6>("h03b")], clk - infer mport T_4006 = tgts[UInt<6>("h03c")], clk - infer mport T_4008 = tgts[UInt<6>("h03d")], clk - node T_4010 = mux(T_3823, T_3886, UInt<1>("h00")) - node T_4012 = mux(T_3824, T_3888, UInt<1>("h00")) - node T_4014 = mux(T_3825, T_3890, UInt<1>("h00")) - node T_4016 = mux(T_3826, T_3892, UInt<1>("h00")) - node T_4018 = mux(T_3827, T_3894, UInt<1>("h00")) - node T_4020 = mux(T_3828, T_3896, UInt<1>("h00")) - node T_4022 = mux(T_3829, T_3898, UInt<1>("h00")) - node T_4024 = mux(T_3830, T_3900, UInt<1>("h00")) - node T_4026 = mux(T_3831, T_3902, UInt<1>("h00")) - node T_4028 = mux(T_3832, T_3904, UInt<1>("h00")) - node T_4030 = mux(T_3833, T_3906, UInt<1>("h00")) - node T_4032 = mux(T_3834, T_3908, UInt<1>("h00")) - node T_4034 = mux(T_3835, T_3910, UInt<1>("h00")) - node T_4036 = mux(T_3836, T_3912, UInt<1>("h00")) - node T_4038 = mux(T_3837, T_3914, UInt<1>("h00")) - node T_4040 = mux(T_3838, T_3916, UInt<1>("h00")) - node T_4042 = mux(T_3839, T_3918, UInt<1>("h00")) - node T_4044 = mux(T_3840, T_3920, UInt<1>("h00")) - node T_4046 = mux(T_3841, T_3922, UInt<1>("h00")) - node T_4048 = mux(T_3842, T_3924, UInt<1>("h00")) - node T_4050 = mux(T_3843, T_3926, UInt<1>("h00")) - node T_4052 = mux(T_3844, T_3928, UInt<1>("h00")) - node T_4054 = mux(T_3845, T_3930, UInt<1>("h00")) - node T_4056 = mux(T_3846, T_3932, UInt<1>("h00")) - node T_4058 = mux(T_3847, T_3934, UInt<1>("h00")) - node T_4060 = mux(T_3848, T_3936, UInt<1>("h00")) - node T_4062 = mux(T_3849, T_3938, UInt<1>("h00")) - node T_4064 = mux(T_3850, T_3940, UInt<1>("h00")) - node T_4066 = mux(T_3851, T_3942, UInt<1>("h00")) - node T_4068 = mux(T_3852, T_3944, UInt<1>("h00")) - node T_4070 = mux(T_3853, T_3946, UInt<1>("h00")) - node T_4072 = mux(T_3854, T_3948, UInt<1>("h00")) - node T_4074 = mux(T_3855, T_3950, UInt<1>("h00")) - node T_4076 = mux(T_3856, T_3952, UInt<1>("h00")) - node T_4078 = mux(T_3857, T_3954, UInt<1>("h00")) - node T_4080 = mux(T_3858, T_3956, UInt<1>("h00")) - node T_4082 = mux(T_3859, T_3958, UInt<1>("h00")) - node T_4084 = mux(T_3860, T_3960, UInt<1>("h00")) - node T_4086 = mux(T_3861, T_3962, UInt<1>("h00")) - node T_4088 = mux(T_3862, T_3964, UInt<1>("h00")) - node T_4090 = mux(T_3863, T_3966, UInt<1>("h00")) - node T_4092 = mux(T_3864, T_3968, UInt<1>("h00")) - node T_4094 = mux(T_3865, T_3970, UInt<1>("h00")) - node T_4096 = mux(T_3866, T_3972, UInt<1>("h00")) - node T_4098 = mux(T_3867, T_3974, UInt<1>("h00")) - node T_4100 = mux(T_3868, T_3976, UInt<1>("h00")) - node T_4102 = mux(T_3869, T_3978, UInt<1>("h00")) - node T_4104 = mux(T_3870, T_3980, UInt<1>("h00")) - node T_4106 = mux(T_3871, T_3982, UInt<1>("h00")) - node T_4108 = mux(T_3872, T_3984, UInt<1>("h00")) - node T_4110 = mux(T_3873, T_3986, UInt<1>("h00")) - node T_4112 = mux(T_3874, T_3988, UInt<1>("h00")) - node T_4114 = mux(T_3875, T_3990, UInt<1>("h00")) - node T_4116 = mux(T_3876, T_3992, UInt<1>("h00")) - node T_4118 = mux(T_3877, T_3994, UInt<1>("h00")) - node T_4120 = mux(T_3878, T_3996, UInt<1>("h00")) - node T_4122 = mux(T_3879, T_3998, UInt<1>("h00")) - node T_4124 = mux(T_3880, T_4000, UInt<1>("h00")) - node T_4126 = mux(T_3881, T_4002, UInt<1>("h00")) - node T_4128 = mux(T_3882, T_4004, UInt<1>("h00")) - node T_4130 = mux(T_3883, T_4006, UInt<1>("h00")) - node T_4132 = mux(T_3884, T_4008, UInt<1>("h00")) - node T_4134 = or(T_4010, T_4012) - node T_4135 = or(T_4134, T_4014) - node T_4136 = or(T_4135, T_4016) - node T_4137 = or(T_4136, T_4018) - node T_4138 = or(T_4137, T_4020) - node T_4139 = or(T_4138, T_4022) - node T_4140 = or(T_4139, T_4024) - node T_4141 = or(T_4140, T_4026) - node T_4142 = or(T_4141, T_4028) - node T_4143 = or(T_4142, T_4030) - node T_4144 = or(T_4143, T_4032) - node T_4145 = or(T_4144, T_4034) - node T_4146 = or(T_4145, T_4036) - node T_4147 = or(T_4146, T_4038) - node T_4148 = or(T_4147, T_4040) - node T_4149 = or(T_4148, T_4042) - node T_4150 = or(T_4149, T_4044) - node T_4151 = or(T_4150, T_4046) - node T_4152 = or(T_4151, T_4048) - node T_4153 = or(T_4152, T_4050) - node T_4154 = or(T_4153, T_4052) - node T_4155 = or(T_4154, T_4054) - node T_4156 = or(T_4155, T_4056) - node T_4157 = or(T_4156, T_4058) - node T_4158 = or(T_4157, T_4060) - node T_4159 = or(T_4158, T_4062) - node T_4160 = or(T_4159, T_4064) - node T_4161 = or(T_4160, T_4066) - node T_4162 = or(T_4161, T_4068) - node T_4163 = or(T_4162, T_4070) - node T_4164 = or(T_4163, T_4072) - node T_4165 = or(T_4164, T_4074) - node T_4166 = or(T_4165, T_4076) - node T_4167 = or(T_4166, T_4078) - node T_4168 = or(T_4167, T_4080) - node T_4169 = or(T_4168, T_4082) - node T_4170 = or(T_4169, T_4084) - node T_4171 = or(T_4170, T_4086) - node T_4172 = or(T_4171, T_4088) - node T_4173 = or(T_4172, T_4090) - node T_4174 = or(T_4173, T_4092) - node T_4175 = or(T_4174, T_4094) - node T_4176 = or(T_4175, T_4096) - node T_4177 = or(T_4176, T_4098) - node T_4178 = or(T_4177, T_4100) - node T_4179 = or(T_4178, T_4102) - node T_4180 = or(T_4179, T_4104) - node T_4181 = or(T_4180, T_4106) - node T_4182 = or(T_4181, T_4108) - node T_4183 = or(T_4182, T_4110) - node T_4184 = or(T_4183, T_4112) - node T_4185 = or(T_4184, T_4114) - node T_4186 = or(T_4185, T_4116) - node T_4187 = or(T_4186, T_4118) - node T_4188 = or(T_4187, T_4120) - node T_4189 = or(T_4188, T_4122) - node T_4190 = or(T_4189, T_4124) - node T_4191 = or(T_4190, T_4126) - node T_4192 = or(T_4191, T_4128) - node T_4193 = or(T_4192, T_4130) - node T_4194 = or(T_4193, T_4132) - wire T_4195 : UInt<12> - T_4195 <= UInt<1>("h00") - T_4195 <= T_4194 - node T_4197 = cat(T_3821, T_4195) - io.resp.bits.target <= T_4197 - node T_4198 = bits(hits, 61, 32) - node T_4199 = bits(hits, 31, 0) - node T_4201 = neq(T_4198, UInt<1>("h00")) - node T_4202 = or(T_4198, T_4199) - node T_4203 = bits(T_4202, 31, 16) - node T_4204 = bits(T_4202, 15, 0) - node T_4206 = neq(T_4203, UInt<1>("h00")) - node T_4207 = or(T_4203, T_4204) - node T_4208 = bits(T_4207, 15, 8) - node T_4209 = bits(T_4207, 7, 0) - node T_4211 = neq(T_4208, UInt<1>("h00")) - node T_4212 = or(T_4208, T_4209) - node T_4213 = bits(T_4212, 7, 4) - node T_4214 = bits(T_4212, 3, 0) - node T_4216 = neq(T_4213, UInt<1>("h00")) - node T_4217 = or(T_4213, T_4214) - node T_4218 = bits(T_4217, 3, 2) - node T_4219 = bits(T_4217, 1, 0) - node T_4221 = neq(T_4218, UInt<1>("h00")) - node T_4222 = or(T_4218, T_4219) - node T_4223 = bit(T_4222, 1) - node T_4224 = cat(T_4221, T_4223) - node T_4225 = cat(T_4216, T_4224) - node T_4226 = cat(T_4211, T_4225) - node T_4227 = cat(T_4206, T_4226) - node T_4228 = cat(T_4201, T_4227) - io.resp.bits.entry <= T_4228 - infer mport T_4229 = brIdx[io.resp.bits.entry], clk - io.resp.bits.bridx <= T_4229 + node T_3521 = bits(hits, 0, 0) + node T_3522 = bits(hits, 1, 1) + node T_3523 = bits(hits, 2, 2) + node T_3524 = bits(hits, 3, 3) + node T_3525 = bits(hits, 4, 4) + node T_3526 = bits(hits, 5, 5) + node T_3527 = bits(hits, 6, 6) + node T_3528 = bits(hits, 7, 7) + node T_3529 = bits(hits, 8, 8) + node T_3530 = bits(hits, 9, 9) + node T_3531 = bits(hits, 10, 10) + node T_3532 = bits(hits, 11, 11) + node T_3533 = bits(hits, 12, 12) + node T_3534 = bits(hits, 13, 13) + node T_3535 = bits(hits, 14, 14) + node T_3536 = bits(hits, 15, 15) + node T_3537 = bits(hits, 16, 16) + node T_3538 = bits(hits, 17, 17) + node T_3539 = bits(hits, 18, 18) + node T_3540 = bits(hits, 19, 19) + node T_3541 = bits(hits, 20, 20) + node T_3542 = bits(hits, 21, 21) + node T_3543 = bits(hits, 22, 22) + node T_3544 = bits(hits, 23, 23) + node T_3545 = bits(hits, 24, 24) + node T_3546 = bits(hits, 25, 25) + node T_3547 = bits(hits, 26, 26) + node T_3548 = bits(hits, 27, 27) + node T_3549 = bits(hits, 28, 28) + node T_3550 = bits(hits, 29, 29) + node T_3551 = bits(hits, 30, 30) + node T_3552 = bits(hits, 31, 31) + node T_3553 = bits(hits, 32, 32) + node T_3554 = bits(hits, 33, 33) + node T_3555 = bits(hits, 34, 34) + node T_3556 = bits(hits, 35, 35) + node T_3557 = bits(hits, 36, 36) + node T_3558 = bits(hits, 37, 37) + node T_3559 = bits(hits, 38, 38) + node T_3560 = bits(hits, 39, 39) + node T_3561 = bits(hits, 40, 40) + node T_3562 = bits(hits, 41, 41) + node T_3563 = bits(hits, 42, 42) + node T_3564 = bits(hits, 43, 43) + node T_3565 = bits(hits, 44, 44) + node T_3566 = bits(hits, 45, 45) + node T_3567 = bits(hits, 46, 46) + node T_3568 = bits(hits, 47, 47) + node T_3569 = bits(hits, 48, 48) + node T_3570 = bits(hits, 49, 49) + node T_3571 = bits(hits, 50, 50) + node T_3572 = bits(hits, 51, 51) + node T_3573 = bits(hits, 52, 52) + node T_3574 = bits(hits, 53, 53) + node T_3575 = bits(hits, 54, 54) + node T_3576 = bits(hits, 55, 55) + node T_3577 = bits(hits, 56, 56) + node T_3578 = bits(hits, 57, 57) + node T_3579 = bits(hits, 58, 58) + node T_3580 = bits(hits, 59, 59) + node T_3581 = bits(hits, 60, 60) + node T_3582 = bits(hits, 61, 61) + node T_3584 = mux(T_3521, T_903, UInt<1>("h00")) + node T_3586 = mux(T_3522, T_908, UInt<1>("h00")) + node T_3588 = mux(T_3523, T_913, UInt<1>("h00")) + node T_3590 = mux(T_3524, T_918, UInt<1>("h00")) + node T_3592 = mux(T_3525, T_923, UInt<1>("h00")) + node T_3594 = mux(T_3526, T_928, UInt<1>("h00")) + node T_3596 = mux(T_3527, T_933, UInt<1>("h00")) + node T_3598 = mux(T_3528, T_938, UInt<1>("h00")) + node T_3600 = mux(T_3529, T_943, UInt<1>("h00")) + node T_3602 = mux(T_3530, T_948, UInt<1>("h00")) + node T_3604 = mux(T_3531, T_953, UInt<1>("h00")) + node T_3606 = mux(T_3532, T_958, UInt<1>("h00")) + node T_3608 = mux(T_3533, T_963, UInt<1>("h00")) + node T_3610 = mux(T_3534, T_968, UInt<1>("h00")) + node T_3612 = mux(T_3535, T_973, UInt<1>("h00")) + node T_3614 = mux(T_3536, T_978, UInt<1>("h00")) + node T_3616 = mux(T_3537, T_983, UInt<1>("h00")) + node T_3618 = mux(T_3538, T_988, UInt<1>("h00")) + node T_3620 = mux(T_3539, T_993, UInt<1>("h00")) + node T_3622 = mux(T_3540, T_998, UInt<1>("h00")) + node T_3624 = mux(T_3541, T_1003, UInt<1>("h00")) + node T_3626 = mux(T_3542, T_1008, UInt<1>("h00")) + node T_3628 = mux(T_3543, T_1013, UInt<1>("h00")) + node T_3630 = mux(T_3544, T_1018, UInt<1>("h00")) + node T_3632 = mux(T_3545, T_1023, UInt<1>("h00")) + node T_3634 = mux(T_3546, T_1028, UInt<1>("h00")) + node T_3636 = mux(T_3547, T_1033, UInt<1>("h00")) + node T_3638 = mux(T_3548, T_1038, UInt<1>("h00")) + node T_3640 = mux(T_3549, T_1043, UInt<1>("h00")) + node T_3642 = mux(T_3550, T_1048, UInt<1>("h00")) + node T_3644 = mux(T_3551, T_1053, UInt<1>("h00")) + node T_3646 = mux(T_3552, T_1058, UInt<1>("h00")) + node T_3648 = mux(T_3553, T_1063, UInt<1>("h00")) + node T_3650 = mux(T_3554, T_1068, UInt<1>("h00")) + node T_3652 = mux(T_3555, T_1073, UInt<1>("h00")) + node T_3654 = mux(T_3556, T_1078, UInt<1>("h00")) + node T_3656 = mux(T_3557, T_1083, UInt<1>("h00")) + node T_3658 = mux(T_3558, T_1088, UInt<1>("h00")) + node T_3660 = mux(T_3559, T_1093, UInt<1>("h00")) + node T_3662 = mux(T_3560, T_1098, UInt<1>("h00")) + node T_3664 = mux(T_3561, T_1103, UInt<1>("h00")) + node T_3666 = mux(T_3562, T_1108, UInt<1>("h00")) + node T_3668 = mux(T_3563, T_1113, UInt<1>("h00")) + node T_3670 = mux(T_3564, T_1118, UInt<1>("h00")) + node T_3672 = mux(T_3565, T_1123, UInt<1>("h00")) + node T_3674 = mux(T_3566, T_1128, UInt<1>("h00")) + node T_3676 = mux(T_3567, T_1133, UInt<1>("h00")) + node T_3678 = mux(T_3568, T_1138, UInt<1>("h00")) + node T_3680 = mux(T_3569, T_1143, UInt<1>("h00")) + node T_3682 = mux(T_3570, T_1148, UInt<1>("h00")) + node T_3684 = mux(T_3571, T_1153, UInt<1>("h00")) + node T_3686 = mux(T_3572, T_1158, UInt<1>("h00")) + node T_3688 = mux(T_3573, T_1163, UInt<1>("h00")) + node T_3690 = mux(T_3574, T_1168, UInt<1>("h00")) + node T_3692 = mux(T_3575, T_1173, UInt<1>("h00")) + node T_3694 = mux(T_3576, T_1178, UInt<1>("h00")) + node T_3696 = mux(T_3577, T_1183, UInt<1>("h00")) + node T_3698 = mux(T_3578, T_1188, UInt<1>("h00")) + node T_3700 = mux(T_3579, T_1193, UInt<1>("h00")) + node T_3702 = mux(T_3580, T_1198, UInt<1>("h00")) + node T_3704 = mux(T_3581, T_1203, UInt<1>("h00")) + node T_3706 = mux(T_3582, T_1208, UInt<1>("h00")) + node T_3708 = or(T_3584, T_3586) + node T_3709 = or(T_3708, T_3588) + node T_3710 = or(T_3709, T_3590) + node T_3711 = or(T_3710, T_3592) + node T_3712 = or(T_3711, T_3594) + node T_3713 = or(T_3712, T_3596) + node T_3714 = or(T_3713, T_3598) + node T_3715 = or(T_3714, T_3600) + node T_3716 = or(T_3715, T_3602) + node T_3717 = or(T_3716, T_3604) + node T_3718 = or(T_3717, T_3606) + node T_3719 = or(T_3718, T_3608) + node T_3720 = or(T_3719, T_3610) + node T_3721 = or(T_3720, T_3612) + node T_3722 = or(T_3721, T_3614) + node T_3723 = or(T_3722, T_3616) + node T_3724 = or(T_3723, T_3618) + node T_3725 = or(T_3724, T_3620) + node T_3726 = or(T_3725, T_3622) + node T_3727 = or(T_3726, T_3624) + node T_3728 = or(T_3727, T_3626) + node T_3729 = or(T_3728, T_3628) + node T_3730 = or(T_3729, T_3630) + node T_3731 = or(T_3730, T_3632) + node T_3732 = or(T_3731, T_3634) + node T_3733 = or(T_3732, T_3636) + node T_3734 = or(T_3733, T_3638) + node T_3735 = or(T_3734, T_3640) + node T_3736 = or(T_3735, T_3642) + node T_3737 = or(T_3736, T_3644) + node T_3738 = or(T_3737, T_3646) + node T_3739 = or(T_3738, T_3648) + node T_3740 = or(T_3739, T_3650) + node T_3741 = or(T_3740, T_3652) + node T_3742 = or(T_3741, T_3654) + node T_3743 = or(T_3742, T_3656) + node T_3744 = or(T_3743, T_3658) + node T_3745 = or(T_3744, T_3660) + node T_3746 = or(T_3745, T_3662) + node T_3747 = or(T_3746, T_3664) + node T_3748 = or(T_3747, T_3666) + node T_3749 = or(T_3748, T_3668) + node T_3750 = or(T_3749, T_3670) + node T_3751 = or(T_3750, T_3672) + node T_3752 = or(T_3751, T_3674) + node T_3753 = or(T_3752, T_3676) + node T_3754 = or(T_3753, T_3678) + node T_3755 = or(T_3754, T_3680) + node T_3756 = or(T_3755, T_3682) + node T_3757 = or(T_3756, T_3684) + node T_3758 = or(T_3757, T_3686) + node T_3759 = or(T_3758, T_3688) + node T_3760 = or(T_3759, T_3690) + node T_3761 = or(T_3760, T_3692) + node T_3762 = or(T_3761, T_3694) + node T_3763 = or(T_3762, T_3696) + node T_3764 = or(T_3763, T_3698) + node T_3765 = or(T_3764, T_3700) + node T_3766 = or(T_3765, T_3702) + node T_3767 = or(T_3766, T_3704) + node T_3768 = or(T_3767, T_3706) + wire T_3769 : UInt<6> + T_3769 is invalid + T_3769 <= T_3768 + node T_3770 = bits(T_3769, 0, 0) + node T_3771 = bits(T_3769, 1, 1) + node T_3772 = bits(T_3769, 2, 2) + node T_3773 = bits(T_3769, 3, 3) + node T_3774 = bits(T_3769, 4, 4) + node T_3775 = bits(T_3769, 5, 5) + infer mport T_3777 = pages[UInt<1>("h00")], clk + infer mport T_3779 = pages[UInt<1>("h01")], clk + infer mport T_3781 = pages[UInt<2>("h02")], clk + infer mport T_3783 = pages[UInt<2>("h03")], clk + infer mport T_3785 = pages[UInt<3>("h04")], clk + infer mport T_3787 = pages[UInt<3>("h05")], clk + node T_3789 = mux(T_3770, T_3777, UInt<1>("h00")) + node T_3791 = mux(T_3771, T_3779, UInt<1>("h00")) + node T_3793 = mux(T_3772, T_3781, UInt<1>("h00")) + node T_3795 = mux(T_3773, T_3783, UInt<1>("h00")) + node T_3797 = mux(T_3774, T_3785, UInt<1>("h00")) + node T_3799 = mux(T_3775, T_3787, UInt<1>("h00")) + node T_3801 = or(T_3789, T_3791) + node T_3802 = or(T_3801, T_3793) + node T_3803 = or(T_3802, T_3795) + node T_3804 = or(T_3803, T_3797) + node T_3805 = or(T_3804, T_3799) + wire T_3806 : UInt<27> + T_3806 is invalid + T_3806 <= T_3805 + node T_3807 = bits(hits, 0, 0) + node T_3808 = bits(hits, 1, 1) + node T_3809 = bits(hits, 2, 2) + node T_3810 = bits(hits, 3, 3) + node T_3811 = bits(hits, 4, 4) + node T_3812 = bits(hits, 5, 5) + node T_3813 = bits(hits, 6, 6) + node T_3814 = bits(hits, 7, 7) + node T_3815 = bits(hits, 8, 8) + node T_3816 = bits(hits, 9, 9) + node T_3817 = bits(hits, 10, 10) + node T_3818 = bits(hits, 11, 11) + node T_3819 = bits(hits, 12, 12) + node T_3820 = bits(hits, 13, 13) + node T_3821 = bits(hits, 14, 14) + node T_3822 = bits(hits, 15, 15) + node T_3823 = bits(hits, 16, 16) + node T_3824 = bits(hits, 17, 17) + node T_3825 = bits(hits, 18, 18) + node T_3826 = bits(hits, 19, 19) + node T_3827 = bits(hits, 20, 20) + node T_3828 = bits(hits, 21, 21) + node T_3829 = bits(hits, 22, 22) + node T_3830 = bits(hits, 23, 23) + node T_3831 = bits(hits, 24, 24) + node T_3832 = bits(hits, 25, 25) + node T_3833 = bits(hits, 26, 26) + node T_3834 = bits(hits, 27, 27) + node T_3835 = bits(hits, 28, 28) + node T_3836 = bits(hits, 29, 29) + node T_3837 = bits(hits, 30, 30) + node T_3838 = bits(hits, 31, 31) + node T_3839 = bits(hits, 32, 32) + node T_3840 = bits(hits, 33, 33) + node T_3841 = bits(hits, 34, 34) + node T_3842 = bits(hits, 35, 35) + node T_3843 = bits(hits, 36, 36) + node T_3844 = bits(hits, 37, 37) + node T_3845 = bits(hits, 38, 38) + node T_3846 = bits(hits, 39, 39) + node T_3847 = bits(hits, 40, 40) + node T_3848 = bits(hits, 41, 41) + node T_3849 = bits(hits, 42, 42) + node T_3850 = bits(hits, 43, 43) + node T_3851 = bits(hits, 44, 44) + node T_3852 = bits(hits, 45, 45) + node T_3853 = bits(hits, 46, 46) + node T_3854 = bits(hits, 47, 47) + node T_3855 = bits(hits, 48, 48) + node T_3856 = bits(hits, 49, 49) + node T_3857 = bits(hits, 50, 50) + node T_3858 = bits(hits, 51, 51) + node T_3859 = bits(hits, 52, 52) + node T_3860 = bits(hits, 53, 53) + node T_3861 = bits(hits, 54, 54) + node T_3862 = bits(hits, 55, 55) + node T_3863 = bits(hits, 56, 56) + node T_3864 = bits(hits, 57, 57) + node T_3865 = bits(hits, 58, 58) + node T_3866 = bits(hits, 59, 59) + node T_3867 = bits(hits, 60, 60) + node T_3868 = bits(hits, 61, 61) + infer mport T_3870 = tgts[UInt<1>("h00")], clk + infer mport T_3872 = tgts[UInt<1>("h01")], clk + infer mport T_3874 = tgts[UInt<2>("h02")], clk + infer mport T_3876 = tgts[UInt<2>("h03")], clk + infer mport T_3878 = tgts[UInt<3>("h04")], clk + infer mport T_3880 = tgts[UInt<3>("h05")], clk + infer mport T_3882 = tgts[UInt<3>("h06")], clk + infer mport T_3884 = tgts[UInt<3>("h07")], clk + infer mport T_3886 = tgts[UInt<4>("h08")], clk + infer mport T_3888 = tgts[UInt<4>("h09")], clk + infer mport T_3890 = tgts[UInt<4>("h0a")], clk + infer mport T_3892 = tgts[UInt<4>("h0b")], clk + infer mport T_3894 = tgts[UInt<4>("h0c")], clk + infer mport T_3896 = tgts[UInt<4>("h0d")], clk + infer mport T_3898 = tgts[UInt<4>("h0e")], clk + infer mport T_3900 = tgts[UInt<4>("h0f")], clk + infer mport T_3902 = tgts[UInt<5>("h010")], clk + infer mport T_3904 = tgts[UInt<5>("h011")], clk + infer mport T_3906 = tgts[UInt<5>("h012")], clk + infer mport T_3908 = tgts[UInt<5>("h013")], clk + infer mport T_3910 = tgts[UInt<5>("h014")], clk + infer mport T_3912 = tgts[UInt<5>("h015")], clk + infer mport T_3914 = tgts[UInt<5>("h016")], clk + infer mport T_3916 = tgts[UInt<5>("h017")], clk + infer mport T_3918 = tgts[UInt<5>("h018")], clk + infer mport T_3920 = tgts[UInt<5>("h019")], clk + infer mport T_3922 = tgts[UInt<5>("h01a")], clk + infer mport T_3924 = tgts[UInt<5>("h01b")], clk + infer mport T_3926 = tgts[UInt<5>("h01c")], clk + infer mport T_3928 = tgts[UInt<5>("h01d")], clk + infer mport T_3930 = tgts[UInt<5>("h01e")], clk + infer mport T_3932 = tgts[UInt<5>("h01f")], clk + infer mport T_3934 = tgts[UInt<6>("h020")], clk + infer mport T_3936 = tgts[UInt<6>("h021")], clk + infer mport T_3938 = tgts[UInt<6>("h022")], clk + infer mport T_3940 = tgts[UInt<6>("h023")], clk + infer mport T_3942 = tgts[UInt<6>("h024")], clk + infer mport T_3944 = tgts[UInt<6>("h025")], clk + infer mport T_3946 = tgts[UInt<6>("h026")], clk + infer mport T_3948 = tgts[UInt<6>("h027")], clk + infer mport T_3950 = tgts[UInt<6>("h028")], clk + infer mport T_3952 = tgts[UInt<6>("h029")], clk + infer mport T_3954 = tgts[UInt<6>("h02a")], clk + infer mport T_3956 = tgts[UInt<6>("h02b")], clk + infer mport T_3958 = tgts[UInt<6>("h02c")], clk + infer mport T_3960 = tgts[UInt<6>("h02d")], clk + infer mport T_3962 = tgts[UInt<6>("h02e")], clk + infer mport T_3964 = tgts[UInt<6>("h02f")], clk + infer mport T_3966 = tgts[UInt<6>("h030")], clk + infer mport T_3968 = tgts[UInt<6>("h031")], clk + infer mport T_3970 = tgts[UInt<6>("h032")], clk + infer mport T_3972 = tgts[UInt<6>("h033")], clk + infer mport T_3974 = tgts[UInt<6>("h034")], clk + infer mport T_3976 = tgts[UInt<6>("h035")], clk + infer mport T_3978 = tgts[UInt<6>("h036")], clk + infer mport T_3980 = tgts[UInt<6>("h037")], clk + infer mport T_3982 = tgts[UInt<6>("h038")], clk + infer mport T_3984 = tgts[UInt<6>("h039")], clk + infer mport T_3986 = tgts[UInt<6>("h03a")], clk + infer mport T_3988 = tgts[UInt<6>("h03b")], clk + infer mport T_3990 = tgts[UInt<6>("h03c")], clk + infer mport T_3992 = tgts[UInt<6>("h03d")], clk + node T_3994 = mux(T_3807, T_3870, UInt<1>("h00")) + node T_3996 = mux(T_3808, T_3872, UInt<1>("h00")) + node T_3998 = mux(T_3809, T_3874, UInt<1>("h00")) + node T_4000 = mux(T_3810, T_3876, UInt<1>("h00")) + node T_4002 = mux(T_3811, T_3878, UInt<1>("h00")) + node T_4004 = mux(T_3812, T_3880, UInt<1>("h00")) + node T_4006 = mux(T_3813, T_3882, UInt<1>("h00")) + node T_4008 = mux(T_3814, T_3884, UInt<1>("h00")) + node T_4010 = mux(T_3815, T_3886, UInt<1>("h00")) + node T_4012 = mux(T_3816, T_3888, UInt<1>("h00")) + node T_4014 = mux(T_3817, T_3890, UInt<1>("h00")) + node T_4016 = mux(T_3818, T_3892, UInt<1>("h00")) + node T_4018 = mux(T_3819, T_3894, UInt<1>("h00")) + node T_4020 = mux(T_3820, T_3896, UInt<1>("h00")) + node T_4022 = mux(T_3821, T_3898, UInt<1>("h00")) + node T_4024 = mux(T_3822, T_3900, UInt<1>("h00")) + node T_4026 = mux(T_3823, T_3902, UInt<1>("h00")) + node T_4028 = mux(T_3824, T_3904, UInt<1>("h00")) + node T_4030 = mux(T_3825, T_3906, UInt<1>("h00")) + node T_4032 = mux(T_3826, T_3908, UInt<1>("h00")) + node T_4034 = mux(T_3827, T_3910, UInt<1>("h00")) + node T_4036 = mux(T_3828, T_3912, UInt<1>("h00")) + node T_4038 = mux(T_3829, T_3914, UInt<1>("h00")) + node T_4040 = mux(T_3830, T_3916, UInt<1>("h00")) + node T_4042 = mux(T_3831, T_3918, UInt<1>("h00")) + node T_4044 = mux(T_3832, T_3920, UInt<1>("h00")) + node T_4046 = mux(T_3833, T_3922, UInt<1>("h00")) + node T_4048 = mux(T_3834, T_3924, UInt<1>("h00")) + node T_4050 = mux(T_3835, T_3926, UInt<1>("h00")) + node T_4052 = mux(T_3836, T_3928, UInt<1>("h00")) + node T_4054 = mux(T_3837, T_3930, UInt<1>("h00")) + node T_4056 = mux(T_3838, T_3932, UInt<1>("h00")) + node T_4058 = mux(T_3839, T_3934, UInt<1>("h00")) + node T_4060 = mux(T_3840, T_3936, UInt<1>("h00")) + node T_4062 = mux(T_3841, T_3938, UInt<1>("h00")) + node T_4064 = mux(T_3842, T_3940, UInt<1>("h00")) + node T_4066 = mux(T_3843, T_3942, UInt<1>("h00")) + node T_4068 = mux(T_3844, T_3944, UInt<1>("h00")) + node T_4070 = mux(T_3845, T_3946, UInt<1>("h00")) + node T_4072 = mux(T_3846, T_3948, UInt<1>("h00")) + node T_4074 = mux(T_3847, T_3950, UInt<1>("h00")) + node T_4076 = mux(T_3848, T_3952, UInt<1>("h00")) + node T_4078 = mux(T_3849, T_3954, UInt<1>("h00")) + node T_4080 = mux(T_3850, T_3956, UInt<1>("h00")) + node T_4082 = mux(T_3851, T_3958, UInt<1>("h00")) + node T_4084 = mux(T_3852, T_3960, UInt<1>("h00")) + node T_4086 = mux(T_3853, T_3962, UInt<1>("h00")) + node T_4088 = mux(T_3854, T_3964, UInt<1>("h00")) + node T_4090 = mux(T_3855, T_3966, UInt<1>("h00")) + node T_4092 = mux(T_3856, T_3968, UInt<1>("h00")) + node T_4094 = mux(T_3857, T_3970, UInt<1>("h00")) + node T_4096 = mux(T_3858, T_3972, UInt<1>("h00")) + node T_4098 = mux(T_3859, T_3974, UInt<1>("h00")) + node T_4100 = mux(T_3860, T_3976, UInt<1>("h00")) + node T_4102 = mux(T_3861, T_3978, UInt<1>("h00")) + node T_4104 = mux(T_3862, T_3980, UInt<1>("h00")) + node T_4106 = mux(T_3863, T_3982, UInt<1>("h00")) + node T_4108 = mux(T_3864, T_3984, UInt<1>("h00")) + node T_4110 = mux(T_3865, T_3986, UInt<1>("h00")) + node T_4112 = mux(T_3866, T_3988, UInt<1>("h00")) + node T_4114 = mux(T_3867, T_3990, UInt<1>("h00")) + node T_4116 = mux(T_3868, T_3992, UInt<1>("h00")) + node T_4118 = or(T_3994, T_3996) + node T_4119 = or(T_4118, T_3998) + node T_4120 = or(T_4119, T_4000) + node T_4121 = or(T_4120, T_4002) + node T_4122 = or(T_4121, T_4004) + node T_4123 = or(T_4122, T_4006) + node T_4124 = or(T_4123, T_4008) + node T_4125 = or(T_4124, T_4010) + node T_4126 = or(T_4125, T_4012) + node T_4127 = or(T_4126, T_4014) + node T_4128 = or(T_4127, T_4016) + node T_4129 = or(T_4128, T_4018) + node T_4130 = or(T_4129, T_4020) + node T_4131 = or(T_4130, T_4022) + node T_4132 = or(T_4131, T_4024) + node T_4133 = or(T_4132, T_4026) + node T_4134 = or(T_4133, T_4028) + node T_4135 = or(T_4134, T_4030) + node T_4136 = or(T_4135, T_4032) + node T_4137 = or(T_4136, T_4034) + node T_4138 = or(T_4137, T_4036) + node T_4139 = or(T_4138, T_4038) + node T_4140 = or(T_4139, T_4040) + node T_4141 = or(T_4140, T_4042) + node T_4142 = or(T_4141, T_4044) + node T_4143 = or(T_4142, T_4046) + node T_4144 = or(T_4143, T_4048) + node T_4145 = or(T_4144, T_4050) + node T_4146 = or(T_4145, T_4052) + node T_4147 = or(T_4146, T_4054) + node T_4148 = or(T_4147, T_4056) + node T_4149 = or(T_4148, T_4058) + node T_4150 = or(T_4149, T_4060) + node T_4151 = or(T_4150, T_4062) + node T_4152 = or(T_4151, T_4064) + node T_4153 = or(T_4152, T_4066) + node T_4154 = or(T_4153, T_4068) + node T_4155 = or(T_4154, T_4070) + node T_4156 = or(T_4155, T_4072) + node T_4157 = or(T_4156, T_4074) + node T_4158 = or(T_4157, T_4076) + node T_4159 = or(T_4158, T_4078) + node T_4160 = or(T_4159, T_4080) + node T_4161 = or(T_4160, T_4082) + node T_4162 = or(T_4161, T_4084) + node T_4163 = or(T_4162, T_4086) + node T_4164 = or(T_4163, T_4088) + node T_4165 = or(T_4164, T_4090) + node T_4166 = or(T_4165, T_4092) + node T_4167 = or(T_4166, T_4094) + node T_4168 = or(T_4167, T_4096) + node T_4169 = or(T_4168, T_4098) + node T_4170 = or(T_4169, T_4100) + node T_4171 = or(T_4170, T_4102) + node T_4172 = or(T_4171, T_4104) + node T_4173 = or(T_4172, T_4106) + node T_4174 = or(T_4173, T_4108) + node T_4175 = or(T_4174, T_4110) + node T_4176 = or(T_4175, T_4112) + node T_4177 = or(T_4176, T_4114) + node T_4178 = or(T_4177, T_4116) + wire T_4179 : UInt<12> + T_4179 is invalid + T_4179 <= T_4178 + node T_4180 = cat(T_3806, T_4179) + io.resp.bits.target <= T_4180 + node T_4181 = bits(hits, 61, 32) + node T_4182 = bits(hits, 31, 0) + node T_4184 = neq(T_4181, UInt<1>("h00")) + node T_4185 = or(T_4181, T_4182) + node T_4186 = bits(T_4185, 31, 16) + node T_4187 = bits(T_4185, 15, 0) + node T_4189 = neq(T_4186, UInt<1>("h00")) + node T_4190 = or(T_4186, T_4187) + node T_4191 = bits(T_4190, 15, 8) + node T_4192 = bits(T_4190, 7, 0) + node T_4194 = neq(T_4191, UInt<1>("h00")) + node T_4195 = or(T_4191, T_4192) + node T_4196 = bits(T_4195, 7, 4) + node T_4197 = bits(T_4195, 3, 0) + node T_4199 = neq(T_4196, UInt<1>("h00")) + node T_4200 = or(T_4196, T_4197) + node T_4201 = bits(T_4200, 3, 2) + node T_4202 = bits(T_4200, 1, 0) + node T_4204 = neq(T_4201, UInt<1>("h00")) + node T_4205 = or(T_4201, T_4202) + node T_4206 = bits(T_4205, 1, 1) + node T_4207 = cat(T_4204, T_4206) + node T_4208 = cat(T_4199, T_4207) + node T_4209 = cat(T_4194, T_4208) + node T_4210 = cat(T_4189, T_4209) + node T_4211 = cat(T_4184, T_4210) + io.resp.bits.entry <= T_4211 + infer mport T_4212 = brIdx[io.resp.bits.entry], clk + io.resp.bits.bridx <= T_4212 io.resp.bits.mask <= UInt<1>("h01") - cmem T_4233 : UInt<2>[128] - reg T_4235 : UInt<7>, clk, UInt<1>("h00"), T_4235 - node T_4236 = bit(hits, 0) - node T_4237 = bit(hits, 1) - node T_4238 = bit(hits, 2) - node T_4239 = bit(hits, 3) - node T_4240 = bit(hits, 4) - node T_4241 = bit(hits, 5) - node T_4242 = bit(hits, 6) - node T_4243 = bit(hits, 7) - node T_4244 = bit(hits, 8) - node T_4245 = bit(hits, 9) - node T_4246 = bit(hits, 10) - node T_4247 = bit(hits, 11) - node T_4248 = bit(hits, 12) - node T_4249 = bit(hits, 13) - node T_4250 = bit(hits, 14) - node T_4251 = bit(hits, 15) - node T_4252 = bit(hits, 16) - node T_4253 = bit(hits, 17) - node T_4254 = bit(hits, 18) - node T_4255 = bit(hits, 19) - node T_4256 = bit(hits, 20) - node T_4257 = bit(hits, 21) - node T_4258 = bit(hits, 22) - node T_4259 = bit(hits, 23) - node T_4260 = bit(hits, 24) - node T_4261 = bit(hits, 25) - node T_4262 = bit(hits, 26) - node T_4263 = bit(hits, 27) - node T_4264 = bit(hits, 28) - node T_4265 = bit(hits, 29) - node T_4266 = bit(hits, 30) - node T_4267 = bit(hits, 31) - node T_4268 = bit(hits, 32) - node T_4269 = bit(hits, 33) - node T_4270 = bit(hits, 34) - node T_4271 = bit(hits, 35) - node T_4272 = bit(hits, 36) - node T_4273 = bit(hits, 37) - node T_4274 = bit(hits, 38) - node T_4275 = bit(hits, 39) - node T_4276 = bit(hits, 40) - node T_4277 = bit(hits, 41) - node T_4278 = bit(hits, 42) - node T_4279 = bit(hits, 43) - node T_4280 = bit(hits, 44) - node T_4281 = bit(hits, 45) - node T_4282 = bit(hits, 46) - node T_4283 = bit(hits, 47) - node T_4284 = bit(hits, 48) - node T_4285 = bit(hits, 49) - node T_4286 = bit(hits, 50) - node T_4287 = bit(hits, 51) - node T_4288 = bit(hits, 52) - node T_4289 = bit(hits, 53) - node T_4290 = bit(hits, 54) - node T_4291 = bit(hits, 55) - node T_4292 = bit(hits, 56) - node T_4293 = bit(hits, 57) - node T_4294 = bit(hits, 58) - node T_4295 = bit(hits, 59) - node T_4296 = bit(hits, 60) - node T_4297 = bit(hits, 61) - node T_4299 = shl(isJump[0], 0) - node T_4300 = mux(T_4236, T_4299, UInt<1>("h00")) - node T_4302 = shl(isJump[1], 0) - node T_4303 = mux(T_4237, T_4302, UInt<1>("h00")) - node T_4305 = shl(isJump[2], 0) - node T_4306 = mux(T_4238, T_4305, UInt<1>("h00")) - node T_4308 = shl(isJump[3], 0) - node T_4309 = mux(T_4239, T_4308, UInt<1>("h00")) - node T_4311 = shl(isJump[4], 0) - node T_4312 = mux(T_4240, T_4311, UInt<1>("h00")) - node T_4314 = shl(isJump[5], 0) - node T_4315 = mux(T_4241, T_4314, UInt<1>("h00")) - node T_4317 = shl(isJump[6], 0) - node T_4318 = mux(T_4242, T_4317, UInt<1>("h00")) - node T_4320 = shl(isJump[7], 0) - node T_4321 = mux(T_4243, T_4320, UInt<1>("h00")) - node T_4323 = shl(isJump[8], 0) - node T_4324 = mux(T_4244, T_4323, UInt<1>("h00")) - node T_4326 = shl(isJump[9], 0) - node T_4327 = mux(T_4245, T_4326, UInt<1>("h00")) - node T_4329 = shl(isJump[10], 0) - node T_4330 = mux(T_4246, T_4329, UInt<1>("h00")) - node T_4332 = shl(isJump[11], 0) - node T_4333 = mux(T_4247, T_4332, UInt<1>("h00")) - node T_4335 = shl(isJump[12], 0) - node T_4336 = mux(T_4248, T_4335, UInt<1>("h00")) - node T_4338 = shl(isJump[13], 0) - node T_4339 = mux(T_4249, T_4338, UInt<1>("h00")) - node T_4341 = shl(isJump[14], 0) - node T_4342 = mux(T_4250, T_4341, UInt<1>("h00")) - node T_4344 = shl(isJump[15], 0) - node T_4345 = mux(T_4251, T_4344, UInt<1>("h00")) - node T_4347 = shl(isJump[16], 0) - node T_4348 = mux(T_4252, T_4347, UInt<1>("h00")) - node T_4350 = shl(isJump[17], 0) - node T_4351 = mux(T_4253, T_4350, UInt<1>("h00")) - node T_4353 = shl(isJump[18], 0) - node T_4354 = mux(T_4254, T_4353, UInt<1>("h00")) - node T_4356 = shl(isJump[19], 0) - node T_4357 = mux(T_4255, T_4356, UInt<1>("h00")) - node T_4359 = shl(isJump[20], 0) - node T_4360 = mux(T_4256, T_4359, UInt<1>("h00")) - node T_4362 = shl(isJump[21], 0) - node T_4363 = mux(T_4257, T_4362, UInt<1>("h00")) - node T_4365 = shl(isJump[22], 0) - node T_4366 = mux(T_4258, T_4365, UInt<1>("h00")) - node T_4368 = shl(isJump[23], 0) - node T_4369 = mux(T_4259, T_4368, UInt<1>("h00")) - node T_4371 = shl(isJump[24], 0) - node T_4372 = mux(T_4260, T_4371, UInt<1>("h00")) - node T_4374 = shl(isJump[25], 0) - node T_4375 = mux(T_4261, T_4374, UInt<1>("h00")) - node T_4377 = shl(isJump[26], 0) - node T_4378 = mux(T_4262, T_4377, UInt<1>("h00")) - node T_4380 = shl(isJump[27], 0) - node T_4381 = mux(T_4263, T_4380, UInt<1>("h00")) - node T_4383 = shl(isJump[28], 0) - node T_4384 = mux(T_4264, T_4383, UInt<1>("h00")) - node T_4386 = shl(isJump[29], 0) - node T_4387 = mux(T_4265, T_4386, UInt<1>("h00")) - node T_4389 = shl(isJump[30], 0) - node T_4390 = mux(T_4266, T_4389, UInt<1>("h00")) - node T_4392 = shl(isJump[31], 0) - node T_4393 = mux(T_4267, T_4392, UInt<1>("h00")) - node T_4395 = shl(isJump[32], 0) - node T_4396 = mux(T_4268, T_4395, UInt<1>("h00")) - node T_4398 = shl(isJump[33], 0) - node T_4399 = mux(T_4269, T_4398, UInt<1>("h00")) - node T_4401 = shl(isJump[34], 0) - node T_4402 = mux(T_4270, T_4401, UInt<1>("h00")) - node T_4404 = shl(isJump[35], 0) - node T_4405 = mux(T_4271, T_4404, UInt<1>("h00")) - node T_4407 = shl(isJump[36], 0) - node T_4408 = mux(T_4272, T_4407, UInt<1>("h00")) - node T_4410 = shl(isJump[37], 0) - node T_4411 = mux(T_4273, T_4410, UInt<1>("h00")) - node T_4413 = shl(isJump[38], 0) - node T_4414 = mux(T_4274, T_4413, UInt<1>("h00")) - node T_4416 = shl(isJump[39], 0) - node T_4417 = mux(T_4275, T_4416, UInt<1>("h00")) - node T_4419 = shl(isJump[40], 0) - node T_4420 = mux(T_4276, T_4419, UInt<1>("h00")) - node T_4422 = shl(isJump[41], 0) - node T_4423 = mux(T_4277, T_4422, UInt<1>("h00")) - node T_4425 = shl(isJump[42], 0) - node T_4426 = mux(T_4278, T_4425, UInt<1>("h00")) - node T_4428 = shl(isJump[43], 0) - node T_4429 = mux(T_4279, T_4428, UInt<1>("h00")) - node T_4431 = shl(isJump[44], 0) - node T_4432 = mux(T_4280, T_4431, UInt<1>("h00")) - node T_4434 = shl(isJump[45], 0) - node T_4435 = mux(T_4281, T_4434, UInt<1>("h00")) - node T_4437 = shl(isJump[46], 0) - node T_4438 = mux(T_4282, T_4437, UInt<1>("h00")) - node T_4440 = shl(isJump[47], 0) - node T_4441 = mux(T_4283, T_4440, UInt<1>("h00")) - node T_4443 = shl(isJump[48], 0) - node T_4444 = mux(T_4284, T_4443, UInt<1>("h00")) - node T_4446 = shl(isJump[49], 0) - node T_4447 = mux(T_4285, T_4446, UInt<1>("h00")) - node T_4449 = shl(isJump[50], 0) - node T_4450 = mux(T_4286, T_4449, UInt<1>("h00")) - node T_4452 = shl(isJump[51], 0) - node T_4453 = mux(T_4287, T_4452, UInt<1>("h00")) - node T_4455 = shl(isJump[52], 0) - node T_4456 = mux(T_4288, T_4455, UInt<1>("h00")) - node T_4458 = shl(isJump[53], 0) - node T_4459 = mux(T_4289, T_4458, UInt<1>("h00")) - node T_4461 = shl(isJump[54], 0) - node T_4462 = mux(T_4290, T_4461, UInt<1>("h00")) - node T_4464 = shl(isJump[55], 0) - node T_4465 = mux(T_4291, T_4464, UInt<1>("h00")) - node T_4467 = shl(isJump[56], 0) - node T_4468 = mux(T_4292, T_4467, UInt<1>("h00")) - node T_4470 = shl(isJump[57], 0) - node T_4471 = mux(T_4293, T_4470, UInt<1>("h00")) - node T_4473 = shl(isJump[58], 0) - node T_4474 = mux(T_4294, T_4473, UInt<1>("h00")) - node T_4476 = shl(isJump[59], 0) - node T_4477 = mux(T_4295, T_4476, UInt<1>("h00")) - node T_4479 = shl(isJump[60], 0) - node T_4480 = mux(T_4296, T_4479, UInt<1>("h00")) - node T_4482 = shl(isJump[61], 0) - node T_4483 = mux(T_4297, T_4482, UInt<1>("h00")) - node T_4485 = or(T_4300, T_4303) - node T_4486 = or(T_4485, T_4306) - node T_4487 = or(T_4486, T_4309) - node T_4488 = or(T_4487, T_4312) - node T_4489 = or(T_4488, T_4315) - node T_4490 = or(T_4489, T_4318) - node T_4491 = or(T_4490, T_4321) - node T_4492 = or(T_4491, T_4324) - node T_4493 = or(T_4492, T_4327) - node T_4494 = or(T_4493, T_4330) - node T_4495 = or(T_4494, T_4333) - node T_4496 = or(T_4495, T_4336) - node T_4497 = or(T_4496, T_4339) - node T_4498 = or(T_4497, T_4342) - node T_4499 = or(T_4498, T_4345) - node T_4500 = or(T_4499, T_4348) - node T_4501 = or(T_4500, T_4351) - node T_4502 = or(T_4501, T_4354) - node T_4503 = or(T_4502, T_4357) - node T_4504 = or(T_4503, T_4360) - node T_4505 = or(T_4504, T_4363) - node T_4506 = or(T_4505, T_4366) - node T_4507 = or(T_4506, T_4369) - node T_4508 = or(T_4507, T_4372) - node T_4509 = or(T_4508, T_4375) - node T_4510 = or(T_4509, T_4378) - node T_4511 = or(T_4510, T_4381) - node T_4512 = or(T_4511, T_4384) - node T_4513 = or(T_4512, T_4387) - node T_4514 = or(T_4513, T_4390) - node T_4515 = or(T_4514, T_4393) - node T_4516 = or(T_4515, T_4396) - node T_4517 = or(T_4516, T_4399) - node T_4518 = or(T_4517, T_4402) - node T_4519 = or(T_4518, T_4405) - node T_4520 = or(T_4519, T_4408) - node T_4521 = or(T_4520, T_4411) - node T_4522 = or(T_4521, T_4414) - node T_4523 = or(T_4522, T_4417) - node T_4524 = or(T_4523, T_4420) - node T_4525 = or(T_4524, T_4423) - node T_4526 = or(T_4525, T_4426) - node T_4527 = or(T_4526, T_4429) - node T_4528 = or(T_4527, T_4432) - node T_4529 = or(T_4528, T_4435) - node T_4530 = or(T_4529, T_4438) - node T_4531 = or(T_4530, T_4441) - node T_4532 = or(T_4531, T_4444) - node T_4533 = or(T_4532, T_4447) - node T_4534 = or(T_4533, T_4450) - node T_4535 = or(T_4534, T_4453) - node T_4536 = or(T_4535, T_4456) - node T_4537 = or(T_4536, T_4459) - node T_4538 = or(T_4537, T_4462) - node T_4539 = or(T_4538, T_4465) - node T_4540 = or(T_4539, T_4468) - node T_4541 = or(T_4540, T_4471) - node T_4542 = or(T_4541, T_4474) - node T_4543 = or(T_4542, T_4477) - node T_4544 = or(T_4543, T_4480) - node T_4545 = or(T_4544, T_4483) - wire T_4546 : UInt<1> - T_4546 <= UInt<1>("h00") - T_4546 <= T_4545 - node T_4549 = eq(T_4546, UInt<1>("h00")) - node T_4550 = and(io.req.valid, io.resp.valid) - node T_4551 = and(T_4550, T_4549) - wire T_4555 : {history : UInt<7>, value : UInt<2>} - T_4555.value <= UInt<1>("h00") - T_4555.history <= UInt<1>("h00") - node T_4560 = bits(io.req.bits.addr, 8, 2) - node T_4561 = xor(T_4560, T_4235) - infer mport T_4562 = T_4233[T_4561], clk - T_4555.value <= T_4562 - T_4555.history <= T_4235 - node T_4563 = bit(T_4555.value, 0) - when T_4551 : - node T_4564 = bits(T_4235, 6, 1) - node T_4565 = cat(T_4563, T_4564) - T_4235 <= T_4565 - skip - node T_4566 = and(io.bht_update.valid, io.bht_update.bits.prediction.valid) - when T_4566 : - node T_4567 = bits(io.bht_update.bits.pc, 8, 2) - node T_4568 = xor(T_4567, io.bht_update.bits.prediction.bits.bht.history) - infer mport T_4569 = T_4233[T_4568], clk - node T_4570 = bit(io.bht_update.bits.prediction.bits.bht.value, 1) - node T_4571 = bit(io.bht_update.bits.prediction.bits.bht.value, 0) - node T_4572 = and(T_4570, T_4571) - node T_4573 = bit(io.bht_update.bits.prediction.bits.bht.value, 1) - node T_4574 = bit(io.bht_update.bits.prediction.bits.bht.value, 0) - node T_4575 = or(T_4573, T_4574) - node T_4576 = and(T_4575, io.bht_update.bits.taken) - node T_4577 = or(T_4572, T_4576) - node T_4578 = cat(io.bht_update.bits.taken, T_4577) - T_4569 <= T_4578 + cmem T_4216 : UInt<2>[128] + reg T_4218 : UInt<7>, clk + node T_4219 = bits(hits, 0, 0) + node T_4220 = bits(hits, 1, 1) + node T_4221 = bits(hits, 2, 2) + node T_4222 = bits(hits, 3, 3) + node T_4223 = bits(hits, 4, 4) + node T_4224 = bits(hits, 5, 5) + node T_4225 = bits(hits, 6, 6) + node T_4226 = bits(hits, 7, 7) + node T_4227 = bits(hits, 8, 8) + node T_4228 = bits(hits, 9, 9) + node T_4229 = bits(hits, 10, 10) + node T_4230 = bits(hits, 11, 11) + node T_4231 = bits(hits, 12, 12) + node T_4232 = bits(hits, 13, 13) + node T_4233 = bits(hits, 14, 14) + node T_4234 = bits(hits, 15, 15) + node T_4235 = bits(hits, 16, 16) + node T_4236 = bits(hits, 17, 17) + node T_4237 = bits(hits, 18, 18) + node T_4238 = bits(hits, 19, 19) + node T_4239 = bits(hits, 20, 20) + node T_4240 = bits(hits, 21, 21) + node T_4241 = bits(hits, 22, 22) + node T_4242 = bits(hits, 23, 23) + node T_4243 = bits(hits, 24, 24) + node T_4244 = bits(hits, 25, 25) + node T_4245 = bits(hits, 26, 26) + node T_4246 = bits(hits, 27, 27) + node T_4247 = bits(hits, 28, 28) + node T_4248 = bits(hits, 29, 29) + node T_4249 = bits(hits, 30, 30) + node T_4250 = bits(hits, 31, 31) + node T_4251 = bits(hits, 32, 32) + node T_4252 = bits(hits, 33, 33) + node T_4253 = bits(hits, 34, 34) + node T_4254 = bits(hits, 35, 35) + node T_4255 = bits(hits, 36, 36) + node T_4256 = bits(hits, 37, 37) + node T_4257 = bits(hits, 38, 38) + node T_4258 = bits(hits, 39, 39) + node T_4259 = bits(hits, 40, 40) + node T_4260 = bits(hits, 41, 41) + node T_4261 = bits(hits, 42, 42) + node T_4262 = bits(hits, 43, 43) + node T_4263 = bits(hits, 44, 44) + node T_4264 = bits(hits, 45, 45) + node T_4265 = bits(hits, 46, 46) + node T_4266 = bits(hits, 47, 47) + node T_4267 = bits(hits, 48, 48) + node T_4268 = bits(hits, 49, 49) + node T_4269 = bits(hits, 50, 50) + node T_4270 = bits(hits, 51, 51) + node T_4271 = bits(hits, 52, 52) + node T_4272 = bits(hits, 53, 53) + node T_4273 = bits(hits, 54, 54) + node T_4274 = bits(hits, 55, 55) + node T_4275 = bits(hits, 56, 56) + node T_4276 = bits(hits, 57, 57) + node T_4277 = bits(hits, 58, 58) + node T_4278 = bits(hits, 59, 59) + node T_4279 = bits(hits, 60, 60) + node T_4280 = bits(hits, 61, 61) + node T_4282 = shl(isJump[0], 0) + node T_4283 = mux(T_4219, T_4282, UInt<1>("h00")) + node T_4285 = shl(isJump[1], 0) + node T_4286 = mux(T_4220, T_4285, UInt<1>("h00")) + node T_4288 = shl(isJump[2], 0) + node T_4289 = mux(T_4221, T_4288, UInt<1>("h00")) + node T_4291 = shl(isJump[3], 0) + node T_4292 = mux(T_4222, T_4291, UInt<1>("h00")) + node T_4294 = shl(isJump[4], 0) + node T_4295 = mux(T_4223, T_4294, UInt<1>("h00")) + node T_4297 = shl(isJump[5], 0) + node T_4298 = mux(T_4224, T_4297, UInt<1>("h00")) + node T_4300 = shl(isJump[6], 0) + node T_4301 = mux(T_4225, T_4300, UInt<1>("h00")) + node T_4303 = shl(isJump[7], 0) + node T_4304 = mux(T_4226, T_4303, UInt<1>("h00")) + node T_4306 = shl(isJump[8], 0) + node T_4307 = mux(T_4227, T_4306, UInt<1>("h00")) + node T_4309 = shl(isJump[9], 0) + node T_4310 = mux(T_4228, T_4309, UInt<1>("h00")) + node T_4312 = shl(isJump[10], 0) + node T_4313 = mux(T_4229, T_4312, UInt<1>("h00")) + node T_4315 = shl(isJump[11], 0) + node T_4316 = mux(T_4230, T_4315, UInt<1>("h00")) + node T_4318 = shl(isJump[12], 0) + node T_4319 = mux(T_4231, T_4318, UInt<1>("h00")) + node T_4321 = shl(isJump[13], 0) + node T_4322 = mux(T_4232, T_4321, UInt<1>("h00")) + node T_4324 = shl(isJump[14], 0) + node T_4325 = mux(T_4233, T_4324, UInt<1>("h00")) + node T_4327 = shl(isJump[15], 0) + node T_4328 = mux(T_4234, T_4327, UInt<1>("h00")) + node T_4330 = shl(isJump[16], 0) + node T_4331 = mux(T_4235, T_4330, UInt<1>("h00")) + node T_4333 = shl(isJump[17], 0) + node T_4334 = mux(T_4236, T_4333, UInt<1>("h00")) + node T_4336 = shl(isJump[18], 0) + node T_4337 = mux(T_4237, T_4336, UInt<1>("h00")) + node T_4339 = shl(isJump[19], 0) + node T_4340 = mux(T_4238, T_4339, UInt<1>("h00")) + node T_4342 = shl(isJump[20], 0) + node T_4343 = mux(T_4239, T_4342, UInt<1>("h00")) + node T_4345 = shl(isJump[21], 0) + node T_4346 = mux(T_4240, T_4345, UInt<1>("h00")) + node T_4348 = shl(isJump[22], 0) + node T_4349 = mux(T_4241, T_4348, UInt<1>("h00")) + node T_4351 = shl(isJump[23], 0) + node T_4352 = mux(T_4242, T_4351, UInt<1>("h00")) + node T_4354 = shl(isJump[24], 0) + node T_4355 = mux(T_4243, T_4354, UInt<1>("h00")) + node T_4357 = shl(isJump[25], 0) + node T_4358 = mux(T_4244, T_4357, UInt<1>("h00")) + node T_4360 = shl(isJump[26], 0) + node T_4361 = mux(T_4245, T_4360, UInt<1>("h00")) + node T_4363 = shl(isJump[27], 0) + node T_4364 = mux(T_4246, T_4363, UInt<1>("h00")) + node T_4366 = shl(isJump[28], 0) + node T_4367 = mux(T_4247, T_4366, UInt<1>("h00")) + node T_4369 = shl(isJump[29], 0) + node T_4370 = mux(T_4248, T_4369, UInt<1>("h00")) + node T_4372 = shl(isJump[30], 0) + node T_4373 = mux(T_4249, T_4372, UInt<1>("h00")) + node T_4375 = shl(isJump[31], 0) + node T_4376 = mux(T_4250, T_4375, UInt<1>("h00")) + node T_4378 = shl(isJump[32], 0) + node T_4379 = mux(T_4251, T_4378, UInt<1>("h00")) + node T_4381 = shl(isJump[33], 0) + node T_4382 = mux(T_4252, T_4381, UInt<1>("h00")) + node T_4384 = shl(isJump[34], 0) + node T_4385 = mux(T_4253, T_4384, UInt<1>("h00")) + node T_4387 = shl(isJump[35], 0) + node T_4388 = mux(T_4254, T_4387, UInt<1>("h00")) + node T_4390 = shl(isJump[36], 0) + node T_4391 = mux(T_4255, T_4390, UInt<1>("h00")) + node T_4393 = shl(isJump[37], 0) + node T_4394 = mux(T_4256, T_4393, UInt<1>("h00")) + node T_4396 = shl(isJump[38], 0) + node T_4397 = mux(T_4257, T_4396, UInt<1>("h00")) + node T_4399 = shl(isJump[39], 0) + node T_4400 = mux(T_4258, T_4399, UInt<1>("h00")) + node T_4402 = shl(isJump[40], 0) + node T_4403 = mux(T_4259, T_4402, UInt<1>("h00")) + node T_4405 = shl(isJump[41], 0) + node T_4406 = mux(T_4260, T_4405, UInt<1>("h00")) + node T_4408 = shl(isJump[42], 0) + node T_4409 = mux(T_4261, T_4408, UInt<1>("h00")) + node T_4411 = shl(isJump[43], 0) + node T_4412 = mux(T_4262, T_4411, UInt<1>("h00")) + node T_4414 = shl(isJump[44], 0) + node T_4415 = mux(T_4263, T_4414, UInt<1>("h00")) + node T_4417 = shl(isJump[45], 0) + node T_4418 = mux(T_4264, T_4417, UInt<1>("h00")) + node T_4420 = shl(isJump[46], 0) + node T_4421 = mux(T_4265, T_4420, UInt<1>("h00")) + node T_4423 = shl(isJump[47], 0) + node T_4424 = mux(T_4266, T_4423, UInt<1>("h00")) + node T_4426 = shl(isJump[48], 0) + node T_4427 = mux(T_4267, T_4426, UInt<1>("h00")) + node T_4429 = shl(isJump[49], 0) + node T_4430 = mux(T_4268, T_4429, UInt<1>("h00")) + node T_4432 = shl(isJump[50], 0) + node T_4433 = mux(T_4269, T_4432, UInt<1>("h00")) + node T_4435 = shl(isJump[51], 0) + node T_4436 = mux(T_4270, T_4435, UInt<1>("h00")) + node T_4438 = shl(isJump[52], 0) + node T_4439 = mux(T_4271, T_4438, UInt<1>("h00")) + node T_4441 = shl(isJump[53], 0) + node T_4442 = mux(T_4272, T_4441, UInt<1>("h00")) + node T_4444 = shl(isJump[54], 0) + node T_4445 = mux(T_4273, T_4444, UInt<1>("h00")) + node T_4447 = shl(isJump[55], 0) + node T_4448 = mux(T_4274, T_4447, UInt<1>("h00")) + node T_4450 = shl(isJump[56], 0) + node T_4451 = mux(T_4275, T_4450, UInt<1>("h00")) + node T_4453 = shl(isJump[57], 0) + node T_4454 = mux(T_4276, T_4453, UInt<1>("h00")) + node T_4456 = shl(isJump[58], 0) + node T_4457 = mux(T_4277, T_4456, UInt<1>("h00")) + node T_4459 = shl(isJump[59], 0) + node T_4460 = mux(T_4278, T_4459, UInt<1>("h00")) + node T_4462 = shl(isJump[60], 0) + node T_4463 = mux(T_4279, T_4462, UInt<1>("h00")) + node T_4465 = shl(isJump[61], 0) + node T_4466 = mux(T_4280, T_4465, UInt<1>("h00")) + node T_4468 = or(T_4283, T_4286) + node T_4469 = or(T_4468, T_4289) + node T_4470 = or(T_4469, T_4292) + node T_4471 = or(T_4470, T_4295) + node T_4472 = or(T_4471, T_4298) + node T_4473 = or(T_4472, T_4301) + node T_4474 = or(T_4473, T_4304) + node T_4475 = or(T_4474, T_4307) + node T_4476 = or(T_4475, T_4310) + node T_4477 = or(T_4476, T_4313) + node T_4478 = or(T_4477, T_4316) + node T_4479 = or(T_4478, T_4319) + node T_4480 = or(T_4479, T_4322) + node T_4481 = or(T_4480, T_4325) + node T_4482 = or(T_4481, T_4328) + node T_4483 = or(T_4482, T_4331) + node T_4484 = or(T_4483, T_4334) + node T_4485 = or(T_4484, T_4337) + node T_4486 = or(T_4485, T_4340) + node T_4487 = or(T_4486, T_4343) + node T_4488 = or(T_4487, T_4346) + node T_4489 = or(T_4488, T_4349) + node T_4490 = or(T_4489, T_4352) + node T_4491 = or(T_4490, T_4355) + node T_4492 = or(T_4491, T_4358) + node T_4493 = or(T_4492, T_4361) + node T_4494 = or(T_4493, T_4364) + node T_4495 = or(T_4494, T_4367) + node T_4496 = or(T_4495, T_4370) + node T_4497 = or(T_4496, T_4373) + node T_4498 = or(T_4497, T_4376) + node T_4499 = or(T_4498, T_4379) + node T_4500 = or(T_4499, T_4382) + node T_4501 = or(T_4500, T_4385) + node T_4502 = or(T_4501, T_4388) + node T_4503 = or(T_4502, T_4391) + node T_4504 = or(T_4503, T_4394) + node T_4505 = or(T_4504, T_4397) + node T_4506 = or(T_4505, T_4400) + node T_4507 = or(T_4506, T_4403) + node T_4508 = or(T_4507, T_4406) + node T_4509 = or(T_4508, T_4409) + node T_4510 = or(T_4509, T_4412) + node T_4511 = or(T_4510, T_4415) + node T_4512 = or(T_4511, T_4418) + node T_4513 = or(T_4512, T_4421) + node T_4514 = or(T_4513, T_4424) + node T_4515 = or(T_4514, T_4427) + node T_4516 = or(T_4515, T_4430) + node T_4517 = or(T_4516, T_4433) + node T_4518 = or(T_4517, T_4436) + node T_4519 = or(T_4518, T_4439) + node T_4520 = or(T_4519, T_4442) + node T_4521 = or(T_4520, T_4445) + node T_4522 = or(T_4521, T_4448) + node T_4523 = or(T_4522, T_4451) + node T_4524 = or(T_4523, T_4454) + node T_4525 = or(T_4524, T_4457) + node T_4526 = or(T_4525, T_4460) + node T_4527 = or(T_4526, T_4463) + node T_4528 = or(T_4527, T_4466) + wire T_4529 : UInt<1> + T_4529 is invalid + T_4529 <= T_4528 + node T_4531 = eq(T_4529, UInt<1>("h00")) + node T_4532 = and(io.req.valid, io.resp.valid) + node T_4533 = and(T_4532, T_4531) + wire T_4537 : {history : UInt<7>, value : UInt<2>} + T_4537 is invalid + node T_4540 = bits(io.req.bits.addr, 8, 2) + node T_4541 = xor(T_4540, T_4218) + infer mport T_4542 = T_4216[T_4541], clk + T_4537.value <= T_4542 + T_4537.history <= T_4218 + node T_4543 = bits(T_4537.value, 0, 0) + when T_4533 : + node T_4544 = bits(T_4218, 6, 1) + node T_4545 = cat(T_4543, T_4544) + T_4218 <= T_4545 + skip + node T_4546 = and(io.bht_update.valid, io.bht_update.bits.prediction.valid) + when T_4546 : + node T_4547 = bits(io.bht_update.bits.pc, 8, 2) + node T_4548 = xor(T_4547, io.bht_update.bits.prediction.bits.bht.history) + infer mport T_4549 = T_4216[T_4548], clk + node T_4550 = bits(io.bht_update.bits.prediction.bits.bht.value, 1, 1) + node T_4551 = bits(io.bht_update.bits.prediction.bits.bht.value, 0, 0) + node T_4552 = and(T_4550, T_4551) + node T_4553 = bits(io.bht_update.bits.prediction.bits.bht.value, 1, 1) + node T_4554 = bits(io.bht_update.bits.prediction.bits.bht.value, 0, 0) + node T_4555 = or(T_4553, T_4554) + node T_4556 = and(T_4555, io.bht_update.bits.taken) + node T_4557 = or(T_4552, T_4556) + node T_4558 = cat(io.bht_update.bits.taken, T_4557) + T_4549 <= T_4558 when io.bht_update.bits.mispredict : - node T_4579 = bits(io.bht_update.bits.prediction.bits.bht.history, 6, 1) - node T_4580 = cat(io.bht_update.bits.taken, T_4579) - T_4235 <= T_4580 + node T_4559 = bits(io.bht_update.bits.prediction.bits.bht.history, 6, 1) + node T_4560 = cat(io.bht_update.bits.taken, T_4559) + T_4218 <= T_4560 skip skip - node T_4581 = bit(T_4555.value, 0) - node T_4583 = eq(T_4581, UInt<1>("h00")) - node T_4584 = and(T_4583, T_4549) - when T_4584 : + node T_4561 = bits(T_4537.value, 0, 0) + node T_4563 = eq(T_4561, UInt<1>("h00")) + node T_4564 = and(T_4563, T_4531) + when T_4564 : io.resp.bits.taken <= UInt<1>("h00") skip - io.resp.bits.bht <- T_4555 - reg T_4587 : UInt<2>, clk, reset, UInt<2>("h00") - reg T_4589 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_4598 : UInt<?>[2], clk, UInt<1>("h00"), T_4598 - node T_4602 = bit(hits, 0) - node T_4603 = bit(hits, 1) - node T_4604 = bit(hits, 2) - node T_4605 = bit(hits, 3) - node T_4606 = bit(hits, 4) - node T_4607 = bit(hits, 5) - node T_4608 = bit(hits, 6) - node T_4609 = bit(hits, 7) - node T_4610 = bit(hits, 8) - node T_4611 = bit(hits, 9) - node T_4612 = bit(hits, 10) - node T_4613 = bit(hits, 11) - node T_4614 = bit(hits, 12) - node T_4615 = bit(hits, 13) - node T_4616 = bit(hits, 14) - node T_4617 = bit(hits, 15) - node T_4618 = bit(hits, 16) - node T_4619 = bit(hits, 17) - node T_4620 = bit(hits, 18) - node T_4621 = bit(hits, 19) - node T_4622 = bit(hits, 20) - node T_4623 = bit(hits, 21) - node T_4624 = bit(hits, 22) - node T_4625 = bit(hits, 23) - node T_4626 = bit(hits, 24) - node T_4627 = bit(hits, 25) - node T_4628 = bit(hits, 26) - node T_4629 = bit(hits, 27) - node T_4630 = bit(hits, 28) - node T_4631 = bit(hits, 29) - node T_4632 = bit(hits, 30) - node T_4633 = bit(hits, 31) - node T_4634 = bit(hits, 32) - node T_4635 = bit(hits, 33) - node T_4636 = bit(hits, 34) - node T_4637 = bit(hits, 35) - node T_4638 = bit(hits, 36) - node T_4639 = bit(hits, 37) - node T_4640 = bit(hits, 38) - node T_4641 = bit(hits, 39) - node T_4642 = bit(hits, 40) - node T_4643 = bit(hits, 41) - node T_4644 = bit(hits, 42) - node T_4645 = bit(hits, 43) - node T_4646 = bit(hits, 44) - node T_4647 = bit(hits, 45) - node T_4648 = bit(hits, 46) - node T_4649 = bit(hits, 47) - node T_4650 = bit(hits, 48) - node T_4651 = bit(hits, 49) - node T_4652 = bit(hits, 50) - node T_4653 = bit(hits, 51) - node T_4654 = bit(hits, 52) - node T_4655 = bit(hits, 53) - node T_4656 = bit(hits, 54) - node T_4657 = bit(hits, 55) - node T_4658 = bit(hits, 56) - node T_4659 = bit(hits, 57) - node T_4660 = bit(hits, 58) - node T_4661 = bit(hits, 59) - node T_4662 = bit(hits, 60) - node T_4663 = bit(hits, 61) - node T_4665 = shl(useRAS[0], 0) - node T_4666 = mux(T_4602, T_4665, UInt<1>("h00")) - node T_4668 = shl(useRAS[1], 0) - node T_4669 = mux(T_4603, T_4668, UInt<1>("h00")) - node T_4671 = shl(useRAS[2], 0) - node T_4672 = mux(T_4604, T_4671, UInt<1>("h00")) - node T_4674 = shl(useRAS[3], 0) - node T_4675 = mux(T_4605, T_4674, UInt<1>("h00")) - node T_4677 = shl(useRAS[4], 0) - node T_4678 = mux(T_4606, T_4677, UInt<1>("h00")) - node T_4680 = shl(useRAS[5], 0) - node T_4681 = mux(T_4607, T_4680, UInt<1>("h00")) - node T_4683 = shl(useRAS[6], 0) - node T_4684 = mux(T_4608, T_4683, UInt<1>("h00")) - node T_4686 = shl(useRAS[7], 0) - node T_4687 = mux(T_4609, T_4686, UInt<1>("h00")) - node T_4689 = shl(useRAS[8], 0) - node T_4690 = mux(T_4610, T_4689, UInt<1>("h00")) - node T_4692 = shl(useRAS[9], 0) - node T_4693 = mux(T_4611, T_4692, UInt<1>("h00")) - node T_4695 = shl(useRAS[10], 0) - node T_4696 = mux(T_4612, T_4695, UInt<1>("h00")) - node T_4698 = shl(useRAS[11], 0) - node T_4699 = mux(T_4613, T_4698, UInt<1>("h00")) - node T_4701 = shl(useRAS[12], 0) - node T_4702 = mux(T_4614, T_4701, UInt<1>("h00")) - node T_4704 = shl(useRAS[13], 0) - node T_4705 = mux(T_4615, T_4704, UInt<1>("h00")) - node T_4707 = shl(useRAS[14], 0) - node T_4708 = mux(T_4616, T_4707, UInt<1>("h00")) - node T_4710 = shl(useRAS[15], 0) - node T_4711 = mux(T_4617, T_4710, UInt<1>("h00")) - node T_4713 = shl(useRAS[16], 0) - node T_4714 = mux(T_4618, T_4713, UInt<1>("h00")) - node T_4716 = shl(useRAS[17], 0) - node T_4717 = mux(T_4619, T_4716, UInt<1>("h00")) - node T_4719 = shl(useRAS[18], 0) - node T_4720 = mux(T_4620, T_4719, UInt<1>("h00")) - node T_4722 = shl(useRAS[19], 0) - node T_4723 = mux(T_4621, T_4722, UInt<1>("h00")) - node T_4725 = shl(useRAS[20], 0) - node T_4726 = mux(T_4622, T_4725, UInt<1>("h00")) - node T_4728 = shl(useRAS[21], 0) - node T_4729 = mux(T_4623, T_4728, UInt<1>("h00")) - node T_4731 = shl(useRAS[22], 0) - node T_4732 = mux(T_4624, T_4731, UInt<1>("h00")) - node T_4734 = shl(useRAS[23], 0) - node T_4735 = mux(T_4625, T_4734, UInt<1>("h00")) - node T_4737 = shl(useRAS[24], 0) - node T_4738 = mux(T_4626, T_4737, UInt<1>("h00")) - node T_4740 = shl(useRAS[25], 0) - node T_4741 = mux(T_4627, T_4740, UInt<1>("h00")) - node T_4743 = shl(useRAS[26], 0) - node T_4744 = mux(T_4628, T_4743, UInt<1>("h00")) - node T_4746 = shl(useRAS[27], 0) - node T_4747 = mux(T_4629, T_4746, UInt<1>("h00")) - node T_4749 = shl(useRAS[28], 0) - node T_4750 = mux(T_4630, T_4749, UInt<1>("h00")) - node T_4752 = shl(useRAS[29], 0) - node T_4753 = mux(T_4631, T_4752, UInt<1>("h00")) - node T_4755 = shl(useRAS[30], 0) - node T_4756 = mux(T_4632, T_4755, UInt<1>("h00")) - node T_4758 = shl(useRAS[31], 0) - node T_4759 = mux(T_4633, T_4758, UInt<1>("h00")) - node T_4761 = shl(useRAS[32], 0) - node T_4762 = mux(T_4634, T_4761, UInt<1>("h00")) - node T_4764 = shl(useRAS[33], 0) - node T_4765 = mux(T_4635, T_4764, UInt<1>("h00")) - node T_4767 = shl(useRAS[34], 0) - node T_4768 = mux(T_4636, T_4767, UInt<1>("h00")) - node T_4770 = shl(useRAS[35], 0) - node T_4771 = mux(T_4637, T_4770, UInt<1>("h00")) - node T_4773 = shl(useRAS[36], 0) - node T_4774 = mux(T_4638, T_4773, UInt<1>("h00")) - node T_4776 = shl(useRAS[37], 0) - node T_4777 = mux(T_4639, T_4776, UInt<1>("h00")) - node T_4779 = shl(useRAS[38], 0) - node T_4780 = mux(T_4640, T_4779, UInt<1>("h00")) - node T_4782 = shl(useRAS[39], 0) - node T_4783 = mux(T_4641, T_4782, UInt<1>("h00")) - node T_4785 = shl(useRAS[40], 0) - node T_4786 = mux(T_4642, T_4785, UInt<1>("h00")) - node T_4788 = shl(useRAS[41], 0) - node T_4789 = mux(T_4643, T_4788, UInt<1>("h00")) - node T_4791 = shl(useRAS[42], 0) - node T_4792 = mux(T_4644, T_4791, UInt<1>("h00")) - node T_4794 = shl(useRAS[43], 0) - node T_4795 = mux(T_4645, T_4794, UInt<1>("h00")) - node T_4797 = shl(useRAS[44], 0) - node T_4798 = mux(T_4646, T_4797, UInt<1>("h00")) - node T_4800 = shl(useRAS[45], 0) - node T_4801 = mux(T_4647, T_4800, UInt<1>("h00")) - node T_4803 = shl(useRAS[46], 0) - node T_4804 = mux(T_4648, T_4803, UInt<1>("h00")) - node T_4806 = shl(useRAS[47], 0) - node T_4807 = mux(T_4649, T_4806, UInt<1>("h00")) - node T_4809 = shl(useRAS[48], 0) - node T_4810 = mux(T_4650, T_4809, UInt<1>("h00")) - node T_4812 = shl(useRAS[49], 0) - node T_4813 = mux(T_4651, T_4812, UInt<1>("h00")) - node T_4815 = shl(useRAS[50], 0) - node T_4816 = mux(T_4652, T_4815, UInt<1>("h00")) - node T_4818 = shl(useRAS[51], 0) - node T_4819 = mux(T_4653, T_4818, UInt<1>("h00")) - node T_4821 = shl(useRAS[52], 0) - node T_4822 = mux(T_4654, T_4821, UInt<1>("h00")) - node T_4824 = shl(useRAS[53], 0) - node T_4825 = mux(T_4655, T_4824, UInt<1>("h00")) - node T_4827 = shl(useRAS[54], 0) - node T_4828 = mux(T_4656, T_4827, UInt<1>("h00")) - node T_4830 = shl(useRAS[55], 0) - node T_4831 = mux(T_4657, T_4830, UInt<1>("h00")) - node T_4833 = shl(useRAS[56], 0) - node T_4834 = mux(T_4658, T_4833, UInt<1>("h00")) - node T_4836 = shl(useRAS[57], 0) - node T_4837 = mux(T_4659, T_4836, UInt<1>("h00")) - node T_4839 = shl(useRAS[58], 0) - node T_4840 = mux(T_4660, T_4839, UInt<1>("h00")) - node T_4842 = shl(useRAS[59], 0) - node T_4843 = mux(T_4661, T_4842, UInt<1>("h00")) - node T_4845 = shl(useRAS[60], 0) - node T_4846 = mux(T_4662, T_4845, UInt<1>("h00")) - node T_4848 = shl(useRAS[61], 0) - node T_4849 = mux(T_4663, T_4848, UInt<1>("h00")) - node T_4851 = or(T_4666, T_4669) - node T_4852 = or(T_4851, T_4672) - node T_4853 = or(T_4852, T_4675) - node T_4854 = or(T_4853, T_4678) - node T_4855 = or(T_4854, T_4681) - node T_4856 = or(T_4855, T_4684) - node T_4857 = or(T_4856, T_4687) - node T_4858 = or(T_4857, T_4690) - node T_4859 = or(T_4858, T_4693) - node T_4860 = or(T_4859, T_4696) - node T_4861 = or(T_4860, T_4699) - node T_4862 = or(T_4861, T_4702) - node T_4863 = or(T_4862, T_4705) - node T_4864 = or(T_4863, T_4708) - node T_4865 = or(T_4864, T_4711) - node T_4866 = or(T_4865, T_4714) - node T_4867 = or(T_4866, T_4717) - node T_4868 = or(T_4867, T_4720) - node T_4869 = or(T_4868, T_4723) - node T_4870 = or(T_4869, T_4726) - node T_4871 = or(T_4870, T_4729) - node T_4872 = or(T_4871, T_4732) - node T_4873 = or(T_4872, T_4735) - node T_4874 = or(T_4873, T_4738) - node T_4875 = or(T_4874, T_4741) - node T_4876 = or(T_4875, T_4744) - node T_4877 = or(T_4876, T_4747) - node T_4878 = or(T_4877, T_4750) - node T_4879 = or(T_4878, T_4753) - node T_4880 = or(T_4879, T_4756) - node T_4881 = or(T_4880, T_4759) - node T_4882 = or(T_4881, T_4762) - node T_4883 = or(T_4882, T_4765) - node T_4884 = or(T_4883, T_4768) - node T_4885 = or(T_4884, T_4771) - node T_4886 = or(T_4885, T_4774) - node T_4887 = or(T_4886, T_4777) - node T_4888 = or(T_4887, T_4780) - node T_4889 = or(T_4888, T_4783) - node T_4890 = or(T_4889, T_4786) - node T_4891 = or(T_4890, T_4789) - node T_4892 = or(T_4891, T_4792) - node T_4893 = or(T_4892, T_4795) - node T_4894 = or(T_4893, T_4798) - node T_4895 = or(T_4894, T_4801) - node T_4896 = or(T_4895, T_4804) - node T_4897 = or(T_4896, T_4807) - node T_4898 = or(T_4897, T_4810) - node T_4899 = or(T_4898, T_4813) - node T_4900 = or(T_4899, T_4816) - node T_4901 = or(T_4900, T_4819) - node T_4902 = or(T_4901, T_4822) - node T_4903 = or(T_4902, T_4825) - node T_4904 = or(T_4903, T_4828) - node T_4905 = or(T_4904, T_4831) - node T_4906 = or(T_4905, T_4834) - node T_4907 = or(T_4906, T_4837) - node T_4908 = or(T_4907, T_4840) - node T_4909 = or(T_4908, T_4843) - node T_4910 = or(T_4909, T_4846) - node T_4911 = or(T_4910, T_4849) - wire T_4912 : UInt<1> - T_4912 <= UInt<1>("h00") - T_4912 <= T_4911 - node T_4915 = eq(T_4587, UInt<1>("h00")) - node T_4917 = eq(T_4915, UInt<1>("h00")) - node T_4918 = and(T_4917, T_4912) - when T_4918 : - io.resp.bits.target <= T_4598[T_4589] + io.resp.bits.bht <- T_4537 + reg T_4567 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + reg T_4569 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_4578 : UInt<?>[2], clk + node T_4582 = bits(hits, 0, 0) + node T_4583 = bits(hits, 1, 1) + node T_4584 = bits(hits, 2, 2) + node T_4585 = bits(hits, 3, 3) + node T_4586 = bits(hits, 4, 4) + node T_4587 = bits(hits, 5, 5) + node T_4588 = bits(hits, 6, 6) + node T_4589 = bits(hits, 7, 7) + node T_4590 = bits(hits, 8, 8) + node T_4591 = bits(hits, 9, 9) + node T_4592 = bits(hits, 10, 10) + node T_4593 = bits(hits, 11, 11) + node T_4594 = bits(hits, 12, 12) + node T_4595 = bits(hits, 13, 13) + node T_4596 = bits(hits, 14, 14) + node T_4597 = bits(hits, 15, 15) + node T_4598 = bits(hits, 16, 16) + node T_4599 = bits(hits, 17, 17) + node T_4600 = bits(hits, 18, 18) + node T_4601 = bits(hits, 19, 19) + node T_4602 = bits(hits, 20, 20) + node T_4603 = bits(hits, 21, 21) + node T_4604 = bits(hits, 22, 22) + node T_4605 = bits(hits, 23, 23) + node T_4606 = bits(hits, 24, 24) + node T_4607 = bits(hits, 25, 25) + node T_4608 = bits(hits, 26, 26) + node T_4609 = bits(hits, 27, 27) + node T_4610 = bits(hits, 28, 28) + node T_4611 = bits(hits, 29, 29) + node T_4612 = bits(hits, 30, 30) + node T_4613 = bits(hits, 31, 31) + node T_4614 = bits(hits, 32, 32) + node T_4615 = bits(hits, 33, 33) + node T_4616 = bits(hits, 34, 34) + node T_4617 = bits(hits, 35, 35) + node T_4618 = bits(hits, 36, 36) + node T_4619 = bits(hits, 37, 37) + node T_4620 = bits(hits, 38, 38) + node T_4621 = bits(hits, 39, 39) + node T_4622 = bits(hits, 40, 40) + node T_4623 = bits(hits, 41, 41) + node T_4624 = bits(hits, 42, 42) + node T_4625 = bits(hits, 43, 43) + node T_4626 = bits(hits, 44, 44) + node T_4627 = bits(hits, 45, 45) + node T_4628 = bits(hits, 46, 46) + node T_4629 = bits(hits, 47, 47) + node T_4630 = bits(hits, 48, 48) + node T_4631 = bits(hits, 49, 49) + node T_4632 = bits(hits, 50, 50) + node T_4633 = bits(hits, 51, 51) + node T_4634 = bits(hits, 52, 52) + node T_4635 = bits(hits, 53, 53) + node T_4636 = bits(hits, 54, 54) + node T_4637 = bits(hits, 55, 55) + node T_4638 = bits(hits, 56, 56) + node T_4639 = bits(hits, 57, 57) + node T_4640 = bits(hits, 58, 58) + node T_4641 = bits(hits, 59, 59) + node T_4642 = bits(hits, 60, 60) + node T_4643 = bits(hits, 61, 61) + node T_4645 = shl(useRAS[0], 0) + node T_4646 = mux(T_4582, T_4645, UInt<1>("h00")) + node T_4648 = shl(useRAS[1], 0) + node T_4649 = mux(T_4583, T_4648, UInt<1>("h00")) + node T_4651 = shl(useRAS[2], 0) + node T_4652 = mux(T_4584, T_4651, UInt<1>("h00")) + node T_4654 = shl(useRAS[3], 0) + node T_4655 = mux(T_4585, T_4654, UInt<1>("h00")) + node T_4657 = shl(useRAS[4], 0) + node T_4658 = mux(T_4586, T_4657, UInt<1>("h00")) + node T_4660 = shl(useRAS[5], 0) + node T_4661 = mux(T_4587, T_4660, UInt<1>("h00")) + node T_4663 = shl(useRAS[6], 0) + node T_4664 = mux(T_4588, T_4663, UInt<1>("h00")) + node T_4666 = shl(useRAS[7], 0) + node T_4667 = mux(T_4589, T_4666, UInt<1>("h00")) + node T_4669 = shl(useRAS[8], 0) + node T_4670 = mux(T_4590, T_4669, UInt<1>("h00")) + node T_4672 = shl(useRAS[9], 0) + node T_4673 = mux(T_4591, T_4672, UInt<1>("h00")) + node T_4675 = shl(useRAS[10], 0) + node T_4676 = mux(T_4592, T_4675, UInt<1>("h00")) + node T_4678 = shl(useRAS[11], 0) + node T_4679 = mux(T_4593, T_4678, UInt<1>("h00")) + node T_4681 = shl(useRAS[12], 0) + node T_4682 = mux(T_4594, T_4681, UInt<1>("h00")) + node T_4684 = shl(useRAS[13], 0) + node T_4685 = mux(T_4595, T_4684, UInt<1>("h00")) + node T_4687 = shl(useRAS[14], 0) + node T_4688 = mux(T_4596, T_4687, UInt<1>("h00")) + node T_4690 = shl(useRAS[15], 0) + node T_4691 = mux(T_4597, T_4690, UInt<1>("h00")) + node T_4693 = shl(useRAS[16], 0) + node T_4694 = mux(T_4598, T_4693, UInt<1>("h00")) + node T_4696 = shl(useRAS[17], 0) + node T_4697 = mux(T_4599, T_4696, UInt<1>("h00")) + node T_4699 = shl(useRAS[18], 0) + node T_4700 = mux(T_4600, T_4699, UInt<1>("h00")) + node T_4702 = shl(useRAS[19], 0) + node T_4703 = mux(T_4601, T_4702, UInt<1>("h00")) + node T_4705 = shl(useRAS[20], 0) + node T_4706 = mux(T_4602, T_4705, UInt<1>("h00")) + node T_4708 = shl(useRAS[21], 0) + node T_4709 = mux(T_4603, T_4708, UInt<1>("h00")) + node T_4711 = shl(useRAS[22], 0) + node T_4712 = mux(T_4604, T_4711, UInt<1>("h00")) + node T_4714 = shl(useRAS[23], 0) + node T_4715 = mux(T_4605, T_4714, UInt<1>("h00")) + node T_4717 = shl(useRAS[24], 0) + node T_4718 = mux(T_4606, T_4717, UInt<1>("h00")) + node T_4720 = shl(useRAS[25], 0) + node T_4721 = mux(T_4607, T_4720, UInt<1>("h00")) + node T_4723 = shl(useRAS[26], 0) + node T_4724 = mux(T_4608, T_4723, UInt<1>("h00")) + node T_4726 = shl(useRAS[27], 0) + node T_4727 = mux(T_4609, T_4726, UInt<1>("h00")) + node T_4729 = shl(useRAS[28], 0) + node T_4730 = mux(T_4610, T_4729, UInt<1>("h00")) + node T_4732 = shl(useRAS[29], 0) + node T_4733 = mux(T_4611, T_4732, UInt<1>("h00")) + node T_4735 = shl(useRAS[30], 0) + node T_4736 = mux(T_4612, T_4735, UInt<1>("h00")) + node T_4738 = shl(useRAS[31], 0) + node T_4739 = mux(T_4613, T_4738, UInt<1>("h00")) + node T_4741 = shl(useRAS[32], 0) + node T_4742 = mux(T_4614, T_4741, UInt<1>("h00")) + node T_4744 = shl(useRAS[33], 0) + node T_4745 = mux(T_4615, T_4744, UInt<1>("h00")) + node T_4747 = shl(useRAS[34], 0) + node T_4748 = mux(T_4616, T_4747, UInt<1>("h00")) + node T_4750 = shl(useRAS[35], 0) + node T_4751 = mux(T_4617, T_4750, UInt<1>("h00")) + node T_4753 = shl(useRAS[36], 0) + node T_4754 = mux(T_4618, T_4753, UInt<1>("h00")) + node T_4756 = shl(useRAS[37], 0) + node T_4757 = mux(T_4619, T_4756, UInt<1>("h00")) + node T_4759 = shl(useRAS[38], 0) + node T_4760 = mux(T_4620, T_4759, UInt<1>("h00")) + node T_4762 = shl(useRAS[39], 0) + node T_4763 = mux(T_4621, T_4762, UInt<1>("h00")) + node T_4765 = shl(useRAS[40], 0) + node T_4766 = mux(T_4622, T_4765, UInt<1>("h00")) + node T_4768 = shl(useRAS[41], 0) + node T_4769 = mux(T_4623, T_4768, UInt<1>("h00")) + node T_4771 = shl(useRAS[42], 0) + node T_4772 = mux(T_4624, T_4771, UInt<1>("h00")) + node T_4774 = shl(useRAS[43], 0) + node T_4775 = mux(T_4625, T_4774, UInt<1>("h00")) + node T_4777 = shl(useRAS[44], 0) + node T_4778 = mux(T_4626, T_4777, UInt<1>("h00")) + node T_4780 = shl(useRAS[45], 0) + node T_4781 = mux(T_4627, T_4780, UInt<1>("h00")) + node T_4783 = shl(useRAS[46], 0) + node T_4784 = mux(T_4628, T_4783, UInt<1>("h00")) + node T_4786 = shl(useRAS[47], 0) + node T_4787 = mux(T_4629, T_4786, UInt<1>("h00")) + node T_4789 = shl(useRAS[48], 0) + node T_4790 = mux(T_4630, T_4789, UInt<1>("h00")) + node T_4792 = shl(useRAS[49], 0) + node T_4793 = mux(T_4631, T_4792, UInt<1>("h00")) + node T_4795 = shl(useRAS[50], 0) + node T_4796 = mux(T_4632, T_4795, UInt<1>("h00")) + node T_4798 = shl(useRAS[51], 0) + node T_4799 = mux(T_4633, T_4798, UInt<1>("h00")) + node T_4801 = shl(useRAS[52], 0) + node T_4802 = mux(T_4634, T_4801, UInt<1>("h00")) + node T_4804 = shl(useRAS[53], 0) + node T_4805 = mux(T_4635, T_4804, UInt<1>("h00")) + node T_4807 = shl(useRAS[54], 0) + node T_4808 = mux(T_4636, T_4807, UInt<1>("h00")) + node T_4810 = shl(useRAS[55], 0) + node T_4811 = mux(T_4637, T_4810, UInt<1>("h00")) + node T_4813 = shl(useRAS[56], 0) + node T_4814 = mux(T_4638, T_4813, UInt<1>("h00")) + node T_4816 = shl(useRAS[57], 0) + node T_4817 = mux(T_4639, T_4816, UInt<1>("h00")) + node T_4819 = shl(useRAS[58], 0) + node T_4820 = mux(T_4640, T_4819, UInt<1>("h00")) + node T_4822 = shl(useRAS[59], 0) + node T_4823 = mux(T_4641, T_4822, UInt<1>("h00")) + node T_4825 = shl(useRAS[60], 0) + node T_4826 = mux(T_4642, T_4825, UInt<1>("h00")) + node T_4828 = shl(useRAS[61], 0) + node T_4829 = mux(T_4643, T_4828, UInt<1>("h00")) + node T_4831 = or(T_4646, T_4649) + node T_4832 = or(T_4831, T_4652) + node T_4833 = or(T_4832, T_4655) + node T_4834 = or(T_4833, T_4658) + node T_4835 = or(T_4834, T_4661) + node T_4836 = or(T_4835, T_4664) + node T_4837 = or(T_4836, T_4667) + node T_4838 = or(T_4837, T_4670) + node T_4839 = or(T_4838, T_4673) + node T_4840 = or(T_4839, T_4676) + node T_4841 = or(T_4840, T_4679) + node T_4842 = or(T_4841, T_4682) + node T_4843 = or(T_4842, T_4685) + node T_4844 = or(T_4843, T_4688) + node T_4845 = or(T_4844, T_4691) + node T_4846 = or(T_4845, T_4694) + node T_4847 = or(T_4846, T_4697) + node T_4848 = or(T_4847, T_4700) + node T_4849 = or(T_4848, T_4703) + node T_4850 = or(T_4849, T_4706) + node T_4851 = or(T_4850, T_4709) + node T_4852 = or(T_4851, T_4712) + node T_4853 = or(T_4852, T_4715) + node T_4854 = or(T_4853, T_4718) + node T_4855 = or(T_4854, T_4721) + node T_4856 = or(T_4855, T_4724) + node T_4857 = or(T_4856, T_4727) + node T_4858 = or(T_4857, T_4730) + node T_4859 = or(T_4858, T_4733) + node T_4860 = or(T_4859, T_4736) + node T_4861 = or(T_4860, T_4739) + node T_4862 = or(T_4861, T_4742) + node T_4863 = or(T_4862, T_4745) + node T_4864 = or(T_4863, T_4748) + node T_4865 = or(T_4864, T_4751) + node T_4866 = or(T_4865, T_4754) + node T_4867 = or(T_4866, T_4757) + node T_4868 = or(T_4867, T_4760) + node T_4869 = or(T_4868, T_4763) + node T_4870 = or(T_4869, T_4766) + node T_4871 = or(T_4870, T_4769) + node T_4872 = or(T_4871, T_4772) + node T_4873 = or(T_4872, T_4775) + node T_4874 = or(T_4873, T_4778) + node T_4875 = or(T_4874, T_4781) + node T_4876 = or(T_4875, T_4784) + node T_4877 = or(T_4876, T_4787) + node T_4878 = or(T_4877, T_4790) + node T_4879 = or(T_4878, T_4793) + node T_4880 = or(T_4879, T_4796) + node T_4881 = or(T_4880, T_4799) + node T_4882 = or(T_4881, T_4802) + node T_4883 = or(T_4882, T_4805) + node T_4884 = or(T_4883, T_4808) + node T_4885 = or(T_4884, T_4811) + node T_4886 = or(T_4885, T_4814) + node T_4887 = or(T_4886, T_4817) + node T_4888 = or(T_4887, T_4820) + node T_4889 = or(T_4888, T_4823) + node T_4890 = or(T_4889, T_4826) + node T_4891 = or(T_4890, T_4829) + wire T_4892 : UInt<1> + T_4892 is invalid + T_4892 <= T_4891 + node T_4894 = eq(T_4567, UInt<1>("h00")) + node T_4896 = eq(T_4894, UInt<1>("h00")) + node T_4897 = and(T_4896, T_4892) + when T_4897 : + io.resp.bits.target <= T_4578[T_4569] skip when io.ras_update.valid : when io.ras_update.bits.isCall : - node T_4921 = lt(T_4587, UInt<2>("h02")) - when T_4921 : - node T_4923 = addw(T_4587, UInt<1>("h01")) - T_4587 <= T_4923 + node T_4900 = lt(T_4567, UInt<2>("h02")) + when T_4900 : + node T_4902 = add(T_4567, UInt<1>("h01")) + node T_4903 = tail(T_4902, 1) + T_4567 <= T_4903 skip - node T_4926 = lt(T_4589, UInt<1>("h01")) - node T_4927 = or(UInt<1>("h01"), T_4926) - node T_4929 = addw(T_4589, UInt<1>("h01")) - node T_4931 = mux(T_4927, T_4929, UInt<1>("h00")) - T_4598[T_4931] <= io.ras_update.bits.returnAddr - T_4589 <= T_4931 - when T_4912 : + node T_4906 = lt(T_4569, UInt<1>("h01")) + node T_4907 = or(UInt<1>("h01"), T_4906) + node T_4909 = add(T_4569, UInt<1>("h01")) + node T_4910 = tail(T_4909, 1) + node T_4912 = mux(T_4907, T_4910, UInt<1>("h00")) + T_4578[T_4912] <= io.ras_update.bits.returnAddr + T_4569 <= T_4912 + when T_4892 : io.resp.bits.target <= io.ras_update.bits.returnAddr skip skip - node T_4933 = and(io.ras_update.bits.isReturn, io.ras_update.bits.prediction.valid) - node T_4935 = eq(io.ras_update.bits.isCall, UInt<1>("h00")) - node T_4936 = and(T_4935, T_4933) - when T_4936 : - node T_4938 = eq(T_4587, UInt<1>("h00")) - node T_4940 = eq(T_4938, UInt<1>("h00")) - when T_4940 : - node T_4942 = subw(T_4587, UInt<1>("h01")) - T_4587 <= T_4942 - node T_4945 = gt(T_4589, UInt<1>("h00")) - node T_4946 = or(UInt<1>("h01"), T_4945) - node T_4948 = subw(T_4589, UInt<1>("h01")) - node T_4950 = mux(T_4946, T_4948, UInt<1>("h01")) - T_4589 <= T_4950 + node T_4914 = and(io.ras_update.bits.isReturn, io.ras_update.bits.prediction.valid) + node T_4916 = eq(io.ras_update.bits.isCall, UInt<1>("h00")) + node T_4917 = and(T_4916, T_4914) + when T_4917 : + node T_4919 = eq(T_4567, UInt<1>("h00")) + node T_4921 = eq(T_4919, UInt<1>("h00")) + when T_4921 : + node T_4923 = sub(T_4567, UInt<1>("h01")) + node T_4924 = tail(T_4923, 1) + T_4567 <= T_4924 + node T_4927 = gt(T_4569, UInt<1>("h00")) + node T_4928 = or(UInt<1>("h01"), T_4927) + node T_4930 = sub(T_4569, UInt<1>("h01")) + node T_4931 = tail(T_4930, 1) + node T_4933 = mux(T_4928, T_4931, UInt<1>("h01")) + T_4569 <= T_4933 skip skip skip when io.invalidate : - T_4587 <= UInt<1>("h00") + T_4567 <= UInt<1>("h00") skip module FlowThroughSerializer : @@ -27645,16 +20939,7 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, cnt : UInt<1>, done : UInt<1>} - io.done <= UInt<1>("h00") - io.cnt <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.bits.g_type <= UInt<1>("h00") - io.out.bits.is_builtin_type <= UInt<1>("h00") - io.out.bits.manager_xact_id <= UInt<1>("h00") - io.out.bits.client_xact_id <= UInt<1>("h00") - io.out.bits.addr_beat <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in.ready <= UInt<1>("h00") + io is invalid io.out <- io.in io.cnt <= UInt<1>("h00") io.done <= UInt<1>("h01") @@ -27664,489 +20949,437 @@ circuit Top : input reset : UInt<1> output io : {flip req : {valid : UInt<1>, bits : {idx : UInt<12>, ppn : UInt<20>, kill : UInt<1>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}}, flip invalidate : UInt<1>, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}} - io.mem.grant.ready <= UInt<1>("h00") - io.mem.acquire.bits.data <= UInt<1>("h00") - io.mem.acquire.bits.union <= UInt<1>("h00") - io.mem.acquire.bits.a_type <= UInt<1>("h00") - io.mem.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.mem.acquire.bits.addr_beat <= UInt<1>("h00") - io.mem.acquire.bits.client_xact_id <= UInt<1>("h00") - io.mem.acquire.bits.addr_block <= UInt<1>("h00") - io.mem.acquire.valid <= UInt<1>("h00") - io.resp.bits.datablock <= UInt<1>("h00") - io.resp.bits.data <= UInt<1>("h00") - io.resp.valid <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") - reg invalidated : UInt<1>, clk, UInt<1>("h00"), invalidated + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + reg invalidated : UInt<1>, clk node stall = eq(io.resp.ready, UInt<1>("h00")) wire rdy : UInt<1> - rdy <= UInt<1>("h00") - reg refill_addr : UInt<32>, clk, UInt<1>("h00"), refill_addr + rdy is invalid + reg refill_addr : UInt<32>, clk wire s1_any_tag_hit : UInt<1> - s1_any_tag_hit <= UInt<1>("h00") - reg s1_valid : UInt<1>, clk, reset, UInt<1>("h00") - reg s1_pgoff : UInt<12>, clk, UInt<1>("h00"), s1_pgoff + s1_any_tag_hit is invalid + reg s1_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg s1_pgoff : UInt<12>, clk node s1_addr = cat(io.req.bits.ppn, s1_pgoff) node s1_tag = bits(s1_addr, 31, 12) + node T_523 = and(s1_valid, stall) + node s0_valid = or(io.req.valid, T_523) node T_525 = and(s1_valid, stall) - node s0_valid = or(io.req.valid, T_525) - node T_527 = and(s1_valid, stall) - node s0_pgoff = mux(T_527, s1_pgoff, io.req.bits.idx) - node T_529 = and(io.req.valid, rdy) - node T_530 = and(s1_valid, stall) - node T_532 = eq(io.req.bits.kill, UInt<1>("h00")) - node T_533 = and(T_530, T_532) - node T_534 = or(T_529, T_533) - s1_valid <= T_534 - node T_535 = and(io.req.valid, rdy) - when T_535 : + node s0_pgoff = mux(T_525, s1_pgoff, io.req.bits.idx) + node T_527 = and(io.req.valid, rdy) + node T_528 = and(s1_valid, stall) + node T_530 = eq(io.req.bits.kill, UInt<1>("h00")) + node T_531 = and(T_528, T_530) + node T_532 = or(T_527, T_531) + s1_valid <= T_532 + node T_533 = and(io.req.valid, rdy) + when T_533 : s1_pgoff <= io.req.bits.idx skip - node T_537 = eq(io.req.bits.kill, UInt<1>("h00")) - node T_538 = and(s1_valid, T_537) - node T_539 = eq(state, UInt<1>("h00")) - node out_valid = and(T_538, T_539) + node T_535 = eq(io.req.bits.kill, UInt<1>("h00")) + node T_536 = and(s1_valid, T_535) + node T_537 = eq(state, UInt<1>("h00")) + node out_valid = and(T_536, T_537) node s1_idx = bits(s1_addr, 11, 6) node s1_offset = bits(s1_addr, 5, 0) node s1_hit = and(out_valid, s1_any_tag_hit) - node T_545 = eq(s1_any_tag_hit, UInt<1>("h00")) - node s1_miss = and(out_valid, T_545) - node T_547 = eq(state, UInt<1>("h00")) - node T_549 = eq(s1_miss, UInt<1>("h00")) - node T_550 = and(T_547, T_549) - rdy <= T_550 - node T_551 = eq(state, UInt<1>("h00")) - node T_552 = and(s1_valid, T_551) - node T_553 = and(T_552, s1_miss) - when T_553 : + node T_543 = eq(s1_any_tag_hit, UInt<1>("h00")) + node s1_miss = and(out_valid, T_543) + node T_545 = eq(state, UInt<1>("h00")) + node T_547 = eq(s1_miss, UInt<1>("h00")) + node T_548 = and(T_545, T_547) + rdy <= T_548 + node T_549 = eq(state, UInt<1>("h00")) + node T_550 = and(s1_valid, T_549) + node T_551 = and(T_550, s1_miss) + when T_551 : refill_addr <= s1_addr skip node refill_tag = bits(refill_addr, 31, 12) - inst T_555 of FlowThroughSerializer - T_555.io.out.ready <= UInt<1>("h00") - T_555.io.in.bits.data <= UInt<1>("h00") - T_555.io.in.bits.g_type <= UInt<1>("h00") - T_555.io.in.bits.is_builtin_type <= UInt<1>("h00") - T_555.io.in.bits.manager_xact_id <= UInt<1>("h00") - T_555.io.in.bits.client_xact_id <= UInt<1>("h00") - T_555.io.in.bits.addr_beat <= UInt<1>("h00") - T_555.io.in.valid <= UInt<1>("h00") - T_555.clk <= clk - T_555.reset <= reset - T_555.io.in.valid <= io.mem.grant.valid - T_555.io.in.bits <- io.mem.grant.bits - io.mem.grant.ready <= T_555.io.in.ready - node T_564 = and(T_555.io.out.ready, T_555.io.out.valid) - reg refill_cnt : UInt<2>, clk, reset, UInt<2>("h00") - when T_564 : - node T_568 = eq(refill_cnt, UInt<2>("h03")) - node T_570 = and(UInt<1>("h00"), T_568) - node T_573 = addw(refill_cnt, UInt<1>("h01")) - node T_574 = mux(T_570, UInt<1>("h00"), T_573) - refill_cnt <= T_574 - skip - node refill_wrap = and(T_564, T_568) - node T_576 = eq(state, UInt<2>("h03")) - node refill_done = and(T_576, refill_wrap) - T_555.io.out.ready <= UInt<1>("h01") - reg T_580 : UInt<16>, clk, reset, UInt<16>("h01") + inst T_553 of FlowThroughSerializer + T_553.io is invalid + T_553.clk <= clk + T_553.reset <= reset + T_553.io.in.valid <= io.mem.grant.valid + T_553.io.in.bits <- io.mem.grant.bits + io.mem.grant.ready <= T_553.io.in.ready + node T_554 = and(T_553.io.out.ready, T_553.io.out.valid) + reg refill_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_554 : + node T_558 = eq(refill_cnt, UInt<2>("h03")) + node T_560 = and(UInt<1>("h00"), T_558) + node T_563 = add(refill_cnt, UInt<1>("h01")) + node T_564 = tail(T_563, 1) + node T_565 = mux(T_560, UInt<1>("h00"), T_564) + refill_cnt <= T_565 + skip + node refill_wrap = and(T_554, T_558) + node T_567 = eq(state, UInt<2>("h03")) + node refill_done = and(T_567, refill_wrap) + T_553.io.out.ready <= UInt<1>("h01") + reg T_571 : UInt<16>, clk with : (reset => (reset, UInt<16>("h01"))) when s1_miss : - node T_581 = bit(T_580, 0) - node T_582 = bit(T_580, 2) - node T_583 = xor(T_581, T_582) - node T_584 = bit(T_580, 3) - node T_585 = xor(T_583, T_584) - node T_586 = bit(T_580, 5) - node T_587 = xor(T_585, T_586) - node T_588 = bits(T_580, 15, 1) - node T_589 = cat(T_587, T_588) - T_580 <= T_589 - skip - node repl_way = bits(T_580, 1, 0) + node T_572 = bits(T_571, 0, 0) + node T_573 = bits(T_571, 2, 2) + node T_574 = xor(T_572, T_573) + node T_575 = bits(T_571, 3, 3) + node T_576 = xor(T_574, T_575) + node T_577 = bits(T_571, 5, 5) + node T_578 = xor(T_576, T_577) + node T_579 = bits(T_571, 15, 1) + node T_580 = cat(T_578, T_579) + T_571 <= T_580 + skip + node repl_way = bits(T_571, 1, 0) smem tag_array : UInt<20>[4][64] - node T_608 = bits(s0_pgoff, 11, 6) - node T_610 = eq(refill_done, UInt<1>("h00")) - node T_611 = and(T_610, s0_valid) - poison T_612 : UInt<6> - node T_613 = mux(T_611, T_608, T_612) - read mport tag_rdata = tag_array[T_613], clk + node T_599 = bits(s0_pgoff, 11, 6) + node T_601 = eq(refill_done, UInt<1>("h00")) + node T_602 = and(T_601, s0_valid) + wire T_604 : UInt<?> + T_604 is invalid + when T_602 : + T_604 <= T_599 + skip + read mport tag_rdata = tag_array[T_604], clk when refill_done : - wire T_623 : UInt<20>[4] - T_623[0] <= refill_tag - T_623[1] <= refill_tag - T_623[2] <= refill_tag - T_623[3] <= refill_tag - node T_630 = eq(repl_way, UInt<1>("h00")) - node T_632 = eq(repl_way, UInt<1>("h01")) - node T_634 = eq(repl_way, UInt<2>("h02")) - node T_636 = eq(repl_way, UInt<2>("h03")) - wire T_638 : UInt<1>[4] - T_638[0] <= T_630 - T_638[1] <= T_632 - T_638[2] <= T_634 - T_638[3] <= T_636 - write mport T_646 = tag_array[s1_idx], clk - when T_638[0] : - T_646[0] <= T_623[0] - skip - when T_638[1] : - T_646[1] <= T_623[1] - skip - when T_638[2] : - T_646[2] <= T_623[2] - skip - when T_638[3] : - T_646[3] <= T_623[3] - skip - skip - reg vb_array : UInt<256>, clk, reset, UInt<256>("h00") - node T_655 = eq(invalidated, UInt<1>("h00")) - node T_656 = and(refill_done, T_655) - when T_656 : - node T_657 = cat(repl_way, s1_idx) - node T_660 = dshl(UInt<1>("h01"), T_657) - node T_661 = or(vb_array, T_660) - node T_662 = not(vb_array) - node T_663 = or(T_662, T_660) - node T_664 = not(T_663) - node T_665 = mux(UInt<1>("h01"), T_661, T_664) - vb_array <= T_665 + wire T_614 : UInt<20>[4] + T_614[0] <= refill_tag + T_614[1] <= refill_tag + T_614[2] <= refill_tag + T_614[3] <= refill_tag + node T_621 = eq(repl_way, UInt<1>("h00")) + node T_623 = eq(repl_way, UInt<1>("h01")) + node T_625 = eq(repl_way, UInt<2>("h02")) + node T_627 = eq(repl_way, UInt<2>("h03")) + wire T_629 : UInt<1>[4] + T_629[0] <= T_621 + T_629[1] <= T_623 + T_629[2] <= T_625 + T_629[3] <= T_627 + write mport T_637 = tag_array[s1_idx], clk + when T_629[0] : + T_637[0] <= T_614[0] + skip + when T_629[1] : + T_637[1] <= T_614[1] + skip + when T_629[2] : + T_637[2] <= T_614[2] + skip + when T_629[3] : + T_637[3] <= T_614[3] + skip + skip + reg vb_array : UInt<256>, clk with : (reset => (reset, UInt<256>("h00"))) + node T_646 = eq(invalidated, UInt<1>("h00")) + node T_647 = and(refill_done, T_646) + when T_647 : + node T_648 = cat(repl_way, s1_idx) + node T_651 = dshl(UInt<1>("h01"), T_648) + node T_652 = or(vb_array, T_651) + node T_653 = not(vb_array) + node T_654 = or(T_653, T_651) + node T_655 = not(T_654) + node T_656 = mux(UInt<1>("h01"), T_652, T_655) + vb_array <= T_656 skip when io.invalidate : vb_array <= UInt<1>("h00") invalidated <= UInt<1>("h01") skip wire s1_disparity : UInt<1>[4] - s1_disparity[0] <= UInt<1>("h00") - s1_disparity[1] <= UInt<1>("h00") - s1_disparity[2] <= UInt<1>("h00") - s1_disparity[3] <= UInt<1>("h00") - node T_688 = and(s1_valid, s1_disparity[0]) - when T_688 : - node T_690 = cat(UInt<1>("h00"), s1_idx) - node T_693 = dshl(UInt<1>("h01"), T_690) - node T_694 = or(vb_array, T_693) - node T_695 = not(vb_array) - node T_696 = or(T_695, T_693) - node T_697 = not(T_696) - node T_698 = mux(UInt<1>("h00"), T_694, T_697) - vb_array <= T_698 - skip - node T_699 = and(s1_valid, s1_disparity[1]) - when T_699 : - node T_701 = cat(UInt<1>("h01"), s1_idx) - node T_704 = dshl(UInt<1>("h01"), T_701) - node T_705 = or(vb_array, T_704) - node T_706 = not(vb_array) - node T_707 = or(T_706, T_704) - node T_708 = not(T_707) - node T_709 = mux(UInt<1>("h00"), T_705, T_708) - vb_array <= T_709 - skip - node T_710 = and(s1_valid, s1_disparity[2]) - when T_710 : - node T_712 = cat(UInt<2>("h02"), s1_idx) - node T_715 = dshl(UInt<1>("h01"), T_712) - node T_716 = or(vb_array, T_715) - node T_717 = not(vb_array) - node T_718 = or(T_717, T_715) - node T_719 = not(T_718) - node T_720 = mux(UInt<1>("h00"), T_716, T_719) - vb_array <= T_720 - skip - node T_721 = and(s1_valid, s1_disparity[3]) - when T_721 : - node T_723 = cat(UInt<2>("h03"), s1_idx) - node T_726 = dshl(UInt<1>("h01"), T_723) - node T_727 = or(vb_array, T_726) - node T_728 = not(vb_array) - node T_729 = or(T_728, T_726) - node T_730 = not(T_729) - node T_731 = mux(UInt<1>("h00"), T_727, T_730) - vb_array <= T_731 + s1_disparity is invalid + node T_675 = and(s1_valid, s1_disparity[0]) + when T_675 : + node T_677 = cat(UInt<1>("h00"), s1_idx) + node T_680 = dshl(UInt<1>("h01"), T_677) + node T_681 = or(vb_array, T_680) + node T_682 = not(vb_array) + node T_683 = or(T_682, T_680) + node T_684 = not(T_683) + node T_685 = mux(UInt<1>("h00"), T_681, T_684) + vb_array <= T_685 + skip + node T_686 = and(s1_valid, s1_disparity[1]) + when T_686 : + node T_688 = cat(UInt<1>("h01"), s1_idx) + node T_691 = dshl(UInt<1>("h01"), T_688) + node T_692 = or(vb_array, T_691) + node T_693 = not(vb_array) + node T_694 = or(T_693, T_691) + node T_695 = not(T_694) + node T_696 = mux(UInt<1>("h00"), T_692, T_695) + vb_array <= T_696 + skip + node T_697 = and(s1_valid, s1_disparity[2]) + when T_697 : + node T_699 = cat(UInt<2>("h02"), s1_idx) + node T_702 = dshl(UInt<1>("h01"), T_699) + node T_703 = or(vb_array, T_702) + node T_704 = not(vb_array) + node T_705 = or(T_704, T_702) + node T_706 = not(T_705) + node T_707 = mux(UInt<1>("h00"), T_703, T_706) + vb_array <= T_707 + skip + node T_708 = and(s1_valid, s1_disparity[3]) + when T_708 : + node T_710 = cat(UInt<2>("h03"), s1_idx) + node T_713 = dshl(UInt<1>("h01"), T_710) + node T_714 = or(vb_array, T_713) + node T_715 = not(vb_array) + node T_716 = or(T_715, T_713) + node T_717 = not(T_716) + node T_718 = mux(UInt<1>("h00"), T_714, T_717) + vb_array <= T_718 skip wire s1_tag_match : UInt<1>[4] - s1_tag_match[0] <= UInt<1>("h00") - s1_tag_match[1] <= UInt<1>("h00") - s1_tag_match[2] <= UInt<1>("h00") - s1_tag_match[3] <= UInt<1>("h00") + s1_tag_match is invalid wire s1_tag_hit : UInt<1>[4] - s1_tag_hit[0] <= UInt<1>("h00") - s1_tag_hit[1] <= UInt<1>("h00") - s1_tag_hit[2] <= UInt<1>("h00") - s1_tag_hit[3] <= UInt<1>("h00") + s1_tag_hit is invalid wire s1_dout : UInt<128>[4] - s1_dout[0] <= UInt<1>("h00") - s1_dout[1] <= UInt<1>("h00") - s1_dout[2] <= UInt<1>("h00") - s1_dout[3] <= UInt<1>("h00") - node T_793 = eq(io.invalidate, UInt<1>("h00")) - node T_795 = bits(s1_pgoff, 11, 6) - node T_796 = cat(UInt<1>("h00"), T_795) - node T_797 = dshr(vb_array, T_796) - node T_798 = bit(T_797, 0) - node T_799 = bit(T_798, 0) - node T_800 = and(T_793, T_799) - node T_803 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_804 = and(s1_valid, rdy) - node T_806 = eq(stall, UInt<1>("h00")) - node T_807 = and(T_804, T_806) - when T_807 : - skip - node T_808 = bits(tag_rdata[0], 19, 0) - node T_809 = eq(T_808, s1_tag) - s1_tag_match[0] <= T_809 - node T_810 = and(T_800, s1_tag_match[0]) - s1_tag_hit[0] <= T_810 - node T_813 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_814 = or(T_803, T_813) - node T_815 = and(T_800, T_814) - s1_disparity[0] <= T_815 - node T_817 = eq(io.invalidate, UInt<1>("h00")) - node T_819 = bits(s1_pgoff, 11, 6) - node T_820 = cat(UInt<1>("h01"), T_819) - node T_821 = dshr(vb_array, T_820) - node T_822 = bit(T_821, 0) - node T_823 = bit(T_822, 0) - node T_824 = and(T_817, T_823) - node T_827 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_828 = and(s1_valid, rdy) - node T_830 = eq(stall, UInt<1>("h00")) - node T_831 = and(T_828, T_830) - when T_831 : - skip - node T_832 = bits(tag_rdata[1], 19, 0) - node T_833 = eq(T_832, s1_tag) - s1_tag_match[1] <= T_833 - node T_834 = and(T_824, s1_tag_match[1]) - s1_tag_hit[1] <= T_834 - node T_837 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_838 = or(T_827, T_837) - node T_839 = and(T_824, T_838) - s1_disparity[1] <= T_839 - node T_841 = eq(io.invalidate, UInt<1>("h00")) - node T_843 = bits(s1_pgoff, 11, 6) - node T_844 = cat(UInt<2>("h02"), T_843) - node T_845 = dshr(vb_array, T_844) - node T_846 = bit(T_845, 0) - node T_847 = bit(T_846, 0) - node T_848 = and(T_841, T_847) - node T_851 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_852 = and(s1_valid, rdy) - node T_854 = eq(stall, UInt<1>("h00")) - node T_855 = and(T_852, T_854) - when T_855 : - skip - node T_856 = bits(tag_rdata[2], 19, 0) - node T_857 = eq(T_856, s1_tag) - s1_tag_match[2] <= T_857 - node T_858 = and(T_848, s1_tag_match[2]) - s1_tag_hit[2] <= T_858 - node T_861 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_862 = or(T_851, T_861) - node T_863 = and(T_848, T_862) - s1_disparity[2] <= T_863 - node T_865 = eq(io.invalidate, UInt<1>("h00")) - node T_867 = bits(s1_pgoff, 11, 6) - node T_868 = cat(UInt<2>("h03"), T_867) - node T_869 = dshr(vb_array, T_868) - node T_870 = bit(T_869, 0) - node T_871 = bit(T_870, 0) - node T_872 = and(T_865, T_871) - node T_875 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_876 = and(s1_valid, rdy) - node T_878 = eq(stall, UInt<1>("h00")) - node T_879 = and(T_876, T_878) - when T_879 : - skip - node T_880 = bits(tag_rdata[3], 19, 0) - node T_881 = eq(T_880, s1_tag) - s1_tag_match[3] <= T_881 - node T_882 = and(T_872, s1_tag_match[3]) - s1_tag_hit[3] <= T_882 - node T_885 = or(UInt<1>("h00"), UInt<1>("h00")) - node T_886 = or(T_875, T_885) - node T_887 = and(T_872, T_886) - s1_disparity[3] <= T_887 - node T_888 = or(s1_tag_hit[0], s1_tag_hit[1]) - node T_889 = or(T_888, s1_tag_hit[2]) - node T_890 = or(T_889, s1_tag_hit[3]) - node T_891 = or(s1_disparity[0], s1_disparity[1]) - node T_892 = or(T_891, s1_disparity[2]) - node T_893 = or(T_892, s1_disparity[3]) - node T_895 = eq(T_893, UInt<1>("h00")) - node T_896 = and(T_890, T_895) - s1_any_tag_hit <= T_896 - smem T_899 : UInt<128>[256] - node T_901 = eq(repl_way, UInt<1>("h00")) - node T_902 = and(T_555.io.out.valid, T_901) - when T_902 : - node T_903 = cat(s1_idx, refill_cnt) - write mport T_904 = T_899[T_903], clk - T_904 <= T_555.io.out.bits.data - skip - node T_905 = bits(s0_pgoff, 11, 4) - node T_907 = eq(T_902, UInt<1>("h00")) - node T_908 = and(T_907, s0_valid) - poison T_909 : UInt<8> - node T_910 = mux(T_908, T_905, T_909) - read mport T_911 = T_899[T_910], clk - s1_dout[0] <= UInt<1>("h00") - node T_913 = and(s1_valid, rdy) - node T_915 = eq(stall, UInt<1>("h00")) - node T_916 = and(T_913, T_915) - node T_918 = or(UInt<1>("h00"), s1_tag_match[0]) - node T_919 = and(T_916, T_918) - when T_919 : - s1_dout[0] <= T_911 - skip - smem T_922 : UInt<128>[256] - node T_924 = eq(repl_way, UInt<1>("h01")) - node T_925 = and(T_555.io.out.valid, T_924) - when T_925 : - node T_926 = cat(s1_idx, refill_cnt) - write mport T_927 = T_922[T_926], clk - T_927 <= T_555.io.out.bits.data - skip - node T_928 = bits(s0_pgoff, 11, 4) - node T_930 = eq(T_925, UInt<1>("h00")) - node T_931 = and(T_930, s0_valid) - poison T_932 : UInt<8> - node T_933 = mux(T_931, T_928, T_932) - read mport T_934 = T_922[T_933], clk - s1_dout[1] <= UInt<1>("h00") - node T_936 = and(s1_valid, rdy) - node T_938 = eq(stall, UInt<1>("h00")) - node T_939 = and(T_936, T_938) - node T_941 = or(UInt<1>("h00"), s1_tag_match[1]) - node T_942 = and(T_939, T_941) - when T_942 : - s1_dout[1] <= T_934 - skip - smem T_945 : UInt<128>[256] - node T_947 = eq(repl_way, UInt<2>("h02")) - node T_948 = and(T_555.io.out.valid, T_947) - when T_948 : - node T_949 = cat(s1_idx, refill_cnt) - write mport T_950 = T_945[T_949], clk - T_950 <= T_555.io.out.bits.data - skip - node T_951 = bits(s0_pgoff, 11, 4) - node T_953 = eq(T_948, UInt<1>("h00")) - node T_954 = and(T_953, s0_valid) - poison T_955 : UInt<8> - node T_956 = mux(T_954, T_951, T_955) - read mport T_957 = T_945[T_956], clk - s1_dout[2] <= UInt<1>("h00") - node T_959 = and(s1_valid, rdy) - node T_961 = eq(stall, UInt<1>("h00")) - node T_962 = and(T_959, T_961) - node T_964 = or(UInt<1>("h00"), s1_tag_match[2]) - node T_965 = and(T_962, T_964) - when T_965 : - s1_dout[2] <= T_957 - skip - smem T_968 : UInt<128>[256] - node T_970 = eq(repl_way, UInt<2>("h03")) - node T_971 = and(T_555.io.out.valid, T_970) - when T_971 : - node T_972 = cat(s1_idx, refill_cnt) - write mport T_973 = T_968[T_972], clk - T_973 <= T_555.io.out.bits.data - skip - node T_974 = bits(s0_pgoff, 11, 4) - node T_976 = eq(T_971, UInt<1>("h00")) - node T_977 = and(T_976, s0_valid) - poison T_978 : UInt<8> - node T_979 = mux(T_977, T_974, T_978) - read mport T_980 = T_968[T_979], clk - s1_dout[3] <= UInt<1>("h00") - node T_982 = and(s1_valid, rdy) - node T_984 = eq(stall, UInt<1>("h00")) - node T_985 = and(T_982, T_984) - node T_987 = or(UInt<1>("h00"), s1_tag_match[3]) - node T_988 = and(T_985, T_987) - when T_988 : - s1_dout[3] <= T_980 - skip - node T_990 = mux(s1_tag_hit[0], s1_dout[0], UInt<1>("h00")) - node T_992 = mux(s1_tag_hit[1], s1_dout[1], UInt<1>("h00")) - node T_994 = mux(s1_tag_hit[2], s1_dout[2], UInt<1>("h00")) - node T_996 = mux(s1_tag_hit[3], s1_dout[3], UInt<1>("h00")) - node T_998 = or(T_990, T_992) - node T_999 = or(T_998, T_994) - node T_1000 = or(T_999, T_996) - wire T_1001 : UInt<128> - T_1001 <= UInt<1>("h00") - T_1001 <= T_1000 - io.resp.bits.datablock <= T_1001 + s1_dout is invalid + node T_768 = eq(io.invalidate, UInt<1>("h00")) + node T_770 = bits(s1_pgoff, 11, 6) + node T_771 = cat(UInt<1>("h00"), T_770) + node T_772 = dshr(vb_array, T_771) + node T_773 = bits(T_772, 0, 0) + node T_774 = bits(T_773, 0, 0) + node T_775 = and(T_768, T_774) + node T_778 = or(UInt<1>("h00"), UInt<1>("h00")) + node T_779 = and(s1_valid, rdy) + node T_781 = eq(stall, UInt<1>("h00")) + node T_782 = and(T_779, T_781) + when T_782 : + skip + node T_783 = bits(tag_rdata[0], 19, 0) + node T_784 = eq(T_783, s1_tag) + s1_tag_match[0] <= T_784 + node T_785 = and(T_775, s1_tag_match[0]) + s1_tag_hit[0] <= T_785 + node T_788 = or(UInt<1>("h00"), UInt<1>("h00")) + node T_789 = or(T_778, T_788) + node T_790 = and(T_775, T_789) + s1_disparity[0] <= T_790 + node T_792 = eq(io.invalidate, UInt<1>("h00")) + node T_794 = bits(s1_pgoff, 11, 6) + node T_795 = cat(UInt<1>("h01"), T_794) + node T_796 = dshr(vb_array, T_795) + node T_797 = bits(T_796, 0, 0) + node T_798 = bits(T_797, 0, 0) + node T_799 = and(T_792, T_798) + node T_802 = or(UInt<1>("h00"), UInt<1>("h00")) + node T_803 = and(s1_valid, rdy) + node T_805 = eq(stall, UInt<1>("h00")) + node T_806 = and(T_803, T_805) + when T_806 : + skip + node T_807 = bits(tag_rdata[1], 19, 0) + node T_808 = eq(T_807, s1_tag) + s1_tag_match[1] <= T_808 + node T_809 = and(T_799, s1_tag_match[1]) + s1_tag_hit[1] <= T_809 + node T_812 = or(UInt<1>("h00"), UInt<1>("h00")) + node T_813 = or(T_802, T_812) + node T_814 = and(T_799, T_813) + s1_disparity[1] <= T_814 + node T_816 = eq(io.invalidate, UInt<1>("h00")) + node T_818 = bits(s1_pgoff, 11, 6) + node T_819 = cat(UInt<2>("h02"), T_818) + node T_820 = dshr(vb_array, T_819) + node T_821 = bits(T_820, 0, 0) + node T_822 = bits(T_821, 0, 0) + node T_823 = and(T_816, T_822) + node T_826 = or(UInt<1>("h00"), UInt<1>("h00")) + node T_827 = and(s1_valid, rdy) + node T_829 = eq(stall, UInt<1>("h00")) + node T_830 = and(T_827, T_829) + when T_830 : + skip + node T_831 = bits(tag_rdata[2], 19, 0) + node T_832 = eq(T_831, s1_tag) + s1_tag_match[2] <= T_832 + node T_833 = and(T_823, s1_tag_match[2]) + s1_tag_hit[2] <= T_833 + node T_836 = or(UInt<1>("h00"), UInt<1>("h00")) + node T_837 = or(T_826, T_836) + node T_838 = and(T_823, T_837) + s1_disparity[2] <= T_838 + node T_840 = eq(io.invalidate, UInt<1>("h00")) + node T_842 = bits(s1_pgoff, 11, 6) + node T_843 = cat(UInt<2>("h03"), T_842) + node T_844 = dshr(vb_array, T_843) + node T_845 = bits(T_844, 0, 0) + node T_846 = bits(T_845, 0, 0) + node T_847 = and(T_840, T_846) + node T_850 = or(UInt<1>("h00"), UInt<1>("h00")) + node T_851 = and(s1_valid, rdy) + node T_853 = eq(stall, UInt<1>("h00")) + node T_854 = and(T_851, T_853) + when T_854 : + skip + node T_855 = bits(tag_rdata[3], 19, 0) + node T_856 = eq(T_855, s1_tag) + s1_tag_match[3] <= T_856 + node T_857 = and(T_847, s1_tag_match[3]) + s1_tag_hit[3] <= T_857 + node T_860 = or(UInt<1>("h00"), UInt<1>("h00")) + node T_861 = or(T_850, T_860) + node T_862 = and(T_847, T_861) + s1_disparity[3] <= T_862 + node T_863 = or(s1_tag_hit[0], s1_tag_hit[1]) + node T_864 = or(T_863, s1_tag_hit[2]) + node T_865 = or(T_864, s1_tag_hit[3]) + node T_866 = or(s1_disparity[0], s1_disparity[1]) + node T_867 = or(T_866, s1_disparity[2]) + node T_868 = or(T_867, s1_disparity[3]) + node T_870 = eq(T_868, UInt<1>("h00")) + node T_871 = and(T_865, T_870) + s1_any_tag_hit <= T_871 + smem T_874 : UInt<128>[256] + node T_876 = eq(repl_way, UInt<1>("h00")) + node T_877 = and(T_553.io.out.valid, T_876) + when T_877 : + node T_878 = cat(s1_idx, refill_cnt) + write mport T_879 = T_874[T_878], clk + T_879 <= T_553.io.out.bits.data + skip + node T_880 = bits(s0_pgoff, 11, 4) + node T_882 = eq(T_877, UInt<1>("h00")) + node T_883 = and(T_882, s0_valid) + wire T_885 : UInt<?> + T_885 is invalid + when T_883 : + T_885 <= T_880 + skip + read mport T_886 = T_874[T_885], clk + s1_dout[0] <= T_886 + smem T_889 : UInt<128>[256] + node T_891 = eq(repl_way, UInt<1>("h01")) + node T_892 = and(T_553.io.out.valid, T_891) + when T_892 : + node T_893 = cat(s1_idx, refill_cnt) + write mport T_894 = T_889[T_893], clk + T_894 <= T_553.io.out.bits.data + skip + node T_895 = bits(s0_pgoff, 11, 4) + node T_897 = eq(T_892, UInt<1>("h00")) + node T_898 = and(T_897, s0_valid) + wire T_900 : UInt<?> + T_900 is invalid + when T_898 : + T_900 <= T_895 + skip + read mport T_901 = T_889[T_900], clk + s1_dout[1] <= T_901 + smem T_904 : UInt<128>[256] + node T_906 = eq(repl_way, UInt<2>("h02")) + node T_907 = and(T_553.io.out.valid, T_906) + when T_907 : + node T_908 = cat(s1_idx, refill_cnt) + write mport T_909 = T_904[T_908], clk + T_909 <= T_553.io.out.bits.data + skip + node T_910 = bits(s0_pgoff, 11, 4) + node T_912 = eq(T_907, UInt<1>("h00")) + node T_913 = and(T_912, s0_valid) + wire T_915 : UInt<?> + T_915 is invalid + when T_913 : + T_915 <= T_910 + skip + read mport T_916 = T_904[T_915], clk + s1_dout[2] <= T_916 + smem T_919 : UInt<128>[256] + node T_921 = eq(repl_way, UInt<2>("h03")) + node T_922 = and(T_553.io.out.valid, T_921) + when T_922 : + node T_923 = cat(s1_idx, refill_cnt) + write mport T_924 = T_919[T_923], clk + T_924 <= T_553.io.out.bits.data + skip + node T_925 = bits(s0_pgoff, 11, 4) + node T_927 = eq(T_922, UInt<1>("h00")) + node T_928 = and(T_927, s0_valid) + wire T_930 : UInt<?> + T_930 is invalid + when T_928 : + T_930 <= T_925 + skip + read mport T_931 = T_919[T_930], clk + s1_dout[3] <= T_931 + node T_933 = mux(s1_tag_hit[0], s1_dout[0], UInt<1>("h00")) + node T_935 = mux(s1_tag_hit[1], s1_dout[1], UInt<1>("h00")) + node T_937 = mux(s1_tag_hit[2], s1_dout[2], UInt<1>("h00")) + node T_939 = mux(s1_tag_hit[3], s1_dout[3], UInt<1>("h00")) + node T_941 = or(T_933, T_935) + node T_942 = or(T_941, T_937) + node T_943 = or(T_942, T_939) + wire T_944 : UInt<128> + T_944 is invalid + T_944 <= T_943 + io.resp.bits.datablock <= T_944 io.resp.valid <= s1_hit - node T_1003 = eq(state, UInt<1>("h01")) - io.mem.acquire.valid <= T_1003 - node T_1004 = shr(refill_addr, 6) - node T_1015 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1016 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1017 = cat(T_1015, T_1016) - node T_1019 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1020 = cat(UInt<3>("h07"), T_1019) - node T_1022 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1024 = cat(UInt<1>("h00"), UInt<1>("h01")) - node T_1026 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1027 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1028 = cat(T_1026, T_1027) - node T_1030 = cat(UInt<5>("h00"), UInt<1>("h01")) - node T_1032 = cat(UInt<5>("h01"), UInt<1>("h01")) - node T_1033 = eq(UInt<3>("h06"), UInt<3>("h01")) - node T_1034 = mux(T_1033, T_1032, UInt<1>("h00")) - node T_1035 = eq(UInt<3>("h05"), UInt<3>("h01")) - node T_1036 = mux(T_1035, T_1030, T_1034) - node T_1037 = eq(UInt<3>("h04"), UInt<3>("h01")) - node T_1038 = mux(T_1037, T_1028, T_1036) - node T_1039 = eq(UInt<3>("h03"), UInt<3>("h01")) - node T_1040 = mux(T_1039, T_1024, T_1038) - node T_1041 = eq(UInt<3>("h02"), UInt<3>("h01")) - node T_1042 = mux(T_1041, T_1022, T_1040) - node T_1043 = eq(UInt<3>("h01"), UInt<3>("h01")) - node T_1044 = mux(T_1043, T_1020, T_1042) - node T_1045 = eq(UInt<3>("h00"), UInt<3>("h01")) - node T_1046 = mux(T_1045, T_1017, T_1044) - wire T_1078 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1078.data <= UInt<1>("h00") - T_1078.union <= UInt<1>("h00") - T_1078.a_type <= UInt<1>("h00") - T_1078.is_builtin_type <= UInt<1>("h00") - T_1078.addr_beat <= UInt<1>("h00") - T_1078.client_xact_id <= UInt<1>("h00") - T_1078.addr_block <= UInt<1>("h00") - T_1078.is_builtin_type <= UInt<1>("h01") - T_1078.a_type <= UInt<3>("h01") - T_1078.client_xact_id <= UInt<1>("h00") - T_1078.addr_block <= T_1004 - T_1078.addr_beat <= UInt<1>("h00") - T_1078.data <= UInt<1>("h00") - T_1078.union <= T_1046 - io.mem.acquire.bits <- T_1078 - node T_1116 = eq(UInt<1>("h00"), state) - when T_1116 : + node T_945 = eq(state, UInt<1>("h01")) + io.mem.acquire.valid <= T_945 + node T_946 = shr(refill_addr, 6) + node T_957 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_958 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_959 = cat(T_957, T_958) + node T_961 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_962 = cat(UInt<3>("h07"), T_961) + node T_964 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_966 = cat(UInt<1>("h00"), UInt<1>("h01")) + node T_968 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_969 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_970 = cat(T_968, T_969) + node T_972 = cat(UInt<5>("h00"), UInt<1>("h01")) + node T_974 = cat(UInt<5>("h01"), UInt<1>("h01")) + node T_975 = eq(UInt<3>("h06"), UInt<3>("h01")) + node T_976 = mux(T_975, T_974, UInt<1>("h00")) + node T_977 = eq(UInt<3>("h05"), UInt<3>("h01")) + node T_978 = mux(T_977, T_972, T_976) + node T_979 = eq(UInt<3>("h04"), UInt<3>("h01")) + node T_980 = mux(T_979, T_970, T_978) + node T_981 = eq(UInt<3>("h03"), UInt<3>("h01")) + node T_982 = mux(T_981, T_966, T_980) + node T_983 = eq(UInt<3>("h02"), UInt<3>("h01")) + node T_984 = mux(T_983, T_964, T_982) + node T_985 = eq(UInt<3>("h01"), UInt<3>("h01")) + node T_986 = mux(T_985, T_962, T_984) + node T_987 = eq(UInt<3>("h00"), UInt<3>("h01")) + node T_988 = mux(T_987, T_959, T_986) + wire T_1020 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} + T_1020 is invalid + T_1020.is_builtin_type <= UInt<1>("h01") + T_1020.a_type <= UInt<3>("h01") + T_1020.client_xact_id <= UInt<1>("h00") + T_1020.addr_block <= T_946 + T_1020.addr_beat <= UInt<1>("h00") + T_1020.data <= UInt<1>("h00") + T_1020.union <= T_988 + io.mem.acquire.bits <- T_1020 + node T_1051 = eq(UInt<1>("h00"), state) + when T_1051 : when s1_miss : state <= UInt<1>("h01") skip invalidated <= UInt<1>("h00") skip - node T_1118 = eq(UInt<1>("h01"), state) - when T_1118 : + node T_1053 = eq(UInt<1>("h01"), state) + when T_1053 : when io.mem.acquire.ready : state <= UInt<2>("h02") skip skip - node T_1119 = eq(UInt<2>("h02"), state) - when T_1119 : + node T_1054 = eq(UInt<2>("h02"), state) + when T_1054 : when io.mem.grant.valid : state <= UInt<2>("h03") skip skip - node T_1120 = eq(UInt<2>("h03"), state) - when T_1120 : + node T_1055 = eq(UInt<2>("h03"), state) + when T_1055 : when refill_done : state <= UInt<1>("h00") skip @@ -28157,11 +21390,9 @@ circuit Top : input reset : UInt<1> output io : {flip clear : UInt<1>, flip clear_mask : UInt<8>, flip tag : UInt<34>, hit : UInt<1>, hits : UInt<8>, valid_bits : UInt<8>, flip write : UInt<1>, flip write_tag : UInt<34>, flip write_addr : UInt<3>} - io.valid_bits <= UInt<1>("h00") - io.hits <= UInt<1>("h00") - io.hit <= UInt<1>("h00") + io is invalid cmem cam_tags : UInt<34>[8] - reg vb_array : UInt<8>, clk, reset, UInt<8>("h00") + reg vb_array : UInt<8>, clk with : (reset => (reset, UInt<8>("h00"))) when io.write : node T_21 = dshl(UInt<1>("h01"), io.write_addr) node T_22 = or(vb_array, T_21) @@ -28178,35 +21409,35 @@ circuit Top : node T_29 = and(vb_array, T_28) vb_array <= T_29 skip - node T_30 = bit(vb_array, 0) + node T_30 = bits(vb_array, 0, 0) infer mport T_32 = cam_tags[UInt<1>("h00")], clk node T_33 = eq(T_32, io.tag) node T_34 = and(T_30, T_33) - node T_35 = bit(vb_array, 1) + node T_35 = bits(vb_array, 1, 1) infer mport T_37 = cam_tags[UInt<1>("h01")], clk node T_38 = eq(T_37, io.tag) node T_39 = and(T_35, T_38) - node T_40 = bit(vb_array, 2) + node T_40 = bits(vb_array, 2, 2) infer mport T_42 = cam_tags[UInt<2>("h02")], clk node T_43 = eq(T_42, io.tag) node T_44 = and(T_40, T_43) - node T_45 = bit(vb_array, 3) + node T_45 = bits(vb_array, 3, 3) infer mport T_47 = cam_tags[UInt<2>("h03")], clk node T_48 = eq(T_47, io.tag) node T_49 = and(T_45, T_48) - node T_50 = bit(vb_array, 4) + node T_50 = bits(vb_array, 4, 4) infer mport T_52 = cam_tags[UInt<3>("h04")], clk node T_53 = eq(T_52, io.tag) node T_54 = and(T_50, T_53) - node T_55 = bit(vb_array, 5) + node T_55 = bits(vb_array, 5, 5) infer mport T_57 = cam_tags[UInt<3>("h05")], clk node T_58 = eq(T_57, io.tag) node T_59 = and(T_55, T_58) - node T_60 = bit(vb_array, 6) + node T_60 = bits(vb_array, 6, 6) infer mport T_62 = cam_tags[UInt<3>("h06")], clk node T_63 = eq(T_62, io.tag) node T_64 = and(T_60, T_63) - node T_65 = bit(vb_array, 7) + node T_65 = bits(vb_array, 7, 7) infer mport T_67 = cam_tags[UInt<3>("h07")], clk node T_68 = eq(T_67, io.tag) node T_69 = and(T_65, T_68) @@ -28236,472 +21467,444 @@ circuit Top : input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}}, resp : {miss : UInt<1>, ppn : UInt<20>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, hit_idx : UInt<8>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}} - io.ptw.req.bits.fetch <= UInt<1>("h00") - io.ptw.req.bits.store <= UInt<1>("h00") - io.ptw.req.bits.prv <= UInt<1>("h00") - io.ptw.req.bits.addr <= UInt<1>("h00") - io.ptw.req.valid <= UInt<1>("h00") - io.resp.hit_idx <= UInt<1>("h00") - io.resp.xcpt_if <= UInt<1>("h00") - io.resp.xcpt_st <= UInt<1>("h00") - io.resp.xcpt_ld <= UInt<1>("h00") - io.resp.ppn <= UInt<1>("h00") - io.resp.miss <= UInt<1>("h00") - io.req.ready <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") - reg r_refill_tag : UInt<?>, clk, UInt<1>("h00"), r_refill_tag - reg r_refill_waddr : UInt<?>, clk, UInt<1>("h00"), r_refill_waddr - reg r_req : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clk, UInt<1>("h00"), r_req + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + reg r_refill_tag : UInt<?>, clk + reg r_refill_waddr : UInt<?>, clk + reg r_req : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clk inst tag_cam of RocketCAM - tag_cam.io.write_addr <= UInt<1>("h00") - tag_cam.io.write_tag <= UInt<1>("h00") - tag_cam.io.write <= UInt<1>("h00") - tag_cam.io.tag <= UInt<1>("h00") - tag_cam.io.clear_mask <= UInt<1>("h00") - tag_cam.io.clear <= UInt<1>("h00") + tag_cam.io is invalid tag_cam.clk <= clk tag_cam.reset <= reset cmem tag_ram : UInt<20>[8] node lookup_tag = cat(io.req.bits.asid, io.req.bits.vpn) tag_cam.io.tag <= lookup_tag - node T_182 = eq(state, UInt<2>("h02")) - node T_183 = and(T_182, io.ptw.resp.valid) - tag_cam.io.write <= T_183 + node T_176 = eq(state, UInt<2>("h02")) + node T_177 = and(T_176, io.ptw.resp.valid) + tag_cam.io.write <= T_177 tag_cam.io.write_tag <= r_refill_tag tag_cam.io.write_addr <= r_refill_waddr - node T_184 = bits(tag_cam.io.hits, 7, 4) - node T_185 = bits(tag_cam.io.hits, 3, 0) - node T_187 = neq(T_184, UInt<1>("h00")) - node T_188 = or(T_184, T_185) - node T_189 = bits(T_188, 3, 2) - node T_190 = bits(T_188, 1, 0) - node T_192 = neq(T_189, UInt<1>("h00")) - node T_193 = or(T_189, T_190) - node T_194 = bit(T_193, 1) - node T_195 = cat(T_192, T_194) - node tag_hit_addr = cat(T_187, T_195) - reg valid_array : UInt<1>[8], clk, UInt<1>("h00"), valid_array - reg ur_array : UInt<1>[8], clk, UInt<1>("h00"), ur_array - reg uw_array : UInt<1>[8], clk, UInt<1>("h00"), uw_array - reg ux_array : UInt<1>[8], clk, UInt<1>("h00"), ux_array - reg sr_array : UInt<1>[8], clk, UInt<1>("h00"), sr_array - reg sw_array : UInt<1>[8], clk, UInt<1>("h00"), sw_array - reg sx_array : UInt<1>[8], clk, UInt<1>("h00"), sx_array - reg dirty_array : UInt<1>[8], clk, UInt<1>("h00"), dirty_array + node T_178 = bits(tag_cam.io.hits, 7, 4) + node T_179 = bits(tag_cam.io.hits, 3, 0) + node T_181 = neq(T_178, UInt<1>("h00")) + node T_182 = or(T_178, T_179) + node T_183 = bits(T_182, 3, 2) + node T_184 = bits(T_182, 1, 0) + node T_186 = neq(T_183, UInt<1>("h00")) + node T_187 = or(T_183, T_184) + node T_188 = bits(T_187, 1, 1) + node T_189 = cat(T_186, T_188) + node tag_hit_addr = cat(T_181, T_189) + reg valid_array : UInt<1>[8], clk + reg ur_array : UInt<1>[8], clk + reg uw_array : UInt<1>[8], clk + reg ux_array : UInt<1>[8], clk + reg sr_array : UInt<1>[8], clk + reg sw_array : UInt<1>[8], clk + reg sx_array : UInt<1>[8], clk + reg dirty_array : UInt<1>[8], clk when io.ptw.resp.valid : - infer mport T_389 = tag_ram[r_refill_waddr], clk - T_389 <= io.ptw.resp.bits.pte.ppn - node T_392 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) - valid_array[r_refill_waddr] <= T_392 - node T_395 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_396 = and(io.ptw.resp.bits.pte.v, T_395) - node T_398 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) - node T_399 = and(T_396, T_398) - node T_401 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) - node T_402 = and(T_399, T_401) - ur_array[r_refill_waddr] <= T_402 - node T_405 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_406 = and(io.ptw.resp.bits.pte.v, T_405) - node T_408 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) - node T_409 = and(T_406, T_408) - node T_410 = bit(io.ptw.resp.bits.pte.typ, 0) - node T_411 = and(T_409, T_410) - node T_413 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) - node T_414 = and(T_411, T_413) - uw_array[r_refill_waddr] <= T_414 - node T_417 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_418 = and(io.ptw.resp.bits.pte.v, T_417) - node T_420 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) - node T_421 = and(T_418, T_420) - node T_422 = bit(io.ptw.resp.bits.pte.typ, 1) - node T_423 = and(T_421, T_422) - node T_425 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) - node T_426 = and(T_423, T_425) - ux_array[r_refill_waddr] <= T_426 - node T_429 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_430 = and(io.ptw.resp.bits.pte.v, T_429) - node T_432 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) - node T_433 = and(T_430, T_432) - sr_array[r_refill_waddr] <= T_433 - node T_436 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) - node T_437 = and(io.ptw.resp.bits.pte.v, T_436) - node T_438 = bit(io.ptw.resp.bits.pte.typ, 0) - node T_439 = and(T_437, T_438) - node T_441 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) - node T_442 = and(T_439, T_441) - sw_array[r_refill_waddr] <= T_442 - node T_445 = geq(io.ptw.resp.bits.pte.typ, UInt<3>("h04")) - node T_446 = and(io.ptw.resp.bits.pte.v, T_445) - node T_447 = bit(io.ptw.resp.bits.pte.typ, 1) - node T_448 = and(T_446, T_447) - node T_450 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) - node T_451 = and(T_448, T_450) - sx_array[r_refill_waddr] <= T_451 + infer mport T_383 = tag_ram[r_refill_waddr], clk + T_383 <= io.ptw.resp.bits.pte.ppn + node T_386 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) + valid_array[r_refill_waddr] <= T_386 + node T_389 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) + node T_390 = and(io.ptw.resp.bits.pte.v, T_389) + node T_392 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) + node T_393 = and(T_390, T_392) + node T_395 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) + node T_396 = and(T_393, T_395) + ur_array[r_refill_waddr] <= T_396 + node T_399 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) + node T_400 = and(io.ptw.resp.bits.pte.v, T_399) + node T_402 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) + node T_403 = and(T_400, T_402) + node T_404 = bits(io.ptw.resp.bits.pte.typ, 0, 0) + node T_405 = and(T_403, T_404) + node T_407 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) + node T_408 = and(T_405, T_407) + uw_array[r_refill_waddr] <= T_408 + node T_411 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) + node T_412 = and(io.ptw.resp.bits.pte.v, T_411) + node T_414 = lt(io.ptw.resp.bits.pte.typ, UInt<4>("h08")) + node T_415 = and(T_412, T_414) + node T_416 = bits(io.ptw.resp.bits.pte.typ, 1, 1) + node T_417 = and(T_415, T_416) + node T_419 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) + node T_420 = and(T_417, T_419) + ux_array[r_refill_waddr] <= T_420 + node T_423 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) + node T_424 = and(io.ptw.resp.bits.pte.v, T_423) + node T_426 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) + node T_427 = and(T_424, T_426) + sr_array[r_refill_waddr] <= T_427 + node T_430 = geq(io.ptw.resp.bits.pte.typ, UInt<2>("h02")) + node T_431 = and(io.ptw.resp.bits.pte.v, T_430) + node T_432 = bits(io.ptw.resp.bits.pte.typ, 0, 0) + node T_433 = and(T_431, T_432) + node T_435 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) + node T_436 = and(T_433, T_435) + sw_array[r_refill_waddr] <= T_436 + node T_439 = geq(io.ptw.resp.bits.pte.typ, UInt<3>("h04")) + node T_440 = and(io.ptw.resp.bits.pte.v, T_439) + node T_441 = bits(io.ptw.resp.bits.pte.typ, 1, 1) + node T_442 = and(T_440, T_441) + node T_444 = eq(io.ptw.resp.bits.error, UInt<1>("h00")) + node T_445 = and(T_442, T_444) + sx_array[r_refill_waddr] <= T_445 dirty_array[r_refill_waddr] <= io.ptw.resp.bits.pte.d skip - node T_453 = not(tag_cam.io.valid_bits) - node T_455 = eq(T_453, UInt<1>("h00")) - node has_invalid_entry = eq(T_455, UInt<1>("h00")) - node T_458 = not(tag_cam.io.valid_bits) - node T_459 = bit(T_458, 0) - node T_460 = bit(T_458, 1) - node T_461 = bit(T_458, 2) - node T_462 = bit(T_458, 3) - node T_463 = bit(T_458, 4) - node T_464 = bit(T_458, 5) - node T_465 = bit(T_458, 6) - node T_466 = bit(T_458, 7) - wire T_468 : UInt<1>[8] - T_468[0] <= T_459 - T_468[1] <= T_460 - T_468[2] <= T_461 - T_468[3] <= T_462 - T_468[4] <= T_463 - T_468[5] <= T_464 - T_468[6] <= T_465 - T_468[7] <= T_466 - node T_486 = mux(T_468[6], UInt<3>("h06"), UInt<3>("h07")) - node T_487 = mux(T_468[5], UInt<3>("h05"), T_486) - node T_488 = mux(T_468[4], UInt<3>("h04"), T_487) - node T_489 = mux(T_468[3], UInt<2>("h03"), T_488) - node T_490 = mux(T_468[2], UInt<2>("h02"), T_489) - node T_491 = mux(T_468[1], UInt<1>("h01"), T_490) - node invalid_entry = mux(T_468[0], UInt<1>("h00"), T_491) - reg T_494 : UInt<8>, clk, UInt<1>("h00"), T_494 - node T_496 = dshr(T_494, UInt<1>("h01")) - node T_497 = bit(T_496, 0) - node T_498 = cat(UInt<1>("h01"), T_497) - node T_499 = dshr(T_494, T_498) - node T_500 = bit(T_499, 0) - node T_501 = cat(T_498, T_500) - node T_502 = dshr(T_494, T_501) - node T_503 = bit(T_502, 0) - node T_504 = cat(T_501, T_503) - node T_505 = bits(T_504, 2, 0) - node repl_waddr = mux(has_invalid_entry, invalid_entry, T_505) - node T_508 = eq(io.req.bits.instruction, UInt<1>("h00")) - node T_509 = and(io.ptw.status.mprv, T_508) - node priv = mux(T_509, io.ptw.status.prv1, io.ptw.status.prv) + node T_447 = not(tag_cam.io.valid_bits) + node T_449 = eq(T_447, UInt<1>("h00")) + node has_invalid_entry = eq(T_449, UInt<1>("h00")) + node T_452 = not(tag_cam.io.valid_bits) + node T_453 = bits(T_452, 0, 0) + node T_454 = bits(T_452, 1, 1) + node T_455 = bits(T_452, 2, 2) + node T_456 = bits(T_452, 3, 3) + node T_457 = bits(T_452, 4, 4) + node T_458 = bits(T_452, 5, 5) + node T_459 = bits(T_452, 6, 6) + node T_460 = bits(T_452, 7, 7) + wire T_462 : UInt<1>[8] + T_462[0] <= T_453 + T_462[1] <= T_454 + T_462[2] <= T_455 + T_462[3] <= T_456 + T_462[4] <= T_457 + T_462[5] <= T_458 + T_462[6] <= T_459 + T_462[7] <= T_460 + node T_480 = mux(T_462[6], UInt<3>("h06"), UInt<3>("h07")) + node T_481 = mux(T_462[5], UInt<3>("h05"), T_480) + node T_482 = mux(T_462[4], UInt<3>("h04"), T_481) + node T_483 = mux(T_462[3], UInt<2>("h03"), T_482) + node T_484 = mux(T_462[2], UInt<2>("h02"), T_483) + node T_485 = mux(T_462[1], UInt<1>("h01"), T_484) + node invalid_entry = mux(T_462[0], UInt<1>("h00"), T_485) + reg T_488 : UInt<8>, clk + node T_490 = dshr(T_488, UInt<1>("h01")) + node T_491 = bits(T_490, 0, 0) + node T_492 = cat(UInt<1>("h01"), T_491) + node T_493 = dshr(T_488, T_492) + node T_494 = bits(T_493, 0, 0) + node T_495 = cat(T_492, T_494) + node T_496 = dshr(T_488, T_495) + node T_497 = bits(T_496, 0, 0) + node T_498 = cat(T_495, T_497) + node T_499 = bits(T_498, 2, 0) + node repl_waddr = mux(has_invalid_entry, invalid_entry, T_499) + node T_502 = eq(io.req.bits.instruction, UInt<1>("h00")) + node T_503 = and(io.ptw.status.mprv, T_502) + node priv = mux(T_503, io.ptw.status.prv1, io.ptw.status.prv) node priv_s = eq(priv, UInt<1>("h01")) node priv_uses_vm = leq(priv, UInt<1>("h01")) - node T_516 = eq(r_req.store, UInt<1>("h00")) - node T_517 = or(r_req.instruction, r_req.store) - node T_519 = eq(T_517, UInt<1>("h00")) - node T_520 = cat(r_req.store, T_519) - node req_xwr = cat(T_516, T_520) - node T_522 = cat(sr_array[7], sr_array[6]) - node T_523 = cat(sr_array[5], sr_array[4]) - node T_524 = cat(T_522, T_523) - node T_525 = cat(sr_array[3], sr_array[2]) - node T_526 = cat(sr_array[1], sr_array[0]) - node T_527 = cat(T_525, T_526) - node T_528 = cat(T_524, T_527) - node T_529 = cat(ur_array[7], ur_array[6]) - node T_530 = cat(ur_array[5], ur_array[4]) - node T_531 = cat(T_529, T_530) - node T_532 = cat(ur_array[3], ur_array[2]) - node T_533 = cat(ur_array[1], ur_array[0]) - node T_534 = cat(T_532, T_533) - node T_535 = cat(T_531, T_534) - node r_array = mux(priv_s, T_528, T_535) - node T_537 = cat(sw_array[7], sw_array[6]) - node T_538 = cat(sw_array[5], sw_array[4]) - node T_539 = cat(T_537, T_538) - node T_540 = cat(sw_array[3], sw_array[2]) - node T_541 = cat(sw_array[1], sw_array[0]) - node T_542 = cat(T_540, T_541) - node T_543 = cat(T_539, T_542) - node T_544 = cat(uw_array[7], uw_array[6]) - node T_545 = cat(uw_array[5], uw_array[4]) - node T_546 = cat(T_544, T_545) - node T_547 = cat(uw_array[3], uw_array[2]) - node T_548 = cat(uw_array[1], uw_array[0]) - node T_549 = cat(T_547, T_548) - node T_550 = cat(T_546, T_549) - node w_array = mux(priv_s, T_543, T_550) - node T_552 = cat(sx_array[7], sx_array[6]) - node T_553 = cat(sx_array[5], sx_array[4]) - node T_554 = cat(T_552, T_553) - node T_555 = cat(sx_array[3], sx_array[2]) - node T_556 = cat(sx_array[1], sx_array[0]) - node T_557 = cat(T_555, T_556) - node T_558 = cat(T_554, T_557) - node T_559 = cat(ux_array[7], ux_array[6]) - node T_560 = cat(ux_array[5], ux_array[4]) - node T_561 = cat(T_559, T_560) - node T_562 = cat(ux_array[3], ux_array[2]) - node T_563 = cat(ux_array[1], ux_array[0]) - node T_564 = cat(T_562, T_563) - node T_565 = cat(T_561, T_564) - node x_array = mux(priv_s, T_558, T_565) - node T_567 = bit(io.ptw.status.vm, 3) - node T_568 = and(T_567, priv_uses_vm) - node T_570 = eq(io.req.bits.passthrough, UInt<1>("h00")) - node vm_enabled = and(T_568, T_570) - node T_572 = bit(io.req.bits.vpn, 27) - node T_573 = bit(io.req.bits.vpn, 26) - node bad_va = neq(T_572, T_573) - node T_575 = cat(dirty_array[7], dirty_array[6]) - node T_576 = cat(dirty_array[5], dirty_array[4]) - node T_577 = cat(T_575, T_576) - node T_578 = cat(dirty_array[3], dirty_array[2]) - node T_579 = cat(dirty_array[1], dirty_array[0]) - node T_580 = cat(T_578, T_579) - node T_581 = cat(T_577, T_580) - node T_583 = mux(io.req.bits.store, w_array, UInt<1>("h00")) - node T_584 = not(T_583) - node T_585 = or(T_581, T_584) - node tag_hits = and(tag_cam.io.hits, T_585) + node T_510 = eq(r_req.store, UInt<1>("h00")) + node T_511 = or(r_req.instruction, r_req.store) + node T_513 = eq(T_511, UInt<1>("h00")) + node T_514 = cat(r_req.store, T_513) + node req_xwr = cat(T_510, T_514) + node T_516 = cat(sr_array[7], sr_array[6]) + node T_517 = cat(sr_array[5], sr_array[4]) + node T_518 = cat(T_516, T_517) + node T_519 = cat(sr_array[3], sr_array[2]) + node T_520 = cat(sr_array[1], sr_array[0]) + node T_521 = cat(T_519, T_520) + node T_522 = cat(T_518, T_521) + node T_523 = cat(ur_array[7], ur_array[6]) + node T_524 = cat(ur_array[5], ur_array[4]) + node T_525 = cat(T_523, T_524) + node T_526 = cat(ur_array[3], ur_array[2]) + node T_527 = cat(ur_array[1], ur_array[0]) + node T_528 = cat(T_526, T_527) + node T_529 = cat(T_525, T_528) + node r_array = mux(priv_s, T_522, T_529) + node T_531 = cat(sw_array[7], sw_array[6]) + node T_532 = cat(sw_array[5], sw_array[4]) + node T_533 = cat(T_531, T_532) + node T_534 = cat(sw_array[3], sw_array[2]) + node T_535 = cat(sw_array[1], sw_array[0]) + node T_536 = cat(T_534, T_535) + node T_537 = cat(T_533, T_536) + node T_538 = cat(uw_array[7], uw_array[6]) + node T_539 = cat(uw_array[5], uw_array[4]) + node T_540 = cat(T_538, T_539) + node T_541 = cat(uw_array[3], uw_array[2]) + node T_542 = cat(uw_array[1], uw_array[0]) + node T_543 = cat(T_541, T_542) + node T_544 = cat(T_540, T_543) + node w_array = mux(priv_s, T_537, T_544) + node T_546 = cat(sx_array[7], sx_array[6]) + node T_547 = cat(sx_array[5], sx_array[4]) + node T_548 = cat(T_546, T_547) + node T_549 = cat(sx_array[3], sx_array[2]) + node T_550 = cat(sx_array[1], sx_array[0]) + node T_551 = cat(T_549, T_550) + node T_552 = cat(T_548, T_551) + node T_553 = cat(ux_array[7], ux_array[6]) + node T_554 = cat(ux_array[5], ux_array[4]) + node T_555 = cat(T_553, T_554) + node T_556 = cat(ux_array[3], ux_array[2]) + node T_557 = cat(ux_array[1], ux_array[0]) + node T_558 = cat(T_556, T_557) + node T_559 = cat(T_555, T_558) + node x_array = mux(priv_s, T_552, T_559) + node T_561 = bits(io.ptw.status.vm, 3, 3) + node T_562 = and(T_561, priv_uses_vm) + node T_564 = eq(io.req.bits.passthrough, UInt<1>("h00")) + node vm_enabled = and(T_562, T_564) + node T_566 = bits(io.req.bits.vpn, 27, 27) + node T_567 = bits(io.req.bits.vpn, 26, 26) + node bad_va = neq(T_566, T_567) + node T_569 = cat(dirty_array[7], dirty_array[6]) + node T_570 = cat(dirty_array[5], dirty_array[4]) + node T_571 = cat(T_569, T_570) + node T_572 = cat(dirty_array[3], dirty_array[2]) + node T_573 = cat(dirty_array[1], dirty_array[0]) + node T_574 = cat(T_572, T_573) + node T_575 = cat(T_571, T_574) + node T_577 = mux(io.req.bits.store, w_array, UInt<1>("h00")) + node T_578 = not(T_577) + node T_579 = or(T_575, T_578) + node tag_hits = and(tag_cam.io.hits, T_579) node tag_hit = neq(tag_hits, UInt<1>("h00")) node tlb_hit = and(vm_enabled, tag_hit) - node T_591 = eq(tag_hit, UInt<1>("h00")) - node T_592 = and(vm_enabled, T_591) - node T_594 = eq(bad_va, UInt<1>("h00")) - node tlb_miss = and(T_592, T_594) - node T_596 = and(io.req.valid, tlb_hit) - when T_596 : - node T_597 = bits(tag_cam.io.hits, 7, 4) - node T_598 = bits(tag_cam.io.hits, 3, 0) - node T_600 = neq(T_597, UInt<1>("h00")) - node T_601 = or(T_597, T_598) - node T_602 = bits(T_601, 3, 2) - node T_603 = bits(T_601, 1, 0) - node T_605 = neq(T_602, UInt<1>("h00")) - node T_606 = or(T_602, T_603) - node T_607 = bit(T_606, 1) - node T_608 = cat(T_605, T_607) - node T_609 = cat(T_600, T_608) - node T_611 = bit(T_609, 2) - node T_613 = dshl(UInt<8>("h01"), UInt<1>("h01")) - node T_614 = bits(T_613, 7, 0) - node T_615 = not(T_614) - node T_616 = and(T_494, T_615) - node T_618 = mux(T_611, UInt<1>("h00"), T_614) - node T_619 = or(T_616, T_618) - node T_620 = cat(UInt<1>("h01"), T_611) - node T_621 = bit(T_609, 1) - node T_623 = dshl(UInt<8>("h01"), T_620) - node T_624 = bits(T_623, 7, 0) - node T_625 = not(T_624) - node T_626 = and(T_619, T_625) - node T_628 = mux(T_621, UInt<1>("h00"), T_624) - node T_629 = or(T_626, T_628) - node T_630 = cat(T_620, T_621) - node T_631 = bit(T_609, 0) - node T_633 = dshl(UInt<8>("h01"), T_630) - node T_634 = bits(T_633, 7, 0) - node T_635 = not(T_634) - node T_636 = and(T_629, T_635) - node T_638 = mux(T_631, UInt<1>("h00"), T_634) - node T_639 = or(T_636, T_638) - node T_640 = cat(T_630, T_631) - T_494 <= T_639 + node T_585 = eq(tag_hit, UInt<1>("h00")) + node T_586 = and(vm_enabled, T_585) + node T_588 = eq(bad_va, UInt<1>("h00")) + node tlb_miss = and(T_586, T_588) + node T_590 = and(io.req.valid, tlb_hit) + when T_590 : + node T_591 = bits(tag_cam.io.hits, 7, 4) + node T_592 = bits(tag_cam.io.hits, 3, 0) + node T_594 = neq(T_591, UInt<1>("h00")) + node T_595 = or(T_591, T_592) + node T_596 = bits(T_595, 3, 2) + node T_597 = bits(T_595, 1, 0) + node T_599 = neq(T_596, UInt<1>("h00")) + node T_600 = or(T_596, T_597) + node T_601 = bits(T_600, 1, 1) + node T_602 = cat(T_599, T_601) + node T_603 = cat(T_594, T_602) + node T_605 = bits(T_603, 2, 2) + node T_607 = dshl(UInt<8>("h01"), UInt<1>("h01")) + node T_608 = bits(T_607, 7, 0) + node T_609 = not(T_608) + node T_610 = and(T_488, T_609) + node T_612 = mux(T_605, UInt<1>("h00"), T_608) + node T_613 = or(T_610, T_612) + node T_614 = cat(UInt<1>("h01"), T_605) + node T_615 = bits(T_603, 1, 1) + node T_617 = dshl(UInt<8>("h01"), T_614) + node T_618 = bits(T_617, 7, 0) + node T_619 = not(T_618) + node T_620 = and(T_613, T_619) + node T_622 = mux(T_615, UInt<1>("h00"), T_618) + node T_623 = or(T_620, T_622) + node T_624 = cat(T_614, T_615) + node T_625 = bits(T_603, 0, 0) + node T_627 = dshl(UInt<8>("h01"), T_624) + node T_628 = bits(T_627, 7, 0) + node T_629 = not(T_628) + node T_630 = and(T_623, T_629) + node T_632 = mux(T_625, UInt<1>("h00"), T_628) + node T_633 = or(T_630, T_632) + node T_634 = cat(T_624, T_625) + T_488 <= T_633 skip node paddr = cat(io.resp.ppn, UInt<12>("h00")) - node T_644 = geq(paddr, UInt<1>("h00")) - node T_646 = lt(paddr, UInt<31>("h040000000")) - node T_647 = and(T_644, T_646) - node T_649 = geq(paddr, UInt<31>("h040000000")) - node T_651 = lt(paddr, UInt<31>("h040008000")) - node T_652 = and(T_649, T_651) - node T_654 = geq(paddr, UInt<31>("h040008000")) - node T_656 = lt(paddr, UInt<31>("h040010000")) - node T_657 = and(T_654, T_656) - node T_659 = geq(paddr, UInt<31>("h040010000")) - node T_661 = lt(paddr, UInt<31>("h040010200")) - node T_662 = and(T_659, T_661) - node T_664 = geq(paddr, UInt<32>("h080000000")) - node T_666 = lt(paddr, UInt<33>("h0100000000")) - node T_667 = and(T_664, T_666) - node T_668 = or(T_647, T_652) - node T_669 = or(T_668, T_657) - node T_670 = or(T_669, T_662) - node addr_ok = or(T_670, T_667) - node T_673 = geq(paddr, UInt<1>("h00")) - node T_675 = lt(paddr, UInt<31>("h040000000")) - node T_676 = and(T_673, T_675) - wire T_686 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} - T_686.r <= UInt<1>("h00") - T_686.w <= UInt<1>("h00") - T_686.x <= UInt<1>("h00") - T_686.r <= UInt<1>("h01") - T_686.w <= UInt<1>("h01") - T_686.x <= UInt<1>("h01") - node T_697 = geq(paddr, UInt<31>("h040000000")) - node T_699 = lt(paddr, UInt<31>("h040008000")) - node T_700 = and(T_697, T_699) - wire T_710 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} - T_710.r <= UInt<1>("h00") - T_710.w <= UInt<1>("h00") - T_710.x <= UInt<1>("h00") - T_710.r <= UInt<1>("h01") - T_710.w <= UInt<1>("h00") - T_710.x <= UInt<1>("h00") - node T_721 = geq(paddr, UInt<31>("h040008000")) - node T_723 = lt(paddr, UInt<31>("h040010000")) - node T_724 = and(T_721, T_723) - wire T_734 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} - T_734.r <= UInt<1>("h00") - T_734.w <= UInt<1>("h00") - T_734.x <= UInt<1>("h00") - T_734.r <= UInt<1>("h01") - T_734.w <= UInt<1>("h01") - T_734.x <= UInt<1>("h00") - node T_745 = geq(paddr, UInt<31>("h040010000")) - node T_747 = lt(paddr, UInt<31>("h040010200")) - node T_748 = and(T_745, T_747) - wire T_758 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} - T_758.r <= UInt<1>("h00") - T_758.w <= UInt<1>("h00") - T_758.x <= UInt<1>("h00") - T_758.r <= UInt<1>("h01") - T_758.w <= UInt<1>("h01") - T_758.x <= UInt<1>("h00") - node T_769 = geq(paddr, UInt<32>("h080000000")) - node T_771 = lt(paddr, UInt<33>("h0100000000")) - node T_772 = and(T_769, T_771) - wire T_782 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} - T_782.r <= UInt<1>("h00") - T_782.w <= UInt<1>("h00") - T_782.x <= UInt<1>("h00") - T_782.r <= UInt<1>("h01") - T_782.w <= UInt<1>("h01") - T_782.x <= UInt<1>("h00") - node T_792 = cat(T_686.w, T_686.r) - node T_793 = cat(T_686.x, T_792) - node T_795 = mux(T_676, T_793, UInt<1>("h00")) - node T_796 = cat(T_710.w, T_710.r) - node T_797 = cat(T_710.x, T_796) - node T_799 = mux(T_700, T_797, UInt<1>("h00")) - node T_800 = cat(T_734.w, T_734.r) - node T_801 = cat(T_734.x, T_800) - node T_803 = mux(T_724, T_801, UInt<1>("h00")) - node T_804 = cat(T_758.w, T_758.r) - node T_805 = cat(T_758.x, T_804) - node T_807 = mux(T_748, T_805, UInt<1>("h00")) - node T_808 = cat(T_782.w, T_782.r) - node T_809 = cat(T_782.x, T_808) - node T_811 = mux(T_772, T_809, UInt<1>("h00")) - node T_816 = or(T_795, T_799) - node T_817 = or(T_816, T_803) - node T_818 = or(T_817, T_807) - node T_819 = or(T_818, T_811) + node T_638 = geq(paddr, UInt<1>("h00")) + node T_640 = lt(paddr, UInt<31>("h040000000")) + node T_641 = and(T_638, T_640) + node T_643 = geq(paddr, UInt<31>("h040000000")) + node T_645 = lt(paddr, UInt<31>("h040008000")) + node T_646 = and(T_643, T_645) + node T_648 = geq(paddr, UInt<31>("h040008000")) + node T_650 = lt(paddr, UInt<31>("h040010000")) + node T_651 = and(T_648, T_650) + node T_653 = geq(paddr, UInt<31>("h040010000")) + node T_655 = lt(paddr, UInt<31>("h040010200")) + node T_656 = and(T_653, T_655) + node T_658 = geq(paddr, UInt<32>("h080000000")) + node T_660 = lt(paddr, UInt<33>("h0100000000")) + node T_661 = and(T_658, T_660) + node T_662 = or(T_641, T_646) + node T_663 = or(T_662, T_651) + node T_664 = or(T_663, T_656) + node addr_ok = or(T_664, T_661) + node T_667 = geq(paddr, UInt<1>("h00")) + node T_669 = lt(paddr, UInt<31>("h040000000")) + node T_670 = and(T_667, T_669) + wire T_680 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} + T_680 is invalid + T_680.r <= UInt<1>("h01") + T_680.w <= UInt<1>("h01") + T_680.x <= UInt<1>("h01") + node T_688 = geq(paddr, UInt<31>("h040000000")) + node T_690 = lt(paddr, UInt<31>("h040008000")) + node T_691 = and(T_688, T_690) + wire T_701 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} + T_701 is invalid + T_701.r <= UInt<1>("h01") + T_701.w <= UInt<1>("h00") + T_701.x <= UInt<1>("h00") + node T_709 = geq(paddr, UInt<31>("h040008000")) + node T_711 = lt(paddr, UInt<31>("h040010000")) + node T_712 = and(T_709, T_711) + wire T_722 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} + T_722 is invalid + T_722.r <= UInt<1>("h01") + T_722.w <= UInt<1>("h01") + T_722.x <= UInt<1>("h00") + node T_730 = geq(paddr, UInt<31>("h040010000")) + node T_732 = lt(paddr, UInt<31>("h040010200")) + node T_733 = and(T_730, T_732) + wire T_743 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} + T_743 is invalid + T_743.r <= UInt<1>("h01") + T_743.w <= UInt<1>("h01") + T_743.x <= UInt<1>("h00") + node T_751 = geq(paddr, UInt<32>("h080000000")) + node T_753 = lt(paddr, UInt<33>("h0100000000")) + node T_754 = and(T_751, T_753) + wire T_764 : {x : UInt<1>, w : UInt<1>, r : UInt<1>} + T_764 is invalid + T_764.r <= UInt<1>("h01") + T_764.w <= UInt<1>("h01") + T_764.x <= UInt<1>("h00") + node T_771 = cat(T_680.w, T_680.r) + node T_772 = cat(T_680.x, T_771) + node T_774 = mux(T_670, T_772, UInt<1>("h00")) + node T_775 = cat(T_701.w, T_701.r) + node T_776 = cat(T_701.x, T_775) + node T_778 = mux(T_691, T_776, UInt<1>("h00")) + node T_779 = cat(T_722.w, T_722.r) + node T_780 = cat(T_722.x, T_779) + node T_782 = mux(T_712, T_780, UInt<1>("h00")) + node T_783 = cat(T_743.w, T_743.r) + node T_784 = cat(T_743.x, T_783) + node T_786 = mux(T_733, T_784, UInt<1>("h00")) + node T_787 = cat(T_764.w, T_764.r) + node T_788 = cat(T_764.x, T_787) + node T_790 = mux(T_754, T_788, UInt<1>("h00")) + node T_795 = or(T_774, T_778) + node T_796 = or(T_795, T_782) + node T_797 = or(T_796, T_786) + node T_798 = or(T_797, T_790) wire addr_prot : {x : UInt<1>, w : UInt<1>, r : UInt<1>} - addr_prot.r <= UInt<1>("h00") - addr_prot.w <= UInt<1>("h00") - addr_prot.x <= UInt<1>("h00") - node T_831 = bits(T_819, 0, 0) - addr_prot.r <= T_831 - node T_832 = bits(T_819, 1, 1) - addr_prot.w <= T_832 - node T_833 = bits(T_819, 2, 2) - addr_prot.x <= T_833 - node T_834 = eq(state, UInt<1>("h00")) - io.req.ready <= T_834 - node T_836 = eq(addr_ok, UInt<1>("h00")) - node T_838 = eq(addr_prot.r, UInt<1>("h00")) - node T_839 = or(T_836, T_838) - node T_840 = or(T_839, bad_va) - node T_841 = and(r_array, tag_cam.io.hits) - node T_843 = neq(T_841, UInt<1>("h00")) - node T_845 = eq(T_843, UInt<1>("h00")) - node T_846 = and(tlb_hit, T_845) - node T_847 = or(T_840, T_846) - io.resp.xcpt_ld <= T_847 - node T_849 = eq(addr_ok, UInt<1>("h00")) - node T_851 = eq(addr_prot.w, UInt<1>("h00")) - node T_852 = or(T_849, T_851) - node T_853 = or(T_852, bad_va) - node T_854 = and(w_array, tag_cam.io.hits) - node T_856 = neq(T_854, UInt<1>("h00")) - node T_858 = eq(T_856, UInt<1>("h00")) - node T_859 = and(tlb_hit, T_858) - node T_860 = or(T_853, T_859) - io.resp.xcpt_st <= T_860 - node T_862 = eq(addr_ok, UInt<1>("h00")) - node T_864 = eq(addr_prot.x, UInt<1>("h00")) - node T_865 = or(T_862, T_864) - node T_866 = or(T_865, bad_va) - node T_867 = and(x_array, tag_cam.io.hits) - node T_869 = neq(T_867, UInt<1>("h00")) - node T_871 = eq(T_869, UInt<1>("h00")) - node T_872 = and(tlb_hit, T_871) - node T_873 = or(T_866, T_872) - io.resp.xcpt_if <= T_873 + addr_prot is invalid + node T_807 = bits(T_798, 0, 0) + addr_prot.r <= T_807 + node T_808 = bits(T_798, 1, 1) + addr_prot.w <= T_808 + node T_809 = bits(T_798, 2, 2) + addr_prot.x <= T_809 + node T_810 = eq(state, UInt<1>("h00")) + io.req.ready <= T_810 + node T_812 = eq(addr_ok, UInt<1>("h00")) + node T_814 = eq(addr_prot.r, UInt<1>("h00")) + node T_815 = or(T_812, T_814) + node T_816 = or(T_815, bad_va) + node T_817 = and(r_array, tag_cam.io.hits) + node T_819 = neq(T_817, UInt<1>("h00")) + node T_821 = eq(T_819, UInt<1>("h00")) + node T_822 = and(tlb_hit, T_821) + node T_823 = or(T_816, T_822) + io.resp.xcpt_ld <= T_823 + node T_825 = eq(addr_ok, UInt<1>("h00")) + node T_827 = eq(addr_prot.w, UInt<1>("h00")) + node T_828 = or(T_825, T_827) + node T_829 = or(T_828, bad_va) + node T_830 = and(w_array, tag_cam.io.hits) + node T_832 = neq(T_830, UInt<1>("h00")) + node T_834 = eq(T_832, UInt<1>("h00")) + node T_835 = and(tlb_hit, T_834) + node T_836 = or(T_829, T_835) + io.resp.xcpt_st <= T_836 + node T_838 = eq(addr_ok, UInt<1>("h00")) + node T_840 = eq(addr_prot.x, UInt<1>("h00")) + node T_841 = or(T_838, T_840) + node T_842 = or(T_841, bad_va) + node T_843 = and(x_array, tag_cam.io.hits) + node T_845 = neq(T_843, UInt<1>("h00")) + node T_847 = eq(T_845, UInt<1>("h00")) + node T_848 = and(tlb_hit, T_847) + node T_849 = or(T_842, T_848) + io.resp.xcpt_if <= T_849 io.resp.miss <= tlb_miss - node T_874 = bit(tag_cam.io.hits, 0) - node T_875 = bit(tag_cam.io.hits, 1) - node T_876 = bit(tag_cam.io.hits, 2) - node T_877 = bit(tag_cam.io.hits, 3) - node T_878 = bit(tag_cam.io.hits, 4) - node T_879 = bit(tag_cam.io.hits, 5) - node T_880 = bit(tag_cam.io.hits, 6) - node T_881 = bit(tag_cam.io.hits, 7) - infer mport T_883 = tag_ram[UInt<1>("h00")], clk - infer mport T_885 = tag_ram[UInt<1>("h01")], clk - infer mport T_887 = tag_ram[UInt<2>("h02")], clk - infer mport T_889 = tag_ram[UInt<2>("h03")], clk - infer mport T_891 = tag_ram[UInt<3>("h04")], clk - infer mport T_893 = tag_ram[UInt<3>("h05")], clk - infer mport T_895 = tag_ram[UInt<3>("h06")], clk - infer mport T_897 = tag_ram[UInt<3>("h07")], clk - node T_899 = mux(T_874, T_883, UInt<1>("h00")) - node T_901 = mux(T_875, T_885, UInt<1>("h00")) - node T_903 = mux(T_876, T_887, UInt<1>("h00")) - node T_905 = mux(T_877, T_889, UInt<1>("h00")) - node T_907 = mux(T_878, T_891, UInt<1>("h00")) - node T_909 = mux(T_879, T_893, UInt<1>("h00")) - node T_911 = mux(T_880, T_895, UInt<1>("h00")) - node T_913 = mux(T_881, T_897, UInt<1>("h00")) - node T_915 = or(T_899, T_901) - node T_916 = or(T_915, T_903) - node T_917 = or(T_916, T_905) - node T_918 = or(T_917, T_907) - node T_919 = or(T_918, T_909) - node T_920 = or(T_919, T_911) - node T_921 = or(T_920, T_913) - wire T_922 : UInt<20> - T_922 <= UInt<1>("h00") - T_922 <= T_921 - node T_924 = bits(io.req.bits.vpn, 19, 0) - node T_925 = mux(vm_enabled, T_922, T_924) - io.resp.ppn <= T_925 + node T_850 = bits(tag_cam.io.hits, 0, 0) + node T_851 = bits(tag_cam.io.hits, 1, 1) + node T_852 = bits(tag_cam.io.hits, 2, 2) + node T_853 = bits(tag_cam.io.hits, 3, 3) + node T_854 = bits(tag_cam.io.hits, 4, 4) + node T_855 = bits(tag_cam.io.hits, 5, 5) + node T_856 = bits(tag_cam.io.hits, 6, 6) + node T_857 = bits(tag_cam.io.hits, 7, 7) + infer mport T_859 = tag_ram[UInt<1>("h00")], clk + infer mport T_861 = tag_ram[UInt<1>("h01")], clk + infer mport T_863 = tag_ram[UInt<2>("h02")], clk + infer mport T_865 = tag_ram[UInt<2>("h03")], clk + infer mport T_867 = tag_ram[UInt<3>("h04")], clk + infer mport T_869 = tag_ram[UInt<3>("h05")], clk + infer mport T_871 = tag_ram[UInt<3>("h06")], clk + infer mport T_873 = tag_ram[UInt<3>("h07")], clk + node T_875 = mux(T_850, T_859, UInt<1>("h00")) + node T_877 = mux(T_851, T_861, UInt<1>("h00")) + node T_879 = mux(T_852, T_863, UInt<1>("h00")) + node T_881 = mux(T_853, T_865, UInt<1>("h00")) + node T_883 = mux(T_854, T_867, UInt<1>("h00")) + node T_885 = mux(T_855, T_869, UInt<1>("h00")) + node T_887 = mux(T_856, T_871, UInt<1>("h00")) + node T_889 = mux(T_857, T_873, UInt<1>("h00")) + node T_891 = or(T_875, T_877) + node T_892 = or(T_891, T_879) + node T_893 = or(T_892, T_881) + node T_894 = or(T_893, T_883) + node T_895 = or(T_894, T_885) + node T_896 = or(T_895, T_887) + node T_897 = or(T_896, T_889) + wire T_898 : UInt<20> + T_898 is invalid + T_898 <= T_897 + node T_899 = bits(io.req.bits.vpn, 19, 0) + node T_900 = mux(vm_enabled, T_898, T_899) + io.resp.ppn <= T_900 io.resp.hit_idx <= tag_cam.io.hits - node T_926 = and(io.req.ready, io.req.valid) - node T_927 = or(io.ptw.invalidate, T_926) - tag_cam.io.clear <= T_927 - node T_928 = cat(valid_array[7], valid_array[6]) - node T_929 = cat(valid_array[5], valid_array[4]) - node T_930 = cat(T_928, T_929) - node T_931 = cat(valid_array[3], valid_array[2]) - node T_932 = cat(valid_array[1], valid_array[0]) - node T_933 = cat(T_931, T_932) - node T_934 = cat(T_930, T_933) - node T_935 = not(T_934) - node T_936 = not(tag_hits) - node T_937 = and(tag_cam.io.hits, T_936) - node T_938 = or(T_935, T_937) - tag_cam.io.clear_mask <= T_938 + node T_901 = and(io.req.ready, io.req.valid) + node T_902 = or(io.ptw.invalidate, T_901) + tag_cam.io.clear <= T_902 + node T_903 = cat(valid_array[7], valid_array[6]) + node T_904 = cat(valid_array[5], valid_array[4]) + node T_905 = cat(T_903, T_904) + node T_906 = cat(valid_array[3], valid_array[2]) + node T_907 = cat(valid_array[1], valid_array[0]) + node T_908 = cat(T_906, T_907) + node T_909 = cat(T_905, T_908) + node T_910 = not(T_909) + node T_911 = not(tag_hits) + node T_912 = and(tag_cam.io.hits, T_911) + node T_913 = or(T_910, T_912) + tag_cam.io.clear_mask <= T_913 when io.ptw.invalidate : - node T_940 = not(UInt<8>("h00")) - tag_cam.io.clear_mask <= T_940 + node T_915 = not(UInt<8>("h00")) + tag_cam.io.clear_mask <= T_915 skip - node T_941 = eq(state, UInt<1>("h01")) - io.ptw.req.valid <= T_941 + node T_916 = eq(state, UInt<1>("h01")) + io.ptw.req.valid <= T_916 io.ptw.req.bits.addr <= r_refill_tag io.ptw.req.bits.prv <= io.ptw.status.prv io.ptw.req.bits.store <= r_req.store io.ptw.req.bits.fetch <= r_req.instruction - node T_942 = and(io.req.ready, io.req.valid) - node T_943 = and(T_942, tlb_miss) - when T_943 : + node T_917 = and(io.req.ready, io.req.valid) + node T_918 = and(T_917, tlb_miss) + when T_918 : state <= UInt<1>("h01") r_refill_tag <= lookup_tag r_refill_waddr <= repl_waddr r_req <- io.req.bits skip - node T_944 = eq(state, UInt<1>("h01")) - when T_944 : + node T_919 = eq(state, UInt<1>("h01")) + when T_919 : when io.ptw.invalidate : state <= UInt<1>("h00") skip @@ -28712,9 +21915,9 @@ circuit Top : skip skip skip - node T_945 = eq(state, UInt<2>("h02")) - node T_946 = and(T_945, io.ptw.invalidate) - when T_946 : + node T_920 = eq(state, UInt<2>("h02")) + node T_921 = and(T_920, io.ptw.invalidate) + when T_921 : state <= UInt<2>("h03") skip when io.ptw.resp.valid : @@ -28726,13 +21929,9 @@ circuit Top : input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}}, count : UInt<1>} - io.count <= UInt<1>("h00") - io.deq.bits.datablock <= UInt<1>("h00") - io.deq.bits.data <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : {data : UInt<32>, datablock : UInt<128>}[1] - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(UInt<1>("h00"), UInt<1>("h00")) node T_463 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_463) @@ -28764,195 +21963,81 @@ circuit Top : node T_538 = or(T_535, T_537) io.enq.ready <= T_538 infer mport T_539 = ram[UInt<1>("h00")], clk - wire T_637 : {data : UInt<32>, datablock : UInt<128>} - T_637 <- T_539 - when maybe_flow : - T_637 <- io.enq.bits - skip - io.deq.bits <- T_637 - node ptr_diff = subw(UInt<1>("h00"), UInt<1>("h00")) - node T_687 = and(maybe_full, ptr_match) - node T_688 = cat(T_687, ptr_diff) - io.count <= T_688 + node T_588 = mux(maybe_flow, io.enq.bits, T_539) + io.deq.bits <- T_588 + node T_637 = sub(UInt<1>("h00"), UInt<1>("h00")) + node ptr_diff = tail(T_637, 1) + node T_639 = and(maybe_full, ptr_match) + node T_640 = cat(T_639, ptr_diff) + io.count <= T_640 module Frontend : input clk : Clock input reset : UInt<1> output io : {flip cpu : {req : {valid : UInt<1>, bits : {pc : UInt<40>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {pc : UInt<40>, data : UInt<32>[1], mask : UInt<1>, xcpt_if : UInt<1>}}, flip btb_resp : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, btb_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, target : UInt<39>, taken : UInt<1>, isJump : UInt<1>, isReturn : UInt<1>, br_pc : UInt<39>}}, bht_update : {valid : UInt<1>, bits : {prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}, pc : UInt<39>, taken : UInt<1>, mispredict : UInt<1>}}, ras_update : {valid : UInt<1>, bits : {isCall : UInt<1>, isReturn : UInt<1>, returnAddr : UInt<39>, prediction : {valid : UInt<1>, bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}}}}, invalidate : UInt<1>, flip npc : UInt<40>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}} - io.mem.grant.ready <= UInt<1>("h00") - io.mem.acquire.bits.data <= UInt<1>("h00") - io.mem.acquire.bits.union <= UInt<1>("h00") - io.mem.acquire.bits.a_type <= UInt<1>("h00") - io.mem.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.mem.acquire.bits.addr_beat <= UInt<1>("h00") - io.mem.acquire.bits.client_xact_id <= UInt<1>("h00") - io.mem.acquire.bits.addr_block <= UInt<1>("h00") - io.mem.acquire.valid <= UInt<1>("h00") - io.ptw.req.bits.fetch <= UInt<1>("h00") - io.ptw.req.bits.store <= UInt<1>("h00") - io.ptw.req.bits.prv <= UInt<1>("h00") - io.ptw.req.bits.addr <= UInt<1>("h00") - io.ptw.req.valid <= UInt<1>("h00") - io.cpu.npc <= UInt<1>("h00") - io.cpu.btb_resp.bits.bht.value <= UInt<1>("h00") - io.cpu.btb_resp.bits.bht.history <= UInt<1>("h00") - io.cpu.btb_resp.bits.entry <= UInt<1>("h00") - io.cpu.btb_resp.bits.target <= UInt<1>("h00") - io.cpu.btb_resp.bits.bridx <= UInt<1>("h00") - io.cpu.btb_resp.bits.mask <= UInt<1>("h00") - io.cpu.btb_resp.bits.taken <= UInt<1>("h00") - io.cpu.btb_resp.valid <= UInt<1>("h00") - io.cpu.resp.bits.xcpt_if <= UInt<1>("h00") - io.cpu.resp.bits.mask <= UInt<1>("h00") - io.cpu.resp.bits.data[0] <= UInt<1>("h00") - io.cpu.resp.bits.pc <= UInt<1>("h00") - io.cpu.resp.valid <= UInt<1>("h00") + io is invalid inst btb of BTB - btb.io.invalidate <= UInt<1>("h00") - btb.io.ras_update.bits.prediction.bits.bht.value <= UInt<1>("h00") - btb.io.ras_update.bits.prediction.bits.bht.history <= UInt<1>("h00") - btb.io.ras_update.bits.prediction.bits.entry <= UInt<1>("h00") - btb.io.ras_update.bits.prediction.bits.target <= UInt<1>("h00") - btb.io.ras_update.bits.prediction.bits.bridx <= UInt<1>("h00") - btb.io.ras_update.bits.prediction.bits.mask <= UInt<1>("h00") - btb.io.ras_update.bits.prediction.bits.taken <= UInt<1>("h00") - btb.io.ras_update.bits.prediction.valid <= UInt<1>("h00") - btb.io.ras_update.bits.returnAddr <= UInt<1>("h00") - btb.io.ras_update.bits.isReturn <= UInt<1>("h00") - btb.io.ras_update.bits.isCall <= UInt<1>("h00") - btb.io.ras_update.valid <= UInt<1>("h00") - btb.io.bht_update.bits.mispredict <= UInt<1>("h00") - btb.io.bht_update.bits.taken <= UInt<1>("h00") - btb.io.bht_update.bits.pc <= UInt<1>("h00") - btb.io.bht_update.bits.prediction.bits.bht.value <= UInt<1>("h00") - btb.io.bht_update.bits.prediction.bits.bht.history <= UInt<1>("h00") - btb.io.bht_update.bits.prediction.bits.entry <= UInt<1>("h00") - btb.io.bht_update.bits.prediction.bits.target <= UInt<1>("h00") - btb.io.bht_update.bits.prediction.bits.bridx <= UInt<1>("h00") - btb.io.bht_update.bits.prediction.bits.mask <= UInt<1>("h00") - btb.io.bht_update.bits.prediction.bits.taken <= UInt<1>("h00") - btb.io.bht_update.bits.prediction.valid <= UInt<1>("h00") - btb.io.bht_update.valid <= UInt<1>("h00") - btb.io.btb_update.bits.br_pc <= UInt<1>("h00") - btb.io.btb_update.bits.isReturn <= UInt<1>("h00") - btb.io.btb_update.bits.isJump <= UInt<1>("h00") - btb.io.btb_update.bits.taken <= UInt<1>("h00") - btb.io.btb_update.bits.target <= UInt<1>("h00") - btb.io.btb_update.bits.pc <= UInt<1>("h00") - btb.io.btb_update.bits.prediction.bits.bht.value <= UInt<1>("h00") - btb.io.btb_update.bits.prediction.bits.bht.history <= UInt<1>("h00") - btb.io.btb_update.bits.prediction.bits.entry <= UInt<1>("h00") - btb.io.btb_update.bits.prediction.bits.target <= UInt<1>("h00") - btb.io.btb_update.bits.prediction.bits.bridx <= UInt<1>("h00") - btb.io.btb_update.bits.prediction.bits.mask <= UInt<1>("h00") - btb.io.btb_update.bits.prediction.bits.taken <= UInt<1>("h00") - btb.io.btb_update.bits.prediction.valid <= UInt<1>("h00") - btb.io.btb_update.valid <= UInt<1>("h00") - btb.io.req.bits.addr <= UInt<1>("h00") - btb.io.req.valid <= UInt<1>("h00") + btb.io is invalid btb.clk <= clk btb.reset <= reset inst icache of ICache - icache.io.mem.grant.bits.data <= UInt<1>("h00") - icache.io.mem.grant.bits.g_type <= UInt<1>("h00") - icache.io.mem.grant.bits.is_builtin_type <= UInt<1>("h00") - icache.io.mem.grant.bits.manager_xact_id <= UInt<1>("h00") - icache.io.mem.grant.bits.client_xact_id <= UInt<1>("h00") - icache.io.mem.grant.bits.addr_beat <= UInt<1>("h00") - icache.io.mem.grant.valid <= UInt<1>("h00") - icache.io.mem.acquire.ready <= UInt<1>("h00") - icache.io.invalidate <= UInt<1>("h00") - icache.io.resp.ready <= UInt<1>("h00") - icache.io.req.bits.kill <= UInt<1>("h00") - icache.io.req.bits.ppn <= UInt<1>("h00") - icache.io.req.bits.idx <= UInt<1>("h00") - icache.io.req.valid <= UInt<1>("h00") + icache.io is invalid icache.clk <= clk icache.reset <= reset inst tlb of TLB - tlb.io.ptw.invalidate <= UInt<1>("h00") - tlb.io.ptw.status.ie <= UInt<1>("h00") - tlb.io.ptw.status.prv <= UInt<1>("h00") - tlb.io.ptw.status.ie1 <= UInt<1>("h00") - tlb.io.ptw.status.prv1 <= UInt<1>("h00") - tlb.io.ptw.status.ie2 <= UInt<1>("h00") - tlb.io.ptw.status.prv2 <= UInt<1>("h00") - tlb.io.ptw.status.ie3 <= UInt<1>("h00") - tlb.io.ptw.status.prv3 <= UInt<1>("h00") - tlb.io.ptw.status.fs <= UInt<1>("h00") - tlb.io.ptw.status.xs <= UInt<1>("h00") - tlb.io.ptw.status.mprv <= UInt<1>("h00") - tlb.io.ptw.status.vm <= UInt<1>("h00") - tlb.io.ptw.status.zero1 <= UInt<1>("h00") - tlb.io.ptw.status.sd_rv32 <= UInt<1>("h00") - tlb.io.ptw.status.zero2 <= UInt<1>("h00") - tlb.io.ptw.status.sd <= UInt<1>("h00") - tlb.io.ptw.resp.bits.pte.v <= UInt<1>("h00") - tlb.io.ptw.resp.bits.pte.typ <= UInt<1>("h00") - tlb.io.ptw.resp.bits.pte.r <= UInt<1>("h00") - tlb.io.ptw.resp.bits.pte.d <= UInt<1>("h00") - tlb.io.ptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") - tlb.io.ptw.resp.bits.pte.ppn <= UInt<1>("h00") - tlb.io.ptw.resp.bits.error <= UInt<1>("h00") - tlb.io.ptw.resp.valid <= UInt<1>("h00") - tlb.io.ptw.req.ready <= UInt<1>("h00") - tlb.io.req.bits.store <= UInt<1>("h00") - tlb.io.req.bits.instruction <= UInt<1>("h00") - tlb.io.req.bits.passthrough <= UInt<1>("h00") - tlb.io.req.bits.vpn <= UInt<1>("h00") - tlb.io.req.bits.asid <= UInt<1>("h00") - tlb.io.req.valid <= UInt<1>("h00") + tlb.io is invalid tlb.clk <= clk tlb.reset <= reset - reg s1_pc_ : UInt<?>, clk, UInt<1>("h00"), s1_pc_ - node T_1368 = not(s1_pc_) - node T_1370 = or(T_1368, UInt<2>("h03")) - node s1_pc = not(T_1370) - reg s1_same_block : UInt<1>, clk, UInt<1>("h00"), s1_same_block - reg s2_valid : UInt<1>, clk, reset, UInt<1>("h01") - reg s2_pc : UInt<?>, clk, reset, UInt<10>("h0200") - reg s2_btb_resp_valid : UInt<1>, clk, reset, UInt<1>("h00") - reg s2_btb_resp_bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk, UInt<1>("h00"), s2_btb_resp_bits - reg s2_xcpt_if : UInt<1>, clk, reset, UInt<1>("h00") + reg s1_pc_ : UInt<?>, clk + node T_1280 = not(s1_pc_) + node T_1282 = or(T_1280, UInt<2>("h03")) + node s1_pc = not(T_1282) + reg s1_same_block : UInt<1>, clk + reg s2_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h01"))) + reg s2_pc : UInt<?>, clk with : (reset => (reset, UInt<10>("h0200"))) + reg s2_btb_resp_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg s2_btb_resp_bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk + reg s2_xcpt_if : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) wire s2_resp_valid : UInt<1> s2_resp_valid <= UInt<1>("h00") wire s2_resp_data : UInt<128> - s2_resp_data <= UInt<1>("h00") - node T_1396 = bit(btb.io.resp.bits.target, 38) - node btbTarget = cat(T_1396, btb.io.resp.bits.target) - node ntpc_0 = addw(s1_pc, UInt<3>("h04")) - node T_1400 = bit(s1_pc, 38) - node T_1401 = bit(ntpc_0, 38) - node T_1402 = and(T_1400, T_1401) - node T_1403 = bits(ntpc_0, 38, 2) - node T_1405 = cat(T_1403, UInt<2>("h00")) - node ntpc = cat(T_1402, T_1405) - node T_1408 = eq(s2_resp_valid, UInt<1>("h00")) - node icmiss = and(s2_valid, T_1408) + s2_resp_data is invalid + node T_1307 = bits(btb.io.resp.bits.target, 38, 38) + node btbTarget = cat(T_1307, btb.io.resp.bits.target) + node T_1310 = add(s1_pc, UInt<3>("h04")) + node ntpc_0 = tail(T_1310, 1) + node T_1312 = bits(s1_pc, 38, 38) + node T_1313 = bits(ntpc_0, 38, 38) + node T_1314 = and(T_1312, T_1313) + node T_1315 = bits(ntpc_0, 38, 2) + node T_1317 = cat(T_1315, UInt<2>("h00")) + node ntpc = cat(T_1314, T_1317) + node T_1320 = eq(s2_resp_valid, UInt<1>("h00")) + node icmiss = and(s2_valid, T_1320) node predicted_npc = mux(btb.io.resp.bits.taken, btbTarget, ntpc) node npc = mux(icmiss, s2_pc, predicted_npc) - node T_1413 = eq(icmiss, UInt<1>("h00")) - node T_1415 = eq(io.cpu.req.valid, UInt<1>("h00")) - node T_1416 = and(T_1413, T_1415) - node T_1418 = eq(btb.io.resp.bits.taken, UInt<1>("h00")) - node T_1419 = and(T_1416, T_1418) - node T_1421 = and(ntpc, UInt<5>("h010")) - node T_1423 = and(s1_pc, UInt<5>("h010")) - node T_1424 = eq(T_1421, T_1423) - node s0_same_block = and(T_1419, T_1424) - node T_1427 = eq(io.cpu.resp.ready, UInt<1>("h00")) - node stall = and(io.cpu.resp.valid, T_1427) - node T_1430 = eq(stall, UInt<1>("h00")) - when T_1430 : - node T_1432 = eq(tlb.io.resp.miss, UInt<1>("h00")) - node T_1433 = and(s0_same_block, T_1432) - s1_same_block <= T_1433 + node T_1325 = eq(icmiss, UInt<1>("h00")) + node T_1327 = eq(io.cpu.req.valid, UInt<1>("h00")) + node T_1328 = and(T_1325, T_1327) + node T_1330 = eq(btb.io.resp.bits.taken, UInt<1>("h00")) + node T_1331 = and(T_1328, T_1330) + node T_1333 = and(ntpc, UInt<5>("h010")) + node T_1335 = and(s1_pc, UInt<5>("h010")) + node T_1336 = eq(T_1333, T_1335) + node s0_same_block = and(T_1331, T_1336) + node T_1339 = eq(io.cpu.resp.ready, UInt<1>("h00")) + node stall = and(io.cpu.resp.valid, T_1339) + node T_1342 = eq(stall, UInt<1>("h00")) + when T_1342 : + node T_1344 = eq(tlb.io.resp.miss, UInt<1>("h00")) + node T_1345 = and(s0_same_block, T_1344) + s1_same_block <= T_1345 s1_pc_ <= npc - node T_1435 = eq(icmiss, UInt<1>("h00")) - s2_valid <= T_1435 - node T_1437 = eq(icmiss, UInt<1>("h00")) - when T_1437 : + node T_1347 = eq(icmiss, UInt<1>("h00")) + s2_valid <= T_1347 + node T_1349 = eq(icmiss, UInt<1>("h00")) + when T_1349 : s2_pc <= s1_pc s2_btb_resp_valid <= btb.io.resp.valid when btb.io.resp.valid : @@ -28966,68 +22051,65 @@ circuit Top : s1_pc_ <= io.cpu.req.bits.pc s2_valid <= UInt<1>("h00") skip - node T_1441 = eq(stall, UInt<1>("h00")) - node T_1443 = eq(icmiss, UInt<1>("h00")) - node T_1444 = and(T_1441, T_1443) - btb.io.req.valid <= T_1444 + node T_1353 = eq(stall, UInt<1>("h00")) + node T_1355 = eq(icmiss, UInt<1>("h00")) + node T_1356 = and(T_1353, T_1355) + btb.io.req.valid <= T_1356 btb.io.req.bits.addr <= s1_pc btb.io.btb_update <- io.cpu.btb_update btb.io.bht_update <- io.cpu.bht_update btb.io.ras_update <- io.cpu.ras_update - node T_1445 = or(io.cpu.invalidate, io.ptw.invalidate) - btb.io.invalidate <= T_1445 + node T_1357 = or(io.cpu.invalidate, io.ptw.invalidate) + btb.io.invalidate <= T_1357 io.ptw <- tlb.io.ptw - node T_1447 = eq(stall, UInt<1>("h00")) - node T_1449 = eq(icmiss, UInt<1>("h00")) - node T_1450 = and(T_1447, T_1449) - tlb.io.req.valid <= T_1450 - node T_1451 = shr(s1_pc, 12) - tlb.io.req.bits.vpn <= T_1451 + node T_1359 = eq(stall, UInt<1>("h00")) + node T_1361 = eq(icmiss, UInt<1>("h00")) + node T_1362 = and(T_1359, T_1361) + tlb.io.req.valid <= T_1362 + node T_1363 = shr(s1_pc, 12) + tlb.io.req.bits.vpn <= T_1363 tlb.io.req.bits.asid <= UInt<1>("h00") tlb.io.req.bits.passthrough <= UInt<1>("h00") tlb.io.req.bits.instruction <= UInt<1>("h01") tlb.io.req.bits.store <= UInt<1>("h00") io.mem <- icache.io.mem - node T_1457 = eq(stall, UInt<1>("h00")) - node T_1459 = eq(s0_same_block, UInt<1>("h00")) - node T_1460 = and(T_1457, T_1459) - icache.io.req.valid <= T_1460 + node T_1369 = eq(stall, UInt<1>("h00")) + node T_1371 = eq(s0_same_block, UInt<1>("h00")) + node T_1372 = and(T_1369, T_1371) + icache.io.req.valid <= T_1372 icache.io.req.bits.idx <= io.cpu.npc icache.io.invalidate <= io.cpu.invalidate icache.io.req.bits.ppn <= tlb.io.resp.ppn - node T_1461 = or(io.cpu.req.valid, tlb.io.resp.miss) - node T_1462 = or(T_1461, tlb.io.resp.xcpt_if) - node T_1463 = or(T_1462, icmiss) - node T_1464 = or(T_1463, io.ptw.invalidate) - icache.io.req.bits.kill <= T_1464 - node T_1465 = or(s2_xcpt_if, s2_resp_valid) - node T_1466 = and(s2_valid, T_1465) - io.cpu.resp.valid <= T_1466 + node T_1373 = or(io.cpu.req.valid, tlb.io.resp.miss) + node T_1374 = or(T_1373, tlb.io.resp.xcpt_if) + node T_1375 = or(T_1374, icmiss) + node T_1376 = or(T_1375, io.ptw.invalidate) + icache.io.req.bits.kill <= T_1376 + node T_1377 = or(s2_xcpt_if, s2_resp_valid) + node T_1378 = and(s2_valid, T_1377) + io.cpu.resp.valid <= T_1378 io.cpu.resp.bits.pc <= s2_pc - node T_1467 = mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) - io.cpu.npc <= T_1467 - inst T_1517 of Queue_92 - T_1517.io.deq.ready <= UInt<1>("h00") - T_1517.io.enq.bits.datablock <= UInt<1>("h00") - T_1517.io.enq.bits.data <= UInt<1>("h00") - T_1517.io.enq.valid <= UInt<1>("h00") - T_1517.clk <= clk - T_1517.reset <= reset - T_1517.io.enq <- icache.io.resp - node T_1523 = eq(stall, UInt<1>("h00")) - node T_1525 = eq(s1_same_block, UInt<1>("h00")) - node T_1526 = and(T_1523, T_1525) - T_1517.io.deq.ready <= T_1526 - s2_resp_valid <= T_1517.io.deq.valid - s2_resp_data <= T_1517.io.deq.bits.datablock - node T_1527 = bits(s2_pc, 3, 2) - node T_1528 = shl(T_1527, 5) - node fetch_data = dshr(s2_resp_data, T_1528) - node T_1530 = bits(fetch_data, 31, 0) - io.cpu.resp.bits.data[0] <= T_1530 - node T_1532 = and(UInt<2>("h03"), s2_btb_resp_bits.mask) - node T_1533 = mux(s2_btb_resp_valid, T_1532, UInt<2>("h03")) - io.cpu.resp.bits.mask <= T_1533 + node T_1379 = mux(io.cpu.req.valid, io.cpu.req.bits.pc, npc) + io.cpu.npc <= T_1379 + inst T_1429 of Queue_92 + T_1429.io is invalid + T_1429.clk <= clk + T_1429.reset <= reset + T_1429.io.enq <- icache.io.resp + node T_1431 = eq(stall, UInt<1>("h00")) + node T_1433 = eq(s1_same_block, UInt<1>("h00")) + node T_1434 = and(T_1431, T_1433) + T_1429.io.deq.ready <= T_1434 + s2_resp_valid <= T_1429.io.deq.valid + s2_resp_data <= T_1429.io.deq.bits.datablock + node T_1435 = bits(s2_pc, 3, 2) + node T_1436 = shl(T_1435, 5) + node fetch_data = dshr(s2_resp_data, T_1436) + node T_1438 = bits(fetch_data, 31, 0) + io.cpu.resp.bits.data[0] <= T_1438 + node T_1440 = and(UInt<2>("h03"), s2_btb_resp_bits.mask) + node T_1441 = mux(s2_btb_resp_valid, T_1440, UInt<2>("h03")) + io.cpu.resp.bits.mask <= T_1441 io.cpu.resp.bits.xcpt_if <= s2_xcpt_if io.cpu.btb_resp.valid <= s2_btb_resp_valid io.cpu.btb_resp.bits <- s2_btb_resp_bits @@ -29037,95 +22119,85 @@ circuit Top : input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, data_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}, flip data_resp : UInt<128>, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}} - io.release.bits.data <= UInt<1>("h00") - io.release.bits.r_type <= UInt<1>("h00") - io.release.bits.voluntary <= UInt<1>("h00") - io.release.bits.client_xact_id <= UInt<1>("h00") - io.release.bits.addr_block <= UInt<1>("h00") - io.release.bits.addr_beat <= UInt<1>("h00") - io.release.valid <= UInt<1>("h00") - io.data_req.bits.addr <= UInt<1>("h00") - io.data_req.bits.way_en <= UInt<1>("h00") - io.data_req.valid <= UInt<1>("h00") - io.meta_read.bits.tag <= UInt<1>("h00") - io.meta_read.bits.idx <= UInt<1>("h00") - io.meta_read.valid <= UInt<1>("h00") - io.req.ready <= UInt<1>("h00") - reg active : UInt<1>, clk, reset, UInt<1>("h00") - reg r1_data_req_fired : UInt<1>, clk, reset, UInt<1>("h00") - reg r2_data_req_fired : UInt<1>, clk, reset, UInt<1>("h00") - reg data_req_cnt : UInt<3>, clk, reset, UInt<3>("h00") + io is invalid + reg active : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg r1_data_req_fired : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg r2_data_req_fired : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg data_req_cnt : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) node T_476 = not(UInt<1>("h01")) node beat_done = eq(T_476, UInt<1>("h00")) node T_479 = and(io.release.ready, io.release.valid) - reg beat_cnt : UInt<2>, clk, reset, UInt<2>("h00") + reg beat_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) when T_479 : node T_483 = eq(beat_cnt, UInt<2>("h03")) node T_485 = and(UInt<1>("h00"), T_483) - node T_488 = addw(beat_cnt, UInt<1>("h01")) - node T_489 = mux(T_485, UInt<1>("h00"), T_488) - beat_cnt <= T_489 + node T_488 = add(beat_cnt, UInt<1>("h01")) + node T_489 = tail(T_488, 1) + node T_490 = mux(T_485, UInt<1>("h00"), T_489) + beat_cnt <= T_490 skip node all_beats_done = and(T_479, T_483) - reg req : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}, clk, UInt<1>("h00"), req + reg req : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}, clk io.release.valid <= UInt<1>("h00") when active : r1_data_req_fired <= UInt<1>("h00") r2_data_req_fired <= r1_data_req_fired - node T_555 = and(io.data_req.ready, io.data_req.valid) - node T_556 = and(io.meta_read.ready, io.meta_read.valid) - node T_557 = and(T_555, T_556) - when T_557 : + node T_556 = and(io.data_req.ready, io.data_req.valid) + node T_557 = and(io.meta_read.ready, io.meta_read.valid) + node T_558 = and(T_556, T_557) + when T_558 : r1_data_req_fired <= UInt<1>("h01") - node T_560 = addw(data_req_cnt, UInt<1>("h01")) - data_req_cnt <= T_560 + node T_561 = add(data_req_cnt, UInt<1>("h01")) + node T_562 = tail(T_561, 1) + data_req_cnt <= T_562 skip when r2_data_req_fired : io.release.valid <= beat_done when beat_done : - node T_562 = eq(io.release.ready, UInt<1>("h00")) - when T_562 : + node T_564 = eq(io.release.ready, UInt<1>("h00")) + when T_564 : r1_data_req_fired <= UInt<1>("h00") r2_data_req_fired <= UInt<1>("h00") - node T_566 = and(UInt<1>("h01"), r1_data_req_fired) - node T_569 = mux(T_566, UInt<2>("h02"), UInt<1>("h01")) - node T_570 = subw(data_req_cnt, T_569) - data_req_cnt <= T_570 + node T_568 = and(UInt<1>("h01"), r1_data_req_fired) + node T_571 = mux(T_568, UInt<2>("h02"), UInt<1>("h01")) + node T_572 = sub(data_req_cnt, T_571) + node T_573 = tail(T_572, 1) + data_req_cnt <= T_573 skip - node T_572 = eq(T_562, UInt<1>("h00")) - when T_572 : + node T_575 = eq(T_564, UInt<1>("h00")) + when T_575 : skip skip - node T_574 = eq(r1_data_req_fired, UInt<1>("h00")) - when T_574 : - node T_576 = lt(data_req_cnt, UInt<3>("h04")) - node T_578 = eq(io.release.ready, UInt<1>("h00")) - node T_579 = or(T_576, T_578) - active <= T_579 + node T_577 = eq(r1_data_req_fired, UInt<1>("h00")) + when T_577 : + node T_579 = lt(data_req_cnt, UInt<3>("h04")) + node T_581 = eq(io.release.ready, UInt<1>("h00")) + node T_582 = or(T_579, T_581) + active <= T_582 skip skip skip - node T_580 = and(io.req.ready, io.req.valid) - when T_580 : + node T_583 = and(io.req.ready, io.req.valid) + when T_583 : active <= UInt<1>("h01") data_req_cnt <= UInt<1>("h00") req <- io.req.bits skip - node T_584 = eq(active, UInt<1>("h00")) - io.req.ready <= T_584 + node T_587 = eq(active, UInt<1>("h00")) + io.req.ready <= T_587 node req_idx = bits(req.addr_block, 5, 0) - node T_587 = lt(data_req_cnt, UInt<3>("h04")) - node fire = and(active, T_587) + node T_590 = lt(data_req_cnt, UInt<3>("h04")) + node fire = and(active, T_590) io.meta_read.valid <= fire io.meta_read.bits.idx <= req_idx - node T_589 = shr(req.addr_block, 6) - io.meta_read.bits.tag <= T_589 + node T_592 = shr(req.addr_block, 6) + io.meta_read.bits.tag <= T_592 io.data_req.valid <= fire io.data_req.bits.way_en <= req.way_en - node T_590 = bits(data_req_cnt, 1, 0) - node T_591 = cat(req_idx, T_590) - node T_592 = shl(T_591, 4) - io.data_req.bits.addr <= T_592 + node T_593 = bits(data_req_cnt, 1, 0) + node T_594 = cat(req_idx, T_593) + node T_595 = shl(T_594, 4) + io.data_req.bits.addr <= T_595 io.release.bits <- req io.release.bits.addr_beat <= beat_cnt io.release.bits.data <= io.data_resp @@ -29135,205 +22207,173 @@ circuit Top : input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<2>}}, rep : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, flip way_en : UInt<4>, flip mshr_rdy : UInt<1>, flip block_state : {state : UInt<2>}} - io.wb_req.bits.way_en <= UInt<1>("h00") - io.wb_req.bits.data <= UInt<1>("h00") - io.wb_req.bits.r_type <= UInt<1>("h00") - io.wb_req.bits.voluntary <= UInt<1>("h00") - io.wb_req.bits.client_xact_id <= UInt<1>("h00") - io.wb_req.bits.addr_block <= UInt<1>("h00") - io.wb_req.bits.addr_beat <= UInt<1>("h00") - io.wb_req.valid <= UInt<1>("h00") - io.meta_write.bits.data.coh.state <= UInt<1>("h00") - io.meta_write.bits.data.tag <= UInt<1>("h00") - io.meta_write.bits.way_en <= UInt<1>("h00") - io.meta_write.bits.idx <= UInt<1>("h00") - io.meta_write.valid <= UInt<1>("h00") - io.meta_read.bits.tag <= UInt<1>("h00") - io.meta_read.bits.idx <= UInt<1>("h00") - io.meta_read.valid <= UInt<1>("h00") - io.rep.bits.data <= UInt<1>("h00") - io.rep.bits.r_type <= UInt<1>("h00") - io.rep.bits.voluntary <= UInt<1>("h00") - io.rep.bits.client_xact_id <= UInt<1>("h00") - io.rep.bits.addr_block <= UInt<1>("h00") - io.rep.bits.addr_beat <= UInt<1>("h00") - io.rep.valid <= UInt<1>("h00") - io.req.ready <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") - reg old_coh : {state : UInt<2>}, clk, UInt<1>("h00"), old_coh - reg way_en : UInt<?>, clk, UInt<1>("h00"), way_en - reg req : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<2>}, clk, UInt<1>("h00"), req + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + reg old_coh : {state : UInt<2>}, clk + reg way_en : UInt<?>, clk + reg req : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<2>}, clk node tag_matches = neq(way_en, UInt<1>("h00")) wire miss_coh : {state : UInt<2>} + miss_coh is invalid miss_coh.state <= UInt<1>("h00") - miss_coh.state <= UInt<1>("h00") - wire reply_coh : {state : UInt<2>} - reply_coh <- miss_coh - when tag_matches : - reply_coh <- old_coh - skip - wire T_973 : UInt<2>[1] - T_973[0] <= UInt<2>("h03") - node T_976 = eq(T_973[0], reply_coh.state) - node T_978 = or(UInt<1>("h00"), T_976) - node T_979 = mux(T_978, UInt<1>("h00"), UInt<2>("h03")) - node T_980 = mux(T_978, UInt<1>("h01"), UInt<3>("h04")) - node T_981 = mux(T_978, UInt<2>("h02"), UInt<3>("h05")) - node T_982 = eq(UInt<5>("h013"), UInt<5>("h010")) - node T_983 = mux(T_982, T_981, UInt<3>("h05")) - node T_984 = eq(UInt<5>("h011"), UInt<5>("h010")) - node T_985 = mux(T_984, T_980, T_983) - node T_986 = eq(UInt<5>("h010"), UInt<5>("h010")) - node T_987 = mux(T_986, T_979, T_985) - wire T_989 : UInt<2>[1] - T_989[0] <= UInt<2>("h03") - node T_992 = eq(T_989[0], reply_coh.state) - node T_994 = or(UInt<1>("h00"), T_992) - node T_995 = mux(T_994, UInt<1>("h00"), UInt<2>("h03")) - node T_996 = mux(T_994, UInt<1>("h01"), UInt<3>("h04")) - node T_997 = mux(T_994, UInt<2>("h02"), UInt<3>("h05")) - node T_998 = eq(UInt<5>("h013"), UInt<5>("h011")) - node T_999 = mux(T_998, T_997, UInt<3>("h05")) - node T_1000 = eq(UInt<5>("h011"), UInt<5>("h011")) - node T_1001 = mux(T_1000, T_996, T_999) - node T_1002 = eq(UInt<5>("h010"), UInt<5>("h011")) - node T_1003 = mux(T_1002, T_995, T_1001) - wire T_1005 : UInt<2>[1] - T_1005[0] <= UInt<2>("h03") - node T_1008 = eq(T_1005[0], reply_coh.state) - node T_1010 = or(UInt<1>("h00"), T_1008) - node T_1011 = mux(T_1010, UInt<1>("h00"), UInt<2>("h03")) - node T_1012 = mux(T_1010, UInt<1>("h01"), UInt<3>("h04")) - node T_1013 = mux(T_1010, UInt<2>("h02"), UInt<3>("h05")) - node T_1014 = eq(UInt<5>("h013"), UInt<5>("h013")) - node T_1015 = mux(T_1014, T_1013, UInt<3>("h05")) - node T_1016 = eq(UInt<5>("h011"), UInt<5>("h013")) - node T_1017 = mux(T_1016, T_1012, T_1015) - node T_1018 = eq(UInt<5>("h010"), UInt<5>("h013")) - node T_1019 = mux(T_1018, T_1011, T_1017) - node T_1020 = eq(UInt<2>("h02"), req.p_type) - node T_1021 = mux(T_1020, T_1019, UInt<2>("h03")) - node T_1022 = eq(UInt<1>("h01"), req.p_type) - node T_1023 = mux(T_1022, T_1003, T_1021) - node T_1024 = eq(UInt<1>("h00"), req.p_type) - node T_1025 = mux(T_1024, T_987, T_1023) + node reply_coh = mux(tag_matches, old_coh, miss_coh) + wire T_947 : UInt<2>[1] + T_947[0] <= UInt<2>("h03") + node T_950 = eq(T_947[0], reply_coh.state) + node T_952 = or(UInt<1>("h00"), T_950) + node T_953 = mux(T_952, UInt<1>("h00"), UInt<2>("h03")) + node T_954 = mux(T_952, UInt<1>("h01"), UInt<3>("h04")) + node T_955 = mux(T_952, UInt<2>("h02"), UInt<3>("h05")) + node T_956 = eq(UInt<5>("h013"), UInt<5>("h010")) + node T_957 = mux(T_956, T_955, UInt<3>("h05")) + node T_958 = eq(UInt<5>("h011"), UInt<5>("h010")) + node T_959 = mux(T_958, T_954, T_957) + node T_960 = eq(UInt<5>("h010"), UInt<5>("h010")) + node T_961 = mux(T_960, T_953, T_959) + wire T_963 : UInt<2>[1] + T_963[0] <= UInt<2>("h03") + node T_966 = eq(T_963[0], reply_coh.state) + node T_968 = or(UInt<1>("h00"), T_966) + node T_969 = mux(T_968, UInt<1>("h00"), UInt<2>("h03")) + node T_970 = mux(T_968, UInt<1>("h01"), UInt<3>("h04")) + node T_971 = mux(T_968, UInt<2>("h02"), UInt<3>("h05")) + node T_972 = eq(UInt<5>("h013"), UInt<5>("h011")) + node T_973 = mux(T_972, T_971, UInt<3>("h05")) + node T_974 = eq(UInt<5>("h011"), UInt<5>("h011")) + node T_975 = mux(T_974, T_970, T_973) + node T_976 = eq(UInt<5>("h010"), UInt<5>("h011")) + node T_977 = mux(T_976, T_969, T_975) + wire T_979 : UInt<2>[1] + T_979[0] <= UInt<2>("h03") + node T_982 = eq(T_979[0], reply_coh.state) + node T_984 = or(UInt<1>("h00"), T_982) + node T_985 = mux(T_984, UInt<1>("h00"), UInt<2>("h03")) + node T_986 = mux(T_984, UInt<1>("h01"), UInt<3>("h04")) + node T_987 = mux(T_984, UInt<2>("h02"), UInt<3>("h05")) + node T_988 = eq(UInt<5>("h013"), UInt<5>("h013")) + node T_989 = mux(T_988, T_987, UInt<3>("h05")) + node T_990 = eq(UInt<5>("h011"), UInt<5>("h013")) + node T_991 = mux(T_990, T_986, T_989) + node T_992 = eq(UInt<5>("h010"), UInt<5>("h013")) + node T_993 = mux(T_992, T_985, T_991) + node T_994 = eq(UInt<2>("h02"), req.p_type) + node T_995 = mux(T_994, T_993, UInt<2>("h03")) + node T_996 = eq(UInt<1>("h01"), req.p_type) + node T_997 = mux(T_996, T_977, T_995) + node T_998 = eq(UInt<1>("h00"), req.p_type) + node T_999 = mux(T_998, T_961, T_997) wire reply : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>} - reply.data <= UInt<1>("h00") - reply.r_type <= UInt<1>("h00") - reply.voluntary <= UInt<1>("h00") - reply.client_xact_id <= UInt<1>("h00") - reply.addr_block <= UInt<1>("h00") - reply.addr_beat <= UInt<1>("h00") - reply.r_type <= T_1025 + reply is invalid + reply.r_type <= T_999 reply.client_xact_id <= UInt<1>("h00") reply.addr_block <= req.addr_block reply.addr_beat <= UInt<1>("h00") reply.data <= UInt<1>("h00") reply.voluntary <= UInt<1>("h00") - node T_1093 = eq(state, UInt<1>("h00")) - io.req.ready <= T_1093 - node T_1094 = eq(state, UInt<3>("h05")) - io.rep.valid <= T_1094 + node T_1061 = eq(state, UInt<1>("h00")) + io.req.ready <= T_1061 + node T_1062 = eq(state, UInt<3>("h05")) + io.rep.valid <= T_1062 io.rep.bits <- reply - node T_1096 = eq(io.rep.valid, UInt<1>("h00")) - wire T_1098 : UInt<2>[3] - T_1098[0] <= UInt<1>("h00") - T_1098[1] <= UInt<1>("h01") - T_1098[2] <= UInt<2>("h02") - node T_1103 = eq(T_1098[0], io.rep.bits.r_type) - node T_1104 = eq(T_1098[1], io.rep.bits.r_type) - node T_1105 = eq(T_1098[2], io.rep.bits.r_type) - node T_1107 = or(UInt<1>("h00"), T_1103) - node T_1108 = or(T_1107, T_1104) - node T_1109 = or(T_1108, T_1105) - node T_1111 = eq(T_1109, UInt<1>("h00")) - node T_1112 = or(T_1096, T_1111) - node T_1114 = eq(reset, UInt<1>("h00")) - when T_1114 : - node T_1116 = eq(T_1112, UInt<1>("h00")) - when T_1116 : - node T_1118 = eq(reset, UInt<1>("h00")) - when T_1118 : + node T_1064 = eq(io.rep.valid, UInt<1>("h00")) + wire T_1066 : UInt<2>[3] + T_1066[0] <= UInt<1>("h00") + T_1066[1] <= UInt<1>("h01") + T_1066[2] <= UInt<2>("h02") + node T_1071 = eq(T_1066[0], io.rep.bits.r_type) + node T_1072 = eq(T_1066[1], io.rep.bits.r_type) + node T_1073 = eq(T_1066[2], io.rep.bits.r_type) + node T_1075 = or(UInt<1>("h00"), T_1071) + node T_1076 = or(T_1075, T_1072) + node T_1077 = or(T_1076, T_1073) + node T_1079 = eq(T_1077, UInt<1>("h00")) + node T_1080 = or(T_1064, T_1079) + node T_1082 = eq(reset, UInt<1>("h00")) + when T_1082 : + node T_1084 = eq(T_1080, UInt<1>("h00")) + when T_1084 : + node T_1086 = eq(reset, UInt<1>("h00")) + when T_1086 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): ProbeUnit should not send releases with data") skip stop(clk, UInt<1>(1), 1) skip skip - node T_1119 = eq(state, UInt<1>("h01")) - io.meta_read.valid <= T_1119 + node T_1087 = eq(state, UInt<1>("h01")) + io.meta_read.valid <= T_1087 io.meta_read.bits.idx <= req.addr_block - node T_1120 = shr(req.addr_block, 6) - io.meta_read.bits.tag <= T_1120 - node T_1121 = eq(state, UInt<4>("h08")) - io.meta_write.valid <= T_1121 + node T_1088 = shr(req.addr_block, 6) + io.meta_read.bits.tag <= T_1088 + node T_1089 = eq(state, UInt<4>("h08")) + io.meta_write.valid <= T_1089 io.meta_write.bits.way_en <= way_en io.meta_write.bits.idx <= req.addr_block - node T_1122 = shr(req.addr_block, 6) - io.meta_write.bits.data.tag <= T_1122 - node T_1123 = eq(UInt<2>("h02"), req.p_type) - node T_1124 = mux(T_1123, old_coh.state, old_coh.state) - node T_1125 = eq(UInt<1>("h01"), req.p_type) - node T_1126 = mux(T_1125, UInt<1>("h01"), T_1124) - node T_1127 = eq(UInt<1>("h00"), req.p_type) - node T_1128 = mux(T_1127, UInt<1>("h00"), T_1126) - wire T_1154 : {state : UInt<2>} - T_1154.state <= UInt<1>("h00") - T_1154.state <= T_1128 - io.meta_write.bits.data.coh <- T_1154 - node T_1180 = eq(state, UInt<3>("h06")) - io.wb_req.valid <= T_1180 + node T_1090 = shr(req.addr_block, 6) + io.meta_write.bits.data.tag <= T_1090 + node T_1091 = eq(UInt<2>("h02"), req.p_type) + node T_1092 = mux(T_1091, old_coh.state, old_coh.state) + node T_1093 = eq(UInt<1>("h01"), req.p_type) + node T_1094 = mux(T_1093, UInt<1>("h01"), T_1092) + node T_1095 = eq(UInt<1>("h00"), req.p_type) + node T_1096 = mux(T_1095, UInt<1>("h00"), T_1094) + wire T_1122 : {state : UInt<2>} + T_1122 is invalid + T_1122.state <= T_1096 + io.meta_write.bits.data.coh <- T_1122 + node T_1147 = eq(state, UInt<3>("h06")) + io.wb_req.valid <= T_1147 io.wb_req.bits <- reply io.wb_req.bits.way_en <= way_en - node T_1181 = and(io.req.ready, io.req.valid) - when T_1181 : + node T_1148 = and(io.req.ready, io.req.valid) + when T_1148 : state <= UInt<1>("h01") req <- io.req.bits skip - node T_1182 = and(io.meta_read.ready, io.meta_read.valid) - when T_1182 : + node T_1149 = and(io.meta_read.ready, io.meta_read.valid) + when T_1149 : state <= UInt<2>("h02") skip - node T_1183 = eq(state, UInt<2>("h02")) - when T_1183 : + node T_1150 = eq(state, UInt<2>("h02")) + when T_1150 : state <= UInt<2>("h03") skip - node T_1184 = eq(state, UInt<2>("h03")) - when T_1184 : + node T_1151 = eq(state, UInt<2>("h03")) + when T_1151 : state <= UInt<3>("h04") old_coh <- io.block_state way_en <= io.way_en - node T_1186 = eq(io.mshr_rdy, UInt<1>("h00")) - when T_1186 : + node T_1153 = eq(io.mshr_rdy, UInt<1>("h00")) + when T_1153 : state <= UInt<1>("h01") skip skip - node T_1187 = eq(state, UInt<3>("h04")) - when T_1187 : - wire T_1189 : UInt<2>[1] - T_1189[0] <= UInt<2>("h03") - node T_1192 = eq(T_1189[0], old_coh.state) - node T_1194 = or(UInt<1>("h00"), T_1192) - node T_1195 = and(tag_matches, T_1194) - node T_1196 = mux(T_1195, UInt<3>("h06"), UInt<3>("h05")) - state <= T_1196 - skip - node T_1197 = eq(state, UInt<3>("h05")) - node T_1198 = and(T_1197, io.rep.ready) - when T_1198 : - node T_1199 = mux(tag_matches, UInt<4>("h08"), UInt<1>("h00")) - state <= T_1199 - skip - node T_1200 = and(io.wb_req.ready, io.wb_req.valid) - when T_1200 : + node T_1154 = eq(state, UInt<3>("h04")) + when T_1154 : + wire T_1156 : UInt<2>[1] + T_1156[0] <= UInt<2>("h03") + node T_1159 = eq(T_1156[0], old_coh.state) + node T_1161 = or(UInt<1>("h00"), T_1159) + node T_1162 = and(tag_matches, T_1161) + node T_1163 = mux(T_1162, UInt<3>("h06"), UInt<3>("h05")) + state <= T_1163 + skip + node T_1164 = eq(state, UInt<3>("h05")) + node T_1165 = and(T_1164, io.rep.ready) + when T_1165 : + node T_1166 = mux(tag_matches, UInt<4>("h08"), UInt<1>("h00")) + state <= T_1166 + skip + node T_1167 = and(io.wb_req.ready, io.wb_req.valid) + when T_1167 : state <= UInt<3>("h07") skip - node T_1201 = eq(state, UInt<3>("h07")) - node T_1202 = and(T_1201, io.wb_req.ready) - when T_1202 : + node T_1168 = eq(state, UInt<3>("h07")) + node T_1169 = and(T_1168, io.wb_req.ready) + when T_1169 : state <= UInt<4>("h08") skip - node T_1203 = and(io.meta_write.ready, io.meta_write.valid) - when T_1203 : + node T_1170 = and(io.meta_write.ready, io.meta_write.valid) + when T_1170 : state <= UInt<1>("h00") skip @@ -29342,109 +22382,87 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, chosen : UInt<1>} - io.chosen <= UInt<1>("h00") - io.out.bits.tag <= UInt<1>("h00") - io.out.bits.idx <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") + io is invalid wire T_108 : UInt<1> - T_108 <= UInt<1>("h00") + T_108 is invalid io.out.valid <= io.in[T_108].valid io.out.bits <- io.in[T_108].bits io.chosen <= T_108 io.in[T_108].ready <= UInt<1>("h00") - node T_140 = or(UInt<1>("h00"), io.in[0].valid) - node T_142 = eq(T_140, UInt<1>("h00")) - node T_144 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_145 = mux(UInt<1>("h00"), T_144, UInt<1>("h01")) - node T_146 = and(T_145, io.out.ready) - io.in[0].ready <= T_146 - node T_148 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_149 = mux(UInt<1>("h00"), T_148, T_142) - node T_150 = and(T_149, io.out.ready) - io.in[1].ready <= T_150 - node T_153 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_154 = mux(UInt<1>("h00"), UInt<1>("h01"), T_153) - T_108 <= T_154 + node T_139 = or(UInt<1>("h00"), io.in[0].valid) + node T_141 = eq(T_139, UInt<1>("h00")) + node T_143 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_144 = mux(UInt<1>("h00"), T_143, UInt<1>("h01")) + node T_145 = and(T_144, io.out.ready) + io.in[0].ready <= T_145 + node T_147 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_148 = mux(UInt<1>("h00"), T_147, T_141) + node T_149 = and(T_148, io.out.ready) + io.in[1].ready <= T_149 + node T_152 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_153 = mux(UInt<1>("h00"), UInt<1>("h01"), T_152) + T_108 <= T_153 module Arbiter_94 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, chosen : UInt<1>} - io.chosen <= UInt<1>("h00") - io.out.bits.data.coh.state <= UInt<1>("h00") - io.out.bits.data.tag <= UInt<1>("h00") - io.out.bits.way_en <= UInt<1>("h00") - io.out.bits.idx <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") + io is invalid wire T_1714 : UInt<1> - T_1714 <= UInt<1>("h00") + T_1714 is invalid io.out.valid <= io.in[T_1714].valid io.out.bits <- io.in[T_1714].bits io.chosen <= T_1714 io.in[T_1714].ready <= UInt<1>("h00") - node T_2184 = or(UInt<1>("h00"), io.in[0].valid) - node T_2186 = eq(T_2184, UInt<1>("h00")) - node T_2188 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2189 = mux(UInt<1>("h00"), T_2188, UInt<1>("h01")) - node T_2190 = and(T_2189, io.out.ready) - io.in[0].ready <= T_2190 - node T_2192 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_2193 = mux(UInt<1>("h00"), T_2192, T_2186) - node T_2194 = and(T_2193, io.out.ready) - io.in[1].ready <= T_2194 - node T_2197 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_2198 = mux(UInt<1>("h00"), UInt<1>("h01"), T_2197) - T_1714 <= T_2198 + node T_2183 = or(UInt<1>("h00"), io.in[0].valid) + node T_2185 = eq(T_2183, UInt<1>("h00")) + node T_2187 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_2188 = mux(UInt<1>("h00"), T_2187, UInt<1>("h01")) + node T_2189 = and(T_2188, io.out.ready) + io.in[0].ready <= T_2189 + node T_2191 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_2192 = mux(UInt<1>("h00"), T_2191, T_2185) + node T_2193 = and(T_2192, io.out.ready) + io.in[1].ready <= T_2193 + node T_2196 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_2197 = mux(UInt<1>("h00"), UInt<1>("h01"), T_2196) + T_1714 <= T_2197 module LockingArbiter : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}[3], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, chosen : UInt<2>} - io.chosen <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.bits.union <= UInt<1>("h00") - io.out.bits.a_type <= UInt<1>("h00") - io.out.bits.is_builtin_type <= UInt<1>("h00") - io.out.bits.addr_beat <= UInt<1>("h00") - io.out.bits.client_xact_id <= UInt<1>("h00") - io.out.bits.addr_block <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") - io.in[2].ready <= UInt<1>("h00") - reg T_852 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_854 : UInt<?>, clk, reset, UInt<2>("h02") + io is invalid + reg T_852 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_854 : UInt<?>, clk with : (reset => (reset, UInt<2>("h02"))) wire T_856 : UInt<2> - T_856 <= UInt<1>("h00") + T_856 is invalid io.out.valid <= io.in[T_856].valid io.out.bits <- io.in[T_856].bits io.chosen <= T_856 io.in[T_856].ready <= UInt<1>("h00") - node T_1056 = or(UInt<1>("h00"), io.in[0].valid) - node T_1058 = eq(T_1056, UInt<1>("h00")) - node T_1060 = or(UInt<1>("h00"), io.in[0].valid) - node T_1061 = or(T_1060, io.in[1].valid) - node T_1063 = eq(T_1061, UInt<1>("h00")) - node T_1065 = eq(T_854, UInt<1>("h00")) - node T_1066 = mux(T_852, T_1065, UInt<1>("h01")) - node T_1067 = and(T_1066, io.out.ready) - io.in[0].ready <= T_1067 - node T_1069 = eq(T_854, UInt<1>("h01")) - node T_1070 = mux(T_852, T_1069, T_1058) - node T_1071 = and(T_1070, io.out.ready) - io.in[1].ready <= T_1071 - node T_1073 = eq(T_854, UInt<2>("h02")) - node T_1074 = mux(T_852, T_1073, T_1063) - node T_1075 = and(T_1074, io.out.ready) - io.in[2].ready <= T_1075 - reg T_1077 : UInt<2>, clk, reset, UInt<2>("h00") - node T_1079 = addw(T_1077, UInt<1>("h01")) + node T_1055 = or(UInt<1>("h00"), io.in[0].valid) + node T_1057 = eq(T_1055, UInt<1>("h00")) + node T_1059 = or(UInt<1>("h00"), io.in[0].valid) + node T_1060 = or(T_1059, io.in[1].valid) + node T_1062 = eq(T_1060, UInt<1>("h00")) + node T_1064 = eq(T_854, UInt<1>("h00")) + node T_1065 = mux(T_852, T_1064, UInt<1>("h01")) + node T_1066 = and(T_1065, io.out.ready) + io.in[0].ready <= T_1066 + node T_1068 = eq(T_854, UInt<1>("h01")) + node T_1069 = mux(T_852, T_1068, T_1057) + node T_1070 = and(T_1069, io.out.ready) + io.in[1].ready <= T_1070 + node T_1072 = eq(T_854, UInt<2>("h02")) + node T_1073 = mux(T_852, T_1072, T_1062) + node T_1074 = and(T_1073, io.out.ready) + io.in[2].ready <= T_1074 + reg T_1076 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + node T_1078 = add(T_1076, UInt<1>("h01")) + node T_1079 = tail(T_1078, 1) node T_1080 = and(io.out.ready, io.out.valid) when T_1080 : node T_1082 = and(UInt<1>("h01"), io.out.bits.is_builtin_type) @@ -29454,7 +22472,7 @@ circuit Top : node T_1090 = or(UInt<1>("h00"), T_1088) node T_1091 = and(T_1082, T_1090) when T_1091 : - T_1077 <= T_1079 + T_1076 <= T_1079 node T_1093 = eq(T_852, UInt<1>("h00")) when T_1093 : T_852 <= UInt<1>("h01") @@ -29485,122 +22503,89 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, chosen : UInt<1>} - io.chosen <= UInt<1>("h00") - io.out.bits.way_en <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.bits.r_type <= UInt<1>("h00") - io.out.bits.voluntary <= UInt<1>("h00") - io.out.bits.client_xact_id <= UInt<1>("h00") - io.out.bits.addr_block <= UInt<1>("h00") - io.out.bits.addr_beat <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") + io is invalid wire T_724 : UInt<1> - T_724 <= UInt<1>("h00") + T_724 is invalid io.out.valid <= io.in[T_724].valid io.out.bits <- io.in[T_724].bits io.chosen <= T_724 io.in[T_724].ready <= UInt<1>("h00") - node T_924 = or(UInt<1>("h00"), io.in[0].valid) - node T_926 = eq(T_924, UInt<1>("h00")) - node T_928 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_929 = mux(UInt<1>("h00"), T_928, UInt<1>("h01")) - node T_930 = and(T_929, io.out.ready) - io.in[0].ready <= T_930 - node T_932 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_933 = mux(UInt<1>("h00"), T_932, T_926) - node T_934 = and(T_933, io.out.ready) - io.in[1].ready <= T_934 - node T_937 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_938 = mux(UInt<1>("h00"), UInt<1>("h01"), T_937) - T_724 <= T_938 + node T_923 = or(UInt<1>("h00"), io.in[0].valid) + node T_925 = eq(T_923, UInt<1>("h00")) + node T_927 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_928 = mux(UInt<1>("h00"), T_927, UInt<1>("h01")) + node T_929 = and(T_928, io.out.ready) + io.in[0].ready <= T_929 + node T_931 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_932 = mux(UInt<1>("h00"), T_931, T_925) + node T_933 = and(T_932, io.out.ready) + io.in[1].ready <= T_933 + node T_936 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_937 = mux(UInt<1>("h00"), UInt<1>("h01"), T_936) + T_724 <= T_937 module Arbiter_96 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, chosen : UInt<1>} - io.chosen <= UInt<1>("h00") - io.out.bits.sdq_id <= UInt<1>("h00") - io.out.bits.phys <= UInt<1>("h00") - io.out.bits.kill <= UInt<1>("h00") - io.out.bits.typ <= UInt<1>("h00") - io.out.bits.cmd <= UInt<1>("h00") - io.out.bits.tag <= UInt<1>("h00") - io.out.bits.addr <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") + io is invalid wire T_1230 : UInt<1> - T_1230 <= UInt<1>("h00") + T_1230 is invalid io.out.valid <= io.in[T_1230].valid io.out.bits <- io.in[T_1230].bits io.chosen <= T_1230 io.in[T_1230].ready <= UInt<1>("h00") - node T_1568 = or(UInt<1>("h00"), io.in[0].valid) - node T_1570 = eq(T_1568, UInt<1>("h00")) - node T_1572 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_1573 = mux(UInt<1>("h00"), T_1572, UInt<1>("h01")) - node T_1574 = and(T_1573, io.out.ready) - io.in[0].ready <= T_1574 - node T_1576 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_1577 = mux(UInt<1>("h00"), T_1576, T_1570) - node T_1578 = and(T_1577, io.out.ready) - io.in[1].ready <= T_1578 - node T_1581 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_1582 = mux(UInt<1>("h00"), UInt<1>("h01"), T_1581) - T_1230 <= T_1582 + node T_1567 = or(UInt<1>("h00"), io.in[0].valid) + node T_1569 = eq(T_1567, UInt<1>("h00")) + node T_1571 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_1572 = mux(UInt<1>("h00"), T_1571, UInt<1>("h01")) + node T_1573 = and(T_1572, io.out.ready) + io.in[0].ready <= T_1573 + node T_1575 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_1576 = mux(UInt<1>("h00"), T_1575, T_1569) + node T_1577 = and(T_1576, io.out.ready) + io.in[1].ready <= T_1577 + node T_1580 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_1581 = mux(UInt<1>("h00"), UInt<1>("h01"), T_1580) + T_1230 <= T_1581 module Arbiter_97 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, chosen : UInt<1>} - io.chosen <= UInt<1>("h00") - io.out.bits <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") + io is invalid wire T_64 : UInt<1> - T_64 <= UInt<1>("h00") + T_64 is invalid io.out.valid <= io.in[T_64].valid io.out.bits <= io.in[T_64].bits io.chosen <= T_64 io.in[T_64].ready <= UInt<1>("h00") - node T_84 = or(UInt<1>("h00"), io.in[0].valid) - node T_86 = eq(T_84, UInt<1>("h00")) - node T_88 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_89 = mux(UInt<1>("h00"), T_88, UInt<1>("h01")) - node T_90 = and(T_89, io.out.ready) - io.in[0].ready <= T_90 - node T_92 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_93 = mux(UInt<1>("h00"), T_92, T_86) - node T_94 = and(T_93, io.out.ready) - io.in[1].ready <= T_94 - node T_97 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_98 = mux(UInt<1>("h00"), UInt<1>("h01"), T_97) - T_64 <= T_98 + node T_83 = or(UInt<1>("h00"), io.in[0].valid) + node T_85 = eq(T_83, UInt<1>("h00")) + node T_87 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_88 = mux(UInt<1>("h00"), T_87, UInt<1>("h01")) + node T_89 = and(T_88, io.out.ready) + io.in[0].ready <= T_89 + node T_91 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_92 = mux(UInt<1>("h00"), T_91, T_85) + node T_93 = and(T_92, io.out.ready) + io.in[1].ready <= T_93 + node T_96 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_97 = mux(UInt<1>("h00"), UInt<1>("h01"), T_96) + T_64 <= T_97 module Queue_98 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, count : UInt<5>} - io.count <= UInt<1>("h00") - io.deq.bits.sdq_id <= UInt<1>("h00") - io.deq.bits.phys <= UInt<1>("h00") - io.deq.bits.kill <= UInt<1>("h00") - io.deq.bits.typ <= UInt<1>("h00") - io.deq.bits.cmd <= UInt<1>("h00") - io.deq.bits.tag <= UInt<1>("h00") - io.deq.bits.addr <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}[16] - reg T_503 : UInt<4>, clk, reset, UInt<4>("h00") - reg T_505 : UInt<4>, clk, reset, UInt<4>("h00") - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg T_503 : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) + reg T_505 : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(T_503, T_505) node T_510 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_510) @@ -29618,238 +22603,192 @@ circuit Top : T_524 <- io.enq.bits node T_579 = eq(T_503, UInt<4>("h0f")) node T_581 = and(UInt<1>("h00"), T_579) - node T_584 = addw(T_503, UInt<1>("h01")) - node T_585 = mux(T_581, UInt<1>("h00"), T_584) - T_503 <= T_585 + node T_584 = add(T_503, UInt<1>("h01")) + node T_585 = tail(T_584, 1) + node T_586 = mux(T_581, UInt<1>("h00"), T_585) + T_503 <= T_586 skip when do_deq : - node T_587 = eq(T_505, UInt<4>("h0f")) - node T_589 = and(UInt<1>("h00"), T_587) - node T_592 = addw(T_505, UInt<1>("h01")) - node T_593 = mux(T_589, UInt<1>("h00"), T_592) - T_505 <= T_593 - skip - node T_594 = neq(do_enq, do_deq) - when T_594 : + node T_588 = eq(T_505, UInt<4>("h0f")) + node T_590 = and(UInt<1>("h00"), T_588) + node T_593 = add(T_505, UInt<1>("h01")) + node T_594 = tail(T_593, 1) + node T_595 = mux(T_590, UInt<1>("h00"), T_594) + T_505 <= T_595 + skip + node T_596 = neq(do_enq, do_deq) + when T_596 : maybe_full <= do_enq skip - node T_596 = eq(empty, UInt<1>("h00")) - node T_598 = and(UInt<1>("h00"), io.enq.valid) - node T_599 = or(T_596, T_598) - io.deq.valid <= T_599 - node T_601 = eq(full, UInt<1>("h00")) - node T_603 = and(UInt<1>("h00"), io.deq.ready) - node T_604 = or(T_601, T_603) - io.enq.ready <= T_604 - infer mport T_605 = ram[T_505], clk - wire T_713 : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>} - T_713 <- T_605 - when maybe_flow : - T_713 <- io.enq.bits - skip - io.deq.bits <- T_713 - node ptr_diff = subw(T_503, T_505) - node T_768 = and(maybe_full, ptr_match) - node T_769 = cat(T_768, ptr_diff) - io.count <= T_769 + node T_598 = eq(empty, UInt<1>("h00")) + node T_600 = and(UInt<1>("h00"), io.enq.valid) + node T_601 = or(T_598, T_600) + io.deq.valid <= T_601 + node T_603 = eq(full, UInt<1>("h00")) + node T_605 = and(UInt<1>("h00"), io.deq.ready) + node T_606 = or(T_603, T_605) + io.enq.ready <= T_606 + infer mport T_607 = ram[T_505], clk + node T_661 = mux(maybe_flow, io.enq.bits, T_607) + io.deq.bits <- T_661 + node T_715 = sub(T_503, T_505) + node ptr_diff = tail(T_715, 1) + node T_717 = and(maybe_full, ptr_match) + node T_718 = cat(T_717, ptr_diff) + io.count <= T_718 module MSHR : input clk : Clock input reset : UInt<1> output io : {flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, idx_match : UInt<1>, tag : UInt<20>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>} - io.probe_rdy <= UInt<1>("h00") - io.wb_req.bits.way_en <= UInt<1>("h00") - io.wb_req.bits.data <= UInt<1>("h00") - io.wb_req.bits.r_type <= UInt<1>("h00") - io.wb_req.bits.voluntary <= UInt<1>("h00") - io.wb_req.bits.client_xact_id <= UInt<1>("h00") - io.wb_req.bits.addr_block <= UInt<1>("h00") - io.wb_req.bits.addr_beat <= UInt<1>("h00") - io.wb_req.valid <= UInt<1>("h00") - io.replay.bits.sdq_id <= UInt<1>("h00") - io.replay.bits.phys <= UInt<1>("h00") - io.replay.bits.kill <= UInt<1>("h00") - io.replay.bits.typ <= UInt<1>("h00") - io.replay.bits.cmd <= UInt<1>("h00") - io.replay.bits.tag <= UInt<1>("h00") - io.replay.bits.addr <= UInt<1>("h00") - io.replay.valid <= UInt<1>("h00") - io.meta_write.bits.data.coh.state <= UInt<1>("h00") - io.meta_write.bits.data.tag <= UInt<1>("h00") - io.meta_write.bits.way_en <= UInt<1>("h00") - io.meta_write.bits.idx <= UInt<1>("h00") - io.meta_write.valid <= UInt<1>("h00") - io.meta_read.bits.tag <= UInt<1>("h00") - io.meta_read.bits.idx <= UInt<1>("h00") - io.meta_read.valid <= UInt<1>("h00") - io.refill.addr <= UInt<1>("h00") - io.refill.way_en <= UInt<1>("h00") - io.mem_req.bits.data <= UInt<1>("h00") - io.mem_req.bits.union <= UInt<1>("h00") - io.mem_req.bits.a_type <= UInt<1>("h00") - io.mem_req.bits.is_builtin_type <= UInt<1>("h00") - io.mem_req.bits.addr_beat <= UInt<1>("h00") - io.mem_req.bits.client_xact_id <= UInt<1>("h00") - io.mem_req.bits.addr_block <= UInt<1>("h00") - io.mem_req.valid <= UInt<1>("h00") - io.tag <= UInt<1>("h00") - io.idx_match <= UInt<1>("h00") - io.req_sec_rdy <= UInt<1>("h00") - io.req_pri_rdy <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) wire T_1277 : {state : UInt<2>} + T_1277 is invalid T_1277.state <= UInt<1>("h00") - T_1277.state <= UInt<1>("h00") - reg new_coh_state : {state : UInt<2>}, clk, reset, T_1277 - reg req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, clk, UInt<1>("h00"), req + reg new_coh_state : {state : UInt<2>}, clk with : (reset => (reset, T_1277)) + reg req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, clk node req_idx = bits(req.addr, 11, 6) - node T_1587 = bits(io.req_bits.addr, 11, 6) - node idx_match = eq(req_idx, T_1587) - node T_1589 = eq(io.req_bits.cmd, UInt<5>("h01")) - node T_1590 = eq(io.req_bits.cmd, UInt<5>("h07")) - node T_1591 = or(T_1589, T_1590) - node T_1592 = bit(io.req_bits.cmd, 3) - node T_1593 = eq(io.req_bits.cmd, UInt<5>("h04")) - node T_1594 = or(T_1592, T_1593) - node T_1595 = or(T_1591, T_1594) - node T_1596 = eq(io.req_bits.cmd, UInt<5>("h03")) - node T_1597 = or(T_1595, T_1596) - node T_1598 = eq(io.req_bits.cmd, UInt<5>("h06")) - node T_1599 = or(T_1597, T_1598) - node T_1600 = eq(req.cmd, UInt<5>("h01")) - node T_1601 = eq(req.cmd, UInt<5>("h07")) - node T_1602 = or(T_1600, T_1601) - node T_1603 = bit(req.cmd, 3) - node T_1604 = eq(req.cmd, UInt<5>("h04")) - node T_1605 = or(T_1603, T_1604) - node T_1606 = or(T_1602, T_1605) - node T_1607 = eq(req.cmd, UInt<5>("h03")) - node T_1608 = or(T_1606, T_1607) - node T_1609 = eq(req.cmd, UInt<5>("h06")) - node T_1610 = or(T_1608, T_1609) - node T_1612 = eq(T_1610, UInt<1>("h00")) - node cmd_requires_second_acquire = and(T_1599, T_1612) + node T_1586 = bits(io.req_bits.addr, 11, 6) + node idx_match = eq(req_idx, T_1586) + node T_1588 = eq(io.req_bits.cmd, UInt<5>("h01")) + node T_1589 = eq(io.req_bits.cmd, UInt<5>("h07")) + node T_1590 = or(T_1588, T_1589) + node T_1591 = bits(io.req_bits.cmd, 3, 3) + node T_1592 = eq(io.req_bits.cmd, UInt<5>("h04")) + node T_1593 = or(T_1591, T_1592) + node T_1594 = or(T_1590, T_1593) + node T_1595 = eq(io.req_bits.cmd, UInt<5>("h03")) + node T_1596 = or(T_1594, T_1595) + node T_1597 = eq(io.req_bits.cmd, UInt<5>("h06")) + node T_1598 = or(T_1596, T_1597) + node T_1599 = eq(req.cmd, UInt<5>("h01")) + node T_1600 = eq(req.cmd, UInt<5>("h07")) + node T_1601 = or(T_1599, T_1600) + node T_1602 = bits(req.cmd, 3, 3) + node T_1603 = eq(req.cmd, UInt<5>("h04")) + node T_1604 = or(T_1602, T_1603) + node T_1605 = or(T_1601, T_1604) + node T_1606 = eq(req.cmd, UInt<5>("h03")) + node T_1607 = or(T_1605, T_1606) + node T_1608 = eq(req.cmd, UInt<5>("h06")) + node T_1609 = or(T_1607, T_1608) + node T_1611 = eq(T_1609, UInt<1>("h00")) + node cmd_requires_second_acquire = and(T_1598, T_1611) wire states_before_refill : UInt<2>[3] states_before_refill[0] <= UInt<1>("h01") states_before_refill[1] <= UInt<2>("h02") states_before_refill[2] <= UInt<2>("h03") - node T_1620 = eq(states_before_refill[0], state) - node T_1621 = eq(states_before_refill[1], state) - node T_1622 = eq(states_before_refill[2], state) - node T_1624 = or(UInt<1>("h00"), T_1620) + node T_1619 = eq(states_before_refill[0], state) + node T_1620 = eq(states_before_refill[1], state) + node T_1621 = eq(states_before_refill[2], state) + node T_1623 = or(UInt<1>("h00"), T_1619) + node T_1624 = or(T_1623, T_1620) node T_1625 = or(T_1624, T_1621) - node T_1626 = or(T_1625, T_1622) - wire T_1628 : UInt<3>[2] - T_1628[0] <= UInt<3>("h04") - T_1628[1] <= UInt<3>("h05") - node T_1632 = eq(T_1628[0], state) - node T_1633 = eq(T_1628[1], state) - node T_1635 = or(UInt<1>("h00"), T_1632) - node T_1636 = or(T_1635, T_1633) - node T_1638 = eq(cmd_requires_second_acquire, UInt<1>("h00")) - node T_1639 = and(T_1636, T_1638) - node T_1640 = or(T_1626, T_1639) - node sec_rdy = and(idx_match, T_1640) - wire T_1645 : UInt<3>[1] - T_1645[0] <= UInt<3>("h05") - node T_1648 = eq(T_1645[0], io.mem_grant.bits.g_type) - node T_1650 = or(UInt<1>("h00"), T_1648) - wire T_1652 : UInt<1>[2] - T_1652[0] <= UInt<1>("h00") - T_1652[1] <= UInt<1>("h01") - node T_1656 = eq(T_1652[0], io.mem_grant.bits.g_type) - node T_1657 = eq(T_1652[1], io.mem_grant.bits.g_type) - node T_1659 = or(UInt<1>("h00"), T_1656) - node T_1660 = or(T_1659, T_1657) - node T_1661 = mux(io.mem_grant.bits.is_builtin_type, T_1650, T_1660) - node gnt_multi_data = and(UInt<1>("h01"), T_1661) - node T_1663 = and(io.mem_grant.valid, gnt_multi_data) - reg refill_cnt : UInt<2>, clk, reset, UInt<2>("h00") - when T_1663 : - node T_1667 = eq(refill_cnt, UInt<2>("h03")) - node T_1669 = and(UInt<1>("h00"), T_1667) - node T_1672 = addw(refill_cnt, UInt<1>("h01")) - node T_1673 = mux(T_1669, UInt<1>("h00"), T_1672) + wire T_1627 : UInt<3>[2] + T_1627[0] <= UInt<3>("h04") + T_1627[1] <= UInt<3>("h05") + node T_1631 = eq(T_1627[0], state) + node T_1632 = eq(T_1627[1], state) + node T_1634 = or(UInt<1>("h00"), T_1631) + node T_1635 = or(T_1634, T_1632) + node T_1637 = eq(cmd_requires_second_acquire, UInt<1>("h00")) + node T_1638 = and(T_1635, T_1637) + node T_1639 = or(T_1625, T_1638) + node sec_rdy = and(idx_match, T_1639) + wire T_1644 : UInt<3>[1] + T_1644[0] <= UInt<3>("h05") + node T_1647 = eq(T_1644[0], io.mem_grant.bits.g_type) + node T_1649 = or(UInt<1>("h00"), T_1647) + wire T_1651 : UInt<1>[2] + T_1651[0] <= UInt<1>("h00") + T_1651[1] <= UInt<1>("h01") + node T_1655 = eq(T_1651[0], io.mem_grant.bits.g_type) + node T_1656 = eq(T_1651[1], io.mem_grant.bits.g_type) + node T_1658 = or(UInt<1>("h00"), T_1655) + node T_1659 = or(T_1658, T_1656) + node T_1660 = mux(io.mem_grant.bits.is_builtin_type, T_1649, T_1659) + node gnt_multi_data = and(UInt<1>("h01"), T_1660) + node T_1662 = and(io.mem_grant.valid, gnt_multi_data) + reg refill_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_1662 : + node T_1666 = eq(refill_cnt, UInt<2>("h03")) + node T_1668 = and(UInt<1>("h00"), T_1666) + node T_1671 = add(refill_cnt, UInt<1>("h01")) + node T_1672 = tail(T_1671, 1) + node T_1673 = mux(T_1668, UInt<1>("h00"), T_1672) refill_cnt <= T_1673 skip - node refill_count_done = and(T_1663, T_1667) + node refill_count_done = and(T_1662, T_1666) node T_1676 = eq(gnt_multi_data, UInt<1>("h00")) node T_1677 = or(T_1676, refill_count_done) node refill_done = and(io.mem_grant.valid, T_1677) inst rpq of Queue_98 - rpq.io.deq.ready <= UInt<1>("h00") - rpq.io.enq.bits.sdq_id <= UInt<1>("h00") - rpq.io.enq.bits.phys <= UInt<1>("h00") - rpq.io.enq.bits.kill <= UInt<1>("h00") - rpq.io.enq.bits.typ <= UInt<1>("h00") - rpq.io.enq.bits.cmd <= UInt<1>("h00") - rpq.io.enq.bits.tag <= UInt<1>("h00") - rpq.io.enq.bits.addr <= UInt<1>("h00") - rpq.io.enq.valid <= UInt<1>("h00") + rpq.io is invalid rpq.clk <= clk rpq.reset <= reset - node T_1743 = and(io.req_pri_val, io.req_pri_rdy) - node T_1744 = and(io.req_sec_val, sec_rdy) - node T_1745 = or(T_1743, T_1744) - node T_1746 = eq(io.req_bits.cmd, UInt<5>("h02")) - node T_1747 = eq(io.req_bits.cmd, UInt<5>("h03")) - node T_1748 = or(T_1746, T_1747) - node T_1750 = eq(T_1748, UInt<1>("h00")) - node T_1751 = and(T_1745, T_1750) - rpq.io.enq.valid <= T_1751 + node T_1734 = and(io.req_pri_val, io.req_pri_rdy) + node T_1735 = and(io.req_sec_val, sec_rdy) + node T_1736 = or(T_1734, T_1735) + node T_1737 = eq(io.req_bits.cmd, UInt<5>("h02")) + node T_1738 = eq(io.req_bits.cmd, UInt<5>("h03")) + node T_1739 = or(T_1737, T_1738) + node T_1741 = eq(T_1739, UInt<1>("h00")) + node T_1742 = and(T_1736, T_1741) + rpq.io.enq.valid <= T_1742 rpq.io.enq.bits <- io.req_bits - node T_1752 = eq(state, UInt<4>("h08")) - node T_1753 = and(io.replay.ready, T_1752) - node T_1754 = eq(state, UInt<1>("h00")) - node T_1755 = or(T_1753, T_1754) - rpq.io.deq.ready <= T_1755 - node T_1756 = eq(req.cmd, UInt<5>("h01")) - node T_1757 = eq(req.cmd, UInt<5>("h07")) - node T_1758 = or(T_1756, T_1757) - node T_1759 = bit(req.cmd, 3) - node T_1760 = eq(req.cmd, UInt<5>("h04")) - node T_1761 = or(T_1759, T_1760) - node T_1762 = or(T_1758, T_1761) - node T_1763 = mux(T_1762, UInt<2>("h03"), UInt<2>("h02")) - node T_1764 = eq(UInt<2>("h02"), io.mem_grant.bits.g_type) - node T_1765 = mux(T_1764, UInt<2>("h03"), UInt<1>("h00")) - node T_1766 = eq(UInt<1>("h01"), io.mem_grant.bits.g_type) - node T_1767 = mux(T_1766, T_1763, T_1765) - node T_1768 = eq(UInt<1>("h00"), io.mem_grant.bits.g_type) - node T_1769 = mux(T_1768, UInt<1>("h01"), T_1767) - node T_1770 = mux(io.mem_grant.bits.is_builtin_type, UInt<1>("h00"), T_1769) + node T_1743 = eq(state, UInt<4>("h08")) + node T_1744 = and(io.replay.ready, T_1743) + node T_1745 = eq(state, UInt<1>("h00")) + node T_1746 = or(T_1744, T_1745) + rpq.io.deq.ready <= T_1746 + node T_1747 = eq(req.cmd, UInt<5>("h01")) + node T_1748 = eq(req.cmd, UInt<5>("h07")) + node T_1749 = or(T_1747, T_1748) + node T_1750 = bits(req.cmd, 3, 3) + node T_1751 = eq(req.cmd, UInt<5>("h04")) + node T_1752 = or(T_1750, T_1751) + node T_1753 = or(T_1749, T_1752) + node T_1754 = mux(T_1753, UInt<2>("h03"), UInt<2>("h02")) + node T_1755 = eq(UInt<2>("h02"), io.mem_grant.bits.g_type) + node T_1756 = mux(T_1755, UInt<2>("h03"), UInt<1>("h00")) + node T_1757 = eq(UInt<1>("h01"), io.mem_grant.bits.g_type) + node T_1758 = mux(T_1757, T_1754, T_1756) + node T_1759 = eq(UInt<1>("h00"), io.mem_grant.bits.g_type) + node T_1760 = mux(T_1759, UInt<1>("h01"), T_1758) + node T_1761 = mux(io.mem_grant.bits.is_builtin_type, UInt<1>("h00"), T_1760) wire coh_on_grant : {state : UInt<2>} - coh_on_grant.state <= UInt<1>("h00") - coh_on_grant.state <= T_1770 - node T_1822 = eq(io.req_bits.cmd, UInt<5>("h01")) - node T_1823 = eq(io.req_bits.cmd, UInt<5>("h07")) - node T_1824 = or(T_1822, T_1823) - node T_1825 = bit(io.req_bits.cmd, 3) - node T_1826 = eq(io.req_bits.cmd, UInt<5>("h04")) - node T_1827 = or(T_1825, T_1826) - node T_1828 = or(T_1824, T_1827) - node T_1829 = mux(T_1828, UInt<2>("h03"), io.req_bits.old_meta.coh.state) + coh_on_grant is invalid + coh_on_grant.state <= T_1761 + node T_1812 = eq(io.req_bits.cmd, UInt<5>("h01")) + node T_1813 = eq(io.req_bits.cmd, UInt<5>("h07")) + node T_1814 = or(T_1812, T_1813) + node T_1815 = bits(io.req_bits.cmd, 3, 3) + node T_1816 = eq(io.req_bits.cmd, UInt<5>("h04")) + node T_1817 = or(T_1815, T_1816) + node T_1818 = or(T_1814, T_1817) + node T_1819 = mux(T_1818, UInt<2>("h03"), io.req_bits.old_meta.coh.state) wire coh_on_hit : {state : UInt<2>} - coh_on_hit.state <= UInt<1>("h00") - coh_on_hit.state <= T_1829 - node T_1881 = eq(state, UInt<4>("h08")) - node T_1883 = eq(rpq.io.deq.valid, UInt<1>("h00")) - node T_1884 = and(T_1881, T_1883) - when T_1884 : + coh_on_hit is invalid + coh_on_hit.state <= T_1819 + node T_1870 = eq(state, UInt<4>("h08")) + node T_1872 = eq(rpq.io.deq.valid, UInt<1>("h00")) + node T_1873 = and(T_1870, T_1872) + when T_1873 : state <= UInt<1>("h00") skip - node T_1885 = eq(state, UInt<3>("h07")) - when T_1885 : + node T_1874 = eq(state, UInt<3>("h07")) + when T_1874 : state <= UInt<4>("h08") skip - node T_1886 = eq(state, UInt<3>("h06")) - node T_1887 = and(T_1886, io.meta_write.ready) - when T_1887 : + node T_1875 = eq(state, UInt<3>("h06")) + node T_1876 = and(T_1875, io.meta_write.ready) + when T_1876 : state <= UInt<3>("h07") skip - node T_1888 = eq(state, UInt<3>("h05")) - when T_1888 : + node T_1877 = eq(state, UInt<3>("h05")) + when T_1877 : when io.mem_grant.valid : new_coh_state <- coh_on_grant skip @@ -29857,230 +22796,216 @@ circuit Top : state <= UInt<3>("h06") skip skip - node T_1889 = and(io.mem_req.ready, io.mem_req.valid) - when T_1889 : + node T_1878 = and(io.mem_req.ready, io.mem_req.valid) + when T_1878 : state <= UInt<3>("h05") skip - node T_1890 = eq(state, UInt<2>("h03")) - node T_1891 = and(T_1890, io.meta_write.ready) - when T_1891 : + node T_1879 = eq(state, UInt<2>("h03")) + node T_1880 = and(T_1879, io.meta_write.ready) + when T_1880 : state <= UInt<3>("h04") skip - node T_1892 = eq(state, UInt<2>("h02")) - node T_1893 = and(T_1892, io.mem_grant.valid) - when T_1893 : + node T_1881 = eq(state, UInt<2>("h02")) + node T_1882 = and(T_1881, io.mem_grant.valid) + when T_1882 : state <= UInt<2>("h03") skip - node T_1894 = and(io.wb_req.ready, io.wb_req.valid) - when T_1894 : - node T_1897 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1898 = mux(T_1897, UInt<2>("h02"), UInt<2>("h03")) - state <= T_1898 + node T_1883 = and(io.wb_req.ready, io.wb_req.valid) + when T_1883 : + node T_1886 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1887 = mux(T_1886, UInt<2>("h02"), UInt<2>("h03")) + state <= T_1887 skip - node T_1899 = and(io.req_sec_val, io.req_sec_rdy) - when T_1899 : + node T_1888 = and(io.req_sec_val, io.req_sec_rdy) + when T_1888 : when cmd_requires_second_acquire : req.cmd <= io.req_bits.cmd skip skip - node T_1900 = and(io.req_pri_val, io.req_pri_rdy) - when T_1900 : + node T_1889 = and(io.req_pri_val, io.req_pri_rdy) + when T_1889 : req <- io.req_bits when io.req_bits.tag_match : - node T_1901 = eq(io.req_bits.cmd, UInt<5>("h01")) - node T_1902 = eq(io.req_bits.cmd, UInt<5>("h07")) - node T_1903 = or(T_1901, T_1902) - node T_1904 = bit(io.req_bits.cmd, 3) - node T_1905 = eq(io.req_bits.cmd, UInt<5>("h04")) - node T_1906 = or(T_1904, T_1905) - node T_1907 = or(T_1903, T_1906) - node T_1908 = eq(io.req_bits.cmd, UInt<5>("h03")) - node T_1909 = or(T_1907, T_1908) - node T_1910 = eq(io.req_bits.cmd, UInt<5>("h06")) - node T_1911 = or(T_1909, T_1910) - wire T_1913 : UInt<2>[2] - T_1913[0] <= UInt<2>("h02") - T_1913[1] <= UInt<2>("h03") - node T_1917 = eq(T_1913[0], io.req_bits.old_meta.coh.state) - node T_1918 = eq(T_1913[1], io.req_bits.old_meta.coh.state) - node T_1920 = or(UInt<1>("h00"), T_1917) - node T_1921 = or(T_1920, T_1918) - wire T_1923 : UInt<2>[3] - T_1923[0] <= UInt<1>("h01") - T_1923[1] <= UInt<2>("h02") - T_1923[2] <= UInt<2>("h03") - node T_1928 = eq(T_1923[0], io.req_bits.old_meta.coh.state) - node T_1929 = eq(T_1923[1], io.req_bits.old_meta.coh.state) - node T_1930 = eq(T_1923[2], io.req_bits.old_meta.coh.state) - node T_1932 = or(UInt<1>("h00"), T_1928) - node T_1933 = or(T_1932, T_1929) - node T_1934 = or(T_1933, T_1930) - node T_1935 = mux(T_1911, T_1921, T_1934) - when T_1935 : + node T_1890 = eq(io.req_bits.cmd, UInt<5>("h01")) + node T_1891 = eq(io.req_bits.cmd, UInt<5>("h07")) + node T_1892 = or(T_1890, T_1891) + node T_1893 = bits(io.req_bits.cmd, 3, 3) + node T_1894 = eq(io.req_bits.cmd, UInt<5>("h04")) + node T_1895 = or(T_1893, T_1894) + node T_1896 = or(T_1892, T_1895) + node T_1897 = eq(io.req_bits.cmd, UInt<5>("h03")) + node T_1898 = or(T_1896, T_1897) + node T_1899 = eq(io.req_bits.cmd, UInt<5>("h06")) + node T_1900 = or(T_1898, T_1899) + wire T_1902 : UInt<2>[2] + T_1902[0] <= UInt<2>("h02") + T_1902[1] <= UInt<2>("h03") + node T_1906 = eq(T_1902[0], io.req_bits.old_meta.coh.state) + node T_1907 = eq(T_1902[1], io.req_bits.old_meta.coh.state) + node T_1909 = or(UInt<1>("h00"), T_1906) + node T_1910 = or(T_1909, T_1907) + wire T_1912 : UInt<2>[3] + T_1912[0] <= UInt<1>("h01") + T_1912[1] <= UInt<2>("h02") + T_1912[2] <= UInt<2>("h03") + node T_1917 = eq(T_1912[0], io.req_bits.old_meta.coh.state) + node T_1918 = eq(T_1912[1], io.req_bits.old_meta.coh.state) + node T_1919 = eq(T_1912[2], io.req_bits.old_meta.coh.state) + node T_1921 = or(UInt<1>("h00"), T_1917) + node T_1922 = or(T_1921, T_1918) + node T_1923 = or(T_1922, T_1919) + node T_1924 = mux(T_1900, T_1910, T_1923) + when T_1924 : state <= UInt<3>("h06") new_coh_state <- coh_on_hit skip - node T_1937 = eq(T_1935, UInt<1>("h00")) - when T_1937 : + node T_1926 = eq(T_1924, UInt<1>("h00")) + when T_1926 : state <= UInt<3>("h04") skip skip - node T_1939 = eq(io.req_bits.tag_match, UInt<1>("h00")) - when T_1939 : - wire T_1941 : UInt<2>[1] - T_1941[0] <= UInt<2>("h03") - node T_1944 = eq(T_1941[0], io.req_bits.old_meta.coh.state) - node T_1946 = or(UInt<1>("h00"), T_1944) - node T_1947 = mux(T_1946, UInt<1>("h01"), UInt<2>("h03")) - state <= T_1947 + node T_1928 = eq(io.req_bits.tag_match, UInt<1>("h00")) + when T_1928 : + wire T_1930 : UInt<2>[1] + T_1930[0] <= UInt<2>("h03") + node T_1933 = eq(T_1930[0], io.req_bits.old_meta.coh.state) + node T_1935 = or(UInt<1>("h00"), T_1933) + node T_1936 = mux(T_1935, UInt<1>("h01"), UInt<2>("h03")) + state <= T_1936 skip skip - node T_1948 = neq(state, UInt<1>("h00")) - node T_1949 = and(T_1948, idx_match) - io.idx_match <= T_1949 + node T_1937 = neq(state, UInt<1>("h00")) + node T_1938 = and(T_1937, idx_match) + io.idx_match <= T_1938 io.refill.way_en <= req.way_en - node T_1950 = cat(req_idx, refill_cnt) - node T_1951 = shl(T_1950, 4) - io.refill.addr <= T_1951 - node T_1952 = shr(req.addr, 12) - io.tag <= T_1952 - node T_1953 = eq(state, UInt<1>("h00")) - io.req_pri_rdy <= T_1953 - node T_1954 = and(sec_rdy, rpq.io.enq.ready) - io.req_sec_rdy <= T_1954 - reg meta_hazard : UInt<2>, clk, reset, UInt<2>("h00") - node T_1958 = neq(meta_hazard, UInt<1>("h00")) - when T_1958 : - node T_1960 = addw(meta_hazard, UInt<1>("h01")) - meta_hazard <= T_1960 - skip - node T_1961 = and(io.meta_write.ready, io.meta_write.valid) - when T_1961 : + node T_1939 = cat(req_idx, refill_cnt) + node T_1940 = shl(T_1939, 4) + io.refill.addr <= T_1940 + node T_1941 = shr(req.addr, 12) + io.tag <= T_1941 + node T_1942 = eq(state, UInt<1>("h00")) + io.req_pri_rdy <= T_1942 + node T_1943 = and(sec_rdy, rpq.io.enq.ready) + io.req_sec_rdy <= T_1943 + reg meta_hazard : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + node T_1947 = neq(meta_hazard, UInt<1>("h00")) + when T_1947 : + node T_1949 = add(meta_hazard, UInt<1>("h01")) + node T_1950 = tail(T_1949, 1) + meta_hazard <= T_1950 + skip + node T_1951 = and(io.meta_write.ready, io.meta_write.valid) + when T_1951 : meta_hazard <= UInt<1>("h01") skip - node T_1964 = eq(idx_match, UInt<1>("h00")) - node T_1965 = eq(states_before_refill[0], state) - node T_1966 = eq(states_before_refill[1], state) - node T_1967 = eq(states_before_refill[2], state) - node T_1969 = or(UInt<1>("h00"), T_1965) - node T_1970 = or(T_1969, T_1966) - node T_1971 = or(T_1970, T_1967) - node T_1973 = eq(T_1971, UInt<1>("h00")) - node T_1975 = eq(meta_hazard, UInt<1>("h00")) - node T_1976 = and(T_1973, T_1975) - node T_1977 = or(T_1964, T_1976) - io.probe_rdy <= T_1977 - node T_1978 = eq(state, UInt<3>("h06")) - node T_1979 = eq(state, UInt<2>("h03")) - node T_1980 = or(T_1978, T_1979) - io.meta_write.valid <= T_1980 + node T_1954 = eq(idx_match, UInt<1>("h00")) + node T_1955 = eq(states_before_refill[0], state) + node T_1956 = eq(states_before_refill[1], state) + node T_1957 = eq(states_before_refill[2], state) + node T_1959 = or(UInt<1>("h00"), T_1955) + node T_1960 = or(T_1959, T_1956) + node T_1961 = or(T_1960, T_1957) + node T_1963 = eq(T_1961, UInt<1>("h00")) + node T_1965 = eq(meta_hazard, UInt<1>("h00")) + node T_1966 = and(T_1963, T_1965) + node T_1967 = or(T_1954, T_1966) + io.probe_rdy <= T_1967 + node T_1968 = eq(state, UInt<3>("h06")) + node T_1969 = eq(state, UInt<2>("h03")) + node T_1970 = or(T_1968, T_1969) + io.meta_write.valid <= T_1970 io.meta_write.bits.idx <= req_idx - node T_1981 = eq(state, UInt<2>("h03")) - wire T_1983 : UInt<2>[2] - T_1983[0] <= UInt<2>("h02") - T_1983[1] <= UInt<2>("h03") - node T_1987 = eq(T_1983[0], req.old_meta.coh.state) - node T_1988 = eq(T_1983[1], req.old_meta.coh.state) - node T_1990 = or(UInt<1>("h00"), T_1987) - node T_1991 = or(T_1990, T_1988) - node T_1992 = mux(T_1991, UInt<1>("h01"), req.old_meta.coh.state) - node T_1993 = eq(req.old_meta.coh.state, UInt<2>("h03")) - node T_1994 = mux(T_1993, UInt<2>("h02"), req.old_meta.coh.state) - node T_1995 = eq(UInt<5>("h013"), UInt<5>("h010")) - node T_1996 = mux(T_1995, T_1994, req.old_meta.coh.state) - node T_1997 = eq(UInt<5>("h011"), UInt<5>("h010")) - node T_1998 = mux(T_1997, T_1992, T_1996) - node T_1999 = eq(UInt<5>("h010"), UInt<5>("h010")) - node T_2000 = mux(T_1999, UInt<1>("h00"), T_1998) - wire T_2026 : {state : UInt<2>} - T_2026.state <= UInt<1>("h00") - T_2026.state <= T_2000 - wire T_2077 : {state : UInt<2>} - T_2077 <- new_coh_state - when T_1981 : - T_2077 <- T_2026 - skip - io.meta_write.bits.data.coh <- T_2077 + node T_1971 = eq(state, UInt<2>("h03")) + wire T_1973 : UInt<2>[2] + T_1973[0] <= UInt<2>("h02") + T_1973[1] <= UInt<2>("h03") + node T_1977 = eq(T_1973[0], req.old_meta.coh.state) + node T_1978 = eq(T_1973[1], req.old_meta.coh.state) + node T_1980 = or(UInt<1>("h00"), T_1977) + node T_1981 = or(T_1980, T_1978) + node T_1982 = mux(T_1981, UInt<1>("h01"), req.old_meta.coh.state) + node T_1983 = eq(req.old_meta.coh.state, UInt<2>("h03")) + node T_1984 = mux(T_1983, UInt<2>("h02"), req.old_meta.coh.state) + node T_1985 = eq(UInt<5>("h013"), UInt<5>("h010")) + node T_1986 = mux(T_1985, T_1984, req.old_meta.coh.state) + node T_1987 = eq(UInt<5>("h011"), UInt<5>("h010")) + node T_1988 = mux(T_1987, T_1982, T_1986) + node T_1989 = eq(UInt<5>("h010"), UInt<5>("h010")) + node T_1990 = mux(T_1989, UInt<1>("h00"), T_1988) + wire T_2016 : {state : UInt<2>} + T_2016 is invalid + T_2016.state <= T_1990 + node T_2041 = mux(T_1971, T_2016, new_coh_state) + io.meta_write.bits.data.coh <- T_2041 io.meta_write.bits.data.tag <= io.tag io.meta_write.bits.way_en <= req.way_en - node T_2102 = eq(state, UInt<1>("h01")) - io.wb_req.valid <= T_2102 - node T_2104 = cat(req.old_meta.tag, req_idx) - wire T_2109 : UInt<2>[1] - T_2109[0] <= UInt<2>("h03") - node T_2112 = eq(T_2109[0], req.old_meta.coh.state) - node T_2114 = or(UInt<1>("h00"), T_2112) - node T_2115 = mux(T_2114, UInt<1>("h00"), UInt<2>("h03")) - node T_2116 = mux(T_2114, UInt<1>("h01"), UInt<3>("h04")) - node T_2117 = mux(T_2114, UInt<2>("h02"), UInt<3>("h05")) - node T_2118 = eq(UInt<5>("h013"), UInt<5>("h010")) - node T_2119 = mux(T_2118, T_2117, UInt<3>("h05")) - node T_2120 = eq(UInt<5>("h011"), UInt<5>("h010")) - node T_2121 = mux(T_2120, T_2116, T_2119) - node T_2122 = eq(UInt<5>("h010"), UInt<5>("h010")) - node T_2123 = mux(T_2122, T_2115, T_2121) - wire T_2154 : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>} - T_2154.data <= UInt<1>("h00") - T_2154.r_type <= UInt<1>("h00") - T_2154.voluntary <= UInt<1>("h00") - T_2154.client_xact_id <= UInt<1>("h00") - T_2154.addr_block <= UInt<1>("h00") - T_2154.addr_beat <= UInt<1>("h00") - T_2154.r_type <= T_2123 - T_2154.client_xact_id <= UInt<1>("h00") - T_2154.addr_block <= T_2104 - T_2154.addr_beat <= UInt<1>("h00") - T_2154.data <= UInt<1>("h00") - T_2154.voluntary <= UInt<1>("h01") - io.wb_req.bits <- T_2154 + node T_2066 = eq(state, UInt<1>("h01")) + io.wb_req.valid <= T_2066 + node T_2068 = cat(req.old_meta.tag, req_idx) + wire T_2073 : UInt<2>[1] + T_2073[0] <= UInt<2>("h03") + node T_2076 = eq(T_2073[0], req.old_meta.coh.state) + node T_2078 = or(UInt<1>("h00"), T_2076) + node T_2079 = mux(T_2078, UInt<1>("h00"), UInt<2>("h03")) + node T_2080 = mux(T_2078, UInt<1>("h01"), UInt<3>("h04")) + node T_2081 = mux(T_2078, UInt<2>("h02"), UInt<3>("h05")) + node T_2082 = eq(UInt<5>("h013"), UInt<5>("h010")) + node T_2083 = mux(T_2082, T_2081, UInt<3>("h05")) + node T_2084 = eq(UInt<5>("h011"), UInt<5>("h010")) + node T_2085 = mux(T_2084, T_2080, T_2083) + node T_2086 = eq(UInt<5>("h010"), UInt<5>("h010")) + node T_2087 = mux(T_2086, T_2079, T_2085) + wire T_2118 : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>} + T_2118 is invalid + T_2118.r_type <= T_2087 + T_2118.client_xact_id <= UInt<1>("h00") + T_2118.addr_block <= T_2068 + T_2118.addr_beat <= UInt<1>("h00") + T_2118.data <= UInt<1>("h00") + T_2118.voluntary <= UInt<1>("h01") + io.wb_req.bits <- T_2118 io.wb_req.bits.way_en <= req.way_en - node T_2190 = eq(state, UInt<3>("h04")) - io.mem_req.valid <= T_2190 - node T_2191 = cat(io.tag, req_idx) - node T_2194 = eq(req.cmd, UInt<5>("h01")) - node T_2195 = eq(req.cmd, UInt<5>("h07")) - node T_2196 = or(T_2194, T_2195) - node T_2197 = bit(req.cmd, 3) - node T_2198 = eq(req.cmd, UInt<5>("h04")) - node T_2199 = or(T_2197, T_2198) - node T_2200 = or(T_2196, T_2199) - node T_2201 = eq(req.cmd, UInt<5>("h03")) - node T_2202 = or(T_2200, T_2201) - node T_2203 = eq(req.cmd, UInt<5>("h06")) - node T_2204 = or(T_2202, T_2203) - node T_2205 = mux(T_2204, UInt<1>("h01"), UInt<1>("h00")) - node T_2207 = cat(req.cmd, UInt<1>("h01")) - wire T_2241 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_2241.data <= UInt<1>("h00") - T_2241.union <= UInt<1>("h00") - T_2241.a_type <= UInt<1>("h00") - T_2241.is_builtin_type <= UInt<1>("h00") - T_2241.addr_beat <= UInt<1>("h00") - T_2241.client_xact_id <= UInt<1>("h00") - T_2241.addr_block <= UInt<1>("h00") - T_2241.is_builtin_type <= UInt<1>("h00") - T_2241.a_type <= T_2205 - T_2241.client_xact_id <= UInt<1>("h00") - T_2241.addr_block <= T_2191 - T_2241.addr_beat <= UInt<1>("h00") - T_2241.data <= UInt<1>("h00") - T_2241.union <= T_2207 - io.mem_req.bits <- T_2241 - node T_2279 = eq(state, UInt<4>("h08")) - io.meta_read.valid <= T_2279 + node T_2148 = eq(state, UInt<3>("h04")) + io.mem_req.valid <= T_2148 + node T_2149 = cat(io.tag, req_idx) + node T_2152 = eq(req.cmd, UInt<5>("h01")) + node T_2153 = eq(req.cmd, UInt<5>("h07")) + node T_2154 = or(T_2152, T_2153) + node T_2155 = bits(req.cmd, 3, 3) + node T_2156 = eq(req.cmd, UInt<5>("h04")) + node T_2157 = or(T_2155, T_2156) + node T_2158 = or(T_2154, T_2157) + node T_2159 = eq(req.cmd, UInt<5>("h03")) + node T_2160 = or(T_2158, T_2159) + node T_2161 = eq(req.cmd, UInt<5>("h06")) + node T_2162 = or(T_2160, T_2161) + node T_2163 = mux(T_2162, UInt<1>("h01"), UInt<1>("h00")) + node T_2165 = cat(req.cmd, UInt<1>("h01")) + wire T_2199 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} + T_2199 is invalid + T_2199.is_builtin_type <= UInt<1>("h00") + T_2199.a_type <= T_2163 + T_2199.client_xact_id <= UInt<1>("h00") + T_2199.addr_block <= T_2149 + T_2199.addr_beat <= UInt<1>("h00") + T_2199.data <= UInt<1>("h00") + T_2199.union <= T_2165 + io.mem_req.bits <- T_2199 + node T_2230 = eq(state, UInt<4>("h08")) + io.meta_read.valid <= T_2230 io.meta_read.bits.idx <= req_idx io.meta_read.bits.tag <= io.tag - node T_2280 = eq(state, UInt<4>("h08")) - node T_2281 = and(T_2280, rpq.io.deq.valid) - io.replay.valid <= T_2281 + node T_2231 = eq(state, UInt<4>("h08")) + node T_2232 = and(T_2231, rpq.io.deq.valid) + io.replay.valid <= T_2232 io.replay.bits <- rpq.io.deq.bits io.replay.bits.phys <= UInt<1>("h01") - node T_2283 = bits(rpq.io.deq.bits.addr, 5, 0) - node T_2284 = cat(req_idx, T_2283) - node T_2285 = cat(io.tag, T_2284) - io.replay.bits.addr <= T_2285 - node T_2287 = eq(io.meta_read.ready, UInt<1>("h00")) - when T_2287 : + node T_2234 = bits(rpq.io.deq.bits.addr, 5, 0) + node T_2235 = cat(req_idx, T_2234) + node T_2236 = cat(io.tag, T_2235) + io.replay.bits.addr <= T_2236 + node T_2238 = eq(io.meta_read.ready, UInt<1>("h00")) + when T_2238 : rpq.io.deq.ready <= UInt<1>("h00") io.replay.bits.cmd <= UInt<5>("h05") skip @@ -30090,198 +23015,153 @@ circuit Top : input reset : UInt<1> output io : {flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, idx_match : UInt<1>, tag : UInt<20>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>} - io.probe_rdy <= UInt<1>("h00") - io.wb_req.bits.way_en <= UInt<1>("h00") - io.wb_req.bits.data <= UInt<1>("h00") - io.wb_req.bits.r_type <= UInt<1>("h00") - io.wb_req.bits.voluntary <= UInt<1>("h00") - io.wb_req.bits.client_xact_id <= UInt<1>("h00") - io.wb_req.bits.addr_block <= UInt<1>("h00") - io.wb_req.bits.addr_beat <= UInt<1>("h00") - io.wb_req.valid <= UInt<1>("h00") - io.replay.bits.sdq_id <= UInt<1>("h00") - io.replay.bits.phys <= UInt<1>("h00") - io.replay.bits.kill <= UInt<1>("h00") - io.replay.bits.typ <= UInt<1>("h00") - io.replay.bits.cmd <= UInt<1>("h00") - io.replay.bits.tag <= UInt<1>("h00") - io.replay.bits.addr <= UInt<1>("h00") - io.replay.valid <= UInt<1>("h00") - io.meta_write.bits.data.coh.state <= UInt<1>("h00") - io.meta_write.bits.data.tag <= UInt<1>("h00") - io.meta_write.bits.way_en <= UInt<1>("h00") - io.meta_write.bits.idx <= UInt<1>("h00") - io.meta_write.valid <= UInt<1>("h00") - io.meta_read.bits.tag <= UInt<1>("h00") - io.meta_read.bits.idx <= UInt<1>("h00") - io.meta_read.valid <= UInt<1>("h00") - io.refill.addr <= UInt<1>("h00") - io.refill.way_en <= UInt<1>("h00") - io.mem_req.bits.data <= UInt<1>("h00") - io.mem_req.bits.union <= UInt<1>("h00") - io.mem_req.bits.a_type <= UInt<1>("h00") - io.mem_req.bits.is_builtin_type <= UInt<1>("h00") - io.mem_req.bits.addr_beat <= UInt<1>("h00") - io.mem_req.bits.client_xact_id <= UInt<1>("h00") - io.mem_req.bits.addr_block <= UInt<1>("h00") - io.mem_req.valid <= UInt<1>("h00") - io.tag <= UInt<1>("h00") - io.idx_match <= UInt<1>("h00") - io.req_sec_rdy <= UInt<1>("h00") - io.req_pri_rdy <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) wire T_1277 : {state : UInt<2>} + T_1277 is invalid T_1277.state <= UInt<1>("h00") - T_1277.state <= UInt<1>("h00") - reg new_coh_state : {state : UInt<2>}, clk, reset, T_1277 - reg req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, clk, UInt<1>("h00"), req + reg new_coh_state : {state : UInt<2>}, clk with : (reset => (reset, T_1277)) + reg req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, clk node req_idx = bits(req.addr, 11, 6) - node T_1587 = bits(io.req_bits.addr, 11, 6) - node idx_match = eq(req_idx, T_1587) - node T_1589 = eq(io.req_bits.cmd, UInt<5>("h01")) - node T_1590 = eq(io.req_bits.cmd, UInt<5>("h07")) - node T_1591 = or(T_1589, T_1590) - node T_1592 = bit(io.req_bits.cmd, 3) - node T_1593 = eq(io.req_bits.cmd, UInt<5>("h04")) - node T_1594 = or(T_1592, T_1593) - node T_1595 = or(T_1591, T_1594) - node T_1596 = eq(io.req_bits.cmd, UInt<5>("h03")) - node T_1597 = or(T_1595, T_1596) - node T_1598 = eq(io.req_bits.cmd, UInt<5>("h06")) - node T_1599 = or(T_1597, T_1598) - node T_1600 = eq(req.cmd, UInt<5>("h01")) - node T_1601 = eq(req.cmd, UInt<5>("h07")) - node T_1602 = or(T_1600, T_1601) - node T_1603 = bit(req.cmd, 3) - node T_1604 = eq(req.cmd, UInt<5>("h04")) - node T_1605 = or(T_1603, T_1604) - node T_1606 = or(T_1602, T_1605) - node T_1607 = eq(req.cmd, UInt<5>("h03")) - node T_1608 = or(T_1606, T_1607) - node T_1609 = eq(req.cmd, UInt<5>("h06")) - node T_1610 = or(T_1608, T_1609) - node T_1612 = eq(T_1610, UInt<1>("h00")) - node cmd_requires_second_acquire = and(T_1599, T_1612) + node T_1586 = bits(io.req_bits.addr, 11, 6) + node idx_match = eq(req_idx, T_1586) + node T_1588 = eq(io.req_bits.cmd, UInt<5>("h01")) + node T_1589 = eq(io.req_bits.cmd, UInt<5>("h07")) + node T_1590 = or(T_1588, T_1589) + node T_1591 = bits(io.req_bits.cmd, 3, 3) + node T_1592 = eq(io.req_bits.cmd, UInt<5>("h04")) + node T_1593 = or(T_1591, T_1592) + node T_1594 = or(T_1590, T_1593) + node T_1595 = eq(io.req_bits.cmd, UInt<5>("h03")) + node T_1596 = or(T_1594, T_1595) + node T_1597 = eq(io.req_bits.cmd, UInt<5>("h06")) + node T_1598 = or(T_1596, T_1597) + node T_1599 = eq(req.cmd, UInt<5>("h01")) + node T_1600 = eq(req.cmd, UInt<5>("h07")) + node T_1601 = or(T_1599, T_1600) + node T_1602 = bits(req.cmd, 3, 3) + node T_1603 = eq(req.cmd, UInt<5>("h04")) + node T_1604 = or(T_1602, T_1603) + node T_1605 = or(T_1601, T_1604) + node T_1606 = eq(req.cmd, UInt<5>("h03")) + node T_1607 = or(T_1605, T_1606) + node T_1608 = eq(req.cmd, UInt<5>("h06")) + node T_1609 = or(T_1607, T_1608) + node T_1611 = eq(T_1609, UInt<1>("h00")) + node cmd_requires_second_acquire = and(T_1598, T_1611) wire states_before_refill : UInt<2>[3] states_before_refill[0] <= UInt<1>("h01") states_before_refill[1] <= UInt<2>("h02") states_before_refill[2] <= UInt<2>("h03") - node T_1620 = eq(states_before_refill[0], state) - node T_1621 = eq(states_before_refill[1], state) - node T_1622 = eq(states_before_refill[2], state) - node T_1624 = or(UInt<1>("h00"), T_1620) + node T_1619 = eq(states_before_refill[0], state) + node T_1620 = eq(states_before_refill[1], state) + node T_1621 = eq(states_before_refill[2], state) + node T_1623 = or(UInt<1>("h00"), T_1619) + node T_1624 = or(T_1623, T_1620) node T_1625 = or(T_1624, T_1621) - node T_1626 = or(T_1625, T_1622) - wire T_1628 : UInt<3>[2] - T_1628[0] <= UInt<3>("h04") - T_1628[1] <= UInt<3>("h05") - node T_1632 = eq(T_1628[0], state) - node T_1633 = eq(T_1628[1], state) - node T_1635 = or(UInt<1>("h00"), T_1632) - node T_1636 = or(T_1635, T_1633) - node T_1638 = eq(cmd_requires_second_acquire, UInt<1>("h00")) - node T_1639 = and(T_1636, T_1638) - node T_1640 = or(T_1626, T_1639) - node sec_rdy = and(idx_match, T_1640) - wire T_1645 : UInt<3>[1] - T_1645[0] <= UInt<3>("h05") - node T_1648 = eq(T_1645[0], io.mem_grant.bits.g_type) - node T_1650 = or(UInt<1>("h00"), T_1648) - wire T_1652 : UInt<1>[2] - T_1652[0] <= UInt<1>("h00") - T_1652[1] <= UInt<1>("h01") - node T_1656 = eq(T_1652[0], io.mem_grant.bits.g_type) - node T_1657 = eq(T_1652[1], io.mem_grant.bits.g_type) - node T_1659 = or(UInt<1>("h00"), T_1656) - node T_1660 = or(T_1659, T_1657) - node T_1661 = mux(io.mem_grant.bits.is_builtin_type, T_1650, T_1660) - node gnt_multi_data = and(UInt<1>("h01"), T_1661) - node T_1663 = and(io.mem_grant.valid, gnt_multi_data) - reg refill_cnt : UInt<2>, clk, reset, UInt<2>("h00") - when T_1663 : - node T_1667 = eq(refill_cnt, UInt<2>("h03")) - node T_1669 = and(UInt<1>("h00"), T_1667) - node T_1672 = addw(refill_cnt, UInt<1>("h01")) - node T_1673 = mux(T_1669, UInt<1>("h00"), T_1672) + wire T_1627 : UInt<3>[2] + T_1627[0] <= UInt<3>("h04") + T_1627[1] <= UInt<3>("h05") + node T_1631 = eq(T_1627[0], state) + node T_1632 = eq(T_1627[1], state) + node T_1634 = or(UInt<1>("h00"), T_1631) + node T_1635 = or(T_1634, T_1632) + node T_1637 = eq(cmd_requires_second_acquire, UInt<1>("h00")) + node T_1638 = and(T_1635, T_1637) + node T_1639 = or(T_1625, T_1638) + node sec_rdy = and(idx_match, T_1639) + wire T_1644 : UInt<3>[1] + T_1644[0] <= UInt<3>("h05") + node T_1647 = eq(T_1644[0], io.mem_grant.bits.g_type) + node T_1649 = or(UInt<1>("h00"), T_1647) + wire T_1651 : UInt<1>[2] + T_1651[0] <= UInt<1>("h00") + T_1651[1] <= UInt<1>("h01") + node T_1655 = eq(T_1651[0], io.mem_grant.bits.g_type) + node T_1656 = eq(T_1651[1], io.mem_grant.bits.g_type) + node T_1658 = or(UInt<1>("h00"), T_1655) + node T_1659 = or(T_1658, T_1656) + node T_1660 = mux(io.mem_grant.bits.is_builtin_type, T_1649, T_1659) + node gnt_multi_data = and(UInt<1>("h01"), T_1660) + node T_1662 = and(io.mem_grant.valid, gnt_multi_data) + reg refill_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + when T_1662 : + node T_1666 = eq(refill_cnt, UInt<2>("h03")) + node T_1668 = and(UInt<1>("h00"), T_1666) + node T_1671 = add(refill_cnt, UInt<1>("h01")) + node T_1672 = tail(T_1671, 1) + node T_1673 = mux(T_1668, UInt<1>("h00"), T_1672) refill_cnt <= T_1673 skip - node refill_count_done = and(T_1663, T_1667) + node refill_count_done = and(T_1662, T_1666) node T_1676 = eq(gnt_multi_data, UInt<1>("h00")) node T_1677 = or(T_1676, refill_count_done) node refill_done = and(io.mem_grant.valid, T_1677) inst rpq of Queue_98 - rpq.io.deq.ready <= UInt<1>("h00") - rpq.io.enq.bits.sdq_id <= UInt<1>("h00") - rpq.io.enq.bits.phys <= UInt<1>("h00") - rpq.io.enq.bits.kill <= UInt<1>("h00") - rpq.io.enq.bits.typ <= UInt<1>("h00") - rpq.io.enq.bits.cmd <= UInt<1>("h00") - rpq.io.enq.bits.tag <= UInt<1>("h00") - rpq.io.enq.bits.addr <= UInt<1>("h00") - rpq.io.enq.valid <= UInt<1>("h00") + rpq.io is invalid rpq.clk <= clk rpq.reset <= reset - node T_1743 = and(io.req_pri_val, io.req_pri_rdy) - node T_1744 = and(io.req_sec_val, sec_rdy) - node T_1745 = or(T_1743, T_1744) - node T_1746 = eq(io.req_bits.cmd, UInt<5>("h02")) - node T_1747 = eq(io.req_bits.cmd, UInt<5>("h03")) - node T_1748 = or(T_1746, T_1747) - node T_1750 = eq(T_1748, UInt<1>("h00")) - node T_1751 = and(T_1745, T_1750) - rpq.io.enq.valid <= T_1751 + node T_1734 = and(io.req_pri_val, io.req_pri_rdy) + node T_1735 = and(io.req_sec_val, sec_rdy) + node T_1736 = or(T_1734, T_1735) + node T_1737 = eq(io.req_bits.cmd, UInt<5>("h02")) + node T_1738 = eq(io.req_bits.cmd, UInt<5>("h03")) + node T_1739 = or(T_1737, T_1738) + node T_1741 = eq(T_1739, UInt<1>("h00")) + node T_1742 = and(T_1736, T_1741) + rpq.io.enq.valid <= T_1742 rpq.io.enq.bits <- io.req_bits - node T_1752 = eq(state, UInt<4>("h08")) - node T_1753 = and(io.replay.ready, T_1752) - node T_1754 = eq(state, UInt<1>("h00")) - node T_1755 = or(T_1753, T_1754) - rpq.io.deq.ready <= T_1755 - node T_1756 = eq(req.cmd, UInt<5>("h01")) - node T_1757 = eq(req.cmd, UInt<5>("h07")) - node T_1758 = or(T_1756, T_1757) - node T_1759 = bit(req.cmd, 3) - node T_1760 = eq(req.cmd, UInt<5>("h04")) - node T_1761 = or(T_1759, T_1760) - node T_1762 = or(T_1758, T_1761) - node T_1763 = mux(T_1762, UInt<2>("h03"), UInt<2>("h02")) - node T_1764 = eq(UInt<2>("h02"), io.mem_grant.bits.g_type) - node T_1765 = mux(T_1764, UInt<2>("h03"), UInt<1>("h00")) - node T_1766 = eq(UInt<1>("h01"), io.mem_grant.bits.g_type) - node T_1767 = mux(T_1766, T_1763, T_1765) - node T_1768 = eq(UInt<1>("h00"), io.mem_grant.bits.g_type) - node T_1769 = mux(T_1768, UInt<1>("h01"), T_1767) - node T_1770 = mux(io.mem_grant.bits.is_builtin_type, UInt<1>("h00"), T_1769) + node T_1743 = eq(state, UInt<4>("h08")) + node T_1744 = and(io.replay.ready, T_1743) + node T_1745 = eq(state, UInt<1>("h00")) + node T_1746 = or(T_1744, T_1745) + rpq.io.deq.ready <= T_1746 + node T_1747 = eq(req.cmd, UInt<5>("h01")) + node T_1748 = eq(req.cmd, UInt<5>("h07")) + node T_1749 = or(T_1747, T_1748) + node T_1750 = bits(req.cmd, 3, 3) + node T_1751 = eq(req.cmd, UInt<5>("h04")) + node T_1752 = or(T_1750, T_1751) + node T_1753 = or(T_1749, T_1752) + node T_1754 = mux(T_1753, UInt<2>("h03"), UInt<2>("h02")) + node T_1755 = eq(UInt<2>("h02"), io.mem_grant.bits.g_type) + node T_1756 = mux(T_1755, UInt<2>("h03"), UInt<1>("h00")) + node T_1757 = eq(UInt<1>("h01"), io.mem_grant.bits.g_type) + node T_1758 = mux(T_1757, T_1754, T_1756) + node T_1759 = eq(UInt<1>("h00"), io.mem_grant.bits.g_type) + node T_1760 = mux(T_1759, UInt<1>("h01"), T_1758) + node T_1761 = mux(io.mem_grant.bits.is_builtin_type, UInt<1>("h00"), T_1760) wire coh_on_grant : {state : UInt<2>} - coh_on_grant.state <= UInt<1>("h00") - coh_on_grant.state <= T_1770 - node T_1822 = eq(io.req_bits.cmd, UInt<5>("h01")) - node T_1823 = eq(io.req_bits.cmd, UInt<5>("h07")) - node T_1824 = or(T_1822, T_1823) - node T_1825 = bit(io.req_bits.cmd, 3) - node T_1826 = eq(io.req_bits.cmd, UInt<5>("h04")) - node T_1827 = or(T_1825, T_1826) - node T_1828 = or(T_1824, T_1827) - node T_1829 = mux(T_1828, UInt<2>("h03"), io.req_bits.old_meta.coh.state) + coh_on_grant is invalid + coh_on_grant.state <= T_1761 + node T_1812 = eq(io.req_bits.cmd, UInt<5>("h01")) + node T_1813 = eq(io.req_bits.cmd, UInt<5>("h07")) + node T_1814 = or(T_1812, T_1813) + node T_1815 = bits(io.req_bits.cmd, 3, 3) + node T_1816 = eq(io.req_bits.cmd, UInt<5>("h04")) + node T_1817 = or(T_1815, T_1816) + node T_1818 = or(T_1814, T_1817) + node T_1819 = mux(T_1818, UInt<2>("h03"), io.req_bits.old_meta.coh.state) wire coh_on_hit : {state : UInt<2>} - coh_on_hit.state <= UInt<1>("h00") - coh_on_hit.state <= T_1829 - node T_1881 = eq(state, UInt<4>("h08")) - node T_1883 = eq(rpq.io.deq.valid, UInt<1>("h00")) - node T_1884 = and(T_1881, T_1883) - when T_1884 : + coh_on_hit is invalid + coh_on_hit.state <= T_1819 + node T_1870 = eq(state, UInt<4>("h08")) + node T_1872 = eq(rpq.io.deq.valid, UInt<1>("h00")) + node T_1873 = and(T_1870, T_1872) + when T_1873 : state <= UInt<1>("h00") skip - node T_1885 = eq(state, UInt<3>("h07")) - when T_1885 : + node T_1874 = eq(state, UInt<3>("h07")) + when T_1874 : state <= UInt<4>("h08") skip - node T_1886 = eq(state, UInt<3>("h06")) - node T_1887 = and(T_1886, io.meta_write.ready) - when T_1887 : + node T_1875 = eq(state, UInt<3>("h06")) + node T_1876 = and(T_1875, io.meta_write.ready) + when T_1876 : state <= UInt<3>("h07") skip - node T_1888 = eq(state, UInt<3>("h05")) - when T_1888 : + node T_1877 = eq(state, UInt<3>("h05")) + when T_1877 : when io.mem_grant.valid : new_coh_state <- coh_on_grant skip @@ -30289,230 +23169,216 @@ circuit Top : state <= UInt<3>("h06") skip skip - node T_1889 = and(io.mem_req.ready, io.mem_req.valid) - when T_1889 : + node T_1878 = and(io.mem_req.ready, io.mem_req.valid) + when T_1878 : state <= UInt<3>("h05") skip - node T_1890 = eq(state, UInt<2>("h03")) - node T_1891 = and(T_1890, io.meta_write.ready) - when T_1891 : + node T_1879 = eq(state, UInt<2>("h03")) + node T_1880 = and(T_1879, io.meta_write.ready) + when T_1880 : state <= UInt<3>("h04") skip - node T_1892 = eq(state, UInt<2>("h02")) - node T_1893 = and(T_1892, io.mem_grant.valid) - when T_1893 : + node T_1881 = eq(state, UInt<2>("h02")) + node T_1882 = and(T_1881, io.mem_grant.valid) + when T_1882 : state <= UInt<2>("h03") skip - node T_1894 = and(io.wb_req.ready, io.wb_req.valid) - when T_1894 : - node T_1897 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1898 = mux(T_1897, UInt<2>("h02"), UInt<2>("h03")) - state <= T_1898 + node T_1883 = and(io.wb_req.ready, io.wb_req.valid) + when T_1883 : + node T_1886 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1887 = mux(T_1886, UInt<2>("h02"), UInt<2>("h03")) + state <= T_1887 skip - node T_1899 = and(io.req_sec_val, io.req_sec_rdy) - when T_1899 : + node T_1888 = and(io.req_sec_val, io.req_sec_rdy) + when T_1888 : when cmd_requires_second_acquire : req.cmd <= io.req_bits.cmd skip skip - node T_1900 = and(io.req_pri_val, io.req_pri_rdy) - when T_1900 : + node T_1889 = and(io.req_pri_val, io.req_pri_rdy) + when T_1889 : req <- io.req_bits when io.req_bits.tag_match : - node T_1901 = eq(io.req_bits.cmd, UInt<5>("h01")) - node T_1902 = eq(io.req_bits.cmd, UInt<5>("h07")) - node T_1903 = or(T_1901, T_1902) - node T_1904 = bit(io.req_bits.cmd, 3) - node T_1905 = eq(io.req_bits.cmd, UInt<5>("h04")) - node T_1906 = or(T_1904, T_1905) - node T_1907 = or(T_1903, T_1906) - node T_1908 = eq(io.req_bits.cmd, UInt<5>("h03")) - node T_1909 = or(T_1907, T_1908) - node T_1910 = eq(io.req_bits.cmd, UInt<5>("h06")) - node T_1911 = or(T_1909, T_1910) - wire T_1913 : UInt<2>[2] - T_1913[0] <= UInt<2>("h02") - T_1913[1] <= UInt<2>("h03") - node T_1917 = eq(T_1913[0], io.req_bits.old_meta.coh.state) - node T_1918 = eq(T_1913[1], io.req_bits.old_meta.coh.state) - node T_1920 = or(UInt<1>("h00"), T_1917) - node T_1921 = or(T_1920, T_1918) - wire T_1923 : UInt<2>[3] - T_1923[0] <= UInt<1>("h01") - T_1923[1] <= UInt<2>("h02") - T_1923[2] <= UInt<2>("h03") - node T_1928 = eq(T_1923[0], io.req_bits.old_meta.coh.state) - node T_1929 = eq(T_1923[1], io.req_bits.old_meta.coh.state) - node T_1930 = eq(T_1923[2], io.req_bits.old_meta.coh.state) - node T_1932 = or(UInt<1>("h00"), T_1928) - node T_1933 = or(T_1932, T_1929) - node T_1934 = or(T_1933, T_1930) - node T_1935 = mux(T_1911, T_1921, T_1934) - when T_1935 : + node T_1890 = eq(io.req_bits.cmd, UInt<5>("h01")) + node T_1891 = eq(io.req_bits.cmd, UInt<5>("h07")) + node T_1892 = or(T_1890, T_1891) + node T_1893 = bits(io.req_bits.cmd, 3, 3) + node T_1894 = eq(io.req_bits.cmd, UInt<5>("h04")) + node T_1895 = or(T_1893, T_1894) + node T_1896 = or(T_1892, T_1895) + node T_1897 = eq(io.req_bits.cmd, UInt<5>("h03")) + node T_1898 = or(T_1896, T_1897) + node T_1899 = eq(io.req_bits.cmd, UInt<5>("h06")) + node T_1900 = or(T_1898, T_1899) + wire T_1902 : UInt<2>[2] + T_1902[0] <= UInt<2>("h02") + T_1902[1] <= UInt<2>("h03") + node T_1906 = eq(T_1902[0], io.req_bits.old_meta.coh.state) + node T_1907 = eq(T_1902[1], io.req_bits.old_meta.coh.state) + node T_1909 = or(UInt<1>("h00"), T_1906) + node T_1910 = or(T_1909, T_1907) + wire T_1912 : UInt<2>[3] + T_1912[0] <= UInt<1>("h01") + T_1912[1] <= UInt<2>("h02") + T_1912[2] <= UInt<2>("h03") + node T_1917 = eq(T_1912[0], io.req_bits.old_meta.coh.state) + node T_1918 = eq(T_1912[1], io.req_bits.old_meta.coh.state) + node T_1919 = eq(T_1912[2], io.req_bits.old_meta.coh.state) + node T_1921 = or(UInt<1>("h00"), T_1917) + node T_1922 = or(T_1921, T_1918) + node T_1923 = or(T_1922, T_1919) + node T_1924 = mux(T_1900, T_1910, T_1923) + when T_1924 : state <= UInt<3>("h06") new_coh_state <- coh_on_hit skip - node T_1937 = eq(T_1935, UInt<1>("h00")) - when T_1937 : + node T_1926 = eq(T_1924, UInt<1>("h00")) + when T_1926 : state <= UInt<3>("h04") skip skip - node T_1939 = eq(io.req_bits.tag_match, UInt<1>("h00")) - when T_1939 : - wire T_1941 : UInt<2>[1] - T_1941[0] <= UInt<2>("h03") - node T_1944 = eq(T_1941[0], io.req_bits.old_meta.coh.state) - node T_1946 = or(UInt<1>("h00"), T_1944) - node T_1947 = mux(T_1946, UInt<1>("h01"), UInt<2>("h03")) - state <= T_1947 + node T_1928 = eq(io.req_bits.tag_match, UInt<1>("h00")) + when T_1928 : + wire T_1930 : UInt<2>[1] + T_1930[0] <= UInt<2>("h03") + node T_1933 = eq(T_1930[0], io.req_bits.old_meta.coh.state) + node T_1935 = or(UInt<1>("h00"), T_1933) + node T_1936 = mux(T_1935, UInt<1>("h01"), UInt<2>("h03")) + state <= T_1936 skip skip - node T_1948 = neq(state, UInt<1>("h00")) - node T_1949 = and(T_1948, idx_match) - io.idx_match <= T_1949 + node T_1937 = neq(state, UInt<1>("h00")) + node T_1938 = and(T_1937, idx_match) + io.idx_match <= T_1938 io.refill.way_en <= req.way_en - node T_1950 = cat(req_idx, refill_cnt) - node T_1951 = shl(T_1950, 4) - io.refill.addr <= T_1951 - node T_1952 = shr(req.addr, 12) - io.tag <= T_1952 - node T_1953 = eq(state, UInt<1>("h00")) - io.req_pri_rdy <= T_1953 - node T_1954 = and(sec_rdy, rpq.io.enq.ready) - io.req_sec_rdy <= T_1954 - reg meta_hazard : UInt<2>, clk, reset, UInt<2>("h00") - node T_1958 = neq(meta_hazard, UInt<1>("h00")) - when T_1958 : - node T_1960 = addw(meta_hazard, UInt<1>("h01")) - meta_hazard <= T_1960 - skip - node T_1961 = and(io.meta_write.ready, io.meta_write.valid) - when T_1961 : + node T_1939 = cat(req_idx, refill_cnt) + node T_1940 = shl(T_1939, 4) + io.refill.addr <= T_1940 + node T_1941 = shr(req.addr, 12) + io.tag <= T_1941 + node T_1942 = eq(state, UInt<1>("h00")) + io.req_pri_rdy <= T_1942 + node T_1943 = and(sec_rdy, rpq.io.enq.ready) + io.req_sec_rdy <= T_1943 + reg meta_hazard : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + node T_1947 = neq(meta_hazard, UInt<1>("h00")) + when T_1947 : + node T_1949 = add(meta_hazard, UInt<1>("h01")) + node T_1950 = tail(T_1949, 1) + meta_hazard <= T_1950 + skip + node T_1951 = and(io.meta_write.ready, io.meta_write.valid) + when T_1951 : meta_hazard <= UInt<1>("h01") skip - node T_1964 = eq(idx_match, UInt<1>("h00")) - node T_1965 = eq(states_before_refill[0], state) - node T_1966 = eq(states_before_refill[1], state) - node T_1967 = eq(states_before_refill[2], state) - node T_1969 = or(UInt<1>("h00"), T_1965) - node T_1970 = or(T_1969, T_1966) - node T_1971 = or(T_1970, T_1967) - node T_1973 = eq(T_1971, UInt<1>("h00")) - node T_1975 = eq(meta_hazard, UInt<1>("h00")) - node T_1976 = and(T_1973, T_1975) - node T_1977 = or(T_1964, T_1976) - io.probe_rdy <= T_1977 - node T_1978 = eq(state, UInt<3>("h06")) - node T_1979 = eq(state, UInt<2>("h03")) - node T_1980 = or(T_1978, T_1979) - io.meta_write.valid <= T_1980 + node T_1954 = eq(idx_match, UInt<1>("h00")) + node T_1955 = eq(states_before_refill[0], state) + node T_1956 = eq(states_before_refill[1], state) + node T_1957 = eq(states_before_refill[2], state) + node T_1959 = or(UInt<1>("h00"), T_1955) + node T_1960 = or(T_1959, T_1956) + node T_1961 = or(T_1960, T_1957) + node T_1963 = eq(T_1961, UInt<1>("h00")) + node T_1965 = eq(meta_hazard, UInt<1>("h00")) + node T_1966 = and(T_1963, T_1965) + node T_1967 = or(T_1954, T_1966) + io.probe_rdy <= T_1967 + node T_1968 = eq(state, UInt<3>("h06")) + node T_1969 = eq(state, UInt<2>("h03")) + node T_1970 = or(T_1968, T_1969) + io.meta_write.valid <= T_1970 io.meta_write.bits.idx <= req_idx - node T_1981 = eq(state, UInt<2>("h03")) - wire T_1983 : UInt<2>[2] - T_1983[0] <= UInt<2>("h02") - T_1983[1] <= UInt<2>("h03") - node T_1987 = eq(T_1983[0], req.old_meta.coh.state) - node T_1988 = eq(T_1983[1], req.old_meta.coh.state) - node T_1990 = or(UInt<1>("h00"), T_1987) - node T_1991 = or(T_1990, T_1988) - node T_1992 = mux(T_1991, UInt<1>("h01"), req.old_meta.coh.state) - node T_1993 = eq(req.old_meta.coh.state, UInt<2>("h03")) - node T_1994 = mux(T_1993, UInt<2>("h02"), req.old_meta.coh.state) - node T_1995 = eq(UInt<5>("h013"), UInt<5>("h010")) - node T_1996 = mux(T_1995, T_1994, req.old_meta.coh.state) - node T_1997 = eq(UInt<5>("h011"), UInt<5>("h010")) - node T_1998 = mux(T_1997, T_1992, T_1996) - node T_1999 = eq(UInt<5>("h010"), UInt<5>("h010")) - node T_2000 = mux(T_1999, UInt<1>("h00"), T_1998) - wire T_2026 : {state : UInt<2>} - T_2026.state <= UInt<1>("h00") - T_2026.state <= T_2000 - wire T_2077 : {state : UInt<2>} - T_2077 <- new_coh_state - when T_1981 : - T_2077 <- T_2026 - skip - io.meta_write.bits.data.coh <- T_2077 + node T_1971 = eq(state, UInt<2>("h03")) + wire T_1973 : UInt<2>[2] + T_1973[0] <= UInt<2>("h02") + T_1973[1] <= UInt<2>("h03") + node T_1977 = eq(T_1973[0], req.old_meta.coh.state) + node T_1978 = eq(T_1973[1], req.old_meta.coh.state) + node T_1980 = or(UInt<1>("h00"), T_1977) + node T_1981 = or(T_1980, T_1978) + node T_1982 = mux(T_1981, UInt<1>("h01"), req.old_meta.coh.state) + node T_1983 = eq(req.old_meta.coh.state, UInt<2>("h03")) + node T_1984 = mux(T_1983, UInt<2>("h02"), req.old_meta.coh.state) + node T_1985 = eq(UInt<5>("h013"), UInt<5>("h010")) + node T_1986 = mux(T_1985, T_1984, req.old_meta.coh.state) + node T_1987 = eq(UInt<5>("h011"), UInt<5>("h010")) + node T_1988 = mux(T_1987, T_1982, T_1986) + node T_1989 = eq(UInt<5>("h010"), UInt<5>("h010")) + node T_1990 = mux(T_1989, UInt<1>("h00"), T_1988) + wire T_2016 : {state : UInt<2>} + T_2016 is invalid + T_2016.state <= T_1990 + node T_2041 = mux(T_1971, T_2016, new_coh_state) + io.meta_write.bits.data.coh <- T_2041 io.meta_write.bits.data.tag <= io.tag io.meta_write.bits.way_en <= req.way_en - node T_2102 = eq(state, UInt<1>("h01")) - io.wb_req.valid <= T_2102 - node T_2104 = cat(req.old_meta.tag, req_idx) - wire T_2109 : UInt<2>[1] - T_2109[0] <= UInt<2>("h03") - node T_2112 = eq(T_2109[0], req.old_meta.coh.state) - node T_2114 = or(UInt<1>("h00"), T_2112) - node T_2115 = mux(T_2114, UInt<1>("h00"), UInt<2>("h03")) - node T_2116 = mux(T_2114, UInt<1>("h01"), UInt<3>("h04")) - node T_2117 = mux(T_2114, UInt<2>("h02"), UInt<3>("h05")) - node T_2118 = eq(UInt<5>("h013"), UInt<5>("h010")) - node T_2119 = mux(T_2118, T_2117, UInt<3>("h05")) - node T_2120 = eq(UInt<5>("h011"), UInt<5>("h010")) - node T_2121 = mux(T_2120, T_2116, T_2119) - node T_2122 = eq(UInt<5>("h010"), UInt<5>("h010")) - node T_2123 = mux(T_2122, T_2115, T_2121) - wire T_2154 : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>} - T_2154.data <= UInt<1>("h00") - T_2154.r_type <= UInt<1>("h00") - T_2154.voluntary <= UInt<1>("h00") - T_2154.client_xact_id <= UInt<1>("h00") - T_2154.addr_block <= UInt<1>("h00") - T_2154.addr_beat <= UInt<1>("h00") - T_2154.r_type <= T_2123 - T_2154.client_xact_id <= UInt<1>("h01") - T_2154.addr_block <= T_2104 - T_2154.addr_beat <= UInt<1>("h00") - T_2154.data <= UInt<1>("h00") - T_2154.voluntary <= UInt<1>("h01") - io.wb_req.bits <- T_2154 + node T_2066 = eq(state, UInt<1>("h01")) + io.wb_req.valid <= T_2066 + node T_2068 = cat(req.old_meta.tag, req_idx) + wire T_2073 : UInt<2>[1] + T_2073[0] <= UInt<2>("h03") + node T_2076 = eq(T_2073[0], req.old_meta.coh.state) + node T_2078 = or(UInt<1>("h00"), T_2076) + node T_2079 = mux(T_2078, UInt<1>("h00"), UInt<2>("h03")) + node T_2080 = mux(T_2078, UInt<1>("h01"), UInt<3>("h04")) + node T_2081 = mux(T_2078, UInt<2>("h02"), UInt<3>("h05")) + node T_2082 = eq(UInt<5>("h013"), UInt<5>("h010")) + node T_2083 = mux(T_2082, T_2081, UInt<3>("h05")) + node T_2084 = eq(UInt<5>("h011"), UInt<5>("h010")) + node T_2085 = mux(T_2084, T_2080, T_2083) + node T_2086 = eq(UInt<5>("h010"), UInt<5>("h010")) + node T_2087 = mux(T_2086, T_2079, T_2085) + wire T_2118 : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>} + T_2118 is invalid + T_2118.r_type <= T_2087 + T_2118.client_xact_id <= UInt<1>("h01") + T_2118.addr_block <= T_2068 + T_2118.addr_beat <= UInt<1>("h00") + T_2118.data <= UInt<1>("h00") + T_2118.voluntary <= UInt<1>("h01") + io.wb_req.bits <- T_2118 io.wb_req.bits.way_en <= req.way_en - node T_2190 = eq(state, UInt<3>("h04")) - io.mem_req.valid <= T_2190 - node T_2191 = cat(io.tag, req_idx) - node T_2194 = eq(req.cmd, UInt<5>("h01")) - node T_2195 = eq(req.cmd, UInt<5>("h07")) - node T_2196 = or(T_2194, T_2195) - node T_2197 = bit(req.cmd, 3) - node T_2198 = eq(req.cmd, UInt<5>("h04")) - node T_2199 = or(T_2197, T_2198) - node T_2200 = or(T_2196, T_2199) - node T_2201 = eq(req.cmd, UInt<5>("h03")) - node T_2202 = or(T_2200, T_2201) - node T_2203 = eq(req.cmd, UInt<5>("h06")) - node T_2204 = or(T_2202, T_2203) - node T_2205 = mux(T_2204, UInt<1>("h01"), UInt<1>("h00")) - node T_2207 = cat(req.cmd, UInt<1>("h01")) - wire T_2241 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_2241.data <= UInt<1>("h00") - T_2241.union <= UInt<1>("h00") - T_2241.a_type <= UInt<1>("h00") - T_2241.is_builtin_type <= UInt<1>("h00") - T_2241.addr_beat <= UInt<1>("h00") - T_2241.client_xact_id <= UInt<1>("h00") - T_2241.addr_block <= UInt<1>("h00") - T_2241.is_builtin_type <= UInt<1>("h00") - T_2241.a_type <= T_2205 - T_2241.client_xact_id <= UInt<1>("h01") - T_2241.addr_block <= T_2191 - T_2241.addr_beat <= UInt<1>("h00") - T_2241.data <= UInt<1>("h00") - T_2241.union <= T_2207 - io.mem_req.bits <- T_2241 - node T_2279 = eq(state, UInt<4>("h08")) - io.meta_read.valid <= T_2279 + node T_2148 = eq(state, UInt<3>("h04")) + io.mem_req.valid <= T_2148 + node T_2149 = cat(io.tag, req_idx) + node T_2152 = eq(req.cmd, UInt<5>("h01")) + node T_2153 = eq(req.cmd, UInt<5>("h07")) + node T_2154 = or(T_2152, T_2153) + node T_2155 = bits(req.cmd, 3, 3) + node T_2156 = eq(req.cmd, UInt<5>("h04")) + node T_2157 = or(T_2155, T_2156) + node T_2158 = or(T_2154, T_2157) + node T_2159 = eq(req.cmd, UInt<5>("h03")) + node T_2160 = or(T_2158, T_2159) + node T_2161 = eq(req.cmd, UInt<5>("h06")) + node T_2162 = or(T_2160, T_2161) + node T_2163 = mux(T_2162, UInt<1>("h01"), UInt<1>("h00")) + node T_2165 = cat(req.cmd, UInt<1>("h01")) + wire T_2199 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} + T_2199 is invalid + T_2199.is_builtin_type <= UInt<1>("h00") + T_2199.a_type <= T_2163 + T_2199.client_xact_id <= UInt<1>("h01") + T_2199.addr_block <= T_2149 + T_2199.addr_beat <= UInt<1>("h00") + T_2199.data <= UInt<1>("h00") + T_2199.union <= T_2165 + io.mem_req.bits <- T_2199 + node T_2230 = eq(state, UInt<4>("h08")) + io.meta_read.valid <= T_2230 io.meta_read.bits.idx <= req_idx io.meta_read.bits.tag <= io.tag - node T_2280 = eq(state, UInt<4>("h08")) - node T_2281 = and(T_2280, rpq.io.deq.valid) - io.replay.valid <= T_2281 + node T_2231 = eq(state, UInt<4>("h08")) + node T_2232 = and(T_2231, rpq.io.deq.valid) + io.replay.valid <= T_2232 io.replay.bits <- rpq.io.deq.bits io.replay.bits.phys <= UInt<1>("h01") - node T_2283 = bits(rpq.io.deq.bits.addr, 5, 0) - node T_2284 = cat(req_idx, T_2283) - node T_2285 = cat(io.tag, T_2284) - io.replay.bits.addr <= T_2285 - node T_2287 = eq(io.meta_read.ready, UInt<1>("h00")) - when T_2287 : + node T_2234 = bits(rpq.io.deq.bits.addr, 5, 0) + node T_2235 = cat(req_idx, T_2234) + node T_2236 = cat(io.tag, T_2235) + io.replay.bits.addr <= T_2236 + node T_2238 = eq(io.meta_read.ready, UInt<1>("h00")) + when T_2238 : rpq.io.deq.ready <= UInt<1>("h00") io.replay.bits.cmd <= UInt<5>("h05") skip @@ -30522,109 +23388,75 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}[1], out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<1>}, chosen : UInt<1>} - io.chosen <= UInt<1>("h00") - io.out.bits <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") + io is invalid wire T_54 : UInt<1> - T_54 <= UInt<1>("h00") + T_54 is invalid io.out.valid <= io.in[T_54].valid io.out.bits <= io.in[T_54].bits io.chosen <= T_54 io.in[T_54].ready <= UInt<1>("h00") - node T_74 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_75 = mux(UInt<1>("h00"), T_74, UInt<1>("h01")) - node T_76 = and(T_75, io.out.ready) - io.in[0].ready <= T_76 - node T_78 = mux(UInt<1>("h00"), UInt<1>("h00"), UInt<1>("h00")) - T_54 <= T_78 + node T_73 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_74 = mux(UInt<1>("h00"), T_73, UInt<1>("h01")) + node T_75 = and(T_74, io.out.ready) + io.in[0].ready <= T_75 + node T_77 = mux(UInt<1>("h00"), UInt<1>("h00"), UInt<1>("h00")) + T_54 <= T_77 module Arbiter_102 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}[1], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, chosen : UInt<1>} - io.chosen <= UInt<1>("h00") - io.out.bits.store_data <= UInt<1>("h00") - io.out.bits.data_word_bypass <= UInt<1>("h00") - io.out.bits.has_data <= UInt<1>("h00") - io.out.bits.replay <= UInt<1>("h00") - io.out.bits.nack <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.bits.typ <= UInt<1>("h00") - io.out.bits.cmd <= UInt<1>("h00") - io.out.bits.tag <= UInt<1>("h00") - io.out.bits.addr <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") + io is invalid wire T_1062 : UInt<1> - T_1062 <= UInt<1>("h00") + T_1062 is invalid io.out.valid <= io.in[T_1062].valid io.out.bits <- io.in[T_1062].bits io.chosen <= T_1062 io.in[T_1062].ready <= UInt<1>("h00") - node T_1418 = eq(UInt<1>("h00"), UInt<1>("h00")) - node T_1419 = mux(UInt<1>("h00"), T_1418, UInt<1>("h01")) - node T_1420 = and(T_1419, io.out.ready) - io.in[0].ready <= T_1420 - node T_1422 = mux(UInt<1>("h00"), UInt<1>("h00"), UInt<1>("h00")) - T_1062 <= T_1422 + node T_1417 = eq(UInt<1>("h00"), UInt<1>("h00")) + node T_1418 = mux(UInt<1>("h00"), T_1417, UInt<1>("h01")) + node T_1419 = and(T_1418, io.out.ready) + io.in[0].ready <= T_1419 + node T_1421 = mux(UInt<1>("h00"), UInt<1>("h00"), UInt<1>("h00")) + T_1062 <= T_1421 module IOMSHR : input clk : Clock input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}} - io.resp.bits.store_data <= UInt<1>("h00") - io.resp.bits.data_word_bypass <= UInt<1>("h00") - io.resp.bits.has_data <= UInt<1>("h00") - io.resp.bits.replay <= UInt<1>("h00") - io.resp.bits.nack <= UInt<1>("h00") - io.resp.bits.data <= UInt<1>("h00") - io.resp.bits.typ <= UInt<1>("h00") - io.resp.bits.cmd <= UInt<1>("h00") - io.resp.bits.tag <= UInt<1>("h00") - io.resp.bits.addr <= UInt<1>("h00") - io.resp.valid <= UInt<1>("h00") - io.acquire.bits.data <= UInt<1>("h00") - io.acquire.bits.union <= UInt<1>("h00") - io.acquire.bits.a_type <= UInt<1>("h00") - io.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.acquire.bits.addr_beat <= UInt<1>("h00") - io.acquire.bits.client_xact_id <= UInt<1>("h00") - io.acquire.bits.addr_block <= UInt<1>("h00") - io.acquire.valid <= UInt<1>("h00") - io.req.ready <= UInt<1>("h00") - reg req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk, UInt<1>("h00"), req + io is invalid + reg req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk node req_cmd_sc = eq(req.cmd, UInt<5>("h07")) - reg grant_word : UInt<64>, clk, UInt<1>("h00"), grant_word + reg grant_word : UInt<64>, clk node T_861 = bits(req.typ, 1, 0) node T_862 = bits(req.typ, 1, 0) node T_863 = asSInt(req.typ) node T_865 = geq(T_863, asSInt(UInt<1>("h00"))) node beat_offset = bits(req.addr, 3, 3) - node T_868 = bit(req.addr, 0) + node T_868 = bits(req.addr, 0, 0) node T_870 = mux(T_868, UInt<1>("h01"), UInt<1>("h00")) node T_872 = geq(T_861, UInt<1>("h01")) node T_875 = mux(T_872, UInt<1>("h01"), UInt<1>("h00")) node T_876 = or(T_870, T_875) - node T_877 = bit(req.addr, 0) + node T_877 = bits(req.addr, 0, 0) node T_879 = mux(T_877, UInt<1>("h00"), UInt<1>("h01")) node T_880 = cat(T_876, T_879) - node T_881 = bit(req.addr, 1) + node T_881 = bits(req.addr, 1, 1) node T_883 = mux(T_881, T_880, UInt<1>("h00")) node T_885 = geq(T_861, UInt<2>("h02")) node T_888 = mux(T_885, UInt<2>("h03"), UInt<1>("h00")) node T_889 = or(T_883, T_888) - node T_890 = bit(req.addr, 1) + node T_890 = bits(req.addr, 1, 1) node T_892 = mux(T_890, UInt<1>("h00"), T_880) node T_893 = cat(T_889, T_892) - node T_894 = bit(req.addr, 2) + node T_894 = bits(req.addr, 2, 2) node T_896 = mux(T_894, T_893, UInt<1>("h00")) node T_898 = geq(T_861, UInt<2>("h03")) node T_901 = mux(T_898, UInt<4>("h0f"), UInt<1>("h00")) node T_902 = or(T_896, T_901) - node T_903 = bit(req.addr, 2) + node T_903 = bits(req.addr, 2, 2) node T_905 = mux(T_903, UInt<1>("h00"), T_893) node T_906 = cat(T_902, T_905) node T_908 = cat(beat_offset, UInt<3>("h00")) @@ -30645,7 +23477,7 @@ circuit Top : node T_926 = mux(T_917, T_920, T_925) node T_927 = mux(T_911, T_915, T_926) node beat_data = cat(T_927, T_927) - reg state : UInt<?>, clk, reset, UInt<1>("h00") + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) node T_935 = eq(state, UInt<1>("h00")) io.req.ready <= T_935 node addr_block = bits(req.addr, 31, 6) @@ -30678,13 +23510,7 @@ circuit Top : node T_977 = eq(UInt<3>("h00"), UInt<3>("h00")) node T_978 = mux(T_977, T_949, T_976) wire get_acquire : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - get_acquire.data <= UInt<1>("h00") - get_acquire.union <= UInt<1>("h00") - get_acquire.a_type <= UInt<1>("h00") - get_acquire.is_builtin_type <= UInt<1>("h00") - get_acquire.addr_beat <= UInt<1>("h00") - get_acquire.client_xact_id <= UInt<1>("h00") - get_acquire.addr_block <= UInt<1>("h00") + get_acquire is invalid get_acquire.is_builtin_type <= UInt<1>("h01") get_acquire.a_type <= UInt<3>("h00") get_acquire.client_xact_id <= UInt<2>("h02") @@ -30692,160 +23518,153 @@ circuit Top : get_acquire.addr_beat <= addr_beat get_acquire.data <= UInt<1>("h00") get_acquire.union <= T_978 - node T_1056 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1057 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_1058 = cat(T_1056, T_1057) - node T_1060 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_1061 = cat(UInt<3>("h07"), T_1060) - node T_1063 = cat(beat_mask, UInt<1>("h00")) - node T_1065 = cat(beat_mask, UInt<1>("h00")) - node T_1067 = cat(UInt<1>("h00"), UInt<3>("h07")) - node T_1068 = cat(UInt<1>("h00"), UInt<1>("h00")) - node T_1069 = cat(T_1067, T_1068) - node T_1071 = cat(UInt<5>("h00"), UInt<1>("h00")) - node T_1073 = cat(UInt<5>("h01"), UInt<1>("h00")) - node T_1074 = eq(UInt<3>("h06"), UInt<3>("h02")) - node T_1075 = mux(T_1074, T_1073, UInt<1>("h00")) - node T_1076 = eq(UInt<3>("h05"), UInt<3>("h02")) - node T_1077 = mux(T_1076, T_1071, T_1075) - node T_1078 = eq(UInt<3>("h04"), UInt<3>("h02")) - node T_1079 = mux(T_1078, T_1069, T_1077) - node T_1080 = eq(UInt<3>("h03"), UInt<3>("h02")) - node T_1081 = mux(T_1080, T_1065, T_1079) - node T_1082 = eq(UInt<3>("h02"), UInt<3>("h02")) - node T_1083 = mux(T_1082, T_1063, T_1081) - node T_1084 = eq(UInt<3>("h01"), UInt<3>("h02")) - node T_1085 = mux(T_1084, T_1061, T_1083) - node T_1086 = eq(UInt<3>("h00"), UInt<3>("h02")) - node T_1087 = mux(T_1086, T_1058, T_1085) + node T_1049 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_1050 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_1051 = cat(T_1049, T_1050) + node T_1053 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_1054 = cat(UInt<3>("h07"), T_1053) + node T_1056 = cat(beat_mask, UInt<1>("h00")) + node T_1058 = cat(beat_mask, UInt<1>("h00")) + node T_1060 = cat(UInt<1>("h00"), UInt<3>("h07")) + node T_1061 = cat(UInt<1>("h00"), UInt<1>("h00")) + node T_1062 = cat(T_1060, T_1061) + node T_1064 = cat(UInt<5>("h00"), UInt<1>("h00")) + node T_1066 = cat(UInt<5>("h01"), UInt<1>("h00")) + node T_1067 = eq(UInt<3>("h06"), UInt<3>("h02")) + node T_1068 = mux(T_1067, T_1066, UInt<1>("h00")) + node T_1069 = eq(UInt<3>("h05"), UInt<3>("h02")) + node T_1070 = mux(T_1069, T_1064, T_1068) + node T_1071 = eq(UInt<3>("h04"), UInt<3>("h02")) + node T_1072 = mux(T_1071, T_1062, T_1070) + node T_1073 = eq(UInt<3>("h03"), UInt<3>("h02")) + node T_1074 = mux(T_1073, T_1058, T_1072) + node T_1075 = eq(UInt<3>("h02"), UInt<3>("h02")) + node T_1076 = mux(T_1075, T_1056, T_1074) + node T_1077 = eq(UInt<3>("h01"), UInt<3>("h02")) + node T_1078 = mux(T_1077, T_1054, T_1076) + node T_1079 = eq(UInt<3>("h00"), UInt<3>("h02")) + node T_1080 = mux(T_1079, T_1051, T_1078) wire put_acquire : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - put_acquire.data <= UInt<1>("h00") - put_acquire.union <= UInt<1>("h00") - put_acquire.a_type <= UInt<1>("h00") - put_acquire.is_builtin_type <= UInt<1>("h00") - put_acquire.addr_beat <= UInt<1>("h00") - put_acquire.client_xact_id <= UInt<1>("h00") - put_acquire.addr_block <= UInt<1>("h00") + put_acquire is invalid put_acquire.is_builtin_type <= UInt<1>("h01") put_acquire.a_type <= UInt<3>("h02") put_acquire.client_xact_id <= UInt<2>("h02") put_acquire.addr_block <= addr_block put_acquire.addr_beat <= addr_beat put_acquire.data <= beat_data - put_acquire.union <= T_1087 - node T_1157 = eq(state, UInt<1>("h01")) - io.acquire.valid <= T_1157 - node T_1158 = eq(req.cmd, UInt<5>("h00")) - node T_1159 = eq(req.cmd, UInt<5>("h06")) - node T_1160 = or(T_1158, T_1159) - node T_1161 = eq(req.cmd, UInt<5>("h07")) - node T_1162 = or(T_1160, T_1161) - node T_1163 = bit(req.cmd, 3) - node T_1164 = eq(req.cmd, UInt<5>("h04")) - node T_1165 = or(T_1163, T_1164) - node T_1166 = or(T_1162, T_1165) - wire T_1198 : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>} - T_1198 <- put_acquire - when T_1166 : - T_1198 <- get_acquire - skip - io.acquire.bits <- T_1198 - node T_1229 = eq(state, UInt<2>("h03")) - io.resp.valid <= T_1229 + put_acquire.union <= T_1080 + node T_1143 = eq(state, UInt<1>("h01")) + io.acquire.valid <= T_1143 + node T_1144 = eq(req.cmd, UInt<5>("h00")) + node T_1145 = eq(req.cmd, UInt<5>("h06")) + node T_1146 = or(T_1144, T_1145) + node T_1147 = eq(req.cmd, UInt<5>("h07")) + node T_1148 = or(T_1146, T_1147) + node T_1149 = bits(req.cmd, 3, 3) + node T_1150 = eq(req.cmd, UInt<5>("h04")) + node T_1151 = or(T_1149, T_1150) + node T_1152 = or(T_1148, T_1151) + node T_1153 = mux(T_1152, get_acquire, put_acquire) + io.acquire.bits <- T_1153 + node T_1184 = eq(state, UInt<2>("h03")) + io.resp.valid <= T_1184 io.resp.bits <- req - node T_1230 = eq(req.cmd, UInt<5>("h00")) - node T_1231 = eq(req.cmd, UInt<5>("h06")) - node T_1232 = or(T_1230, T_1231) - node T_1233 = eq(req.cmd, UInt<5>("h07")) - node T_1234 = or(T_1232, T_1233) - node T_1235 = bit(req.cmd, 3) - node T_1236 = eq(req.cmd, UInt<5>("h04")) - node T_1237 = or(T_1235, T_1236) - node T_1238 = or(T_1234, T_1237) - io.resp.bits.has_data <= T_1238 - node T_1239 = bit(req.addr, 2) - node T_1240 = bits(grant_word, 63, 32) - node T_1241 = bits(grant_word, 31, 0) - node T_1242 = mux(T_1239, T_1240, T_1241) - node T_1244 = and(UInt<1>("h00"), req_cmd_sc) - node T_1246 = mux(T_1244, UInt<1>("h00"), T_1242) - node T_1248 = eq(T_862, UInt<2>("h02")) - node T_1249 = or(T_1248, T_1244) - node T_1250 = bit(T_1246, 31) - node T_1251 = and(T_865, T_1250) - node T_1253 = subw(UInt<32>("h00"), T_1251) - node T_1254 = bits(grant_word, 63, 32) - node T_1255 = mux(T_1249, T_1253, T_1254) - node T_1256 = cat(T_1255, T_1246) - node T_1257 = bit(req.addr, 1) - node T_1258 = bits(T_1256, 31, 16) - node T_1259 = bits(T_1256, 15, 0) - node T_1260 = mux(T_1257, T_1258, T_1259) - node T_1262 = and(UInt<1>("h00"), req_cmd_sc) - node T_1264 = mux(T_1262, UInt<1>("h00"), T_1260) - node T_1266 = eq(T_862, UInt<1>("h01")) - node T_1267 = or(T_1266, T_1262) - node T_1268 = bit(T_1264, 15) - node T_1269 = and(T_865, T_1268) - node T_1271 = subw(UInt<48>("h00"), T_1269) - node T_1272 = bits(T_1256, 63, 16) - node T_1273 = mux(T_1267, T_1271, T_1272) - node T_1274 = cat(T_1273, T_1264) - node T_1275 = bit(req.addr, 0) - node T_1276 = bits(T_1274, 15, 8) - node T_1277 = bits(T_1274, 7, 0) - node T_1278 = mux(T_1275, T_1276, T_1277) - node T_1280 = and(UInt<1>("h01"), req_cmd_sc) - node T_1282 = mux(T_1280, UInt<1>("h00"), T_1278) - node T_1284 = eq(T_862, UInt<1>("h00")) - node T_1285 = or(T_1284, T_1280) - node T_1286 = bit(T_1282, 7) - node T_1287 = and(T_865, T_1286) - node T_1289 = subw(UInt<56>("h00"), T_1287) - node T_1290 = bits(T_1274, 63, 8) - node T_1291 = mux(T_1285, T_1289, T_1290) - node T_1292 = cat(T_1291, T_1282) - node T_1293 = or(T_1292, req_cmd_sc) - io.resp.bits.data <= T_1293 + node T_1185 = eq(req.cmd, UInt<5>("h00")) + node T_1186 = eq(req.cmd, UInt<5>("h06")) + node T_1187 = or(T_1185, T_1186) + node T_1188 = eq(req.cmd, UInt<5>("h07")) + node T_1189 = or(T_1187, T_1188) + node T_1190 = bits(req.cmd, 3, 3) + node T_1191 = eq(req.cmd, UInt<5>("h04")) + node T_1192 = or(T_1190, T_1191) + node T_1193 = or(T_1189, T_1192) + io.resp.bits.has_data <= T_1193 + node T_1194 = bits(req.addr, 2, 2) + node T_1195 = bits(grant_word, 63, 32) + node T_1196 = bits(grant_word, 31, 0) + node T_1197 = mux(T_1194, T_1195, T_1196) + node T_1199 = and(UInt<1>("h00"), req_cmd_sc) + node T_1201 = mux(T_1199, UInt<1>("h00"), T_1197) + node T_1203 = eq(T_862, UInt<2>("h02")) + node T_1204 = or(T_1203, T_1199) + node T_1205 = bits(T_1201, 31, 31) + node T_1206 = and(T_865, T_1205) + node T_1208 = sub(UInt<32>("h00"), T_1206) + node T_1209 = tail(T_1208, 1) + node T_1210 = bits(grant_word, 63, 32) + node T_1211 = mux(T_1204, T_1209, T_1210) + node T_1212 = cat(T_1211, T_1201) + node T_1213 = bits(req.addr, 1, 1) + node T_1214 = bits(T_1212, 31, 16) + node T_1215 = bits(T_1212, 15, 0) + node T_1216 = mux(T_1213, T_1214, T_1215) + node T_1218 = and(UInt<1>("h00"), req_cmd_sc) + node T_1220 = mux(T_1218, UInt<1>("h00"), T_1216) + node T_1222 = eq(T_862, UInt<1>("h01")) + node T_1223 = or(T_1222, T_1218) + node T_1224 = bits(T_1220, 15, 15) + node T_1225 = and(T_865, T_1224) + node T_1227 = sub(UInt<48>("h00"), T_1225) + node T_1228 = tail(T_1227, 1) + node T_1229 = bits(T_1212, 63, 16) + node T_1230 = mux(T_1223, T_1228, T_1229) + node T_1231 = cat(T_1230, T_1220) + node T_1232 = bits(req.addr, 0, 0) + node T_1233 = bits(T_1231, 15, 8) + node T_1234 = bits(T_1231, 7, 0) + node T_1235 = mux(T_1232, T_1233, T_1234) + node T_1237 = and(UInt<1>("h01"), req_cmd_sc) + node T_1239 = mux(T_1237, UInt<1>("h00"), T_1235) + node T_1241 = eq(T_862, UInt<1>("h00")) + node T_1242 = or(T_1241, T_1237) + node T_1243 = bits(T_1239, 7, 7) + node T_1244 = and(T_865, T_1243) + node T_1246 = sub(UInt<56>("h00"), T_1244) + node T_1247 = tail(T_1246, 1) + node T_1248 = bits(T_1231, 63, 8) + node T_1249 = mux(T_1242, T_1247, T_1248) + node T_1250 = cat(T_1249, T_1239) + node T_1251 = or(T_1250, req_cmd_sc) + io.resp.bits.data <= T_1251 io.resp.bits.store_data <= req.data io.resp.bits.nack <= UInt<1>("h00") io.resp.bits.replay <= io.resp.valid - node T_1295 = and(io.req.ready, io.req.valid) - when T_1295 : + node T_1253 = and(io.req.ready, io.req.valid) + when T_1253 : req <- io.req.bits state <= UInt<1>("h01") skip - node T_1296 = and(io.acquire.ready, io.acquire.valid) - when T_1296 : + node T_1254 = and(io.acquire.ready, io.acquire.valid) + when T_1254 : state <= UInt<2>("h02") skip - node T_1297 = eq(state, UInt<2>("h02")) - node T_1298 = and(T_1297, io.grant.valid) - when T_1298 : - node T_1299 = eq(req.cmd, UInt<5>("h00")) - node T_1300 = eq(req.cmd, UInt<5>("h06")) - node T_1301 = or(T_1299, T_1300) - node T_1302 = eq(req.cmd, UInt<5>("h07")) - node T_1303 = or(T_1301, T_1302) - node T_1304 = bit(req.cmd, 3) - node T_1305 = eq(req.cmd, UInt<5>("h04")) - node T_1306 = or(T_1304, T_1305) - node T_1307 = or(T_1303, T_1306) - when T_1307 : - node T_1308 = bits(req.addr, 3, 3) - node T_1310 = cat(T_1308, UInt<6>("h00")) - node T_1311 = dshr(io.grant.bits.data, T_1310) - node T_1312 = bits(T_1311, 63, 0) - grant_word <= T_1312 + node T_1255 = eq(state, UInt<2>("h02")) + node T_1256 = and(T_1255, io.grant.valid) + when T_1256 : + node T_1257 = eq(req.cmd, UInt<5>("h00")) + node T_1258 = eq(req.cmd, UInt<5>("h06")) + node T_1259 = or(T_1257, T_1258) + node T_1260 = eq(req.cmd, UInt<5>("h07")) + node T_1261 = or(T_1259, T_1260) + node T_1262 = bits(req.cmd, 3, 3) + node T_1263 = eq(req.cmd, UInt<5>("h04")) + node T_1264 = or(T_1262, T_1263) + node T_1265 = or(T_1261, T_1264) + when T_1265 : + node T_1266 = bits(req.addr, 3, 3) + node T_1268 = cat(T_1266, UInt<6>("h00")) + node T_1269 = dshr(io.grant.bits.data, T_1268) + node T_1270 = bits(T_1269, 63, 0) + grant_word <= T_1270 state <= UInt<2>("h03") skip - node T_1314 = eq(T_1307, UInt<1>("h00")) - when T_1314 : + node T_1272 = eq(T_1265, UInt<1>("h00")) + when T_1272 : state <= UInt<1>("h00") skip skip - node T_1315 = and(io.resp.ready, io.resp.valid) - when T_1315 : + node T_1273 = and(io.resp.ready, io.resp.valid) + when T_1273 : state <= UInt<1>("h00") skip @@ -30854,76 +23673,28 @@ circuit Top : input reset : UInt<1> output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, secondary_miss : UInt<1>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>, fence_rdy : UInt<1>} - io.fence_rdy <= UInt<1>("h00") - io.probe_rdy <= UInt<1>("h00") - io.wb_req.bits.way_en <= UInt<1>("h00") - io.wb_req.bits.data <= UInt<1>("h00") - io.wb_req.bits.r_type <= UInt<1>("h00") - io.wb_req.bits.voluntary <= UInt<1>("h00") - io.wb_req.bits.client_xact_id <= UInt<1>("h00") - io.wb_req.bits.addr_block <= UInt<1>("h00") - io.wb_req.bits.addr_beat <= UInt<1>("h00") - io.wb_req.valid <= UInt<1>("h00") - io.replay.bits.data <= UInt<1>("h00") - io.replay.bits.phys <= UInt<1>("h00") - io.replay.bits.kill <= UInt<1>("h00") - io.replay.bits.typ <= UInt<1>("h00") - io.replay.bits.cmd <= UInt<1>("h00") - io.replay.bits.tag <= UInt<1>("h00") - io.replay.bits.addr <= UInt<1>("h00") - io.replay.valid <= UInt<1>("h00") - io.meta_write.bits.data.coh.state <= UInt<1>("h00") - io.meta_write.bits.data.tag <= UInt<1>("h00") - io.meta_write.bits.way_en <= UInt<1>("h00") - io.meta_write.bits.idx <= UInt<1>("h00") - io.meta_write.valid <= UInt<1>("h00") - io.meta_read.bits.tag <= UInt<1>("h00") - io.meta_read.bits.idx <= UInt<1>("h00") - io.meta_read.valid <= UInt<1>("h00") - io.refill.addr <= UInt<1>("h00") - io.refill.way_en <= UInt<1>("h00") - io.mem_req.bits.data <= UInt<1>("h00") - io.mem_req.bits.union <= UInt<1>("h00") - io.mem_req.bits.a_type <= UInt<1>("h00") - io.mem_req.bits.is_builtin_type <= UInt<1>("h00") - io.mem_req.bits.addr_beat <= UInt<1>("h00") - io.mem_req.bits.client_xact_id <= UInt<1>("h00") - io.mem_req.bits.addr_block <= UInt<1>("h00") - io.mem_req.valid <= UInt<1>("h00") - io.secondary_miss <= UInt<1>("h00") - io.resp.bits.store_data <= UInt<1>("h00") - io.resp.bits.data_word_bypass <= UInt<1>("h00") - io.resp.bits.has_data <= UInt<1>("h00") - io.resp.bits.replay <= UInt<1>("h00") - io.resp.bits.nack <= UInt<1>("h00") - io.resp.bits.data <= UInt<1>("h00") - io.resp.bits.typ <= UInt<1>("h00") - io.resp.bits.cmd <= UInt<1>("h00") - io.resp.bits.tag <= UInt<1>("h00") - io.resp.bits.addr <= UInt<1>("h00") - io.resp.valid <= UInt<1>("h00") - io.req.ready <= UInt<1>("h00") + io is invalid node cacheable = lt(io.req.bits.addr, UInt<31>("h040000000")) - reg sdq_val : UInt<17>, clk, reset, UInt<17>("h00") + reg sdq_val : UInt<17>, clk with : (reset => (reset, UInt<17>("h00"))) node T_1807 = bits(sdq_val, 16, 0) node T_1808 = not(T_1807) - node T_1809 = bit(T_1808, 0) - node T_1810 = bit(T_1808, 1) - node T_1811 = bit(T_1808, 2) - node T_1812 = bit(T_1808, 3) - node T_1813 = bit(T_1808, 4) - node T_1814 = bit(T_1808, 5) - node T_1815 = bit(T_1808, 6) - node T_1816 = bit(T_1808, 7) - node T_1817 = bit(T_1808, 8) - node T_1818 = bit(T_1808, 9) - node T_1819 = bit(T_1808, 10) - node T_1820 = bit(T_1808, 11) - node T_1821 = bit(T_1808, 12) - node T_1822 = bit(T_1808, 13) - node T_1823 = bit(T_1808, 14) - node T_1824 = bit(T_1808, 15) - node T_1825 = bit(T_1808, 16) + node T_1809 = bits(T_1808, 0, 0) + node T_1810 = bits(T_1808, 1, 1) + node T_1811 = bits(T_1808, 2, 2) + node T_1812 = bits(T_1808, 3, 3) + node T_1813 = bits(T_1808, 4, 4) + node T_1814 = bits(T_1808, 5, 5) + node T_1815 = bits(T_1808, 6, 6) + node T_1816 = bits(T_1808, 7, 7) + node T_1817 = bits(T_1808, 8, 8) + node T_1818 = bits(T_1808, 9, 9) + node T_1819 = bits(T_1808, 10, 10) + node T_1820 = bits(T_1808, 11, 11) + node T_1821 = bits(T_1808, 12, 12) + node T_1822 = bits(T_1808, 13, 13) + node T_1823 = bits(T_1808, 14, 14) + node T_1824 = bits(T_1808, 15, 15) + node T_1825 = bits(T_1808, 16, 16) wire T_1827 : UInt<1>[17] T_1827[0] <= T_1809 T_1827[1] <= T_1810 @@ -30966,7 +23737,7 @@ circuit Top : node T_1886 = eq(io.req.bits.cmd, UInt<5>("h01")) node T_1887 = eq(io.req.bits.cmd, UInt<5>("h07")) node T_1888 = or(T_1886, T_1887) - node T_1889 = bit(io.req.bits.cmd, 3) + node T_1889 = bits(io.req.bits.cmd, 3, 3) node T_1890 = eq(io.req.bits.cmd, UInt<5>("h04")) node T_1891 = or(T_1889, T_1890) node T_1892 = or(T_1888, T_1891) @@ -30977,406 +23748,249 @@ circuit Top : T_1896 <= io.req.bits.data skip wire idxMatch : UInt<1>[2] - idxMatch[0] <= UInt<1>("h00") - idxMatch[1] <= UInt<1>("h00") + idxMatch is invalid wire tagList : UInt<20>[2] - tagList[0] <= UInt<1>("h00") - tagList[1] <= UInt<1>("h00") - node T_1926 = mux(idxMatch[0], tagList[0], UInt<1>("h00")) - node T_1928 = mux(idxMatch[1], tagList[1], UInt<1>("h00")) - node T_1930 = or(T_1926, T_1928) - wire T_1931 : UInt<20> - T_1931 <= UInt<1>("h00") - T_1931 <= T_1930 - node T_1933 = shr(io.req.bits.addr, 12) - node tag_match = eq(T_1931, T_1933) + tagList is invalid + node T_1922 = mux(idxMatch[0], tagList[0], UInt<1>("h00")) + node T_1924 = mux(idxMatch[1], tagList[1], UInt<1>("h00")) + node T_1926 = or(T_1922, T_1924) + wire T_1927 : UInt<20> + T_1927 is invalid + T_1927 <= T_1926 + node T_1928 = shr(io.req.bits.addr, 12) + node tag_match = eq(T_1927, T_1928) wire wbTagList : UInt<?>[2] - wbTagList[0] <= UInt<1>("h00") - wbTagList[1] <= UInt<1>("h00") + wbTagList is invalid wire refillMux : {way_en : UInt<4>, addr : UInt<12>}[2] - refillMux[0].addr <= UInt<1>("h00") - refillMux[0].way_en <= UInt<1>("h00") - refillMux[1].addr <= UInt<1>("h00") - refillMux[1].way_en <= UInt<1>("h00") + refillMux is invalid inst meta_read_arb of Arbiter_93 - meta_read_arb.io.out.ready <= UInt<1>("h00") - meta_read_arb.io.in[0].bits.tag <= UInt<1>("h00") - meta_read_arb.io.in[0].bits.idx <= UInt<1>("h00") - meta_read_arb.io.in[0].valid <= UInt<1>("h00") - meta_read_arb.io.in[1].bits.tag <= UInt<1>("h00") - meta_read_arb.io.in[1].bits.idx <= UInt<1>("h00") - meta_read_arb.io.in[1].valid <= UInt<1>("h00") + meta_read_arb.io is invalid meta_read_arb.clk <= clk meta_read_arb.reset <= reset inst meta_write_arb of Arbiter_94 - meta_write_arb.io.out.ready <= UInt<1>("h00") - meta_write_arb.io.in[0].bits.data.coh.state <= UInt<1>("h00") - meta_write_arb.io.in[0].bits.data.tag <= UInt<1>("h00") - meta_write_arb.io.in[0].bits.way_en <= UInt<1>("h00") - meta_write_arb.io.in[0].bits.idx <= UInt<1>("h00") - meta_write_arb.io.in[0].valid <= UInt<1>("h00") - meta_write_arb.io.in[1].bits.data.coh.state <= UInt<1>("h00") - meta_write_arb.io.in[1].bits.data.tag <= UInt<1>("h00") - meta_write_arb.io.in[1].bits.way_en <= UInt<1>("h00") - meta_write_arb.io.in[1].bits.idx <= UInt<1>("h00") - meta_write_arb.io.in[1].valid <= UInt<1>("h00") + meta_write_arb.io is invalid meta_write_arb.clk <= clk meta_write_arb.reset <= reset inst mem_req_arb of LockingArbiter - mem_req_arb.io.out.ready <= UInt<1>("h00") - mem_req_arb.io.in[0].bits.data <= UInt<1>("h00") - mem_req_arb.io.in[0].bits.union <= UInt<1>("h00") - mem_req_arb.io.in[0].bits.a_type <= UInt<1>("h00") - mem_req_arb.io.in[0].bits.is_builtin_type <= UInt<1>("h00") - mem_req_arb.io.in[0].bits.addr_beat <= UInt<1>("h00") - mem_req_arb.io.in[0].bits.client_xact_id <= UInt<1>("h00") - mem_req_arb.io.in[0].bits.addr_block <= UInt<1>("h00") - mem_req_arb.io.in[0].valid <= UInt<1>("h00") - mem_req_arb.io.in[1].bits.data <= UInt<1>("h00") - mem_req_arb.io.in[1].bits.union <= UInt<1>("h00") - mem_req_arb.io.in[1].bits.a_type <= UInt<1>("h00") - mem_req_arb.io.in[1].bits.is_builtin_type <= UInt<1>("h00") - mem_req_arb.io.in[1].bits.addr_beat <= UInt<1>("h00") - mem_req_arb.io.in[1].bits.client_xact_id <= UInt<1>("h00") - mem_req_arb.io.in[1].bits.addr_block <= UInt<1>("h00") - mem_req_arb.io.in[1].valid <= UInt<1>("h00") - mem_req_arb.io.in[2].bits.data <= UInt<1>("h00") - mem_req_arb.io.in[2].bits.union <= UInt<1>("h00") - mem_req_arb.io.in[2].bits.a_type <= UInt<1>("h00") - mem_req_arb.io.in[2].bits.is_builtin_type <= UInt<1>("h00") - mem_req_arb.io.in[2].bits.addr_beat <= UInt<1>("h00") - mem_req_arb.io.in[2].bits.client_xact_id <= UInt<1>("h00") - mem_req_arb.io.in[2].bits.addr_block <= UInt<1>("h00") - mem_req_arb.io.in[2].valid <= UInt<1>("h00") + mem_req_arb.io is invalid mem_req_arb.clk <= clk mem_req_arb.reset <= reset inst wb_req_arb of Arbiter_95 - wb_req_arb.io.out.ready <= UInt<1>("h00") - wb_req_arb.io.in[0].bits.way_en <= UInt<1>("h00") - wb_req_arb.io.in[0].bits.data <= UInt<1>("h00") - wb_req_arb.io.in[0].bits.r_type <= UInt<1>("h00") - wb_req_arb.io.in[0].bits.voluntary <= UInt<1>("h00") - wb_req_arb.io.in[0].bits.client_xact_id <= UInt<1>("h00") - wb_req_arb.io.in[0].bits.addr_block <= UInt<1>("h00") - wb_req_arb.io.in[0].bits.addr_beat <= UInt<1>("h00") - wb_req_arb.io.in[0].valid <= UInt<1>("h00") - wb_req_arb.io.in[1].bits.way_en <= UInt<1>("h00") - wb_req_arb.io.in[1].bits.data <= UInt<1>("h00") - wb_req_arb.io.in[1].bits.r_type <= UInt<1>("h00") - wb_req_arb.io.in[1].bits.voluntary <= UInt<1>("h00") - wb_req_arb.io.in[1].bits.client_xact_id <= UInt<1>("h00") - wb_req_arb.io.in[1].bits.addr_block <= UInt<1>("h00") - wb_req_arb.io.in[1].bits.addr_beat <= UInt<1>("h00") - wb_req_arb.io.in[1].valid <= UInt<1>("h00") + wb_req_arb.io is invalid wb_req_arb.clk <= clk wb_req_arb.reset <= reset inst replay_arb of Arbiter_96 - replay_arb.io.out.ready <= UInt<1>("h00") - replay_arb.io.in[0].bits.sdq_id <= UInt<1>("h00") - replay_arb.io.in[0].bits.phys <= UInt<1>("h00") - replay_arb.io.in[0].bits.kill <= UInt<1>("h00") - replay_arb.io.in[0].bits.typ <= UInt<1>("h00") - replay_arb.io.in[0].bits.cmd <= UInt<1>("h00") - replay_arb.io.in[0].bits.tag <= UInt<1>("h00") - replay_arb.io.in[0].bits.addr <= UInt<1>("h00") - replay_arb.io.in[0].valid <= UInt<1>("h00") - replay_arb.io.in[1].bits.sdq_id <= UInt<1>("h00") - replay_arb.io.in[1].bits.phys <= UInt<1>("h00") - replay_arb.io.in[1].bits.kill <= UInt<1>("h00") - replay_arb.io.in[1].bits.typ <= UInt<1>("h00") - replay_arb.io.in[1].bits.cmd <= UInt<1>("h00") - replay_arb.io.in[1].bits.tag <= UInt<1>("h00") - replay_arb.io.in[1].bits.addr <= UInt<1>("h00") - replay_arb.io.in[1].valid <= UInt<1>("h00") + replay_arb.io is invalid replay_arb.clk <= clk replay_arb.reset <= reset inst alloc_arb of Arbiter_97 - alloc_arb.io.out.ready <= UInt<1>("h00") - alloc_arb.io.in[0].bits <= UInt<1>("h00") - alloc_arb.io.in[0].valid <= UInt<1>("h00") - alloc_arb.io.in[1].bits <= UInt<1>("h00") - alloc_arb.io.in[1].valid <= UInt<1>("h00") + alloc_arb.io is invalid alloc_arb.clk <= clk alloc_arb.reset <= reset io.fence_rdy <= UInt<1>("h01") io.probe_rdy <= UInt<1>("h01") - inst T_2807 of MSHR - T_2807.io.wb_req.ready <= UInt<1>("h00") - T_2807.io.mem_grant.bits.data <= UInt<1>("h00") - T_2807.io.mem_grant.bits.g_type <= UInt<1>("h00") - T_2807.io.mem_grant.bits.is_builtin_type <= UInt<1>("h00") - T_2807.io.mem_grant.bits.manager_xact_id <= UInt<1>("h00") - T_2807.io.mem_grant.bits.client_xact_id <= UInt<1>("h00") - T_2807.io.mem_grant.bits.addr_beat <= UInt<1>("h00") - T_2807.io.mem_grant.valid <= UInt<1>("h00") - T_2807.io.replay.ready <= UInt<1>("h00") - T_2807.io.meta_write.ready <= UInt<1>("h00") - T_2807.io.meta_read.ready <= UInt<1>("h00") - T_2807.io.mem_req.ready <= UInt<1>("h00") - T_2807.io.req_bits.way_en <= UInt<1>("h00") - T_2807.io.req_bits.old_meta.coh.state <= UInt<1>("h00") - T_2807.io.req_bits.old_meta.tag <= UInt<1>("h00") - T_2807.io.req_bits.tag_match <= UInt<1>("h00") - T_2807.io.req_bits.sdq_id <= UInt<1>("h00") - T_2807.io.req_bits.phys <= UInt<1>("h00") - T_2807.io.req_bits.kill <= UInt<1>("h00") - T_2807.io.req_bits.typ <= UInt<1>("h00") - T_2807.io.req_bits.cmd <= UInt<1>("h00") - T_2807.io.req_bits.tag <= UInt<1>("h00") - T_2807.io.req_bits.addr <= UInt<1>("h00") - T_2807.io.req_sec_val <= UInt<1>("h00") - T_2807.io.req_pri_val <= UInt<1>("h00") - T_2807.clk <= clk - T_2807.reset <= reset - idxMatch[0] <= T_2807.io.idx_match - tagList[0] <= T_2807.io.tag - node T_2833 = shr(T_2807.io.wb_req.bits.addr_block, 6) - wbTagList[0] <= T_2833 - alloc_arb.io.in[0].valid <= T_2807.io.req_pri_rdy - T_2807.io.req_pri_val <= alloc_arb.io.in[0].ready - node T_2834 = and(io.req.valid, sdq_rdy) - node T_2835 = and(T_2834, tag_match) - T_2807.io.req_sec_val <= T_2835 - T_2807.io.req_bits <- io.req.bits - T_2807.io.req_bits.sdq_id <= sdq_alloc_id - meta_read_arb.io.in[0] <- T_2807.io.meta_read - meta_write_arb.io.in[0] <- T_2807.io.meta_write - mem_req_arb.io.in[0] <- T_2807.io.mem_req - wb_req_arb.io.in[0] <- T_2807.io.wb_req - replay_arb.io.in[0] <- T_2807.io.replay - node T_2837 = eq(io.mem_grant.bits.client_xact_id, UInt<1>("h00")) - node T_2838 = and(io.mem_grant.valid, T_2837) - T_2807.io.mem_grant.valid <= T_2838 - T_2807.io.mem_grant.bits <- io.mem_grant.bits - refillMux[0] <- T_2807.io.refill - node T_2839 = or(UInt<1>("h00"), T_2807.io.req_pri_rdy) - node T_2840 = or(UInt<1>("h00"), T_2807.io.req_sec_rdy) - node T_2841 = or(UInt<1>("h00"), T_2807.io.idx_match) - node T_2843 = eq(T_2807.io.req_pri_rdy, UInt<1>("h00")) - when T_2843 : + inst T_2714 of MSHR + T_2714.io is invalid + T_2714.clk <= clk + T_2714.reset <= reset + idxMatch[0] <= T_2714.io.idx_match + tagList[0] <= T_2714.io.tag + node T_2715 = shr(T_2714.io.wb_req.bits.addr_block, 6) + wbTagList[0] <= T_2715 + alloc_arb.io.in[0].valid <= T_2714.io.req_pri_rdy + T_2714.io.req_pri_val <= alloc_arb.io.in[0].ready + node T_2716 = and(io.req.valid, sdq_rdy) + node T_2717 = and(T_2716, tag_match) + T_2714.io.req_sec_val <= T_2717 + T_2714.io.req_bits <- io.req.bits + T_2714.io.req_bits.sdq_id <= sdq_alloc_id + meta_read_arb.io.in[0] <- T_2714.io.meta_read + meta_write_arb.io.in[0] <- T_2714.io.meta_write + mem_req_arb.io.in[0] <- T_2714.io.mem_req + wb_req_arb.io.in[0] <- T_2714.io.wb_req + replay_arb.io.in[0] <- T_2714.io.replay + node T_2719 = eq(io.mem_grant.bits.client_xact_id, UInt<1>("h00")) + node T_2720 = and(io.mem_grant.valid, T_2719) + T_2714.io.mem_grant.valid <= T_2720 + T_2714.io.mem_grant.bits <- io.mem_grant.bits + refillMux[0] <- T_2714.io.refill + node T_2721 = or(UInt<1>("h00"), T_2714.io.req_pri_rdy) + node T_2722 = or(UInt<1>("h00"), T_2714.io.req_sec_rdy) + node T_2723 = or(UInt<1>("h00"), T_2714.io.idx_match) + node T_2725 = eq(T_2714.io.req_pri_rdy, UInt<1>("h00")) + when T_2725 : io.fence_rdy <= UInt<1>("h00") skip - node T_2846 = eq(T_2807.io.probe_rdy, UInt<1>("h00")) - when T_2846 : + node T_2728 = eq(T_2714.io.probe_rdy, UInt<1>("h00")) + when T_2728 : io.probe_rdy <= UInt<1>("h00") skip - inst T_2848 of MSHR_99 - T_2848.io.wb_req.ready <= UInt<1>("h00") - T_2848.io.mem_grant.bits.data <= UInt<1>("h00") - T_2848.io.mem_grant.bits.g_type <= UInt<1>("h00") - T_2848.io.mem_grant.bits.is_builtin_type <= UInt<1>("h00") - T_2848.io.mem_grant.bits.manager_xact_id <= UInt<1>("h00") - T_2848.io.mem_grant.bits.client_xact_id <= UInt<1>("h00") - T_2848.io.mem_grant.bits.addr_beat <= UInt<1>("h00") - T_2848.io.mem_grant.valid <= UInt<1>("h00") - T_2848.io.replay.ready <= UInt<1>("h00") - T_2848.io.meta_write.ready <= UInt<1>("h00") - T_2848.io.meta_read.ready <= UInt<1>("h00") - T_2848.io.mem_req.ready <= UInt<1>("h00") - T_2848.io.req_bits.way_en <= UInt<1>("h00") - T_2848.io.req_bits.old_meta.coh.state <= UInt<1>("h00") - T_2848.io.req_bits.old_meta.tag <= UInt<1>("h00") - T_2848.io.req_bits.tag_match <= UInt<1>("h00") - T_2848.io.req_bits.sdq_id <= UInt<1>("h00") - T_2848.io.req_bits.phys <= UInt<1>("h00") - T_2848.io.req_bits.kill <= UInt<1>("h00") - T_2848.io.req_bits.typ <= UInt<1>("h00") - T_2848.io.req_bits.cmd <= UInt<1>("h00") - T_2848.io.req_bits.tag <= UInt<1>("h00") - T_2848.io.req_bits.addr <= UInt<1>("h00") - T_2848.io.req_sec_val <= UInt<1>("h00") - T_2848.io.req_pri_val <= UInt<1>("h00") - T_2848.clk <= clk - T_2848.reset <= reset - idxMatch[1] <= T_2848.io.idx_match - tagList[1] <= T_2848.io.tag - node T_2874 = shr(T_2848.io.wb_req.bits.addr_block, 6) - wbTagList[1] <= T_2874 - alloc_arb.io.in[1].valid <= T_2848.io.req_pri_rdy - T_2848.io.req_pri_val <= alloc_arb.io.in[1].ready - node T_2875 = and(io.req.valid, sdq_rdy) - node T_2876 = and(T_2875, tag_match) - T_2848.io.req_sec_val <= T_2876 - T_2848.io.req_bits <- io.req.bits - T_2848.io.req_bits.sdq_id <= sdq_alloc_id - meta_read_arb.io.in[1] <- T_2848.io.meta_read - meta_write_arb.io.in[1] <- T_2848.io.meta_write - mem_req_arb.io.in[1] <- T_2848.io.mem_req - wb_req_arb.io.in[1] <- T_2848.io.wb_req - replay_arb.io.in[1] <- T_2848.io.replay - node T_2878 = eq(io.mem_grant.bits.client_xact_id, UInt<1>("h01")) - node T_2879 = and(io.mem_grant.valid, T_2878) - T_2848.io.mem_grant.valid <= T_2879 - T_2848.io.mem_grant.bits <- io.mem_grant.bits - refillMux[1] <- T_2848.io.refill - node pri_rdy = or(T_2839, T_2848.io.req_pri_rdy) - node sec_rdy = or(T_2840, T_2848.io.req_sec_rdy) - node idx_match = or(T_2841, T_2848.io.idx_match) - node T_2884 = eq(T_2848.io.req_pri_rdy, UInt<1>("h00")) - when T_2884 : + inst T_2730 of MSHR_99 + T_2730.io is invalid + T_2730.clk <= clk + T_2730.reset <= reset + idxMatch[1] <= T_2730.io.idx_match + tagList[1] <= T_2730.io.tag + node T_2731 = shr(T_2730.io.wb_req.bits.addr_block, 6) + wbTagList[1] <= T_2731 + alloc_arb.io.in[1].valid <= T_2730.io.req_pri_rdy + T_2730.io.req_pri_val <= alloc_arb.io.in[1].ready + node T_2732 = and(io.req.valid, sdq_rdy) + node T_2733 = and(T_2732, tag_match) + T_2730.io.req_sec_val <= T_2733 + T_2730.io.req_bits <- io.req.bits + T_2730.io.req_bits.sdq_id <= sdq_alloc_id + meta_read_arb.io.in[1] <- T_2730.io.meta_read + meta_write_arb.io.in[1] <- T_2730.io.meta_write + mem_req_arb.io.in[1] <- T_2730.io.mem_req + wb_req_arb.io.in[1] <- T_2730.io.wb_req + replay_arb.io.in[1] <- T_2730.io.replay + node T_2735 = eq(io.mem_grant.bits.client_xact_id, UInt<1>("h01")) + node T_2736 = and(io.mem_grant.valid, T_2735) + T_2730.io.mem_grant.valid <= T_2736 + T_2730.io.mem_grant.bits <- io.mem_grant.bits + refillMux[1] <- T_2730.io.refill + node pri_rdy = or(T_2721, T_2730.io.req_pri_rdy) + node sec_rdy = or(T_2722, T_2730.io.req_sec_rdy) + node idx_match = or(T_2723, T_2730.io.idx_match) + node T_2741 = eq(T_2730.io.req_pri_rdy, UInt<1>("h00")) + when T_2741 : io.fence_rdy <= UInt<1>("h00") skip - node T_2887 = eq(T_2848.io.probe_rdy, UInt<1>("h00")) - when T_2887 : + node T_2744 = eq(T_2730.io.probe_rdy, UInt<1>("h00")) + when T_2744 : io.probe_rdy <= UInt<1>("h00") skip - node T_2889 = and(io.req.valid, sdq_rdy) - node T_2890 = and(T_2889, cacheable) - node T_2892 = eq(idx_match, UInt<1>("h00")) - node T_2893 = and(T_2890, T_2892) - alloc_arb.io.out.ready <= T_2893 + node T_2746 = and(io.req.valid, sdq_rdy) + node T_2747 = and(T_2746, cacheable) + node T_2749 = eq(idx_match, UInt<1>("h00")) + node T_2750 = and(T_2747, T_2749) + alloc_arb.io.out.ready <= T_2750 io.meta_read <- meta_read_arb.io.out io.meta_write <- meta_write_arb.io.out io.mem_req <- mem_req_arb.io.out io.wb_req <- wb_req_arb.io.out inst mmio_alloc_arb of Arbiter_101 - mmio_alloc_arb.io.out.ready <= UInt<1>("h00") - mmio_alloc_arb.io.in[0].bits <= UInt<1>("h00") - mmio_alloc_arb.io.in[0].valid <= UInt<1>("h00") + mmio_alloc_arb.io is invalid mmio_alloc_arb.clk <= clk mmio_alloc_arb.reset <= reset inst resp_arb of Arbiter_102 - resp_arb.io.out.ready <= UInt<1>("h00") - resp_arb.io.in[0].bits.store_data <= UInt<1>("h00") - resp_arb.io.in[0].bits.data_word_bypass <= UInt<1>("h00") - resp_arb.io.in[0].bits.has_data <= UInt<1>("h00") - resp_arb.io.in[0].bits.replay <= UInt<1>("h00") - resp_arb.io.in[0].bits.nack <= UInt<1>("h00") - resp_arb.io.in[0].bits.data <= UInt<1>("h00") - resp_arb.io.in[0].bits.typ <= UInt<1>("h00") - resp_arb.io.in[0].bits.cmd <= UInt<1>("h00") - resp_arb.io.in[0].bits.tag <= UInt<1>("h00") - resp_arb.io.in[0].bits.addr <= UInt<1>("h00") - resp_arb.io.in[0].valid <= UInt<1>("h00") + resp_arb.io is invalid resp_arb.clk <= clk resp_arb.reset <= reset - inst T_2970 of IOMSHR - T_2970.io.resp.ready <= UInt<1>("h00") - T_2970.io.grant.bits.data <= UInt<1>("h00") - T_2970.io.grant.bits.g_type <= UInt<1>("h00") - T_2970.io.grant.bits.is_builtin_type <= UInt<1>("h00") - T_2970.io.grant.bits.manager_xact_id <= UInt<1>("h00") - T_2970.io.grant.bits.client_xact_id <= UInt<1>("h00") - T_2970.io.grant.bits.addr_beat <= UInt<1>("h00") - T_2970.io.grant.valid <= UInt<1>("h00") - T_2970.io.acquire.ready <= UInt<1>("h00") - T_2970.io.req.bits.data <= UInt<1>("h00") - T_2970.io.req.bits.phys <= UInt<1>("h00") - T_2970.io.req.bits.kill <= UInt<1>("h00") - T_2970.io.req.bits.typ <= UInt<1>("h00") - T_2970.io.req.bits.cmd <= UInt<1>("h00") - T_2970.io.req.bits.tag <= UInt<1>("h00") - T_2970.io.req.bits.addr <= UInt<1>("h00") - T_2970.io.req.valid <= UInt<1>("h00") - T_2970.clk <= clk - T_2970.reset <= reset - mmio_alloc_arb.io.in[0].valid <= T_2970.io.req.ready - T_2970.io.req.valid <= mmio_alloc_arb.io.in[0].ready - T_2970.io.req.bits <- io.req.bits - node mmio_rdy = or(UInt<1>("h00"), T_2970.io.req.ready) - mem_req_arb.io.in[2] <- T_2970.io.acquire - T_2970.io.grant.bits <- io.mem_grant.bits - node T_2990 = eq(io.mem_grant.bits.client_xact_id, UInt<2>("h02")) - node T_2991 = and(io.mem_grant.valid, T_2990) - T_2970.io.grant.valid <= T_2991 - resp_arb.io.in[0] <- T_2970.io.resp - node T_2993 = eq(T_2970.io.req.ready, UInt<1>("h00")) - when T_2993 : + inst T_2812 of IOMSHR + T_2812.io is invalid + T_2812.clk <= clk + T_2812.reset <= reset + mmio_alloc_arb.io.in[0].valid <= T_2812.io.req.ready + T_2812.io.req.valid <= mmio_alloc_arb.io.in[0].ready + T_2812.io.req.bits <- io.req.bits + node mmio_rdy = or(UInt<1>("h00"), T_2812.io.req.ready) + mem_req_arb.io.in[2] <- T_2812.io.acquire + T_2812.io.grant.bits <- io.mem_grant.bits + node T_2815 = eq(io.mem_grant.bits.client_xact_id, UInt<2>("h02")) + node T_2816 = and(io.mem_grant.valid, T_2815) + T_2812.io.grant.valid <= T_2816 + resp_arb.io.in[0] <- T_2812.io.resp + node T_2818 = eq(T_2812.io.req.ready, UInt<1>("h00")) + when T_2818 : io.fence_rdy <= UInt<1>("h00") skip - node T_2996 = eq(cacheable, UInt<1>("h00")) - node T_2997 = and(io.req.valid, T_2996) - mmio_alloc_arb.io.out.ready <= T_2997 + node T_2821 = eq(cacheable, UInt<1>("h00")) + node T_2822 = and(io.req.valid, T_2821) + mmio_alloc_arb.io.out.ready <= T_2822 io.resp <- resp_arb.io.out - node T_2999 = eq(cacheable, UInt<1>("h00")) - node T_3000 = and(tag_match, sec_rdy) - node T_3001 = mux(idx_match, T_3000, pri_rdy) - node T_3002 = and(T_3001, sdq_rdy) - node T_3003 = mux(T_2999, mmio_rdy, T_3002) - io.req.ready <= T_3003 + node T_2824 = eq(cacheable, UInt<1>("h00")) + node T_2825 = and(tag_match, sec_rdy) + node T_2826 = mux(idx_match, T_2825, pri_rdy) + node T_2827 = and(T_2826, sdq_rdy) + node T_2828 = mux(T_2824, mmio_rdy, T_2827) + io.req.ready <= T_2828 io.secondary_miss <= idx_match io.refill <- refillMux[io.mem_grant.bits.client_xact_id] - node T_3053 = and(io.replay.ready, io.replay.valid) - node T_3054 = eq(io.replay.bits.cmd, UInt<5>("h01")) - node T_3055 = eq(io.replay.bits.cmd, UInt<5>("h07")) - node T_3056 = or(T_3054, T_3055) - node T_3057 = bit(io.replay.bits.cmd, 3) - node T_3058 = eq(io.replay.bits.cmd, UInt<5>("h04")) - node T_3059 = or(T_3057, T_3058) - node T_3060 = or(T_3056, T_3059) - node free_sdq = and(T_3053, T_3060) - reg T_3062 : UInt<5>, clk, UInt<1>("h00"), T_3062 + node T_2878 = and(io.replay.ready, io.replay.valid) + node T_2879 = eq(io.replay.bits.cmd, UInt<5>("h01")) + node T_2880 = eq(io.replay.bits.cmd, UInt<5>("h07")) + node T_2881 = or(T_2879, T_2880) + node T_2882 = bits(io.replay.bits.cmd, 3, 3) + node T_2883 = eq(io.replay.bits.cmd, UInt<5>("h04")) + node T_2884 = or(T_2882, T_2883) + node T_2885 = or(T_2881, T_2884) + node free_sdq = and(T_2878, T_2885) + reg T_2887 : UInt<5>, clk when free_sdq : - T_3062 <= replay_arb.io.out.bits.sdq_id + T_2887 <= replay_arb.io.out.bits.sdq_id skip - infer mport T_3063 = sdq[T_3062], clk - io.replay.bits.data <= T_3063 + infer mport T_2888 = sdq[T_2887], clk + io.replay.bits.data <= T_2888 io.replay <- replay_arb.io.out - node T_3064 = or(io.replay.valid, sdq_enq) - when T_3064 : - node T_3066 = dshl(UInt<1>("h01"), replay_arb.io.out.bits.sdq_id) - node T_3068 = subw(UInt<17>("h00"), free_sdq) - node T_3069 = and(T_3066, T_3068) - node T_3070 = not(T_3069) - node T_3071 = and(sdq_val, T_3070) - node T_3072 = bits(sdq_val, 16, 0) - node T_3073 = not(T_3072) - node T_3074 = bit(T_3073, 0) - node T_3075 = bit(T_3073, 1) - node T_3076 = bit(T_3073, 2) - node T_3077 = bit(T_3073, 3) - node T_3078 = bit(T_3073, 4) - node T_3079 = bit(T_3073, 5) - node T_3080 = bit(T_3073, 6) - node T_3081 = bit(T_3073, 7) - node T_3082 = bit(T_3073, 8) - node T_3083 = bit(T_3073, 9) - node T_3084 = bit(T_3073, 10) - node T_3085 = bit(T_3073, 11) - node T_3086 = bit(T_3073, 12) - node T_3087 = bit(T_3073, 13) - node T_3088 = bit(T_3073, 14) - node T_3089 = bit(T_3073, 15) - node T_3090 = bit(T_3073, 16) - wire T_3109 : UInt<17>[17] - T_3109[0] <= UInt<17>("h01") - T_3109[1] <= UInt<17>("h02") - T_3109[2] <= UInt<17>("h04") - T_3109[3] <= UInt<17>("h08") - T_3109[4] <= UInt<17>("h010") - T_3109[5] <= UInt<17>("h020") - T_3109[6] <= UInt<17>("h040") - T_3109[7] <= UInt<17>("h080") - T_3109[8] <= UInt<17>("h0100") - T_3109[9] <= UInt<17>("h0200") - T_3109[10] <= UInt<17>("h0400") - T_3109[11] <= UInt<17>("h0800") - T_3109[12] <= UInt<17>("h01000") - T_3109[13] <= UInt<17>("h02000") - T_3109[14] <= UInt<17>("h04000") - T_3109[15] <= UInt<17>("h08000") - T_3109[16] <= UInt<17>("h010000") - node T_3130 = mux(T_3090, T_3109[16], UInt<17>("h00")) - node T_3131 = mux(T_3089, T_3109[15], T_3130) - node T_3132 = mux(T_3088, T_3109[14], T_3131) - node T_3133 = mux(T_3087, T_3109[13], T_3132) - node T_3134 = mux(T_3086, T_3109[12], T_3133) - node T_3135 = mux(T_3085, T_3109[11], T_3134) - node T_3136 = mux(T_3084, T_3109[10], T_3135) - node T_3137 = mux(T_3083, T_3109[9], T_3136) - node T_3138 = mux(T_3082, T_3109[8], T_3137) - node T_3139 = mux(T_3081, T_3109[7], T_3138) - node T_3140 = mux(T_3080, T_3109[6], T_3139) - node T_3141 = mux(T_3079, T_3109[5], T_3140) - node T_3142 = mux(T_3078, T_3109[4], T_3141) - node T_3143 = mux(T_3077, T_3109[3], T_3142) - node T_3144 = mux(T_3076, T_3109[2], T_3143) - node T_3145 = mux(T_3075, T_3109[1], T_3144) - node T_3146 = mux(T_3074, T_3109[0], T_3145) - node T_3148 = subw(UInt<17>("h00"), sdq_enq) - node T_3149 = and(T_3146, T_3148) - node T_3150 = or(T_3071, T_3149) - sdq_val <= T_3150 + node T_2889 = or(io.replay.valid, sdq_enq) + when T_2889 : + node T_2891 = dshl(UInt<1>("h01"), replay_arb.io.out.bits.sdq_id) + node T_2893 = sub(UInt<17>("h00"), free_sdq) + node T_2894 = tail(T_2893, 1) + node T_2895 = and(T_2891, T_2894) + node T_2896 = not(T_2895) + node T_2897 = and(sdq_val, T_2896) + node T_2898 = bits(sdq_val, 16, 0) + node T_2899 = not(T_2898) + node T_2900 = bits(T_2899, 0, 0) + node T_2901 = bits(T_2899, 1, 1) + node T_2902 = bits(T_2899, 2, 2) + node T_2903 = bits(T_2899, 3, 3) + node T_2904 = bits(T_2899, 4, 4) + node T_2905 = bits(T_2899, 5, 5) + node T_2906 = bits(T_2899, 6, 6) + node T_2907 = bits(T_2899, 7, 7) + node T_2908 = bits(T_2899, 8, 8) + node T_2909 = bits(T_2899, 9, 9) + node T_2910 = bits(T_2899, 10, 10) + node T_2911 = bits(T_2899, 11, 11) + node T_2912 = bits(T_2899, 12, 12) + node T_2913 = bits(T_2899, 13, 13) + node T_2914 = bits(T_2899, 14, 14) + node T_2915 = bits(T_2899, 15, 15) + node T_2916 = bits(T_2899, 16, 16) + wire T_2935 : UInt<17>[17] + T_2935[0] <= UInt<17>("h01") + T_2935[1] <= UInt<17>("h02") + T_2935[2] <= UInt<17>("h04") + T_2935[3] <= UInt<17>("h08") + T_2935[4] <= UInt<17>("h010") + T_2935[5] <= UInt<17>("h020") + T_2935[6] <= UInt<17>("h040") + T_2935[7] <= UInt<17>("h080") + T_2935[8] <= UInt<17>("h0100") + T_2935[9] <= UInt<17>("h0200") + T_2935[10] <= UInt<17>("h0400") + T_2935[11] <= UInt<17>("h0800") + T_2935[12] <= UInt<17>("h01000") + T_2935[13] <= UInt<17>("h02000") + T_2935[14] <= UInt<17>("h04000") + T_2935[15] <= UInt<17>("h08000") + T_2935[16] <= UInt<17>("h010000") + node T_2956 = mux(T_2916, T_2935[16], UInt<17>("h00")) + node T_2957 = mux(T_2915, T_2935[15], T_2956) + node T_2958 = mux(T_2914, T_2935[14], T_2957) + node T_2959 = mux(T_2913, T_2935[13], T_2958) + node T_2960 = mux(T_2912, T_2935[12], T_2959) + node T_2961 = mux(T_2911, T_2935[11], T_2960) + node T_2962 = mux(T_2910, T_2935[10], T_2961) + node T_2963 = mux(T_2909, T_2935[9], T_2962) + node T_2964 = mux(T_2908, T_2935[8], T_2963) + node T_2965 = mux(T_2907, T_2935[7], T_2964) + node T_2966 = mux(T_2906, T_2935[6], T_2965) + node T_2967 = mux(T_2905, T_2935[5], T_2966) + node T_2968 = mux(T_2904, T_2935[4], T_2967) + node T_2969 = mux(T_2903, T_2935[3], T_2968) + node T_2970 = mux(T_2902, T_2935[2], T_2969) + node T_2971 = mux(T_2901, T_2935[1], T_2970) + node T_2972 = mux(T_2900, T_2935[0], T_2971) + node T_2974 = sub(UInt<17>("h00"), sdq_enq) + node T_2975 = tail(T_2974, 1) + node T_2976 = and(T_2972, T_2975) + node T_2977 = or(T_2897, T_2976) + sdq_val <= T_2977 skip module MetadataArray : @@ -31384,368 +23998,349 @@ circuit Top : input reset : UInt<1> output io : {flip read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}, flip write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, resp : {tag : UInt<20>, coh : {state : UInt<2>}}[4]} - io.resp[0].coh.state <= UInt<1>("h00") - io.resp[0].tag <= UInt<1>("h00") - io.resp[1].coh.state <= UInt<1>("h00") - io.resp[1].tag <= UInt<1>("h00") - io.resp[2].coh.state <= UInt<1>("h00") - io.resp[2].tag <= UInt<1>("h00") - io.resp[3].coh.state <= UInt<1>("h00") - io.resp[3].tag <= UInt<1>("h00") - io.write.ready <= UInt<1>("h00") - io.read.ready <= UInt<1>("h00") + io is invalid wire T_30 : {state : UInt<2>} - T_30.state <= UInt<1>("h00") + T_30 is invalid T_30.state <= UInt<1>("h00") wire rstVal : {tag : UInt<20>, coh : {state : UInt<2>}} - rstVal.coh.state <= UInt<1>("h00") - rstVal.tag <= UInt<1>("h00") + rstVal is invalid rstVal.tag <= UInt<1>("h00") rstVal.coh <- T_30 - reg rst_cnt : UInt<7>, clk, reset, UInt<7>("h00") + reg rst_cnt : UInt<7>, clk with : (reset => (reset, UInt<7>("h00"))) node rst = lt(rst_cnt, UInt<7>("h040")) node waddr = mux(rst, rst_cnt, io.write.bits.idx) - wire T_1709 : {tag : UInt<20>, coh : {state : UInt<2>}} - T_1709 <- io.write.bits.data - when rst : - T_1709 <- rstVal - skip - node wdata = cat(T_1709.tag, T_1709.coh.state) - node T_1784 = asSInt(io.write.bits.way_en) - node T_1785 = mux(rst, asSInt(UInt<1>("h01")), T_1784) - node T_1786 = bit(T_1785, 0) - node T_1787 = bit(T_1785, 1) - node T_1788 = bit(T_1785, 2) - node T_1789 = bit(T_1785, 3) + node T_1633 = mux(rst, rstVal, io.write.bits.data) + node wdata = cat(T_1633.tag, T_1633.coh.state) + node T_1708 = asSInt(io.write.bits.way_en) + node T_1709 = mux(rst, asSInt(UInt<1>("h01")), T_1708) + node T_1710 = bits(T_1709, 0, 0) + node T_1711 = bits(T_1709, 1, 1) + node T_1712 = bits(T_1709, 2, 2) + node T_1713 = bits(T_1709, 3, 3) wire wmask : UInt<1>[4] - wmask[0] <= T_1786 - wmask[1] <= T_1787 - wmask[2] <= T_1788 - wmask[3] <= T_1789 + wmask[0] <= T_1710 + wmask[1] <= T_1711 + wmask[2] <= T_1712 + wmask[3] <= T_1713 when rst : - node T_1798 = addw(rst_cnt, UInt<1>("h01")) - rst_cnt <= T_1798 + node T_1722 = add(rst_cnt, UInt<1>("h01")) + node T_1723 = tail(T_1722, 1) + rst_cnt <= T_1723 skip smem tag_arr : UInt<22>[4][64] - node T_1816 = or(rst, io.write.valid) - when T_1816 : - wire T_1818 : UInt<22>[4] - T_1818[0] <= wdata - T_1818[1] <= wdata - T_1818[2] <= wdata - T_1818[3] <= wdata - write mport T_1826 = tag_arr[waddr], clk + node T_1741 = or(rst, io.write.valid) + when T_1741 : + wire T_1743 : UInt<22>[4] + T_1743[0] <= wdata + T_1743[1] <= wdata + T_1743[2] <= wdata + T_1743[3] <= wdata + write mport T_1751 = tag_arr[waddr], clk when wmask[0] : - T_1826[0] <= T_1818[0] + T_1751[0] <= T_1743[0] skip when wmask[1] : - T_1826[1] <= T_1818[1] + T_1751[1] <= T_1743[1] skip when wmask[2] : - T_1826[2] <= T_1818[2] + T_1751[2] <= T_1743[2] skip when wmask[3] : - T_1826[3] <= T_1818[3] - skip - skip - poison T_1832 : UInt<6> - node T_1833 = mux(io.read.valid, io.read.bits.idx, T_1832) - read mport T_1836 = tag_arr[T_1833], clk - node T_1842 = cat(T_1836[3], T_1836[2]) - node T_1843 = cat(T_1836[1], T_1836[0]) - node tags = cat(T_1842, T_1843) - wire T_2503 : {tag : UInt<20>, coh : {state : UInt<2>}}[4] - T_2503[0].coh.state <= UInt<1>("h00") - T_2503[0].tag <= UInt<1>("h00") - T_2503[1].coh.state <= UInt<1>("h00") - T_2503[1].tag <= UInt<1>("h00") - T_2503[2].coh.state <= UInt<1>("h00") - T_2503[2].tag <= UInt<1>("h00") - T_2503[3].coh.state <= UInt<1>("h00") - T_2503[3].tag <= UInt<1>("h00") - node T_2877 = bits(tags, 1, 0) - T_2503[0].coh.state <= T_2877 - node T_2878 = bits(tags, 21, 2) - T_2503[0].tag <= T_2878 - node T_2879 = bits(tags, 23, 22) - T_2503[1].coh.state <= T_2879 - node T_2880 = bits(tags, 43, 24) - T_2503[1].tag <= T_2880 - node T_2881 = bits(tags, 45, 44) - T_2503[2].coh.state <= T_2881 - node T_2882 = bits(tags, 65, 46) - T_2503[2].tag <= T_2882 - node T_2883 = bits(tags, 67, 66) - T_2503[3].coh.state <= T_2883 - node T_2884 = bits(tags, 87, 68) - T_2503[3].tag <= T_2884 - io.resp <= T_2503 - node T_2886 = eq(rst, UInt<1>("h00")) - node T_2888 = eq(io.write.valid, UInt<1>("h00")) - node T_2889 = and(T_2886, T_2888) - io.read.ready <= T_2889 - node T_2891 = eq(rst, UInt<1>("h00")) - io.write.ready <= T_2891 + T_1751[3] <= T_1743[3] + skip + skip + wire T_1758 : UInt<?> + T_1758 is invalid + when io.read.valid : + T_1758 <= io.read.bits.idx + skip + read mport T_1761 = tag_arr[T_1758], clk + node T_1767 = cat(T_1761[3], T_1761[2]) + node T_1768 = cat(T_1761[1], T_1761[0]) + node tags = cat(T_1767, T_1768) + wire T_2428 : {tag : UInt<20>, coh : {state : UInt<2>}}[4] + T_2428 is invalid + node T_2794 = bits(tags, 1, 0) + T_2428[0].coh.state <= T_2794 + node T_2795 = bits(tags, 21, 2) + T_2428[0].tag <= T_2795 + node T_2796 = bits(tags, 23, 22) + T_2428[1].coh.state <= T_2796 + node T_2797 = bits(tags, 43, 24) + T_2428[1].tag <= T_2797 + node T_2798 = bits(tags, 45, 44) + T_2428[2].coh.state <= T_2798 + node T_2799 = bits(tags, 65, 46) + T_2428[2].tag <= T_2799 + node T_2800 = bits(tags, 67, 66) + T_2428[3].coh.state <= T_2800 + node T_2801 = bits(tags, 87, 68) + T_2428[3].tag <= T_2801 + io.resp <= T_2428 + node T_2803 = eq(rst, UInt<1>("h00")) + node T_2805 = eq(io.write.valid, UInt<1>("h00")) + node T_2806 = and(T_2803, T_2805) + io.read.ready <= T_2806 + node T_2808 = eq(rst, UInt<1>("h00")) + io.write.ready <= T_2808 module Arbiter_105 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}[5], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>}}, chosen : UInt<3>} - io.chosen <= UInt<1>("h00") - io.out.bits.idx <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") - io.in[2].ready <= UInt<1>("h00") - io.in[3].ready <= UInt<1>("h00") - io.in[4].ready <= UInt<1>("h00") + io is invalid wire T_128 : UInt<3> - T_128 <= UInt<1>("h00") + T_128 is invalid io.out.valid <= io.in[T_128].valid io.out.bits <- io.in[T_128].bits io.chosen <= T_128 io.in[T_128].ready <= UInt<1>("h00") - node T_154 = or(UInt<1>("h00"), io.in[0].valid) - node T_156 = eq(T_154, UInt<1>("h00")) - node T_158 = or(UInt<1>("h00"), io.in[0].valid) - node T_159 = or(T_158, io.in[1].valid) - node T_161 = eq(T_159, UInt<1>("h00")) - node T_163 = or(UInt<1>("h00"), io.in[0].valid) - node T_164 = or(T_163, io.in[1].valid) - node T_165 = or(T_164, io.in[2].valid) - node T_167 = eq(T_165, UInt<1>("h00")) - node T_169 = or(UInt<1>("h00"), io.in[0].valid) - node T_170 = or(T_169, io.in[1].valid) - node T_171 = or(T_170, io.in[2].valid) - node T_172 = or(T_171, io.in[3].valid) - node T_174 = eq(T_172, UInt<1>("h00")) - node T_176 = eq(UInt<3>("h04"), UInt<1>("h00")) - node T_177 = mux(UInt<1>("h00"), T_176, UInt<1>("h01")) - node T_178 = and(T_177, io.out.ready) - io.in[0].ready <= T_178 - node T_180 = eq(UInt<3>("h04"), UInt<1>("h01")) - node T_181 = mux(UInt<1>("h00"), T_180, T_156) - node T_182 = and(T_181, io.out.ready) - io.in[1].ready <= T_182 - node T_184 = eq(UInt<3>("h04"), UInt<2>("h02")) - node T_185 = mux(UInt<1>("h00"), T_184, T_161) - node T_186 = and(T_185, io.out.ready) - io.in[2].ready <= T_186 - node T_188 = eq(UInt<3>("h04"), UInt<2>("h03")) - node T_189 = mux(UInt<1>("h00"), T_188, T_167) - node T_190 = and(T_189, io.out.ready) - io.in[3].ready <= T_190 - node T_192 = eq(UInt<3>("h04"), UInt<3>("h04")) - node T_193 = mux(UInt<1>("h00"), T_192, T_174) - node T_194 = and(T_193, io.out.ready) - io.in[4].ready <= T_194 - node T_197 = mux(io.in[3].valid, UInt<2>("h03"), UInt<3>("h04")) - node T_199 = mux(io.in[2].valid, UInt<2>("h02"), T_197) - node T_201 = mux(io.in[1].valid, UInt<1>("h01"), T_199) - node T_203 = mux(io.in[0].valid, UInt<1>("h00"), T_201) - node T_204 = mux(UInt<1>("h00"), UInt<3>("h04"), T_203) - T_128 <= T_204 + node T_153 = or(UInt<1>("h00"), io.in[0].valid) + node T_155 = eq(T_153, UInt<1>("h00")) + node T_157 = or(UInt<1>("h00"), io.in[0].valid) + node T_158 = or(T_157, io.in[1].valid) + node T_160 = eq(T_158, UInt<1>("h00")) + node T_162 = or(UInt<1>("h00"), io.in[0].valid) + node T_163 = or(T_162, io.in[1].valid) + node T_164 = or(T_163, io.in[2].valid) + node T_166 = eq(T_164, UInt<1>("h00")) + node T_168 = or(UInt<1>("h00"), io.in[0].valid) + node T_169 = or(T_168, io.in[1].valid) + node T_170 = or(T_169, io.in[2].valid) + node T_171 = or(T_170, io.in[3].valid) + node T_173 = eq(T_171, UInt<1>("h00")) + node T_175 = eq(UInt<3>("h04"), UInt<1>("h00")) + node T_176 = mux(UInt<1>("h00"), T_175, UInt<1>("h01")) + node T_177 = and(T_176, io.out.ready) + io.in[0].ready <= T_177 + node T_179 = eq(UInt<3>("h04"), UInt<1>("h01")) + node T_180 = mux(UInt<1>("h00"), T_179, T_155) + node T_181 = and(T_180, io.out.ready) + io.in[1].ready <= T_181 + node T_183 = eq(UInt<3>("h04"), UInt<2>("h02")) + node T_184 = mux(UInt<1>("h00"), T_183, T_160) + node T_185 = and(T_184, io.out.ready) + io.in[2].ready <= T_185 + node T_187 = eq(UInt<3>("h04"), UInt<2>("h03")) + node T_188 = mux(UInt<1>("h00"), T_187, T_166) + node T_189 = and(T_188, io.out.ready) + io.in[3].ready <= T_189 + node T_191 = eq(UInt<3>("h04"), UInt<3>("h04")) + node T_192 = mux(UInt<1>("h00"), T_191, T_173) + node T_193 = and(T_192, io.out.ready) + io.in[4].ready <= T_193 + node T_196 = mux(io.in[3].valid, UInt<2>("h03"), UInt<3>("h04")) + node T_198 = mux(io.in[2].valid, UInt<2>("h02"), T_196) + node T_200 = mux(io.in[1].valid, UInt<1>("h01"), T_198) + node T_202 = mux(io.in[0].valid, UInt<1>("h00"), T_200) + node T_203 = mux(UInt<1>("h00"), UInt<3>("h04"), T_202) + T_128 <= T_203 module DataArray : input clk : Clock input reset : UInt<1> output io : {flip read : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}, flip write : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, resp : UInt<128>[4]} - io.resp[0] <= UInt<1>("h00") - io.resp[1] <= UInt<1>("h00") - io.resp[2] <= UInt<1>("h00") - io.resp[3] <= UInt<1>("h00") - io.write.ready <= UInt<1>("h00") - io.read.ready <= UInt<1>("h00") + io is invalid node waddr = shr(io.write.bits.addr, 4) node raddr = shr(io.read.bits.addr, 4) node T_572 = bits(io.write.bits.way_en, 1, 0) node T_573 = bits(io.read.bits.way_en, 1, 0) wire T_582 : UInt<128>[2] - T_582[0] <= UInt<1>("h00") - T_582[1] <= UInt<1>("h00") - reg T_588 : UInt<12>, clk, UInt<1>("h00"), T_588 + T_582 is invalid + reg T_586 : UInt<12>, clk when io.read.valid : - T_588 <= io.read.bits.addr - skip - smem T_601 : UInt<64>[2][256] - node T_603 = neq(T_572, UInt<1>("h00")) - node T_604 = and(T_603, io.write.valid) - node T_605 = bit(io.write.bits.wmask, 0) - node T_606 = and(T_604, T_605) - when T_606 : - node T_607 = bits(io.write.bits.data, 63, 0) - node T_608 = bits(io.write.bits.data, 63, 0) - wire T_610 : UInt<64>[2] - T_610[0] <= T_607 - T_610[1] <= T_608 - node T_614 = bit(T_572, 0) - node T_615 = bit(T_572, 1) - wire T_617 : UInt<1>[2] - T_617[0] <= T_614 - T_617[1] <= T_615 - write mport T_623 = T_601[waddr], clk - when T_617[0] : - T_623[0] <= T_610[0] - skip - when T_617[1] : - T_623[1] <= T_610[1] - skip - skip - node T_628 = neq(T_573, UInt<1>("h00")) - node T_629 = and(T_628, io.read.valid) - poison T_630 : UInt<8> - node T_631 = mux(T_629, raddr, T_630) - read mport T_634 = T_601[T_631], clk - node T_638 = cat(T_634[1], T_634[0]) - T_582[0] <= T_638 - smem T_651 : UInt<64>[2][256] - node T_653 = neq(T_572, UInt<1>("h00")) - node T_654 = and(T_653, io.write.valid) - node T_655 = bit(io.write.bits.wmask, 1) - node T_656 = and(T_654, T_655) - when T_656 : - node T_657 = bits(io.write.bits.data, 127, 64) - node T_658 = bits(io.write.bits.data, 127, 64) - wire T_660 : UInt<64>[2] - T_660[0] <= T_657 - T_660[1] <= T_658 - node T_664 = bit(T_572, 0) - node T_665 = bit(T_572, 1) - wire T_667 : UInt<1>[2] - T_667[0] <= T_664 - T_667[1] <= T_665 - write mport T_673 = T_651[waddr], clk - when T_667[0] : - T_673[0] <= T_660[0] - skip - when T_667[1] : - T_673[1] <= T_660[1] - skip - skip - node T_678 = neq(T_573, UInt<1>("h00")) - node T_679 = and(T_678, io.read.valid) - poison T_680 : UInt<8> - node T_681 = mux(T_679, raddr, T_680) - read mport T_684 = T_651[T_681], clk - node T_688 = cat(T_684[1], T_684[0]) - T_582[1] <= T_688 - node T_689 = bits(T_582[0], 63, 0) - node T_690 = bits(T_582[1], 63, 0) - wire T_692 : UInt<64>[2] - T_692[0] <= T_689 - T_692[1] <= T_690 - node T_696 = bits(T_588, 3, 3) - wire T_699 : UInt<64>[2] - T_699[0] <= T_692[T_696] - T_699[1] <= T_692[1] - node T_703 = cat(T_699[1], T_699[0]) - io.resp[0] <= T_703 - node T_704 = bits(T_582[0], 127, 64) - node T_705 = bits(T_582[1], 127, 64) - wire T_707 : UInt<64>[2] - T_707[0] <= T_704 - T_707[1] <= T_705 - node T_711 = bits(T_588, 3, 3) - wire T_714 : UInt<64>[2] - T_714[0] <= T_707[T_711] - T_714[1] <= T_707[1] - node T_718 = cat(T_714[1], T_714[0]) - io.resp[1] <= T_718 - node T_719 = bits(io.write.bits.way_en, 3, 2) - node T_720 = bits(io.read.bits.way_en, 3, 2) - wire T_729 : UInt<128>[2] - T_729[0] <= UInt<1>("h00") - T_729[1] <= UInt<1>("h00") - reg T_735 : UInt<12>, clk, UInt<1>("h00"), T_735 + T_586 <= io.read.bits.addr + skip + smem T_599 : UInt<64>[2][256] + node T_601 = neq(T_572, UInt<1>("h00")) + node T_602 = and(T_601, io.write.valid) + node T_603 = bits(io.write.bits.wmask, 0, 0) + node T_604 = and(T_602, T_603) + when T_604 : + node T_605 = bits(io.write.bits.data, 63, 0) + node T_606 = bits(io.write.bits.data, 63, 0) + wire T_608 : UInt<64>[2] + T_608[0] <= T_605 + T_608[1] <= T_606 + node T_612 = bits(T_572, 0, 0) + node T_613 = bits(T_572, 1, 1) + wire T_615 : UInt<1>[2] + T_615[0] <= T_612 + T_615[1] <= T_613 + write mport T_621 = T_599[waddr], clk + when T_615[0] : + T_621[0] <= T_608[0] + skip + when T_615[1] : + T_621[1] <= T_608[1] + skip + skip + node T_626 = neq(T_573, UInt<1>("h00")) + node T_627 = and(T_626, io.read.valid) + wire T_629 : UInt<?> + T_629 is invalid + when T_627 : + T_629 <= raddr + skip + read mport T_632 = T_599[T_629], clk + node T_636 = cat(T_632[1], T_632[0]) + T_582[0] <= T_636 + smem T_649 : UInt<64>[2][256] + node T_651 = neq(T_572, UInt<1>("h00")) + node T_652 = and(T_651, io.write.valid) + node T_653 = bits(io.write.bits.wmask, 1, 1) + node T_654 = and(T_652, T_653) + when T_654 : + node T_655 = bits(io.write.bits.data, 127, 64) + node T_656 = bits(io.write.bits.data, 127, 64) + wire T_658 : UInt<64>[2] + T_658[0] <= T_655 + T_658[1] <= T_656 + node T_662 = bits(T_572, 0, 0) + node T_663 = bits(T_572, 1, 1) + wire T_665 : UInt<1>[2] + T_665[0] <= T_662 + T_665[1] <= T_663 + write mport T_671 = T_649[waddr], clk + when T_665[0] : + T_671[0] <= T_658[0] + skip + when T_665[1] : + T_671[1] <= T_658[1] + skip + skip + node T_676 = neq(T_573, UInt<1>("h00")) + node T_677 = and(T_676, io.read.valid) + wire T_679 : UInt<?> + T_679 is invalid + when T_677 : + T_679 <= raddr + skip + read mport T_682 = T_649[T_679], clk + node T_686 = cat(T_682[1], T_682[0]) + T_582[1] <= T_686 + node T_687 = bits(T_582[0], 63, 0) + node T_688 = bits(T_582[1], 63, 0) + wire T_690 : UInt<64>[2] + T_690[0] <= T_687 + T_690[1] <= T_688 + node T_694 = bits(T_586, 3, 3) + wire T_697 : UInt<64>[2] + T_697[0] <= T_690[T_694] + T_697[1] <= T_690[1] + node T_701 = cat(T_697[1], T_697[0]) + io.resp[0] <= T_701 + node T_702 = bits(T_582[0], 127, 64) + node T_703 = bits(T_582[1], 127, 64) + wire T_705 : UInt<64>[2] + T_705[0] <= T_702 + T_705[1] <= T_703 + node T_709 = bits(T_586, 3, 3) + wire T_712 : UInt<64>[2] + T_712[0] <= T_705[T_709] + T_712[1] <= T_705[1] + node T_716 = cat(T_712[1], T_712[0]) + io.resp[1] <= T_716 + node T_717 = bits(io.write.bits.way_en, 3, 2) + node T_718 = bits(io.read.bits.way_en, 3, 2) + wire T_727 : UInt<128>[2] + T_727 is invalid + reg T_731 : UInt<12>, clk when io.read.valid : - T_735 <= io.read.bits.addr - skip - smem T_748 : UInt<64>[2][256] - node T_750 = neq(T_719, UInt<1>("h00")) - node T_751 = and(T_750, io.write.valid) - node T_752 = bit(io.write.bits.wmask, 0) - node T_753 = and(T_751, T_752) - when T_753 : - node T_754 = bits(io.write.bits.data, 63, 0) - node T_755 = bits(io.write.bits.data, 63, 0) - wire T_757 : UInt<64>[2] - T_757[0] <= T_754 - T_757[1] <= T_755 - node T_761 = bit(T_719, 0) - node T_762 = bit(T_719, 1) - wire T_764 : UInt<1>[2] - T_764[0] <= T_761 - T_764[1] <= T_762 - write mport T_770 = T_748[waddr], clk - when T_764[0] : - T_770[0] <= T_757[0] - skip - when T_764[1] : - T_770[1] <= T_757[1] - skip - skip - node T_775 = neq(T_720, UInt<1>("h00")) - node T_776 = and(T_775, io.read.valid) - poison T_777 : UInt<8> - node T_778 = mux(T_776, raddr, T_777) - read mport T_781 = T_748[T_778], clk - node T_785 = cat(T_781[1], T_781[0]) - T_729[0] <= T_785 - smem T_798 : UInt<64>[2][256] - node T_800 = neq(T_719, UInt<1>("h00")) - node T_801 = and(T_800, io.write.valid) - node T_802 = bit(io.write.bits.wmask, 1) - node T_803 = and(T_801, T_802) - when T_803 : - node T_804 = bits(io.write.bits.data, 127, 64) - node T_805 = bits(io.write.bits.data, 127, 64) - wire T_807 : UInt<64>[2] - T_807[0] <= T_804 - T_807[1] <= T_805 - node T_811 = bit(T_719, 0) - node T_812 = bit(T_719, 1) - wire T_814 : UInt<1>[2] - T_814[0] <= T_811 - T_814[1] <= T_812 - write mport T_820 = T_798[waddr], clk - when T_814[0] : - T_820[0] <= T_807[0] - skip - when T_814[1] : - T_820[1] <= T_807[1] - skip - skip - node T_825 = neq(T_720, UInt<1>("h00")) - node T_826 = and(T_825, io.read.valid) - poison T_827 : UInt<8> - node T_828 = mux(T_826, raddr, T_827) - read mport T_831 = T_798[T_828], clk - node T_835 = cat(T_831[1], T_831[0]) - T_729[1] <= T_835 - node T_836 = bits(T_729[0], 63, 0) - node T_837 = bits(T_729[1], 63, 0) - wire T_839 : UInt<64>[2] - T_839[0] <= T_836 - T_839[1] <= T_837 - node T_843 = bits(T_735, 3, 3) - wire T_846 : UInt<64>[2] - T_846[0] <= T_839[T_843] - T_846[1] <= T_839[1] - node T_850 = cat(T_846[1], T_846[0]) - io.resp[2] <= T_850 - node T_851 = bits(T_729[0], 127, 64) - node T_852 = bits(T_729[1], 127, 64) - wire T_854 : UInt<64>[2] - T_854[0] <= T_851 - T_854[1] <= T_852 - node T_858 = bits(T_735, 3, 3) - wire T_861 : UInt<64>[2] - T_861[0] <= T_854[T_858] - T_861[1] <= T_854[1] - node T_865 = cat(T_861[1], T_861[0]) - io.resp[3] <= T_865 + T_731 <= io.read.bits.addr + skip + smem T_744 : UInt<64>[2][256] + node T_746 = neq(T_717, UInt<1>("h00")) + node T_747 = and(T_746, io.write.valid) + node T_748 = bits(io.write.bits.wmask, 0, 0) + node T_749 = and(T_747, T_748) + when T_749 : + node T_750 = bits(io.write.bits.data, 63, 0) + node T_751 = bits(io.write.bits.data, 63, 0) + wire T_753 : UInt<64>[2] + T_753[0] <= T_750 + T_753[1] <= T_751 + node T_757 = bits(T_717, 0, 0) + node T_758 = bits(T_717, 1, 1) + wire T_760 : UInt<1>[2] + T_760[0] <= T_757 + T_760[1] <= T_758 + write mport T_766 = T_744[waddr], clk + when T_760[0] : + T_766[0] <= T_753[0] + skip + when T_760[1] : + T_766[1] <= T_753[1] + skip + skip + node T_771 = neq(T_718, UInt<1>("h00")) + node T_772 = and(T_771, io.read.valid) + wire T_774 : UInt<?> + T_774 is invalid + when T_772 : + T_774 <= raddr + skip + read mport T_777 = T_744[T_774], clk + node T_781 = cat(T_777[1], T_777[0]) + T_727[0] <= T_781 + smem T_794 : UInt<64>[2][256] + node T_796 = neq(T_717, UInt<1>("h00")) + node T_797 = and(T_796, io.write.valid) + node T_798 = bits(io.write.bits.wmask, 1, 1) + node T_799 = and(T_797, T_798) + when T_799 : + node T_800 = bits(io.write.bits.data, 127, 64) + node T_801 = bits(io.write.bits.data, 127, 64) + wire T_803 : UInt<64>[2] + T_803[0] <= T_800 + T_803[1] <= T_801 + node T_807 = bits(T_717, 0, 0) + node T_808 = bits(T_717, 1, 1) + wire T_810 : UInt<1>[2] + T_810[0] <= T_807 + T_810[1] <= T_808 + write mport T_816 = T_794[waddr], clk + when T_810[0] : + T_816[0] <= T_803[0] + skip + when T_810[1] : + T_816[1] <= T_803[1] + skip + skip + node T_821 = neq(T_718, UInt<1>("h00")) + node T_822 = and(T_821, io.read.valid) + wire T_824 : UInt<?> + T_824 is invalid + when T_822 : + T_824 <= raddr + skip + read mport T_827 = T_794[T_824], clk + node T_831 = cat(T_827[1], T_827[0]) + T_727[1] <= T_831 + node T_832 = bits(T_727[0], 63, 0) + node T_833 = bits(T_727[1], 63, 0) + wire T_835 : UInt<64>[2] + T_835[0] <= T_832 + T_835[1] <= T_833 + node T_839 = bits(T_731, 3, 3) + wire T_842 : UInt<64>[2] + T_842[0] <= T_835[T_839] + T_842[1] <= T_835[1] + node T_846 = cat(T_842[1], T_842[0]) + io.resp[2] <= T_846 + node T_847 = bits(T_727[0], 127, 64) + node T_848 = bits(T_727[1], 127, 64) + wire T_850 : UInt<64>[2] + T_850[0] <= T_847 + T_850[1] <= T_848 + node T_854 = bits(T_731, 3, 3) + wire T_857 : UInt<64>[2] + T_857[0] <= T_850[T_854] + T_857[1] <= T_850[1] + node T_861 = cat(T_857[1], T_857[0]) + io.resp[3] <= T_861 io.read.ready <= UInt<1>("h01") io.write.ready <= UInt<1>("h01") @@ -31754,90 +24349,76 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}[4], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>}}, chosen : UInt<2>} - io.chosen <= UInt<1>("h00") - io.out.bits.addr <= UInt<1>("h00") - io.out.bits.way_en <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") - io.in[2].ready <= UInt<1>("h00") - io.in[3].ready <= UInt<1>("h00") + io is invalid wire T_1524 : UInt<2> - T_1524 <= UInt<1>("h00") + T_1524 is invalid io.out.valid <= io.in[T_1524].valid io.out.bits <- io.in[T_1524].bits io.chosen <= T_1524 io.in[T_1524].ready <= UInt<1>("h00") - node T_1832 = or(UInt<1>("h00"), io.in[0].valid) - node T_1834 = eq(T_1832, UInt<1>("h00")) - node T_1836 = or(UInt<1>("h00"), io.in[0].valid) - node T_1837 = or(T_1836, io.in[1].valid) - node T_1839 = eq(T_1837, UInt<1>("h00")) - node T_1841 = or(UInt<1>("h00"), io.in[0].valid) - node T_1842 = or(T_1841, io.in[1].valid) - node T_1843 = or(T_1842, io.in[2].valid) - node T_1845 = eq(T_1843, UInt<1>("h00")) - node T_1847 = eq(UInt<2>("h03"), UInt<1>("h00")) - node T_1848 = mux(UInt<1>("h00"), T_1847, UInt<1>("h01")) - node T_1849 = and(T_1848, io.out.ready) - io.in[0].ready <= T_1849 - node T_1851 = eq(UInt<2>("h03"), UInt<1>("h01")) - node T_1852 = mux(UInt<1>("h00"), T_1851, T_1834) - node T_1853 = and(T_1852, io.out.ready) - io.in[1].ready <= T_1853 - node T_1855 = eq(UInt<2>("h03"), UInt<2>("h02")) - node T_1856 = mux(UInt<1>("h00"), T_1855, T_1839) - node T_1857 = and(T_1856, io.out.ready) - io.in[2].ready <= T_1857 - node T_1859 = eq(UInt<2>("h03"), UInt<2>("h03")) - node T_1860 = mux(UInt<1>("h00"), T_1859, T_1845) - node T_1861 = and(T_1860, io.out.ready) - io.in[3].ready <= T_1861 - node T_1864 = mux(io.in[2].valid, UInt<2>("h02"), UInt<2>("h03")) - node T_1866 = mux(io.in[1].valid, UInt<1>("h01"), T_1864) - node T_1868 = mux(io.in[0].valid, UInt<1>("h00"), T_1866) - node T_1869 = mux(UInt<1>("h00"), UInt<2>("h03"), T_1868) - T_1524 <= T_1869 + node T_1831 = or(UInt<1>("h00"), io.in[0].valid) + node T_1833 = eq(T_1831, UInt<1>("h00")) + node T_1835 = or(UInt<1>("h00"), io.in[0].valid) + node T_1836 = or(T_1835, io.in[1].valid) + node T_1838 = eq(T_1836, UInt<1>("h00")) + node T_1840 = or(UInt<1>("h00"), io.in[0].valid) + node T_1841 = or(T_1840, io.in[1].valid) + node T_1842 = or(T_1841, io.in[2].valid) + node T_1844 = eq(T_1842, UInt<1>("h00")) + node T_1846 = eq(UInt<2>("h03"), UInt<1>("h00")) + node T_1847 = mux(UInt<1>("h00"), T_1846, UInt<1>("h01")) + node T_1848 = and(T_1847, io.out.ready) + io.in[0].ready <= T_1848 + node T_1850 = eq(UInt<2>("h03"), UInt<1>("h01")) + node T_1851 = mux(UInt<1>("h00"), T_1850, T_1833) + node T_1852 = and(T_1851, io.out.ready) + io.in[1].ready <= T_1852 + node T_1854 = eq(UInt<2>("h03"), UInt<2>("h02")) + node T_1855 = mux(UInt<1>("h00"), T_1854, T_1838) + node T_1856 = and(T_1855, io.out.ready) + io.in[2].ready <= T_1856 + node T_1858 = eq(UInt<2>("h03"), UInt<2>("h03")) + node T_1859 = mux(UInt<1>("h00"), T_1858, T_1844) + node T_1860 = and(T_1859, io.out.ready) + io.in[3].ready <= T_1860 + node T_1863 = mux(io.in[2].valid, UInt<2>("h02"), UInt<2>("h03")) + node T_1865 = mux(io.in[1].valid, UInt<1>("h01"), T_1863) + node T_1867 = mux(io.in[0].valid, UInt<1>("h00"), T_1865) + node T_1868 = mux(UInt<1>("h00"), UInt<2>("h03"), T_1867) + T_1524 <= T_1868 module Arbiter_108 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {way_en : UInt<4>, addr : UInt<12>, wmask : UInt<2>, data : UInt<128>}}, chosen : UInt<1>} - io.chosen <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.bits.wmask <= UInt<1>("h00") - io.out.bits.addr <= UInt<1>("h00") - io.out.bits.way_en <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") + io is invalid wire T_1164 : UInt<1> - T_1164 <= UInt<1>("h00") + T_1164 is invalid io.out.valid <= io.in[T_1164].valid io.out.bits <- io.in[T_1164].bits io.chosen <= T_1164 io.in[T_1164].ready <= UInt<1>("h00") - node T_1484 = or(UInt<1>("h00"), io.in[0].valid) - node T_1486 = eq(T_1484, UInt<1>("h00")) - node T_1488 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_1489 = mux(UInt<1>("h00"), T_1488, UInt<1>("h01")) - node T_1490 = and(T_1489, io.out.ready) - io.in[0].ready <= T_1490 - node T_1492 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_1493 = mux(UInt<1>("h00"), T_1492, T_1486) - node T_1494 = and(T_1493, io.out.ready) - io.in[1].ready <= T_1494 - node T_1497 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_1498 = mux(UInt<1>("h00"), UInt<1>("h01"), T_1497) - T_1164 <= T_1498 + node T_1483 = or(UInt<1>("h00"), io.in[0].valid) + node T_1485 = eq(T_1483, UInt<1>("h00")) + node T_1487 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_1488 = mux(UInt<1>("h00"), T_1487, UInt<1>("h01")) + node T_1489 = and(T_1488, io.out.ready) + io.in[0].ready <= T_1489 + node T_1491 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_1492 = mux(UInt<1>("h00"), T_1491, T_1485) + node T_1493 = and(T_1492, io.out.ready) + io.in[1].ready <= T_1493 + node T_1496 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_1497 = mux(UInt<1>("h00"), UInt<1>("h01"), T_1496) + T_1164 <= T_1497 module AMOALU : input clk : Clock input reset : UInt<1> output io : {flip addr : UInt<6>, flip cmd : UInt<5>, flip typ : UInt<3>, flip lhs : UInt<64>, flip rhs : UInt<64>, out : UInt<64>} - io.out <= UInt<1>("h00") + io is invalid node T_10 = bits(io.typ, 1, 0) node T_12 = eq(T_10, UInt<2>("h02")) node T_13 = bits(io.rhs, 31, 0) @@ -31860,175 +24441,176 @@ circuit Top : node T_30 = eq(io.typ, UInt<3>("h04")) node word = or(T_29, T_30) node T_33 = not(UInt<64>("h00")) - node T_34 = bit(io.addr, 2) + node T_34 = bits(io.addr, 2, 2) node T_35 = shl(T_34, 31) node mask = xor(T_33, T_35) node T_37 = and(io.lhs, mask) node T_38 = and(rhs, mask) - node adder_out = addw(T_37, T_38) - node T_40 = bit(io.addr, 2) - node T_42 = eq(T_40, UInt<1>("h00")) - node T_43 = and(word, T_42) - node T_44 = bit(io.lhs, 31) - node T_45 = bit(io.lhs, 63) - node cmp_lhs = mux(T_43, T_44, T_45) - node T_47 = bit(io.addr, 2) - node T_49 = eq(T_47, UInt<1>("h00")) - node T_50 = and(word, T_49) - node T_51 = bit(rhs, 31) - node T_52 = bit(rhs, 63) - node cmp_rhs = mux(T_50, T_51, T_52) - node T_54 = bits(io.lhs, 31, 0) - node T_55 = bits(rhs, 31, 0) - node lt_lo = lt(T_54, T_55) - node T_57 = bits(io.lhs, 63, 32) - node T_58 = bits(rhs, 63, 32) - node lt_hi = lt(T_57, T_58) - node T_60 = bits(io.lhs, 63, 32) - node T_61 = bits(rhs, 63, 32) - node eq_hi = eq(T_60, T_61) - node T_63 = bit(io.addr, 2) - node T_64 = mux(T_63, lt_hi, lt_lo) - node T_65 = and(eq_hi, lt_lo) - node T_66 = or(lt_hi, T_65) - node lt = mux(word, T_64, T_66) - node T_68 = eq(cmp_lhs, cmp_rhs) - node T_69 = mux(sgned, cmp_lhs, cmp_rhs) - node less = mux(T_68, lt, T_69) - node T_71 = eq(io.cmd, UInt<5>("h08")) - node T_72 = eq(io.cmd, UInt<5>("h0b")) - node T_73 = and(io.lhs, rhs) - node T_74 = eq(io.cmd, UInt<5>("h0a")) - node T_75 = or(io.lhs, rhs) - node T_76 = eq(io.cmd, UInt<5>("h09")) - node T_77 = xor(io.lhs, rhs) - node T_78 = mux(less, min, max) - node T_80 = eq(T_10, UInt<1>("h00")) - node T_81 = bits(io.rhs, 7, 0) - node T_82 = cat(T_81, T_81) + node T_39 = add(T_37, T_38) + node adder_out = tail(T_39, 1) + node T_41 = bits(io.addr, 2, 2) + node T_43 = eq(T_41, UInt<1>("h00")) + node T_44 = and(word, T_43) + node T_45 = bits(io.lhs, 31, 31) + node T_46 = bits(io.lhs, 63, 63) + node cmp_lhs = mux(T_44, T_45, T_46) + node T_48 = bits(io.addr, 2, 2) + node T_50 = eq(T_48, UInt<1>("h00")) + node T_51 = and(word, T_50) + node T_52 = bits(rhs, 31, 31) + node T_53 = bits(rhs, 63, 63) + node cmp_rhs = mux(T_51, T_52, T_53) + node T_55 = bits(io.lhs, 31, 0) + node T_56 = bits(rhs, 31, 0) + node lt_lo = lt(T_55, T_56) + node T_58 = bits(io.lhs, 63, 32) + node T_59 = bits(rhs, 63, 32) + node lt_hi = lt(T_58, T_59) + node T_61 = bits(io.lhs, 63, 32) + node T_62 = bits(rhs, 63, 32) + node eq_hi = eq(T_61, T_62) + node T_64 = bits(io.addr, 2, 2) + node T_65 = mux(T_64, lt_hi, lt_lo) + node T_66 = and(eq_hi, lt_lo) + node T_67 = or(lt_hi, T_66) + node lt = mux(word, T_65, T_67) + node T_69 = eq(cmp_lhs, cmp_rhs) + node T_70 = mux(sgned, cmp_lhs, cmp_rhs) + node less = mux(T_69, lt, T_70) + node T_72 = eq(io.cmd, UInt<5>("h08")) + node T_73 = eq(io.cmd, UInt<5>("h0b")) + node T_74 = and(io.lhs, rhs) + node T_75 = eq(io.cmd, UInt<5>("h0a")) + node T_76 = or(io.lhs, rhs) + node T_77 = eq(io.cmd, UInt<5>("h09")) + node T_78 = xor(io.lhs, rhs) + node T_79 = mux(less, min, max) + node T_81 = eq(T_10, UInt<1>("h00")) + node T_82 = bits(io.rhs, 7, 0) node T_83 = cat(T_82, T_82) node T_84 = cat(T_83, T_83) - node T_86 = eq(T_10, UInt<1>("h01")) - node T_87 = bits(io.rhs, 15, 0) - node T_88 = cat(T_87, T_87) + node T_85 = cat(T_84, T_84) + node T_87 = eq(T_10, UInt<1>("h01")) + node T_88 = bits(io.rhs, 15, 0) node T_89 = cat(T_88, T_88) - node T_91 = eq(T_10, UInt<2>("h02")) - node T_92 = bits(io.rhs, 31, 0) - node T_93 = cat(T_92, T_92) - node T_94 = mux(T_91, T_93, io.rhs) - node T_95 = mux(T_86, T_89, T_94) - node T_96 = mux(T_80, T_84, T_95) - node T_97 = mux(T_78, io.lhs, T_96) - node T_98 = mux(T_76, T_77, T_97) - node T_99 = mux(T_74, T_75, T_98) - node T_100 = mux(T_72, T_73, T_99) - node out = mux(T_71, adder_out, T_100) - node T_103 = bit(io.addr, 0) - node T_105 = mux(T_103, UInt<1>("h01"), UInt<1>("h00")) - node T_107 = geq(T_10, UInt<1>("h01")) - node T_110 = mux(T_107, UInt<1>("h01"), UInt<1>("h00")) - node T_111 = or(T_105, T_110) - node T_112 = bit(io.addr, 0) - node T_114 = mux(T_112, UInt<1>("h00"), UInt<1>("h01")) - node T_115 = cat(T_111, T_114) - node T_116 = bit(io.addr, 1) - node T_118 = mux(T_116, T_115, UInt<1>("h00")) - node T_120 = geq(T_10, UInt<2>("h02")) - node T_123 = mux(T_120, UInt<2>("h03"), UInt<1>("h00")) - node T_124 = or(T_118, T_123) - node T_125 = bit(io.addr, 1) - node T_127 = mux(T_125, UInt<1>("h00"), T_115) - node T_128 = cat(T_124, T_127) - node T_129 = bit(io.addr, 2) - node T_131 = mux(T_129, T_128, UInt<1>("h00")) - node T_133 = geq(T_10, UInt<2>("h03")) - node T_136 = mux(T_133, UInt<4>("h0f"), UInt<1>("h00")) - node T_137 = or(T_131, T_136) - node T_138 = bit(io.addr, 2) - node T_140 = mux(T_138, UInt<1>("h00"), T_128) - node T_141 = cat(T_137, T_140) - node T_142 = bit(T_141, 0) - node T_143 = bit(T_141, 1) - node T_144 = bit(T_141, 2) - node T_145 = bit(T_141, 3) - node T_146 = bit(T_141, 4) - node T_147 = bit(T_141, 5) - node T_148 = bit(T_141, 6) - node T_149 = bit(T_141, 7) - wire T_151 : UInt<1>[8] - T_151[0] <= T_142 - T_151[1] <= T_143 - T_151[2] <= T_144 - T_151[3] <= T_145 - T_151[4] <= T_146 - T_151[5] <= T_147 - T_151[6] <= T_148 - T_151[7] <= T_149 - node T_162 = subw(UInt<8>("h00"), T_151[0]) - node T_164 = subw(UInt<8>("h00"), T_151[1]) - node T_166 = subw(UInt<8>("h00"), T_151[2]) - node T_168 = subw(UInt<8>("h00"), T_151[3]) - node T_170 = subw(UInt<8>("h00"), T_151[4]) - node T_172 = subw(UInt<8>("h00"), T_151[5]) - node T_174 = subw(UInt<8>("h00"), T_151[6]) - node T_176 = subw(UInt<8>("h00"), T_151[7]) - wire T_178 : UInt<8>[8] - T_178[0] <= T_162 - T_178[1] <= T_164 - T_178[2] <= T_166 - T_178[3] <= T_168 - T_178[4] <= T_170 - T_178[5] <= T_172 - T_178[6] <= T_174 - T_178[7] <= T_176 - node T_188 = cat(T_178[7], T_178[6]) - node T_189 = cat(T_178[5], T_178[4]) - node T_190 = cat(T_188, T_189) - node T_191 = cat(T_178[3], T_178[2]) - node T_192 = cat(T_178[1], T_178[0]) - node T_193 = cat(T_191, T_192) - node wmask = cat(T_190, T_193) - node T_195 = and(wmask, out) - node T_196 = not(wmask) - node T_197 = and(T_196, io.lhs) - node T_198 = or(T_195, T_197) - io.out <= T_198 + node T_90 = cat(T_89, T_89) + node T_92 = eq(T_10, UInt<2>("h02")) + node T_93 = bits(io.rhs, 31, 0) + node T_94 = cat(T_93, T_93) + node T_95 = mux(T_92, T_94, io.rhs) + node T_96 = mux(T_87, T_90, T_95) + node T_97 = mux(T_81, T_85, T_96) + node T_98 = mux(T_79, io.lhs, T_97) + node T_99 = mux(T_77, T_78, T_98) + node T_100 = mux(T_75, T_76, T_99) + node T_101 = mux(T_73, T_74, T_100) + node out = mux(T_72, adder_out, T_101) + node T_104 = bits(io.addr, 0, 0) + node T_106 = mux(T_104, UInt<1>("h01"), UInt<1>("h00")) + node T_108 = geq(T_10, UInt<1>("h01")) + node T_111 = mux(T_108, UInt<1>("h01"), UInt<1>("h00")) + node T_112 = or(T_106, T_111) + node T_113 = bits(io.addr, 0, 0) + node T_115 = mux(T_113, UInt<1>("h00"), UInt<1>("h01")) + node T_116 = cat(T_112, T_115) + node T_117 = bits(io.addr, 1, 1) + node T_119 = mux(T_117, T_116, UInt<1>("h00")) + node T_121 = geq(T_10, UInt<2>("h02")) + node T_124 = mux(T_121, UInt<2>("h03"), UInt<1>("h00")) + node T_125 = or(T_119, T_124) + node T_126 = bits(io.addr, 1, 1) + node T_128 = mux(T_126, UInt<1>("h00"), T_116) + node T_129 = cat(T_125, T_128) + node T_130 = bits(io.addr, 2, 2) + node T_132 = mux(T_130, T_129, UInt<1>("h00")) + node T_134 = geq(T_10, UInt<2>("h03")) + node T_137 = mux(T_134, UInt<4>("h0f"), UInt<1>("h00")) + node T_138 = or(T_132, T_137) + node T_139 = bits(io.addr, 2, 2) + node T_141 = mux(T_139, UInt<1>("h00"), T_129) + node T_142 = cat(T_138, T_141) + node T_143 = bits(T_142, 0, 0) + node T_144 = bits(T_142, 1, 1) + node T_145 = bits(T_142, 2, 2) + node T_146 = bits(T_142, 3, 3) + node T_147 = bits(T_142, 4, 4) + node T_148 = bits(T_142, 5, 5) + node T_149 = bits(T_142, 6, 6) + node T_150 = bits(T_142, 7, 7) + wire T_152 : UInt<1>[8] + T_152[0] <= T_143 + T_152[1] <= T_144 + T_152[2] <= T_145 + T_152[3] <= T_146 + T_152[4] <= T_147 + T_152[5] <= T_148 + T_152[6] <= T_149 + T_152[7] <= T_150 + node T_163 = sub(UInt<8>("h00"), T_152[0]) + node T_164 = tail(T_163, 1) + node T_166 = sub(UInt<8>("h00"), T_152[1]) + node T_167 = tail(T_166, 1) + node T_169 = sub(UInt<8>("h00"), T_152[2]) + node T_170 = tail(T_169, 1) + node T_172 = sub(UInt<8>("h00"), T_152[3]) + node T_173 = tail(T_172, 1) + node T_175 = sub(UInt<8>("h00"), T_152[4]) + node T_176 = tail(T_175, 1) + node T_178 = sub(UInt<8>("h00"), T_152[5]) + node T_179 = tail(T_178, 1) + node T_181 = sub(UInt<8>("h00"), T_152[6]) + node T_182 = tail(T_181, 1) + node T_184 = sub(UInt<8>("h00"), T_152[7]) + node T_185 = tail(T_184, 1) + wire T_187 : UInt<8>[8] + T_187[0] <= T_164 + T_187[1] <= T_167 + T_187[2] <= T_170 + T_187[3] <= T_173 + T_187[4] <= T_176 + T_187[5] <= T_179 + T_187[6] <= T_182 + T_187[7] <= T_185 + node T_197 = cat(T_187[7], T_187[6]) + node T_198 = cat(T_187[5], T_187[4]) + node T_199 = cat(T_197, T_198) + node T_200 = cat(T_187[3], T_187[2]) + node T_201 = cat(T_187[1], T_187[0]) + node T_202 = cat(T_200, T_201) + node wmask = cat(T_199, T_202) + node T_204 = and(wmask, out) + node T_205 = not(wmask) + node T_206 = and(T_205, io.lhs) + node T_207 = or(T_204, T_206) + io.out <= T_207 module LockingArbiter_109 : input clk : Clock input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}, chosen : UInt<1>} - io.chosen <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.bits.r_type <= UInt<1>("h00") - io.out.bits.voluntary <= UInt<1>("h00") - io.out.bits.client_xact_id <= UInt<1>("h00") - io.out.bits.addr_block <= UInt<1>("h00") - io.out.bits.addr_beat <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") - reg T_700 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_702 : UInt<?>, clk, reset, UInt<1>("h01") + io is invalid + reg T_700 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_702 : UInt<?>, clk with : (reset => (reset, UInt<1>("h01"))) wire T_704 : UInt<1> - T_704 <= UInt<1>("h00") + T_704 is invalid io.out.valid <= io.in[T_704].valid io.out.bits <- io.in[T_704].bits io.chosen <= T_704 io.in[T_704].ready <= UInt<1>("h00") - node T_898 = or(UInt<1>("h00"), io.in[0].valid) - node T_900 = eq(T_898, UInt<1>("h00")) - node T_902 = eq(T_702, UInt<1>("h00")) - node T_903 = mux(T_700, T_902, UInt<1>("h01")) - node T_904 = and(T_903, io.out.ready) - io.in[0].ready <= T_904 - node T_906 = eq(T_702, UInt<1>("h01")) - node T_907 = mux(T_700, T_906, T_900) - node T_908 = and(T_907, io.out.ready) - io.in[1].ready <= T_908 - reg T_910 : UInt<2>, clk, reset, UInt<2>("h00") - node T_912 = addw(T_910, UInt<1>("h01")) + node T_897 = or(UInt<1>("h00"), io.in[0].valid) + node T_899 = eq(T_897, UInt<1>("h00")) + node T_901 = eq(T_702, UInt<1>("h00")) + node T_902 = mux(T_700, T_901, UInt<1>("h01")) + node T_903 = and(T_902, io.out.ready) + io.in[0].ready <= T_903 + node T_905 = eq(T_702, UInt<1>("h01")) + node T_906 = mux(T_700, T_905, T_899) + node T_907 = and(T_906, io.out.ready) + io.in[1].ready <= T_907 + reg T_909 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + node T_911 = add(T_909, UInt<1>("h01")) + node T_912 = tail(T_911, 1) node T_913 = and(io.out.ready, io.out.valid) when T_913 : wire T_916 : UInt<2>[3] @@ -32043,7 +24625,7 @@ circuit Top : node T_927 = or(T_926, T_923) node T_928 = and(UInt<1>("h01"), T_927) when T_928 : - T_910 <= T_912 + T_909 <= T_912 node T_930 = eq(T_700, UInt<1>("h00")) when T_930 : T_700 <= UInt<1>("h01") @@ -32070,220 +24652,104 @@ circuit Top : input reset : UInt<1> output io : {flip cpu : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}} - io.mem.release.bits.data <= UInt<1>("h00") - io.mem.release.bits.r_type <= UInt<1>("h00") - io.mem.release.bits.voluntary <= UInt<1>("h00") - io.mem.release.bits.client_xact_id <= UInt<1>("h00") - io.mem.release.bits.addr_block <= UInt<1>("h00") - io.mem.release.bits.addr_beat <= UInt<1>("h00") - io.mem.release.valid <= UInt<1>("h00") - io.mem.probe.ready <= UInt<1>("h00") - io.mem.grant.ready <= UInt<1>("h00") - io.mem.acquire.bits.data <= UInt<1>("h00") - io.mem.acquire.bits.union <= UInt<1>("h00") - io.mem.acquire.bits.a_type <= UInt<1>("h00") - io.mem.acquire.bits.is_builtin_type <= UInt<1>("h00") - io.mem.acquire.bits.addr_beat <= UInt<1>("h00") - io.mem.acquire.bits.client_xact_id <= UInt<1>("h00") - io.mem.acquire.bits.addr_block <= UInt<1>("h00") - io.mem.acquire.valid <= UInt<1>("h00") - io.ptw.req.bits.fetch <= UInt<1>("h00") - io.ptw.req.bits.store <= UInt<1>("h00") - io.ptw.req.bits.prv <= UInt<1>("h00") - io.ptw.req.bits.addr <= UInt<1>("h00") - io.ptw.req.valid <= UInt<1>("h00") - io.cpu.ordered <= UInt<1>("h00") - io.cpu.xcpt.pf.st <= UInt<1>("h00") - io.cpu.xcpt.pf.ld <= UInt<1>("h00") - io.cpu.xcpt.ma.st <= UInt<1>("h00") - io.cpu.xcpt.ma.ld <= UInt<1>("h00") - io.cpu.replay_next.bits <= UInt<1>("h00") - io.cpu.replay_next.valid <= UInt<1>("h00") - io.cpu.resp.bits.store_data <= UInt<1>("h00") - io.cpu.resp.bits.data_word_bypass <= UInt<1>("h00") - io.cpu.resp.bits.has_data <= UInt<1>("h00") - io.cpu.resp.bits.replay <= UInt<1>("h00") - io.cpu.resp.bits.nack <= UInt<1>("h00") - io.cpu.resp.bits.data <= UInt<1>("h00") - io.cpu.resp.bits.typ <= UInt<1>("h00") - io.cpu.resp.bits.cmd <= UInt<1>("h00") - io.cpu.resp.bits.tag <= UInt<1>("h00") - io.cpu.resp.bits.addr <= UInt<1>("h00") - io.cpu.resp.valid <= UInt<1>("h00") - io.cpu.req.ready <= UInt<1>("h00") + io is invalid inst wb of WritebackUnit - wb.io.release.ready <= UInt<1>("h00") - wb.io.data_resp <= UInt<1>("h00") - wb.io.data_req.ready <= UInt<1>("h00") - wb.io.meta_read.ready <= UInt<1>("h00") - wb.io.req.bits.way_en <= UInt<1>("h00") - wb.io.req.bits.data <= UInt<1>("h00") - wb.io.req.bits.r_type <= UInt<1>("h00") - wb.io.req.bits.voluntary <= UInt<1>("h00") - wb.io.req.bits.client_xact_id <= UInt<1>("h00") - wb.io.req.bits.addr_block <= UInt<1>("h00") - wb.io.req.bits.addr_beat <= UInt<1>("h00") - wb.io.req.valid <= UInt<1>("h00") + wb.io is invalid wb.clk <= clk wb.reset <= reset inst prober of ProbeUnit - prober.io.block_state.state <= UInt<1>("h00") - prober.io.mshr_rdy <= UInt<1>("h00") - prober.io.way_en <= UInt<1>("h00") - prober.io.wb_req.ready <= UInt<1>("h00") - prober.io.meta_write.ready <= UInt<1>("h00") - prober.io.meta_read.ready <= UInt<1>("h00") - prober.io.rep.ready <= UInt<1>("h00") - prober.io.req.bits.client_xact_id <= UInt<1>("h00") - prober.io.req.bits.p_type <= UInt<1>("h00") - prober.io.req.bits.addr_block <= UInt<1>("h00") - prober.io.req.valid <= UInt<1>("h00") + prober.io is invalid prober.clk <= clk prober.reset <= reset inst mshrs of MSHRFile - mshrs.io.wb_req.ready <= UInt<1>("h00") - mshrs.io.mem_grant.bits.data <= UInt<1>("h00") - mshrs.io.mem_grant.bits.g_type <= UInt<1>("h00") - mshrs.io.mem_grant.bits.is_builtin_type <= UInt<1>("h00") - mshrs.io.mem_grant.bits.manager_xact_id <= UInt<1>("h00") - mshrs.io.mem_grant.bits.client_xact_id <= UInt<1>("h00") - mshrs.io.mem_grant.bits.addr_beat <= UInt<1>("h00") - mshrs.io.mem_grant.valid <= UInt<1>("h00") - mshrs.io.replay.ready <= UInt<1>("h00") - mshrs.io.meta_write.ready <= UInt<1>("h00") - mshrs.io.meta_read.ready <= UInt<1>("h00") - mshrs.io.mem_req.ready <= UInt<1>("h00") - mshrs.io.resp.ready <= UInt<1>("h00") - mshrs.io.req.bits.way_en <= UInt<1>("h00") - mshrs.io.req.bits.old_meta.coh.state <= UInt<1>("h00") - mshrs.io.req.bits.old_meta.tag <= UInt<1>("h00") - mshrs.io.req.bits.tag_match <= UInt<1>("h00") - mshrs.io.req.bits.data <= UInt<1>("h00") - mshrs.io.req.bits.phys <= UInt<1>("h00") - mshrs.io.req.bits.kill <= UInt<1>("h00") - mshrs.io.req.bits.typ <= UInt<1>("h00") - mshrs.io.req.bits.cmd <= UInt<1>("h00") - mshrs.io.req.bits.tag <= UInt<1>("h00") - mshrs.io.req.bits.addr <= UInt<1>("h00") - mshrs.io.req.valid <= UInt<1>("h00") + mshrs.io is invalid mshrs.clk <= clk mshrs.reset <= reset io.cpu.req.ready <= UInt<1>("h01") - node T_1670 = and(io.cpu.req.ready, io.cpu.req.valid) - reg s1_valid : UInt<1>, clk, reset, UInt<1>("h00") - s1_valid <= T_1670 - reg s1_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk, UInt<1>("h00"), s1_req - node T_1728 = eq(io.cpu.req.bits.kill, UInt<1>("h00")) - node s1_valid_masked = and(s1_valid, T_1728) - reg s1_replay : UInt<1>, clk, reset, UInt<1>("h00") - reg s1_clk_en : UInt<1>, clk, UInt<1>("h00"), s1_clk_en - reg s2_valid : UInt<1>, clk, reset, UInt<1>("h00") + node T_1622 = and(io.cpu.req.ready, io.cpu.req.valid) + reg s1_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + s1_valid <= T_1622 + reg s1_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk + node T_1680 = eq(io.cpu.req.bits.kill, UInt<1>("h00")) + node s1_valid_masked = and(s1_valid, T_1680) + reg s1_replay : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg s1_clk_en : UInt<1>, clk + reg s2_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) s2_valid <= s1_valid_masked - node T_1736 = and(s1_valid, io.cpu.req.bits.kill) - reg s2_killed : UInt<1>, clk, UInt<1>("h00"), s2_killed - s2_killed <= T_1736 - reg s2_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk, UInt<1>("h00"), s2_req - reg T_1793 : UInt<1>, clk, reset, UInt<1>("h00") - T_1793 <= s1_replay - node T_1794 = neq(s2_req.cmd, UInt<5>("h05")) - node s2_replay = and(T_1793, T_1794) + node T_1688 = and(s1_valid, io.cpu.req.bits.kill) + reg s2_killed : UInt<1>, clk + s2_killed <= T_1688 + reg s2_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk + reg T_1745 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + T_1745 <= s1_replay + node T_1746 = neq(s2_req.cmd, UInt<5>("h05")) + node s2_replay = and(T_1745, T_1746) wire s2_recycle : UInt<1> - s2_recycle <= UInt<1>("h00") + s2_recycle is invalid wire s2_valid_masked : UInt<1> - s2_valid_masked <= UInt<1>("h00") - reg s3_valid : UInt<1>, clk, reset, UInt<1>("h00") - reg s3_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk, UInt<1>("h00"), s3_req - reg s3_way : UInt<?>, clk, UInt<1>("h00"), s3_way - reg s1_recycled : UInt<1>, clk, reset, UInt<1>("h00") + s2_valid_masked is invalid + reg s3_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg s3_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk + reg s3_way : UInt<?>, clk + reg s1_recycled : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) when s1_clk_en : s1_recycled <= s2_recycle skip - node T_1862 = eq(s1_req.cmd, UInt<5>("h00")) - node T_1863 = eq(s1_req.cmd, UInt<5>("h06")) - node T_1864 = or(T_1862, T_1863) - node T_1865 = eq(s1_req.cmd, UInt<5>("h07")) - node T_1866 = or(T_1864, T_1865) - node T_1867 = bit(s1_req.cmd, 3) - node T_1868 = eq(s1_req.cmd, UInt<5>("h04")) - node T_1869 = or(T_1867, T_1868) - node s1_read = or(T_1866, T_1869) - node T_1871 = eq(s1_req.cmd, UInt<5>("h01")) - node T_1872 = eq(s1_req.cmd, UInt<5>("h07")) - node T_1873 = or(T_1871, T_1872) - node T_1874 = bit(s1_req.cmd, 3) - node T_1875 = eq(s1_req.cmd, UInt<5>("h04")) - node T_1876 = or(T_1874, T_1875) - node s1_write = or(T_1873, T_1876) - node T_1878 = or(s1_read, s1_write) - node T_1879 = eq(s1_req.cmd, UInt<5>("h02")) - node T_1880 = eq(s1_req.cmd, UInt<5>("h03")) - node T_1881 = or(T_1879, T_1880) - node s1_readwrite = or(T_1878, T_1881) + node T_1812 = eq(s1_req.cmd, UInt<5>("h00")) + node T_1813 = eq(s1_req.cmd, UInt<5>("h06")) + node T_1814 = or(T_1812, T_1813) + node T_1815 = eq(s1_req.cmd, UInt<5>("h07")) + node T_1816 = or(T_1814, T_1815) + node T_1817 = bits(s1_req.cmd, 3, 3) + node T_1818 = eq(s1_req.cmd, UInt<5>("h04")) + node T_1819 = or(T_1817, T_1818) + node s1_read = or(T_1816, T_1819) + node T_1821 = eq(s1_req.cmd, UInt<5>("h01")) + node T_1822 = eq(s1_req.cmd, UInt<5>("h07")) + node T_1823 = or(T_1821, T_1822) + node T_1824 = bits(s1_req.cmd, 3, 3) + node T_1825 = eq(s1_req.cmd, UInt<5>("h04")) + node T_1826 = or(T_1824, T_1825) + node s1_write = or(T_1823, T_1826) + node T_1828 = or(s1_read, s1_write) + node T_1829 = eq(s1_req.cmd, UInt<5>("h02")) + node T_1830 = eq(s1_req.cmd, UInt<5>("h03")) + node T_1831 = or(T_1829, T_1830) + node s1_readwrite = or(T_1828, T_1831) inst dtlb of TLB - dtlb.io.ptw.invalidate <= UInt<1>("h00") - dtlb.io.ptw.status.ie <= UInt<1>("h00") - dtlb.io.ptw.status.prv <= UInt<1>("h00") - dtlb.io.ptw.status.ie1 <= UInt<1>("h00") - dtlb.io.ptw.status.prv1 <= UInt<1>("h00") - dtlb.io.ptw.status.ie2 <= UInt<1>("h00") - dtlb.io.ptw.status.prv2 <= UInt<1>("h00") - dtlb.io.ptw.status.ie3 <= UInt<1>("h00") - dtlb.io.ptw.status.prv3 <= UInt<1>("h00") - dtlb.io.ptw.status.fs <= UInt<1>("h00") - dtlb.io.ptw.status.xs <= UInt<1>("h00") - dtlb.io.ptw.status.mprv <= UInt<1>("h00") - dtlb.io.ptw.status.vm <= UInt<1>("h00") - dtlb.io.ptw.status.zero1 <= UInt<1>("h00") - dtlb.io.ptw.status.sd_rv32 <= UInt<1>("h00") - dtlb.io.ptw.status.zero2 <= UInt<1>("h00") - dtlb.io.ptw.status.sd <= UInt<1>("h00") - dtlb.io.ptw.resp.bits.pte.v <= UInt<1>("h00") - dtlb.io.ptw.resp.bits.pte.typ <= UInt<1>("h00") - dtlb.io.ptw.resp.bits.pte.r <= UInt<1>("h00") - dtlb.io.ptw.resp.bits.pte.d <= UInt<1>("h00") - dtlb.io.ptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") - dtlb.io.ptw.resp.bits.pte.ppn <= UInt<1>("h00") - dtlb.io.ptw.resp.bits.error <= UInt<1>("h00") - dtlb.io.ptw.resp.valid <= UInt<1>("h00") - dtlb.io.ptw.req.ready <= UInt<1>("h00") - dtlb.io.req.bits.store <= UInt<1>("h00") - dtlb.io.req.bits.instruction <= UInt<1>("h00") - dtlb.io.req.bits.passthrough <= UInt<1>("h00") - dtlb.io.req.bits.vpn <= UInt<1>("h00") - dtlb.io.req.bits.asid <= UInt<1>("h00") - dtlb.io.req.valid <= UInt<1>("h00") + dtlb.io is invalid dtlb.clk <= clk dtlb.reset <= reset io.ptw <- dtlb.io.ptw - node T_1916 = and(s1_valid_masked, s1_readwrite) - node T_1918 = eq(s1_req.phys, UInt<1>("h00")) - node T_1919 = and(T_1916, T_1918) - dtlb.io.req.valid <= T_1919 + node T_1834 = and(s1_valid_masked, s1_readwrite) + node T_1836 = eq(s1_req.phys, UInt<1>("h00")) + node T_1837 = and(T_1834, T_1836) + dtlb.io.req.valid <= T_1837 dtlb.io.req.bits.passthrough <= s1_req.phys dtlb.io.req.bits.asid <= UInt<1>("h00") - node T_1921 = shr(s1_req.addr, 12) - dtlb.io.req.bits.vpn <= T_1921 + node T_1839 = shr(s1_req.addr, 12) + dtlb.io.req.bits.vpn <= T_1839 dtlb.io.req.bits.instruction <= UInt<1>("h00") dtlb.io.req.bits.store <= s1_write - node T_1924 = eq(dtlb.io.req.ready, UInt<1>("h00")) - node T_1926 = eq(io.cpu.req.bits.phys, UInt<1>("h00")) - node T_1927 = and(T_1924, T_1926) - when T_1927 : + node T_1842 = eq(dtlb.io.req.ready, UInt<1>("h00")) + node T_1844 = eq(io.cpu.req.bits.phys, UInt<1>("h00")) + node T_1845 = and(T_1842, T_1844) + when T_1845 : io.cpu.req.ready <= UInt<1>("h00") skip when io.cpu.req.valid : s1_req <- io.cpu.req.bits skip when wb.io.meta_read.valid : - node T_1929 = cat(wb.io.meta_read.bits.tag, wb.io.meta_read.bits.idx) - node T_1930 = shl(T_1929, 6) - s1_req.addr <= T_1930 + node T_1847 = cat(wb.io.meta_read.bits.tag, wb.io.meta_read.bits.idx) + node T_1848 = shl(T_1847, 6) + s1_req.addr <= T_1848 s1_req.phys <= UInt<1>("h01") skip when prober.io.meta_read.valid : - node T_1932 = cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) - node T_1933 = shl(T_1932, 6) - s1_req.addr <= T_1933 + node T_1850 = cat(prober.io.meta_read.bits.tag, prober.io.meta_read.bits.idx) + node T_1851 = shl(T_1850, 6) + s1_req.addr <= T_1851 s1_req.phys <= UInt<1>("h01") skip when mshrs.io.replay.valid : @@ -32292,16 +24758,16 @@ circuit Top : when s2_recycle : s1_req <- s2_req skip - node T_1935 = bits(s1_req.addr, 11, 0) - node s1_addr = cat(dtlb.io.resp.ppn, T_1935) + node T_1853 = bits(s1_req.addr, 11, 0) + node s1_addr = cat(dtlb.io.resp.ppn, T_1853) when s1_clk_en : s2_req.kill <= s1_req.kill s2_req.typ <= s1_req.typ s2_req.phys <= s1_req.phys s2_req.addr <= s1_addr when s1_write : - node T_1937 = mux(s1_replay, mshrs.io.replay.bits.data, io.cpu.req.bits.data) - s2_req.data <= T_1937 + node T_1855 = mux(s1_replay, mshrs.io.replay.bits.data, io.cpu.req.bits.data) + s2_req.data <= T_1855 skip when s1_recycled : s2_req.data <= s1_req.data @@ -32309,300 +24775,247 @@ circuit Top : s2_req.tag <= s1_req.tag s2_req.cmd <= s1_req.cmd skip - node T_1939 = bits(s1_req.typ, 1, 0) - node T_1941 = dshl(UInt<1>("h01"), T_1939) - node T_1943 = subw(T_1941, UInt<1>("h01")) - node T_1944 = bits(T_1943, 2, 0) - node T_1945 = and(s1_req.addr, T_1944) - node misaligned = neq(T_1945, UInt<1>("h00")) - node T_1948 = and(s1_read, misaligned) - io.cpu.xcpt.ma.ld <= T_1948 - node T_1949 = and(s1_write, misaligned) - io.cpu.xcpt.ma.st <= T_1949 - node T_1950 = and(s1_read, dtlb.io.resp.xcpt_ld) - io.cpu.xcpt.pf.ld <= T_1950 - node T_1951 = and(s1_write, dtlb.io.resp.xcpt_st) - io.cpu.xcpt.pf.st <= T_1951 - node T_1952 = or(io.cpu.xcpt.ma.ld, io.cpu.xcpt.ma.st) - node T_1953 = or(T_1952, io.cpu.xcpt.pf.ld) - node T_1954 = or(T_1953, io.cpu.xcpt.pf.st) - reg T_1955 : UInt<1>, clk, UInt<1>("h00"), T_1955 - T_1955 <= T_1954 - node T_1956 = and(T_1955, io.cpu.resp.valid) - node T_1958 = eq(T_1956, UInt<1>("h00")) - node T_1960 = eq(reset, UInt<1>("h00")) - when T_1960 : - node T_1962 = eq(T_1958, UInt<1>("h00")) - when T_1962 : - node T_1964 = eq(reset, UInt<1>("h00")) - when T_1964 : + node T_1857 = bits(s1_req.typ, 1, 0) + node T_1859 = dshl(UInt<1>("h01"), T_1857) + node T_1861 = sub(T_1859, UInt<1>("h01")) + node T_1862 = tail(T_1861, 1) + node T_1863 = bits(T_1862, 2, 0) + node T_1864 = and(s1_req.addr, T_1863) + node misaligned = neq(T_1864, UInt<1>("h00")) + node T_1867 = and(s1_read, misaligned) + io.cpu.xcpt.ma.ld <= T_1867 + node T_1868 = and(s1_write, misaligned) + io.cpu.xcpt.ma.st <= T_1868 + node T_1869 = and(s1_read, dtlb.io.resp.xcpt_ld) + io.cpu.xcpt.pf.ld <= T_1869 + node T_1870 = and(s1_write, dtlb.io.resp.xcpt_st) + io.cpu.xcpt.pf.st <= T_1870 + node T_1871 = or(io.cpu.xcpt.ma.ld, io.cpu.xcpt.ma.st) + node T_1872 = or(T_1871, io.cpu.xcpt.pf.ld) + node T_1873 = or(T_1872, io.cpu.xcpt.pf.st) + reg T_1874 : UInt<1>, clk + T_1874 <= T_1873 + node T_1875 = and(T_1874, io.cpu.resp.valid) + node T_1877 = eq(T_1875, UInt<1>("h00")) + node T_1879 = eq(reset, UInt<1>("h00")) + when T_1879 : + node T_1881 = eq(T_1877, UInt<1>("h00")) + when T_1881 : + node T_1883 = eq(reset, UInt<1>("h00")) + when T_1883 : printf(clk, UInt<1>(1), "Assertion failed: (TODO: code / lineno): DCache exception occurred - cache response not killed.") skip stop(clk, UInt<1>(1), 1) skip skip inst meta of MetadataArray - meta.io.write.bits.data.coh.state <= UInt<1>("h00") - meta.io.write.bits.data.tag <= UInt<1>("h00") - meta.io.write.bits.way_en <= UInt<1>("h00") - meta.io.write.bits.idx <= UInt<1>("h00") - meta.io.write.valid <= UInt<1>("h00") - meta.io.read.bits.idx <= UInt<1>("h00") - meta.io.read.valid <= UInt<1>("h00") + meta.io is invalid meta.clk <= clk meta.reset <= reset inst metaReadArb of Arbiter_105 - metaReadArb.io.out.ready <= UInt<1>("h00") - metaReadArb.io.in[0].bits.idx <= UInt<1>("h00") - metaReadArb.io.in[0].valid <= UInt<1>("h00") - metaReadArb.io.in[1].bits.idx <= UInt<1>("h00") - metaReadArb.io.in[1].valid <= UInt<1>("h00") - metaReadArb.io.in[2].bits.idx <= UInt<1>("h00") - metaReadArb.io.in[2].valid <= UInt<1>("h00") - metaReadArb.io.in[3].bits.idx <= UInt<1>("h00") - metaReadArb.io.in[3].valid <= UInt<1>("h00") - metaReadArb.io.in[4].bits.idx <= UInt<1>("h00") - metaReadArb.io.in[4].valid <= UInt<1>("h00") + metaReadArb.io is invalid metaReadArb.clk <= clk metaReadArb.reset <= reset inst metaWriteArb of Arbiter_94 - metaWriteArb.io.out.ready <= UInt<1>("h00") - metaWriteArb.io.in[0].bits.data.coh.state <= UInt<1>("h00") - metaWriteArb.io.in[0].bits.data.tag <= UInt<1>("h00") - metaWriteArb.io.in[0].bits.way_en <= UInt<1>("h00") - metaWriteArb.io.in[0].bits.idx <= UInt<1>("h00") - metaWriteArb.io.in[0].valid <= UInt<1>("h00") - metaWriteArb.io.in[1].bits.data.coh.state <= UInt<1>("h00") - metaWriteArb.io.in[1].bits.data.tag <= UInt<1>("h00") - metaWriteArb.io.in[1].bits.way_en <= UInt<1>("h00") - metaWriteArb.io.in[1].bits.idx <= UInt<1>("h00") - metaWriteArb.io.in[1].valid <= UInt<1>("h00") + metaWriteArb.io is invalid metaWriteArb.clk <= clk metaWriteArb.reset <= reset meta.io.read <- metaReadArb.io.out meta.io.write <- metaWriteArb.io.out inst data of DataArray - data.io.write.bits.data <= UInt<1>("h00") - data.io.write.bits.wmask <= UInt<1>("h00") - data.io.write.bits.addr <= UInt<1>("h00") - data.io.write.bits.way_en <= UInt<1>("h00") - data.io.write.valid <= UInt<1>("h00") - data.io.read.bits.addr <= UInt<1>("h00") - data.io.read.bits.way_en <= UInt<1>("h00") - data.io.read.valid <= UInt<1>("h00") + data.io is invalid data.clk <= clk data.reset <= reset inst readArb of Arbiter_107 - readArb.io.out.ready <= UInt<1>("h00") - readArb.io.in[0].bits.addr <= UInt<1>("h00") - readArb.io.in[0].bits.way_en <= UInt<1>("h00") - readArb.io.in[0].valid <= UInt<1>("h00") - readArb.io.in[1].bits.addr <= UInt<1>("h00") - readArb.io.in[1].bits.way_en <= UInt<1>("h00") - readArb.io.in[1].valid <= UInt<1>("h00") - readArb.io.in[2].bits.addr <= UInt<1>("h00") - readArb.io.in[2].bits.way_en <= UInt<1>("h00") - readArb.io.in[2].valid <= UInt<1>("h00") - readArb.io.in[3].bits.addr <= UInt<1>("h00") - readArb.io.in[3].bits.way_en <= UInt<1>("h00") - readArb.io.in[3].valid <= UInt<1>("h00") + readArb.io is invalid readArb.clk <= clk readArb.reset <= reset inst writeArb of Arbiter_108 - writeArb.io.out.ready <= UInt<1>("h00") - writeArb.io.in[0].bits.data <= UInt<1>("h00") - writeArb.io.in[0].bits.wmask <= UInt<1>("h00") - writeArb.io.in[0].bits.addr <= UInt<1>("h00") - writeArb.io.in[0].bits.way_en <= UInt<1>("h00") - writeArb.io.in[0].valid <= UInt<1>("h00") - writeArb.io.in[1].bits.data <= UInt<1>("h00") - writeArb.io.in[1].bits.wmask <= UInt<1>("h00") - writeArb.io.in[1].bits.addr <= UInt<1>("h00") - writeArb.io.in[1].bits.way_en <= UInt<1>("h00") - writeArb.io.in[1].valid <= UInt<1>("h00") + writeArb.io is invalid writeArb.clk <= clk writeArb.reset <= reset data.io.write.valid <= writeArb.io.out.valid writeArb.io.out.ready <= data.io.write.ready data.io.write.bits <- writeArb.io.out.bits - node T_2283 = bits(writeArb.io.out.bits.data, 63, 0) - node T_2284 = bits(writeArb.io.out.bits.data, 127, 64) - wire T_2286 : UInt<64>[2] - T_2286[0] <= T_2283 - T_2286[1] <= T_2284 - node T_2290 = cat(T_2286[1], T_2286[0]) - data.io.write.bits.data <= T_2290 + node T_2141 = bits(writeArb.io.out.bits.data, 63, 0) + node T_2142 = bits(writeArb.io.out.bits.data, 127, 64) + wire T_2144 : UInt<64>[2] + T_2144[0] <= T_2141 + T_2144[1] <= T_2142 + node T_2148 = cat(T_2144[1], T_2144[0]) + data.io.write.bits.data <= T_2148 metaReadArb.io.in[4].valid <= io.cpu.req.valid - node T_2291 = shr(io.cpu.req.bits.addr, 6) - metaReadArb.io.in[4].bits.idx <= T_2291 - node T_2293 = eq(metaReadArb.io.in[4].ready, UInt<1>("h00")) - when T_2293 : + node T_2149 = shr(io.cpu.req.bits.addr, 6) + metaReadArb.io.in[4].bits.idx <= T_2149 + node T_2151 = eq(metaReadArb.io.in[4].ready, UInt<1>("h00")) + when T_2151 : io.cpu.req.ready <= UInt<1>("h00") skip readArb.io.in[3].valid <= io.cpu.req.valid readArb.io.in[3].bits.addr <= io.cpu.req.bits.addr - node T_2296 = not(UInt<4>("h00")) - readArb.io.in[3].bits.way_en <= T_2296 - node T_2298 = eq(readArb.io.in[3].ready, UInt<1>("h00")) - when T_2298 : + node T_2154 = not(UInt<4>("h00")) + readArb.io.in[3].bits.way_en <= T_2154 + node T_2156 = eq(readArb.io.in[3].ready, UInt<1>("h00")) + when T_2156 : io.cpu.req.ready <= UInt<1>("h00") skip metaReadArb.io.in[0].valid <= s2_recycle - node T_2300 = shr(s2_req.addr, 6) - metaReadArb.io.in[0].bits.idx <= T_2300 + node T_2158 = shr(s2_req.addr, 6) + metaReadArb.io.in[0].bits.idx <= T_2158 readArb.io.in[0].valid <= s2_recycle readArb.io.in[0].bits.addr <= s2_req.addr - node T_2302 = not(UInt<4>("h00")) - readArb.io.in[0].bits.way_en <= T_2302 - node T_2303 = shr(s1_addr, 12) - node T_2304 = eq(meta.io.resp[0].tag, T_2303) - node T_2305 = shr(s1_addr, 12) - node T_2306 = eq(meta.io.resp[1].tag, T_2305) - node T_2307 = shr(s1_addr, 12) - node T_2308 = eq(meta.io.resp[2].tag, T_2307) - node T_2309 = shr(s1_addr, 12) - node T_2310 = eq(meta.io.resp[3].tag, T_2309) - wire T_2312 : UInt<1>[4] - T_2312[0] <= T_2304 - T_2312[1] <= T_2306 - T_2312[2] <= T_2308 - T_2312[3] <= T_2310 - node T_2318 = cat(T_2312[3], T_2312[2]) - node T_2319 = cat(T_2312[1], T_2312[0]) - node s1_tag_eq_way = cat(T_2318, T_2319) - node T_2321 = bit(s1_tag_eq_way, 0) - node T_2322 = neq(meta.io.resp[0].coh.state, UInt<1>("h00")) - node T_2323 = and(T_2321, T_2322) - node T_2324 = bit(s1_tag_eq_way, 1) - node T_2325 = neq(meta.io.resp[1].coh.state, UInt<1>("h00")) - node T_2326 = and(T_2324, T_2325) - node T_2327 = bit(s1_tag_eq_way, 2) - node T_2328 = neq(meta.io.resp[2].coh.state, UInt<1>("h00")) - node T_2329 = and(T_2327, T_2328) - node T_2330 = bit(s1_tag_eq_way, 3) - node T_2331 = neq(meta.io.resp[3].coh.state, UInt<1>("h00")) - node T_2332 = and(T_2330, T_2331) - wire T_2334 : UInt<1>[4] - T_2334[0] <= T_2323 - T_2334[1] <= T_2326 - T_2334[2] <= T_2329 - T_2334[3] <= T_2332 - node T_2340 = cat(T_2334[3], T_2334[2]) - node T_2341 = cat(T_2334[1], T_2334[0]) - node s1_tag_match_way = cat(T_2340, T_2341) + node T_2160 = not(UInt<4>("h00")) + readArb.io.in[0].bits.way_en <= T_2160 + node T_2161 = shr(s1_addr, 12) + node T_2162 = eq(meta.io.resp[0].tag, T_2161) + node T_2163 = shr(s1_addr, 12) + node T_2164 = eq(meta.io.resp[1].tag, T_2163) + node T_2165 = shr(s1_addr, 12) + node T_2166 = eq(meta.io.resp[2].tag, T_2165) + node T_2167 = shr(s1_addr, 12) + node T_2168 = eq(meta.io.resp[3].tag, T_2167) + wire T_2170 : UInt<1>[4] + T_2170[0] <= T_2162 + T_2170[1] <= T_2164 + T_2170[2] <= T_2166 + T_2170[3] <= T_2168 + node T_2176 = cat(T_2170[3], T_2170[2]) + node T_2177 = cat(T_2170[1], T_2170[0]) + node s1_tag_eq_way = cat(T_2176, T_2177) + node T_2179 = bits(s1_tag_eq_way, 0, 0) + node T_2180 = neq(meta.io.resp[0].coh.state, UInt<1>("h00")) + node T_2181 = and(T_2179, T_2180) + node T_2182 = bits(s1_tag_eq_way, 1, 1) + node T_2183 = neq(meta.io.resp[1].coh.state, UInt<1>("h00")) + node T_2184 = and(T_2182, T_2183) + node T_2185 = bits(s1_tag_eq_way, 2, 2) + node T_2186 = neq(meta.io.resp[2].coh.state, UInt<1>("h00")) + node T_2187 = and(T_2185, T_2186) + node T_2188 = bits(s1_tag_eq_way, 3, 3) + node T_2189 = neq(meta.io.resp[3].coh.state, UInt<1>("h00")) + node T_2190 = and(T_2188, T_2189) + wire T_2192 : UInt<1>[4] + T_2192[0] <= T_2181 + T_2192[1] <= T_2184 + T_2192[2] <= T_2187 + T_2192[3] <= T_2190 + node T_2198 = cat(T_2192[3], T_2192[2]) + node T_2199 = cat(T_2192[1], T_2192[0]) + node s1_tag_match_way = cat(T_2198, T_2199) s1_clk_en <= metaReadArb.io.out.valid - node T_2344 = eq(s1_valid, UInt<1>("h00")) - node T_2345 = and(s1_clk_en, T_2344) - node T_2347 = eq(s1_replay, UInt<1>("h00")) - node s1_writeback = and(T_2345, T_2347) - reg s2_tag_match_way : UInt<4>, clk, UInt<1>("h00"), s2_tag_match_way + node T_2202 = eq(s1_valid, UInt<1>("h00")) + node T_2203 = and(s1_clk_en, T_2202) + node T_2205 = eq(s1_replay, UInt<1>("h00")) + node s1_writeback = and(T_2203, T_2205) + reg s2_tag_match_way : UInt<4>, clk when s1_clk_en : s2_tag_match_way <= s1_tag_match_way skip node s2_tag_match = neq(s2_tag_match_way, UInt<1>("h00")) - reg T_2352 : {state : UInt<2>}, clk, UInt<1>("h00"), T_2352 + reg T_2210 : {state : UInt<2>}, clk when s1_clk_en : - T_2352 <- meta.io.resp[0].coh + T_2210 <- meta.io.resp[0].coh skip - reg T_2377 : {state : UInt<2>}, clk, UInt<1>("h00"), T_2377 + reg T_2235 : {state : UInt<2>}, clk when s1_clk_en : - T_2377 <- meta.io.resp[1].coh + T_2235 <- meta.io.resp[1].coh skip - reg T_2402 : {state : UInt<2>}, clk, UInt<1>("h00"), T_2402 + reg T_2260 : {state : UInt<2>}, clk when s1_clk_en : - T_2402 <- meta.io.resp[2].coh + T_2260 <- meta.io.resp[2].coh skip - reg T_2427 : {state : UInt<2>}, clk, UInt<1>("h00"), T_2427 + reg T_2285 : {state : UInt<2>}, clk when s1_clk_en : - T_2427 <- meta.io.resp[3].coh - skip - wire T_2477 : {state : UInt<2>}[4] - T_2477[0] <- T_2352 - T_2477[1] <- T_2377 - T_2477[2] <- T_2402 - T_2477[3] <- T_2427 - node T_2603 = bit(s2_tag_match_way, 0) - node T_2604 = bit(s2_tag_match_way, 1) - node T_2605 = bit(s2_tag_match_way, 2) - node T_2606 = bit(s2_tag_match_way, 3) - node T_2608 = mux(T_2603, T_2477[0].state, UInt<1>("h00")) - node T_2610 = mux(T_2604, T_2477[1].state, UInt<1>("h00")) - node T_2612 = mux(T_2605, T_2477[2].state, UInt<1>("h00")) - node T_2614 = mux(T_2606, T_2477[3].state, UInt<1>("h00")) - node T_2640 = or(T_2608, T_2610) - node T_2641 = or(T_2640, T_2612) - node T_2642 = or(T_2641, T_2614) + T_2285 <- meta.io.resp[3].coh + skip + wire T_2335 : {state : UInt<2>}[4] + T_2335[0] <- T_2210 + T_2335[1] <- T_2235 + T_2335[2] <- T_2260 + T_2335[3] <- T_2285 + node T_2461 = bits(s2_tag_match_way, 0, 0) + node T_2462 = bits(s2_tag_match_way, 1, 1) + node T_2463 = bits(s2_tag_match_way, 2, 2) + node T_2464 = bits(s2_tag_match_way, 3, 3) + node T_2466 = mux(T_2461, T_2335[0].state, UInt<1>("h00")) + node T_2468 = mux(T_2462, T_2335[1].state, UInt<1>("h00")) + node T_2470 = mux(T_2463, T_2335[2].state, UInt<1>("h00")) + node T_2472 = mux(T_2464, T_2335[3].state, UInt<1>("h00")) + node T_2498 = or(T_2466, T_2468) + node T_2499 = or(T_2498, T_2470) + node T_2500 = or(T_2499, T_2472) wire s2_hit_state : {state : UInt<2>} - s2_hit_state.state <= UInt<1>("h00") - node T_2694 = bits(T_2642, 1, 0) - s2_hit_state.state <= T_2694 - node T_2695 = eq(s2_req.cmd, UInt<5>("h01")) - node T_2696 = eq(s2_req.cmd, UInt<5>("h07")) - node T_2697 = or(T_2695, T_2696) - node T_2698 = bit(s2_req.cmd, 3) - node T_2699 = eq(s2_req.cmd, UInt<5>("h04")) - node T_2700 = or(T_2698, T_2699) - node T_2701 = or(T_2697, T_2700) - node T_2702 = eq(s2_req.cmd, UInt<5>("h03")) - node T_2703 = or(T_2701, T_2702) - node T_2704 = eq(s2_req.cmd, UInt<5>("h06")) - node T_2705 = or(T_2703, T_2704) - wire T_2707 : UInt<2>[2] - T_2707[0] <= UInt<2>("h02") - T_2707[1] <= UInt<2>("h03") - node T_2711 = eq(T_2707[0], s2_hit_state.state) - node T_2712 = eq(T_2707[1], s2_hit_state.state) - node T_2714 = or(UInt<1>("h00"), T_2711) - node T_2715 = or(T_2714, T_2712) - wire T_2717 : UInt<2>[3] - T_2717[0] <= UInt<1>("h01") - T_2717[1] <= UInt<2>("h02") - T_2717[2] <= UInt<2>("h03") - node T_2722 = eq(T_2717[0], s2_hit_state.state) - node T_2723 = eq(T_2717[1], s2_hit_state.state) - node T_2724 = eq(T_2717[2], s2_hit_state.state) - node T_2726 = or(UInt<1>("h00"), T_2722) - node T_2727 = or(T_2726, T_2723) - node T_2728 = or(T_2727, T_2724) - node T_2729 = mux(T_2705, T_2715, T_2728) - node T_2730 = and(s2_tag_match, T_2729) - node T_2731 = eq(s2_req.cmd, UInt<5>("h01")) - node T_2732 = eq(s2_req.cmd, UInt<5>("h07")) - node T_2733 = or(T_2731, T_2732) - node T_2734 = bit(s2_req.cmd, 3) - node T_2735 = eq(s2_req.cmd, UInt<5>("h04")) - node T_2736 = or(T_2734, T_2735) - node T_2737 = or(T_2733, T_2736) - node T_2738 = mux(T_2737, UInt<2>("h03"), s2_hit_state.state) - wire T_2764 : {state : UInt<2>} - T_2764.state <= UInt<1>("h00") - T_2764.state <= T_2738 - node T_2790 = eq(s2_hit_state.state, T_2764.state) - node s2_hit = and(T_2730, T_2790) - reg lrsc_count : UInt<?>, clk, reset, UInt<1>("h00") + s2_hit_state is invalid + node T_2551 = bits(T_2500, 1, 0) + s2_hit_state.state <= T_2551 + node T_2552 = eq(s2_req.cmd, UInt<5>("h01")) + node T_2553 = eq(s2_req.cmd, UInt<5>("h07")) + node T_2554 = or(T_2552, T_2553) + node T_2555 = bits(s2_req.cmd, 3, 3) + node T_2556 = eq(s2_req.cmd, UInt<5>("h04")) + node T_2557 = or(T_2555, T_2556) + node T_2558 = or(T_2554, T_2557) + node T_2559 = eq(s2_req.cmd, UInt<5>("h03")) + node T_2560 = or(T_2558, T_2559) + node T_2561 = eq(s2_req.cmd, UInt<5>("h06")) + node T_2562 = or(T_2560, T_2561) + wire T_2564 : UInt<2>[2] + T_2564[0] <= UInt<2>("h02") + T_2564[1] <= UInt<2>("h03") + node T_2568 = eq(T_2564[0], s2_hit_state.state) + node T_2569 = eq(T_2564[1], s2_hit_state.state) + node T_2571 = or(UInt<1>("h00"), T_2568) + node T_2572 = or(T_2571, T_2569) + wire T_2574 : UInt<2>[3] + T_2574[0] <= UInt<1>("h01") + T_2574[1] <= UInt<2>("h02") + T_2574[2] <= UInt<2>("h03") + node T_2579 = eq(T_2574[0], s2_hit_state.state) + node T_2580 = eq(T_2574[1], s2_hit_state.state) + node T_2581 = eq(T_2574[2], s2_hit_state.state) + node T_2583 = or(UInt<1>("h00"), T_2579) + node T_2584 = or(T_2583, T_2580) + node T_2585 = or(T_2584, T_2581) + node T_2586 = mux(T_2562, T_2572, T_2585) + node T_2587 = and(s2_tag_match, T_2586) + node T_2588 = eq(s2_req.cmd, UInt<5>("h01")) + node T_2589 = eq(s2_req.cmd, UInt<5>("h07")) + node T_2590 = or(T_2588, T_2589) + node T_2591 = bits(s2_req.cmd, 3, 3) + node T_2592 = eq(s2_req.cmd, UInt<5>("h04")) + node T_2593 = or(T_2591, T_2592) + node T_2594 = or(T_2590, T_2593) + node T_2595 = mux(T_2594, UInt<2>("h03"), s2_hit_state.state) + wire T_2621 : {state : UInt<2>} + T_2621 is invalid + T_2621.state <= T_2595 + node T_2646 = eq(s2_hit_state.state, T_2621.state) + node s2_hit = and(T_2587, T_2646) + reg lrsc_count : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) node lrsc_valid = neq(lrsc_count, UInt<1>("h00")) - reg lrsc_addr : UInt<?>, clk, UInt<1>("h00"), lrsc_addr + reg lrsc_addr : UInt<?>, clk node s2_lr = eq(s2_req.cmd, UInt<5>("h06")) node s2_sc = eq(s2_req.cmd, UInt<5>("h07")) - node T_2800 = shr(s2_req.addr, 6) - node T_2801 = eq(lrsc_addr, T_2800) - node s2_lrsc_addr_match = and(lrsc_valid, T_2801) - node T_2804 = eq(s2_lrsc_addr_match, UInt<1>("h00")) - node s2_sc_fail = and(s2_sc, T_2804) + node T_2656 = shr(s2_req.addr, 6) + node T_2657 = eq(lrsc_addr, T_2656) + node s2_lrsc_addr_match = and(lrsc_valid, T_2657) + node T_2660 = eq(s2_lrsc_addr_match, UInt<1>("h00")) + node s2_sc_fail = and(s2_sc, T_2660) when lrsc_valid : - node T_2807 = subw(lrsc_count, UInt<1>("h01")) - lrsc_count <= T_2807 + node T_2663 = sub(lrsc_count, UInt<1>("h01")) + node T_2664 = tail(T_2663, 1) + lrsc_count <= T_2664 skip - node T_2808 = and(s2_valid_masked, s2_hit) - node T_2809 = or(T_2808, s2_replay) - when T_2809 : + node T_2665 = and(s2_valid_masked, s2_hit) + node T_2666 = or(T_2665, s2_replay) + when T_2666 : when s2_lr : - node T_2811 = eq(lrsc_valid, UInt<1>("h00")) - when T_2811 : + node T_2668 = eq(lrsc_valid, UInt<1>("h00")) + when T_2668 : lrsc_count <= UInt<5>("h01f") skip - node T_2813 = shr(s2_req.addr, 6) - lrsc_addr <= T_2813 + node T_2670 = shr(s2_req.addr, 6) + lrsc_addr <= T_2670 skip when s2_sc : lrsc_count <= UInt<1>("h00") @@ -32612,324 +25025,297 @@ circuit Top : lrsc_count <= UInt<1>("h00") skip wire s2_data : UInt<128>[4] - s2_data[0] <= UInt<1>("h00") - s2_data[1] <= UInt<1>("h00") - s2_data[2] <= UInt<1>("h00") - s2_data[3] <= UInt<1>("h00") - reg T_2844 : UInt<64>[2], clk, UInt<1>("h00"), T_2844 - node T_2848 = bit(s1_tag_eq_way, 0) - node T_2849 = and(s1_clk_en, T_2848) - node T_2853 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2854 = or(UInt<1>("h01"), T_2853) - node T_2855 = or(T_2854, s1_writeback) - node T_2856 = and(T_2849, T_2855) - when T_2856 : - node T_2857 = shr(data.io.resp[0], 0) - T_2844[0] <= T_2857 - skip - node T_2861 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2862 = or(UInt<1>("h00"), T_2861) - node T_2863 = or(T_2862, s1_writeback) - node T_2864 = and(T_2849, T_2863) - when T_2864 : - node T_2865 = shr(data.io.resp[0], 64) - T_2844[1] <= T_2865 - skip - node T_2866 = cat(T_2844[1], T_2844[0]) - s2_data[0] <= T_2866 - reg T_2875 : UInt<64>[2], clk, UInt<1>("h00"), T_2875 - node T_2879 = bit(s1_tag_eq_way, 1) - node T_2880 = and(s1_clk_en, T_2879) - node T_2884 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2885 = or(UInt<1>("h01"), T_2884) - node T_2886 = or(T_2885, s1_writeback) - node T_2887 = and(T_2880, T_2886) - when T_2887 : - node T_2888 = shr(data.io.resp[1], 0) - T_2875[0] <= T_2888 - skip - node T_2892 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2893 = or(UInt<1>("h00"), T_2892) - node T_2894 = or(T_2893, s1_writeback) - node T_2895 = and(T_2880, T_2894) - when T_2895 : - node T_2896 = shr(data.io.resp[1], 64) - T_2875[1] <= T_2896 - skip - node T_2897 = cat(T_2875[1], T_2875[0]) - s2_data[1] <= T_2897 - reg T_2906 : UInt<64>[2], clk, UInt<1>("h00"), T_2906 - node T_2910 = bit(s1_tag_eq_way, 2) - node T_2911 = and(s1_clk_en, T_2910) - node T_2915 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2916 = or(UInt<1>("h01"), T_2915) - node T_2917 = or(T_2916, s1_writeback) - node T_2918 = and(T_2911, T_2917) - when T_2918 : - node T_2919 = shr(data.io.resp[2], 0) - T_2906[0] <= T_2919 - skip - node T_2923 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2924 = or(UInt<1>("h00"), T_2923) - node T_2925 = or(T_2924, s1_writeback) - node T_2926 = and(T_2911, T_2925) - when T_2926 : - node T_2927 = shr(data.io.resp[2], 64) - T_2906[1] <= T_2927 - skip - node T_2928 = cat(T_2906[1], T_2906[0]) - s2_data[2] <= T_2928 - reg T_2937 : UInt<64>[2], clk, UInt<1>("h00"), T_2937 - node T_2941 = bit(s1_tag_eq_way, 3) - node T_2942 = and(s1_clk_en, T_2941) - node T_2946 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2947 = or(UInt<1>("h01"), T_2946) - node T_2948 = or(T_2947, s1_writeback) - node T_2949 = and(T_2942, T_2948) - when T_2949 : - node T_2950 = shr(data.io.resp[3], 0) - T_2937[0] <= T_2950 - skip - node T_2954 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_2955 = or(UInt<1>("h00"), T_2954) - node T_2956 = or(T_2955, s1_writeback) - node T_2957 = and(T_2942, T_2956) - when T_2957 : - node T_2958 = shr(data.io.resp[3], 64) - T_2937[1] <= T_2958 - skip - node T_2959 = cat(T_2937[1], T_2937[0]) - s2_data[3] <= T_2959 - node T_2960 = bit(s2_tag_match_way, 0) - node T_2961 = bit(s2_tag_match_way, 1) - node T_2962 = bit(s2_tag_match_way, 2) - node T_2963 = bit(s2_tag_match_way, 3) - node T_2965 = mux(T_2960, s2_data[0], UInt<1>("h00")) - node T_2967 = mux(T_2961, s2_data[1], UInt<1>("h00")) - node T_2969 = mux(T_2962, s2_data[2], UInt<1>("h00")) - node T_2971 = mux(T_2963, s2_data[3], UInt<1>("h00")) - node T_2973 = or(T_2965, T_2967) - node T_2974 = or(T_2973, T_2969) - node T_2975 = or(T_2974, T_2971) + s2_data is invalid + reg T_2697 : UInt<64>[2], clk + node T_2701 = bits(s1_tag_eq_way, 0, 0) + node T_2702 = and(s1_clk_en, T_2701) + node T_2706 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_2707 = or(UInt<1>("h01"), T_2706) + node T_2708 = or(T_2707, s1_writeback) + node T_2709 = and(T_2702, T_2708) + when T_2709 : + node T_2710 = shr(data.io.resp[0], 0) + T_2697[0] <= T_2710 + skip + node T_2714 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_2715 = or(UInt<1>("h00"), T_2714) + node T_2716 = or(T_2715, s1_writeback) + node T_2717 = and(T_2702, T_2716) + when T_2717 : + node T_2718 = shr(data.io.resp[0], 64) + T_2697[1] <= T_2718 + skip + node T_2719 = cat(T_2697[1], T_2697[0]) + s2_data[0] <= T_2719 + reg T_2728 : UInt<64>[2], clk + node T_2732 = bits(s1_tag_eq_way, 1, 1) + node T_2733 = and(s1_clk_en, T_2732) + node T_2737 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_2738 = or(UInt<1>("h01"), T_2737) + node T_2739 = or(T_2738, s1_writeback) + node T_2740 = and(T_2733, T_2739) + when T_2740 : + node T_2741 = shr(data.io.resp[1], 0) + T_2728[0] <= T_2741 + skip + node T_2745 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_2746 = or(UInt<1>("h00"), T_2745) + node T_2747 = or(T_2746, s1_writeback) + node T_2748 = and(T_2733, T_2747) + when T_2748 : + node T_2749 = shr(data.io.resp[1], 64) + T_2728[1] <= T_2749 + skip + node T_2750 = cat(T_2728[1], T_2728[0]) + s2_data[1] <= T_2750 + reg T_2759 : UInt<64>[2], clk + node T_2763 = bits(s1_tag_eq_way, 2, 2) + node T_2764 = and(s1_clk_en, T_2763) + node T_2768 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_2769 = or(UInt<1>("h01"), T_2768) + node T_2770 = or(T_2769, s1_writeback) + node T_2771 = and(T_2764, T_2770) + when T_2771 : + node T_2772 = shr(data.io.resp[2], 0) + T_2759[0] <= T_2772 + skip + node T_2776 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_2777 = or(UInt<1>("h00"), T_2776) + node T_2778 = or(T_2777, s1_writeback) + node T_2779 = and(T_2764, T_2778) + when T_2779 : + node T_2780 = shr(data.io.resp[2], 64) + T_2759[1] <= T_2780 + skip + node T_2781 = cat(T_2759[1], T_2759[0]) + s2_data[2] <= T_2781 + reg T_2790 : UInt<64>[2], clk + node T_2794 = bits(s1_tag_eq_way, 3, 3) + node T_2795 = and(s1_clk_en, T_2794) + node T_2799 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_2800 = or(UInt<1>("h01"), T_2799) + node T_2801 = or(T_2800, s1_writeback) + node T_2802 = and(T_2795, T_2801) + when T_2802 : + node T_2803 = shr(data.io.resp[3], 0) + T_2790[0] <= T_2803 + skip + node T_2807 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_2808 = or(UInt<1>("h00"), T_2807) + node T_2809 = or(T_2808, s1_writeback) + node T_2810 = and(T_2795, T_2809) + when T_2810 : + node T_2811 = shr(data.io.resp[3], 64) + T_2790[1] <= T_2811 + skip + node T_2812 = cat(T_2790[1], T_2790[0]) + s2_data[3] <= T_2812 + node T_2813 = bits(s2_tag_match_way, 0, 0) + node T_2814 = bits(s2_tag_match_way, 1, 1) + node T_2815 = bits(s2_tag_match_way, 2, 2) + node T_2816 = bits(s2_tag_match_way, 3, 3) + node T_2818 = mux(T_2813, s2_data[0], UInt<1>("h00")) + node T_2820 = mux(T_2814, s2_data[1], UInt<1>("h00")) + node T_2822 = mux(T_2815, s2_data[2], UInt<1>("h00")) + node T_2824 = mux(T_2816, s2_data[3], UInt<1>("h00")) + node T_2826 = or(T_2818, T_2820) + node T_2827 = or(T_2826, T_2822) + node T_2828 = or(T_2827, T_2824) wire s2_data_muxed : UInt<128> - s2_data_muxed <= UInt<1>("h00") - s2_data_muxed <= T_2975 - node T_2978 = bits(s2_data_muxed, 63, 0) - node T_2979 = bits(s2_data_muxed, 127, 64) - wire T_2981 : UInt<64>[2] - T_2981[0] <= T_2978 - T_2981[1] <= T_2979 - node s2_data_corrected = cat(T_2981[1], T_2981[0]) - wire T_2987 : UInt<64>[2] - T_2987[0] <= T_2978 - T_2987[1] <= T_2979 - node s2_data_uncorrected = cat(T_2987[1], T_2987[0]) - wire T_2996 : UInt<1>[2] - T_2996[0] <= UInt<1>("h00") - T_2996[1] <= UInt<1>("h00") - node T_3000 = cat(T_2996[1], T_2996[0]) - node T_3001 = dshr(T_3000, UInt<1>("h00")) - node s2_data_correctable = bit(T_3001, 0) - node T_3003 = and(s2_valid_masked, s2_hit) - node T_3004 = or(T_3003, s2_replay) - node T_3006 = eq(s2_sc_fail, UInt<1>("h00")) - node T_3007 = and(T_3004, T_3006) - node T_3008 = eq(s2_req.cmd, UInt<5>("h01")) - node T_3009 = eq(s2_req.cmd, UInt<5>("h07")) - node T_3010 = or(T_3008, T_3009) - node T_3011 = bit(s2_req.cmd, 3) - node T_3012 = eq(s2_req.cmd, UInt<5>("h04")) - node T_3013 = or(T_3011, T_3012) - node T_3014 = or(T_3010, T_3013) - node T_3015 = and(T_3007, T_3014) - s3_valid <= T_3015 + s2_data_muxed is invalid + s2_data_muxed <= T_2828 + node T_2830 = bits(s2_data_muxed, 63, 0) + node T_2831 = bits(s2_data_muxed, 127, 64) + wire T_2833 : UInt<64>[2] + T_2833[0] <= T_2830 + T_2833[1] <= T_2831 + node s2_data_corrected = cat(T_2833[1], T_2833[0]) + wire T_2839 : UInt<64>[2] + T_2839[0] <= T_2830 + T_2839[1] <= T_2831 + node s2_data_uncorrected = cat(T_2839[1], T_2839[0]) + wire T_2848 : UInt<1>[2] + T_2848[0] <= UInt<1>("h00") + T_2848[1] <= UInt<1>("h00") + node T_2852 = cat(T_2848[1], T_2848[0]) + node T_2853 = dshr(T_2852, UInt<1>("h00")) + node s2_data_correctable = bits(T_2853, 0, 0) + node T_2855 = and(s2_valid_masked, s2_hit) + node T_2856 = or(T_2855, s2_replay) + node T_2858 = eq(s2_sc_fail, UInt<1>("h00")) + node T_2859 = and(T_2856, T_2858) + node T_2860 = eq(s2_req.cmd, UInt<5>("h01")) + node T_2861 = eq(s2_req.cmd, UInt<5>("h07")) + node T_2862 = or(T_2860, T_2861) + node T_2863 = bits(s2_req.cmd, 3, 3) + node T_2864 = eq(s2_req.cmd, UInt<5>("h04")) + node T_2865 = or(T_2863, T_2864) + node T_2866 = or(T_2862, T_2865) + node T_2867 = and(T_2859, T_2866) + s3_valid <= T_2867 inst amoalu of AMOALU - amoalu.io.rhs <= UInt<1>("h00") - amoalu.io.lhs <= UInt<1>("h00") - amoalu.io.typ <= UInt<1>("h00") - amoalu.io.cmd <= UInt<1>("h00") - amoalu.io.addr <= UInt<1>("h00") + amoalu.io is invalid amoalu.clk <= clk amoalu.reset <= reset - node T_3022 = or(s2_valid, s2_replay) - node T_3023 = eq(s2_req.cmd, UInt<5>("h01")) - node T_3024 = eq(s2_req.cmd, UInt<5>("h07")) - node T_3025 = or(T_3023, T_3024) - node T_3026 = bit(s2_req.cmd, 3) - node T_3027 = eq(s2_req.cmd, UInt<5>("h04")) - node T_3028 = or(T_3026, T_3027) - node T_3029 = or(T_3025, T_3028) - node T_3030 = or(T_3029, s2_data_correctable) - node T_3031 = and(T_3022, T_3030) - when T_3031 : + node T_2869 = or(s2_valid, s2_replay) + node T_2870 = eq(s2_req.cmd, UInt<5>("h01")) + node T_2871 = eq(s2_req.cmd, UInt<5>("h07")) + node T_2872 = or(T_2870, T_2871) + node T_2873 = bits(s2_req.cmd, 3, 3) + node T_2874 = eq(s2_req.cmd, UInt<5>("h04")) + node T_2875 = or(T_2873, T_2874) + node T_2876 = or(T_2872, T_2875) + node T_2877 = or(T_2876, s2_data_correctable) + node T_2878 = and(T_2869, T_2877) + when T_2878 : s3_req <- s2_req - node T_3032 = mux(s2_data_correctable, s2_data_corrected, amoalu.io.out) - s3_req.data <= T_3032 + node T_2879 = mux(s2_data_correctable, s2_data_corrected, amoalu.io.out) + s3_req.data <= T_2879 s3_way <= s2_tag_match_way skip writeArb.io.in[0].bits.addr <= s3_req.addr node rowIdx = bits(s3_req.addr, 3, 3) node rowWMask = dshl(UInt<1>("h01"), rowIdx) writeArb.io.in[0].bits.wmask <= rowWMask - node T_3036 = cat(s3_req.data, s3_req.data) - writeArb.io.in[0].bits.data <= T_3036 + node T_2883 = cat(s3_req.data, s3_req.data) + writeArb.io.in[0].bits.data <= T_2883 writeArb.io.in[0].valid <= s3_valid writeArb.io.in[0].bits.way_en <= s3_way - wire T_3038 : UInt<1> - T_3038 <= UInt<1>("h00") - T_3038 <= UInt<1>("h00") - reg T_3042 : UInt<16>, clk, reset, UInt<16>("h01") - when T_3038 : - node T_3043 = bit(T_3042, 0) - node T_3044 = bit(T_3042, 2) - node T_3045 = xor(T_3043, T_3044) - node T_3046 = bit(T_3042, 3) - node T_3047 = xor(T_3045, T_3046) - node T_3048 = bit(T_3042, 5) - node T_3049 = xor(T_3047, T_3048) - node T_3050 = bits(T_3042, 15, 1) - node T_3051 = cat(T_3049, T_3050) - T_3042 <= T_3051 - skip - node T_3052 = bits(T_3042, 1, 0) - node s1_replaced_way_en = dshl(UInt<1>("h01"), T_3052) - node T_3055 = bits(T_3042, 1, 0) - reg T_3056 : UInt<2>, clk, UInt<1>("h00"), T_3056 + wire T_2885 : UInt<1> + T_2885 is invalid + T_2885 <= UInt<1>("h00") + reg T_2888 : UInt<16>, clk with : (reset => (reset, UInt<16>("h01"))) + when T_2885 : + node T_2889 = bits(T_2888, 0, 0) + node T_2890 = bits(T_2888, 2, 2) + node T_2891 = xor(T_2889, T_2890) + node T_2892 = bits(T_2888, 3, 3) + node T_2893 = xor(T_2891, T_2892) + node T_2894 = bits(T_2888, 5, 5) + node T_2895 = xor(T_2893, T_2894) + node T_2896 = bits(T_2888, 15, 1) + node T_2897 = cat(T_2895, T_2896) + T_2888 <= T_2897 + skip + node T_2898 = bits(T_2888, 1, 0) + node s1_replaced_way_en = dshl(UInt<1>("h01"), T_2898) + node T_2901 = bits(T_2888, 1, 0) + reg T_2902 : UInt<2>, clk when s1_clk_en : - T_3056 <= T_3055 - skip - node s2_replaced_way_en = dshl(UInt<1>("h01"), T_3056) - node T_3059 = bit(s1_replaced_way_en, 0) - node T_3060 = and(s1_clk_en, T_3059) - reg T_3061 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk, UInt<1>("h00"), T_3061 - when T_3060 : - T_3061 <- meta.io.resp[0] - skip - node T_3134 = bit(s1_replaced_way_en, 1) - node T_3135 = and(s1_clk_en, T_3134) - reg T_3136 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk, UInt<1>("h00"), T_3136 - when T_3135 : - T_3136 <- meta.io.resp[1] - skip - node T_3209 = bit(s1_replaced_way_en, 2) - node T_3210 = and(s1_clk_en, T_3209) - reg T_3211 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk, UInt<1>("h00"), T_3211 - when T_3210 : - T_3211 <- meta.io.resp[2] - skip - node T_3284 = bit(s1_replaced_way_en, 3) - node T_3285 = and(s1_clk_en, T_3284) - reg T_3286 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk, UInt<1>("h00"), T_3286 - when T_3285 : - T_3286 <- meta.io.resp[3] - skip - wire T_3432 : {tag : UInt<20>, coh : {state : UInt<2>}}[4] - T_3432[0] <- T_3061 - T_3432[1] <- T_3136 - T_3432[2] <- T_3211 - T_3432[3] <- T_3286 - node T_3798 = bit(s2_replaced_way_en, 0) - node T_3799 = bit(s2_replaced_way_en, 1) - node T_3800 = bit(s2_replaced_way_en, 2) - node T_3801 = bit(s2_replaced_way_en, 3) - node T_3802 = cat(T_3432[0].tag, T_3432[0].coh.state) - node T_3804 = mux(T_3798, T_3802, UInt<1>("h00")) - node T_3805 = cat(T_3432[1].tag, T_3432[1].coh.state) - node T_3807 = mux(T_3799, T_3805, UInt<1>("h00")) - node T_3808 = cat(T_3432[2].tag, T_3432[2].coh.state) - node T_3810 = mux(T_3800, T_3808, UInt<1>("h00")) - node T_3811 = cat(T_3432[3].tag, T_3432[3].coh.state) - node T_3813 = mux(T_3801, T_3811, UInt<1>("h00")) - node T_3887 = or(T_3804, T_3807) - node T_3888 = or(T_3887, T_3810) - node T_3889 = or(T_3888, T_3813) + T_2902 <= T_2901 + skip + node s2_replaced_way_en = dshl(UInt<1>("h01"), T_2902) + node T_2905 = bits(s1_replaced_way_en, 0, 0) + node T_2906 = and(s1_clk_en, T_2905) + reg T_2907 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk + when T_2906 : + T_2907 <- meta.io.resp[0] + skip + node T_2980 = bits(s1_replaced_way_en, 1, 1) + node T_2981 = and(s1_clk_en, T_2980) + reg T_2982 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk + when T_2981 : + T_2982 <- meta.io.resp[1] + skip + node T_3055 = bits(s1_replaced_way_en, 2, 2) + node T_3056 = and(s1_clk_en, T_3055) + reg T_3057 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk + when T_3056 : + T_3057 <- meta.io.resp[2] + skip + node T_3130 = bits(s1_replaced_way_en, 3, 3) + node T_3131 = and(s1_clk_en, T_3130) + reg T_3132 : {tag : UInt<20>, coh : {state : UInt<2>}}, clk + when T_3131 : + T_3132 <- meta.io.resp[3] + skip + wire T_3278 : {tag : UInt<20>, coh : {state : UInt<2>}}[4] + T_3278[0] <- T_2907 + T_3278[1] <- T_2982 + T_3278[2] <- T_3057 + T_3278[3] <- T_3132 + node T_3644 = bits(s2_replaced_way_en, 0, 0) + node T_3645 = bits(s2_replaced_way_en, 1, 1) + node T_3646 = bits(s2_replaced_way_en, 2, 2) + node T_3647 = bits(s2_replaced_way_en, 3, 3) + node T_3648 = cat(T_3278[0].tag, T_3278[0].coh.state) + node T_3650 = mux(T_3644, T_3648, UInt<1>("h00")) + node T_3651 = cat(T_3278[1].tag, T_3278[1].coh.state) + node T_3653 = mux(T_3645, T_3651, UInt<1>("h00")) + node T_3654 = cat(T_3278[2].tag, T_3278[2].coh.state) + node T_3656 = mux(T_3646, T_3654, UInt<1>("h00")) + node T_3657 = cat(T_3278[3].tag, T_3278[3].coh.state) + node T_3659 = mux(T_3647, T_3657, UInt<1>("h00")) + node T_3733 = or(T_3650, T_3653) + node T_3734 = or(T_3733, T_3656) + node T_3735 = or(T_3734, T_3659) wire s2_repl_meta : {tag : UInt<20>, coh : {state : UInt<2>}} - s2_repl_meta.coh.state <= UInt<1>("h00") - s2_repl_meta.tag <= UInt<1>("h00") - node T_4038 = bits(T_3889, 1, 0) - s2_repl_meta.coh.state <= T_4038 - node T_4039 = bits(T_3889, 21, 2) - s2_repl_meta.tag <= T_4039 - node T_4041 = eq(s2_hit, UInt<1>("h00")) - node T_4042 = and(s2_valid_masked, T_4041) - node T_4043 = eq(s2_req.cmd, UInt<5>("h02")) - node T_4044 = eq(s2_req.cmd, UInt<5>("h03")) - node T_4045 = or(T_4043, T_4044) - node T_4046 = eq(s2_req.cmd, UInt<5>("h00")) - node T_4047 = eq(s2_req.cmd, UInt<5>("h06")) - node T_4048 = or(T_4046, T_4047) - node T_4049 = eq(s2_req.cmd, UInt<5>("h07")) - node T_4050 = or(T_4048, T_4049) - node T_4051 = bit(s2_req.cmd, 3) - node T_4052 = eq(s2_req.cmd, UInt<5>("h04")) - node T_4053 = or(T_4051, T_4052) - node T_4054 = or(T_4050, T_4053) - node T_4055 = or(T_4045, T_4054) - node T_4056 = eq(s2_req.cmd, UInt<5>("h01")) - node T_4057 = eq(s2_req.cmd, UInt<5>("h07")) - node T_4058 = or(T_4056, T_4057) - node T_4059 = bit(s2_req.cmd, 3) - node T_4060 = eq(s2_req.cmd, UInt<5>("h04")) - node T_4061 = or(T_4059, T_4060) - node T_4062 = or(T_4058, T_4061) - node T_4063 = or(T_4055, T_4062) - node T_4064 = and(T_4042, T_4063) - mshrs.io.req.valid <= T_4064 + s2_repl_meta is invalid + node T_3882 = bits(T_3735, 1, 0) + s2_repl_meta.coh.state <= T_3882 + node T_3883 = bits(T_3735, 21, 2) + s2_repl_meta.tag <= T_3883 + node T_3885 = eq(s2_hit, UInt<1>("h00")) + node T_3886 = and(s2_valid_masked, T_3885) + node T_3887 = eq(s2_req.cmd, UInt<5>("h02")) + node T_3888 = eq(s2_req.cmd, UInt<5>("h03")) + node T_3889 = or(T_3887, T_3888) + node T_3890 = eq(s2_req.cmd, UInt<5>("h00")) + node T_3891 = eq(s2_req.cmd, UInt<5>("h06")) + node T_3892 = or(T_3890, T_3891) + node T_3893 = eq(s2_req.cmd, UInt<5>("h07")) + node T_3894 = or(T_3892, T_3893) + node T_3895 = bits(s2_req.cmd, 3, 3) + node T_3896 = eq(s2_req.cmd, UInt<5>("h04")) + node T_3897 = or(T_3895, T_3896) + node T_3898 = or(T_3894, T_3897) + node T_3899 = or(T_3889, T_3898) + node T_3900 = eq(s2_req.cmd, UInt<5>("h01")) + node T_3901 = eq(s2_req.cmd, UInt<5>("h07")) + node T_3902 = or(T_3900, T_3901) + node T_3903 = bits(s2_req.cmd, 3, 3) + node T_3904 = eq(s2_req.cmd, UInt<5>("h04")) + node T_3905 = or(T_3903, T_3904) + node T_3906 = or(T_3902, T_3905) + node T_3907 = or(T_3899, T_3906) + node T_3908 = and(T_3886, T_3907) + mshrs.io.req.valid <= T_3908 mshrs.io.req.bits <- s2_req mshrs.io.req.bits.tag_match <= s2_tag_match - wire T_4138 : {tag : UInt<20>, coh : {state : UInt<2>}} - T_4138.coh.state <= UInt<1>("h00") - T_4138.tag <= UInt<1>("h00") - T_4138.tag <= s2_repl_meta.tag - T_4138.coh <- s2_hit_state - wire T_4286 : {tag : UInt<20>, coh : {state : UInt<2>}} - T_4286 <- s2_repl_meta - when s2_tag_match : - T_4286 <- T_4138 - skip - mshrs.io.req.bits.old_meta <- T_4286 - node T_4359 = mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en) - mshrs.io.req.bits.way_en <= T_4359 + wire T_3982 : {tag : UInt<20>, coh : {state : UInt<2>}} + T_3982 is invalid + T_3982.tag <= s2_repl_meta.tag + T_3982.coh <- s2_hit_state + node T_4055 = mux(s2_tag_match, T_3982, s2_repl_meta) + mshrs.io.req.bits.old_meta <- T_4055 + node T_4128 = mux(s2_tag_match, s2_tag_match_way, s2_replaced_way_en) + mshrs.io.req.bits.way_en <= T_4128 mshrs.io.req.bits.data <= s2_req.data - node T_4360 = and(mshrs.io.req.ready, mshrs.io.req.valid) - when T_4360 : - T_3038 <= UInt<1>("h01") + node T_4129 = and(mshrs.io.req.ready, mshrs.io.req.valid) + when T_4129 : + T_2885 <= UInt<1>("h01") skip io.mem.acquire <- mshrs.io.mem_req readArb.io.in[1].valid <= mshrs.io.replay.valid readArb.io.in[1].bits <- mshrs.io.replay.bits - node T_4363 = not(UInt<4>("h00")) - readArb.io.in[1].bits.way_en <= T_4363 + node T_4132 = not(UInt<4>("h00")) + readArb.io.in[1].bits.way_en <= T_4132 mshrs.io.replay.ready <= readArb.io.in[1].ready - node T_4364 = and(mshrs.io.replay.valid, readArb.io.in[1].ready) - s1_replay <= T_4364 + node T_4133 = and(mshrs.io.replay.valid, readArb.io.in[1].ready) + s1_replay <= T_4133 metaReadArb.io.in[1] <- mshrs.io.meta_read metaWriteArb.io.in[0] <- mshrs.io.meta_write inst releaseArb of LockingArbiter_109 - releaseArb.io.out.ready <= UInt<1>("h00") - releaseArb.io.in[0].bits.data <= UInt<1>("h00") - releaseArb.io.in[0].bits.r_type <= UInt<1>("h00") - releaseArb.io.in[0].bits.voluntary <= UInt<1>("h00") - releaseArb.io.in[0].bits.client_xact_id <= UInt<1>("h00") - releaseArb.io.in[0].bits.addr_block <= UInt<1>("h00") - releaseArb.io.in[0].bits.addr_beat <= UInt<1>("h00") - releaseArb.io.in[0].valid <= UInt<1>("h00") - releaseArb.io.in[1].bits.data <= UInt<1>("h00") - releaseArb.io.in[1].bits.r_type <= UInt<1>("h00") - releaseArb.io.in[1].bits.voluntary <= UInt<1>("h00") - releaseArb.io.in[1].bits.client_xact_id <= UInt<1>("h00") - releaseArb.io.in[1].bits.addr_block <= UInt<1>("h00") - releaseArb.io.in[1].bits.addr_beat <= UInt<1>("h00") - releaseArb.io.in[1].valid <= UInt<1>("h00") + releaseArb.io is invalid releaseArb.clk <= clk releaseArb.reset <= reset io.mem.release <- releaseArb.io.out - node T_4412 = eq(lrsc_valid, UInt<1>("h00")) - node T_4413 = and(io.mem.probe.valid, T_4412) - prober.io.req.valid <= T_4413 - node T_4415 = eq(lrsc_valid, UInt<1>("h00")) - node T_4416 = and(prober.io.req.ready, T_4415) - io.mem.probe.ready <= T_4416 + node T_4166 = eq(lrsc_valid, UInt<1>("h00")) + node T_4167 = and(io.mem.probe.valid, T_4166) + prober.io.req.valid <= T_4167 + node T_4169 = eq(lrsc_valid, UInt<1>("h00")) + node T_4170 = and(prober.io.req.ready, T_4169) + io.mem.probe.ready <= T_4170 prober.io.req.bits <- io.mem.probe.bits releaseArb.io.in[1] <- prober.io.rep prober.io.way_en <= s2_tag_match_way @@ -32937,88 +25323,65 @@ circuit Top : metaReadArb.io.in[2] <- prober.io.meta_read metaWriteArb.io.in[1] <- prober.io.meta_write prober.io.mshr_rdy <= mshrs.io.probe_rdy - inst T_4417 of FlowThroughSerializer - T_4417.io.out.ready <= UInt<1>("h00") - T_4417.io.in.bits.data <= UInt<1>("h00") - T_4417.io.in.bits.g_type <= UInt<1>("h00") - T_4417.io.in.bits.is_builtin_type <= UInt<1>("h00") - T_4417.io.in.bits.manager_xact_id <= UInt<1>("h00") - T_4417.io.in.bits.client_xact_id <= UInt<1>("h00") - T_4417.io.in.bits.addr_beat <= UInt<1>("h00") - T_4417.io.in.valid <= UInt<1>("h00") - T_4417.clk <= clk - T_4417.reset <= reset - T_4417.io.in.valid <= io.mem.grant.valid - T_4417.io.in.bits <- io.mem.grant.bits - io.mem.grant.ready <= T_4417.io.in.ready - node T_4426 = and(T_4417.io.out.ready, T_4417.io.out.valid) - mshrs.io.mem_grant.valid <= T_4426 - mshrs.io.mem_grant.bits <- T_4417.io.out.bits - wire T_4430 : UInt<3>[2] - T_4430[0] <= UInt<3>("h05") - T_4430[1] <= UInt<3>("h04") - node T_4434 = eq(T_4430[0], T_4417.io.out.bits.g_type) - node T_4435 = eq(T_4430[1], T_4417.io.out.bits.g_type) - node T_4437 = or(UInt<1>("h00"), T_4434) - node T_4438 = or(T_4437, T_4435) - wire T_4440 : UInt<1>[2] - T_4440[0] <= UInt<1>("h00") - T_4440[1] <= UInt<1>("h01") - node T_4444 = eq(T_4440[0], T_4417.io.out.bits.g_type) - node T_4445 = eq(T_4440[1], T_4417.io.out.bits.g_type) - node T_4447 = or(UInt<1>("h00"), T_4444) - node T_4448 = or(T_4447, T_4445) - node T_4449 = mux(T_4417.io.out.bits.is_builtin_type, T_4438, T_4448) - node T_4451 = eq(T_4449, UInt<1>("h00")) - node T_4452 = or(writeArb.io.in[1].ready, T_4451) - T_4417.io.out.ready <= T_4452 - wire T_4456 : UInt<3>[2] - T_4456[0] <= UInt<3>("h05") - T_4456[1] <= UInt<3>("h04") - node T_4460 = eq(T_4456[0], T_4417.io.out.bits.g_type) - node T_4461 = eq(T_4456[1], T_4417.io.out.bits.g_type) - node T_4463 = or(UInt<1>("h00"), T_4460) - node T_4464 = or(T_4463, T_4461) - wire T_4466 : UInt<1>[2] - T_4466[0] <= UInt<1>("h00") - T_4466[1] <= UInt<1>("h01") - node T_4470 = eq(T_4466[0], T_4417.io.out.bits.g_type) - node T_4471 = eq(T_4466[1], T_4417.io.out.bits.g_type) - node T_4473 = or(UInt<1>("h00"), T_4470) - node T_4474 = or(T_4473, T_4471) - node T_4475 = mux(T_4417.io.out.bits.is_builtin_type, T_4464, T_4474) - node T_4476 = and(T_4417.io.out.valid, T_4475) - node T_4478 = lt(T_4417.io.out.bits.client_xact_id, UInt<2>("h02")) - node T_4479 = and(T_4476, T_4478) - writeArb.io.in[1].valid <= T_4479 + inst T_4171 of FlowThroughSerializer + T_4171.io is invalid + T_4171.clk <= clk + T_4171.reset <= reset + T_4171.io.in.valid <= io.mem.grant.valid + T_4171.io.in.bits <- io.mem.grant.bits + io.mem.grant.ready <= T_4171.io.in.ready + node T_4172 = and(T_4171.io.out.ready, T_4171.io.out.valid) + mshrs.io.mem_grant.valid <= T_4172 + mshrs.io.mem_grant.bits <- T_4171.io.out.bits + wire T_4176 : UInt<3>[2] + T_4176[0] <= UInt<3>("h05") + T_4176[1] <= UInt<3>("h04") + node T_4180 = eq(T_4176[0], T_4171.io.out.bits.g_type) + node T_4181 = eq(T_4176[1], T_4171.io.out.bits.g_type) + node T_4183 = or(UInt<1>("h00"), T_4180) + node T_4184 = or(T_4183, T_4181) + wire T_4186 : UInt<1>[2] + T_4186[0] <= UInt<1>("h00") + T_4186[1] <= UInt<1>("h01") + node T_4190 = eq(T_4186[0], T_4171.io.out.bits.g_type) + node T_4191 = eq(T_4186[1], T_4171.io.out.bits.g_type) + node T_4193 = or(UInt<1>("h00"), T_4190) + node T_4194 = or(T_4193, T_4191) + node T_4195 = mux(T_4171.io.out.bits.is_builtin_type, T_4184, T_4194) + node T_4197 = eq(T_4195, UInt<1>("h00")) + node T_4198 = or(writeArb.io.in[1].ready, T_4197) + T_4171.io.out.ready <= T_4198 + wire T_4202 : UInt<3>[2] + T_4202[0] <= UInt<3>("h05") + T_4202[1] <= UInt<3>("h04") + node T_4206 = eq(T_4202[0], T_4171.io.out.bits.g_type) + node T_4207 = eq(T_4202[1], T_4171.io.out.bits.g_type) + node T_4209 = or(UInt<1>("h00"), T_4206) + node T_4210 = or(T_4209, T_4207) + wire T_4212 : UInt<1>[2] + T_4212[0] <= UInt<1>("h00") + T_4212[1] <= UInt<1>("h01") + node T_4216 = eq(T_4212[0], T_4171.io.out.bits.g_type) + node T_4217 = eq(T_4212[1], T_4171.io.out.bits.g_type) + node T_4219 = or(UInt<1>("h00"), T_4216) + node T_4220 = or(T_4219, T_4217) + node T_4221 = mux(T_4171.io.out.bits.is_builtin_type, T_4210, T_4220) + node T_4222 = and(T_4171.io.out.valid, T_4221) + node T_4224 = lt(T_4171.io.out.bits.client_xact_id, UInt<2>("h02")) + node T_4225 = and(T_4222, T_4224) + writeArb.io.in[1].valid <= T_4225 writeArb.io.in[1].bits.addr <= mshrs.io.refill.addr writeArb.io.in[1].bits.way_en <= mshrs.io.refill.way_en - node T_4481 = not(UInt<2>("h00")) - writeArb.io.in[1].bits.wmask <= T_4481 - node T_4482 = bits(T_4417.io.out.bits.data, 127, 0) - writeArb.io.in[1].bits.data <= T_4482 + node T_4227 = not(UInt<2>("h00")) + writeArb.io.in[1].bits.wmask <= T_4227 + node T_4228 = bits(T_4171.io.out.bits.data, 127, 0) + writeArb.io.in[1].bits.data <= T_4228 data.io.read <- readArb.io.out - node T_4484 = eq(T_4417.io.out.valid, UInt<1>("h00")) - node T_4485 = or(T_4484, T_4417.io.out.ready) - readArb.io.out.ready <= T_4485 + node T_4230 = eq(T_4171.io.out.valid, UInt<1>("h00")) + node T_4231 = or(T_4230, T_4171.io.out.ready) + readArb.io.out.ready <= T_4231 inst wbArb of Arbiter_95 - wbArb.io.out.ready <= UInt<1>("h00") - wbArb.io.in[0].bits.way_en <= UInt<1>("h00") - wbArb.io.in[0].bits.data <= UInt<1>("h00") - wbArb.io.in[0].bits.r_type <= UInt<1>("h00") - wbArb.io.in[0].bits.voluntary <= UInt<1>("h00") - wbArb.io.in[0].bits.client_xact_id <= UInt<1>("h00") - wbArb.io.in[0].bits.addr_block <= UInt<1>("h00") - wbArb.io.in[0].bits.addr_beat <= UInt<1>("h00") - wbArb.io.in[0].valid <= UInt<1>("h00") - wbArb.io.in[1].bits.way_en <= UInt<1>("h00") - wbArb.io.in[1].bits.data <= UInt<1>("h00") - wbArb.io.in[1].bits.r_type <= UInt<1>("h00") - wbArb.io.in[1].bits.voluntary <= UInt<1>("h00") - wbArb.io.in[1].bits.client_xact_id <= UInt<1>("h00") - wbArb.io.in[1].bits.addr_block <= UInt<1>("h00") - wbArb.io.in[1].bits.addr_beat <= UInt<1>("h00") - wbArb.io.in[1].valid <= UInt<1>("h00") + wbArb.io is invalid wbArb.clk <= clk wbArb.reset <= reset wbArb.io.in[0] <- prober.io.wb_req @@ -33028,238 +25391,218 @@ circuit Top : readArb.io.in[2] <- wb.io.data_req wb.io.data_resp <= s2_data_corrected releaseArb.io.in[0] <- wb.io.release - reg s4_valid : UInt<1>, clk, reset, UInt<1>("h00") + reg s4_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) s4_valid <= s3_valid - node T_4537 = and(s3_valid, metaReadArb.io.out.valid) - reg s4_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk, UInt<1>("h00"), s4_req - when T_4537 : + node T_4266 = and(s3_valid, metaReadArb.io.out.valid) + reg s4_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk + when T_4266 : s4_req <- s3_req skip - node T_4592 = or(s2_valid_masked, s2_replay) - node T_4594 = eq(s2_sc_fail, UInt<1>("h00")) - node T_4595 = and(T_4592, T_4594) - node T_4596 = shr(s1_addr, 3) - node T_4597 = shr(s2_req.addr, 3) - node T_4598 = eq(T_4596, T_4597) - node T_4599 = and(T_4595, T_4598) - node T_4600 = eq(s2_req.cmd, UInt<5>("h01")) - node T_4601 = eq(s2_req.cmd, UInt<5>("h07")) - node T_4602 = or(T_4600, T_4601) - node T_4603 = bit(s2_req.cmd, 3) - node T_4604 = eq(s2_req.cmd, UInt<5>("h04")) - node T_4605 = or(T_4603, T_4604) - node T_4606 = or(T_4602, T_4605) - node T_4607 = and(T_4599, T_4606) - node T_4608 = shr(s1_addr, 3) - node T_4609 = shr(s3_req.addr, 3) - node T_4610 = eq(T_4608, T_4609) - node T_4611 = and(s3_valid, T_4610) - node T_4612 = eq(s3_req.cmd, UInt<5>("h01")) - node T_4613 = eq(s3_req.cmd, UInt<5>("h07")) - node T_4614 = or(T_4612, T_4613) - node T_4615 = bit(s3_req.cmd, 3) - node T_4616 = eq(s3_req.cmd, UInt<5>("h04")) - node T_4617 = or(T_4615, T_4616) - node T_4618 = or(T_4614, T_4617) - node T_4619 = and(T_4611, T_4618) - node T_4620 = shr(s1_addr, 3) - node T_4621 = shr(s4_req.addr, 3) - node T_4622 = eq(T_4620, T_4621) - node T_4623 = and(s4_valid, T_4622) - node T_4624 = eq(s4_req.cmd, UInt<5>("h01")) - node T_4625 = eq(s4_req.cmd, UInt<5>("h07")) - node T_4626 = or(T_4624, T_4625) - node T_4627 = bit(s4_req.cmd, 3) - node T_4628 = eq(s4_req.cmd, UInt<5>("h04")) - node T_4629 = or(T_4627, T_4628) - node T_4630 = or(T_4626, T_4629) - node T_4631 = and(T_4623, T_4630) - reg s2_store_bypass_data : UInt<64>, clk, UInt<1>("h00"), s2_store_bypass_data - reg s2_store_bypass : UInt<1>, clk, UInt<1>("h00"), s2_store_bypass + node T_4321 = or(s2_valid_masked, s2_replay) + node T_4323 = eq(s2_sc_fail, UInt<1>("h00")) + node T_4324 = and(T_4321, T_4323) + node T_4325 = shr(s1_addr, 3) + node T_4326 = shr(s2_req.addr, 3) + node T_4327 = eq(T_4325, T_4326) + node T_4328 = and(T_4324, T_4327) + node T_4329 = eq(s2_req.cmd, UInt<5>("h01")) + node T_4330 = eq(s2_req.cmd, UInt<5>("h07")) + node T_4331 = or(T_4329, T_4330) + node T_4332 = bits(s2_req.cmd, 3, 3) + node T_4333 = eq(s2_req.cmd, UInt<5>("h04")) + node T_4334 = or(T_4332, T_4333) + node T_4335 = or(T_4331, T_4334) + node T_4336 = and(T_4328, T_4335) + node T_4337 = shr(s1_addr, 3) + node T_4338 = shr(s3_req.addr, 3) + node T_4339 = eq(T_4337, T_4338) + node T_4340 = and(s3_valid, T_4339) + node T_4341 = eq(s3_req.cmd, UInt<5>("h01")) + node T_4342 = eq(s3_req.cmd, UInt<5>("h07")) + node T_4343 = or(T_4341, T_4342) + node T_4344 = bits(s3_req.cmd, 3, 3) + node T_4345 = eq(s3_req.cmd, UInt<5>("h04")) + node T_4346 = or(T_4344, T_4345) + node T_4347 = or(T_4343, T_4346) + node T_4348 = and(T_4340, T_4347) + node T_4349 = shr(s1_addr, 3) + node T_4350 = shr(s4_req.addr, 3) + node T_4351 = eq(T_4349, T_4350) + node T_4352 = and(s4_valid, T_4351) + node T_4353 = eq(s4_req.cmd, UInt<5>("h01")) + node T_4354 = eq(s4_req.cmd, UInt<5>("h07")) + node T_4355 = or(T_4353, T_4354) + node T_4356 = bits(s4_req.cmd, 3, 3) + node T_4357 = eq(s4_req.cmd, UInt<5>("h04")) + node T_4358 = or(T_4356, T_4357) + node T_4359 = or(T_4355, T_4358) + node T_4360 = and(T_4352, T_4359) + reg s2_store_bypass_data : UInt<64>, clk + reg s2_store_bypass : UInt<1>, clk when s1_clk_en : s2_store_bypass <= UInt<1>("h00") - node T_4637 = or(T_4607, T_4619) - node T_4638 = or(T_4637, T_4631) - when T_4638 : - node T_4639 = mux(T_4619, s3_req.data, s4_req.data) - node T_4640 = mux(T_4607, amoalu.io.out, T_4639) - s2_store_bypass_data <= T_4640 + node T_4366 = or(T_4336, T_4348) + node T_4367 = or(T_4366, T_4360) + when T_4367 : + node T_4368 = mux(T_4348, s3_req.data, s4_req.data) + node T_4369 = mux(T_4336, amoalu.io.out, T_4368) + s2_store_bypass_data <= T_4369 s2_store_bypass <= UInt<1>("h01") skip skip - node T_4643 = cat(UInt<1>("h00"), UInt<6>("h00")) - node s2_data_word_prebypass = dshr(s2_data_uncorrected, T_4643) + node T_4372 = cat(UInt<1>("h00"), UInt<6>("h00")) + node s2_data_word_prebypass = dshr(s2_data_uncorrected, T_4372) node s2_data_word = mux(s2_store_bypass, s2_store_bypass_data, s2_data_word_prebypass) - node T_4646 = bits(s2_req.typ, 1, 0) - node T_4647 = asSInt(s2_req.typ) - node T_4649 = geq(T_4647, asSInt(UInt<1>("h00"))) + node T_4375 = bits(s2_req.typ, 1, 0) + node T_4376 = asSInt(s2_req.typ) + node T_4378 = geq(T_4376, asSInt(UInt<1>("h00"))) amoalu.io.addr <= s2_req.addr amoalu.io.cmd <= s2_req.cmd amoalu.io.typ <= s2_req.typ amoalu.io.lhs <= s2_data_word amoalu.io.rhs <= s2_req.data - node T_4650 = and(dtlb.io.req.valid, dtlb.io.resp.miss) - node T_4651 = bits(s1_req.addr, 11, 6) - node T_4652 = eq(T_4651, prober.io.meta_write.bits.idx) - node T_4654 = eq(prober.io.req.ready, UInt<1>("h00")) - node T_4655 = and(T_4652, T_4654) - node s1_nack = or(T_4650, T_4655) - node T_4657 = or(s1_valid, s1_replay) - reg s2_nack_hit : UInt<1>, clk, UInt<1>("h00"), s2_nack_hit - when T_4657 : + node T_4379 = and(dtlb.io.req.valid, dtlb.io.resp.miss) + node T_4380 = bits(s1_req.addr, 11, 6) + node T_4381 = eq(T_4380, prober.io.meta_write.bits.idx) + node T_4383 = eq(prober.io.req.ready, UInt<1>("h00")) + node T_4384 = and(T_4381, T_4383) + node s1_nack = or(T_4379, T_4384) + node T_4386 = or(s1_valid, s1_replay) + reg s2_nack_hit : UInt<1>, clk + when T_4386 : s2_nack_hit <= s1_nack skip when s2_nack_hit : mshrs.io.req.valid <= UInt<1>("h00") skip node s2_nack_victim = and(s2_hit, mshrs.io.secondary_miss) - node T_4662 = eq(s2_hit, UInt<1>("h00")) - node T_4664 = eq(mshrs.io.req.ready, UInt<1>("h00")) - node s2_nack_miss = and(T_4662, T_4664) - node T_4666 = or(s2_nack_hit, s2_nack_victim) - node s2_nack = or(T_4666, s2_nack_miss) - node T_4669 = eq(s2_nack, UInt<1>("h00")) - node T_4670 = and(s2_valid, T_4669) - s2_valid_masked <= T_4670 - node T_4671 = or(s2_valid, s2_replay) - node T_4672 = and(T_4671, s2_hit) - node s2_recycle_ecc = and(T_4672, s2_data_correctable) - reg s2_recycle_next : UInt<1>, clk, reset, UInt<1>("h00") - node T_4676 = or(s1_valid, s1_replay) - when T_4676 : + node T_4391 = eq(s2_hit, UInt<1>("h00")) + node T_4393 = eq(mshrs.io.req.ready, UInt<1>("h00")) + node s2_nack_miss = and(T_4391, T_4393) + node T_4395 = or(s2_nack_hit, s2_nack_victim) + node s2_nack = or(T_4395, s2_nack_miss) + node T_4398 = eq(s2_nack, UInt<1>("h00")) + node T_4399 = and(s2_valid, T_4398) + s2_valid_masked <= T_4399 + node T_4400 = or(s2_valid, s2_replay) + node T_4401 = and(T_4400, s2_hit) + node s2_recycle_ecc = and(T_4401, s2_data_correctable) + reg s2_recycle_next : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_4405 = or(s1_valid, s1_replay) + when T_4405 : s2_recycle_next <= s2_recycle_ecc skip - node T_4677 = or(s2_recycle_ecc, s2_recycle_next) - s2_recycle <= T_4677 - reg block_miss : UInt<1>, clk, reset, UInt<1>("h00") - node T_4680 = or(s2_valid, block_miss) - node T_4681 = and(T_4680, s2_nack_miss) - block_miss <= T_4681 + node T_4406 = or(s2_recycle_ecc, s2_recycle_next) + s2_recycle <= T_4406 + reg block_miss : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_4409 = or(s2_valid, block_miss) + node T_4410 = and(T_4409, s2_nack_miss) + block_miss <= T_4410 when block_miss : io.cpu.req.ready <= UInt<1>("h00") skip wire cache_resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}} - cache_resp.bits.store_data <= UInt<1>("h00") - cache_resp.bits.data_word_bypass <= UInt<1>("h00") - cache_resp.bits.has_data <= UInt<1>("h00") - cache_resp.bits.replay <= UInt<1>("h00") - cache_resp.bits.nack <= UInt<1>("h00") - cache_resp.bits.data <= UInt<1>("h00") - cache_resp.bits.typ <= UInt<1>("h00") - cache_resp.bits.cmd <= UInt<1>("h00") - cache_resp.bits.tag <= UInt<1>("h00") - cache_resp.bits.addr <= UInt<1>("h00") - cache_resp.valid <= UInt<1>("h00") - node T_4983 = and(s2_valid_masked, s2_hit) - node T_4984 = or(s2_replay, T_4983) - node T_4986 = eq(s2_data_correctable, UInt<1>("h00")) - node T_4987 = and(T_4984, T_4986) - cache_resp.valid <= T_4987 + cache_resp is invalid + node T_4701 = and(s2_valid_masked, s2_hit) + node T_4702 = or(s2_replay, T_4701) + node T_4704 = eq(s2_data_correctable, UInt<1>("h00")) + node T_4705 = and(T_4702, T_4704) + cache_resp.valid <= T_4705 cache_resp.bits <- s2_req - node T_4988 = eq(s2_req.cmd, UInt<5>("h00")) - node T_4989 = eq(s2_req.cmd, UInt<5>("h06")) - node T_4990 = or(T_4988, T_4989) - node T_4991 = eq(s2_req.cmd, UInt<5>("h07")) - node T_4992 = or(T_4990, T_4991) - node T_4993 = bit(s2_req.cmd, 3) - node T_4994 = eq(s2_req.cmd, UInt<5>("h04")) - node T_4995 = or(T_4993, T_4994) - node T_4996 = or(T_4992, T_4995) - cache_resp.bits.has_data <= T_4996 - node T_4997 = bit(s2_req.addr, 2) - node T_4998 = bits(s2_data_word, 63, 32) - node T_4999 = bits(s2_data_word, 31, 0) - node T_5000 = mux(T_4997, T_4998, T_4999) - node T_5002 = and(UInt<1>("h00"), s2_sc) - node T_5004 = mux(T_5002, UInt<1>("h00"), T_5000) - node T_5006 = eq(T_4646, UInt<2>("h02")) - node T_5007 = or(T_5006, T_5002) - node T_5008 = bit(T_5004, 31) - node T_5009 = and(T_4649, T_5008) - node T_5011 = subw(UInt<32>("h00"), T_5009) - node T_5012 = bits(s2_data_word, 63, 32) - node T_5013 = mux(T_5007, T_5011, T_5012) - node T_5014 = cat(T_5013, T_5004) - node T_5015 = bit(s2_req.addr, 1) - node T_5016 = bits(T_5014, 31, 16) - node T_5017 = bits(T_5014, 15, 0) - node T_5018 = mux(T_5015, T_5016, T_5017) - node T_5020 = and(UInt<1>("h00"), s2_sc) - node T_5022 = mux(T_5020, UInt<1>("h00"), T_5018) - node T_5024 = eq(T_4646, UInt<1>("h01")) - node T_5025 = or(T_5024, T_5020) - node T_5026 = bit(T_5022, 15) - node T_5027 = and(T_4649, T_5026) - node T_5029 = subw(UInt<48>("h00"), T_5027) - node T_5030 = bits(T_5014, 63, 16) - node T_5031 = mux(T_5025, T_5029, T_5030) - node T_5032 = cat(T_5031, T_5022) - node T_5033 = bit(s2_req.addr, 0) - node T_5034 = bits(T_5032, 15, 8) - node T_5035 = bits(T_5032, 7, 0) - node T_5036 = mux(T_5033, T_5034, T_5035) - node T_5038 = and(UInt<1>("h01"), s2_sc) - node T_5040 = mux(T_5038, UInt<1>("h00"), T_5036) - node T_5042 = eq(T_4646, UInt<1>("h00")) - node T_5043 = or(T_5042, T_5038) - node T_5044 = bit(T_5040, 7) - node T_5045 = and(T_4649, T_5044) - node T_5047 = subw(UInt<56>("h00"), T_5045) - node T_5048 = bits(T_5032, 63, 8) - node T_5049 = mux(T_5043, T_5047, T_5048) - node T_5050 = cat(T_5049, T_5040) - node T_5051 = or(T_5050, s2_sc_fail) - cache_resp.bits.data <= T_5051 + node T_4706 = eq(s2_req.cmd, UInt<5>("h00")) + node T_4707 = eq(s2_req.cmd, UInt<5>("h06")) + node T_4708 = or(T_4706, T_4707) + node T_4709 = eq(s2_req.cmd, UInt<5>("h07")) + node T_4710 = or(T_4708, T_4709) + node T_4711 = bits(s2_req.cmd, 3, 3) + node T_4712 = eq(s2_req.cmd, UInt<5>("h04")) + node T_4713 = or(T_4711, T_4712) + node T_4714 = or(T_4710, T_4713) + cache_resp.bits.has_data <= T_4714 + node T_4715 = bits(s2_req.addr, 2, 2) + node T_4716 = bits(s2_data_word, 63, 32) + node T_4717 = bits(s2_data_word, 31, 0) + node T_4718 = mux(T_4715, T_4716, T_4717) + node T_4720 = and(UInt<1>("h00"), s2_sc) + node T_4722 = mux(T_4720, UInt<1>("h00"), T_4718) + node T_4724 = eq(T_4375, UInt<2>("h02")) + node T_4725 = or(T_4724, T_4720) + node T_4726 = bits(T_4722, 31, 31) + node T_4727 = and(T_4378, T_4726) + node T_4729 = sub(UInt<32>("h00"), T_4727) + node T_4730 = tail(T_4729, 1) + node T_4731 = bits(s2_data_word, 63, 32) + node T_4732 = mux(T_4725, T_4730, T_4731) + node T_4733 = cat(T_4732, T_4722) + node T_4734 = bits(s2_req.addr, 1, 1) + node T_4735 = bits(T_4733, 31, 16) + node T_4736 = bits(T_4733, 15, 0) + node T_4737 = mux(T_4734, T_4735, T_4736) + node T_4739 = and(UInt<1>("h00"), s2_sc) + node T_4741 = mux(T_4739, UInt<1>("h00"), T_4737) + node T_4743 = eq(T_4375, UInt<1>("h01")) + node T_4744 = or(T_4743, T_4739) + node T_4745 = bits(T_4741, 15, 15) + node T_4746 = and(T_4378, T_4745) + node T_4748 = sub(UInt<48>("h00"), T_4746) + node T_4749 = tail(T_4748, 1) + node T_4750 = bits(T_4733, 63, 16) + node T_4751 = mux(T_4744, T_4749, T_4750) + node T_4752 = cat(T_4751, T_4741) + node T_4753 = bits(s2_req.addr, 0, 0) + node T_4754 = bits(T_4752, 15, 8) + node T_4755 = bits(T_4752, 7, 0) + node T_4756 = mux(T_4753, T_4754, T_4755) + node T_4758 = and(UInt<1>("h01"), s2_sc) + node T_4760 = mux(T_4758, UInt<1>("h00"), T_4756) + node T_4762 = eq(T_4375, UInt<1>("h00")) + node T_4763 = or(T_4762, T_4758) + node T_4764 = bits(T_4760, 7, 7) + node T_4765 = and(T_4378, T_4764) + node T_4767 = sub(UInt<56>("h00"), T_4765) + node T_4768 = tail(T_4767, 1) + node T_4769 = bits(T_4752, 63, 8) + node T_4770 = mux(T_4763, T_4768, T_4769) + node T_4771 = cat(T_4770, T_4760) + node T_4772 = or(T_4771, s2_sc_fail) + cache_resp.bits.data <= T_4772 cache_resp.bits.store_data <= s2_req.data - node T_5052 = and(s2_valid, s2_nack) - cache_resp.bits.nack <= T_5052 + node T_4773 = and(s2_valid, s2_nack) + cache_resp.bits.nack <= T_4773 cache_resp.bits.replay <= s2_replay wire uncache_resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}} - uncache_resp.bits.store_data <= UInt<1>("h00") - uncache_resp.bits.data_word_bypass <= UInt<1>("h00") - uncache_resp.bits.has_data <= UInt<1>("h00") - uncache_resp.bits.replay <= UInt<1>("h00") - uncache_resp.bits.nack <= UInt<1>("h00") - uncache_resp.bits.data <= UInt<1>("h00") - uncache_resp.bits.typ <= UInt<1>("h00") - uncache_resp.bits.cmd <= UInt<1>("h00") - uncache_resp.bits.tag <= UInt<1>("h00") - uncache_resp.bits.addr <= UInt<1>("h00") - uncache_resp.valid <= UInt<1>("h00") + uncache_resp is invalid uncache_resp.bits <- mshrs.io.resp.bits uncache_resp.valid <= mshrs.io.resp.valid - node T_5353 = or(s2_valid, s2_killed) - node cache_pass = or(T_5353, s2_replay) - node T_5356 = eq(cache_pass, UInt<1>("h00")) - mshrs.io.resp.ready <= T_5356 - wire T_5473 : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}} - T_5473 <- uncache_resp - when cache_pass : - T_5473 <- cache_resp - skip - io.cpu.resp <- T_5473 - node T_5589 = bit(s2_req.addr, 2) - node T_5590 = bits(s2_data_word, 63, 32) - node T_5591 = bits(s2_data_word, 31, 0) - node T_5592 = mux(T_5589, T_5590, T_5591) - node T_5594 = and(UInt<1>("h00"), s2_sc) - node T_5596 = mux(T_5594, UInt<1>("h00"), T_5592) - node T_5598 = eq(T_4646, UInt<2>("h02")) - node T_5599 = or(T_5598, T_5594) - node T_5600 = bit(T_5596, 31) - node T_5601 = and(T_4649, T_5600) - node T_5603 = subw(UInt<32>("h00"), T_5601) - node T_5604 = bits(s2_data_word, 63, 32) - node T_5605 = mux(T_5599, T_5603, T_5604) - node T_5606 = cat(T_5605, T_5596) - io.cpu.resp.bits.data_word_bypass <= T_5606 - node T_5608 = eq(s1_valid, UInt<1>("h00")) - node T_5609 = and(mshrs.io.fence_rdy, T_5608) - node T_5611 = eq(s2_valid, UInt<1>("h00")) - node T_5612 = and(T_5609, T_5611) - io.cpu.ordered <= T_5612 - node T_5613 = and(s1_replay, s1_read) - io.cpu.replay_next.valid <= T_5613 + node T_5063 = or(s2_valid, s2_killed) + node cache_pass = or(T_5063, s2_replay) + node T_5066 = eq(cache_pass, UInt<1>("h00")) + mshrs.io.resp.ready <= T_5066 + node T_5067 = mux(cache_pass, cache_resp, uncache_resp) + io.cpu.resp <- T_5067 + node T_5183 = bits(s2_req.addr, 2, 2) + node T_5184 = bits(s2_data_word, 63, 32) + node T_5185 = bits(s2_data_word, 31, 0) + node T_5186 = mux(T_5183, T_5184, T_5185) + node T_5188 = and(UInt<1>("h00"), s2_sc) + node T_5190 = mux(T_5188, UInt<1>("h00"), T_5186) + node T_5192 = eq(T_4375, UInt<2>("h02")) + node T_5193 = or(T_5192, T_5188) + node T_5194 = bits(T_5190, 31, 31) + node T_5195 = and(T_4378, T_5194) + node T_5197 = sub(UInt<32>("h00"), T_5195) + node T_5198 = tail(T_5197, 1) + node T_5199 = bits(s2_data_word, 63, 32) + node T_5200 = mux(T_5193, T_5198, T_5199) + node T_5201 = cat(T_5200, T_5190) + io.cpu.resp.bits.data_word_bypass <= T_5201 + node T_5203 = eq(s1_valid, UInt<1>("h00")) + node T_5204 = and(mshrs.io.fence_rdy, T_5203) + node T_5206 = eq(s2_valid, UInt<1>("h00")) + node T_5207 = and(T_5204, T_5206) + io.cpu.ordered <= T_5207 + node T_5208 = and(s1_replay, s1_read) + io.cpu.replay_next.valid <= T_5208 io.cpu.replay_next.bits <= s1_req.tag module RRArbiter_112 : @@ -33267,57 +25610,50 @@ circuit Top : input reset : UInt<1> output io : {flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}[2], out : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, chosen : UInt<1>} - io.chosen <= UInt<1>("h00") - io.out.bits.fetch <= UInt<1>("h00") - io.out.bits.store <= UInt<1>("h00") - io.out.bits.prv <= UInt<1>("h00") - io.out.bits.addr <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.in[0].ready <= UInt<1>("h00") - io.in[1].ready <= UInt<1>("h00") + io is invalid wire T_152 : UInt<1> - T_152 <= UInt<1>("h00") + T_152 is invalid io.out.valid <= io.in[T_152].valid io.out.bits <- io.in[T_152].bits io.chosen <= T_152 io.in[T_152].ready <= UInt<1>("h00") - reg T_196 : UInt<1>, clk, reset, UInt<1>("h00") - node T_197 = gt(UInt<1>("h00"), T_196) - node T_198 = and(io.in[0].valid, T_197) - node T_200 = gt(UInt<1>("h01"), T_196) - node T_201 = and(io.in[1].valid, T_200) - node T_204 = or(UInt<1>("h00"), T_198) - node T_206 = eq(T_204, UInt<1>("h00")) - node T_208 = or(UInt<1>("h00"), T_198) - node T_209 = or(T_208, T_201) - node T_211 = eq(T_209, UInt<1>("h00")) - node T_213 = or(UInt<1>("h00"), T_198) - node T_214 = or(T_213, T_201) - node T_215 = or(T_214, io.in[0].valid) - node T_217 = eq(T_215, UInt<1>("h00")) - node T_219 = gt(UInt<1>("h00"), T_196) - node T_220 = and(UInt<1>("h01"), T_219) - node T_221 = or(T_220, T_211) - node T_223 = gt(UInt<1>("h01"), T_196) - node T_224 = and(T_206, T_223) - node T_225 = or(T_224, T_217) - node T_227 = eq(UInt<1>("h01"), UInt<1>("h00")) - node T_228 = mux(UInt<1>("h00"), T_227, T_221) - node T_229 = and(T_228, io.out.ready) - io.in[0].ready <= T_229 - node T_231 = eq(UInt<1>("h01"), UInt<1>("h01")) - node T_232 = mux(UInt<1>("h00"), T_231, T_225) - node T_233 = and(T_232, io.out.ready) - io.in[1].ready <= T_233 - node T_236 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) - node T_238 = gt(UInt<1>("h01"), T_196) - node T_239 = and(io.in[1].valid, T_238) - node T_241 = mux(T_239, UInt<1>("h01"), T_236) - node T_242 = mux(UInt<1>("h00"), UInt<1>("h01"), T_241) - T_152 <= T_242 - node T_243 = and(io.out.ready, io.out.valid) - when T_243 : - T_196 <= T_152 + reg T_195 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + node T_196 = gt(UInt<1>("h00"), T_195) + node T_197 = and(io.in[0].valid, T_196) + node T_199 = gt(UInt<1>("h01"), T_195) + node T_200 = and(io.in[1].valid, T_199) + node T_203 = or(UInt<1>("h00"), T_197) + node T_205 = eq(T_203, UInt<1>("h00")) + node T_207 = or(UInt<1>("h00"), T_197) + node T_208 = or(T_207, T_200) + node T_210 = eq(T_208, UInt<1>("h00")) + node T_212 = or(UInt<1>("h00"), T_197) + node T_213 = or(T_212, T_200) + node T_214 = or(T_213, io.in[0].valid) + node T_216 = eq(T_214, UInt<1>("h00")) + node T_218 = gt(UInt<1>("h00"), T_195) + node T_219 = and(UInt<1>("h01"), T_218) + node T_220 = or(T_219, T_210) + node T_222 = gt(UInt<1>("h01"), T_195) + node T_223 = and(T_205, T_222) + node T_224 = or(T_223, T_216) + node T_226 = eq(UInt<1>("h01"), UInt<1>("h00")) + node T_227 = mux(UInt<1>("h00"), T_226, T_220) + node T_228 = and(T_227, io.out.ready) + io.in[0].ready <= T_228 + node T_230 = eq(UInt<1>("h01"), UInt<1>("h01")) + node T_231 = mux(UInt<1>("h00"), T_230, T_224) + node T_232 = and(T_231, io.out.ready) + io.in[1].ready <= T_232 + node T_235 = mux(io.in[0].valid, UInt<1>("h00"), UInt<1>("h01")) + node T_237 = gt(UInt<1>("h01"), T_195) + node T_238 = and(io.in[1].valid, T_237) + node T_240 = mux(T_238, UInt<1>("h01"), T_235) + node T_241 = mux(UInt<1>("h00"), UInt<1>("h01"), T_240) + T_152 <= T_241 + node T_242 = and(io.out.ready, io.out.valid) + when T_242 : + T_195 <= T_152 skip module PTW : @@ -33325,72 +25661,12 @@ circuit Top : input reset : UInt<1> output io : {flip requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}[2], mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, dpath : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}}} - io.mem.invalidate_lr <= UInt<1>("h00") - io.mem.req.bits.data <= UInt<1>("h00") - io.mem.req.bits.phys <= UInt<1>("h00") - io.mem.req.bits.kill <= UInt<1>("h00") - io.mem.req.bits.typ <= UInt<1>("h00") - io.mem.req.bits.cmd <= UInt<1>("h00") - io.mem.req.bits.tag <= UInt<1>("h00") - io.mem.req.bits.addr <= UInt<1>("h00") - io.mem.req.valid <= UInt<1>("h00") - io.requestor[0].invalidate <= UInt<1>("h00") - io.requestor[0].status.ie <= UInt<1>("h00") - io.requestor[0].status.prv <= UInt<1>("h00") - io.requestor[0].status.ie1 <= UInt<1>("h00") - io.requestor[0].status.prv1 <= UInt<1>("h00") - io.requestor[0].status.ie2 <= UInt<1>("h00") - io.requestor[0].status.prv2 <= UInt<1>("h00") - io.requestor[0].status.ie3 <= UInt<1>("h00") - io.requestor[0].status.prv3 <= UInt<1>("h00") - io.requestor[0].status.fs <= UInt<1>("h00") - io.requestor[0].status.xs <= UInt<1>("h00") - io.requestor[0].status.mprv <= UInt<1>("h00") - io.requestor[0].status.vm <= UInt<1>("h00") - io.requestor[0].status.zero1 <= UInt<1>("h00") - io.requestor[0].status.sd_rv32 <= UInt<1>("h00") - io.requestor[0].status.zero2 <= UInt<1>("h00") - io.requestor[0].status.sd <= UInt<1>("h00") - io.requestor[0].resp.bits.pte.v <= UInt<1>("h00") - io.requestor[0].resp.bits.pte.typ <= UInt<1>("h00") - io.requestor[0].resp.bits.pte.r <= UInt<1>("h00") - io.requestor[0].resp.bits.pte.d <= UInt<1>("h00") - io.requestor[0].resp.bits.pte.reserved_for_software <= UInt<1>("h00") - io.requestor[0].resp.bits.pte.ppn <= UInt<1>("h00") - io.requestor[0].resp.bits.error <= UInt<1>("h00") - io.requestor[0].resp.valid <= UInt<1>("h00") - io.requestor[0].req.ready <= UInt<1>("h00") - io.requestor[1].invalidate <= UInt<1>("h00") - io.requestor[1].status.ie <= UInt<1>("h00") - io.requestor[1].status.prv <= UInt<1>("h00") - io.requestor[1].status.ie1 <= UInt<1>("h00") - io.requestor[1].status.prv1 <= UInt<1>("h00") - io.requestor[1].status.ie2 <= UInt<1>("h00") - io.requestor[1].status.prv2 <= UInt<1>("h00") - io.requestor[1].status.ie3 <= UInt<1>("h00") - io.requestor[1].status.prv3 <= UInt<1>("h00") - io.requestor[1].status.fs <= UInt<1>("h00") - io.requestor[1].status.xs <= UInt<1>("h00") - io.requestor[1].status.mprv <= UInt<1>("h00") - io.requestor[1].status.vm <= UInt<1>("h00") - io.requestor[1].status.zero1 <= UInt<1>("h00") - io.requestor[1].status.sd_rv32 <= UInt<1>("h00") - io.requestor[1].status.zero2 <= UInt<1>("h00") - io.requestor[1].status.sd <= UInt<1>("h00") - io.requestor[1].resp.bits.pte.v <= UInt<1>("h00") - io.requestor[1].resp.bits.pte.typ <= UInt<1>("h00") - io.requestor[1].resp.bits.pte.r <= UInt<1>("h00") - io.requestor[1].resp.bits.pte.d <= UInt<1>("h00") - io.requestor[1].resp.bits.pte.reserved_for_software <= UInt<1>("h00") - io.requestor[1].resp.bits.pte.ppn <= UInt<1>("h00") - io.requestor[1].resp.bits.error <= UInt<1>("h00") - io.requestor[1].resp.valid <= UInt<1>("h00") - io.requestor[1].req.ready <= UInt<1>("h00") - reg state : UInt<?>, clk, reset, UInt<1>("h00") - reg count : UInt<2>, clk, UInt<1>("h00"), count - reg r_req : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}, clk, UInt<1>("h00"), r_req - reg r_req_dest : UInt<?>, clk, UInt<1>("h00"), r_req_dest - reg r_pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}, clk, UInt<1>("h00"), r_pte + io is invalid + reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00"))) + reg count : UInt<2>, clk + reg r_req : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}, clk + reg r_req_dest : UInt<?>, clk + reg r_pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}, clk node T_1590 = shr(r_req.addr, 18) node T_1591 = bits(T_1590, 8, 0) node T_1592 = shr(r_req.addr, 9) @@ -33402,314 +25678,296 @@ circuit Top : T_1597[1] <= T_1593 T_1597[2] <= T_1595 inst arb of RRArbiter_112 - arb.io.out.ready <= UInt<1>("h00") - arb.io.in[0].bits.fetch <= UInt<1>("h00") - arb.io.in[0].bits.store <= UInt<1>("h00") - arb.io.in[0].bits.prv <= UInt<1>("h00") - arb.io.in[0].bits.addr <= UInt<1>("h00") - arb.io.in[0].valid <= UInt<1>("h00") - arb.io.in[1].bits.fetch <= UInt<1>("h00") - arb.io.in[1].bits.store <= UInt<1>("h00") - arb.io.in[1].bits.prv <= UInt<1>("h00") - arb.io.in[1].bits.addr <= UInt<1>("h00") - arb.io.in[1].valid <= UInt<1>("h00") + arb.io is invalid arb.clk <= clk arb.reset <= reset arb.io.in[0] <- io.requestor[0].req arb.io.in[1] <- io.requestor[1].req - node T_1620 = eq(state, UInt<1>("h00")) - arb.io.out.ready <= T_1620 + node T_1609 = eq(state, UInt<1>("h00")) + arb.io.out.ready <= T_1609 wire pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} - pte.v <= UInt<1>("h00") - pte.typ <= UInt<1>("h00") - pte.r <= UInt<1>("h00") - pte.d <= UInt<1>("h00") - pte.reserved_for_software <= UInt<1>("h00") - pte.ppn <= UInt<1>("h00") - node T_1648 = bits(io.mem.resp.bits.data, 0, 0) - pte.v <= T_1648 - node T_1649 = bits(io.mem.resp.bits.data, 4, 1) - pte.typ <= T_1649 - node T_1650 = bits(io.mem.resp.bits.data, 5, 5) - pte.r <= T_1650 - node T_1651 = bits(io.mem.resp.bits.data, 6, 6) - pte.d <= T_1651 - node T_1652 = bits(io.mem.resp.bits.data, 9, 7) - pte.reserved_for_software <= T_1652 - node T_1653 = bits(io.mem.resp.bits.data, 29, 10) - pte.ppn <= T_1653 - node T_1654 = cat(r_pte.ppn, T_1597[count]) - node pte_addr = shl(T_1654, 3) - node T_1656 = and(arb.io.out.ready, arb.io.out.valid) - when T_1656 : + pte is invalid + node T_1631 = bits(io.mem.resp.bits.data, 0, 0) + pte.v <= T_1631 + node T_1632 = bits(io.mem.resp.bits.data, 4, 1) + pte.typ <= T_1632 + node T_1633 = bits(io.mem.resp.bits.data, 5, 5) + pte.r <= T_1633 + node T_1634 = bits(io.mem.resp.bits.data, 6, 6) + pte.d <= T_1634 + node T_1635 = bits(io.mem.resp.bits.data, 9, 7) + pte.reserved_for_software <= T_1635 + node T_1636 = bits(io.mem.resp.bits.data, 29, 10) + pte.ppn <= T_1636 + node T_1637 = cat(r_pte.ppn, T_1597[count]) + node pte_addr = shl(T_1637, 3) + node T_1639 = and(arb.io.out.ready, arb.io.out.valid) + when T_1639 : r_req <- arb.io.out.bits r_req_dest <= arb.io.chosen - node T_1657 = bits(io.dpath.ptbr, 31, 12) - r_pte.ppn <= T_1657 - skip - reg T_1659 : UInt<3>, clk, UInt<1>("h00"), T_1659 - reg T_1669 : UInt<1>[3], clk, UInt<1>("h00"), T_1669 - node T_1674 = cat(T_1669[1], T_1669[0]) - node T_1675 = cat(T_1669[2], T_1674) - cmem T_1678 : UInt<32>[3] - cmem T_1681 : UInt<20>[3] - infer mport T_1683 = T_1678[UInt<1>("h00")], clk - node T_1684 = eq(T_1683, pte_addr) - infer mport T_1686 = T_1678[UInt<1>("h01")], clk - node T_1687 = eq(T_1686, pte_addr) - infer mport T_1689 = T_1678[UInt<2>("h02")], clk - node T_1690 = eq(T_1689, pte_addr) - wire T_1692 : UInt<1>[3] - T_1692[0] <= T_1684 - T_1692[1] <= T_1687 - T_1692[2] <= T_1690 - node T_1697 = cat(T_1692[1], T_1692[0]) - node T_1698 = cat(T_1692[2], T_1697) - node T_1699 = and(T_1698, T_1675) - node pte_cache_hit = neq(T_1699, UInt<1>("h00")) - node T_1703 = lt(pte.typ, UInt<2>("h02")) - node T_1704 = and(pte.v, T_1703) - node T_1705 = and(io.mem.resp.valid, T_1704) - node T_1707 = eq(pte_cache_hit, UInt<1>("h00")) - node T_1708 = and(T_1705, T_1707) - when T_1708 : - node T_1709 = not(T_1675) - node T_1711 = eq(T_1709, UInt<1>("h00")) - node T_1713 = dshr(T_1659, UInt<1>("h01")) - node T_1714 = bit(T_1713, 0) - node T_1715 = cat(UInt<1>("h01"), T_1714) - node T_1716 = dshr(T_1659, T_1715) - node T_1717 = bit(T_1716, 0) - node T_1718 = cat(T_1715, T_1717) - node T_1719 = bits(T_1718, 1, 0) - node T_1720 = not(T_1675) - node T_1721 = bit(T_1720, 0) - node T_1722 = bit(T_1720, 1) - node T_1723 = bit(T_1720, 2) - wire T_1725 : UInt<1>[3] - T_1725[0] <= T_1721 - T_1725[1] <= T_1722 - T_1725[2] <= T_1723 - node T_1733 = mux(T_1725[1], UInt<1>("h01"), UInt<2>("h02")) - node T_1734 = mux(T_1725[0], UInt<1>("h00"), T_1733) - node T_1735 = mux(T_1711, T_1719, T_1734) - T_1669[T_1735] <= UInt<1>("h01") - infer mport T_1738 = T_1678[T_1735], clk - T_1738 <= pte_addr - infer mport T_1739 = T_1681[T_1735], clk - T_1739 <= pte.ppn - skip - node T_1740 = eq(state, UInt<1>("h01")) - node T_1741 = and(pte_cache_hit, T_1740) - when T_1741 : - node T_1742 = bits(T_1699, 2, 2) - node T_1743 = bits(T_1699, 1, 0) - node T_1745 = neq(T_1742, UInt<1>("h00")) - node T_1746 = or(T_1742, T_1743) - node T_1747 = bit(T_1746, 1) - node T_1748 = cat(T_1745, T_1747) - node T_1750 = bit(T_1748, 1) - node T_1752 = dshl(UInt<3>("h01"), UInt<1>("h01")) - node T_1753 = bits(T_1752, 2, 0) - node T_1754 = not(T_1753) - node T_1755 = and(T_1659, T_1754) - node T_1757 = mux(T_1750, UInt<1>("h00"), T_1753) - node T_1758 = or(T_1755, T_1757) - node T_1759 = cat(UInt<1>("h01"), T_1750) - node T_1760 = bit(T_1748, 0) - node T_1762 = dshl(UInt<3>("h01"), T_1759) - node T_1763 = bits(T_1762, 2, 0) - node T_1764 = not(T_1763) - node T_1765 = and(T_1758, T_1764) - node T_1767 = mux(T_1760, UInt<1>("h00"), T_1763) - node T_1768 = or(T_1765, T_1767) - node T_1769 = cat(T_1759, T_1760) - T_1659 <= T_1768 - skip - node T_1770 = or(reset, io.dpath.invalidate) - when T_1770 : - T_1669[0] <= UInt<1>("h00") - T_1669[1] <= UInt<1>("h00") - T_1669[2] <= UInt<1>("h00") - skip - node T_1774 = bit(T_1699, 0) - node T_1775 = bit(T_1699, 1) - node T_1776 = bit(T_1699, 2) - infer mport T_1778 = T_1681[UInt<1>("h00")], clk - infer mport T_1780 = T_1681[UInt<1>("h01")], clk - infer mport T_1782 = T_1681[UInt<2>("h02")], clk - node T_1784 = mux(T_1774, T_1778, UInt<1>("h00")) - node T_1786 = mux(T_1775, T_1780, UInt<1>("h00")) - node T_1788 = mux(T_1776, T_1782, UInt<1>("h00")) - node T_1790 = or(T_1784, T_1786) - node T_1791 = or(T_1790, T_1788) + node T_1640 = bits(io.dpath.ptbr, 31, 12) + r_pte.ppn <= T_1640 + skip + reg T_1642 : UInt<3>, clk + reg T_1652 : UInt<1>[3], clk + node T_1657 = cat(T_1652[1], T_1652[0]) + node T_1658 = cat(T_1652[2], T_1657) + cmem T_1661 : UInt<32>[3] + cmem T_1664 : UInt<20>[3] + infer mport T_1666 = T_1661[UInt<1>("h00")], clk + node T_1667 = eq(T_1666, pte_addr) + infer mport T_1669 = T_1661[UInt<1>("h01")], clk + node T_1670 = eq(T_1669, pte_addr) + infer mport T_1672 = T_1661[UInt<2>("h02")], clk + node T_1673 = eq(T_1672, pte_addr) + wire T_1675 : UInt<1>[3] + T_1675[0] <= T_1667 + T_1675[1] <= T_1670 + T_1675[2] <= T_1673 + node T_1680 = cat(T_1675[1], T_1675[0]) + node T_1681 = cat(T_1675[2], T_1680) + node T_1682 = and(T_1681, T_1658) + node pte_cache_hit = neq(T_1682, UInt<1>("h00")) + node T_1686 = lt(pte.typ, UInt<2>("h02")) + node T_1687 = and(pte.v, T_1686) + node T_1688 = and(io.mem.resp.valid, T_1687) + node T_1690 = eq(pte_cache_hit, UInt<1>("h00")) + node T_1691 = and(T_1688, T_1690) + when T_1691 : + node T_1692 = not(T_1658) + node T_1694 = eq(T_1692, UInt<1>("h00")) + node T_1696 = dshr(T_1642, UInt<1>("h01")) + node T_1697 = bits(T_1696, 0, 0) + node T_1698 = cat(UInt<1>("h01"), T_1697) + node T_1699 = dshr(T_1642, T_1698) + node T_1700 = bits(T_1699, 0, 0) + node T_1701 = cat(T_1698, T_1700) + node T_1702 = bits(T_1701, 1, 0) + node T_1703 = not(T_1658) + node T_1704 = bits(T_1703, 0, 0) + node T_1705 = bits(T_1703, 1, 1) + node T_1706 = bits(T_1703, 2, 2) + wire T_1708 : UInt<1>[3] + T_1708[0] <= T_1704 + T_1708[1] <= T_1705 + T_1708[2] <= T_1706 + node T_1716 = mux(T_1708[1], UInt<1>("h01"), UInt<2>("h02")) + node T_1717 = mux(T_1708[0], UInt<1>("h00"), T_1716) + node T_1718 = mux(T_1694, T_1702, T_1717) + T_1652[T_1718] <= UInt<1>("h01") + infer mport T_1721 = T_1661[T_1718], clk + T_1721 <= pte_addr + infer mport T_1722 = T_1664[T_1718], clk + T_1722 <= pte.ppn + skip + node T_1723 = eq(state, UInt<1>("h01")) + node T_1724 = and(pte_cache_hit, T_1723) + when T_1724 : + node T_1725 = bits(T_1682, 2, 2) + node T_1726 = bits(T_1682, 1, 0) + node T_1728 = neq(T_1725, UInt<1>("h00")) + node T_1729 = or(T_1725, T_1726) + node T_1730 = bits(T_1729, 1, 1) + node T_1731 = cat(T_1728, T_1730) + node T_1733 = bits(T_1731, 1, 1) + node T_1735 = dshl(UInt<3>("h01"), UInt<1>("h01")) + node T_1736 = bits(T_1735, 2, 0) + node T_1737 = not(T_1736) + node T_1738 = and(T_1642, T_1737) + node T_1740 = mux(T_1733, UInt<1>("h00"), T_1736) + node T_1741 = or(T_1738, T_1740) + node T_1742 = cat(UInt<1>("h01"), T_1733) + node T_1743 = bits(T_1731, 0, 0) + node T_1745 = dshl(UInt<3>("h01"), T_1742) + node T_1746 = bits(T_1745, 2, 0) + node T_1747 = not(T_1746) + node T_1748 = and(T_1741, T_1747) + node T_1750 = mux(T_1743, UInt<1>("h00"), T_1746) + node T_1751 = or(T_1748, T_1750) + node T_1752 = cat(T_1742, T_1743) + T_1642 <= T_1751 + skip + node T_1753 = or(reset, io.dpath.invalidate) + when T_1753 : + T_1652[0] <= UInt<1>("h00") + T_1652[1] <= UInt<1>("h00") + T_1652[2] <= UInt<1>("h00") + skip + node T_1757 = bits(T_1682, 0, 0) + node T_1758 = bits(T_1682, 1, 1) + node T_1759 = bits(T_1682, 2, 2) + infer mport T_1761 = T_1664[UInt<1>("h00")], clk + infer mport T_1763 = T_1664[UInt<1>("h01")], clk + infer mport T_1765 = T_1664[UInt<2>("h02")], clk + node T_1767 = mux(T_1757, T_1761, UInt<1>("h00")) + node T_1769 = mux(T_1758, T_1763, UInt<1>("h00")) + node T_1771 = mux(T_1759, T_1765, UInt<1>("h00")) + node T_1773 = or(T_1767, T_1769) + node T_1774 = or(T_1773, T_1771) wire pte_cache_data : UInt<20> - pte_cache_data <= UInt<1>("h00") - pte_cache_data <= T_1791 - node T_1794 = bit(r_req.prv, 0) - node T_1796 = geq(pte.typ, UInt<3>("h04")) - node T_1797 = and(pte.v, T_1796) - node T_1798 = bit(pte.typ, 1) + pte_cache_data is invalid + pte_cache_data <= T_1774 + node T_1776 = bits(r_req.prv, 0, 0) + node T_1778 = geq(pte.typ, UInt<3>("h04")) + node T_1779 = and(pte.v, T_1778) + node T_1780 = bits(pte.typ, 1, 1) + node T_1781 = and(T_1779, T_1780) + node T_1783 = geq(pte.typ, UInt<2>("h02")) + node T_1784 = and(pte.v, T_1783) + node T_1785 = bits(pte.typ, 0, 0) + node T_1786 = and(T_1784, T_1785) + node T_1788 = geq(pte.typ, UInt<2>("h02")) + node T_1789 = and(pte.v, T_1788) + node T_1790 = mux(r_req.store, T_1786, T_1789) + node T_1791 = mux(r_req.fetch, T_1781, T_1790) + node T_1793 = geq(pte.typ, UInt<2>("h02")) + node T_1794 = and(pte.v, T_1793) + node T_1796 = lt(pte.typ, UInt<4>("h08")) + node T_1797 = and(T_1794, T_1796) + node T_1798 = bits(pte.typ, 1, 1) node T_1799 = and(T_1797, T_1798) node T_1801 = geq(pte.typ, UInt<2>("h02")) node T_1802 = and(pte.v, T_1801) - node T_1803 = bit(pte.typ, 0) - node T_1804 = and(T_1802, T_1803) - node T_1806 = geq(pte.typ, UInt<2>("h02")) - node T_1807 = and(pte.v, T_1806) - node T_1808 = mux(r_req.store, T_1804, T_1807) - node T_1809 = mux(r_req.fetch, T_1799, T_1808) - node T_1811 = geq(pte.typ, UInt<2>("h02")) - node T_1812 = and(pte.v, T_1811) - node T_1814 = lt(pte.typ, UInt<4>("h08")) - node T_1815 = and(T_1812, T_1814) - node T_1816 = bit(pte.typ, 1) - node T_1817 = and(T_1815, T_1816) - node T_1819 = geq(pte.typ, UInt<2>("h02")) - node T_1820 = and(pte.v, T_1819) - node T_1822 = lt(pte.typ, UInt<4>("h08")) - node T_1823 = and(T_1820, T_1822) - node T_1824 = bit(pte.typ, 0) - node T_1825 = and(T_1823, T_1824) - node T_1827 = geq(pte.typ, UInt<2>("h02")) - node T_1828 = and(pte.v, T_1827) - node T_1830 = lt(pte.typ, UInt<4>("h08")) - node T_1831 = and(T_1828, T_1830) - node T_1832 = mux(r_req.store, T_1825, T_1831) - node T_1833 = mux(r_req.fetch, T_1817, T_1832) - node perm_ok = mux(T_1794, T_1809, T_1833) - node T_1836 = eq(pte.r, UInt<1>("h00")) - node T_1838 = eq(pte.d, UInt<1>("h00")) - node T_1839 = and(r_req.store, T_1838) - node T_1840 = or(T_1836, T_1839) - node set_dirty_bit = and(perm_ok, T_1840) - node T_1842 = eq(state, UInt<2>("h02")) - node T_1843 = and(io.mem.resp.valid, T_1842) - node T_1845 = eq(set_dirty_bit, UInt<1>("h00")) - node T_1846 = and(T_1843, T_1845) - when T_1846 : + node T_1804 = lt(pte.typ, UInt<4>("h08")) + node T_1805 = and(T_1802, T_1804) + node T_1806 = bits(pte.typ, 0, 0) + node T_1807 = and(T_1805, T_1806) + node T_1809 = geq(pte.typ, UInt<2>("h02")) + node T_1810 = and(pte.v, T_1809) + node T_1812 = lt(pte.typ, UInt<4>("h08")) + node T_1813 = and(T_1810, T_1812) + node T_1814 = mux(r_req.store, T_1807, T_1813) + node T_1815 = mux(r_req.fetch, T_1799, T_1814) + node perm_ok = mux(T_1776, T_1791, T_1815) + node T_1818 = eq(pte.r, UInt<1>("h00")) + node T_1820 = eq(pte.d, UInt<1>("h00")) + node T_1821 = and(r_req.store, T_1820) + node T_1822 = or(T_1818, T_1821) + node set_dirty_bit = and(perm_ok, T_1822) + node T_1824 = eq(state, UInt<2>("h02")) + node T_1825 = and(io.mem.resp.valid, T_1824) + node T_1827 = eq(set_dirty_bit, UInt<1>("h00")) + node T_1828 = and(T_1825, T_1827) + when T_1828 : r_pte <- pte skip - wire T_1862 : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} - T_1862.v <= UInt<1>("h00") - T_1862.typ <= UInt<1>("h00") - T_1862.r <= UInt<1>("h00") - T_1862.d <= UInt<1>("h00") - T_1862.reserved_for_software <= UInt<1>("h00") - T_1862.ppn <= UInt<1>("h00") - T_1862.v <= UInt<1>("h00") - T_1862.typ <= UInt<4>("h00") - T_1862.r <= UInt<1>("h00") - T_1862.d <= UInt<1>("h00") - T_1862.reserved_for_software <= UInt<3>("h00") - T_1862.ppn <= UInt<20>("h00") + wire T_1844 : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} + T_1844 is invalid + T_1844.v <= UInt<1>("h00") + T_1844.typ <= UInt<4>("h00") + T_1844.r <= UInt<1>("h00") + T_1844.d <= UInt<1>("h00") + T_1844.reserved_for_software <= UInt<3>("h00") + T_1844.ppn <= UInt<20>("h00") wire pte_wdata : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>} - pte_wdata <- T_1862 + pte_wdata <- T_1844 pte_wdata.r <= UInt<1>("h01") pte_wdata.d <= r_req.store - node T_1889 = eq(state, UInt<1>("h01")) - node T_1890 = eq(state, UInt<2>("h03")) - node T_1891 = or(T_1889, T_1890) - io.mem.req.valid <= T_1891 + node T_1865 = eq(state, UInt<1>("h01")) + node T_1866 = eq(state, UInt<2>("h03")) + node T_1867 = or(T_1865, T_1866) + io.mem.req.valid <= T_1867 io.mem.req.bits.phys <= UInt<1>("h01") - node T_1893 = eq(state, UInt<2>("h03")) - node T_1894 = mux(T_1893, UInt<5>("h0a"), UInt<5>("h00")) - io.mem.req.bits.cmd <= T_1894 + node T_1869 = eq(state, UInt<2>("h03")) + node T_1870 = mux(T_1869, UInt<5>("h0a"), UInt<5>("h00")) + io.mem.req.bits.cmd <= T_1870 io.mem.req.bits.typ <= UInt<3>("h03") io.mem.req.bits.addr <= pte_addr io.mem.req.bits.kill <= UInt<1>("h00") - node T_1896 = cat(pte_wdata.reserved_for_software, pte_wdata.d) - node T_1897 = cat(pte_wdata.ppn, T_1896) - node T_1898 = cat(pte_wdata.typ, pte_wdata.v) - node T_1899 = cat(pte_wdata.r, T_1898) - node T_1900 = cat(T_1897, T_1899) - io.mem.req.bits.data <= T_1900 + node T_1872 = cat(pte_wdata.reserved_for_software, pte_wdata.d) + node T_1873 = cat(pte_wdata.ppn, T_1872) + node T_1874 = cat(pte_wdata.typ, pte_wdata.v) + node T_1875 = cat(pte_wdata.r, T_1874) + node T_1876 = cat(T_1873, T_1875) + io.mem.req.bits.data <= T_1876 node resp_err = eq(state, UInt<3>("h06")) - node T_1902 = eq(state, UInt<3>("h05")) - node resp_val = or(T_1902, resp_err) + node T_1878 = eq(state, UInt<3>("h05")) + node resp_val = or(T_1878, resp_err) node r_resp_ppn = shr(io.mem.req.bits.addr, 12) - node T_1905 = shr(r_resp_ppn, 18) - node T_1906 = bits(r_req.addr, 17, 0) - node T_1907 = cat(T_1905, T_1906) - node T_1908 = shr(r_resp_ppn, 9) - node T_1909 = bits(r_req.addr, 8, 0) - node T_1910 = cat(T_1908, T_1909) - wire T_1912 : UInt<28>[3] - T_1912[0] <= T_1907 - T_1912[1] <= T_1910 - T_1912[2] <= r_resp_ppn - node T_1919 = eq(r_req_dest, UInt<1>("h00")) - node T_1920 = and(resp_val, T_1919) - io.requestor[0].resp.valid <= T_1920 + node T_1881 = shr(r_resp_ppn, 18) + node T_1882 = bits(r_req.addr, 17, 0) + node T_1883 = cat(T_1881, T_1882) + node T_1884 = shr(r_resp_ppn, 9) + node T_1885 = bits(r_req.addr, 8, 0) + node T_1886 = cat(T_1884, T_1885) + wire T_1888 : UInt<28>[3] + T_1888[0] <= T_1883 + T_1888[1] <= T_1886 + T_1888[2] <= r_resp_ppn + node T_1895 = eq(r_req_dest, UInt<1>("h00")) + node T_1896 = and(resp_val, T_1895) + io.requestor[0].resp.valid <= T_1896 io.requestor[0].resp.bits.error <= resp_err io.requestor[0].resp.bits.pte <- r_pte - io.requestor[0].resp.bits.pte.ppn <= T_1912[count] + io.requestor[0].resp.bits.pte.ppn <= T_1888[count] io.requestor[0].invalidate <= io.dpath.invalidate io.requestor[0].status <- io.dpath.status - node T_1922 = eq(r_req_dest, UInt<1>("h01")) - node T_1923 = and(resp_val, T_1922) - io.requestor[1].resp.valid <= T_1923 + node T_1898 = eq(r_req_dest, UInt<1>("h01")) + node T_1899 = and(resp_val, T_1898) + io.requestor[1].resp.valid <= T_1899 io.requestor[1].resp.bits.error <= resp_err io.requestor[1].resp.bits.pte <- r_pte - io.requestor[1].resp.bits.pte.ppn <= T_1912[count] + io.requestor[1].resp.bits.pte.ppn <= T_1888[count] io.requestor[1].invalidate <= io.dpath.invalidate io.requestor[1].status <- io.dpath.status - node T_1924 = eq(UInt<1>("h00"), state) - when T_1924 : + node T_1900 = eq(UInt<1>("h00"), state) + when T_1900 : when arb.io.out.valid : state <= UInt<1>("h01") skip count <= UInt<1>("h00") skip - node T_1926 = eq(UInt<1>("h01"), state) - when T_1926 : - node T_1928 = lt(count, UInt<2>("h02")) - node T_1929 = and(pte_cache_hit, T_1928) - when T_1929 : + node T_1902 = eq(UInt<1>("h01"), state) + when T_1902 : + node T_1904 = lt(count, UInt<2>("h02")) + node T_1905 = and(pte_cache_hit, T_1904) + when T_1905 : io.mem.req.valid <= UInt<1>("h00") state <= UInt<1>("h01") - node T_1932 = addw(count, UInt<1>("h01")) - count <= T_1932 + node T_1908 = add(count, UInt<1>("h01")) + node T_1909 = tail(T_1908, 1) + count <= T_1909 r_pte.ppn <= pte_cache_data skip - node T_1934 = eq(T_1929, UInt<1>("h00")) - node T_1935 = and(T_1934, io.mem.req.ready) - when T_1935 : + node T_1911 = eq(T_1905, UInt<1>("h00")) + node T_1912 = and(T_1911, io.mem.req.ready) + when T_1912 : state <= UInt<2>("h02") skip skip - node T_1936 = eq(UInt<2>("h02"), state) - when T_1936 : + node T_1913 = eq(UInt<2>("h02"), state) + when T_1913 : when io.mem.resp.bits.nack : state <= UInt<1>("h01") skip when io.mem.resp.valid : state <= UInt<3>("h06") - node T_1938 = lt(pte.typ, UInt<2>("h02")) - node T_1939 = and(pte.v, T_1938) - node T_1941 = lt(count, UInt<2>("h02")) - node T_1942 = and(T_1939, T_1941) - when T_1942 : + node T_1915 = lt(pte.typ, UInt<2>("h02")) + node T_1916 = and(pte.v, T_1915) + node T_1918 = lt(count, UInt<2>("h02")) + node T_1919 = and(T_1916, T_1918) + when T_1919 : state <= UInt<1>("h01") - node T_1944 = addw(count, UInt<1>("h01")) - count <= T_1944 + node T_1921 = add(count, UInt<1>("h01")) + node T_1922 = tail(T_1921, 1) + count <= T_1922 skip - node T_1946 = geq(pte.typ, UInt<2>("h02")) - node T_1947 = and(pte.v, T_1946) - when T_1947 : - node T_1948 = mux(set_dirty_bit, UInt<2>("h03"), UInt<3>("h05")) - state <= T_1948 + node T_1924 = geq(pte.typ, UInt<2>("h02")) + node T_1925 = and(pte.v, T_1924) + when T_1925 : + node T_1926 = mux(set_dirty_bit, UInt<2>("h03"), UInt<3>("h05")) + state <= T_1926 skip skip skip - node T_1949 = eq(UInt<2>("h03"), state) - when T_1949 : + node T_1927 = eq(UInt<2>("h03"), state) + when T_1927 : when io.mem.req.ready : state <= UInt<3>("h04") skip skip - node T_1950 = eq(UInt<3>("h04"), state) - when T_1950 : + node T_1928 = eq(UInt<3>("h04"), state) + when T_1928 : when io.mem.resp.bits.nack : state <= UInt<2>("h03") skip @@ -33717,12 +25975,12 @@ circuit Top : state <= UInt<1>("h01") skip skip - node T_1951 = eq(UInt<3>("h05"), state) - when T_1951 : + node T_1929 = eq(UInt<3>("h05"), state) + when T_1929 : state <= UInt<1>("h00") skip - node T_1952 = eq(UInt<3>("h06"), state) - when T_1952 : + node T_1930 = eq(UInt<3>("h06"), state) + when T_1930 : state <= UInt<1>("h00") skip @@ -33731,56 +25989,10 @@ circuit Top : input reset : UInt<1> output io : {flip requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}[2], mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}} - io.mem.invalidate_lr <= UInt<1>("h00") - io.mem.req.bits.data <= UInt<1>("h00") - io.mem.req.bits.phys <= UInt<1>("h00") - io.mem.req.bits.kill <= UInt<1>("h00") - io.mem.req.bits.typ <= UInt<1>("h00") - io.mem.req.bits.cmd <= UInt<1>("h00") - io.mem.req.bits.tag <= UInt<1>("h00") - io.mem.req.bits.addr <= UInt<1>("h00") - io.mem.req.valid <= UInt<1>("h00") - io.requestor[0].ordered <= UInt<1>("h00") - io.requestor[0].xcpt.pf.st <= UInt<1>("h00") - io.requestor[0].xcpt.pf.ld <= UInt<1>("h00") - io.requestor[0].xcpt.ma.st <= UInt<1>("h00") - io.requestor[0].xcpt.ma.ld <= UInt<1>("h00") - io.requestor[0].replay_next.bits <= UInt<1>("h00") - io.requestor[0].replay_next.valid <= UInt<1>("h00") - io.requestor[0].resp.bits.store_data <= UInt<1>("h00") - io.requestor[0].resp.bits.data_word_bypass <= UInt<1>("h00") - io.requestor[0].resp.bits.has_data <= UInt<1>("h00") - io.requestor[0].resp.bits.replay <= UInt<1>("h00") - io.requestor[0].resp.bits.nack <= UInt<1>("h00") - io.requestor[0].resp.bits.data <= UInt<1>("h00") - io.requestor[0].resp.bits.typ <= UInt<1>("h00") - io.requestor[0].resp.bits.cmd <= UInt<1>("h00") - io.requestor[0].resp.bits.tag <= UInt<1>("h00") - io.requestor[0].resp.bits.addr <= UInt<1>("h00") - io.requestor[0].resp.valid <= UInt<1>("h00") - io.requestor[0].req.ready <= UInt<1>("h00") - io.requestor[1].ordered <= UInt<1>("h00") - io.requestor[1].xcpt.pf.st <= UInt<1>("h00") - io.requestor[1].xcpt.pf.ld <= UInt<1>("h00") - io.requestor[1].xcpt.ma.st <= UInt<1>("h00") - io.requestor[1].xcpt.ma.ld <= UInt<1>("h00") - io.requestor[1].replay_next.bits <= UInt<1>("h00") - io.requestor[1].replay_next.valid <= UInt<1>("h00") - io.requestor[1].resp.bits.store_data <= UInt<1>("h00") - io.requestor[1].resp.bits.data_word_bypass <= UInt<1>("h00") - io.requestor[1].resp.bits.has_data <= UInt<1>("h00") - io.requestor[1].resp.bits.replay <= UInt<1>("h00") - io.requestor[1].resp.bits.nack <= UInt<1>("h00") - io.requestor[1].resp.bits.data <= UInt<1>("h00") - io.requestor[1].resp.bits.typ <= UInt<1>("h00") - io.requestor[1].resp.bits.cmd <= UInt<1>("h00") - io.requestor[1].resp.bits.tag <= UInt<1>("h00") - io.requestor[1].resp.bits.addr <= UInt<1>("h00") - io.requestor[1].resp.valid <= UInt<1>("h00") - io.requestor[1].req.ready <= UInt<1>("h00") - reg T_5286 : UInt<1>, clk, UInt<1>("h00"), T_5286 + io is invalid + reg T_5286 : UInt<1>, clk T_5286 <= io.requestor[0].req.valid - reg T_5287 : UInt<1>, clk, UInt<1>("h00"), T_5287 + reg T_5287 : UInt<1>, clk T_5287 <= io.requestor[1].req.valid node T_5288 = or(io.requestor[0].req.valid, io.requestor[1].req.valid) io.mem.req.valid <= T_5288 @@ -33847,23 +26059,7 @@ circuit Top : input reset : UInt<1> output io : {flip inst : UInt<32>, sigs : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}} - io.sigs.wflags <= UInt<1>("h00") - io.sigs.round <= UInt<1>("h00") - io.sigs.sqrt <= UInt<1>("h00") - io.sigs.div <= UInt<1>("h00") - io.sigs.fma <= UInt<1>("h00") - io.sigs.fastpipe <= UInt<1>("h00") - io.sigs.toint <= UInt<1>("h00") - io.sigs.fromint <= UInt<1>("h00") - io.sigs.single <= UInt<1>("h00") - io.sigs.swap23 <= UInt<1>("h00") - io.sigs.swap12 <= UInt<1>("h00") - io.sigs.ren3 <= UInt<1>("h00") - io.sigs.ren2 <= UInt<1>("h00") - io.sigs.ren1 <= UInt<1>("h00") - io.sigs.wen <= UInt<1>("h00") - io.sigs.ldst <= UInt<1>("h00") - io.sigs.cmd <= UInt<1>("h00") + io is invalid node T_42 = and(io.inst, UInt<32>("h04")) node T_44 = eq(T_42, UInt<32>("h04")) node T_46 = and(io.inst, UInt<32>("h08000010")) @@ -33997,41 +26193,23 @@ circuit Top : input reset : UInt<1> output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, mulAddA : UInt<24>, mulAddB : UInt<24>, mulAddC : UInt<48>, toPostMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}} - io.toPostMul.roundingMode <= UInt<1>("h00") - io.toPostMul.sExpSum <= UInt<1>("h00") - io.toPostMul.highAlignedNegSigC <= UInt<1>("h00") - io.toPostMul.bit0AlignedNegSigC <= UInt<1>("h00") - io.toPostMul.CAlignDist <= UInt<1>("h00") - io.toPostMul.CAlignDist_0 <= UInt<1>("h00") - io.toPostMul.isCDominant <= UInt<1>("h00") - io.toPostMul.isNaN_isQuietNaNC <= UInt<1>("h00") - io.toPostMul.highExpC <= UInt<1>("h00") - io.toPostMul.opSignC <= UInt<1>("h00") - io.toPostMul.isZeroProd <= UInt<1>("h00") - io.toPostMul.signProd <= UInt<1>("h00") - io.toPostMul.isNaN_isQuietNaNB <= UInt<1>("h00") - io.toPostMul.highExpB <= UInt<1>("h00") - io.toPostMul.isNaN_isQuietNaNA <= UInt<1>("h00") - io.toPostMul.highExpA <= UInt<1>("h00") - io.mulAddC <= UInt<1>("h00") - io.mulAddB <= UInt<1>("h00") - io.mulAddA <= UInt<1>("h00") - node signA = bit(io.a, 32) + io is invalid + node signA = bits(io.a, 32, 32) node expA = bits(io.a, 31, 23) node fractA = bits(io.a, 22, 0) node T_50 = bits(expA, 8, 6) node isZeroA = eq(T_50, UInt<1>("h00")) node T_54 = eq(isZeroA, UInt<1>("h00")) node sigA = cat(T_54, fractA) - node signB = bit(io.b, 32) + node signB = bits(io.b, 32, 32) node expB = bits(io.b, 31, 23) node fractB = bits(io.b, 22, 0) node T_59 = bits(expB, 8, 6) node isZeroB = eq(T_59, UInt<1>("h00")) node T_63 = eq(isZeroB, UInt<1>("h00")) node sigB = cat(T_63, fractB) - node T_65 = bit(io.c, 32) - node T_66 = bit(io.op, 0) + node T_65 = bits(io.c, 32, 32) + node T_66 = bits(io.op, 0, 0) node opSignC = xor(T_65, T_66) node expC = bits(io.c, 31, 23) node fractC = bits(io.c, 22, 0) @@ -34040,146 +26218,151 @@ circuit Top : node T_74 = eq(isZeroC, UInt<1>("h00")) node sigC = cat(T_74, fractC) node T_76 = xor(signA, signB) - node T_77 = bit(io.op, 1) + node T_77 = bits(io.op, 1, 1) node signProd = xor(T_76, T_77) node isZeroProd = or(isZeroA, isZeroB) - node T_80 = bit(expB, 8) + node T_80 = bits(expB, 8, 8) node T_82 = eq(T_80, UInt<1>("h00")) - node T_84 = subw(UInt<3>("h00"), T_82) - node T_85 = bits(expB, 7, 0) - node T_86 = cat(T_84, T_85) - node T_87 = addw(expA, T_86) - node sExpAlignedProd = addw(T_87, UInt<5>("h01b")) + node T_84 = sub(UInt<3>("h00"), T_82) + node T_85 = tail(T_84, 1) + node T_86 = bits(expB, 7, 0) + node T_87 = cat(T_85, T_86) + node T_88 = add(expA, T_87) + node T_89 = tail(T_88, 1) + node T_91 = add(T_89, UInt<5>("h01b")) + node sExpAlignedProd = tail(T_91, 1) node doSubMags = xor(signProd, opSignC) - node sNatCAlignDist = subw(sExpAlignedProd, expC) - node T_92 = bit(sNatCAlignDist, 10) - node CAlignDist_floor = or(isZeroProd, T_92) - node T_94 = bits(sNatCAlignDist, 9, 0) - node T_96 = eq(T_94, UInt<1>("h00")) - node CAlignDist_0 = or(CAlignDist_floor, T_96) - node T_99 = eq(isZeroC, UInt<1>("h00")) - node T_100 = bits(sNatCAlignDist, 9, 0) - node T_102 = lt(T_100, UInt<5>("h019")) - node T_103 = or(CAlignDist_floor, T_102) - node isCDominant = and(T_99, T_103) - node T_106 = bits(sNatCAlignDist, 9, 0) - node T_108 = lt(T_106, UInt<7>("h04a")) - node T_109 = bits(sNatCAlignDist, 6, 0) - node T_111 = mux(T_108, T_109, UInt<7>("h04a")) - node CAlignDist = mux(CAlignDist_floor, UInt<1>("h00"), T_111) + node T_94 = sub(sExpAlignedProd, expC) + node sNatCAlignDist = tail(T_94, 1) + node T_96 = bits(sNatCAlignDist, 10, 10) + node CAlignDist_floor = or(isZeroProd, T_96) + node T_98 = bits(sNatCAlignDist, 9, 0) + node T_100 = eq(T_98, UInt<1>("h00")) + node CAlignDist_0 = or(CAlignDist_floor, T_100) + node T_103 = eq(isZeroC, UInt<1>("h00")) + node T_104 = bits(sNatCAlignDist, 9, 0) + node T_106 = lt(T_104, UInt<5>("h019")) + node T_107 = or(CAlignDist_floor, T_106) + node isCDominant = and(T_103, T_107) + node T_110 = bits(sNatCAlignDist, 9, 0) + node T_112 = lt(T_110, UInt<7>("h04a")) + node T_113 = bits(sNatCAlignDist, 6, 0) + node T_115 = mux(T_112, T_113, UInt<7>("h04a")) + node CAlignDist = mux(CAlignDist_floor, UInt<1>("h00"), T_115) node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) - node T_115 = dshr(asSInt(UInt<129>("h0100000000000000000000000000000000")), CAlignDist) - node T_116 = bits(T_115, 77, 54) - node T_117 = bits(T_116, 15, 0) - node T_120 = shl(UInt<8>("h0ff"), 8) - node T_121 = xor(UInt<16>("h0ffff"), T_120) - node T_122 = shr(T_117, 8) - node T_123 = and(T_122, T_121) - node T_124 = bits(T_117, 7, 0) - node T_125 = shl(T_124, 8) - node T_126 = not(T_121) - node T_127 = and(T_125, T_126) - node T_128 = or(T_123, T_127) - node T_129 = bits(T_121, 11, 0) - node T_130 = shl(T_129, 4) - node T_131 = xor(T_121, T_130) - node T_132 = shr(T_128, 4) - node T_133 = and(T_132, T_131) - node T_134 = bits(T_128, 11, 0) - node T_135 = shl(T_134, 4) - node T_136 = not(T_131) - node T_137 = and(T_135, T_136) - node T_138 = or(T_133, T_137) - node T_139 = bits(T_131, 13, 0) - node T_140 = shl(T_139, 2) - node T_141 = xor(T_131, T_140) - node T_142 = shr(T_138, 2) - node T_143 = and(T_142, T_141) - node T_144 = bits(T_138, 13, 0) - node T_145 = shl(T_144, 2) - node T_146 = not(T_141) - node T_147 = and(T_145, T_146) - node T_148 = or(T_143, T_147) - node T_149 = bits(T_141, 14, 0) - node T_150 = shl(T_149, 1) - node T_151 = xor(T_141, T_150) - node T_152 = shr(T_148, 1) - node T_153 = and(T_152, T_151) - node T_154 = bits(T_148, 14, 0) - node T_155 = shl(T_154, 1) - node T_156 = not(T_151) - node T_157 = and(T_155, T_156) - node T_158 = or(T_153, T_157) - node T_159 = bits(T_116, 23, 16) - node T_162 = shl(UInt<4>("h0f"), 4) - node T_163 = xor(UInt<8>("h0ff"), T_162) - node T_164 = shr(T_159, 4) - node T_165 = and(T_164, T_163) - node T_166 = bits(T_159, 3, 0) - node T_167 = shl(T_166, 4) - node T_168 = not(T_163) - node T_169 = and(T_167, T_168) - node T_170 = or(T_165, T_169) - node T_171 = bits(T_163, 5, 0) - node T_172 = shl(T_171, 2) - node T_173 = xor(T_163, T_172) - node T_174 = shr(T_170, 2) - node T_175 = and(T_174, T_173) - node T_176 = bits(T_170, 5, 0) - node T_177 = shl(T_176, 2) - node T_178 = not(T_173) - node T_179 = and(T_177, T_178) - node T_180 = or(T_175, T_179) - node T_181 = bits(T_173, 6, 0) - node T_182 = shl(T_181, 1) - node T_183 = xor(T_173, T_182) - node T_184 = shr(T_180, 1) - node T_185 = and(T_184, T_183) - node T_186 = bits(T_180, 6, 0) - node T_187 = shl(T_186, 1) - node T_188 = not(T_183) - node T_189 = and(T_187, T_188) - node T_190 = or(T_185, T_189) - node CExtraMask = cat(T_158, T_190) - node T_192 = not(sigC) - node negSigC = mux(doSubMags, T_192, sigC) - node T_195 = subw(UInt<50>("h00"), doSubMags) - node T_196 = cat(negSigC, T_195) - node T_197 = cat(doSubMags, T_196) - node T_198 = asSInt(T_197) - node T_199 = dshr(T_198, CAlignDist) - node T_200 = and(sigC, CExtraMask) - node T_202 = neq(T_200, UInt<1>("h00")) - node T_203 = xor(T_202, doSubMags) - node T_204 = asUInt(T_199) - node T_205 = cat(T_204, T_203) - node alignedNegSigC = bits(T_205, 74, 0) + node T_119 = dshr(asSInt(UInt<129>("h0100000000000000000000000000000000")), CAlignDist) + node T_120 = bits(T_119, 77, 54) + node T_121 = bits(T_120, 15, 0) + node T_124 = shl(UInt<8>("h0ff"), 8) + node T_125 = xor(UInt<16>("h0ffff"), T_124) + node T_126 = shr(T_121, 8) + node T_127 = and(T_126, T_125) + node T_128 = bits(T_121, 7, 0) + node T_129 = shl(T_128, 8) + node T_130 = not(T_125) + node T_131 = and(T_129, T_130) + node T_132 = or(T_127, T_131) + node T_133 = bits(T_125, 11, 0) + node T_134 = shl(T_133, 4) + node T_135 = xor(T_125, T_134) + node T_136 = shr(T_132, 4) + node T_137 = and(T_136, T_135) + node T_138 = bits(T_132, 11, 0) + node T_139 = shl(T_138, 4) + node T_140 = not(T_135) + node T_141 = and(T_139, T_140) + node T_142 = or(T_137, T_141) + node T_143 = bits(T_135, 13, 0) + node T_144 = shl(T_143, 2) + node T_145 = xor(T_135, T_144) + node T_146 = shr(T_142, 2) + node T_147 = and(T_146, T_145) + node T_148 = bits(T_142, 13, 0) + node T_149 = shl(T_148, 2) + node T_150 = not(T_145) + node T_151 = and(T_149, T_150) + node T_152 = or(T_147, T_151) + node T_153 = bits(T_145, 14, 0) + node T_154 = shl(T_153, 1) + node T_155 = xor(T_145, T_154) + node T_156 = shr(T_152, 1) + node T_157 = and(T_156, T_155) + node T_158 = bits(T_152, 14, 0) + node T_159 = shl(T_158, 1) + node T_160 = not(T_155) + node T_161 = and(T_159, T_160) + node T_162 = or(T_157, T_161) + node T_163 = bits(T_120, 23, 16) + node T_166 = shl(UInt<4>("h0f"), 4) + node T_167 = xor(UInt<8>("h0ff"), T_166) + node T_168 = shr(T_163, 4) + node T_169 = and(T_168, T_167) + node T_170 = bits(T_163, 3, 0) + node T_171 = shl(T_170, 4) + node T_172 = not(T_167) + node T_173 = and(T_171, T_172) + node T_174 = or(T_169, T_173) + node T_175 = bits(T_167, 5, 0) + node T_176 = shl(T_175, 2) + node T_177 = xor(T_167, T_176) + node T_178 = shr(T_174, 2) + node T_179 = and(T_178, T_177) + node T_180 = bits(T_174, 5, 0) + node T_181 = shl(T_180, 2) + node T_182 = not(T_177) + node T_183 = and(T_181, T_182) + node T_184 = or(T_179, T_183) + node T_185 = bits(T_177, 6, 0) + node T_186 = shl(T_185, 1) + node T_187 = xor(T_177, T_186) + node T_188 = shr(T_184, 1) + node T_189 = and(T_188, T_187) + node T_190 = bits(T_184, 6, 0) + node T_191 = shl(T_190, 1) + node T_192 = not(T_187) + node T_193 = and(T_191, T_192) + node T_194 = or(T_189, T_193) + node CExtraMask = cat(T_162, T_194) + node T_196 = not(sigC) + node negSigC = mux(doSubMags, T_196, sigC) + node T_199 = sub(UInt<50>("h00"), doSubMags) + node T_200 = tail(T_199, 1) + node T_201 = cat(negSigC, T_200) + node T_202 = cat(doSubMags, T_201) + node T_203 = asSInt(T_202) + node T_204 = dshr(T_203, CAlignDist) + node T_205 = and(sigC, CExtraMask) + node T_207 = neq(T_205, UInt<1>("h00")) + node T_208 = xor(T_207, doSubMags) + node T_209 = asUInt(T_204) + node T_210 = cat(T_209, T_208) + node alignedNegSigC = bits(T_210, 74, 0) io.mulAddA <= sigA io.mulAddB <= sigB - node T_207 = bits(alignedNegSigC, 48, 1) - io.mulAddC <= T_207 - node T_208 = bits(expA, 8, 6) - io.toPostMul.highExpA <= T_208 - node T_209 = bit(fractA, 22) - io.toPostMul.isNaN_isQuietNaNA <= T_209 - node T_210 = bits(expB, 8, 6) - io.toPostMul.highExpB <= T_210 - node T_211 = bit(fractB, 22) - io.toPostMul.isNaN_isQuietNaNB <= T_211 + node T_212 = bits(alignedNegSigC, 48, 1) + io.mulAddC <= T_212 + node T_213 = bits(expA, 8, 6) + io.toPostMul.highExpA <= T_213 + node T_214 = bits(fractA, 22, 22) + io.toPostMul.isNaN_isQuietNaNA <= T_214 + node T_215 = bits(expB, 8, 6) + io.toPostMul.highExpB <= T_215 + node T_216 = bits(fractB, 22, 22) + io.toPostMul.isNaN_isQuietNaNB <= T_216 io.toPostMul.signProd <= signProd io.toPostMul.isZeroProd <= isZeroProd io.toPostMul.opSignC <= opSignC - node T_212 = bits(expC, 8, 6) - io.toPostMul.highExpC <= T_212 - node T_213 = bit(fractC, 22) - io.toPostMul.isNaN_isQuietNaNC <= T_213 + node T_217 = bits(expC, 8, 6) + io.toPostMul.highExpC <= T_217 + node T_218 = bits(fractC, 22, 22) + io.toPostMul.isNaN_isQuietNaNC <= T_218 io.toPostMul.isCDominant <= isCDominant io.toPostMul.CAlignDist_0 <= CAlignDist_0 io.toPostMul.CAlignDist <= CAlignDist - node T_214 = bit(alignedNegSigC, 0) - io.toPostMul.bit0AlignedNegSigC <= T_214 - node T_215 = bits(alignedNegSigC, 74, 49) - io.toPostMul.highAlignedNegSigC <= T_215 + node T_219 = bits(alignedNegSigC, 0, 0) + io.toPostMul.bit0AlignedNegSigC <= T_219 + node T_220 = bits(alignedNegSigC, 74, 49) + io.toPostMul.highAlignedNegSigC <= T_220 io.toPostMul.sExpSum <= sExpSum io.toPostMul.roundingMode <= io.roundingMode @@ -34188,35 +26371,34 @@ circuit Top : input reset : UInt<1> output io : {flip fromPreMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<7>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<26>, sExpSum : UInt<11>, roundingMode : UInt<2>}, flip mulAddResult : UInt<49>, out : UInt<33>, exceptionFlags : UInt<5>} - io.exceptionFlags <= UInt<1>("h00") - io.out <= UInt<1>("h00") + io is invalid node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h00")) node T_44 = bits(io.fromPreMul.highExpA, 2, 1) node isSpecialA = eq(T_44, UInt<2>("h03")) - node T_47 = bit(io.fromPreMul.highExpA, 0) + node T_47 = bits(io.fromPreMul.highExpA, 0, 0) node T_49 = eq(T_47, UInt<1>("h00")) node isInfA = and(isSpecialA, T_49) - node T_51 = bit(io.fromPreMul.highExpA, 0) + node T_51 = bits(io.fromPreMul.highExpA, 0, 0) node isNaNA = and(isSpecialA, T_51) node T_54 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h00")) node isSigNaNA = and(isNaNA, T_54) node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h00")) node T_58 = bits(io.fromPreMul.highExpB, 2, 1) node isSpecialB = eq(T_58, UInt<2>("h03")) - node T_61 = bit(io.fromPreMul.highExpB, 0) + node T_61 = bits(io.fromPreMul.highExpB, 0, 0) node T_63 = eq(T_61, UInt<1>("h00")) node isInfB = and(isSpecialB, T_63) - node T_65 = bit(io.fromPreMul.highExpB, 0) + node T_65 = bits(io.fromPreMul.highExpB, 0, 0) node isNaNB = and(isSpecialB, T_65) node T_68 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h00")) node isSigNaNB = and(isNaNB, T_68) node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h00")) node T_72 = bits(io.fromPreMul.highExpC, 2, 1) node isSpecialC = eq(T_72, UInt<2>("h03")) - node T_75 = bit(io.fromPreMul.highExpC, 0) + node T_75 = bits(io.fromPreMul.highExpC, 0, 0) node T_77 = eq(T_75, UInt<1>("h00")) node isInfC = and(isSpecialC, T_77) - node T_79 = bit(io.fromPreMul.highExpC, 0) + node T_79 = bits(io.fromPreMul.highExpC, 0, 0) node isNaNC = and(isSpecialC, T_79) node T_82 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h00")) node isSigNaNC = and(isNaNC, T_82) @@ -34226,595 +26408,592 @@ circuit Top : node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h03")) node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h01"), UInt<1>("h00")) node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC) - node T_96 = bit(io.mulAddResult, 48) - node T_98 = addw(io.fromPreMul.highAlignedNegSigC, UInt<1>("h01")) - node T_99 = mux(T_96, T_98, io.fromPreMul.highAlignedNegSigC) - node T_100 = bits(io.mulAddResult, 47, 0) - node T_101 = cat(T_100, io.fromPreMul.bit0AlignedNegSigC) - node sigSum = cat(T_99, T_101) - node T_104 = bits(sigSum, 50, 1) - node T_105 = xor(UInt<50>("h00"), T_104) - node T_106 = or(UInt<50>("h00"), T_104) - node T_107 = shl(T_106, 1) - node T_108 = xor(T_105, T_107) - node T_110 = bits(T_108, 49, 0) - node T_111 = bit(T_110, 49) - node T_113 = bit(T_110, 48) - node T_115 = bit(T_110, 47) - node T_117 = bit(T_110, 46) - node T_119 = bit(T_110, 45) - node T_121 = bit(T_110, 44) - node T_123 = bit(T_110, 43) - node T_125 = bit(T_110, 42) - node T_127 = bit(T_110, 41) - node T_129 = bit(T_110, 40) - node T_131 = bit(T_110, 39) - node T_133 = bit(T_110, 38) - node T_135 = bit(T_110, 37) - node T_137 = bit(T_110, 36) - node T_139 = bit(T_110, 35) - node T_141 = bit(T_110, 34) - node T_143 = bit(T_110, 33) - node T_145 = bit(T_110, 32) - node T_147 = bit(T_110, 31) - node T_149 = bit(T_110, 30) - node T_151 = bit(T_110, 29) - node T_153 = bit(T_110, 28) - node T_155 = bit(T_110, 27) - node T_157 = bit(T_110, 26) - node T_159 = bit(T_110, 25) - node T_161 = bit(T_110, 24) - node T_163 = bit(T_110, 23) - node T_165 = bit(T_110, 22) - node T_167 = bit(T_110, 21) - node T_169 = bit(T_110, 20) - node T_171 = bit(T_110, 19) - node T_173 = bit(T_110, 18) - node T_175 = bit(T_110, 17) - node T_177 = bit(T_110, 16) - node T_179 = bit(T_110, 15) - node T_181 = bit(T_110, 14) - node T_183 = bit(T_110, 13) - node T_185 = bit(T_110, 12) - node T_187 = bit(T_110, 11) - node T_189 = bit(T_110, 10) - node T_191 = bit(T_110, 9) - node T_193 = bit(T_110, 8) - node T_195 = bit(T_110, 7) - node T_197 = bit(T_110, 6) - node T_199 = bit(T_110, 5) - node T_201 = bit(T_110, 4) - node T_203 = bit(T_110, 3) - node T_205 = bit(T_110, 2) - node T_207 = bit(T_110, 1) - node T_208 = shl(T_207, 0) - node T_209 = mux(T_205, UInt<2>("h02"), T_208) - node T_210 = mux(T_203, UInt<2>("h03"), T_209) - node T_211 = mux(T_201, UInt<3>("h04"), T_210) - node T_212 = mux(T_199, UInt<3>("h05"), T_211) - node T_213 = mux(T_197, UInt<3>("h06"), T_212) - node T_214 = mux(T_195, UInt<3>("h07"), T_213) - node T_215 = mux(T_193, UInt<4>("h08"), T_214) - node T_216 = mux(T_191, UInt<4>("h09"), T_215) - node T_217 = mux(T_189, UInt<4>("h0a"), T_216) - node T_218 = mux(T_187, UInt<4>("h0b"), T_217) - node T_219 = mux(T_185, UInt<4>("h0c"), T_218) - node T_220 = mux(T_183, UInt<4>("h0d"), T_219) - node T_221 = mux(T_181, UInt<4>("h0e"), T_220) - node T_222 = mux(T_179, UInt<4>("h0f"), T_221) - node T_223 = mux(T_177, UInt<5>("h010"), T_222) - node T_224 = mux(T_175, UInt<5>("h011"), T_223) - node T_225 = mux(T_173, UInt<5>("h012"), T_224) - node T_226 = mux(T_171, UInt<5>("h013"), T_225) - node T_227 = mux(T_169, UInt<5>("h014"), T_226) - node T_228 = mux(T_167, UInt<5>("h015"), T_227) - node T_229 = mux(T_165, UInt<5>("h016"), T_228) - node T_230 = mux(T_163, UInt<5>("h017"), T_229) - node T_231 = mux(T_161, UInt<5>("h018"), T_230) - node T_232 = mux(T_159, UInt<5>("h019"), T_231) - node T_233 = mux(T_157, UInt<5>("h01a"), T_232) - node T_234 = mux(T_155, UInt<5>("h01b"), T_233) - node T_235 = mux(T_153, UInt<5>("h01c"), T_234) - node T_236 = mux(T_151, UInt<5>("h01d"), T_235) - node T_237 = mux(T_149, UInt<5>("h01e"), T_236) - node T_238 = mux(T_147, UInt<5>("h01f"), T_237) - node T_239 = mux(T_145, UInt<6>("h020"), T_238) - node T_240 = mux(T_143, UInt<6>("h021"), T_239) - node T_241 = mux(T_141, UInt<6>("h022"), T_240) - node T_242 = mux(T_139, UInt<6>("h023"), T_241) - node T_243 = mux(T_137, UInt<6>("h024"), T_242) - node T_244 = mux(T_135, UInt<6>("h025"), T_243) - node T_245 = mux(T_133, UInt<6>("h026"), T_244) - node T_246 = mux(T_131, UInt<6>("h027"), T_245) - node T_247 = mux(T_129, UInt<6>("h028"), T_246) - node T_248 = mux(T_127, UInt<6>("h029"), T_247) - node T_249 = mux(T_125, UInt<6>("h02a"), T_248) - node T_250 = mux(T_123, UInt<6>("h02b"), T_249) - node T_251 = mux(T_121, UInt<6>("h02c"), T_250) - node T_252 = mux(T_119, UInt<6>("h02d"), T_251) - node T_253 = mux(T_117, UInt<6>("h02e"), T_252) - node T_254 = mux(T_115, UInt<6>("h02f"), T_253) - node T_255 = mux(T_113, UInt<6>("h030"), T_254) - node T_256 = mux(T_111, UInt<6>("h031"), T_255) - node estNormPos_dist = subw(UInt<7>("h049"), T_256) - node T_258 = bits(sigSum, 33, 18) - node T_260 = neq(T_258, UInt<1>("h00")) - node T_261 = bits(sigSum, 17, 0) - node T_263 = neq(T_261, UInt<1>("h00")) - node firstReduceSigSum = cat(T_260, T_263) + node T_96 = bits(io.mulAddResult, 48, 48) + node T_98 = add(io.fromPreMul.highAlignedNegSigC, UInt<1>("h01")) + node T_99 = tail(T_98, 1) + node T_100 = mux(T_96, T_99, io.fromPreMul.highAlignedNegSigC) + node T_101 = bits(io.mulAddResult, 47, 0) + node T_102 = cat(T_101, io.fromPreMul.bit0AlignedNegSigC) + node sigSum = cat(T_100, T_102) + node T_105 = bits(sigSum, 50, 1) + node T_106 = xor(UInt<50>("h00"), T_105) + node T_107 = or(UInt<50>("h00"), T_105) + node T_108 = shl(T_107, 1) + node T_109 = xor(T_106, T_108) + node T_111 = bits(T_109, 49, 0) + node T_112 = bits(T_111, 49, 49) + node T_114 = bits(T_111, 48, 48) + node T_116 = bits(T_111, 47, 47) + node T_118 = bits(T_111, 46, 46) + node T_120 = bits(T_111, 45, 45) + node T_122 = bits(T_111, 44, 44) + node T_124 = bits(T_111, 43, 43) + node T_126 = bits(T_111, 42, 42) + node T_128 = bits(T_111, 41, 41) + node T_130 = bits(T_111, 40, 40) + node T_132 = bits(T_111, 39, 39) + node T_134 = bits(T_111, 38, 38) + node T_136 = bits(T_111, 37, 37) + node T_138 = bits(T_111, 36, 36) + node T_140 = bits(T_111, 35, 35) + node T_142 = bits(T_111, 34, 34) + node T_144 = bits(T_111, 33, 33) + node T_146 = bits(T_111, 32, 32) + node T_148 = bits(T_111, 31, 31) + node T_150 = bits(T_111, 30, 30) + node T_152 = bits(T_111, 29, 29) + node T_154 = bits(T_111, 28, 28) + node T_156 = bits(T_111, 27, 27) + node T_158 = bits(T_111, 26, 26) + node T_160 = bits(T_111, 25, 25) + node T_162 = bits(T_111, 24, 24) + node T_164 = bits(T_111, 23, 23) + node T_166 = bits(T_111, 22, 22) + node T_168 = bits(T_111, 21, 21) + node T_170 = bits(T_111, 20, 20) + node T_172 = bits(T_111, 19, 19) + node T_174 = bits(T_111, 18, 18) + node T_176 = bits(T_111, 17, 17) + node T_178 = bits(T_111, 16, 16) + node T_180 = bits(T_111, 15, 15) + node T_182 = bits(T_111, 14, 14) + node T_184 = bits(T_111, 13, 13) + node T_186 = bits(T_111, 12, 12) + node T_188 = bits(T_111, 11, 11) + node T_190 = bits(T_111, 10, 10) + node T_192 = bits(T_111, 9, 9) + node T_194 = bits(T_111, 8, 8) + node T_196 = bits(T_111, 7, 7) + node T_198 = bits(T_111, 6, 6) + node T_200 = bits(T_111, 5, 5) + node T_202 = bits(T_111, 4, 4) + node T_204 = bits(T_111, 3, 3) + node T_206 = bits(T_111, 2, 2) + node T_208 = bits(T_111, 1, 1) + node T_209 = shl(T_208, 0) + node T_210 = mux(T_206, UInt<2>("h02"), T_209) + node T_211 = mux(T_204, UInt<2>("h03"), T_210) + node T_212 = mux(T_202, UInt<3>("h04"), T_211) + node T_213 = mux(T_200, UInt<3>("h05"), T_212) + node T_214 = mux(T_198, UInt<3>("h06"), T_213) + node T_215 = mux(T_196, UInt<3>("h07"), T_214) + node T_216 = mux(T_194, UInt<4>("h08"), T_215) + node T_217 = mux(T_192, UInt<4>("h09"), T_216) + node T_218 = mux(T_190, UInt<4>("h0a"), T_217) + node T_219 = mux(T_188, UInt<4>("h0b"), T_218) + node T_220 = mux(T_186, UInt<4>("h0c"), T_219) + node T_221 = mux(T_184, UInt<4>("h0d"), T_220) + node T_222 = mux(T_182, UInt<4>("h0e"), T_221) + node T_223 = mux(T_180, UInt<4>("h0f"), T_222) + node T_224 = mux(T_178, UInt<5>("h010"), T_223) + node T_225 = mux(T_176, UInt<5>("h011"), T_224) + node T_226 = mux(T_174, UInt<5>("h012"), T_225) + node T_227 = mux(T_172, UInt<5>("h013"), T_226) + node T_228 = mux(T_170, UInt<5>("h014"), T_227) + node T_229 = mux(T_168, UInt<5>("h015"), T_228) + node T_230 = mux(T_166, UInt<5>("h016"), T_229) + node T_231 = mux(T_164, UInt<5>("h017"), T_230) + node T_232 = mux(T_162, UInt<5>("h018"), T_231) + node T_233 = mux(T_160, UInt<5>("h019"), T_232) + node T_234 = mux(T_158, UInt<5>("h01a"), T_233) + node T_235 = mux(T_156, UInt<5>("h01b"), T_234) + node T_236 = mux(T_154, UInt<5>("h01c"), T_235) + node T_237 = mux(T_152, UInt<5>("h01d"), T_236) + node T_238 = mux(T_150, UInt<5>("h01e"), T_237) + node T_239 = mux(T_148, UInt<5>("h01f"), T_238) + node T_240 = mux(T_146, UInt<6>("h020"), T_239) + node T_241 = mux(T_144, UInt<6>("h021"), T_240) + node T_242 = mux(T_142, UInt<6>("h022"), T_241) + node T_243 = mux(T_140, UInt<6>("h023"), T_242) + node T_244 = mux(T_138, UInt<6>("h024"), T_243) + node T_245 = mux(T_136, UInt<6>("h025"), T_244) + node T_246 = mux(T_134, UInt<6>("h026"), T_245) + node T_247 = mux(T_132, UInt<6>("h027"), T_246) + node T_248 = mux(T_130, UInt<6>("h028"), T_247) + node T_249 = mux(T_128, UInt<6>("h029"), T_248) + node T_250 = mux(T_126, UInt<6>("h02a"), T_249) + node T_251 = mux(T_124, UInt<6>("h02b"), T_250) + node T_252 = mux(T_122, UInt<6>("h02c"), T_251) + node T_253 = mux(T_120, UInt<6>("h02d"), T_252) + node T_254 = mux(T_118, UInt<6>("h02e"), T_253) + node T_255 = mux(T_116, UInt<6>("h02f"), T_254) + node T_256 = mux(T_114, UInt<6>("h030"), T_255) + node T_257 = mux(T_112, UInt<6>("h031"), T_256) + node T_258 = sub(UInt<7>("h049"), T_257) + node estNormPos_dist = tail(T_258, 1) + node T_260 = bits(sigSum, 33, 18) + node T_262 = neq(T_260, UInt<1>("h00")) + node T_263 = bits(sigSum, 17, 0) + node T_265 = neq(T_263, UInt<1>("h00")) + node firstReduceSigSum = cat(T_262, T_265) node notSigSum = not(sigSum) - node T_266 = bits(notSigSum, 33, 18) - node T_268 = neq(T_266, UInt<1>("h00")) - node T_269 = bits(notSigSum, 17, 0) - node T_271 = neq(T_269, UInt<1>("h00")) - node firstReduceNotSigSum = cat(T_268, T_271) - node T_273 = or(io.fromPreMul.CAlignDist_0, doSubMags) - node T_275 = subw(io.fromPreMul.CAlignDist, UInt<1>("h01")) - node T_276 = bits(T_275, 4, 0) - node CDom_estNormDist = mux(T_273, io.fromPreMul.CAlignDist, T_276) - node T_278 = not(doSubMags) - node T_279 = bit(CDom_estNormDist, 4) - node T_280 = not(T_279) - node T_281 = and(T_278, T_280) - node T_282 = asSInt(T_281) - node T_283 = bits(sigSum, 74, 34) - node T_285 = neq(firstReduceSigSum, UInt<1>("h00")) - node T_286 = cat(T_283, T_285) - node T_287 = asSInt(T_286) - node T_288 = and(T_282, T_287) - node T_289 = not(doSubMags) - node T_290 = bit(CDom_estNormDist, 4) - node T_291 = and(T_289, T_290) + node T_268 = bits(notSigSum, 33, 18) + node T_270 = neq(T_268, UInt<1>("h00")) + node T_271 = bits(notSigSum, 17, 0) + node T_273 = neq(T_271, UInt<1>("h00")) + node firstReduceNotSigSum = cat(T_270, T_273) + node T_275 = or(io.fromPreMul.CAlignDist_0, doSubMags) + node T_277 = sub(io.fromPreMul.CAlignDist, UInt<1>("h01")) + node T_278 = tail(T_277, 1) + node T_279 = bits(T_278, 4, 0) + node CDom_estNormDist = mux(T_275, io.fromPreMul.CAlignDist, T_279) + node T_281 = not(doSubMags) + node T_282 = bits(CDom_estNormDist, 4, 4) + node T_283 = not(T_282) + node T_284 = and(T_281, T_283) + node T_285 = asSInt(T_284) + node T_286 = bits(sigSum, 74, 34) + node T_288 = neq(firstReduceSigSum, UInt<1>("h00")) + node T_289 = cat(T_286, T_288) + node T_290 = asSInt(T_289) + node T_291 = and(T_285, T_290) node T_292 = asSInt(T_291) - node T_293 = bits(sigSum, 58, 18) - node T_294 = bit(firstReduceSigSum, 0) - node T_295 = cat(T_293, T_294) + node T_293 = not(doSubMags) + node T_294 = bits(CDom_estNormDist, 4, 4) + node T_295 = and(T_293, T_294) node T_296 = asSInt(T_295) - node T_297 = and(T_292, T_296) - node T_298 = or(T_288, T_297) - node T_299 = bit(CDom_estNormDist, 4) - node T_300 = not(T_299) - node T_301 = and(doSubMags, T_300) + node T_297 = bits(sigSum, 58, 18) + node T_298 = bits(firstReduceSigSum, 0, 0) + node T_299 = cat(T_297, T_298) + node T_300 = asSInt(T_299) + node T_301 = and(T_296, T_300) node T_302 = asSInt(T_301) - node T_303 = bits(notSigSum, 74, 34) - node T_305 = neq(firstReduceNotSigSum, UInt<1>("h00")) - node T_306 = cat(T_303, T_305) - node T_307 = asSInt(T_306) - node T_308 = and(T_302, T_307) - node T_309 = or(T_298, T_308) - node T_310 = bit(CDom_estNormDist, 4) - node T_311 = and(doSubMags, T_310) - node T_312 = asSInt(T_311) - node T_313 = bits(notSigSum, 58, 18) - node T_314 = bit(firstReduceNotSigSum, 0) - node T_315 = cat(T_313, T_314) - node T_316 = asSInt(T_315) - node T_317 = and(T_312, T_316) - node T_318 = or(T_309, T_317) - node CDom_firstNormAbsSigSum = asUInt(T_318) - node T_320 = bits(sigSum, 50, 18) - node T_321 = bit(firstReduceNotSigSum, 0) - node T_322 = not(T_321) - node T_323 = bit(firstReduceSigSum, 0) - node T_324 = mux(doSubMags, T_322, T_323) - node T_325 = cat(T_320, T_324) - node T_326 = bits(sigSum, 42, 1) - node T_327 = bit(estNormPos_dist, 5) - node T_328 = bit(estNormPos_dist, 4) - node T_329 = bits(sigSum, 26, 1) - node T_331 = subw(UInt<16>("h00"), doSubMags) - node T_332 = cat(T_329, T_331) - node T_333 = mux(T_328, T_332, T_326) - node T_334 = bit(estNormPos_dist, 4) - node T_335 = bits(sigSum, 10, 1) - node T_337 = subw(UInt<32>("h00"), doSubMags) - node T_338 = cat(T_335, T_337) - node T_339 = mux(T_334, T_325, T_338) - node notCDom_pos_firstNormAbsSigSum = mux(T_327, T_333, T_339) - node T_341 = bits(notSigSum, 49, 18) - node T_342 = bit(firstReduceNotSigSum, 0) - node T_343 = cat(T_341, T_342) - node T_344 = bits(notSigSum, 42, 1) - node T_345 = bit(estNormPos_dist, 5) - node T_346 = bit(estNormPos_dist, 4) - node T_347 = bits(notSigSum, 27, 1) - node T_349 = dshl(T_347, UInt<5>("h010")) - node T_350 = mux(T_346, T_349, T_344) - node T_351 = bit(estNormPos_dist, 4) - node T_352 = bits(notSigSum, 11, 1) - node T_354 = dshl(T_352, UInt<6>("h020")) - node T_355 = mux(T_351, T_343, T_354) - node notCDom_neg_cFirstNormAbsSigSum = mux(T_345, T_350, T_355) - node notCDom_signSigSum = bit(sigSum, 51) - node T_358 = not(isZeroC) - node T_359 = and(doSubMags, T_358) - node doNegSignSum = mux(io.fromPreMul.isCDominant, T_359, notCDom_signSigSum) - node T_361 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) - node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, T_361) - node T_363 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) - node T_364 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) - node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_363, T_364) - node T_366 = not(io.fromPreMul.isCDominant) - node T_367 = not(notCDom_signSigSum) - node T_368 = and(T_366, T_367) - node doIncrSig = and(T_368, doSubMags) + node T_303 = or(T_292, T_302) + node T_304 = asSInt(T_303) + node T_305 = bits(CDom_estNormDist, 4, 4) + node T_306 = not(T_305) + node T_307 = and(doSubMags, T_306) + node T_308 = asSInt(T_307) + node T_309 = bits(notSigSum, 74, 34) + node T_311 = neq(firstReduceNotSigSum, UInt<1>("h00")) + node T_312 = cat(T_309, T_311) + node T_313 = asSInt(T_312) + node T_314 = and(T_308, T_313) + node T_315 = asSInt(T_314) + node T_316 = or(T_304, T_315) + node T_317 = asSInt(T_316) + node T_318 = bits(CDom_estNormDist, 4, 4) + node T_319 = and(doSubMags, T_318) + node T_320 = asSInt(T_319) + node T_321 = bits(notSigSum, 58, 18) + node T_322 = bits(firstReduceNotSigSum, 0, 0) + node T_323 = cat(T_321, T_322) + node T_324 = asSInt(T_323) + node T_325 = and(T_320, T_324) + node T_326 = asSInt(T_325) + node T_327 = or(T_317, T_326) + node T_328 = asSInt(T_327) + node CDom_firstNormAbsSigSum = asUInt(T_328) + node T_330 = bits(sigSum, 50, 18) + node T_331 = bits(firstReduceNotSigSum, 0, 0) + node T_332 = not(T_331) + node T_333 = bits(firstReduceSigSum, 0, 0) + node T_334 = mux(doSubMags, T_332, T_333) + node T_335 = cat(T_330, T_334) + node T_336 = bits(sigSum, 42, 1) + node T_337 = bits(estNormPos_dist, 5, 5) + node T_338 = bits(estNormPos_dist, 4, 4) + node T_339 = bits(sigSum, 26, 1) + node T_341 = sub(UInt<16>("h00"), doSubMags) + node T_342 = tail(T_341, 1) + node T_343 = cat(T_339, T_342) + node T_344 = mux(T_338, T_343, T_336) + node T_345 = bits(estNormPos_dist, 4, 4) + node T_346 = bits(sigSum, 10, 1) + node T_348 = sub(UInt<32>("h00"), doSubMags) + node T_349 = tail(T_348, 1) + node T_350 = cat(T_346, T_349) + node T_351 = mux(T_345, T_335, T_350) + node notCDom_pos_firstNormAbsSigSum = mux(T_337, T_344, T_351) + node T_353 = bits(notSigSum, 49, 18) + node T_354 = bits(firstReduceNotSigSum, 0, 0) + node T_355 = cat(T_353, T_354) + node T_356 = bits(notSigSum, 42, 1) + node T_357 = bits(estNormPos_dist, 5, 5) + node T_358 = bits(estNormPos_dist, 4, 4) + node T_359 = bits(notSigSum, 27, 1) + node T_361 = dshl(T_359, UInt<5>("h010")) + node T_362 = mux(T_358, T_361, T_356) + node T_363 = bits(estNormPos_dist, 4, 4) + node T_364 = bits(notSigSum, 11, 1) + node T_366 = dshl(T_364, UInt<6>("h020")) + node T_367 = mux(T_363, T_355, T_366) + node notCDom_neg_cFirstNormAbsSigSum = mux(T_357, T_362, T_367) + node notCDom_signSigSum = bits(sigSum, 51, 51) + node T_370 = not(isZeroC) + node T_371 = and(doSubMags, T_370) + node doNegSignSum = mux(io.fromPreMul.isCDominant, T_371, notCDom_signSigSum) + node T_373 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) + node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, T_373) + node T_375 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) + node T_376 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) + node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_375, T_376) + node T_378 = not(io.fromPreMul.isCDominant) + node T_379 = not(notCDom_signSigSum) + node T_380 = and(T_378, T_379) + node doIncrSig = and(T_380, doSubMags) node estNormDist_5 = bits(estNormDist, 3, 0) node normTo2ShiftDist = not(estNormDist_5) - node T_373 = dshr(asSInt(UInt<17>("h010000")), normTo2ShiftDist) - node T_374 = bits(T_373, 15, 1) - node T_375 = bits(T_374, 7, 0) - node T_378 = shl(UInt<4>("h0f"), 4) - node T_379 = xor(UInt<8>("h0ff"), T_378) - node T_380 = shr(T_375, 4) - node T_381 = and(T_380, T_379) - node T_382 = bits(T_375, 3, 0) - node T_383 = shl(T_382, 4) - node T_384 = not(T_379) - node T_385 = and(T_383, T_384) - node T_386 = or(T_381, T_385) - node T_387 = bits(T_379, 5, 0) - node T_388 = shl(T_387, 2) - node T_389 = xor(T_379, T_388) - node T_390 = shr(T_386, 2) - node T_391 = and(T_390, T_389) - node T_392 = bits(T_386, 5, 0) - node T_393 = shl(T_392, 2) - node T_394 = not(T_389) - node T_395 = and(T_393, T_394) - node T_396 = or(T_391, T_395) - node T_397 = bits(T_389, 6, 0) - node T_398 = shl(T_397, 1) - node T_399 = xor(T_389, T_398) - node T_400 = shr(T_396, 1) - node T_401 = and(T_400, T_399) - node T_402 = bits(T_396, 6, 0) - node T_403 = shl(T_402, 1) - node T_404 = not(T_399) - node T_405 = and(T_403, T_404) - node T_406 = or(T_401, T_405) - node T_407 = bits(T_374, 14, 8) - node T_408 = bits(T_407, 3, 0) - node T_409 = bits(T_408, 1, 0) - node T_410 = bits(T_409, 0, 0) - node T_411 = bits(T_409, 1, 1) - node T_412 = cat(T_410, T_411) - node T_413 = bits(T_408, 3, 2) - node T_414 = bits(T_413, 0, 0) - node T_415 = bits(T_413, 1, 1) - node T_416 = cat(T_414, T_415) - node T_417 = cat(T_412, T_416) - node T_418 = bits(T_407, 6, 4) - node T_419 = bits(T_418, 1, 0) - node T_420 = bits(T_419, 0, 0) - node T_421 = bits(T_419, 1, 1) - node T_422 = cat(T_420, T_421) - node T_423 = bits(T_418, 2, 2) + node T_385 = dshr(asSInt(UInt<17>("h010000")), normTo2ShiftDist) + node T_386 = bits(T_385, 15, 1) + node T_387 = bits(T_386, 7, 0) + node T_390 = shl(UInt<4>("h0f"), 4) + node T_391 = xor(UInt<8>("h0ff"), T_390) + node T_392 = shr(T_387, 4) + node T_393 = and(T_392, T_391) + node T_394 = bits(T_387, 3, 0) + node T_395 = shl(T_394, 4) + node T_396 = not(T_391) + node T_397 = and(T_395, T_396) + node T_398 = or(T_393, T_397) + node T_399 = bits(T_391, 5, 0) + node T_400 = shl(T_399, 2) + node T_401 = xor(T_391, T_400) + node T_402 = shr(T_398, 2) + node T_403 = and(T_402, T_401) + node T_404 = bits(T_398, 5, 0) + node T_405 = shl(T_404, 2) + node T_406 = not(T_401) + node T_407 = and(T_405, T_406) + node T_408 = or(T_403, T_407) + node T_409 = bits(T_401, 6, 0) + node T_410 = shl(T_409, 1) + node T_411 = xor(T_401, T_410) + node T_412 = shr(T_408, 1) + node T_413 = and(T_412, T_411) + node T_414 = bits(T_408, 6, 0) + node T_415 = shl(T_414, 1) + node T_416 = not(T_411) + node T_417 = and(T_415, T_416) + node T_418 = or(T_413, T_417) + node T_419 = bits(T_386, 14, 8) + node T_420 = bits(T_419, 3, 0) + node T_421 = bits(T_420, 1, 0) + node T_422 = bits(T_421, 0, 0) + node T_423 = bits(T_421, 1, 1) node T_424 = cat(T_422, T_423) - node T_425 = cat(T_417, T_424) - node T_426 = cat(T_406, T_425) - node absSigSumExtraMask = cat(T_426, UInt<1>("h01")) - node T_429 = bits(cFirstNormAbsSigSum, 42, 1) - node T_430 = dshr(T_429, normTo2ShiftDist) - node T_431 = bits(cFirstNormAbsSigSum, 15, 0) - node T_432 = not(T_431) - node T_433 = and(T_432, absSigSumExtraMask) - node T_435 = eq(T_433, UInt<1>("h00")) - node T_436 = bits(cFirstNormAbsSigSum, 15, 0) - node T_437 = and(T_436, absSigSumExtraMask) - node T_439 = neq(T_437, UInt<1>("h00")) - node T_440 = mux(doIncrSig, T_435, T_439) - node T_441 = cat(T_430, T_440) - node sigX3 = bits(T_441, 27, 0) - node T_443 = bits(sigX3, 27, 26) - node sigX3Shift1 = eq(T_443, UInt<1>("h00")) - node sExpX3 = subw(io.fromPreMul.sExpSum, estNormDist) - node T_447 = bits(sigX3, 27, 25) - node isZeroY = eq(T_447, UInt<1>("h00")) - node T_450 = xor(io.fromPreMul.signProd, doNegSignSum) - node signY = mux(isZeroY, signZeroNotEqOpSigns, T_450) + node T_425 = bits(T_420, 3, 2) + node T_426 = bits(T_425, 0, 0) + node T_427 = bits(T_425, 1, 1) + node T_428 = cat(T_426, T_427) + node T_429 = cat(T_424, T_428) + node T_430 = bits(T_419, 6, 4) + node T_431 = bits(T_430, 1, 0) + node T_432 = bits(T_431, 0, 0) + node T_433 = bits(T_431, 1, 1) + node T_434 = cat(T_432, T_433) + node T_435 = bits(T_430, 2, 2) + node T_436 = cat(T_434, T_435) + node T_437 = cat(T_429, T_436) + node T_438 = cat(T_418, T_437) + node absSigSumExtraMask = cat(T_438, UInt<1>("h01")) + node T_441 = bits(cFirstNormAbsSigSum, 42, 1) + node T_442 = dshr(T_441, normTo2ShiftDist) + node T_443 = bits(cFirstNormAbsSigSum, 15, 0) + node T_444 = not(T_443) + node T_445 = and(T_444, absSigSumExtraMask) + node T_447 = eq(T_445, UInt<1>("h00")) + node T_448 = bits(cFirstNormAbsSigSum, 15, 0) + node T_449 = and(T_448, absSigSumExtraMask) + node T_451 = neq(T_449, UInt<1>("h00")) + node T_452 = mux(doIncrSig, T_447, T_451) + node T_453 = cat(T_442, T_452) + node sigX3 = bits(T_453, 27, 0) + node T_455 = bits(sigX3, 27, 26) + node sigX3Shift1 = eq(T_455, UInt<1>("h00")) + node T_458 = sub(io.fromPreMul.sExpSum, estNormDist) + node sExpX3 = tail(T_458, 1) + node T_460 = bits(sigX3, 27, 25) + node isZeroY = eq(T_460, UInt<1>("h00")) + node T_463 = xor(io.fromPreMul.signProd, doNegSignSum) + node signY = mux(isZeroY, signZeroNotEqOpSigns, T_463) node sExpX3_13 = bits(sExpX3, 9, 0) - node T_453 = bit(sExpX3, 10) - node T_455 = subw(UInt<27>("h00"), T_453) - node T_456 = not(sExpX3_13) - node T_458 = dshr(asSInt(UInt<1025>("h010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_456) - node T_459 = bits(T_458, 131, 107) - node T_460 = bits(T_459, 15, 0) - node T_463 = shl(UInt<8>("h0ff"), 8) - node T_464 = xor(UInt<16>("h0ffff"), T_463) - node T_465 = shr(T_460, 8) - node T_466 = and(T_465, T_464) - node T_467 = bits(T_460, 7, 0) - node T_468 = shl(T_467, 8) - node T_469 = not(T_464) - node T_470 = and(T_468, T_469) - node T_471 = or(T_466, T_470) - node T_472 = bits(T_464, 11, 0) - node T_473 = shl(T_472, 4) - node T_474 = xor(T_464, T_473) - node T_475 = shr(T_471, 4) - node T_476 = and(T_475, T_474) - node T_477 = bits(T_471, 11, 0) - node T_478 = shl(T_477, 4) - node T_479 = not(T_474) - node T_480 = and(T_478, T_479) - node T_481 = or(T_476, T_480) - node T_482 = bits(T_474, 13, 0) - node T_483 = shl(T_482, 2) - node T_484 = xor(T_474, T_483) - node T_485 = shr(T_481, 2) - node T_486 = and(T_485, T_484) - node T_487 = bits(T_481, 13, 0) - node T_488 = shl(T_487, 2) - node T_489 = not(T_484) - node T_490 = and(T_488, T_489) - node T_491 = or(T_486, T_490) - node T_492 = bits(T_484, 14, 0) - node T_493 = shl(T_492, 1) - node T_494 = xor(T_484, T_493) - node T_495 = shr(T_491, 1) - node T_496 = and(T_495, T_494) - node T_497 = bits(T_491, 14, 0) - node T_498 = shl(T_497, 1) - node T_499 = not(T_494) - node T_500 = and(T_498, T_499) - node T_501 = or(T_496, T_500) - node T_502 = bits(T_459, 24, 16) - node T_503 = bits(T_502, 7, 0) - node T_506 = shl(UInt<4>("h0f"), 4) - node T_507 = xor(UInt<8>("h0ff"), T_506) - node T_508 = shr(T_503, 4) - node T_509 = and(T_508, T_507) - node T_510 = bits(T_503, 3, 0) - node T_511 = shl(T_510, 4) - node T_512 = not(T_507) - node T_513 = and(T_511, T_512) - node T_514 = or(T_509, T_513) - node T_515 = bits(T_507, 5, 0) - node T_516 = shl(T_515, 2) - node T_517 = xor(T_507, T_516) - node T_518 = shr(T_514, 2) - node T_519 = and(T_518, T_517) - node T_520 = bits(T_514, 5, 0) - node T_521 = shl(T_520, 2) - node T_522 = not(T_517) - node T_523 = and(T_521, T_522) - node T_524 = or(T_519, T_523) - node T_525 = bits(T_517, 6, 0) - node T_526 = shl(T_525, 1) - node T_527 = xor(T_517, T_526) - node T_528 = shr(T_524, 1) - node T_529 = and(T_528, T_527) - node T_530 = bits(T_524, 6, 0) - node T_531 = shl(T_530, 1) - node T_532 = not(T_527) - node T_533 = and(T_531, T_532) - node T_534 = or(T_529, T_533) - node T_535 = bits(T_502, 8, 8) - node T_536 = cat(T_534, T_535) - node T_537 = cat(T_501, T_536) - node T_538 = bit(sigX3, 26) - node T_539 = or(T_537, T_538) - node T_541 = cat(T_539, UInt<2>("h03")) - node roundMask = or(T_455, T_541) - node T_543 = shr(roundMask, 1) - node T_544 = not(T_543) - node roundPosMask = and(T_544, roundMask) - node T_546 = and(sigX3, roundPosMask) - node roundPosBit = neq(T_546, UInt<1>("h00")) - node T_549 = shr(roundMask, 1) - node T_550 = and(sigX3, T_549) - node anyRoundExtra = neq(T_550, UInt<1>("h00")) - node T_553 = not(sigX3) - node T_554 = shr(roundMask, 1) - node T_555 = and(T_553, T_554) - node allRoundExtra = eq(T_555, UInt<1>("h00")) + node T_466 = bits(sExpX3, 10, 10) + node T_468 = sub(UInt<27>("h00"), T_466) + node T_469 = tail(T_468, 1) + node T_470 = not(sExpX3_13) + node T_472 = dshr(asSInt(UInt<1025>("h010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_470) + node T_473 = bits(T_472, 131, 107) + node T_474 = bits(T_473, 15, 0) + node T_477 = shl(UInt<8>("h0ff"), 8) + node T_478 = xor(UInt<16>("h0ffff"), T_477) + node T_479 = shr(T_474, 8) + node T_480 = and(T_479, T_478) + node T_481 = bits(T_474, 7, 0) + node T_482 = shl(T_481, 8) + node T_483 = not(T_478) + node T_484 = and(T_482, T_483) + node T_485 = or(T_480, T_484) + node T_486 = bits(T_478, 11, 0) + node T_487 = shl(T_486, 4) + node T_488 = xor(T_478, T_487) + node T_489 = shr(T_485, 4) + node T_490 = and(T_489, T_488) + node T_491 = bits(T_485, 11, 0) + node T_492 = shl(T_491, 4) + node T_493 = not(T_488) + node T_494 = and(T_492, T_493) + node T_495 = or(T_490, T_494) + node T_496 = bits(T_488, 13, 0) + node T_497 = shl(T_496, 2) + node T_498 = xor(T_488, T_497) + node T_499 = shr(T_495, 2) + node T_500 = and(T_499, T_498) + node T_501 = bits(T_495, 13, 0) + node T_502 = shl(T_501, 2) + node T_503 = not(T_498) + node T_504 = and(T_502, T_503) + node T_505 = or(T_500, T_504) + node T_506 = bits(T_498, 14, 0) + node T_507 = shl(T_506, 1) + node T_508 = xor(T_498, T_507) + node T_509 = shr(T_505, 1) + node T_510 = and(T_509, T_508) + node T_511 = bits(T_505, 14, 0) + node T_512 = shl(T_511, 1) + node T_513 = not(T_508) + node T_514 = and(T_512, T_513) + node T_515 = or(T_510, T_514) + node T_516 = bits(T_473, 24, 16) + node T_517 = bits(T_516, 7, 0) + node T_520 = shl(UInt<4>("h0f"), 4) + node T_521 = xor(UInt<8>("h0ff"), T_520) + node T_522 = shr(T_517, 4) + node T_523 = and(T_522, T_521) + node T_524 = bits(T_517, 3, 0) + node T_525 = shl(T_524, 4) + node T_526 = not(T_521) + node T_527 = and(T_525, T_526) + node T_528 = or(T_523, T_527) + node T_529 = bits(T_521, 5, 0) + node T_530 = shl(T_529, 2) + node T_531 = xor(T_521, T_530) + node T_532 = shr(T_528, 2) + node T_533 = and(T_532, T_531) + node T_534 = bits(T_528, 5, 0) + node T_535 = shl(T_534, 2) + node T_536 = not(T_531) + node T_537 = and(T_535, T_536) + node T_538 = or(T_533, T_537) + node T_539 = bits(T_531, 6, 0) + node T_540 = shl(T_539, 1) + node T_541 = xor(T_531, T_540) + node T_542 = shr(T_538, 1) + node T_543 = and(T_542, T_541) + node T_544 = bits(T_538, 6, 0) + node T_545 = shl(T_544, 1) + node T_546 = not(T_541) + node T_547 = and(T_545, T_546) + node T_548 = or(T_543, T_547) + node T_549 = bits(T_516, 8, 8) + node T_550 = cat(T_548, T_549) + node T_551 = cat(T_515, T_550) + node T_552 = bits(sigX3, 26, 26) + node T_553 = or(T_551, T_552) + node T_555 = cat(T_553, UInt<2>("h03")) + node roundMask = or(T_469, T_555) + node T_557 = shr(roundMask, 1) + node T_558 = not(T_557) + node roundPosMask = and(T_558, roundMask) + node T_560 = and(sigX3, roundPosMask) + node roundPosBit = neq(T_560, UInt<1>("h00")) + node T_563 = shr(roundMask, 1) + node T_564 = and(sigX3, T_563) + node anyRoundExtra = neq(T_564, UInt<1>("h00")) + node T_567 = not(sigX3) + node T_568 = shr(roundMask, 1) + node T_569 = and(T_567, T_568) + node allRoundExtra = eq(T_569, UInt<1>("h00")) node anyRound = or(roundPosBit, anyRoundExtra) node allRound = and(roundPosBit, allRoundExtra) node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) - node T_561 = not(doIncrSig) - node T_562 = and(T_561, roundingMode_nearest_even) - node T_563 = and(T_562, roundPosBit) - node T_564 = and(T_563, anyRoundExtra) - node T_565 = not(doIncrSig) - node T_566 = and(T_565, roundDirectUp) - node T_567 = and(T_566, anyRound) - node T_568 = or(T_564, T_567) - node T_569 = and(doIncrSig, allRound) - node T_570 = or(T_568, T_569) - node T_571 = and(doIncrSig, roundingMode_nearest_even) - node T_572 = and(T_571, roundPosBit) - node T_573 = or(T_570, T_572) - node T_574 = and(doIncrSig, roundDirectUp) - node T_576 = and(T_574, UInt<1>("h01")) - node roundUp = or(T_573, T_576) - node T_578 = not(roundPosBit) - node T_579 = and(roundingMode_nearest_even, T_578) - node T_580 = and(T_579, allRoundExtra) - node T_581 = and(roundingMode_nearest_even, roundPosBit) - node T_582 = not(anyRoundExtra) - node T_583 = and(T_581, T_582) - node roundEven = mux(doIncrSig, T_580, T_583) - node T_585 = not(allRound) - node roundInexact = mux(doIncrSig, T_585, anyRound) - node T_587 = or(sigX3, roundMask) - node T_588 = shr(T_587, 2) - node T_590 = addw(T_588, UInt<1>("h01")) - node roundUp_sigY3 = bits(T_590, 25, 0) - node T_592 = not(roundUp) - node T_593 = not(roundEven) - node T_594 = and(T_592, T_593) - node T_595 = bit(T_594, 0) - node T_596 = not(roundMask) - node T_597 = and(sigX3, T_596) - node T_598 = shr(T_597, 2) - node T_600 = mux(T_595, T_598, UInt<1>("h00")) - node T_601 = bit(roundUp, 0) - node T_603 = mux(T_601, roundUp_sigY3, UInt<1>("h00")) - node T_604 = or(T_600, T_603) - node T_605 = shr(roundMask, 1) - node T_606 = not(T_605) - node T_607 = and(roundUp_sigY3, T_606) - node T_609 = mux(roundEven, T_607, UInt<1>("h00")) - node sigY3 = or(T_604, T_609) - node T_611 = bit(sigY3, 25) - node T_613 = addw(sExpX3, UInt<1>("h01")) - node T_615 = mux(T_611, T_613, UInt<1>("h00")) - node T_616 = bit(sigY3, 24) - node T_618 = mux(T_616, sExpX3, UInt<1>("h00")) + node T_575 = not(doIncrSig) + node T_576 = and(T_575, roundingMode_nearest_even) + node T_577 = and(T_576, roundPosBit) + node T_578 = and(T_577, anyRoundExtra) + node T_579 = not(doIncrSig) + node T_580 = and(T_579, roundDirectUp) + node T_581 = and(T_580, anyRound) + node T_582 = or(T_578, T_581) + node T_583 = and(doIncrSig, allRound) + node T_584 = or(T_582, T_583) + node T_585 = and(doIncrSig, roundingMode_nearest_even) + node T_586 = and(T_585, roundPosBit) + node T_587 = or(T_584, T_586) + node T_588 = and(doIncrSig, roundDirectUp) + node T_590 = and(T_588, UInt<1>("h01")) + node roundUp = or(T_587, T_590) + node T_592 = not(roundPosBit) + node T_593 = and(roundingMode_nearest_even, T_592) + node T_594 = and(T_593, allRoundExtra) + node T_595 = and(roundingMode_nearest_even, roundPosBit) + node T_596 = not(anyRoundExtra) + node T_597 = and(T_595, T_596) + node roundEven = mux(doIncrSig, T_594, T_597) + node T_599 = not(allRound) + node roundInexact = mux(doIncrSig, T_599, anyRound) + node T_601 = or(sigX3, roundMask) + node T_602 = shr(T_601, 2) + node T_604 = add(T_602, UInt<1>("h01")) + node T_605 = tail(T_604, 1) + node roundUp_sigY3 = bits(T_605, 25, 0) + node T_607 = not(roundUp) + node T_608 = not(roundEven) + node T_609 = and(T_607, T_608) + node T_610 = bits(T_609, 0, 0) + node T_611 = not(roundMask) + node T_612 = and(sigX3, T_611) + node T_613 = shr(T_612, 2) + node T_615 = mux(T_610, T_613, UInt<1>("h00")) + node T_616 = bits(roundUp, 0, 0) + node T_618 = mux(T_616, roundUp_sigY3, UInt<1>("h00")) node T_619 = or(T_615, T_618) - node T_620 = bits(sigY3, 25, 24) - node T_622 = eq(T_620, UInt<1>("h00")) - node T_624 = subw(sExpX3, UInt<1>("h01")) - node T_626 = mux(T_622, T_624, UInt<1>("h00")) - node sExpY = or(T_619, T_626) + node T_620 = shr(roundMask, 1) + node T_621 = not(T_620) + node T_622 = and(roundUp_sigY3, T_621) + node T_624 = mux(roundEven, T_622, UInt<1>("h00")) + node sigY3 = or(T_619, T_624) + node T_626 = bits(sigY3, 25, 25) + node T_628 = add(sExpX3, UInt<1>("h01")) + node T_629 = tail(T_628, 1) + node T_631 = mux(T_626, T_629, UInt<1>("h00")) + node T_632 = bits(sigY3, 24, 24) + node T_634 = mux(T_632, sExpX3, UInt<1>("h00")) + node T_635 = or(T_631, T_634) + node T_636 = bits(sigY3, 25, 24) + node T_638 = eq(T_636, UInt<1>("h00")) + node T_640 = sub(sExpX3, UInt<1>("h01")) + node T_641 = tail(T_640, 1) + node T_643 = mux(T_638, T_641, UInt<1>("h00")) + node sExpY = or(T_635, T_643) node expY = bits(sExpY, 8, 0) - node T_629 = bits(sigY3, 22, 0) - node T_630 = bits(sigY3, 23, 1) - node fractY = mux(sigX3Shift1, T_629, T_630) - node T_632 = bits(sExpY, 9, 7) - node overflowY = eq(T_632, UInt<2>("h03")) - node T_635 = not(isZeroY) - node T_636 = bit(sExpY, 9) - node T_637 = bits(sExpY, 8, 0) - node T_639 = lt(T_637, UInt<7>("h06b")) - node T_640 = or(T_636, T_639) - node totalUnderflowY = and(T_635, T_640) - node T_642 = bit(sExpX3, 10) - node T_645 = mux(sigX3Shift1, UInt<8>("h082"), UInt<8>("h081")) - node T_646 = leq(sExpX3_13, T_645) - node T_647 = or(T_642, T_646) - node underflowY = and(roundInexact, T_647) - node T_649 = and(roundingMode_min, signY) - node T_650 = not(signY) - node T_651 = and(roundingMode_max, T_650) - node roundMagUp = or(T_649, T_651) + node T_646 = bits(sigY3, 22, 0) + node T_647 = bits(sigY3, 23, 1) + node fractY = mux(sigX3Shift1, T_646, T_647) + node T_649 = bits(sExpY, 9, 7) + node overflowY = eq(T_649, UInt<2>("h03")) + node T_652 = not(isZeroY) + node T_653 = bits(sExpY, 9, 9) + node T_654 = bits(sExpY, 8, 0) + node T_656 = lt(T_654, UInt<7>("h06b")) + node T_657 = or(T_653, T_656) + node totalUnderflowY = and(T_652, T_657) + node T_659 = bits(sExpX3, 10, 10) + node T_662 = mux(sigX3Shift1, UInt<8>("h082"), UInt<8>("h081")) + node T_663 = leq(sExpX3_13, T_662) + node T_664 = or(T_659, T_663) + node underflowY = and(roundInexact, T_664) + node T_666 = and(roundingMode_min, signY) + node T_667 = not(signY) + node T_668 = and(roundingMode_max, T_667) + node roundMagUp = or(T_666, T_668) node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp) node mulSpecial = or(isSpecialA, isSpecialB) node addSpecial = or(mulSpecial, isSpecialC) node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC) - node T_657 = not(addSpecial) - node T_658 = not(notSpecial_addZeros) - node commonCase = and(T_657, T_658) - node T_660 = and(isInfA, isZeroB) - node T_661 = and(isZeroA, isInfB) - node T_662 = or(T_660, T_661) - node T_663 = not(isNaNA) - node T_664 = not(isNaNB) - node T_665 = and(T_663, T_664) - node T_666 = or(isInfA, isInfB) - node T_667 = and(T_665, T_666) - node T_668 = and(T_667, isInfC) - node T_669 = and(T_668, doSubMags) - node notSigNaN_invalid = or(T_662, T_669) - node T_671 = or(isSigNaNA, isSigNaNB) - node T_672 = or(T_671, isSigNaNC) - node invalid = or(T_672, notSigNaN_invalid) + node T_674 = not(addSpecial) + node T_675 = not(notSpecial_addZeros) + node commonCase = and(T_674, T_675) + node T_677 = and(isInfA, isZeroB) + node T_678 = and(isZeroA, isInfB) + node T_679 = or(T_677, T_678) + node T_680 = not(isNaNA) + node T_681 = not(isNaNB) + node T_682 = and(T_680, T_681) + node T_683 = or(isInfA, isInfB) + node T_684 = and(T_682, T_683) + node T_685 = and(T_684, isInfC) + node T_686 = and(T_685, doSubMags) + node notSigNaN_invalid = or(T_679, T_686) + node T_688 = or(isSigNaNA, isSigNaNB) + node T_689 = or(T_688, isSigNaNC) + node invalid = or(T_689, notSigNaN_invalid) node overflow = and(commonCase, overflowY) node underflow = and(commonCase, underflowY) - node T_676 = and(commonCase, roundInexact) - node inexact = or(overflow, T_676) - node T_678 = or(notSpecial_addZeros, isZeroY) - node notSpecial_isZeroOut = or(T_678, totalUnderflowY) - node T_680 = and(commonCase, totalUnderflowY) - node pegMinFiniteMagOut = and(T_680, roundMagUp) - node T_682 = not(overflowY_roundMagUp) - node pegMaxFiniteMagOut = and(overflow, T_682) - node T_684 = or(isInfA, isInfB) - node T_685 = or(T_684, isInfC) - node T_686 = and(overflow, overflowY_roundMagUp) - node notNaN_isInfOut = or(T_685, T_686) - node T_688 = or(isNaNA, isNaNB) - node T_689 = or(T_688, isNaNC) - node isNaNOut = or(T_689, notSigNaN_invalid) - node T_692 = eq(doSubMags, UInt<1>("h00")) - node T_693 = and(T_692, io.fromPreMul.opSignC) - node T_695 = eq(isSpecialC, UInt<1>("h00")) - node T_696 = and(mulSpecial, T_695) - node T_697 = and(T_696, io.fromPreMul.signProd) - node T_698 = or(T_693, T_697) - node T_700 = eq(mulSpecial, UInt<1>("h00")) - node T_701 = and(T_700, isSpecialC) - node T_702 = and(T_701, io.fromPreMul.opSignC) - node T_703 = or(T_698, T_702) - node T_705 = eq(mulSpecial, UInt<1>("h00")) - node T_706 = and(T_705, notSpecial_addZeros) - node T_707 = and(T_706, doSubMags) - node T_708 = and(T_707, signZeroNotEqOpSigns) - node uncommonCaseSignOut = or(T_703, T_708) - node T_711 = eq(isNaNOut, UInt<1>("h00")) - node T_712 = and(T_711, uncommonCaseSignOut) - node T_713 = and(commonCase, signY) - node signOut = or(T_712, T_713) - node T_717 = mux(notSpecial_isZeroOut, UInt<9>("h01c0"), UInt<9>("h00")) - node T_718 = not(T_717) - node T_719 = and(expY, T_718) - node T_721 = not(UInt<9>("h06b")) - node T_723 = mux(pegMinFiniteMagOut, T_721, UInt<9>("h00")) - node T_724 = not(T_723) - node T_725 = and(T_719, T_724) - node T_728 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<9>("h00")) - node T_729 = not(T_728) - node T_730 = and(T_725, T_729) - node T_733 = mux(notNaN_isInfOut, UInt<7>("h040"), UInt<9>("h00")) - node T_734 = not(T_733) - node T_735 = and(T_730, T_734) - node T_738 = mux(pegMinFiniteMagOut, UInt<7>("h06b"), UInt<9>("h00")) - node T_739 = or(T_735, T_738) - node T_742 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<9>("h00")) - node T_743 = or(T_739, T_742) - node T_746 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<9>("h00")) - node T_747 = or(T_743, T_746) - node T_750 = mux(isNaNOut, UInt<9>("h01c0"), UInt<9>("h00")) - node expOut = or(T_747, T_750) - node T_752 = and(totalUnderflowY, roundMagUp) - node T_753 = or(T_752, isNaNOut) - node T_755 = mux(T_753, UInt<1>("h00"), fractY) - node T_756 = shl(isNaNOut, 22) - node T_757 = or(T_755, T_756) - node T_759 = subw(UInt<23>("h00"), pegMaxFiniteMagOut) - node fractOut = or(T_757, T_759) - node T_761 = cat(expOut, fractOut) - node T_762 = cat(signOut, T_761) - io.out <= T_762 - node T_764 = cat(invalid, UInt<1>("h00")) - node T_765 = cat(underflow, inexact) - node T_766 = cat(overflow, T_765) - node T_767 = cat(T_764, T_766) - io.exceptionFlags <= T_767 + node T_693 = and(commonCase, roundInexact) + node inexact = or(overflow, T_693) + node T_695 = or(notSpecial_addZeros, isZeroY) + node notSpecial_isZeroOut = or(T_695, totalUnderflowY) + node T_697 = and(commonCase, totalUnderflowY) + node pegMinFiniteMagOut = and(T_697, roundMagUp) + node T_699 = not(overflowY_roundMagUp) + node pegMaxFiniteMagOut = and(overflow, T_699) + node T_701 = or(isInfA, isInfB) + node T_702 = or(T_701, isInfC) + node T_703 = and(overflow, overflowY_roundMagUp) + node notNaN_isInfOut = or(T_702, T_703) + node T_705 = or(isNaNA, isNaNB) + node T_706 = or(T_705, isNaNC) + node isNaNOut = or(T_706, notSigNaN_invalid) + node T_709 = eq(doSubMags, UInt<1>("h00")) + node T_710 = and(T_709, io.fromPreMul.opSignC) + node T_712 = eq(isSpecialC, UInt<1>("h00")) + node T_713 = and(mulSpecial, T_712) + node T_714 = and(T_713, io.fromPreMul.signProd) + node T_715 = or(T_710, T_714) + node T_717 = eq(mulSpecial, UInt<1>("h00")) + node T_718 = and(T_717, isSpecialC) + node T_719 = and(T_718, io.fromPreMul.opSignC) + node T_720 = or(T_715, T_719) + node T_722 = eq(mulSpecial, UInt<1>("h00")) + node T_723 = and(T_722, notSpecial_addZeros) + node T_724 = and(T_723, doSubMags) + node T_725 = and(T_724, signZeroNotEqOpSigns) + node uncommonCaseSignOut = or(T_720, T_725) + node T_728 = eq(isNaNOut, UInt<1>("h00")) + node T_729 = and(T_728, uncommonCaseSignOut) + node T_730 = and(commonCase, signY) + node signOut = or(T_729, T_730) + node T_734 = mux(notSpecial_isZeroOut, UInt<9>("h01c0"), UInt<9>("h00")) + node T_735 = not(T_734) + node T_736 = and(expY, T_735) + node T_738 = not(UInt<9>("h06b")) + node T_740 = mux(pegMinFiniteMagOut, T_738, UInt<9>("h00")) + node T_741 = not(T_740) + node T_742 = and(T_736, T_741) + node T_745 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<9>("h00")) + node T_746 = not(T_745) + node T_747 = and(T_742, T_746) + node T_750 = mux(notNaN_isInfOut, UInt<7>("h040"), UInt<9>("h00")) + node T_751 = not(T_750) + node T_752 = and(T_747, T_751) + node T_755 = mux(pegMinFiniteMagOut, UInt<7>("h06b"), UInt<9>("h00")) + node T_756 = or(T_752, T_755) + node T_759 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<9>("h00")) + node T_760 = or(T_756, T_759) + node T_763 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<9>("h00")) + node T_764 = or(T_760, T_763) + node T_767 = mux(isNaNOut, UInt<9>("h01c0"), UInt<9>("h00")) + node expOut = or(T_764, T_767) + node T_769 = and(totalUnderflowY, roundMagUp) + node T_770 = or(T_769, isNaNOut) + node T_772 = mux(T_770, UInt<1>("h00"), fractY) + node T_773 = shl(isNaNOut, 22) + node T_774 = or(T_772, T_773) + node T_776 = sub(UInt<23>("h00"), pegMaxFiniteMagOut) + node T_777 = tail(T_776, 1) + node fractOut = or(T_774, T_777) + node T_779 = cat(expOut, fractOut) + node T_780 = cat(signOut, T_779) + io.out <= T_780 + node T_782 = cat(invalid, UInt<1>("h00")) + node T_783 = cat(underflow, inexact) + node T_784 = cat(overflow, T_783) + node T_785 = cat(T_782, T_784) + io.exceptionFlags <= T_785 module MulAddRecFN : input clk : Clock input reset : UInt<1> output io : {flip op : UInt<2>, flip a : UInt<33>, flip b : UInt<33>, flip c : UInt<33>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} - io.exceptionFlags <= UInt<1>("h00") - io.out <= UInt<1>("h00") + io is invalid inst mulAddRecFN_preMul of MulAddRecFN_preMul - mulAddRecFN_preMul.io.roundingMode <= UInt<1>("h00") - mulAddRecFN_preMul.io.c <= UInt<1>("h00") - mulAddRecFN_preMul.io.b <= UInt<1>("h00") - mulAddRecFN_preMul.io.a <= UInt<1>("h00") - mulAddRecFN_preMul.io.op <= UInt<1>("h00") + mulAddRecFN_preMul.io is invalid mulAddRecFN_preMul.clk <= clk mulAddRecFN_preMul.reset <= reset inst mulAddRecFN_postMul of MulAddRecFN_postMul - mulAddRecFN_postMul.io.mulAddResult <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.roundingMode <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.sExpSum <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.highAlignedNegSigC <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.bit0AlignedNegSigC <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.CAlignDist <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.CAlignDist_0 <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.isCDominant <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.isNaN_isQuietNaNC <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.highExpC <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.opSignC <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.isZeroProd <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.signProd <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.isNaN_isQuietNaNB <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.highExpB <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.isNaN_isQuietNaNA <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.highExpA <= UInt<1>("h00") + mulAddRecFN_postMul.io is invalid mulAddRecFN_postMul.clk <= clk mulAddRecFN_postMul.reset <= reset mulAddRecFN_preMul.io.op <= io.op @@ -34823,10 +27002,11 @@ circuit Top : mulAddRecFN_preMul.io.c <= io.c mulAddRecFN_preMul.io.roundingMode <= io.roundingMode mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul - node T_36 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) - node T_38 = cat(UInt<1>("h00"), mulAddRecFN_preMul.io.mulAddC) - node T_39 = addw(T_36, T_38) - mulAddRecFN_postMul.io.mulAddResult <= T_39 + node T_14 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) + node T_16 = cat(UInt<1>("h00"), mulAddRecFN_preMul.io.mulAddC) + node T_17 = add(T_14, T_16) + node T_18 = tail(T_17, 1) + mulAddRecFN_postMul.io.mulAddResult <= T_18 io.out <= mulAddRecFN_postMul.io.out io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags @@ -34835,23 +27015,21 @@ circuit Top : input reset : UInt<1> output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} - io.out.bits.exc <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") + io is invalid node one = shl(UInt<1>("h01"), 31) - node T_136 = bit(io.in.bits.in1, 32) - node T_137 = bit(io.in.bits.in2, 32) + node T_136 = bits(io.in.bits.in1, 32, 32) + node T_137 = bits(io.in.bits.in2, 32, 32) node T_138 = xor(T_136, T_137) node zero = shl(T_138, 32) - reg valid : UInt<1>, clk, UInt<1>("h00"), valid + reg valid : UInt<1>, clk valid <= io.in.valid - reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk, UInt<1>("h00"), in + reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk when io.in.valid : in <- io.in.bits - node T_187 = bit(io.in.bits.cmd, 1) + node T_187 = bits(io.in.bits.cmd, 1, 1) node T_188 = or(io.in.bits.ren3, io.in.bits.swap23) node T_189 = and(T_187, T_188) - node T_190 = bit(io.in.bits.cmd, 0) + node T_190 = bits(io.in.bits.cmd, 0, 0) node T_191 = cat(T_189, T_190) in.cmd <= T_191 when io.in.bits.swap23 : @@ -34864,11 +27042,7 @@ circuit Top : skip skip inst fma of MulAddRecFN - fma.io.roundingMode <= UInt<1>("h00") - fma.io.c <= UInt<1>("h00") - fma.io.b <= UInt<1>("h00") - fma.io.a <= UInt<1>("h00") - fma.io.op <= UInt<1>("h00") + fma.io is invalid fma.clk <= clk fma.reset <= reset fma.io.op <= in.cmd @@ -34877,66 +27051,45 @@ circuit Top : fma.io.b <= in.in2 fma.io.c <= in.in3 wire res : {data : UInt<65>, exc : UInt<5>} - res.exc <= UInt<1>("h00") - res.data <= UInt<1>("h00") - node T_210 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_211 = cat(T_210, fma.io.out) - res.data <= T_211 + res is invalid + node T_203 = asUInt(asSInt(UInt<32>("h0ffffffff"))) + node T_204 = cat(T_203, fma.io.out) + res.data <= T_204 res.exc <= fma.io.exceptionFlags - reg T_214 : UInt<1>, clk, reset, UInt<1>("h00") - T_214 <= valid - reg T_215 : {data : UInt<65>, exc : UInt<5>}, clk, UInt<1>("h00"), T_215 + reg T_207 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + T_207 <= valid + reg T_208 : {data : UInt<65>, exc : UInt<5>}, clk when valid : - T_215 <- res + T_208 <- res skip - wire T_226 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} - T_226.bits.exc <= UInt<1>("h00") - T_226.bits.data <= UInt<1>("h00") - T_226.valid <= UInt<1>("h00") - T_226.valid <= T_214 - T_226.bits <- T_215 - io.out <- T_226 + wire T_219 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} + T_219 is invalid + T_219.valid <= T_207 + T_219.bits <- T_208 + io.out <- T_219 module MulAddRecFN_preMul_115 : input clk : Clock input reset : UInt<1> output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, mulAddA : UInt<53>, mulAddB : UInt<53>, mulAddC : UInt<106>, toPostMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}} - io.toPostMul.roundingMode <= UInt<1>("h00") - io.toPostMul.sExpSum <= UInt<1>("h00") - io.toPostMul.highAlignedNegSigC <= UInt<1>("h00") - io.toPostMul.bit0AlignedNegSigC <= UInt<1>("h00") - io.toPostMul.CAlignDist <= UInt<1>("h00") - io.toPostMul.CAlignDist_0 <= UInt<1>("h00") - io.toPostMul.isCDominant <= UInt<1>("h00") - io.toPostMul.isNaN_isQuietNaNC <= UInt<1>("h00") - io.toPostMul.highExpC <= UInt<1>("h00") - io.toPostMul.opSignC <= UInt<1>("h00") - io.toPostMul.isZeroProd <= UInt<1>("h00") - io.toPostMul.signProd <= UInt<1>("h00") - io.toPostMul.isNaN_isQuietNaNB <= UInt<1>("h00") - io.toPostMul.highExpB <= UInt<1>("h00") - io.toPostMul.isNaN_isQuietNaNA <= UInt<1>("h00") - io.toPostMul.highExpA <= UInt<1>("h00") - io.mulAddC <= UInt<1>("h00") - io.mulAddB <= UInt<1>("h00") - io.mulAddA <= UInt<1>("h00") - node signA = bit(io.a, 64) + io is invalid + node signA = bits(io.a, 64, 64) node expA = bits(io.a, 63, 52) node fractA = bits(io.a, 51, 0) node T_50 = bits(expA, 11, 9) node isZeroA = eq(T_50, UInt<1>("h00")) node T_54 = eq(isZeroA, UInt<1>("h00")) node sigA = cat(T_54, fractA) - node signB = bit(io.b, 64) + node signB = bits(io.b, 64, 64) node expB = bits(io.b, 63, 52) node fractB = bits(io.b, 51, 0) node T_59 = bits(expB, 11, 9) node isZeroB = eq(T_59, UInt<1>("h00")) node T_63 = eq(isZeroB, UInt<1>("h00")) node sigB = cat(T_63, fractB) - node T_65 = bit(io.c, 64) - node T_66 = bit(io.op, 0) + node T_65 = bits(io.c, 64, 64) + node T_66 = bits(io.op, 0, 0) node opSignC = xor(T_65, T_66) node expC = bits(io.c, 63, 52) node fractC = bits(io.c, 51, 0) @@ -34945,181 +27098,186 @@ circuit Top : node T_74 = eq(isZeroC, UInt<1>("h00")) node sigC = cat(T_74, fractC) node T_76 = xor(signA, signB) - node T_77 = bit(io.op, 1) + node T_77 = bits(io.op, 1, 1) node signProd = xor(T_76, T_77) node isZeroProd = or(isZeroA, isZeroB) - node T_80 = bit(expB, 11) + node T_80 = bits(expB, 11, 11) node T_82 = eq(T_80, UInt<1>("h00")) - node T_84 = subw(UInt<3>("h00"), T_82) - node T_85 = bits(expB, 10, 0) - node T_86 = cat(T_84, T_85) - node T_87 = addw(expA, T_86) - node sExpAlignedProd = addw(T_87, UInt<6>("h038")) + node T_84 = sub(UInt<3>("h00"), T_82) + node T_85 = tail(T_84, 1) + node T_86 = bits(expB, 10, 0) + node T_87 = cat(T_85, T_86) + node T_88 = add(expA, T_87) + node T_89 = tail(T_88, 1) + node T_91 = add(T_89, UInt<6>("h038")) + node sExpAlignedProd = tail(T_91, 1) node doSubMags = xor(signProd, opSignC) - node sNatCAlignDist = subw(sExpAlignedProd, expC) - node T_92 = bit(sNatCAlignDist, 13) - node CAlignDist_floor = or(isZeroProd, T_92) - node T_94 = bits(sNatCAlignDist, 12, 0) - node T_96 = eq(T_94, UInt<1>("h00")) - node CAlignDist_0 = or(CAlignDist_floor, T_96) - node T_99 = eq(isZeroC, UInt<1>("h00")) - node T_100 = bits(sNatCAlignDist, 12, 0) - node T_102 = lt(T_100, UInt<6>("h036")) - node T_103 = or(CAlignDist_floor, T_102) - node isCDominant = and(T_99, T_103) - node T_106 = bits(sNatCAlignDist, 12, 0) - node T_108 = lt(T_106, UInt<8>("h0a1")) - node T_109 = bits(sNatCAlignDist, 7, 0) - node T_111 = mux(T_108, T_109, UInt<8>("h0a1")) - node CAlignDist = mux(CAlignDist_floor, UInt<1>("h00"), T_111) + node T_94 = sub(sExpAlignedProd, expC) + node sNatCAlignDist = tail(T_94, 1) + node T_96 = bits(sNatCAlignDist, 13, 13) + node CAlignDist_floor = or(isZeroProd, T_96) + node T_98 = bits(sNatCAlignDist, 12, 0) + node T_100 = eq(T_98, UInt<1>("h00")) + node CAlignDist_0 = or(CAlignDist_floor, T_100) + node T_103 = eq(isZeroC, UInt<1>("h00")) + node T_104 = bits(sNatCAlignDist, 12, 0) + node T_106 = lt(T_104, UInt<6>("h036")) + node T_107 = or(CAlignDist_floor, T_106) + node isCDominant = and(T_103, T_107) + node T_110 = bits(sNatCAlignDist, 12, 0) + node T_112 = lt(T_110, UInt<8>("h0a1")) + node T_113 = bits(sNatCAlignDist, 7, 0) + node T_115 = mux(T_112, T_113, UInt<8>("h0a1")) + node CAlignDist = mux(CAlignDist_floor, UInt<1>("h00"), T_115) node sExpSum = mux(CAlignDist_floor, expC, sExpAlignedProd) - node T_115 = dshr(asSInt(UInt<257>("h010000000000000000000000000000000000000000000000000000000000000000")), CAlignDist) - node T_116 = bits(T_115, 147, 95) - node T_117 = bits(T_116, 31, 0) - node T_120 = shl(UInt<16>("h0ffff"), 16) - node T_121 = xor(UInt<32>("h0ffffffff"), T_120) - node T_122 = shr(T_117, 16) - node T_123 = and(T_122, T_121) - node T_124 = bits(T_117, 15, 0) - node T_125 = shl(T_124, 16) - node T_126 = not(T_121) - node T_127 = and(T_125, T_126) - node T_128 = or(T_123, T_127) - node T_129 = bits(T_121, 23, 0) - node T_130 = shl(T_129, 8) - node T_131 = xor(T_121, T_130) - node T_132 = shr(T_128, 8) - node T_133 = and(T_132, T_131) - node T_134 = bits(T_128, 23, 0) - node T_135 = shl(T_134, 8) - node T_136 = not(T_131) - node T_137 = and(T_135, T_136) - node T_138 = or(T_133, T_137) - node T_139 = bits(T_131, 27, 0) - node T_140 = shl(T_139, 4) - node T_141 = xor(T_131, T_140) - node T_142 = shr(T_138, 4) - node T_143 = and(T_142, T_141) - node T_144 = bits(T_138, 27, 0) - node T_145 = shl(T_144, 4) - node T_146 = not(T_141) - node T_147 = and(T_145, T_146) - node T_148 = or(T_143, T_147) - node T_149 = bits(T_141, 29, 0) - node T_150 = shl(T_149, 2) - node T_151 = xor(T_141, T_150) - node T_152 = shr(T_148, 2) - node T_153 = and(T_152, T_151) - node T_154 = bits(T_148, 29, 0) - node T_155 = shl(T_154, 2) - node T_156 = not(T_151) - node T_157 = and(T_155, T_156) - node T_158 = or(T_153, T_157) - node T_159 = bits(T_151, 30, 0) - node T_160 = shl(T_159, 1) - node T_161 = xor(T_151, T_160) - node T_162 = shr(T_158, 1) - node T_163 = and(T_162, T_161) - node T_164 = bits(T_158, 30, 0) - node T_165 = shl(T_164, 1) - node T_166 = not(T_161) - node T_167 = and(T_165, T_166) - node T_168 = or(T_163, T_167) - node T_169 = bits(T_116, 52, 32) - node T_170 = bits(T_169, 15, 0) - node T_173 = shl(UInt<8>("h0ff"), 8) - node T_174 = xor(UInt<16>("h0ffff"), T_173) - node T_175 = shr(T_170, 8) - node T_176 = and(T_175, T_174) - node T_177 = bits(T_170, 7, 0) - node T_178 = shl(T_177, 8) - node T_179 = not(T_174) - node T_180 = and(T_178, T_179) - node T_181 = or(T_176, T_180) - node T_182 = bits(T_174, 11, 0) - node T_183 = shl(T_182, 4) - node T_184 = xor(T_174, T_183) - node T_185 = shr(T_181, 4) - node T_186 = and(T_185, T_184) - node T_187 = bits(T_181, 11, 0) - node T_188 = shl(T_187, 4) - node T_189 = not(T_184) - node T_190 = and(T_188, T_189) - node T_191 = or(T_186, T_190) - node T_192 = bits(T_184, 13, 0) - node T_193 = shl(T_192, 2) - node T_194 = xor(T_184, T_193) - node T_195 = shr(T_191, 2) - node T_196 = and(T_195, T_194) - node T_197 = bits(T_191, 13, 0) - node T_198 = shl(T_197, 2) - node T_199 = not(T_194) - node T_200 = and(T_198, T_199) - node T_201 = or(T_196, T_200) - node T_202 = bits(T_194, 14, 0) - node T_203 = shl(T_202, 1) - node T_204 = xor(T_194, T_203) - node T_205 = shr(T_201, 1) - node T_206 = and(T_205, T_204) - node T_207 = bits(T_201, 14, 0) - node T_208 = shl(T_207, 1) - node T_209 = not(T_204) - node T_210 = and(T_208, T_209) - node T_211 = or(T_206, T_210) - node T_212 = bits(T_169, 20, 16) - node T_213 = bits(T_212, 3, 0) - node T_214 = bits(T_213, 1, 0) - node T_215 = bits(T_214, 0, 0) - node T_216 = bits(T_214, 1, 1) - node T_217 = cat(T_215, T_216) - node T_218 = bits(T_213, 3, 2) + node T_119 = dshr(asSInt(UInt<257>("h010000000000000000000000000000000000000000000000000000000000000000")), CAlignDist) + node T_120 = bits(T_119, 147, 95) + node T_121 = bits(T_120, 31, 0) + node T_124 = shl(UInt<16>("h0ffff"), 16) + node T_125 = xor(UInt<32>("h0ffffffff"), T_124) + node T_126 = shr(T_121, 16) + node T_127 = and(T_126, T_125) + node T_128 = bits(T_121, 15, 0) + node T_129 = shl(T_128, 16) + node T_130 = not(T_125) + node T_131 = and(T_129, T_130) + node T_132 = or(T_127, T_131) + node T_133 = bits(T_125, 23, 0) + node T_134 = shl(T_133, 8) + node T_135 = xor(T_125, T_134) + node T_136 = shr(T_132, 8) + node T_137 = and(T_136, T_135) + node T_138 = bits(T_132, 23, 0) + node T_139 = shl(T_138, 8) + node T_140 = not(T_135) + node T_141 = and(T_139, T_140) + node T_142 = or(T_137, T_141) + node T_143 = bits(T_135, 27, 0) + node T_144 = shl(T_143, 4) + node T_145 = xor(T_135, T_144) + node T_146 = shr(T_142, 4) + node T_147 = and(T_146, T_145) + node T_148 = bits(T_142, 27, 0) + node T_149 = shl(T_148, 4) + node T_150 = not(T_145) + node T_151 = and(T_149, T_150) + node T_152 = or(T_147, T_151) + node T_153 = bits(T_145, 29, 0) + node T_154 = shl(T_153, 2) + node T_155 = xor(T_145, T_154) + node T_156 = shr(T_152, 2) + node T_157 = and(T_156, T_155) + node T_158 = bits(T_152, 29, 0) + node T_159 = shl(T_158, 2) + node T_160 = not(T_155) + node T_161 = and(T_159, T_160) + node T_162 = or(T_157, T_161) + node T_163 = bits(T_155, 30, 0) + node T_164 = shl(T_163, 1) + node T_165 = xor(T_155, T_164) + node T_166 = shr(T_162, 1) + node T_167 = and(T_166, T_165) + node T_168 = bits(T_162, 30, 0) + node T_169 = shl(T_168, 1) + node T_170 = not(T_165) + node T_171 = and(T_169, T_170) + node T_172 = or(T_167, T_171) + node T_173 = bits(T_120, 52, 32) + node T_174 = bits(T_173, 15, 0) + node T_177 = shl(UInt<8>("h0ff"), 8) + node T_178 = xor(UInt<16>("h0ffff"), T_177) + node T_179 = shr(T_174, 8) + node T_180 = and(T_179, T_178) + node T_181 = bits(T_174, 7, 0) + node T_182 = shl(T_181, 8) + node T_183 = not(T_178) + node T_184 = and(T_182, T_183) + node T_185 = or(T_180, T_184) + node T_186 = bits(T_178, 11, 0) + node T_187 = shl(T_186, 4) + node T_188 = xor(T_178, T_187) + node T_189 = shr(T_185, 4) + node T_190 = and(T_189, T_188) + node T_191 = bits(T_185, 11, 0) + node T_192 = shl(T_191, 4) + node T_193 = not(T_188) + node T_194 = and(T_192, T_193) + node T_195 = or(T_190, T_194) + node T_196 = bits(T_188, 13, 0) + node T_197 = shl(T_196, 2) + node T_198 = xor(T_188, T_197) + node T_199 = shr(T_195, 2) + node T_200 = and(T_199, T_198) + node T_201 = bits(T_195, 13, 0) + node T_202 = shl(T_201, 2) + node T_203 = not(T_198) + node T_204 = and(T_202, T_203) + node T_205 = or(T_200, T_204) + node T_206 = bits(T_198, 14, 0) + node T_207 = shl(T_206, 1) + node T_208 = xor(T_198, T_207) + node T_209 = shr(T_205, 1) + node T_210 = and(T_209, T_208) + node T_211 = bits(T_205, 14, 0) + node T_212 = shl(T_211, 1) + node T_213 = not(T_208) + node T_214 = and(T_212, T_213) + node T_215 = or(T_210, T_214) + node T_216 = bits(T_173, 20, 16) + node T_217 = bits(T_216, 3, 0) + node T_218 = bits(T_217, 1, 0) node T_219 = bits(T_218, 0, 0) node T_220 = bits(T_218, 1, 1) node T_221 = cat(T_219, T_220) - node T_222 = cat(T_217, T_221) - node T_223 = bits(T_212, 4, 4) - node T_224 = cat(T_222, T_223) - node T_225 = cat(T_211, T_224) - node CExtraMask = cat(T_168, T_225) - node T_227 = not(sigC) - node negSigC = mux(doSubMags, T_227, sigC) - node T_230 = subw(UInt<108>("h00"), doSubMags) - node T_231 = cat(negSigC, T_230) - node T_232 = cat(doSubMags, T_231) - node T_233 = asSInt(T_232) - node T_234 = dshr(T_233, CAlignDist) - node T_235 = and(sigC, CExtraMask) - node T_237 = neq(T_235, UInt<1>("h00")) - node T_238 = xor(T_237, doSubMags) - node T_239 = asUInt(T_234) - node T_240 = cat(T_239, T_238) - node alignedNegSigC = bits(T_240, 161, 0) + node T_222 = bits(T_217, 3, 2) + node T_223 = bits(T_222, 0, 0) + node T_224 = bits(T_222, 1, 1) + node T_225 = cat(T_223, T_224) + node T_226 = cat(T_221, T_225) + node T_227 = bits(T_216, 4, 4) + node T_228 = cat(T_226, T_227) + node T_229 = cat(T_215, T_228) + node CExtraMask = cat(T_172, T_229) + node T_231 = not(sigC) + node negSigC = mux(doSubMags, T_231, sigC) + node T_234 = sub(UInt<108>("h00"), doSubMags) + node T_235 = tail(T_234, 1) + node T_236 = cat(negSigC, T_235) + node T_237 = cat(doSubMags, T_236) + node T_238 = asSInt(T_237) + node T_239 = dshr(T_238, CAlignDist) + node T_240 = and(sigC, CExtraMask) + node T_242 = neq(T_240, UInt<1>("h00")) + node T_243 = xor(T_242, doSubMags) + node T_244 = asUInt(T_239) + node T_245 = cat(T_244, T_243) + node alignedNegSigC = bits(T_245, 161, 0) io.mulAddA <= sigA io.mulAddB <= sigB - node T_242 = bits(alignedNegSigC, 106, 1) - io.mulAddC <= T_242 - node T_243 = bits(expA, 11, 9) - io.toPostMul.highExpA <= T_243 - node T_244 = bit(fractA, 51) - io.toPostMul.isNaN_isQuietNaNA <= T_244 - node T_245 = bits(expB, 11, 9) - io.toPostMul.highExpB <= T_245 - node T_246 = bit(fractB, 51) - io.toPostMul.isNaN_isQuietNaNB <= T_246 + node T_247 = bits(alignedNegSigC, 106, 1) + io.mulAddC <= T_247 + node T_248 = bits(expA, 11, 9) + io.toPostMul.highExpA <= T_248 + node T_249 = bits(fractA, 51, 51) + io.toPostMul.isNaN_isQuietNaNA <= T_249 + node T_250 = bits(expB, 11, 9) + io.toPostMul.highExpB <= T_250 + node T_251 = bits(fractB, 51, 51) + io.toPostMul.isNaN_isQuietNaNB <= T_251 io.toPostMul.signProd <= signProd io.toPostMul.isZeroProd <= isZeroProd io.toPostMul.opSignC <= opSignC - node T_247 = bits(expC, 11, 9) - io.toPostMul.highExpC <= T_247 - node T_248 = bit(fractC, 51) - io.toPostMul.isNaN_isQuietNaNC <= T_248 + node T_252 = bits(expC, 11, 9) + io.toPostMul.highExpC <= T_252 + node T_253 = bits(fractC, 51, 51) + io.toPostMul.isNaN_isQuietNaNC <= T_253 io.toPostMul.isCDominant <= isCDominant io.toPostMul.CAlignDist_0 <= CAlignDist_0 io.toPostMul.CAlignDist <= CAlignDist - node T_249 = bit(alignedNegSigC, 0) - io.toPostMul.bit0AlignedNegSigC <= T_249 - node T_250 = bits(alignedNegSigC, 161, 107) - io.toPostMul.highAlignedNegSigC <= T_250 + node T_254 = bits(alignedNegSigC, 0, 0) + io.toPostMul.bit0AlignedNegSigC <= T_254 + node T_255 = bits(alignedNegSigC, 161, 107) + io.toPostMul.highAlignedNegSigC <= T_255 io.toPostMul.sExpSum <= sExpSum io.toPostMul.roundingMode <= io.roundingMode @@ -35128,35 +27286,34 @@ circuit Top : input reset : UInt<1> output io : {flip fromPreMul : {highExpA : UInt<3>, isNaN_isQuietNaNA : UInt<1>, highExpB : UInt<3>, isNaN_isQuietNaNB : UInt<1>, signProd : UInt<1>, isZeroProd : UInt<1>, opSignC : UInt<1>, highExpC : UInt<3>, isNaN_isQuietNaNC : UInt<1>, isCDominant : UInt<1>, CAlignDist_0 : UInt<1>, CAlignDist : UInt<8>, bit0AlignedNegSigC : UInt<1>, highAlignedNegSigC : UInt<55>, sExpSum : UInt<14>, roundingMode : UInt<2>}, flip mulAddResult : UInt<107>, out : UInt<65>, exceptionFlags : UInt<5>} - io.exceptionFlags <= UInt<1>("h00") - io.out <= UInt<1>("h00") + io is invalid node isZeroA = eq(io.fromPreMul.highExpA, UInt<1>("h00")) node T_44 = bits(io.fromPreMul.highExpA, 2, 1) node isSpecialA = eq(T_44, UInt<2>("h03")) - node T_47 = bit(io.fromPreMul.highExpA, 0) + node T_47 = bits(io.fromPreMul.highExpA, 0, 0) node T_49 = eq(T_47, UInt<1>("h00")) node isInfA = and(isSpecialA, T_49) - node T_51 = bit(io.fromPreMul.highExpA, 0) + node T_51 = bits(io.fromPreMul.highExpA, 0, 0) node isNaNA = and(isSpecialA, T_51) node T_54 = eq(io.fromPreMul.isNaN_isQuietNaNA, UInt<1>("h00")) node isSigNaNA = and(isNaNA, T_54) node isZeroB = eq(io.fromPreMul.highExpB, UInt<1>("h00")) node T_58 = bits(io.fromPreMul.highExpB, 2, 1) node isSpecialB = eq(T_58, UInt<2>("h03")) - node T_61 = bit(io.fromPreMul.highExpB, 0) + node T_61 = bits(io.fromPreMul.highExpB, 0, 0) node T_63 = eq(T_61, UInt<1>("h00")) node isInfB = and(isSpecialB, T_63) - node T_65 = bit(io.fromPreMul.highExpB, 0) + node T_65 = bits(io.fromPreMul.highExpB, 0, 0) node isNaNB = and(isSpecialB, T_65) node T_68 = eq(io.fromPreMul.isNaN_isQuietNaNB, UInt<1>("h00")) node isSigNaNB = and(isNaNB, T_68) node isZeroC = eq(io.fromPreMul.highExpC, UInt<1>("h00")) node T_72 = bits(io.fromPreMul.highExpC, 2, 1) node isSpecialC = eq(T_72, UInt<2>("h03")) - node T_75 = bit(io.fromPreMul.highExpC, 0) + node T_75 = bits(io.fromPreMul.highExpC, 0, 0) node T_77 = eq(T_75, UInt<1>("h00")) node isInfC = and(isSpecialC, T_77) - node T_79 = bit(io.fromPreMul.highExpC, 0) + node T_79 = bits(io.fromPreMul.highExpC, 0, 0) node isNaNC = and(isSpecialC, T_79) node T_82 = eq(io.fromPreMul.isNaN_isQuietNaNC, UInt<1>("h00")) node isSigNaNC = and(isNaNC, T_82) @@ -35166,808 +27323,806 @@ circuit Top : node roundingMode_max = eq(io.fromPreMul.roundingMode, UInt<2>("h03")) node signZeroNotEqOpSigns = mux(roundingMode_min, UInt<1>("h01"), UInt<1>("h00")) node doSubMags = xor(io.fromPreMul.signProd, io.fromPreMul.opSignC) - node T_92 = bit(io.mulAddResult, 106) - node T_94 = addw(io.fromPreMul.highAlignedNegSigC, UInt<1>("h01")) - node T_95 = mux(T_92, T_94, io.fromPreMul.highAlignedNegSigC) - node T_96 = bits(io.mulAddResult, 105, 0) - node T_97 = cat(T_96, io.fromPreMul.bit0AlignedNegSigC) - node sigSum = cat(T_95, T_97) - node T_100 = bits(sigSum, 108, 1) - node T_101 = xor(UInt<108>("h00"), T_100) - node T_102 = or(UInt<108>("h00"), T_100) - node T_103 = shl(T_102, 1) - node T_104 = xor(T_101, T_103) - node T_106 = bits(T_104, 107, 0) - node T_107 = bit(T_106, 107) - node T_109 = bit(T_106, 106) - node T_111 = bit(T_106, 105) - node T_113 = bit(T_106, 104) - node T_115 = bit(T_106, 103) - node T_117 = bit(T_106, 102) - node T_119 = bit(T_106, 101) - node T_121 = bit(T_106, 100) - node T_123 = bit(T_106, 99) - node T_125 = bit(T_106, 98) - node T_127 = bit(T_106, 97) - node T_129 = bit(T_106, 96) - node T_131 = bit(T_106, 95) - node T_133 = bit(T_106, 94) - node T_135 = bit(T_106, 93) - node T_137 = bit(T_106, 92) - node T_139 = bit(T_106, 91) - node T_141 = bit(T_106, 90) - node T_143 = bit(T_106, 89) - node T_145 = bit(T_106, 88) - node T_147 = bit(T_106, 87) - node T_149 = bit(T_106, 86) - node T_151 = bit(T_106, 85) - node T_153 = bit(T_106, 84) - node T_155 = bit(T_106, 83) - node T_157 = bit(T_106, 82) - node T_159 = bit(T_106, 81) - node T_161 = bit(T_106, 80) - node T_163 = bit(T_106, 79) - node T_165 = bit(T_106, 78) - node T_167 = bit(T_106, 77) - node T_169 = bit(T_106, 76) - node T_171 = bit(T_106, 75) - node T_173 = bit(T_106, 74) - node T_175 = bit(T_106, 73) - node T_177 = bit(T_106, 72) - node T_179 = bit(T_106, 71) - node T_181 = bit(T_106, 70) - node T_183 = bit(T_106, 69) - node T_185 = bit(T_106, 68) - node T_187 = bit(T_106, 67) - node T_189 = bit(T_106, 66) - node T_191 = bit(T_106, 65) - node T_193 = bit(T_106, 64) - node T_195 = bit(T_106, 63) - node T_197 = bit(T_106, 62) - node T_199 = bit(T_106, 61) - node T_201 = bit(T_106, 60) - node T_203 = bit(T_106, 59) - node T_205 = bit(T_106, 58) - node T_207 = bit(T_106, 57) - node T_209 = bit(T_106, 56) - node T_211 = bit(T_106, 55) - node T_213 = bit(T_106, 54) - node T_215 = bit(T_106, 53) - node T_217 = bit(T_106, 52) - node T_219 = bit(T_106, 51) - node T_221 = bit(T_106, 50) - node T_223 = bit(T_106, 49) - node T_225 = bit(T_106, 48) - node T_227 = bit(T_106, 47) - node T_229 = bit(T_106, 46) - node T_231 = bit(T_106, 45) - node T_233 = bit(T_106, 44) - node T_235 = bit(T_106, 43) - node T_237 = bit(T_106, 42) - node T_239 = bit(T_106, 41) - node T_241 = bit(T_106, 40) - node T_243 = bit(T_106, 39) - node T_245 = bit(T_106, 38) - node T_247 = bit(T_106, 37) - node T_249 = bit(T_106, 36) - node T_251 = bit(T_106, 35) - node T_253 = bit(T_106, 34) - node T_255 = bit(T_106, 33) - node T_257 = bit(T_106, 32) - node T_259 = bit(T_106, 31) - node T_261 = bit(T_106, 30) - node T_263 = bit(T_106, 29) - node T_265 = bit(T_106, 28) - node T_267 = bit(T_106, 27) - node T_269 = bit(T_106, 26) - node T_271 = bit(T_106, 25) - node T_273 = bit(T_106, 24) - node T_275 = bit(T_106, 23) - node T_277 = bit(T_106, 22) - node T_279 = bit(T_106, 21) - node T_281 = bit(T_106, 20) - node T_283 = bit(T_106, 19) - node T_285 = bit(T_106, 18) - node T_287 = bit(T_106, 17) - node T_289 = bit(T_106, 16) - node T_291 = bit(T_106, 15) - node T_293 = bit(T_106, 14) - node T_295 = bit(T_106, 13) - node T_297 = bit(T_106, 12) - node T_299 = bit(T_106, 11) - node T_301 = bit(T_106, 10) - node T_303 = bit(T_106, 9) - node T_305 = bit(T_106, 8) - node T_307 = bit(T_106, 7) - node T_309 = bit(T_106, 6) - node T_311 = bit(T_106, 5) - node T_313 = bit(T_106, 4) - node T_315 = bit(T_106, 3) - node T_317 = bit(T_106, 2) - node T_319 = bit(T_106, 1) - node T_320 = shl(T_319, 0) - node T_321 = mux(T_317, UInt<2>("h02"), T_320) - node T_322 = mux(T_315, UInt<2>("h03"), T_321) - node T_323 = mux(T_313, UInt<3>("h04"), T_322) - node T_324 = mux(T_311, UInt<3>("h05"), T_323) - node T_325 = mux(T_309, UInt<3>("h06"), T_324) - node T_326 = mux(T_307, UInt<3>("h07"), T_325) - node T_327 = mux(T_305, UInt<4>("h08"), T_326) - node T_328 = mux(T_303, UInt<4>("h09"), T_327) - node T_329 = mux(T_301, UInt<4>("h0a"), T_328) - node T_330 = mux(T_299, UInt<4>("h0b"), T_329) - node T_331 = mux(T_297, UInt<4>("h0c"), T_330) - node T_332 = mux(T_295, UInt<4>("h0d"), T_331) - node T_333 = mux(T_293, UInt<4>("h0e"), T_332) - node T_334 = mux(T_291, UInt<4>("h0f"), T_333) - node T_335 = mux(T_289, UInt<5>("h010"), T_334) - node T_336 = mux(T_287, UInt<5>("h011"), T_335) - node T_337 = mux(T_285, UInt<5>("h012"), T_336) - node T_338 = mux(T_283, UInt<5>("h013"), T_337) - node T_339 = mux(T_281, UInt<5>("h014"), T_338) - node T_340 = mux(T_279, UInt<5>("h015"), T_339) - node T_341 = mux(T_277, UInt<5>("h016"), T_340) - node T_342 = mux(T_275, UInt<5>("h017"), T_341) - node T_343 = mux(T_273, UInt<5>("h018"), T_342) - node T_344 = mux(T_271, UInt<5>("h019"), T_343) - node T_345 = mux(T_269, UInt<5>("h01a"), T_344) - node T_346 = mux(T_267, UInt<5>("h01b"), T_345) - node T_347 = mux(T_265, UInt<5>("h01c"), T_346) - node T_348 = mux(T_263, UInt<5>("h01d"), T_347) - node T_349 = mux(T_261, UInt<5>("h01e"), T_348) - node T_350 = mux(T_259, UInt<5>("h01f"), T_349) - node T_351 = mux(T_257, UInt<6>("h020"), T_350) - node T_352 = mux(T_255, UInt<6>("h021"), T_351) - node T_353 = mux(T_253, UInt<6>("h022"), T_352) - node T_354 = mux(T_251, UInt<6>("h023"), T_353) - node T_355 = mux(T_249, UInt<6>("h024"), T_354) - node T_356 = mux(T_247, UInt<6>("h025"), T_355) - node T_357 = mux(T_245, UInt<6>("h026"), T_356) - node T_358 = mux(T_243, UInt<6>("h027"), T_357) - node T_359 = mux(T_241, UInt<6>("h028"), T_358) - node T_360 = mux(T_239, UInt<6>("h029"), T_359) - node T_361 = mux(T_237, UInt<6>("h02a"), T_360) - node T_362 = mux(T_235, UInt<6>("h02b"), T_361) - node T_363 = mux(T_233, UInt<6>("h02c"), T_362) - node T_364 = mux(T_231, UInt<6>("h02d"), T_363) - node T_365 = mux(T_229, UInt<6>("h02e"), T_364) - node T_366 = mux(T_227, UInt<6>("h02f"), T_365) - node T_367 = mux(T_225, UInt<6>("h030"), T_366) - node T_368 = mux(T_223, UInt<6>("h031"), T_367) - node T_369 = mux(T_221, UInt<6>("h032"), T_368) - node T_370 = mux(T_219, UInt<6>("h033"), T_369) - node T_371 = mux(T_217, UInt<6>("h034"), T_370) - node T_372 = mux(T_215, UInt<6>("h035"), T_371) - node T_373 = mux(T_213, UInt<6>("h036"), T_372) - node T_374 = mux(T_211, UInt<6>("h037"), T_373) - node T_375 = mux(T_209, UInt<6>("h038"), T_374) - node T_376 = mux(T_207, UInt<6>("h039"), T_375) - node T_377 = mux(T_205, UInt<6>("h03a"), T_376) - node T_378 = mux(T_203, UInt<6>("h03b"), T_377) - node T_379 = mux(T_201, UInt<6>("h03c"), T_378) - node T_380 = mux(T_199, UInt<6>("h03d"), T_379) - node T_381 = mux(T_197, UInt<6>("h03e"), T_380) - node T_382 = mux(T_195, UInt<6>("h03f"), T_381) - node T_383 = mux(T_193, UInt<7>("h040"), T_382) - node T_384 = mux(T_191, UInt<7>("h041"), T_383) - node T_385 = mux(T_189, UInt<7>("h042"), T_384) - node T_386 = mux(T_187, UInt<7>("h043"), T_385) - node T_387 = mux(T_185, UInt<7>("h044"), T_386) - node T_388 = mux(T_183, UInt<7>("h045"), T_387) - node T_389 = mux(T_181, UInt<7>("h046"), T_388) - node T_390 = mux(T_179, UInt<7>("h047"), T_389) - node T_391 = mux(T_177, UInt<7>("h048"), T_390) - node T_392 = mux(T_175, UInt<7>("h049"), T_391) - node T_393 = mux(T_173, UInt<7>("h04a"), T_392) - node T_394 = mux(T_171, UInt<7>("h04b"), T_393) - node T_395 = mux(T_169, UInt<7>("h04c"), T_394) - node T_396 = mux(T_167, UInt<7>("h04d"), T_395) - node T_397 = mux(T_165, UInt<7>("h04e"), T_396) - node T_398 = mux(T_163, UInt<7>("h04f"), T_397) - node T_399 = mux(T_161, UInt<7>("h050"), T_398) - node T_400 = mux(T_159, UInt<7>("h051"), T_399) - node T_401 = mux(T_157, UInt<7>("h052"), T_400) - node T_402 = mux(T_155, UInt<7>("h053"), T_401) - node T_403 = mux(T_153, UInt<7>("h054"), T_402) - node T_404 = mux(T_151, UInt<7>("h055"), T_403) - node T_405 = mux(T_149, UInt<7>("h056"), T_404) - node T_406 = mux(T_147, UInt<7>("h057"), T_405) - node T_407 = mux(T_145, UInt<7>("h058"), T_406) - node T_408 = mux(T_143, UInt<7>("h059"), T_407) - node T_409 = mux(T_141, UInt<7>("h05a"), T_408) - node T_410 = mux(T_139, UInt<7>("h05b"), T_409) - node T_411 = mux(T_137, UInt<7>("h05c"), T_410) - node T_412 = mux(T_135, UInt<7>("h05d"), T_411) - node T_413 = mux(T_133, UInt<7>("h05e"), T_412) - node T_414 = mux(T_131, UInt<7>("h05f"), T_413) - node T_415 = mux(T_129, UInt<7>("h060"), T_414) - node T_416 = mux(T_127, UInt<7>("h061"), T_415) - node T_417 = mux(T_125, UInt<7>("h062"), T_416) - node T_418 = mux(T_123, UInt<7>("h063"), T_417) - node T_419 = mux(T_121, UInt<7>("h064"), T_418) - node T_420 = mux(T_119, UInt<7>("h065"), T_419) - node T_421 = mux(T_117, UInt<7>("h066"), T_420) - node T_422 = mux(T_115, UInt<7>("h067"), T_421) - node T_423 = mux(T_113, UInt<7>("h068"), T_422) - node T_424 = mux(T_111, UInt<7>("h069"), T_423) - node T_425 = mux(T_109, UInt<7>("h06a"), T_424) - node T_426 = mux(T_107, UInt<7>("h06b"), T_425) - node estNormPos_dist = subw(UInt<8>("h0a0"), T_426) - node T_428 = bits(sigSum, 75, 44) - node T_430 = neq(T_428, UInt<1>("h00")) - node T_431 = bits(sigSum, 43, 0) - node T_433 = neq(T_431, UInt<1>("h00")) - node firstReduceSigSum = cat(T_430, T_433) + node T_92 = bits(io.mulAddResult, 106, 106) + node T_94 = add(io.fromPreMul.highAlignedNegSigC, UInt<1>("h01")) + node T_95 = tail(T_94, 1) + node T_96 = mux(T_92, T_95, io.fromPreMul.highAlignedNegSigC) + node T_97 = bits(io.mulAddResult, 105, 0) + node T_98 = cat(T_97, io.fromPreMul.bit0AlignedNegSigC) + node sigSum = cat(T_96, T_98) + node T_101 = bits(sigSum, 108, 1) + node T_102 = xor(UInt<108>("h00"), T_101) + node T_103 = or(UInt<108>("h00"), T_101) + node T_104 = shl(T_103, 1) + node T_105 = xor(T_102, T_104) + node T_107 = bits(T_105, 107, 0) + node T_108 = bits(T_107, 107, 107) + node T_110 = bits(T_107, 106, 106) + node T_112 = bits(T_107, 105, 105) + node T_114 = bits(T_107, 104, 104) + node T_116 = bits(T_107, 103, 103) + node T_118 = bits(T_107, 102, 102) + node T_120 = bits(T_107, 101, 101) + node T_122 = bits(T_107, 100, 100) + node T_124 = bits(T_107, 99, 99) + node T_126 = bits(T_107, 98, 98) + node T_128 = bits(T_107, 97, 97) + node T_130 = bits(T_107, 96, 96) + node T_132 = bits(T_107, 95, 95) + node T_134 = bits(T_107, 94, 94) + node T_136 = bits(T_107, 93, 93) + node T_138 = bits(T_107, 92, 92) + node T_140 = bits(T_107, 91, 91) + node T_142 = bits(T_107, 90, 90) + node T_144 = bits(T_107, 89, 89) + node T_146 = bits(T_107, 88, 88) + node T_148 = bits(T_107, 87, 87) + node T_150 = bits(T_107, 86, 86) + node T_152 = bits(T_107, 85, 85) + node T_154 = bits(T_107, 84, 84) + node T_156 = bits(T_107, 83, 83) + node T_158 = bits(T_107, 82, 82) + node T_160 = bits(T_107, 81, 81) + node T_162 = bits(T_107, 80, 80) + node T_164 = bits(T_107, 79, 79) + node T_166 = bits(T_107, 78, 78) + node T_168 = bits(T_107, 77, 77) + node T_170 = bits(T_107, 76, 76) + node T_172 = bits(T_107, 75, 75) + node T_174 = bits(T_107, 74, 74) + node T_176 = bits(T_107, 73, 73) + node T_178 = bits(T_107, 72, 72) + node T_180 = bits(T_107, 71, 71) + node T_182 = bits(T_107, 70, 70) + node T_184 = bits(T_107, 69, 69) + node T_186 = bits(T_107, 68, 68) + node T_188 = bits(T_107, 67, 67) + node T_190 = bits(T_107, 66, 66) + node T_192 = bits(T_107, 65, 65) + node T_194 = bits(T_107, 64, 64) + node T_196 = bits(T_107, 63, 63) + node T_198 = bits(T_107, 62, 62) + node T_200 = bits(T_107, 61, 61) + node T_202 = bits(T_107, 60, 60) + node T_204 = bits(T_107, 59, 59) + node T_206 = bits(T_107, 58, 58) + node T_208 = bits(T_107, 57, 57) + node T_210 = bits(T_107, 56, 56) + node T_212 = bits(T_107, 55, 55) + node T_214 = bits(T_107, 54, 54) + node T_216 = bits(T_107, 53, 53) + node T_218 = bits(T_107, 52, 52) + node T_220 = bits(T_107, 51, 51) + node T_222 = bits(T_107, 50, 50) + node T_224 = bits(T_107, 49, 49) + node T_226 = bits(T_107, 48, 48) + node T_228 = bits(T_107, 47, 47) + node T_230 = bits(T_107, 46, 46) + node T_232 = bits(T_107, 45, 45) + node T_234 = bits(T_107, 44, 44) + node T_236 = bits(T_107, 43, 43) + node T_238 = bits(T_107, 42, 42) + node T_240 = bits(T_107, 41, 41) + node T_242 = bits(T_107, 40, 40) + node T_244 = bits(T_107, 39, 39) + node T_246 = bits(T_107, 38, 38) + node T_248 = bits(T_107, 37, 37) + node T_250 = bits(T_107, 36, 36) + node T_252 = bits(T_107, 35, 35) + node T_254 = bits(T_107, 34, 34) + node T_256 = bits(T_107, 33, 33) + node T_258 = bits(T_107, 32, 32) + node T_260 = bits(T_107, 31, 31) + node T_262 = bits(T_107, 30, 30) + node T_264 = bits(T_107, 29, 29) + node T_266 = bits(T_107, 28, 28) + node T_268 = bits(T_107, 27, 27) + node T_270 = bits(T_107, 26, 26) + node T_272 = bits(T_107, 25, 25) + node T_274 = bits(T_107, 24, 24) + node T_276 = bits(T_107, 23, 23) + node T_278 = bits(T_107, 22, 22) + node T_280 = bits(T_107, 21, 21) + node T_282 = bits(T_107, 20, 20) + node T_284 = bits(T_107, 19, 19) + node T_286 = bits(T_107, 18, 18) + node T_288 = bits(T_107, 17, 17) + node T_290 = bits(T_107, 16, 16) + node T_292 = bits(T_107, 15, 15) + node T_294 = bits(T_107, 14, 14) + node T_296 = bits(T_107, 13, 13) + node T_298 = bits(T_107, 12, 12) + node T_300 = bits(T_107, 11, 11) + node T_302 = bits(T_107, 10, 10) + node T_304 = bits(T_107, 9, 9) + node T_306 = bits(T_107, 8, 8) + node T_308 = bits(T_107, 7, 7) + node T_310 = bits(T_107, 6, 6) + node T_312 = bits(T_107, 5, 5) + node T_314 = bits(T_107, 4, 4) + node T_316 = bits(T_107, 3, 3) + node T_318 = bits(T_107, 2, 2) + node T_320 = bits(T_107, 1, 1) + node T_321 = shl(T_320, 0) + node T_322 = mux(T_318, UInt<2>("h02"), T_321) + node T_323 = mux(T_316, UInt<2>("h03"), T_322) + node T_324 = mux(T_314, UInt<3>("h04"), T_323) + node T_325 = mux(T_312, UInt<3>("h05"), T_324) + node T_326 = mux(T_310, UInt<3>("h06"), T_325) + node T_327 = mux(T_308, UInt<3>("h07"), T_326) + node T_328 = mux(T_306, UInt<4>("h08"), T_327) + node T_329 = mux(T_304, UInt<4>("h09"), T_328) + node T_330 = mux(T_302, UInt<4>("h0a"), T_329) + node T_331 = mux(T_300, UInt<4>("h0b"), T_330) + node T_332 = mux(T_298, UInt<4>("h0c"), T_331) + node T_333 = mux(T_296, UInt<4>("h0d"), T_332) + node T_334 = mux(T_294, UInt<4>("h0e"), T_333) + node T_335 = mux(T_292, UInt<4>("h0f"), T_334) + node T_336 = mux(T_290, UInt<5>("h010"), T_335) + node T_337 = mux(T_288, UInt<5>("h011"), T_336) + node T_338 = mux(T_286, UInt<5>("h012"), T_337) + node T_339 = mux(T_284, UInt<5>("h013"), T_338) + node T_340 = mux(T_282, UInt<5>("h014"), T_339) + node T_341 = mux(T_280, UInt<5>("h015"), T_340) + node T_342 = mux(T_278, UInt<5>("h016"), T_341) + node T_343 = mux(T_276, UInt<5>("h017"), T_342) + node T_344 = mux(T_274, UInt<5>("h018"), T_343) + node T_345 = mux(T_272, UInt<5>("h019"), T_344) + node T_346 = mux(T_270, UInt<5>("h01a"), T_345) + node T_347 = mux(T_268, UInt<5>("h01b"), T_346) + node T_348 = mux(T_266, UInt<5>("h01c"), T_347) + node T_349 = mux(T_264, UInt<5>("h01d"), T_348) + node T_350 = mux(T_262, UInt<5>("h01e"), T_349) + node T_351 = mux(T_260, UInt<5>("h01f"), T_350) + node T_352 = mux(T_258, UInt<6>("h020"), T_351) + node T_353 = mux(T_256, UInt<6>("h021"), T_352) + node T_354 = mux(T_254, UInt<6>("h022"), T_353) + node T_355 = mux(T_252, UInt<6>("h023"), T_354) + node T_356 = mux(T_250, UInt<6>("h024"), T_355) + node T_357 = mux(T_248, UInt<6>("h025"), T_356) + node T_358 = mux(T_246, UInt<6>("h026"), T_357) + node T_359 = mux(T_244, UInt<6>("h027"), T_358) + node T_360 = mux(T_242, UInt<6>("h028"), T_359) + node T_361 = mux(T_240, UInt<6>("h029"), T_360) + node T_362 = mux(T_238, UInt<6>("h02a"), T_361) + node T_363 = mux(T_236, UInt<6>("h02b"), T_362) + node T_364 = mux(T_234, UInt<6>("h02c"), T_363) + node T_365 = mux(T_232, UInt<6>("h02d"), T_364) + node T_366 = mux(T_230, UInt<6>("h02e"), T_365) + node T_367 = mux(T_228, UInt<6>("h02f"), T_366) + node T_368 = mux(T_226, UInt<6>("h030"), T_367) + node T_369 = mux(T_224, UInt<6>("h031"), T_368) + node T_370 = mux(T_222, UInt<6>("h032"), T_369) + node T_371 = mux(T_220, UInt<6>("h033"), T_370) + node T_372 = mux(T_218, UInt<6>("h034"), T_371) + node T_373 = mux(T_216, UInt<6>("h035"), T_372) + node T_374 = mux(T_214, UInt<6>("h036"), T_373) + node T_375 = mux(T_212, UInt<6>("h037"), T_374) + node T_376 = mux(T_210, UInt<6>("h038"), T_375) + node T_377 = mux(T_208, UInt<6>("h039"), T_376) + node T_378 = mux(T_206, UInt<6>("h03a"), T_377) + node T_379 = mux(T_204, UInt<6>("h03b"), T_378) + node T_380 = mux(T_202, UInt<6>("h03c"), T_379) + node T_381 = mux(T_200, UInt<6>("h03d"), T_380) + node T_382 = mux(T_198, UInt<6>("h03e"), T_381) + node T_383 = mux(T_196, UInt<6>("h03f"), T_382) + node T_384 = mux(T_194, UInt<7>("h040"), T_383) + node T_385 = mux(T_192, UInt<7>("h041"), T_384) + node T_386 = mux(T_190, UInt<7>("h042"), T_385) + node T_387 = mux(T_188, UInt<7>("h043"), T_386) + node T_388 = mux(T_186, UInt<7>("h044"), T_387) + node T_389 = mux(T_184, UInt<7>("h045"), T_388) + node T_390 = mux(T_182, UInt<7>("h046"), T_389) + node T_391 = mux(T_180, UInt<7>("h047"), T_390) + node T_392 = mux(T_178, UInt<7>("h048"), T_391) + node T_393 = mux(T_176, UInt<7>("h049"), T_392) + node T_394 = mux(T_174, UInt<7>("h04a"), T_393) + node T_395 = mux(T_172, UInt<7>("h04b"), T_394) + node T_396 = mux(T_170, UInt<7>("h04c"), T_395) + node T_397 = mux(T_168, UInt<7>("h04d"), T_396) + node T_398 = mux(T_166, UInt<7>("h04e"), T_397) + node T_399 = mux(T_164, UInt<7>("h04f"), T_398) + node T_400 = mux(T_162, UInt<7>("h050"), T_399) + node T_401 = mux(T_160, UInt<7>("h051"), T_400) + node T_402 = mux(T_158, UInt<7>("h052"), T_401) + node T_403 = mux(T_156, UInt<7>("h053"), T_402) + node T_404 = mux(T_154, UInt<7>("h054"), T_403) + node T_405 = mux(T_152, UInt<7>("h055"), T_404) + node T_406 = mux(T_150, UInt<7>("h056"), T_405) + node T_407 = mux(T_148, UInt<7>("h057"), T_406) + node T_408 = mux(T_146, UInt<7>("h058"), T_407) + node T_409 = mux(T_144, UInt<7>("h059"), T_408) + node T_410 = mux(T_142, UInt<7>("h05a"), T_409) + node T_411 = mux(T_140, UInt<7>("h05b"), T_410) + node T_412 = mux(T_138, UInt<7>("h05c"), T_411) + node T_413 = mux(T_136, UInt<7>("h05d"), T_412) + node T_414 = mux(T_134, UInt<7>("h05e"), T_413) + node T_415 = mux(T_132, UInt<7>("h05f"), T_414) + node T_416 = mux(T_130, UInt<7>("h060"), T_415) + node T_417 = mux(T_128, UInt<7>("h061"), T_416) + node T_418 = mux(T_126, UInt<7>("h062"), T_417) + node T_419 = mux(T_124, UInt<7>("h063"), T_418) + node T_420 = mux(T_122, UInt<7>("h064"), T_419) + node T_421 = mux(T_120, UInt<7>("h065"), T_420) + node T_422 = mux(T_118, UInt<7>("h066"), T_421) + node T_423 = mux(T_116, UInt<7>("h067"), T_422) + node T_424 = mux(T_114, UInt<7>("h068"), T_423) + node T_425 = mux(T_112, UInt<7>("h069"), T_424) + node T_426 = mux(T_110, UInt<7>("h06a"), T_425) + node T_427 = mux(T_108, UInt<7>("h06b"), T_426) + node T_428 = sub(UInt<8>("h0a0"), T_427) + node estNormPos_dist = tail(T_428, 1) + node T_430 = bits(sigSum, 75, 44) + node T_432 = neq(T_430, UInt<1>("h00")) + node T_433 = bits(sigSum, 43, 0) + node T_435 = neq(T_433, UInt<1>("h00")) + node firstReduceSigSum = cat(T_432, T_435) node notSigSum = not(sigSum) - node T_436 = bits(notSigSum, 75, 44) - node T_438 = neq(T_436, UInt<1>("h00")) - node T_439 = bits(notSigSum, 43, 0) - node T_441 = neq(T_439, UInt<1>("h00")) - node firstReduceNotSigSum = cat(T_438, T_441) - node T_443 = or(io.fromPreMul.CAlignDist_0, doSubMags) - node T_445 = subw(io.fromPreMul.CAlignDist, UInt<1>("h01")) - node T_446 = bits(T_445, 5, 0) - node CDom_estNormDist = mux(T_443, io.fromPreMul.CAlignDist, T_446) - node T_448 = not(doSubMags) - node T_449 = bit(CDom_estNormDist, 5) - node T_450 = not(T_449) - node T_451 = and(T_448, T_450) - node T_452 = asSInt(T_451) - node T_453 = bits(sigSum, 161, 76) - node T_455 = neq(firstReduceSigSum, UInt<1>("h00")) - node T_456 = cat(T_453, T_455) - node T_457 = asSInt(T_456) - node T_458 = and(T_452, T_457) - node T_459 = not(doSubMags) - node T_460 = bit(CDom_estNormDist, 5) - node T_461 = and(T_459, T_460) + node T_438 = bits(notSigSum, 75, 44) + node T_440 = neq(T_438, UInt<1>("h00")) + node T_441 = bits(notSigSum, 43, 0) + node T_443 = neq(T_441, UInt<1>("h00")) + node firstReduceNotSigSum = cat(T_440, T_443) + node T_445 = or(io.fromPreMul.CAlignDist_0, doSubMags) + node T_447 = sub(io.fromPreMul.CAlignDist, UInt<1>("h01")) + node T_448 = tail(T_447, 1) + node T_449 = bits(T_448, 5, 0) + node CDom_estNormDist = mux(T_445, io.fromPreMul.CAlignDist, T_449) + node T_451 = not(doSubMags) + node T_452 = bits(CDom_estNormDist, 5, 5) + node T_453 = not(T_452) + node T_454 = and(T_451, T_453) + node T_455 = asSInt(T_454) + node T_456 = bits(sigSum, 161, 76) + node T_458 = neq(firstReduceSigSum, UInt<1>("h00")) + node T_459 = cat(T_456, T_458) + node T_460 = asSInt(T_459) + node T_461 = and(T_455, T_460) node T_462 = asSInt(T_461) - node T_463 = bits(sigSum, 129, 44) - node T_464 = bit(firstReduceSigSum, 0) - node T_465 = cat(T_463, T_464) + node T_463 = not(doSubMags) + node T_464 = bits(CDom_estNormDist, 5, 5) + node T_465 = and(T_463, T_464) node T_466 = asSInt(T_465) - node T_467 = and(T_462, T_466) - node T_468 = or(T_458, T_467) - node T_469 = bit(CDom_estNormDist, 5) - node T_470 = not(T_469) - node T_471 = and(doSubMags, T_470) + node T_467 = bits(sigSum, 129, 44) + node T_468 = bits(firstReduceSigSum, 0, 0) + node T_469 = cat(T_467, T_468) + node T_470 = asSInt(T_469) + node T_471 = and(T_466, T_470) node T_472 = asSInt(T_471) - node T_473 = bits(notSigSum, 161, 76) - node T_475 = neq(firstReduceNotSigSum, UInt<1>("h00")) - node T_476 = cat(T_473, T_475) - node T_477 = asSInt(T_476) - node T_478 = and(T_472, T_477) - node T_479 = or(T_468, T_478) - node T_480 = bit(CDom_estNormDist, 5) - node T_481 = and(doSubMags, T_480) - node T_482 = asSInt(T_481) - node T_483 = bits(notSigSum, 129, 44) - node T_484 = bit(firstReduceNotSigSum, 0) - node T_485 = cat(T_483, T_484) - node T_486 = asSInt(T_485) - node T_487 = and(T_482, T_486) - node T_488 = or(T_479, T_487) - node CDom_firstNormAbsSigSum = asUInt(T_488) - node T_490 = bits(sigSum, 108, 44) - node T_491 = bit(firstReduceNotSigSum, 0) - node T_492 = not(T_491) - node T_493 = bit(firstReduceSigSum, 0) - node T_494 = mux(doSubMags, T_492, T_493) - node T_495 = cat(T_490, T_494) - node T_496 = bits(sigSum, 97, 1) - node T_497 = bit(estNormPos_dist, 4) - node T_498 = bits(sigSum, 1, 1) - node T_500 = subw(UInt<86>("h00"), doSubMags) - node T_501 = cat(T_498, T_500) - node T_502 = mux(T_497, T_495, T_501) - node T_503 = bits(sigSum, 97, 12) - node T_504 = bits(notSigSum, 11, 1) - node T_506 = eq(T_504, UInt<1>("h00")) - node T_507 = bits(sigSum, 11, 1) - node T_509 = neq(T_507, UInt<1>("h00")) - node T_510 = mux(doSubMags, T_506, T_509) - node T_511 = cat(T_503, T_510) - node T_512 = bit(estNormPos_dist, 6) - node T_513 = bit(estNormPos_dist, 5) - node T_514 = bits(sigSum, 65, 1) - node T_516 = subw(UInt<22>("h00"), doSubMags) - node T_517 = cat(T_514, T_516) - node T_518 = mux(T_513, T_517, T_511) - node T_519 = bit(estNormPos_dist, 5) - node T_520 = bits(sigSum, 33, 1) - node T_522 = subw(UInt<54>("h00"), doSubMags) - node T_523 = cat(T_520, T_522) - node T_524 = mux(T_519, T_502, T_523) - node notCDom_pos_firstNormAbsSigSum = mux(T_512, T_518, T_524) - node T_526 = bits(notSigSum, 107, 44) - node T_527 = bit(firstReduceNotSigSum, 0) - node T_528 = cat(T_526, T_527) - node T_529 = bits(notSigSum, 97, 1) - node T_530 = bit(estNormPos_dist, 4) - node T_531 = bits(notSigSum, 2, 1) - node T_533 = dshl(T_531, UInt<7>("h056")) - node T_534 = mux(T_530, T_528, T_533) - node T_535 = bits(notSigSum, 98, 12) - node T_536 = bits(notSigSum, 11, 1) - node T_538 = neq(T_536, UInt<1>("h00")) - node T_539 = cat(T_535, T_538) - node T_540 = bit(estNormPos_dist, 6) - node T_541 = bit(estNormPos_dist, 5) - node T_542 = bits(notSigSum, 66, 1) - node T_544 = dshl(T_542, UInt<5>("h016")) - node T_545 = mux(T_541, T_544, T_539) - node T_546 = bit(estNormPos_dist, 5) - node T_547 = bits(notSigSum, 34, 1) - node T_549 = dshl(T_547, UInt<6>("h036")) - node T_550 = mux(T_546, T_534, T_549) - node notCDom_neg_cFirstNormAbsSigSum = mux(T_540, T_545, T_550) - node notCDom_signSigSum = bit(sigSum, 109) - node T_553 = not(isZeroC) - node T_554 = and(doSubMags, T_553) - node doNegSignSum = mux(io.fromPreMul.isCDominant, T_554, notCDom_signSigSum) - node T_556 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) - node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, T_556) - node T_558 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) - node T_559 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) - node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_558, T_559) - node T_561 = not(io.fromPreMul.isCDominant) - node T_562 = not(notCDom_signSigSum) - node T_563 = and(T_561, T_562) - node doIncrSig = and(T_563, doSubMags) + node T_473 = or(T_462, T_472) + node T_474 = asSInt(T_473) + node T_475 = bits(CDom_estNormDist, 5, 5) + node T_476 = not(T_475) + node T_477 = and(doSubMags, T_476) + node T_478 = asSInt(T_477) + node T_479 = bits(notSigSum, 161, 76) + node T_481 = neq(firstReduceNotSigSum, UInt<1>("h00")) + node T_482 = cat(T_479, T_481) + node T_483 = asSInt(T_482) + node T_484 = and(T_478, T_483) + node T_485 = asSInt(T_484) + node T_486 = or(T_474, T_485) + node T_487 = asSInt(T_486) + node T_488 = bits(CDom_estNormDist, 5, 5) + node T_489 = and(doSubMags, T_488) + node T_490 = asSInt(T_489) + node T_491 = bits(notSigSum, 129, 44) + node T_492 = bits(firstReduceNotSigSum, 0, 0) + node T_493 = cat(T_491, T_492) + node T_494 = asSInt(T_493) + node T_495 = and(T_490, T_494) + node T_496 = asSInt(T_495) + node T_497 = or(T_487, T_496) + node T_498 = asSInt(T_497) + node CDom_firstNormAbsSigSum = asUInt(T_498) + node T_500 = bits(sigSum, 108, 44) + node T_501 = bits(firstReduceNotSigSum, 0, 0) + node T_502 = not(T_501) + node T_503 = bits(firstReduceSigSum, 0, 0) + node T_504 = mux(doSubMags, T_502, T_503) + node T_505 = cat(T_500, T_504) + node T_506 = bits(sigSum, 97, 1) + node T_507 = bits(estNormPos_dist, 4, 4) + node T_508 = bits(sigSum, 1, 1) + node T_510 = sub(UInt<86>("h00"), doSubMags) + node T_511 = tail(T_510, 1) + node T_512 = cat(T_508, T_511) + node T_513 = mux(T_507, T_505, T_512) + node T_514 = bits(sigSum, 97, 12) + node T_515 = bits(notSigSum, 11, 1) + node T_517 = eq(T_515, UInt<1>("h00")) + node T_518 = bits(sigSum, 11, 1) + node T_520 = neq(T_518, UInt<1>("h00")) + node T_521 = mux(doSubMags, T_517, T_520) + node T_522 = cat(T_514, T_521) + node T_523 = bits(estNormPos_dist, 6, 6) + node T_524 = bits(estNormPos_dist, 5, 5) + node T_525 = bits(sigSum, 65, 1) + node T_527 = sub(UInt<22>("h00"), doSubMags) + node T_528 = tail(T_527, 1) + node T_529 = cat(T_525, T_528) + node T_530 = mux(T_524, T_529, T_522) + node T_531 = bits(estNormPos_dist, 5, 5) + node T_532 = bits(sigSum, 33, 1) + node T_534 = sub(UInt<54>("h00"), doSubMags) + node T_535 = tail(T_534, 1) + node T_536 = cat(T_532, T_535) + node T_537 = mux(T_531, T_513, T_536) + node notCDom_pos_firstNormAbsSigSum = mux(T_523, T_530, T_537) + node T_539 = bits(notSigSum, 107, 44) + node T_540 = bits(firstReduceNotSigSum, 0, 0) + node T_541 = cat(T_539, T_540) + node T_542 = bits(notSigSum, 97, 1) + node T_543 = bits(estNormPos_dist, 4, 4) + node T_544 = bits(notSigSum, 2, 1) + node T_546 = dshl(T_544, UInt<7>("h056")) + node T_547 = mux(T_543, T_541, T_546) + node T_548 = bits(notSigSum, 98, 12) + node T_549 = bits(notSigSum, 11, 1) + node T_551 = neq(T_549, UInt<1>("h00")) + node T_552 = cat(T_548, T_551) + node T_553 = bits(estNormPos_dist, 6, 6) + node T_554 = bits(estNormPos_dist, 5, 5) + node T_555 = bits(notSigSum, 66, 1) + node T_557 = dshl(T_555, UInt<5>("h016")) + node T_558 = mux(T_554, T_557, T_552) + node T_559 = bits(estNormPos_dist, 5, 5) + node T_560 = bits(notSigSum, 34, 1) + node T_562 = dshl(T_560, UInt<6>("h036")) + node T_563 = mux(T_559, T_547, T_562) + node notCDom_neg_cFirstNormAbsSigSum = mux(T_553, T_558, T_563) + node notCDom_signSigSum = bits(sigSum, 109, 109) + node T_566 = not(isZeroC) + node T_567 = and(doSubMags, T_566) + node doNegSignSum = mux(io.fromPreMul.isCDominant, T_567, notCDom_signSigSum) + node T_569 = mux(notCDom_signSigSum, estNormPos_dist, estNormPos_dist) + node estNormDist = mux(io.fromPreMul.isCDominant, CDom_estNormDist, T_569) + node T_571 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_neg_cFirstNormAbsSigSum) + node T_572 = mux(io.fromPreMul.isCDominant, CDom_firstNormAbsSigSum, notCDom_pos_firstNormAbsSigSum) + node cFirstNormAbsSigSum = mux(notCDom_signSigSum, T_571, T_572) + node T_574 = not(io.fromPreMul.isCDominant) + node T_575 = not(notCDom_signSigSum) + node T_576 = and(T_574, T_575) + node doIncrSig = and(T_576, doSubMags) node estNormDist_5 = bits(estNormDist, 4, 0) node normTo2ShiftDist = not(estNormDist_5) - node T_568 = dshr(asSInt(UInt<33>("h0100000000")), normTo2ShiftDist) - node T_569 = bits(T_568, 31, 1) - node T_570 = bits(T_569, 15, 0) - node T_573 = shl(UInt<8>("h0ff"), 8) - node T_574 = xor(UInt<16>("h0ffff"), T_573) - node T_575 = shr(T_570, 8) - node T_576 = and(T_575, T_574) - node T_577 = bits(T_570, 7, 0) - node T_578 = shl(T_577, 8) - node T_579 = not(T_574) - node T_580 = and(T_578, T_579) - node T_581 = or(T_576, T_580) - node T_582 = bits(T_574, 11, 0) - node T_583 = shl(T_582, 4) - node T_584 = xor(T_574, T_583) - node T_585 = shr(T_581, 4) - node T_586 = and(T_585, T_584) - node T_587 = bits(T_581, 11, 0) - node T_588 = shl(T_587, 4) - node T_589 = not(T_584) - node T_590 = and(T_588, T_589) - node T_591 = or(T_586, T_590) - node T_592 = bits(T_584, 13, 0) - node T_593 = shl(T_592, 2) - node T_594 = xor(T_584, T_593) - node T_595 = shr(T_591, 2) - node T_596 = and(T_595, T_594) - node T_597 = bits(T_591, 13, 0) - node T_598 = shl(T_597, 2) - node T_599 = not(T_594) - node T_600 = and(T_598, T_599) - node T_601 = or(T_596, T_600) - node T_602 = bits(T_594, 14, 0) - node T_603 = shl(T_602, 1) - node T_604 = xor(T_594, T_603) - node T_605 = shr(T_601, 1) - node T_606 = and(T_605, T_604) - node T_607 = bits(T_601, 14, 0) - node T_608 = shl(T_607, 1) - node T_609 = not(T_604) - node T_610 = and(T_608, T_609) - node T_611 = or(T_606, T_610) - node T_612 = bits(T_569, 30, 16) - node T_613 = bits(T_612, 7, 0) - node T_616 = shl(UInt<4>("h0f"), 4) - node T_617 = xor(UInt<8>("h0ff"), T_616) - node T_618 = shr(T_613, 4) + node T_581 = dshr(asSInt(UInt<33>("h0100000000")), normTo2ShiftDist) + node T_582 = bits(T_581, 31, 1) + node T_583 = bits(T_582, 15, 0) + node T_586 = shl(UInt<8>("h0ff"), 8) + node T_587 = xor(UInt<16>("h0ffff"), T_586) + node T_588 = shr(T_583, 8) + node T_589 = and(T_588, T_587) + node T_590 = bits(T_583, 7, 0) + node T_591 = shl(T_590, 8) + node T_592 = not(T_587) + node T_593 = and(T_591, T_592) + node T_594 = or(T_589, T_593) + node T_595 = bits(T_587, 11, 0) + node T_596 = shl(T_595, 4) + node T_597 = xor(T_587, T_596) + node T_598 = shr(T_594, 4) + node T_599 = and(T_598, T_597) + node T_600 = bits(T_594, 11, 0) + node T_601 = shl(T_600, 4) + node T_602 = not(T_597) + node T_603 = and(T_601, T_602) + node T_604 = or(T_599, T_603) + node T_605 = bits(T_597, 13, 0) + node T_606 = shl(T_605, 2) + node T_607 = xor(T_597, T_606) + node T_608 = shr(T_604, 2) + node T_609 = and(T_608, T_607) + node T_610 = bits(T_604, 13, 0) + node T_611 = shl(T_610, 2) + node T_612 = not(T_607) + node T_613 = and(T_611, T_612) + node T_614 = or(T_609, T_613) + node T_615 = bits(T_607, 14, 0) + node T_616 = shl(T_615, 1) + node T_617 = xor(T_607, T_616) + node T_618 = shr(T_614, 1) node T_619 = and(T_618, T_617) - node T_620 = bits(T_613, 3, 0) - node T_621 = shl(T_620, 4) + node T_620 = bits(T_614, 14, 0) + node T_621 = shl(T_620, 1) node T_622 = not(T_617) node T_623 = and(T_621, T_622) node T_624 = or(T_619, T_623) - node T_625 = bits(T_617, 5, 0) - node T_626 = shl(T_625, 2) - node T_627 = xor(T_617, T_626) - node T_628 = shr(T_624, 2) - node T_629 = and(T_628, T_627) - node T_630 = bits(T_624, 5, 0) - node T_631 = shl(T_630, 2) - node T_632 = not(T_627) - node T_633 = and(T_631, T_632) - node T_634 = or(T_629, T_633) - node T_635 = bits(T_627, 6, 0) - node T_636 = shl(T_635, 1) - node T_637 = xor(T_627, T_636) - node T_638 = shr(T_634, 1) - node T_639 = and(T_638, T_637) - node T_640 = bits(T_634, 6, 0) - node T_641 = shl(T_640, 1) - node T_642 = not(T_637) - node T_643 = and(T_641, T_642) - node T_644 = or(T_639, T_643) - node T_645 = bits(T_612, 14, 8) - node T_646 = bits(T_645, 3, 0) - node T_647 = bits(T_646, 1, 0) - node T_648 = bits(T_647, 0, 0) - node T_649 = bits(T_647, 1, 1) - node T_650 = cat(T_648, T_649) - node T_651 = bits(T_646, 3, 2) - node T_652 = bits(T_651, 0, 0) - node T_653 = bits(T_651, 1, 1) - node T_654 = cat(T_652, T_653) - node T_655 = cat(T_650, T_654) - node T_656 = bits(T_645, 6, 4) - node T_657 = bits(T_656, 1, 0) - node T_658 = bits(T_657, 0, 0) - node T_659 = bits(T_657, 1, 1) - node T_660 = cat(T_658, T_659) - node T_661 = bits(T_656, 2, 2) - node T_662 = cat(T_660, T_661) - node T_663 = cat(T_655, T_662) - node T_664 = cat(T_644, T_663) - node T_665 = cat(T_611, T_664) - node absSigSumExtraMask = cat(T_665, UInt<1>("h01")) - node T_668 = bits(cFirstNormAbsSigSum, 87, 1) - node T_669 = dshr(T_668, normTo2ShiftDist) - node T_670 = bits(cFirstNormAbsSigSum, 31, 0) - node T_671 = not(T_670) - node T_672 = and(T_671, absSigSumExtraMask) - node T_674 = eq(T_672, UInt<1>("h00")) - node T_675 = bits(cFirstNormAbsSigSum, 31, 0) - node T_676 = and(T_675, absSigSumExtraMask) - node T_678 = neq(T_676, UInt<1>("h00")) - node T_679 = mux(doIncrSig, T_674, T_678) - node T_680 = cat(T_669, T_679) - node sigX3 = bits(T_680, 56, 0) - node T_682 = bits(sigX3, 56, 55) - node sigX3Shift1 = eq(T_682, UInt<1>("h00")) - node sExpX3 = subw(io.fromPreMul.sExpSum, estNormDist) - node T_686 = bits(sigX3, 56, 54) - node isZeroY = eq(T_686, UInt<1>("h00")) - node T_689 = xor(io.fromPreMul.signProd, doNegSignSum) - node signY = mux(isZeroY, signZeroNotEqOpSigns, T_689) + node T_625 = bits(T_582, 30, 16) + node T_626 = bits(T_625, 7, 0) + node T_629 = shl(UInt<4>("h0f"), 4) + node T_630 = xor(UInt<8>("h0ff"), T_629) + node T_631 = shr(T_626, 4) + node T_632 = and(T_631, T_630) + node T_633 = bits(T_626, 3, 0) + node T_634 = shl(T_633, 4) + node T_635 = not(T_630) + node T_636 = and(T_634, T_635) + node T_637 = or(T_632, T_636) + node T_638 = bits(T_630, 5, 0) + node T_639 = shl(T_638, 2) + node T_640 = xor(T_630, T_639) + node T_641 = shr(T_637, 2) + node T_642 = and(T_641, T_640) + node T_643 = bits(T_637, 5, 0) + node T_644 = shl(T_643, 2) + node T_645 = not(T_640) + node T_646 = and(T_644, T_645) + node T_647 = or(T_642, T_646) + node T_648 = bits(T_640, 6, 0) + node T_649 = shl(T_648, 1) + node T_650 = xor(T_640, T_649) + node T_651 = shr(T_647, 1) + node T_652 = and(T_651, T_650) + node T_653 = bits(T_647, 6, 0) + node T_654 = shl(T_653, 1) + node T_655 = not(T_650) + node T_656 = and(T_654, T_655) + node T_657 = or(T_652, T_656) + node T_658 = bits(T_625, 14, 8) + node T_659 = bits(T_658, 3, 0) + node T_660 = bits(T_659, 1, 0) + node T_661 = bits(T_660, 0, 0) + node T_662 = bits(T_660, 1, 1) + node T_663 = cat(T_661, T_662) + node T_664 = bits(T_659, 3, 2) + node T_665 = bits(T_664, 0, 0) + node T_666 = bits(T_664, 1, 1) + node T_667 = cat(T_665, T_666) + node T_668 = cat(T_663, T_667) + node T_669 = bits(T_658, 6, 4) + node T_670 = bits(T_669, 1, 0) + node T_671 = bits(T_670, 0, 0) + node T_672 = bits(T_670, 1, 1) + node T_673 = cat(T_671, T_672) + node T_674 = bits(T_669, 2, 2) + node T_675 = cat(T_673, T_674) + node T_676 = cat(T_668, T_675) + node T_677 = cat(T_657, T_676) + node T_678 = cat(T_624, T_677) + node absSigSumExtraMask = cat(T_678, UInt<1>("h01")) + node T_681 = bits(cFirstNormAbsSigSum, 87, 1) + node T_682 = dshr(T_681, normTo2ShiftDist) + node T_683 = bits(cFirstNormAbsSigSum, 31, 0) + node T_684 = not(T_683) + node T_685 = and(T_684, absSigSumExtraMask) + node T_687 = eq(T_685, UInt<1>("h00")) + node T_688 = bits(cFirstNormAbsSigSum, 31, 0) + node T_689 = and(T_688, absSigSumExtraMask) + node T_691 = neq(T_689, UInt<1>("h00")) + node T_692 = mux(doIncrSig, T_687, T_691) + node T_693 = cat(T_682, T_692) + node sigX3 = bits(T_693, 56, 0) + node T_695 = bits(sigX3, 56, 55) + node sigX3Shift1 = eq(T_695, UInt<1>("h00")) + node T_698 = sub(io.fromPreMul.sExpSum, estNormDist) + node sExpX3 = tail(T_698, 1) + node T_700 = bits(sigX3, 56, 54) + node isZeroY = eq(T_700, UInt<1>("h00")) + node T_703 = xor(io.fromPreMul.signProd, doNegSignSum) + node signY = mux(isZeroY, signZeroNotEqOpSigns, T_703) node sExpX3_13 = bits(sExpX3, 12, 0) - node T_692 = bit(sExpX3, 13) - node T_694 = subw(UInt<56>("h00"), T_692) - node T_695 = not(sExpX3_13) - node T_697 = dshr(asSInt(UInt<8193>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_695) - node T_698 = bits(T_697, 1027, 974) - node T_699 = bits(T_698, 31, 0) - node T_702 = shl(UInt<16>("h0ffff"), 16) - node T_703 = xor(UInt<32>("h0ffffffff"), T_702) - node T_704 = shr(T_699, 16) - node T_705 = and(T_704, T_703) - node T_706 = bits(T_699, 15, 0) - node T_707 = shl(T_706, 16) - node T_708 = not(T_703) - node T_709 = and(T_707, T_708) - node T_710 = or(T_705, T_709) - node T_711 = bits(T_703, 23, 0) - node T_712 = shl(T_711, 8) - node T_713 = xor(T_703, T_712) - node T_714 = shr(T_710, 8) - node T_715 = and(T_714, T_713) - node T_716 = bits(T_710, 23, 0) - node T_717 = shl(T_716, 8) - node T_718 = not(T_713) - node T_719 = and(T_717, T_718) - node T_720 = or(T_715, T_719) - node T_721 = bits(T_713, 27, 0) - node T_722 = shl(T_721, 4) - node T_723 = xor(T_713, T_722) - node T_724 = shr(T_720, 4) - node T_725 = and(T_724, T_723) - node T_726 = bits(T_720, 27, 0) - node T_727 = shl(T_726, 4) - node T_728 = not(T_723) - node T_729 = and(T_727, T_728) - node T_730 = or(T_725, T_729) - node T_731 = bits(T_723, 29, 0) - node T_732 = shl(T_731, 2) - node T_733 = xor(T_723, T_732) - node T_734 = shr(T_730, 2) - node T_735 = and(T_734, T_733) - node T_736 = bits(T_730, 29, 0) - node T_737 = shl(T_736, 2) - node T_738 = not(T_733) - node T_739 = and(T_737, T_738) - node T_740 = or(T_735, T_739) - node T_741 = bits(T_733, 30, 0) - node T_742 = shl(T_741, 1) - node T_743 = xor(T_733, T_742) - node T_744 = shr(T_740, 1) - node T_745 = and(T_744, T_743) - node T_746 = bits(T_740, 30, 0) - node T_747 = shl(T_746, 1) - node T_748 = not(T_743) - node T_749 = and(T_747, T_748) - node T_750 = or(T_745, T_749) - node T_751 = bits(T_698, 53, 32) - node T_752 = bits(T_751, 15, 0) - node T_755 = shl(UInt<8>("h0ff"), 8) - node T_756 = xor(UInt<16>("h0ffff"), T_755) - node T_757 = shr(T_752, 8) - node T_758 = and(T_757, T_756) - node T_759 = bits(T_752, 7, 0) - node T_760 = shl(T_759, 8) - node T_761 = not(T_756) - node T_762 = and(T_760, T_761) - node T_763 = or(T_758, T_762) - node T_764 = bits(T_756, 11, 0) - node T_765 = shl(T_764, 4) - node T_766 = xor(T_756, T_765) - node T_767 = shr(T_763, 4) - node T_768 = and(T_767, T_766) - node T_769 = bits(T_763, 11, 0) - node T_770 = shl(T_769, 4) - node T_771 = not(T_766) - node T_772 = and(T_770, T_771) - node T_773 = or(T_768, T_772) - node T_774 = bits(T_766, 13, 0) - node T_775 = shl(T_774, 2) - node T_776 = xor(T_766, T_775) - node T_777 = shr(T_773, 2) - node T_778 = and(T_777, T_776) - node T_779 = bits(T_773, 13, 0) - node T_780 = shl(T_779, 2) - node T_781 = not(T_776) - node T_782 = and(T_780, T_781) - node T_783 = or(T_778, T_782) - node T_784 = bits(T_776, 14, 0) - node T_785 = shl(T_784, 1) - node T_786 = xor(T_776, T_785) - node T_787 = shr(T_783, 1) - node T_788 = and(T_787, T_786) - node T_789 = bits(T_783, 14, 0) - node T_790 = shl(T_789, 1) - node T_791 = not(T_786) - node T_792 = and(T_790, T_791) - node T_793 = or(T_788, T_792) - node T_794 = bits(T_751, 21, 16) - node T_795 = bits(T_794, 3, 0) - node T_796 = bits(T_795, 1, 0) - node T_797 = bits(T_796, 0, 0) - node T_798 = bits(T_796, 1, 1) - node T_799 = cat(T_797, T_798) - node T_800 = bits(T_795, 3, 2) - node T_801 = bits(T_800, 0, 0) - node T_802 = bits(T_800, 1, 1) - node T_803 = cat(T_801, T_802) - node T_804 = cat(T_799, T_803) - node T_805 = bits(T_794, 5, 4) - node T_806 = bits(T_805, 0, 0) - node T_807 = bits(T_805, 1, 1) - node T_808 = cat(T_806, T_807) - node T_809 = cat(T_804, T_808) - node T_810 = cat(T_793, T_809) - node T_811 = cat(T_750, T_810) - node T_812 = bit(sigX3, 55) - node T_813 = or(T_811, T_812) - node T_815 = cat(T_813, UInt<2>("h03")) - node roundMask = or(T_694, T_815) - node T_817 = shr(roundMask, 1) - node T_818 = not(T_817) - node roundPosMask = and(T_818, roundMask) - node T_820 = and(sigX3, roundPosMask) - node roundPosBit = neq(T_820, UInt<1>("h00")) - node T_823 = shr(roundMask, 1) - node T_824 = and(sigX3, T_823) - node anyRoundExtra = neq(T_824, UInt<1>("h00")) - node T_827 = not(sigX3) - node T_828 = shr(roundMask, 1) - node T_829 = and(T_827, T_828) - node allRoundExtra = eq(T_829, UInt<1>("h00")) + node T_706 = bits(sExpX3, 13, 13) + node T_708 = sub(UInt<56>("h00"), T_706) + node T_709 = tail(T_708, 1) + node T_710 = not(sExpX3_13) + node T_712 = dshr(asSInt(UInt<8193>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_710) + node T_713 = bits(T_712, 1027, 974) + node T_714 = bits(T_713, 31, 0) + node T_717 = shl(UInt<16>("h0ffff"), 16) + node T_718 = xor(UInt<32>("h0ffffffff"), T_717) + node T_719 = shr(T_714, 16) + node T_720 = and(T_719, T_718) + node T_721 = bits(T_714, 15, 0) + node T_722 = shl(T_721, 16) + node T_723 = not(T_718) + node T_724 = and(T_722, T_723) + node T_725 = or(T_720, T_724) + node T_726 = bits(T_718, 23, 0) + node T_727 = shl(T_726, 8) + node T_728 = xor(T_718, T_727) + node T_729 = shr(T_725, 8) + node T_730 = and(T_729, T_728) + node T_731 = bits(T_725, 23, 0) + node T_732 = shl(T_731, 8) + node T_733 = not(T_728) + node T_734 = and(T_732, T_733) + node T_735 = or(T_730, T_734) + node T_736 = bits(T_728, 27, 0) + node T_737 = shl(T_736, 4) + node T_738 = xor(T_728, T_737) + node T_739 = shr(T_735, 4) + node T_740 = and(T_739, T_738) + node T_741 = bits(T_735, 27, 0) + node T_742 = shl(T_741, 4) + node T_743 = not(T_738) + node T_744 = and(T_742, T_743) + node T_745 = or(T_740, T_744) + node T_746 = bits(T_738, 29, 0) + node T_747 = shl(T_746, 2) + node T_748 = xor(T_738, T_747) + node T_749 = shr(T_745, 2) + node T_750 = and(T_749, T_748) + node T_751 = bits(T_745, 29, 0) + node T_752 = shl(T_751, 2) + node T_753 = not(T_748) + node T_754 = and(T_752, T_753) + node T_755 = or(T_750, T_754) + node T_756 = bits(T_748, 30, 0) + node T_757 = shl(T_756, 1) + node T_758 = xor(T_748, T_757) + node T_759 = shr(T_755, 1) + node T_760 = and(T_759, T_758) + node T_761 = bits(T_755, 30, 0) + node T_762 = shl(T_761, 1) + node T_763 = not(T_758) + node T_764 = and(T_762, T_763) + node T_765 = or(T_760, T_764) + node T_766 = bits(T_713, 53, 32) + node T_767 = bits(T_766, 15, 0) + node T_770 = shl(UInt<8>("h0ff"), 8) + node T_771 = xor(UInt<16>("h0ffff"), T_770) + node T_772 = shr(T_767, 8) + node T_773 = and(T_772, T_771) + node T_774 = bits(T_767, 7, 0) + node T_775 = shl(T_774, 8) + node T_776 = not(T_771) + node T_777 = and(T_775, T_776) + node T_778 = or(T_773, T_777) + node T_779 = bits(T_771, 11, 0) + node T_780 = shl(T_779, 4) + node T_781 = xor(T_771, T_780) + node T_782 = shr(T_778, 4) + node T_783 = and(T_782, T_781) + node T_784 = bits(T_778, 11, 0) + node T_785 = shl(T_784, 4) + node T_786 = not(T_781) + node T_787 = and(T_785, T_786) + node T_788 = or(T_783, T_787) + node T_789 = bits(T_781, 13, 0) + node T_790 = shl(T_789, 2) + node T_791 = xor(T_781, T_790) + node T_792 = shr(T_788, 2) + node T_793 = and(T_792, T_791) + node T_794 = bits(T_788, 13, 0) + node T_795 = shl(T_794, 2) + node T_796 = not(T_791) + node T_797 = and(T_795, T_796) + node T_798 = or(T_793, T_797) + node T_799 = bits(T_791, 14, 0) + node T_800 = shl(T_799, 1) + node T_801 = xor(T_791, T_800) + node T_802 = shr(T_798, 1) + node T_803 = and(T_802, T_801) + node T_804 = bits(T_798, 14, 0) + node T_805 = shl(T_804, 1) + node T_806 = not(T_801) + node T_807 = and(T_805, T_806) + node T_808 = or(T_803, T_807) + node T_809 = bits(T_766, 21, 16) + node T_810 = bits(T_809, 3, 0) + node T_811 = bits(T_810, 1, 0) + node T_812 = bits(T_811, 0, 0) + node T_813 = bits(T_811, 1, 1) + node T_814 = cat(T_812, T_813) + node T_815 = bits(T_810, 3, 2) + node T_816 = bits(T_815, 0, 0) + node T_817 = bits(T_815, 1, 1) + node T_818 = cat(T_816, T_817) + node T_819 = cat(T_814, T_818) + node T_820 = bits(T_809, 5, 4) + node T_821 = bits(T_820, 0, 0) + node T_822 = bits(T_820, 1, 1) + node T_823 = cat(T_821, T_822) + node T_824 = cat(T_819, T_823) + node T_825 = cat(T_808, T_824) + node T_826 = cat(T_765, T_825) + node T_827 = bits(sigX3, 55, 55) + node T_828 = or(T_826, T_827) + node T_830 = cat(T_828, UInt<2>("h03")) + node roundMask = or(T_709, T_830) + node T_832 = shr(roundMask, 1) + node T_833 = not(T_832) + node roundPosMask = and(T_833, roundMask) + node T_835 = and(sigX3, roundPosMask) + node roundPosBit = neq(T_835, UInt<1>("h00")) + node T_838 = shr(roundMask, 1) + node T_839 = and(sigX3, T_838) + node anyRoundExtra = neq(T_839, UInt<1>("h00")) + node T_842 = not(sigX3) + node T_843 = shr(roundMask, 1) + node T_844 = and(T_842, T_843) + node allRoundExtra = eq(T_844, UInt<1>("h00")) node anyRound = or(roundPosBit, anyRoundExtra) node allRound = and(roundPosBit, allRoundExtra) node roundDirectUp = mux(signY, roundingMode_min, roundingMode_max) - node T_835 = not(doIncrSig) - node T_836 = and(T_835, roundingMode_nearest_even) - node T_837 = and(T_836, roundPosBit) - node T_838 = and(T_837, anyRoundExtra) - node T_839 = not(doIncrSig) - node T_840 = and(T_839, roundDirectUp) - node T_841 = and(T_840, anyRound) - node T_842 = or(T_838, T_841) - node T_843 = and(doIncrSig, allRound) - node T_844 = or(T_842, T_843) - node T_845 = and(doIncrSig, roundingMode_nearest_even) - node T_846 = and(T_845, roundPosBit) - node T_847 = or(T_844, T_846) - node T_848 = and(doIncrSig, roundDirectUp) - node T_850 = and(T_848, UInt<1>("h01")) - node roundUp = or(T_847, T_850) - node T_852 = not(roundPosBit) - node T_853 = and(roundingMode_nearest_even, T_852) - node T_854 = and(T_853, allRoundExtra) - node T_855 = and(roundingMode_nearest_even, roundPosBit) - node T_856 = not(anyRoundExtra) - node T_857 = and(T_855, T_856) - node roundEven = mux(doIncrSig, T_854, T_857) - node T_859 = not(allRound) - node roundInexact = mux(doIncrSig, T_859, anyRound) - node T_861 = or(sigX3, roundMask) - node T_862 = shr(T_861, 2) - node T_864 = addw(T_862, UInt<1>("h01")) - node roundUp_sigY3 = bits(T_864, 54, 0) - node T_866 = not(roundUp) - node T_867 = not(roundEven) - node T_868 = and(T_866, T_867) - node T_869 = bit(T_868, 0) - node T_870 = not(roundMask) - node T_871 = and(sigX3, T_870) - node T_872 = shr(T_871, 2) - node T_874 = mux(T_869, T_872, UInt<1>("h00")) - node T_875 = bit(roundUp, 0) - node T_877 = mux(T_875, roundUp_sigY3, UInt<1>("h00")) - node T_878 = or(T_874, T_877) - node T_879 = shr(roundMask, 1) - node T_880 = not(T_879) - node T_881 = and(roundUp_sigY3, T_880) - node T_883 = mux(roundEven, T_881, UInt<1>("h00")) - node sigY3 = or(T_878, T_883) - node T_885 = bit(sigY3, 54) - node T_887 = addw(sExpX3, UInt<1>("h01")) - node T_889 = mux(T_885, T_887, UInt<1>("h00")) - node T_890 = bit(sigY3, 53) - node T_892 = mux(T_890, sExpX3, UInt<1>("h00")) - node T_893 = or(T_889, T_892) - node T_894 = bits(sigY3, 54, 53) - node T_896 = eq(T_894, UInt<1>("h00")) - node T_898 = subw(sExpX3, UInt<1>("h01")) - node T_900 = mux(T_896, T_898, UInt<1>("h00")) - node sExpY = or(T_893, T_900) + node T_850 = not(doIncrSig) + node T_851 = and(T_850, roundingMode_nearest_even) + node T_852 = and(T_851, roundPosBit) + node T_853 = and(T_852, anyRoundExtra) + node T_854 = not(doIncrSig) + node T_855 = and(T_854, roundDirectUp) + node T_856 = and(T_855, anyRound) + node T_857 = or(T_853, T_856) + node T_858 = and(doIncrSig, allRound) + node T_859 = or(T_857, T_858) + node T_860 = and(doIncrSig, roundingMode_nearest_even) + node T_861 = and(T_860, roundPosBit) + node T_862 = or(T_859, T_861) + node T_863 = and(doIncrSig, roundDirectUp) + node T_865 = and(T_863, UInt<1>("h01")) + node roundUp = or(T_862, T_865) + node T_867 = not(roundPosBit) + node T_868 = and(roundingMode_nearest_even, T_867) + node T_869 = and(T_868, allRoundExtra) + node T_870 = and(roundingMode_nearest_even, roundPosBit) + node T_871 = not(anyRoundExtra) + node T_872 = and(T_870, T_871) + node roundEven = mux(doIncrSig, T_869, T_872) + node T_874 = not(allRound) + node roundInexact = mux(doIncrSig, T_874, anyRound) + node T_876 = or(sigX3, roundMask) + node T_877 = shr(T_876, 2) + node T_879 = add(T_877, UInt<1>("h01")) + node T_880 = tail(T_879, 1) + node roundUp_sigY3 = bits(T_880, 54, 0) + node T_882 = not(roundUp) + node T_883 = not(roundEven) + node T_884 = and(T_882, T_883) + node T_885 = bits(T_884, 0, 0) + node T_886 = not(roundMask) + node T_887 = and(sigX3, T_886) + node T_888 = shr(T_887, 2) + node T_890 = mux(T_885, T_888, UInt<1>("h00")) + node T_891 = bits(roundUp, 0, 0) + node T_893 = mux(T_891, roundUp_sigY3, UInt<1>("h00")) + node T_894 = or(T_890, T_893) + node T_895 = shr(roundMask, 1) + node T_896 = not(T_895) + node T_897 = and(roundUp_sigY3, T_896) + node T_899 = mux(roundEven, T_897, UInt<1>("h00")) + node sigY3 = or(T_894, T_899) + node T_901 = bits(sigY3, 54, 54) + node T_903 = add(sExpX3, UInt<1>("h01")) + node T_904 = tail(T_903, 1) + node T_906 = mux(T_901, T_904, UInt<1>("h00")) + node T_907 = bits(sigY3, 53, 53) + node T_909 = mux(T_907, sExpX3, UInt<1>("h00")) + node T_910 = or(T_906, T_909) + node T_911 = bits(sigY3, 54, 53) + node T_913 = eq(T_911, UInt<1>("h00")) + node T_915 = sub(sExpX3, UInt<1>("h01")) + node T_916 = tail(T_915, 1) + node T_918 = mux(T_913, T_916, UInt<1>("h00")) + node sExpY = or(T_910, T_918) node expY = bits(sExpY, 11, 0) - node T_903 = bits(sigY3, 51, 0) - node T_904 = bits(sigY3, 52, 1) - node fractY = mux(sigX3Shift1, T_903, T_904) - node T_906 = bits(sExpY, 12, 10) - node overflowY = eq(T_906, UInt<2>("h03")) - node T_909 = not(isZeroY) - node T_910 = bit(sExpY, 12) - node T_911 = bits(sExpY, 11, 0) - node T_913 = lt(T_911, UInt<10>("h03ce")) - node T_914 = or(T_910, T_913) - node totalUnderflowY = and(T_909, T_914) - node T_916 = bit(sExpX3, 13) - node T_919 = mux(sigX3Shift1, UInt<11>("h0402"), UInt<11>("h0401")) - node T_920 = leq(sExpX3_13, T_919) - node T_921 = or(T_916, T_920) - node underflowY = and(roundInexact, T_921) - node T_923 = and(roundingMode_min, signY) - node T_924 = not(signY) - node T_925 = and(roundingMode_max, T_924) - node roundMagUp = or(T_923, T_925) + node T_921 = bits(sigY3, 51, 0) + node T_922 = bits(sigY3, 52, 1) + node fractY = mux(sigX3Shift1, T_921, T_922) + node T_924 = bits(sExpY, 12, 10) + node overflowY = eq(T_924, UInt<2>("h03")) + node T_927 = not(isZeroY) + node T_928 = bits(sExpY, 12, 12) + node T_929 = bits(sExpY, 11, 0) + node T_931 = lt(T_929, UInt<10>("h03ce")) + node T_932 = or(T_928, T_931) + node totalUnderflowY = and(T_927, T_932) + node T_934 = bits(sExpX3, 13, 13) + node T_937 = mux(sigX3Shift1, UInt<11>("h0402"), UInt<11>("h0401")) + node T_938 = leq(sExpX3_13, T_937) + node T_939 = or(T_934, T_938) + node underflowY = and(roundInexact, T_939) + node T_941 = and(roundingMode_min, signY) + node T_942 = not(signY) + node T_943 = and(roundingMode_max, T_942) + node roundMagUp = or(T_941, T_943) node overflowY_roundMagUp = or(roundingMode_nearest_even, roundMagUp) node mulSpecial = or(isSpecialA, isSpecialB) node addSpecial = or(mulSpecial, isSpecialC) node notSpecial_addZeros = and(io.fromPreMul.isZeroProd, isZeroC) - node T_931 = not(addSpecial) - node T_932 = not(notSpecial_addZeros) - node commonCase = and(T_931, T_932) - node T_934 = and(isInfA, isZeroB) - node T_935 = and(isZeroA, isInfB) - node T_936 = or(T_934, T_935) - node T_937 = not(isNaNA) - node T_938 = not(isNaNB) - node T_939 = and(T_937, T_938) - node T_940 = or(isInfA, isInfB) - node T_941 = and(T_939, T_940) - node T_942 = and(T_941, isInfC) - node T_943 = and(T_942, doSubMags) - node notSigNaN_invalid = or(T_936, T_943) - node T_945 = or(isSigNaNA, isSigNaNB) - node T_946 = or(T_945, isSigNaNC) - node invalid = or(T_946, notSigNaN_invalid) + node T_949 = not(addSpecial) + node T_950 = not(notSpecial_addZeros) + node commonCase = and(T_949, T_950) + node T_952 = and(isInfA, isZeroB) + node T_953 = and(isZeroA, isInfB) + node T_954 = or(T_952, T_953) + node T_955 = not(isNaNA) + node T_956 = not(isNaNB) + node T_957 = and(T_955, T_956) + node T_958 = or(isInfA, isInfB) + node T_959 = and(T_957, T_958) + node T_960 = and(T_959, isInfC) + node T_961 = and(T_960, doSubMags) + node notSigNaN_invalid = or(T_954, T_961) + node T_963 = or(isSigNaNA, isSigNaNB) + node T_964 = or(T_963, isSigNaNC) + node invalid = or(T_964, notSigNaN_invalid) node overflow = and(commonCase, overflowY) node underflow = and(commonCase, underflowY) - node T_950 = and(commonCase, roundInexact) - node inexact = or(overflow, T_950) - node T_952 = or(notSpecial_addZeros, isZeroY) - node notSpecial_isZeroOut = or(T_952, totalUnderflowY) - node T_954 = and(commonCase, totalUnderflowY) - node pegMinFiniteMagOut = and(T_954, roundMagUp) - node T_956 = not(overflowY_roundMagUp) - node pegMaxFiniteMagOut = and(overflow, T_956) - node T_958 = or(isInfA, isInfB) - node T_959 = or(T_958, isInfC) - node T_960 = and(overflow, overflowY_roundMagUp) - node notNaN_isInfOut = or(T_959, T_960) - node T_962 = or(isNaNA, isNaNB) - node T_963 = or(T_962, isNaNC) - node isNaNOut = or(T_963, notSigNaN_invalid) - node T_966 = eq(doSubMags, UInt<1>("h00")) - node T_967 = and(T_966, io.fromPreMul.opSignC) - node T_969 = eq(isSpecialC, UInt<1>("h00")) - node T_970 = and(mulSpecial, T_969) - node T_971 = and(T_970, io.fromPreMul.signProd) - node T_972 = or(T_967, T_971) - node T_974 = eq(mulSpecial, UInt<1>("h00")) - node T_975 = and(T_974, isSpecialC) - node T_976 = and(T_975, io.fromPreMul.opSignC) - node T_977 = or(T_972, T_976) - node T_979 = eq(mulSpecial, UInt<1>("h00")) - node T_980 = and(T_979, notSpecial_addZeros) - node T_981 = and(T_980, doSubMags) - node T_982 = and(T_981, signZeroNotEqOpSigns) - node uncommonCaseSignOut = or(T_977, T_982) - node T_985 = eq(isNaNOut, UInt<1>("h00")) - node T_986 = and(T_985, uncommonCaseSignOut) - node T_987 = and(commonCase, signY) - node signOut = or(T_986, T_987) - node T_991 = mux(notSpecial_isZeroOut, UInt<12>("h0e00"), UInt<12>("h00")) - node T_992 = not(T_991) - node T_993 = and(expY, T_992) - node T_995 = not(UInt<12>("h03ce")) - node T_997 = mux(pegMinFiniteMagOut, T_995, UInt<12>("h00")) - node T_998 = not(T_997) - node T_999 = and(T_993, T_998) - node T_1002 = mux(pegMaxFiniteMagOut, UInt<12>("h0400"), UInt<12>("h00")) - node T_1003 = not(T_1002) - node T_1004 = and(T_999, T_1003) - node T_1007 = mux(notNaN_isInfOut, UInt<10>("h0200"), UInt<12>("h00")) - node T_1008 = not(T_1007) - node T_1009 = and(T_1004, T_1008) - node T_1012 = mux(pegMinFiniteMagOut, UInt<10>("h03ce"), UInt<12>("h00")) - node T_1013 = or(T_1009, T_1012) - node T_1016 = mux(pegMaxFiniteMagOut, UInt<12>("h0bff"), UInt<12>("h00")) - node T_1017 = or(T_1013, T_1016) - node T_1020 = mux(notNaN_isInfOut, UInt<12>("h0c00"), UInt<12>("h00")) - node T_1021 = or(T_1017, T_1020) - node T_1024 = mux(isNaNOut, UInt<12>("h0e00"), UInt<12>("h00")) - node expOut = or(T_1021, T_1024) - node T_1026 = and(totalUnderflowY, roundMagUp) - node T_1027 = or(T_1026, isNaNOut) - node T_1029 = mux(T_1027, UInt<1>("h00"), fractY) - node T_1030 = shl(isNaNOut, 51) - node T_1031 = or(T_1029, T_1030) - node T_1033 = subw(UInt<52>("h00"), pegMaxFiniteMagOut) - node fractOut = or(T_1031, T_1033) - node T_1035 = cat(expOut, fractOut) - node T_1036 = cat(signOut, T_1035) - io.out <= T_1036 - node T_1038 = cat(invalid, UInt<1>("h00")) - node T_1039 = cat(underflow, inexact) - node T_1040 = cat(overflow, T_1039) - node T_1041 = cat(T_1038, T_1040) - io.exceptionFlags <= T_1041 + node T_968 = and(commonCase, roundInexact) + node inexact = or(overflow, T_968) + node T_970 = or(notSpecial_addZeros, isZeroY) + node notSpecial_isZeroOut = or(T_970, totalUnderflowY) + node T_972 = and(commonCase, totalUnderflowY) + node pegMinFiniteMagOut = and(T_972, roundMagUp) + node T_974 = not(overflowY_roundMagUp) + node pegMaxFiniteMagOut = and(overflow, T_974) + node T_976 = or(isInfA, isInfB) + node T_977 = or(T_976, isInfC) + node T_978 = and(overflow, overflowY_roundMagUp) + node notNaN_isInfOut = or(T_977, T_978) + node T_980 = or(isNaNA, isNaNB) + node T_981 = or(T_980, isNaNC) + node isNaNOut = or(T_981, notSigNaN_invalid) + node T_984 = eq(doSubMags, UInt<1>("h00")) + node T_985 = and(T_984, io.fromPreMul.opSignC) + node T_987 = eq(isSpecialC, UInt<1>("h00")) + node T_988 = and(mulSpecial, T_987) + node T_989 = and(T_988, io.fromPreMul.signProd) + node T_990 = or(T_985, T_989) + node T_992 = eq(mulSpecial, UInt<1>("h00")) + node T_993 = and(T_992, isSpecialC) + node T_994 = and(T_993, io.fromPreMul.opSignC) + node T_995 = or(T_990, T_994) + node T_997 = eq(mulSpecial, UInt<1>("h00")) + node T_998 = and(T_997, notSpecial_addZeros) + node T_999 = and(T_998, doSubMags) + node T_1000 = and(T_999, signZeroNotEqOpSigns) + node uncommonCaseSignOut = or(T_995, T_1000) + node T_1003 = eq(isNaNOut, UInt<1>("h00")) + node T_1004 = and(T_1003, uncommonCaseSignOut) + node T_1005 = and(commonCase, signY) + node signOut = or(T_1004, T_1005) + node T_1009 = mux(notSpecial_isZeroOut, UInt<12>("h0e00"), UInt<12>("h00")) + node T_1010 = not(T_1009) + node T_1011 = and(expY, T_1010) + node T_1013 = not(UInt<12>("h03ce")) + node T_1015 = mux(pegMinFiniteMagOut, T_1013, UInt<12>("h00")) + node T_1016 = not(T_1015) + node T_1017 = and(T_1011, T_1016) + node T_1020 = mux(pegMaxFiniteMagOut, UInt<12>("h0400"), UInt<12>("h00")) + node T_1021 = not(T_1020) + node T_1022 = and(T_1017, T_1021) + node T_1025 = mux(notNaN_isInfOut, UInt<10>("h0200"), UInt<12>("h00")) + node T_1026 = not(T_1025) + node T_1027 = and(T_1022, T_1026) + node T_1030 = mux(pegMinFiniteMagOut, UInt<10>("h03ce"), UInt<12>("h00")) + node T_1031 = or(T_1027, T_1030) + node T_1034 = mux(pegMaxFiniteMagOut, UInt<12>("h0bff"), UInt<12>("h00")) + node T_1035 = or(T_1031, T_1034) + node T_1038 = mux(notNaN_isInfOut, UInt<12>("h0c00"), UInt<12>("h00")) + node T_1039 = or(T_1035, T_1038) + node T_1042 = mux(isNaNOut, UInt<12>("h0e00"), UInt<12>("h00")) + node expOut = or(T_1039, T_1042) + node T_1044 = and(totalUnderflowY, roundMagUp) + node T_1045 = or(T_1044, isNaNOut) + node T_1047 = mux(T_1045, UInt<1>("h00"), fractY) + node T_1048 = shl(isNaNOut, 51) + node T_1049 = or(T_1047, T_1048) + node T_1051 = sub(UInt<52>("h00"), pegMaxFiniteMagOut) + node T_1052 = tail(T_1051, 1) + node fractOut = or(T_1049, T_1052) + node T_1054 = cat(expOut, fractOut) + node T_1055 = cat(signOut, T_1054) + io.out <= T_1055 + node T_1057 = cat(invalid, UInt<1>("h00")) + node T_1058 = cat(underflow, inexact) + node T_1059 = cat(overflow, T_1058) + node T_1060 = cat(T_1057, T_1059) + io.exceptionFlags <= T_1060 module MulAddRecFN_114 : input clk : Clock input reset : UInt<1> output io : {flip op : UInt<2>, flip a : UInt<65>, flip b : UInt<65>, flip c : UInt<65>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} - io.exceptionFlags <= UInt<1>("h00") - io.out <= UInt<1>("h00") + io is invalid inst mulAddRecFN_preMul of MulAddRecFN_preMul_115 - mulAddRecFN_preMul.io.roundingMode <= UInt<1>("h00") - mulAddRecFN_preMul.io.c <= UInt<1>("h00") - mulAddRecFN_preMul.io.b <= UInt<1>("h00") - mulAddRecFN_preMul.io.a <= UInt<1>("h00") - mulAddRecFN_preMul.io.op <= UInt<1>("h00") + mulAddRecFN_preMul.io is invalid mulAddRecFN_preMul.clk <= clk mulAddRecFN_preMul.reset <= reset inst mulAddRecFN_postMul of MulAddRecFN_postMul_116 - mulAddRecFN_postMul.io.mulAddResult <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.roundingMode <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.sExpSum <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.highAlignedNegSigC <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.bit0AlignedNegSigC <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.CAlignDist <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.CAlignDist_0 <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.isCDominant <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.isNaN_isQuietNaNC <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.highExpC <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.opSignC <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.isZeroProd <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.signProd <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.isNaN_isQuietNaNB <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.highExpB <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.isNaN_isQuietNaNA <= UInt<1>("h00") - mulAddRecFN_postMul.io.fromPreMul.highExpA <= UInt<1>("h00") + mulAddRecFN_postMul.io is invalid mulAddRecFN_postMul.clk <= clk mulAddRecFN_postMul.reset <= reset mulAddRecFN_preMul.io.op <= io.op @@ -35976,10 +28131,11 @@ circuit Top : mulAddRecFN_preMul.io.c <= io.c mulAddRecFN_preMul.io.roundingMode <= io.roundingMode mulAddRecFN_postMul.io.fromPreMul <- mulAddRecFN_preMul.io.toPostMul - node T_36 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) - node T_38 = cat(UInt<1>("h00"), mulAddRecFN_preMul.io.mulAddC) - node T_39 = addw(T_36, T_38) - mulAddRecFN_postMul.io.mulAddResult <= T_39 + node T_14 = mul(mulAddRecFN_preMul.io.mulAddA, mulAddRecFN_preMul.io.mulAddB) + node T_16 = cat(UInt<1>("h00"), mulAddRecFN_preMul.io.mulAddC) + node T_17 = add(T_14, T_16) + node T_18 = tail(T_17, 1) + mulAddRecFN_postMul.io.mulAddResult <= T_18 io.out <= mulAddRecFN_postMul.io.out io.exceptionFlags <= mulAddRecFN_postMul.io.exceptionFlags @@ -35988,23 +28144,21 @@ circuit Top : input reset : UInt<1> output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} - io.out.bits.exc <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") + io is invalid node one = shl(UInt<1>("h01"), 63) - node T_136 = bit(io.in.bits.in1, 64) - node T_137 = bit(io.in.bits.in2, 64) + node T_136 = bits(io.in.bits.in1, 64, 64) + node T_137 = bits(io.in.bits.in2, 64, 64) node T_138 = xor(T_136, T_137) node zero = shl(T_138, 64) - reg valid : UInt<1>, clk, UInt<1>("h00"), valid + reg valid : UInt<1>, clk valid <= io.in.valid - reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk, UInt<1>("h00"), in + reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk when io.in.valid : in <- io.in.bits - node T_187 = bit(io.in.bits.cmd, 1) + node T_187 = bits(io.in.bits.cmd, 1, 1) node T_188 = or(io.in.bits.ren3, io.in.bits.swap23) node T_189 = and(T_187, T_188) - node T_190 = bit(io.in.bits.cmd, 0) + node T_190 = bits(io.in.bits.cmd, 0, 0) node T_191 = cat(T_189, T_190) in.cmd <= T_191 when io.in.bits.swap23 : @@ -36017,11 +28171,7 @@ circuit Top : skip skip inst fma of MulAddRecFN_114 - fma.io.roundingMode <= UInt<1>("h00") - fma.io.c <= UInt<1>("h00") - fma.io.b <= UInt<1>("h00") - fma.io.a <= UInt<1>("h00") - fma.io.op <= UInt<1>("h00") + fma.io is invalid fma.clk <= clk fma.reset <= reset fma.io.op <= in.cmd @@ -36030,232 +28180,206 @@ circuit Top : fma.io.b <= in.in2 fma.io.c <= in.in3 wire res : {data : UInt<65>, exc : UInt<5>} - res.exc <= UInt<1>("h00") - res.data <= UInt<1>("h00") - node T_210 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_211 = cat(T_210, fma.io.out) - res.data <= T_211 + res is invalid + node T_203 = asUInt(asSInt(UInt<32>("h0ffffffff"))) + node T_204 = cat(T_203, fma.io.out) + res.data <= T_204 res.exc <= fma.io.exceptionFlags - reg T_214 : UInt<1>, clk, reset, UInt<1>("h00") - T_214 <= valid - reg T_215 : {data : UInt<65>, exc : UInt<5>}, clk, UInt<1>("h00"), T_215 + reg T_207 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + T_207 <= valid + reg T_208 : {data : UInt<65>, exc : UInt<5>}, clk when valid : - T_215 <- res + T_208 <- res skip - reg T_220 : UInt<1>, clk, reset, UInt<1>("h00") - T_220 <= T_214 - reg T_221 : {data : UInt<65>, exc : UInt<5>}, clk, UInt<1>("h00"), T_221 - when T_214 : - T_221 <- T_215 + reg T_213 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + T_213 <= T_207 + reg T_214 : {data : UInt<65>, exc : UInt<5>}, clk + when T_207 : + T_214 <- T_208 skip - wire T_232 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} - T_232.bits.exc <= UInt<1>("h00") - T_232.bits.data <= UInt<1>("h00") - T_232.valid <= UInt<1>("h00") - T_232.valid <= T_220 - T_232.bits <- T_221 - io.out <- T_232 + wire T_225 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} + T_225 is invalid + T_225.valid <= T_213 + T_225.bits <- T_214 + io.out <- T_225 module RecFNToRecFN : input clk : Clock input reset : UInt<1> output io : {flip in : UInt<33>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} - io.exceptionFlags <= UInt<1>("h00") - io.out <= UInt<1>("h00") + io is invalid node T_8 = bits(io.in, 31, 23) node T_9 = bits(T_8, 8, 7) node T_11 = eq(T_9, UInt<2>("h03")) wire T_19 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} - T_19.sig <= UInt<1>("h00") - T_19.sExp <= asSInt(UInt<1>("h00")) - T_19.isZero <= UInt<1>("h00") - T_19.isInf <= UInt<1>("h00") - T_19.isNaN <= UInt<1>("h00") - T_19.sign <= UInt<1>("h00") - node T_32 = bit(io.in, 32) - T_19.sign <= T_32 - node T_33 = bit(T_8, 6) - node T_34 = and(T_11, T_33) - T_19.isNaN <= T_34 - node T_35 = bit(T_8, 6) - node T_37 = eq(T_35, UInt<1>("h00")) - node T_38 = and(T_11, T_37) - T_19.isInf <= T_38 - node T_39 = bits(T_8, 8, 6) - node T_41 = eq(T_39, UInt<1>("h00")) - T_19.isZero <= T_41 - node T_42 = cvt(T_8) - T_19.sExp <= T_42 - node T_44 = bits(io.in, 22, 0) - node T_46 = cat(T_44, UInt<2>("h00")) - node T_47 = cat(UInt<2>("h01"), T_46) - T_19.sig <= T_47 - node T_49 = addw(T_19.sExp, asSInt(UInt<12>("h0700"))) + T_19 is invalid + node T_26 = bits(io.in, 32, 32) + T_19.sign <= T_26 + node T_27 = bits(T_8, 6, 6) + node T_28 = and(T_11, T_27) + T_19.isNaN <= T_28 + node T_29 = bits(T_8, 6, 6) + node T_31 = eq(T_29, UInt<1>("h00")) + node T_32 = and(T_11, T_31) + T_19.isInf <= T_32 + node T_33 = bits(T_8, 8, 6) + node T_35 = eq(T_33, UInt<1>("h00")) + T_19.isZero <= T_35 + node T_36 = cvt(T_8) + T_19.sExp <= T_36 + node T_38 = bits(io.in, 22, 0) + node T_40 = cat(T_38, UInt<2>("h00")) + node T_41 = cat(UInt<2>("h01"), T_40) + T_19.sig <= T_41 + node T_43 = add(T_19.sExp, asSInt(UInt<12>("h0700"))) + node T_44 = tail(T_43, 1) + node T_45 = asSInt(T_44) wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} - outRawFloat.sig <= UInt<1>("h00") - outRawFloat.sExp <= asSInt(UInt<1>("h00")) - outRawFloat.isZero <= UInt<1>("h00") - outRawFloat.isInf <= UInt<1>("h00") - outRawFloat.isNaN <= UInt<1>("h00") - outRawFloat.sign <= UInt<1>("h00") + outRawFloat is invalid outRawFloat.sign <= T_19.sign outRawFloat.isNaN <= T_19.isNaN outRawFloat.isInf <= T_19.isInf outRawFloat.isZero <= T_19.isZero - outRawFloat.sExp <= T_49 - node T_70 = shl(T_19.sig, 29) - outRawFloat.sig <= T_70 - node T_71 = bit(outRawFloat.sig, 53) - node T_73 = eq(T_71, UInt<1>("h00")) - node invalidExc = and(outRawFloat.isNaN, T_73) - node T_75 = not(outRawFloat.isNaN) - node T_76 = and(outRawFloat.sign, T_75) - node T_77 = bits(outRawFloat.sExp, 11, 0) - node T_80 = mux(outRawFloat.isZero, UInt<12>("h0c00"), UInt<1>("h00")) - node T_81 = not(T_80) - node T_82 = and(T_77, T_81) - node T_83 = or(outRawFloat.isZero, outRawFloat.isInf) - node T_86 = mux(T_83, UInt<12>("h0200"), UInt<1>("h00")) - node T_87 = not(T_86) - node T_88 = and(T_82, T_87) - node T_91 = mux(outRawFloat.isInf, UInt<12>("h0c00"), UInt<1>("h00")) - node T_92 = or(T_88, T_91) - node T_95 = mux(outRawFloat.isNaN, UInt<12>("h0e00"), UInt<1>("h00")) - node T_96 = or(T_92, T_95) - node T_98 = bits(outRawFloat.sig, 53, 2) - node T_99 = mux(outRawFloat.isNaN, UInt<52>("h08000000000000"), T_98) - node T_100 = cat(T_96, T_99) - node T_101 = cat(T_76, T_100) - io.out <= T_101 - node T_103 = cat(invalidExc, UInt<4>("h00")) - io.exceptionFlags <= T_103 + outRawFloat.sExp <= T_45 + node T_60 = shl(T_19.sig, 29) + outRawFloat.sig <= T_60 + node T_61 = bits(outRawFloat.sig, 53, 53) + node T_63 = eq(T_61, UInt<1>("h00")) + node invalidExc = and(outRawFloat.isNaN, T_63) + node T_65 = not(outRawFloat.isNaN) + node T_66 = and(outRawFloat.sign, T_65) + node T_67 = bits(outRawFloat.sExp, 11, 0) + node T_70 = mux(outRawFloat.isZero, UInt<12>("h0c00"), UInt<1>("h00")) + node T_71 = not(T_70) + node T_72 = and(T_67, T_71) + node T_73 = or(outRawFloat.isZero, outRawFloat.isInf) + node T_76 = mux(T_73, UInt<12>("h0200"), UInt<1>("h00")) + node T_77 = not(T_76) + node T_78 = and(T_72, T_77) + node T_81 = mux(outRawFloat.isInf, UInt<12>("h0c00"), UInt<1>("h00")) + node T_82 = or(T_78, T_81) + node T_85 = mux(outRawFloat.isNaN, UInt<12>("h0e00"), UInt<1>("h00")) + node T_86 = or(T_82, T_85) + node T_88 = bits(outRawFloat.sig, 53, 2) + node T_89 = mux(outRawFloat.isNaN, UInt<52>("h08000000000000"), T_88) + node T_90 = cat(T_86, T_89) + node T_91 = cat(T_66, T_90) + io.out <= T_91 + node T_93 = cat(invalidExc, UInt<4>("h00")) + io.exceptionFlags <= T_93 module CompareRecFN : input clk : Clock input reset : UInt<1> output io : {flip a : UInt<65>, flip b : UInt<65>, flip signaling : UInt<1>, lt : UInt<1>, eq : UInt<1>, gt : UInt<1>, exceptionFlags : UInt<5>} - io.exceptionFlags <= UInt<1>("h00") - io.gt <= UInt<1>("h00") - io.eq <= UInt<1>("h00") - io.lt <= UInt<1>("h00") + io is invalid node T_11 = bits(io.a, 63, 52) node T_12 = bits(T_11, 11, 10) node T_14 = eq(T_12, UInt<2>("h03")) wire rawA : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} - rawA.sig <= UInt<1>("h00") - rawA.sExp <= asSInt(UInt<1>("h00")) - rawA.isZero <= UInt<1>("h00") - rawA.isInf <= UInt<1>("h00") - rawA.isNaN <= UInt<1>("h00") - rawA.sign <= UInt<1>("h00") - node T_35 = bit(io.a, 64) - rawA.sign <= T_35 - node T_36 = bit(T_11, 9) - node T_37 = and(T_14, T_36) - rawA.isNaN <= T_37 - node T_38 = bit(T_11, 9) - node T_40 = eq(T_38, UInt<1>("h00")) - node T_41 = and(T_14, T_40) - rawA.isInf <= T_41 - node T_42 = bits(T_11, 11, 9) - node T_44 = eq(T_42, UInt<1>("h00")) - rawA.isZero <= T_44 - node T_45 = cvt(T_11) - rawA.sExp <= T_45 - node T_47 = bits(io.a, 51, 0) - node T_49 = cat(T_47, UInt<2>("h00")) - node T_50 = cat(UInt<2>("h01"), T_49) - rawA.sig <= T_50 - node T_51 = bits(io.b, 63, 52) - node T_52 = bits(T_51, 11, 10) - node T_54 = eq(T_52, UInt<2>("h03")) + rawA is invalid + node T_29 = bits(io.a, 64, 64) + rawA.sign <= T_29 + node T_30 = bits(T_11, 9, 9) + node T_31 = and(T_14, T_30) + rawA.isNaN <= T_31 + node T_32 = bits(T_11, 9, 9) + node T_34 = eq(T_32, UInt<1>("h00")) + node T_35 = and(T_14, T_34) + rawA.isInf <= T_35 + node T_36 = bits(T_11, 11, 9) + node T_38 = eq(T_36, UInt<1>("h00")) + rawA.isZero <= T_38 + node T_39 = cvt(T_11) + rawA.sExp <= T_39 + node T_41 = bits(io.a, 51, 0) + node T_43 = cat(T_41, UInt<2>("h00")) + node T_44 = cat(UInt<2>("h01"), T_43) + rawA.sig <= T_44 + node T_45 = bits(io.b, 63, 52) + node T_46 = bits(T_45, 11, 10) + node T_48 = eq(T_46, UInt<2>("h03")) wire rawB : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} - rawB.sig <= UInt<1>("h00") - rawB.sExp <= asSInt(UInt<1>("h00")) - rawB.isZero <= UInt<1>("h00") - rawB.isInf <= UInt<1>("h00") - rawB.isNaN <= UInt<1>("h00") - rawB.sign <= UInt<1>("h00") - node T_75 = bit(io.b, 64) - rawB.sign <= T_75 - node T_76 = bit(T_51, 9) - node T_77 = and(T_54, T_76) - rawB.isNaN <= T_77 - node T_78 = bit(T_51, 9) - node T_80 = eq(T_78, UInt<1>("h00")) - node T_81 = and(T_54, T_80) - rawB.isInf <= T_81 - node T_82 = bits(T_51, 11, 9) - node T_84 = eq(T_82, UInt<1>("h00")) - rawB.isZero <= T_84 - node T_85 = cvt(T_51) - rawB.sExp <= T_85 - node T_87 = bits(io.b, 51, 0) - node T_89 = cat(T_87, UInt<2>("h00")) - node T_90 = cat(UInt<2>("h01"), T_89) - rawB.sig <= T_90 - node T_91 = not(rawA.isNaN) - node T_92 = not(rawB.isNaN) - node ordered = and(T_91, T_92) + rawB is invalid + node T_63 = bits(io.b, 64, 64) + rawB.sign <= T_63 + node T_64 = bits(T_45, 9, 9) + node T_65 = and(T_48, T_64) + rawB.isNaN <= T_65 + node T_66 = bits(T_45, 9, 9) + node T_68 = eq(T_66, UInt<1>("h00")) + node T_69 = and(T_48, T_68) + rawB.isInf <= T_69 + node T_70 = bits(T_45, 11, 9) + node T_72 = eq(T_70, UInt<1>("h00")) + rawB.isZero <= T_72 + node T_73 = cvt(T_45) + rawB.sExp <= T_73 + node T_75 = bits(io.b, 51, 0) + node T_77 = cat(T_75, UInt<2>("h00")) + node T_78 = cat(UInt<2>("h01"), T_77) + rawB.sig <= T_78 + node T_79 = not(rawA.isNaN) + node T_80 = not(rawB.isNaN) + node ordered = and(T_79, T_80) node bothInfs = and(rawA.isInf, rawB.isInf) node bothZeros = and(rawA.isZero, rawB.isZero) node eqExps = eq(rawA.sExp, rawB.sExp) - node T_97 = lt(rawA.sExp, rawB.sExp) - node T_98 = lt(rawA.sig, rawB.sig) - node T_99 = and(eqExps, T_98) - node common_ltMags = or(T_97, T_99) - node T_101 = eq(rawA.sig, rawB.sig) - node common_eqMags = and(eqExps, T_101) - node T_103 = not(bothZeros) - node T_104 = not(rawB.sign) - node T_105 = and(rawA.sign, T_104) - node T_106 = not(bothInfs) - node T_107 = not(common_ltMags) - node T_108 = and(rawA.sign, T_107) - node T_109 = not(common_eqMags) - node T_110 = and(T_108, T_109) - node T_111 = not(rawB.sign) - node T_112 = and(T_111, common_ltMags) - node T_113 = or(T_110, T_112) - node T_114 = and(T_106, T_113) - node T_115 = or(T_105, T_114) - node ordered_lt = and(T_103, T_115) - node T_117 = eq(rawA.sign, rawB.sign) - node T_118 = or(bothInfs, common_eqMags) - node T_119 = and(T_117, T_118) - node ordered_eq = or(bothZeros, T_119) - node T_121 = bit(rawA.sig, 53) - node T_123 = eq(T_121, UInt<1>("h00")) - node T_124 = and(rawA.isNaN, T_123) - node T_125 = bit(rawB.sig, 53) - node T_127 = eq(T_125, UInt<1>("h00")) - node T_128 = and(rawB.isNaN, T_127) - node T_129 = or(T_124, T_128) - node T_130 = not(ordered) - node T_131 = and(io.signaling, T_130) - node invalid = or(T_129, T_131) - node T_133 = and(ordered, ordered_lt) - io.lt <= T_133 - node T_134 = and(ordered, ordered_eq) - io.eq <= T_134 - node T_135 = not(ordered_lt) - node T_136 = and(ordered, T_135) - node T_137 = not(ordered_eq) - node T_138 = and(T_136, T_137) - io.gt <= T_138 - node T_140 = cat(invalid, UInt<4>("h00")) - io.exceptionFlags <= T_140 + node T_85 = lt(rawA.sExp, rawB.sExp) + node T_86 = lt(rawA.sig, rawB.sig) + node T_87 = and(eqExps, T_86) + node common_ltMags = or(T_85, T_87) + node T_89 = eq(rawA.sig, rawB.sig) + node common_eqMags = and(eqExps, T_89) + node T_91 = not(bothZeros) + node T_92 = not(rawB.sign) + node T_93 = and(rawA.sign, T_92) + node T_94 = not(bothInfs) + node T_95 = not(common_ltMags) + node T_96 = and(rawA.sign, T_95) + node T_97 = not(common_eqMags) + node T_98 = and(T_96, T_97) + node T_99 = not(rawB.sign) + node T_100 = and(T_99, common_ltMags) + node T_101 = or(T_98, T_100) + node T_102 = and(T_94, T_101) + node T_103 = or(T_93, T_102) + node ordered_lt = and(T_91, T_103) + node T_105 = eq(rawA.sign, rawB.sign) + node T_106 = or(bothInfs, common_eqMags) + node T_107 = and(T_105, T_106) + node ordered_eq = or(bothZeros, T_107) + node T_109 = bits(rawA.sig, 53, 53) + node T_111 = eq(T_109, UInt<1>("h00")) + node T_112 = and(rawA.isNaN, T_111) + node T_113 = bits(rawB.sig, 53, 53) + node T_115 = eq(T_113, UInt<1>("h00")) + node T_116 = and(rawB.isNaN, T_115) + node T_117 = or(T_112, T_116) + node T_118 = not(ordered) + node T_119 = and(io.signaling, T_118) + node invalid = or(T_117, T_119) + node T_121 = and(ordered, ordered_lt) + io.lt <= T_121 + node T_122 = and(ordered, ordered_eq) + io.eq <= T_122 + node T_123 = not(ordered_lt) + node T_124 = and(ordered, T_123) + node T_125 = not(ordered_eq) + node T_126 = and(T_124, T_125) + io.gt <= T_126 + node T_128 = cat(invalid, UInt<4>("h00")) + io.exceptionFlags <= T_128 module RecFNToIN : input clk : Clock input reset : UInt<1> output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<64>, intExceptionFlags : UInt<3>} - io.intExceptionFlags <= UInt<1>("h00") - io.out <= UInt<1>("h00") - node sign = bit(io.in, 64) + io is invalid + node sign = bits(io.in, 64, 64) node exp = bits(io.in, 63, 52) node fract = bits(io.in, 51, 0) node T_12 = bits(exp, 11, 9) @@ -36263,9 +28387,9 @@ circuit Top : node T_15 = bits(exp, 11, 10) node T_16 = not(T_15) node isSpecial = eq(T_16, UInt<1>("h00")) - node T_19 = bit(exp, 9) + node T_19 = bits(exp, 9, 9) node isNaN = and(isSpecial, T_19) - node notSpecial_magGeOne = bit(exp, 11) + node notSpecial_magGeOne = bits(exp, 11, 11) node T_22 = cat(notSpecial_magGeOne, fract) node T_23 = bits(exp, 5, 0) node T_25 = mux(notSpecial_magGeOne, T_23, UInt<1>("h00")) @@ -36307,68 +28431,68 @@ circuit Top : node T_70 = not(unroundedInt) node onesCompUnroundedInt = mux(sign, T_70, unroundedInt) node T_72 = xor(roundIncr, sign) - node T_74 = addw(onesCompUnroundedInt, UInt<1>("h01")) - node roundedInt = mux(T_72, T_74, onesCompUnroundedInt) - node T_76 = bits(unroundedInt, 61, 0) - node T_77 = not(T_76) - node T_79 = eq(T_77, UInt<1>("h00")) - node roundCarryBut2 = and(T_79, roundIncr) + node T_74 = add(onesCompUnroundedInt, UInt<1>("h01")) + node T_75 = tail(T_74, 1) + node roundedInt = mux(T_72, T_75, onesCompUnroundedInt) + node T_77 = bits(unroundedInt, 61, 0) + node T_78 = not(T_77) + node T_80 = eq(T_78, UInt<1>("h00")) + node roundCarryBut2 = and(T_80, roundIncr) node posExp = bits(exp, 10, 0) - node T_83 = geq(posExp, UInt<7>("h040")) - node T_85 = eq(posExp, UInt<6>("h03f")) - node T_87 = eq(sign, UInt<1>("h00")) - node T_88 = bits(unroundedInt, 62, 0) - node T_90 = neq(T_88, UInt<1>("h00")) - node T_91 = or(T_87, T_90) - node T_92 = or(T_91, roundIncr) - node T_93 = and(T_85, T_92) - node T_94 = or(T_83, T_93) - node T_96 = eq(sign, UInt<1>("h00")) - node T_98 = eq(posExp, UInt<6>("h03e")) - node T_99 = and(T_96, T_98) - node T_100 = and(T_99, roundCarryBut2) - node T_101 = or(T_94, T_100) - node overflow_signed = mux(notSpecial_magGeOne, T_101, UInt<1>("h00")) - node T_105 = geq(posExp, UInt<7>("h040")) - node T_106 = or(sign, T_105) - node T_108 = eq(posExp, UInt<6>("h03f")) - node T_109 = bit(unroundedInt, 62) - node T_110 = and(T_108, T_109) - node T_111 = and(T_110, roundCarryBut2) - node T_112 = or(T_106, T_111) - node T_113 = and(sign, roundIncr) - node overflow_unsigned = mux(notSpecial_magGeOne, T_112, T_113) + node T_84 = geq(posExp, UInt<7>("h040")) + node T_86 = eq(posExp, UInt<6>("h03f")) + node T_88 = eq(sign, UInt<1>("h00")) + node T_89 = bits(unroundedInt, 62, 0) + node T_91 = neq(T_89, UInt<1>("h00")) + node T_92 = or(T_88, T_91) + node T_93 = or(T_92, roundIncr) + node T_94 = and(T_86, T_93) + node T_95 = or(T_84, T_94) + node T_97 = eq(sign, UInt<1>("h00")) + node T_99 = eq(posExp, UInt<6>("h03e")) + node T_100 = and(T_97, T_99) + node T_101 = and(T_100, roundCarryBut2) + node T_102 = or(T_95, T_101) + node overflow_signed = mux(notSpecial_magGeOne, T_102, UInt<1>("h00")) + node T_106 = geq(posExp, UInt<7>("h040")) + node T_107 = or(sign, T_106) + node T_109 = eq(posExp, UInt<6>("h03f")) + node T_110 = bits(unroundedInt, 62, 62) + node T_111 = and(T_109, T_110) + node T_112 = and(T_111, roundCarryBut2) + node T_113 = or(T_107, T_112) + node T_114 = and(sign, roundIncr) + node overflow_unsigned = mux(notSpecial_magGeOne, T_113, T_114) node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned) - node T_117 = eq(isNaN, UInt<1>("h00")) - node excSign = and(sign, T_117) - node T_119 = and(io.signedOut, excSign) - node T_122 = mux(T_119, UInt<64>("h08000000000000000"), UInt<1>("h00")) - node T_124 = eq(excSign, UInt<1>("h00")) - node T_125 = and(io.signedOut, T_124) - node T_128 = mux(T_125, UInt<63>("h07fffffffffffffff"), UInt<1>("h00")) - node T_129 = or(T_122, T_128) - node T_131 = eq(io.signedOut, UInt<1>("h00")) - node T_134 = mux(T_131, UInt<64>("h0ffffffffffffffff"), UInt<1>("h00")) - node excValue = or(T_129, T_134) - node T_137 = eq(isSpecial, UInt<1>("h00")) - node T_138 = and(roundInexact, T_137) - node T_140 = eq(overflow, UInt<1>("h00")) - node inexact = and(T_138, T_140) - node T_142 = or(isSpecial, overflow) - node T_143 = mux(T_142, excValue, roundedInt) - io.out <= T_143 - node T_144 = cat(overflow, inexact) - node T_145 = cat(isSpecial, T_144) - io.intExceptionFlags <= T_145 + node T_118 = eq(isNaN, UInt<1>("h00")) + node excSign = and(sign, T_118) + node T_120 = and(io.signedOut, excSign) + node T_123 = mux(T_120, UInt<64>("h08000000000000000"), UInt<1>("h00")) + node T_125 = eq(excSign, UInt<1>("h00")) + node T_126 = and(io.signedOut, T_125) + node T_129 = mux(T_126, UInt<63>("h07fffffffffffffff"), UInt<1>("h00")) + node T_130 = or(T_123, T_129) + node T_132 = eq(io.signedOut, UInt<1>("h00")) + node T_135 = mux(T_132, UInt<64>("h0ffffffffffffffff"), UInt<1>("h00")) + node excValue = or(T_130, T_135) + node T_138 = eq(isSpecial, UInt<1>("h00")) + node T_139 = and(roundInexact, T_138) + node T_141 = eq(overflow, UInt<1>("h00")) + node inexact = and(T_139, T_141) + node T_143 = or(isSpecial, overflow) + node T_144 = mux(T_143, excValue, roundedInt) + io.out <= T_144 + node T_145 = cat(overflow, inexact) + node T_146 = cat(isSpecial, T_145) + io.intExceptionFlags <= T_146 module RecFNToIN_118 : input clk : Clock input reset : UInt<1> output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, flip signedOut : UInt<1>, out : UInt<32>, intExceptionFlags : UInt<3>} - io.intExceptionFlags <= UInt<1>("h00") - io.out <= UInt<1>("h00") - node sign = bit(io.in, 64) + io is invalid + node sign = bits(io.in, 64, 64) node exp = bits(io.in, 63, 52) node fract = bits(io.in, 51, 0) node T_12 = bits(exp, 11, 9) @@ -36376,9 +28500,9 @@ circuit Top : node T_15 = bits(exp, 11, 10) node T_16 = not(T_15) node isSpecial = eq(T_16, UInt<1>("h00")) - node T_19 = bit(exp, 9) + node T_19 = bits(exp, 9, 9) node isNaN = and(isSpecial, T_19) - node notSpecial_magGeOne = bit(exp, 11) + node notSpecial_magGeOne = bits(exp, 11, 11) node T_22 = cat(notSpecial_magGeOne, fract) node T_23 = bits(exp, 4, 0) node T_25 = mux(notSpecial_magGeOne, T_23, UInt<1>("h00")) @@ -36420,301 +28544,279 @@ circuit Top : node T_70 = not(unroundedInt) node onesCompUnroundedInt = mux(sign, T_70, unroundedInt) node T_72 = xor(roundIncr, sign) - node T_74 = addw(onesCompUnroundedInt, UInt<1>("h01")) - node roundedInt = mux(T_72, T_74, onesCompUnroundedInt) - node T_76 = bits(unroundedInt, 29, 0) - node T_77 = not(T_76) - node T_79 = eq(T_77, UInt<1>("h00")) - node roundCarryBut2 = and(T_79, roundIncr) + node T_74 = add(onesCompUnroundedInt, UInt<1>("h01")) + node T_75 = tail(T_74, 1) + node roundedInt = mux(T_72, T_75, onesCompUnroundedInt) + node T_77 = bits(unroundedInt, 29, 0) + node T_78 = not(T_77) + node T_80 = eq(T_78, UInt<1>("h00")) + node roundCarryBut2 = and(T_80, roundIncr) node posExp = bits(exp, 10, 0) - node T_83 = geq(posExp, UInt<6>("h020")) - node T_85 = eq(posExp, UInt<5>("h01f")) - node T_87 = eq(sign, UInt<1>("h00")) - node T_88 = bits(unroundedInt, 30, 0) - node T_90 = neq(T_88, UInt<1>("h00")) - node T_91 = or(T_87, T_90) - node T_92 = or(T_91, roundIncr) - node T_93 = and(T_85, T_92) - node T_94 = or(T_83, T_93) - node T_96 = eq(sign, UInt<1>("h00")) - node T_98 = eq(posExp, UInt<5>("h01e")) - node T_99 = and(T_96, T_98) - node T_100 = and(T_99, roundCarryBut2) - node T_101 = or(T_94, T_100) - node overflow_signed = mux(notSpecial_magGeOne, T_101, UInt<1>("h00")) - node T_105 = geq(posExp, UInt<6>("h020")) - node T_106 = or(sign, T_105) - node T_108 = eq(posExp, UInt<5>("h01f")) - node T_109 = bit(unroundedInt, 30) - node T_110 = and(T_108, T_109) - node T_111 = and(T_110, roundCarryBut2) - node T_112 = or(T_106, T_111) - node T_113 = and(sign, roundIncr) - node overflow_unsigned = mux(notSpecial_magGeOne, T_112, T_113) + node T_84 = geq(posExp, UInt<6>("h020")) + node T_86 = eq(posExp, UInt<5>("h01f")) + node T_88 = eq(sign, UInt<1>("h00")) + node T_89 = bits(unroundedInt, 30, 0) + node T_91 = neq(T_89, UInt<1>("h00")) + node T_92 = or(T_88, T_91) + node T_93 = or(T_92, roundIncr) + node T_94 = and(T_86, T_93) + node T_95 = or(T_84, T_94) + node T_97 = eq(sign, UInt<1>("h00")) + node T_99 = eq(posExp, UInt<5>("h01e")) + node T_100 = and(T_97, T_99) + node T_101 = and(T_100, roundCarryBut2) + node T_102 = or(T_95, T_101) + node overflow_signed = mux(notSpecial_magGeOne, T_102, UInt<1>("h00")) + node T_106 = geq(posExp, UInt<6>("h020")) + node T_107 = or(sign, T_106) + node T_109 = eq(posExp, UInt<5>("h01f")) + node T_110 = bits(unroundedInt, 30, 30) + node T_111 = and(T_109, T_110) + node T_112 = and(T_111, roundCarryBut2) + node T_113 = or(T_107, T_112) + node T_114 = and(sign, roundIncr) + node overflow_unsigned = mux(notSpecial_magGeOne, T_113, T_114) node overflow = mux(io.signedOut, overflow_signed, overflow_unsigned) - node T_117 = eq(isNaN, UInt<1>("h00")) - node excSign = and(sign, T_117) - node T_119 = and(io.signedOut, excSign) - node T_122 = mux(T_119, UInt<32>("h080000000"), UInt<1>("h00")) - node T_124 = eq(excSign, UInt<1>("h00")) - node T_125 = and(io.signedOut, T_124) - node T_128 = mux(T_125, UInt<31>("h07fffffff"), UInt<1>("h00")) - node T_129 = or(T_122, T_128) - node T_131 = eq(io.signedOut, UInt<1>("h00")) - node T_134 = mux(T_131, UInt<32>("h0ffffffff"), UInt<1>("h00")) - node excValue = or(T_129, T_134) - node T_137 = eq(isSpecial, UInt<1>("h00")) - node T_138 = and(roundInexact, T_137) - node T_140 = eq(overflow, UInt<1>("h00")) - node inexact = and(T_138, T_140) - node T_142 = or(isSpecial, overflow) - node T_143 = mux(T_142, excValue, roundedInt) - io.out <= T_143 - node T_144 = cat(overflow, inexact) - node T_145 = cat(isSpecial, T_144) - io.intExceptionFlags <= T_145 + node T_118 = eq(isNaN, UInt<1>("h00")) + node excSign = and(sign, T_118) + node T_120 = and(io.signedOut, excSign) + node T_123 = mux(T_120, UInt<32>("h080000000"), UInt<1>("h00")) + node T_125 = eq(excSign, UInt<1>("h00")) + node T_126 = and(io.signedOut, T_125) + node T_129 = mux(T_126, UInt<31>("h07fffffff"), UInt<1>("h00")) + node T_130 = or(T_123, T_129) + node T_132 = eq(io.signedOut, UInt<1>("h00")) + node T_135 = mux(T_132, UInt<32>("h0ffffffff"), UInt<1>("h00")) + node excValue = or(T_130, T_135) + node T_138 = eq(isSpecial, UInt<1>("h00")) + node T_139 = and(roundInexact, T_138) + node T_141 = eq(overflow, UInt<1>("h00")) + node inexact = and(T_139, T_141) + node T_143 = or(isSpecial, overflow) + node T_144 = mux(T_143, excValue, roundedInt) + io.out <= T_144 + node T_145 = cat(overflow, inexact) + node T_146 = cat(isSpecial, T_145) + io.intExceptionFlags <= T_146 module FPToInt : input clk : Clock input reset : UInt<1> output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, as_double : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, out : {valid : UInt<1>, bits : {lt : UInt<1>, store : UInt<64>, toint : UInt<64>, exc : UInt<5>}}} - io.out.bits.exc <= UInt<1>("h00") - io.out.bits.toint <= UInt<1>("h00") - io.out.bits.store <= UInt<1>("h00") - io.out.bits.lt <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - io.as_double.in3 <= UInt<1>("h00") - io.as_double.in2 <= UInt<1>("h00") - io.as_double.in1 <= UInt<1>("h00") - io.as_double.typ <= UInt<1>("h00") - io.as_double.rm <= UInt<1>("h00") - io.as_double.wflags <= UInt<1>("h00") - io.as_double.round <= UInt<1>("h00") - io.as_double.sqrt <= UInt<1>("h00") - io.as_double.div <= UInt<1>("h00") - io.as_double.fma <= UInt<1>("h00") - io.as_double.fastpipe <= UInt<1>("h00") - io.as_double.toint <= UInt<1>("h00") - io.as_double.fromint <= UInt<1>("h00") - io.as_double.single <= UInt<1>("h00") - io.as_double.swap23 <= UInt<1>("h00") - io.as_double.swap12 <= UInt<1>("h00") - io.as_double.ren3 <= UInt<1>("h00") - io.as_double.ren2 <= UInt<1>("h00") - io.as_double.ren1 <= UInt<1>("h00") - io.as_double.wen <= UInt<1>("h00") - io.as_double.ldst <= UInt<1>("h00") - io.as_double.cmd <= UInt<1>("h00") - reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk, UInt<1>("h00"), in - reg valid : UInt<1>, clk, UInt<1>("h00"), valid + io is invalid + reg in : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk + reg valid : UInt<1>, clk valid <= io.in.valid inst T_233 of RecFNToRecFN - T_233.io.roundingMode <= UInt<1>("h00") - T_233.io.in <= UInt<1>("h00") + T_233.io is invalid T_233.clk <= clk T_233.reset <= reset T_233.io.in <= io.in.bits.in1 T_233.io.roundingMode <= UInt<1>("h00") - inst T_237 of RecFNToRecFN - T_237.io.roundingMode <= UInt<1>("h00") - T_237.io.in <= UInt<1>("h00") - T_237.clk <= clk - T_237.reset <= reset - T_237.io.in <= io.in.bits.in2 - T_237.io.roundingMode <= UInt<1>("h00") + inst T_235 of RecFNToRecFN + T_235.io is invalid + T_235.clk <= clk + T_235.reset <= reset + T_235.io.in <= io.in.bits.in2 + T_235.io.roundingMode <= UInt<1>("h00") when io.in.valid : in <- io.in.bits - node T_242 = eq(io.in.bits.ldst, UInt<1>("h00")) - node T_243 = and(io.in.bits.single, T_242) - node T_246 = and(io.in.bits.cmd, UInt<4>("h0c")) - node T_247 = eq(UInt<4>("h0c"), T_246) - node T_249 = eq(T_247, UInt<1>("h00")) - node T_250 = and(T_243, T_249) - when T_250 : + node T_238 = eq(io.in.bits.ldst, UInt<1>("h00")) + node T_239 = and(io.in.bits.single, T_238) + node T_242 = and(io.in.bits.cmd, UInt<4>("h0c")) + node T_243 = eq(UInt<4>("h0c"), T_242) + node T_245 = eq(T_243, UInt<1>("h00")) + node T_246 = and(T_239, T_245) + when T_246 : in.in1 <= T_233.io.out - in.in2 <= T_237.io.out - skip - skip - node T_251 = bit(in.in1, 32) - node T_252 = bits(in.in1, 31, 23) - node T_253 = bits(in.in1, 22, 0) - node T_254 = bits(T_252, 6, 0) - node T_256 = lt(T_254, UInt<2>("h02")) - node T_257 = bits(T_252, 8, 6) - node T_259 = eq(T_257, UInt<1>("h01")) - node T_260 = bits(T_252, 8, 7) - node T_262 = eq(T_260, UInt<1>("h01")) - node T_263 = and(T_262, T_256) - node T_264 = or(T_259, T_263) - node T_265 = bits(T_252, 8, 7) - node T_267 = eq(T_265, UInt<1>("h01")) - node T_269 = eq(T_256, UInt<1>("h00")) - node T_270 = and(T_267, T_269) - node T_271 = bits(T_252, 8, 7) - node T_273 = eq(T_271, UInt<2>("h02")) - node T_274 = or(T_270, T_273) - node T_275 = bits(T_252, 8, 7) - node T_277 = eq(T_275, UInt<2>("h03")) - node T_278 = bit(T_252, 6) - node T_279 = and(T_277, T_278) - node T_281 = bits(T_252, 4, 0) - node T_282 = subw(UInt<2>("h02"), T_281) - node T_284 = cat(UInt<1>("h01"), T_253) - node T_285 = dshr(T_284, T_282) - node T_286 = bits(T_285, 22, 0) - node T_287 = bits(T_252, 7, 0) - node T_289 = subw(T_287, UInt<8>("h081")) - node T_291 = subw(UInt<8>("h00"), T_277) - node T_292 = mux(T_274, T_289, T_291) - node T_293 = or(T_274, T_279) - node T_295 = mux(T_264, T_286, UInt<1>("h00")) - node T_296 = mux(T_293, T_253, T_295) - node T_297 = cat(T_292, T_296) - node unrec_s = cat(T_251, T_297) - node T_299 = bit(in.in1, 64) - node T_300 = bits(in.in1, 63, 52) - node T_301 = bits(in.in1, 51, 0) - node T_302 = bits(T_300, 9, 0) - node T_304 = lt(T_302, UInt<2>("h02")) - node T_305 = bits(T_300, 11, 9) - node T_307 = eq(T_305, UInt<1>("h01")) - node T_308 = bits(T_300, 11, 10) - node T_310 = eq(T_308, UInt<1>("h01")) - node T_311 = and(T_310, T_304) - node T_312 = or(T_307, T_311) - node T_313 = bits(T_300, 11, 10) - node T_315 = eq(T_313, UInt<1>("h01")) - node T_317 = eq(T_304, UInt<1>("h00")) - node T_318 = and(T_315, T_317) - node T_319 = bits(T_300, 11, 10) - node T_321 = eq(T_319, UInt<2>("h02")) - node T_322 = or(T_318, T_321) - node T_323 = bits(T_300, 11, 10) - node T_325 = eq(T_323, UInt<2>("h03")) - node T_326 = bit(T_300, 9) - node T_327 = and(T_325, T_326) - node T_329 = bits(T_300, 5, 0) - node T_330 = subw(UInt<2>("h02"), T_329) - node T_332 = cat(UInt<1>("h01"), T_301) + in.in2 <= T_235.io.out + skip + skip + node T_247 = bits(in.in1, 32, 32) + node T_248 = bits(in.in1, 31, 23) + node T_249 = bits(in.in1, 22, 0) + node T_250 = bits(T_248, 6, 0) + node T_252 = lt(T_250, UInt<2>("h02")) + node T_253 = bits(T_248, 8, 6) + node T_255 = eq(T_253, UInt<1>("h01")) + node T_256 = bits(T_248, 8, 7) + node T_258 = eq(T_256, UInt<1>("h01")) + node T_259 = and(T_258, T_252) + node T_260 = or(T_255, T_259) + node T_261 = bits(T_248, 8, 7) + node T_263 = eq(T_261, UInt<1>("h01")) + node T_265 = eq(T_252, UInt<1>("h00")) + node T_266 = and(T_263, T_265) + node T_267 = bits(T_248, 8, 7) + node T_269 = eq(T_267, UInt<2>("h02")) + node T_270 = or(T_266, T_269) + node T_271 = bits(T_248, 8, 7) + node T_273 = eq(T_271, UInt<2>("h03")) + node T_274 = bits(T_248, 6, 6) + node T_275 = and(T_273, T_274) + node T_277 = bits(T_248, 4, 0) + node T_278 = sub(UInt<2>("h02"), T_277) + node T_279 = tail(T_278, 1) + node T_281 = cat(UInt<1>("h01"), T_249) + node T_282 = dshr(T_281, T_279) + node T_283 = bits(T_282, 22, 0) + node T_284 = bits(T_248, 7, 0) + node T_286 = sub(T_284, UInt<8>("h081")) + node T_287 = tail(T_286, 1) + node T_289 = sub(UInt<8>("h00"), T_273) + node T_290 = tail(T_289, 1) + node T_291 = mux(T_270, T_287, T_290) + node T_292 = or(T_270, T_275) + node T_294 = mux(T_260, T_283, UInt<1>("h00")) + node T_295 = mux(T_292, T_249, T_294) + node T_296 = cat(T_291, T_295) + node unrec_s = cat(T_247, T_296) + node T_298 = bits(in.in1, 64, 64) + node T_299 = bits(in.in1, 63, 52) + node T_300 = bits(in.in1, 51, 0) + node T_301 = bits(T_299, 9, 0) + node T_303 = lt(T_301, UInt<2>("h02")) + node T_304 = bits(T_299, 11, 9) + node T_306 = eq(T_304, UInt<1>("h01")) + node T_307 = bits(T_299, 11, 10) + node T_309 = eq(T_307, UInt<1>("h01")) + node T_310 = and(T_309, T_303) + node T_311 = or(T_306, T_310) + node T_312 = bits(T_299, 11, 10) + node T_314 = eq(T_312, UInt<1>("h01")) + node T_316 = eq(T_303, UInt<1>("h00")) + node T_317 = and(T_314, T_316) + node T_318 = bits(T_299, 11, 10) + node T_320 = eq(T_318, UInt<2>("h02")) + node T_321 = or(T_317, T_320) + node T_322 = bits(T_299, 11, 10) + node T_324 = eq(T_322, UInt<2>("h03")) + node T_325 = bits(T_299, 9, 9) + node T_326 = and(T_324, T_325) + node T_328 = bits(T_299, 5, 0) + node T_329 = sub(UInt<2>("h02"), T_328) + node T_330 = tail(T_329, 1) + node T_332 = cat(UInt<1>("h01"), T_300) node T_333 = dshr(T_332, T_330) node T_334 = bits(T_333, 51, 0) - node T_335 = bits(T_300, 10, 0) - node T_337 = subw(T_335, UInt<11>("h0401")) - node T_339 = subw(UInt<11>("h00"), T_325) - node T_340 = mux(T_322, T_337, T_339) - node T_341 = or(T_322, T_327) - node T_343 = mux(T_312, T_334, UInt<1>("h00")) - node T_344 = mux(T_341, T_301, T_343) - node T_345 = cat(T_340, T_344) - node unrec_d = cat(T_299, T_345) - node T_347 = bit(unrec_s, 31) - node T_349 = subw(UInt<32>("h00"), T_347) - node T_350 = cat(T_349, unrec_s) - node unrec_out = mux(in.single, T_350, unrec_d) - node T_352 = bit(in.in1, 32) - node T_353 = bits(in.in1, 31, 23) - node T_354 = bits(in.in1, 22, 0) - node T_355 = bits(T_353, 8, 6) - node T_356 = bits(T_355, 2, 1) - node T_358 = eq(T_356, UInt<2>("h03")) - node T_359 = bits(T_353, 6, 0) - node T_361 = lt(T_359, UInt<2>("h02")) - node T_363 = eq(T_355, UInt<1>("h01")) - node T_365 = eq(T_356, UInt<1>("h01")) - node T_366 = and(T_365, T_361) - node T_367 = or(T_363, T_366) - node T_369 = eq(T_356, UInt<1>("h01")) - node T_371 = eq(T_361, UInt<1>("h00")) - node T_372 = and(T_369, T_371) - node T_374 = eq(T_356, UInt<2>("h02")) - node T_375 = or(T_372, T_374) - node T_377 = eq(T_355, UInt<1>("h00")) - node T_378 = bit(T_353, 6) - node T_380 = eq(T_378, UInt<1>("h00")) - node T_381 = and(T_358, T_380) - node T_382 = not(T_355) - node T_384 = eq(T_382, UInt<1>("h00")) - node T_385 = bit(T_354, 22) + node T_335 = bits(T_299, 10, 0) + node T_337 = sub(T_335, UInt<11>("h0401")) + node T_338 = tail(T_337, 1) + node T_340 = sub(UInt<11>("h00"), T_324) + node T_341 = tail(T_340, 1) + node T_342 = mux(T_321, T_338, T_341) + node T_343 = or(T_321, T_326) + node T_345 = mux(T_311, T_334, UInt<1>("h00")) + node T_346 = mux(T_343, T_300, T_345) + node T_347 = cat(T_342, T_346) + node unrec_d = cat(T_298, T_347) + node T_349 = bits(unrec_s, 31, 31) + node T_351 = sub(UInt<32>("h00"), T_349) + node T_352 = tail(T_351, 1) + node T_353 = cat(T_352, unrec_s) + node unrec_out = mux(in.single, T_353, unrec_d) + node T_355 = bits(in.in1, 32, 32) + node T_356 = bits(in.in1, 31, 23) + node T_357 = bits(in.in1, 22, 0) + node T_358 = bits(T_356, 8, 6) + node T_359 = bits(T_358, 2, 1) + node T_361 = eq(T_359, UInt<2>("h03")) + node T_362 = bits(T_356, 6, 0) + node T_364 = lt(T_362, UInt<2>("h02")) + node T_366 = eq(T_358, UInt<1>("h01")) + node T_368 = eq(T_359, UInt<1>("h01")) + node T_369 = and(T_368, T_364) + node T_370 = or(T_366, T_369) + node T_372 = eq(T_359, UInt<1>("h01")) + node T_374 = eq(T_364, UInt<1>("h00")) + node T_375 = and(T_372, T_374) + node T_377 = eq(T_359, UInt<2>("h02")) + node T_378 = or(T_375, T_377) + node T_380 = eq(T_358, UInt<1>("h00")) + node T_381 = bits(T_356, 6, 6) + node T_383 = eq(T_381, UInt<1>("h00")) + node T_384 = and(T_361, T_383) + node T_385 = not(T_358) node T_387 = eq(T_385, UInt<1>("h00")) - node T_388 = and(T_384, T_387) - node T_389 = bit(T_354, 22) - node T_390 = and(T_384, T_389) - node T_392 = eq(T_352, UInt<1>("h00")) - node T_393 = and(T_381, T_392) - node T_395 = eq(T_352, UInt<1>("h00")) - node T_396 = and(T_375, T_395) - node T_398 = eq(T_352, UInt<1>("h00")) - node T_399 = and(T_367, T_398) - node T_401 = eq(T_352, UInt<1>("h00")) - node T_402 = and(T_377, T_401) - node T_403 = and(T_377, T_352) - node T_404 = and(T_367, T_352) - node T_405 = and(T_375, T_352) - node T_406 = and(T_381, T_352) - node T_407 = cat(T_390, T_388) - node T_408 = cat(T_396, T_399) - node T_409 = cat(T_393, T_408) - node T_410 = cat(T_407, T_409) - node T_411 = cat(T_402, T_403) - node T_412 = cat(T_405, T_406) - node T_413 = cat(T_404, T_412) - node T_414 = cat(T_411, T_413) - node classify_s = cat(T_410, T_414) - node T_416 = bit(in.in1, 64) - node T_417 = bits(in.in1, 63, 52) - node T_418 = bits(in.in1, 51, 0) - node T_419 = bits(T_417, 11, 9) - node T_420 = bits(T_419, 2, 1) - node T_422 = eq(T_420, UInt<2>("h03")) - node T_423 = bits(T_417, 9, 0) - node T_425 = lt(T_423, UInt<2>("h02")) - node T_427 = eq(T_419, UInt<1>("h01")) - node T_429 = eq(T_420, UInt<1>("h01")) - node T_430 = and(T_429, T_425) - node T_431 = or(T_427, T_430) - node T_433 = eq(T_420, UInt<1>("h01")) - node T_435 = eq(T_425, UInt<1>("h00")) - node T_436 = and(T_433, T_435) - node T_438 = eq(T_420, UInt<2>("h02")) - node T_439 = or(T_436, T_438) - node T_441 = eq(T_419, UInt<1>("h00")) - node T_442 = bit(T_417, 9) - node T_444 = eq(T_442, UInt<1>("h00")) - node T_445 = and(T_422, T_444) - node T_446 = not(T_419) - node T_448 = eq(T_446, UInt<1>("h00")) - node T_449 = bit(T_418, 51) + node T_388 = bits(T_357, 22, 22) + node T_390 = eq(T_388, UInt<1>("h00")) + node T_391 = and(T_387, T_390) + node T_392 = bits(T_357, 22, 22) + node T_393 = and(T_387, T_392) + node T_395 = eq(T_355, UInt<1>("h00")) + node T_396 = and(T_384, T_395) + node T_398 = eq(T_355, UInt<1>("h00")) + node T_399 = and(T_378, T_398) + node T_401 = eq(T_355, UInt<1>("h00")) + node T_402 = and(T_370, T_401) + node T_404 = eq(T_355, UInt<1>("h00")) + node T_405 = and(T_380, T_404) + node T_406 = and(T_380, T_355) + node T_407 = and(T_370, T_355) + node T_408 = and(T_378, T_355) + node T_409 = and(T_384, T_355) + node T_410 = cat(T_393, T_391) + node T_411 = cat(T_399, T_402) + node T_412 = cat(T_396, T_411) + node T_413 = cat(T_410, T_412) + node T_414 = cat(T_405, T_406) + node T_415 = cat(T_408, T_409) + node T_416 = cat(T_407, T_415) + node T_417 = cat(T_414, T_416) + node classify_s = cat(T_413, T_417) + node T_419 = bits(in.in1, 64, 64) + node T_420 = bits(in.in1, 63, 52) + node T_421 = bits(in.in1, 51, 0) + node T_422 = bits(T_420, 11, 9) + node T_423 = bits(T_422, 2, 1) + node T_425 = eq(T_423, UInt<2>("h03")) + node T_426 = bits(T_420, 9, 0) + node T_428 = lt(T_426, UInt<2>("h02")) + node T_430 = eq(T_422, UInt<1>("h01")) + node T_432 = eq(T_423, UInt<1>("h01")) + node T_433 = and(T_432, T_428) + node T_434 = or(T_430, T_433) + node T_436 = eq(T_423, UInt<1>("h01")) + node T_438 = eq(T_428, UInt<1>("h00")) + node T_439 = and(T_436, T_438) + node T_441 = eq(T_423, UInt<2>("h02")) + node T_442 = or(T_439, T_441) + node T_444 = eq(T_422, UInt<1>("h00")) + node T_445 = bits(T_420, 9, 9) + node T_447 = eq(T_445, UInt<1>("h00")) + node T_448 = and(T_425, T_447) + node T_449 = not(T_422) node T_451 = eq(T_449, UInt<1>("h00")) - node T_452 = and(T_448, T_451) - node T_453 = bit(T_418, 51) - node T_454 = and(T_448, T_453) - node T_456 = eq(T_416, UInt<1>("h00")) - node T_457 = and(T_445, T_456) - node T_459 = eq(T_416, UInt<1>("h00")) - node T_460 = and(T_439, T_459) - node T_462 = eq(T_416, UInt<1>("h00")) - node T_463 = and(T_431, T_462) - node T_465 = eq(T_416, UInt<1>("h00")) - node T_466 = and(T_441, T_465) - node T_467 = and(T_441, T_416) - node T_468 = and(T_431, T_416) - node T_469 = and(T_439, T_416) - node T_470 = and(T_445, T_416) - node T_471 = cat(T_454, T_452) - node T_472 = cat(T_460, T_463) - node T_473 = cat(T_457, T_472) - node T_474 = cat(T_471, T_473) - node T_475 = cat(T_466, T_467) - node T_476 = cat(T_469, T_470) - node T_477 = cat(T_468, T_476) - node T_478 = cat(T_475, T_477) - node classify_d = cat(T_474, T_478) + node T_452 = bits(T_421, 51, 51) + node T_454 = eq(T_452, UInt<1>("h00")) + node T_455 = and(T_451, T_454) + node T_456 = bits(T_421, 51, 51) + node T_457 = and(T_451, T_456) + node T_459 = eq(T_419, UInt<1>("h00")) + node T_460 = and(T_448, T_459) + node T_462 = eq(T_419, UInt<1>("h00")) + node T_463 = and(T_442, T_462) + node T_465 = eq(T_419, UInt<1>("h00")) + node T_466 = and(T_434, T_465) + node T_468 = eq(T_419, UInt<1>("h00")) + node T_469 = and(T_444, T_468) + node T_470 = and(T_444, T_419) + node T_471 = and(T_434, T_419) + node T_472 = and(T_442, T_419) + node T_473 = and(T_448, T_419) + node T_474 = cat(T_457, T_455) + node T_475 = cat(T_463, T_466) + node T_476 = cat(T_460, T_475) + node T_477 = cat(T_474, T_476) + node T_478 = cat(T_469, T_470) + node T_479 = cat(T_472, T_473) + node T_480 = cat(T_471, T_479) + node T_481 = cat(T_478, T_480) + node classify_d = cat(T_477, T_481) node classify_out = mux(in.single, classify_s, classify_d) inst dcmp of CompareRecFN - dcmp.io.signaling <= UInt<1>("h00") - dcmp.io.b <= UInt<1>("h00") - dcmp.io.a <= UInt<1>("h00") + dcmp.io is invalid dcmp.clk <= clk dcmp.reset <= reset dcmp.io.a <= in.in1 @@ -36725,55 +28827,51 @@ circuit Top : node T_488 = and(T_486, T_487) node dcmp_out = neq(T_488, UInt<1>("h00")) inst d2l of RecFNToIN - d2l.io.signedOut <= UInt<1>("h00") - d2l.io.roundingMode <= UInt<1>("h00") - d2l.io.in <= UInt<1>("h00") + d2l.io is invalid d2l.clk <= clk d2l.reset <= reset inst d2w of RecFNToIN_118 - d2w.io.signedOut <= UInt<1>("h00") - d2w.io.roundingMode <= UInt<1>("h00") - d2w.io.in <= UInt<1>("h00") + d2w.io is invalid d2w.clk <= clk d2w.reset <= reset d2l.io.in <= in.in1 d2l.io.roundingMode <= in.rm - node T_499 = bit(in.typ, 0) - node T_500 = not(T_499) - d2l.io.signedOut <= T_500 + node T_493 = bits(in.typ, 0, 0) + node T_494 = not(T_493) + d2l.io.signedOut <= T_494 d2w.io.in <= in.in1 d2w.io.roundingMode <= in.rm - node T_501 = bit(in.typ, 0) - node T_502 = not(T_501) - d2w.io.signedOut <= T_502 - node T_503 = bit(in.rm, 0) - node T_504 = mux(T_503, classify_out, unrec_out) - io.out.bits.toint <= T_504 + node T_495 = bits(in.typ, 0, 0) + node T_496 = not(T_495) + d2w.io.signedOut <= T_496 + node T_497 = bits(in.rm, 0, 0) + node T_498 = mux(T_497, classify_out, unrec_out) + io.out.bits.toint <= T_498 io.out.bits.store <= unrec_out io.out.bits.exc <= UInt<1>("h00") - node T_508 = and(in.cmd, UInt<4>("h0c")) - node T_509 = eq(UInt<3>("h04"), T_508) - when T_509 : + node T_502 = and(in.cmd, UInt<4>("h0c")) + node T_503 = eq(UInt<3>("h04"), T_502) + when T_503 : io.out.bits.toint <= dcmp_out io.out.bits.exc <= dcmp.io.exceptionFlags skip - node T_512 = and(in.cmd, UInt<4>("h0c")) - node T_513 = eq(UInt<4>("h08"), T_512) - when T_513 : - node T_514 = bit(in.typ, 1) - node T_515 = asSInt(d2l.io.out) - node T_516 = asSInt(d2w.io.out) - node T_517 = mux(T_514, T_515, T_516) - node T_518 = asUInt(T_517) - io.out.bits.toint <= T_518 - node T_519 = bit(in.typ, 1) - node T_520 = mux(T_519, d2l.io.intExceptionFlags, d2w.io.intExceptionFlags) - node T_521 = bits(T_520, 2, 1) - node T_523 = neq(T_521, UInt<1>("h00")) - node T_525 = bit(T_520, 0) - node T_526 = cat(UInt<3>("h00"), T_525) - node T_527 = cat(T_523, T_526) - io.out.bits.exc <= T_527 + node T_506 = and(in.cmd, UInt<4>("h0c")) + node T_507 = eq(UInt<4>("h08"), T_506) + when T_507 : + node T_508 = bits(in.typ, 1, 1) + node T_509 = asSInt(d2l.io.out) + node T_510 = asSInt(d2w.io.out) + node T_511 = mux(T_508, T_509, T_510) + node T_512 = asUInt(T_511) + io.out.bits.toint <= T_512 + node T_513 = bits(in.typ, 1, 1) + node T_514 = mux(T_513, d2l.io.intExceptionFlags, d2w.io.intExceptionFlags) + node T_515 = bits(T_514, 2, 1) + node T_517 = neq(T_515, UInt<1>("h00")) + node T_519 = bits(T_514, 0, 0) + node T_520 = cat(UInt<3>("h00"), T_519) + node T_521 = cat(T_517, T_520) + io.out.bits.exc <= T_521 skip io.out.valid <= valid io.out.bits.lt <= dcmp.io.lt @@ -36784,752 +28882,730 @@ circuit Top : input reset : UInt<1> output io : {flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} - io.exceptionFlags <= UInt<1>("h00") - io.out <= UInt<1>("h00") - node T_9 = bit(io.in, 63) + io is invalid + node T_9 = bits(io.in, 63, 63) node sign = and(io.signedIn, T_9) - node T_12 = subw(UInt<1>("h00"), io.in) - node absIn = mux(sign, T_12, io.in) - node T_14 = shl(absIn, 0) - node T_15 = bit(T_14, 63) - node T_17 = bit(T_14, 62) - node T_19 = bit(T_14, 61) - node T_21 = bit(T_14, 60) - node T_23 = bit(T_14, 59) - node T_25 = bit(T_14, 58) - node T_27 = bit(T_14, 57) - node T_29 = bit(T_14, 56) - node T_31 = bit(T_14, 55) - node T_33 = bit(T_14, 54) - node T_35 = bit(T_14, 53) - node T_37 = bit(T_14, 52) - node T_39 = bit(T_14, 51) - node T_41 = bit(T_14, 50) - node T_43 = bit(T_14, 49) - node T_45 = bit(T_14, 48) - node T_47 = bit(T_14, 47) - node T_49 = bit(T_14, 46) - node T_51 = bit(T_14, 45) - node T_53 = bit(T_14, 44) - node T_55 = bit(T_14, 43) - node T_57 = bit(T_14, 42) - node T_59 = bit(T_14, 41) - node T_61 = bit(T_14, 40) - node T_63 = bit(T_14, 39) - node T_65 = bit(T_14, 38) - node T_67 = bit(T_14, 37) - node T_69 = bit(T_14, 36) - node T_71 = bit(T_14, 35) - node T_73 = bit(T_14, 34) - node T_75 = bit(T_14, 33) - node T_77 = bit(T_14, 32) - node T_79 = bit(T_14, 31) - node T_81 = bit(T_14, 30) - node T_83 = bit(T_14, 29) - node T_85 = bit(T_14, 28) - node T_87 = bit(T_14, 27) - node T_89 = bit(T_14, 26) - node T_91 = bit(T_14, 25) - node T_93 = bit(T_14, 24) - node T_95 = bit(T_14, 23) - node T_97 = bit(T_14, 22) - node T_99 = bit(T_14, 21) - node T_101 = bit(T_14, 20) - node T_103 = bit(T_14, 19) - node T_105 = bit(T_14, 18) - node T_107 = bit(T_14, 17) - node T_109 = bit(T_14, 16) - node T_111 = bit(T_14, 15) - node T_113 = bit(T_14, 14) - node T_115 = bit(T_14, 13) - node T_117 = bit(T_14, 12) - node T_119 = bit(T_14, 11) - node T_121 = bit(T_14, 10) - node T_123 = bit(T_14, 9) - node T_125 = bit(T_14, 8) - node T_127 = bit(T_14, 7) - node T_129 = bit(T_14, 6) - node T_131 = bit(T_14, 5) - node T_133 = bit(T_14, 4) - node T_135 = bit(T_14, 3) - node T_137 = bit(T_14, 2) - node T_139 = bit(T_14, 1) - node T_140 = shl(T_139, 0) - node T_141 = mux(T_137, UInt<2>("h02"), T_140) - node T_142 = mux(T_135, UInt<2>("h03"), T_141) - node T_143 = mux(T_133, UInt<3>("h04"), T_142) - node T_144 = mux(T_131, UInt<3>("h05"), T_143) - node T_145 = mux(T_129, UInt<3>("h06"), T_144) - node T_146 = mux(T_127, UInt<3>("h07"), T_145) - node T_147 = mux(T_125, UInt<4>("h08"), T_146) - node T_148 = mux(T_123, UInt<4>("h09"), T_147) - node T_149 = mux(T_121, UInt<4>("h0a"), T_148) - node T_150 = mux(T_119, UInt<4>("h0b"), T_149) - node T_151 = mux(T_117, UInt<4>("h0c"), T_150) - node T_152 = mux(T_115, UInt<4>("h0d"), T_151) - node T_153 = mux(T_113, UInt<4>("h0e"), T_152) - node T_154 = mux(T_111, UInt<4>("h0f"), T_153) - node T_155 = mux(T_109, UInt<5>("h010"), T_154) - node T_156 = mux(T_107, UInt<5>("h011"), T_155) - node T_157 = mux(T_105, UInt<5>("h012"), T_156) - node T_158 = mux(T_103, UInt<5>("h013"), T_157) - node T_159 = mux(T_101, UInt<5>("h014"), T_158) - node T_160 = mux(T_99, UInt<5>("h015"), T_159) - node T_161 = mux(T_97, UInt<5>("h016"), T_160) - node T_162 = mux(T_95, UInt<5>("h017"), T_161) - node T_163 = mux(T_93, UInt<5>("h018"), T_162) - node T_164 = mux(T_91, UInt<5>("h019"), T_163) - node T_165 = mux(T_89, UInt<5>("h01a"), T_164) - node T_166 = mux(T_87, UInt<5>("h01b"), T_165) - node T_167 = mux(T_85, UInt<5>("h01c"), T_166) - node T_168 = mux(T_83, UInt<5>("h01d"), T_167) - node T_169 = mux(T_81, UInt<5>("h01e"), T_168) - node T_170 = mux(T_79, UInt<5>("h01f"), T_169) - node T_171 = mux(T_77, UInt<6>("h020"), T_170) - node T_172 = mux(T_75, UInt<6>("h021"), T_171) - node T_173 = mux(T_73, UInt<6>("h022"), T_172) - node T_174 = mux(T_71, UInt<6>("h023"), T_173) - node T_175 = mux(T_69, UInt<6>("h024"), T_174) - node T_176 = mux(T_67, UInt<6>("h025"), T_175) - node T_177 = mux(T_65, UInt<6>("h026"), T_176) - node T_178 = mux(T_63, UInt<6>("h027"), T_177) - node T_179 = mux(T_61, UInt<6>("h028"), T_178) - node T_180 = mux(T_59, UInt<6>("h029"), T_179) - node T_181 = mux(T_57, UInt<6>("h02a"), T_180) - node T_182 = mux(T_55, UInt<6>("h02b"), T_181) - node T_183 = mux(T_53, UInt<6>("h02c"), T_182) - node T_184 = mux(T_51, UInt<6>("h02d"), T_183) - node T_185 = mux(T_49, UInt<6>("h02e"), T_184) - node T_186 = mux(T_47, UInt<6>("h02f"), T_185) - node T_187 = mux(T_45, UInt<6>("h030"), T_186) - node T_188 = mux(T_43, UInt<6>("h031"), T_187) - node T_189 = mux(T_41, UInt<6>("h032"), T_188) - node T_190 = mux(T_39, UInt<6>("h033"), T_189) - node T_191 = mux(T_37, UInt<6>("h034"), T_190) - node T_192 = mux(T_35, UInt<6>("h035"), T_191) - node T_193 = mux(T_33, UInt<6>("h036"), T_192) - node T_194 = mux(T_31, UInt<6>("h037"), T_193) - node T_195 = mux(T_29, UInt<6>("h038"), T_194) - node T_196 = mux(T_27, UInt<6>("h039"), T_195) - node T_197 = mux(T_25, UInt<6>("h03a"), T_196) - node T_198 = mux(T_23, UInt<6>("h03b"), T_197) - node T_199 = mux(T_21, UInt<6>("h03c"), T_198) - node T_200 = mux(T_19, UInt<6>("h03d"), T_199) - node T_201 = mux(T_17, UInt<6>("h03e"), T_200) - node T_202 = mux(T_15, UInt<6>("h03f"), T_201) - node normCount = not(T_202) - node T_204 = dshl(absIn, normCount) - node normAbsIn = bits(T_204, 63, 0) - node T_207 = bits(normAbsIn, 40, 39) - node T_208 = bits(normAbsIn, 38, 0) - node T_210 = neq(T_208, UInt<1>("h00")) - node roundBits = cat(T_207, T_210) - node T_212 = bits(roundBits, 1, 0) - node roundInexact = neq(T_212, UInt<1>("h00")) - node T_215 = eq(io.roundingMode, UInt<2>("h00")) - node T_216 = bits(roundBits, 2, 1) - node T_217 = not(T_216) - node T_219 = eq(T_217, UInt<1>("h00")) - node T_220 = bits(roundBits, 1, 0) - node T_221 = not(T_220) - node T_223 = eq(T_221, UInt<1>("h00")) - node T_224 = or(T_219, T_223) - node T_226 = mux(T_215, T_224, UInt<1>("h00")) - node T_227 = eq(io.roundingMode, UInt<2>("h02")) - node T_228 = and(sign, roundInexact) - node T_230 = mux(T_227, T_228, UInt<1>("h00")) - node T_231 = or(T_226, T_230) - node T_232 = eq(io.roundingMode, UInt<2>("h03")) - node T_234 = eq(sign, UInt<1>("h00")) - node T_235 = and(T_234, roundInexact) - node T_237 = mux(T_232, T_235, UInt<1>("h00")) - node round = or(T_231, T_237) - node T_240 = bits(normAbsIn, 63, 40) - node unroundedNorm = cat(UInt<1>("h00"), T_240) - node T_244 = addw(unroundedNorm, UInt<1>("h01")) - node roundedNorm = mux(round, T_244, unroundedNorm) - node T_247 = not(normCount) - node unroundedExp = cat(UInt<1>("h00"), T_247) - node T_251 = cat(UInt<1>("h00"), unroundedExp) - node T_252 = bit(roundedNorm, 24) - node roundedExp = addw(T_251, T_252) - node T_255 = bit(normAbsIn, 63) - node T_257 = bits(roundedExp, 7, 0) - node T_258 = mux(UInt<1>("h00"), UInt<8>("h080"), T_257) - node expOut = cat(T_255, T_258) + node T_12 = sub(UInt<1>("h00"), io.in) + node T_13 = tail(T_12, 1) + node absIn = mux(sign, T_13, io.in) + node T_15 = shl(absIn, 0) + node T_16 = bits(T_15, 63, 63) + node T_18 = bits(T_15, 62, 62) + node T_20 = bits(T_15, 61, 61) + node T_22 = bits(T_15, 60, 60) + node T_24 = bits(T_15, 59, 59) + node T_26 = bits(T_15, 58, 58) + node T_28 = bits(T_15, 57, 57) + node T_30 = bits(T_15, 56, 56) + node T_32 = bits(T_15, 55, 55) + node T_34 = bits(T_15, 54, 54) + node T_36 = bits(T_15, 53, 53) + node T_38 = bits(T_15, 52, 52) + node T_40 = bits(T_15, 51, 51) + node T_42 = bits(T_15, 50, 50) + node T_44 = bits(T_15, 49, 49) + node T_46 = bits(T_15, 48, 48) + node T_48 = bits(T_15, 47, 47) + node T_50 = bits(T_15, 46, 46) + node T_52 = bits(T_15, 45, 45) + node T_54 = bits(T_15, 44, 44) + node T_56 = bits(T_15, 43, 43) + node T_58 = bits(T_15, 42, 42) + node T_60 = bits(T_15, 41, 41) + node T_62 = bits(T_15, 40, 40) + node T_64 = bits(T_15, 39, 39) + node T_66 = bits(T_15, 38, 38) + node T_68 = bits(T_15, 37, 37) + node T_70 = bits(T_15, 36, 36) + node T_72 = bits(T_15, 35, 35) + node T_74 = bits(T_15, 34, 34) + node T_76 = bits(T_15, 33, 33) + node T_78 = bits(T_15, 32, 32) + node T_80 = bits(T_15, 31, 31) + node T_82 = bits(T_15, 30, 30) + node T_84 = bits(T_15, 29, 29) + node T_86 = bits(T_15, 28, 28) + node T_88 = bits(T_15, 27, 27) + node T_90 = bits(T_15, 26, 26) + node T_92 = bits(T_15, 25, 25) + node T_94 = bits(T_15, 24, 24) + node T_96 = bits(T_15, 23, 23) + node T_98 = bits(T_15, 22, 22) + node T_100 = bits(T_15, 21, 21) + node T_102 = bits(T_15, 20, 20) + node T_104 = bits(T_15, 19, 19) + node T_106 = bits(T_15, 18, 18) + node T_108 = bits(T_15, 17, 17) + node T_110 = bits(T_15, 16, 16) + node T_112 = bits(T_15, 15, 15) + node T_114 = bits(T_15, 14, 14) + node T_116 = bits(T_15, 13, 13) + node T_118 = bits(T_15, 12, 12) + node T_120 = bits(T_15, 11, 11) + node T_122 = bits(T_15, 10, 10) + node T_124 = bits(T_15, 9, 9) + node T_126 = bits(T_15, 8, 8) + node T_128 = bits(T_15, 7, 7) + node T_130 = bits(T_15, 6, 6) + node T_132 = bits(T_15, 5, 5) + node T_134 = bits(T_15, 4, 4) + node T_136 = bits(T_15, 3, 3) + node T_138 = bits(T_15, 2, 2) + node T_140 = bits(T_15, 1, 1) + node T_141 = shl(T_140, 0) + node T_142 = mux(T_138, UInt<2>("h02"), T_141) + node T_143 = mux(T_136, UInt<2>("h03"), T_142) + node T_144 = mux(T_134, UInt<3>("h04"), T_143) + node T_145 = mux(T_132, UInt<3>("h05"), T_144) + node T_146 = mux(T_130, UInt<3>("h06"), T_145) + node T_147 = mux(T_128, UInt<3>("h07"), T_146) + node T_148 = mux(T_126, UInt<4>("h08"), T_147) + node T_149 = mux(T_124, UInt<4>("h09"), T_148) + node T_150 = mux(T_122, UInt<4>("h0a"), T_149) + node T_151 = mux(T_120, UInt<4>("h0b"), T_150) + node T_152 = mux(T_118, UInt<4>("h0c"), T_151) + node T_153 = mux(T_116, UInt<4>("h0d"), T_152) + node T_154 = mux(T_114, UInt<4>("h0e"), T_153) + node T_155 = mux(T_112, UInt<4>("h0f"), T_154) + node T_156 = mux(T_110, UInt<5>("h010"), T_155) + node T_157 = mux(T_108, UInt<5>("h011"), T_156) + node T_158 = mux(T_106, UInt<5>("h012"), T_157) + node T_159 = mux(T_104, UInt<5>("h013"), T_158) + node T_160 = mux(T_102, UInt<5>("h014"), T_159) + node T_161 = mux(T_100, UInt<5>("h015"), T_160) + node T_162 = mux(T_98, UInt<5>("h016"), T_161) + node T_163 = mux(T_96, UInt<5>("h017"), T_162) + node T_164 = mux(T_94, UInt<5>("h018"), T_163) + node T_165 = mux(T_92, UInt<5>("h019"), T_164) + node T_166 = mux(T_90, UInt<5>("h01a"), T_165) + node T_167 = mux(T_88, UInt<5>("h01b"), T_166) + node T_168 = mux(T_86, UInt<5>("h01c"), T_167) + node T_169 = mux(T_84, UInt<5>("h01d"), T_168) + node T_170 = mux(T_82, UInt<5>("h01e"), T_169) + node T_171 = mux(T_80, UInt<5>("h01f"), T_170) + node T_172 = mux(T_78, UInt<6>("h020"), T_171) + node T_173 = mux(T_76, UInt<6>("h021"), T_172) + node T_174 = mux(T_74, UInt<6>("h022"), T_173) + node T_175 = mux(T_72, UInt<6>("h023"), T_174) + node T_176 = mux(T_70, UInt<6>("h024"), T_175) + node T_177 = mux(T_68, UInt<6>("h025"), T_176) + node T_178 = mux(T_66, UInt<6>("h026"), T_177) + node T_179 = mux(T_64, UInt<6>("h027"), T_178) + node T_180 = mux(T_62, UInt<6>("h028"), T_179) + node T_181 = mux(T_60, UInt<6>("h029"), T_180) + node T_182 = mux(T_58, UInt<6>("h02a"), T_181) + node T_183 = mux(T_56, UInt<6>("h02b"), T_182) + node T_184 = mux(T_54, UInt<6>("h02c"), T_183) + node T_185 = mux(T_52, UInt<6>("h02d"), T_184) + node T_186 = mux(T_50, UInt<6>("h02e"), T_185) + node T_187 = mux(T_48, UInt<6>("h02f"), T_186) + node T_188 = mux(T_46, UInt<6>("h030"), T_187) + node T_189 = mux(T_44, UInt<6>("h031"), T_188) + node T_190 = mux(T_42, UInt<6>("h032"), T_189) + node T_191 = mux(T_40, UInt<6>("h033"), T_190) + node T_192 = mux(T_38, UInt<6>("h034"), T_191) + node T_193 = mux(T_36, UInt<6>("h035"), T_192) + node T_194 = mux(T_34, UInt<6>("h036"), T_193) + node T_195 = mux(T_32, UInt<6>("h037"), T_194) + node T_196 = mux(T_30, UInt<6>("h038"), T_195) + node T_197 = mux(T_28, UInt<6>("h039"), T_196) + node T_198 = mux(T_26, UInt<6>("h03a"), T_197) + node T_199 = mux(T_24, UInt<6>("h03b"), T_198) + node T_200 = mux(T_22, UInt<6>("h03c"), T_199) + node T_201 = mux(T_20, UInt<6>("h03d"), T_200) + node T_202 = mux(T_18, UInt<6>("h03e"), T_201) + node T_203 = mux(T_16, UInt<6>("h03f"), T_202) + node normCount = not(T_203) + node T_205 = dshl(absIn, normCount) + node normAbsIn = bits(T_205, 63, 0) + node T_208 = bits(normAbsIn, 40, 39) + node T_209 = bits(normAbsIn, 38, 0) + node T_211 = neq(T_209, UInt<1>("h00")) + node roundBits = cat(T_208, T_211) + node T_213 = bits(roundBits, 1, 0) + node roundInexact = neq(T_213, UInt<1>("h00")) + node T_216 = eq(io.roundingMode, UInt<2>("h00")) + node T_217 = bits(roundBits, 2, 1) + node T_218 = not(T_217) + node T_220 = eq(T_218, UInt<1>("h00")) + node T_221 = bits(roundBits, 1, 0) + node T_222 = not(T_221) + node T_224 = eq(T_222, UInt<1>("h00")) + node T_225 = or(T_220, T_224) + node T_227 = mux(T_216, T_225, UInt<1>("h00")) + node T_228 = eq(io.roundingMode, UInt<2>("h02")) + node T_229 = and(sign, roundInexact) + node T_231 = mux(T_228, T_229, UInt<1>("h00")) + node T_232 = or(T_227, T_231) + node T_233 = eq(io.roundingMode, UInt<2>("h03")) + node T_235 = eq(sign, UInt<1>("h00")) + node T_236 = and(T_235, roundInexact) + node T_238 = mux(T_233, T_236, UInt<1>("h00")) + node round = or(T_232, T_238) + node T_241 = bits(normAbsIn, 63, 40) + node unroundedNorm = cat(UInt<1>("h00"), T_241) + node T_245 = add(unroundedNorm, UInt<1>("h01")) + node T_246 = tail(T_245, 1) + node roundedNorm = mux(round, T_246, unroundedNorm) + node T_249 = not(normCount) + node unroundedExp = cat(UInt<1>("h00"), T_249) + node T_253 = cat(UInt<1>("h00"), unroundedExp) + node T_254 = bits(roundedNorm, 24, 24) + node T_255 = add(T_253, T_254) + node roundedExp = tail(T_255, 1) + node T_258 = bits(normAbsIn, 63, 63) + node T_260 = bits(roundedExp, 7, 0) + node T_261 = mux(UInt<1>("h00"), UInt<8>("h080"), T_260) + node expOut = cat(T_258, T_261) node overflow = or(UInt<1>("h00"), UInt<1>("h00")) node inexact = or(roundInexact, overflow) - node T_262 = bits(roundedNorm, 22, 0) - node T_263 = cat(expOut, T_262) - node T_264 = cat(sign, T_263) - io.out <= T_264 - node T_267 = cat(UInt<2>("h00"), overflow) - node T_268 = cat(UInt<1>("h00"), inexact) - node T_269 = cat(T_267, T_268) - io.exceptionFlags <= T_269 + node T_265 = bits(roundedNorm, 22, 0) + node T_266 = cat(expOut, T_265) + node T_267 = cat(sign, T_266) + io.out <= T_267 + node T_270 = cat(UInt<2>("h00"), overflow) + node T_271 = cat(UInt<1>("h00"), inexact) + node T_272 = cat(T_270, T_271) + io.exceptionFlags <= T_272 module INToRecFN_119 : input clk : Clock input reset : UInt<1> output io : {flip signedIn : UInt<1>, flip in : UInt<64>, flip roundingMode : UInt<2>, out : UInt<65>, exceptionFlags : UInt<5>} - io.exceptionFlags <= UInt<1>("h00") - io.out <= UInt<1>("h00") - node T_9 = bit(io.in, 63) + io is invalid + node T_9 = bits(io.in, 63, 63) node sign = and(io.signedIn, T_9) - node T_12 = subw(UInt<1>("h00"), io.in) - node absIn = mux(sign, T_12, io.in) - node T_14 = shl(absIn, 0) - node T_15 = bit(T_14, 63) - node T_17 = bit(T_14, 62) - node T_19 = bit(T_14, 61) - node T_21 = bit(T_14, 60) - node T_23 = bit(T_14, 59) - node T_25 = bit(T_14, 58) - node T_27 = bit(T_14, 57) - node T_29 = bit(T_14, 56) - node T_31 = bit(T_14, 55) - node T_33 = bit(T_14, 54) - node T_35 = bit(T_14, 53) - node T_37 = bit(T_14, 52) - node T_39 = bit(T_14, 51) - node T_41 = bit(T_14, 50) - node T_43 = bit(T_14, 49) - node T_45 = bit(T_14, 48) - node T_47 = bit(T_14, 47) - node T_49 = bit(T_14, 46) - node T_51 = bit(T_14, 45) - node T_53 = bit(T_14, 44) - node T_55 = bit(T_14, 43) - node T_57 = bit(T_14, 42) - node T_59 = bit(T_14, 41) - node T_61 = bit(T_14, 40) - node T_63 = bit(T_14, 39) - node T_65 = bit(T_14, 38) - node T_67 = bit(T_14, 37) - node T_69 = bit(T_14, 36) - node T_71 = bit(T_14, 35) - node T_73 = bit(T_14, 34) - node T_75 = bit(T_14, 33) - node T_77 = bit(T_14, 32) - node T_79 = bit(T_14, 31) - node T_81 = bit(T_14, 30) - node T_83 = bit(T_14, 29) - node T_85 = bit(T_14, 28) - node T_87 = bit(T_14, 27) - node T_89 = bit(T_14, 26) - node T_91 = bit(T_14, 25) - node T_93 = bit(T_14, 24) - node T_95 = bit(T_14, 23) - node T_97 = bit(T_14, 22) - node T_99 = bit(T_14, 21) - node T_101 = bit(T_14, 20) - node T_103 = bit(T_14, 19) - node T_105 = bit(T_14, 18) - node T_107 = bit(T_14, 17) - node T_109 = bit(T_14, 16) - node T_111 = bit(T_14, 15) - node T_113 = bit(T_14, 14) - node T_115 = bit(T_14, 13) - node T_117 = bit(T_14, 12) - node T_119 = bit(T_14, 11) - node T_121 = bit(T_14, 10) - node T_123 = bit(T_14, 9) - node T_125 = bit(T_14, 8) - node T_127 = bit(T_14, 7) - node T_129 = bit(T_14, 6) - node T_131 = bit(T_14, 5) - node T_133 = bit(T_14, 4) - node T_135 = bit(T_14, 3) - node T_137 = bit(T_14, 2) - node T_139 = bit(T_14, 1) - node T_140 = shl(T_139, 0) - node T_141 = mux(T_137, UInt<2>("h02"), T_140) - node T_142 = mux(T_135, UInt<2>("h03"), T_141) - node T_143 = mux(T_133, UInt<3>("h04"), T_142) - node T_144 = mux(T_131, UInt<3>("h05"), T_143) - node T_145 = mux(T_129, UInt<3>("h06"), T_144) - node T_146 = mux(T_127, UInt<3>("h07"), T_145) - node T_147 = mux(T_125, UInt<4>("h08"), T_146) - node T_148 = mux(T_123, UInt<4>("h09"), T_147) - node T_149 = mux(T_121, UInt<4>("h0a"), T_148) - node T_150 = mux(T_119, UInt<4>("h0b"), T_149) - node T_151 = mux(T_117, UInt<4>("h0c"), T_150) - node T_152 = mux(T_115, UInt<4>("h0d"), T_151) - node T_153 = mux(T_113, UInt<4>("h0e"), T_152) - node T_154 = mux(T_111, UInt<4>("h0f"), T_153) - node T_155 = mux(T_109, UInt<5>("h010"), T_154) - node T_156 = mux(T_107, UInt<5>("h011"), T_155) - node T_157 = mux(T_105, UInt<5>("h012"), T_156) - node T_158 = mux(T_103, UInt<5>("h013"), T_157) - node T_159 = mux(T_101, UInt<5>("h014"), T_158) - node T_160 = mux(T_99, UInt<5>("h015"), T_159) - node T_161 = mux(T_97, UInt<5>("h016"), T_160) - node T_162 = mux(T_95, UInt<5>("h017"), T_161) - node T_163 = mux(T_93, UInt<5>("h018"), T_162) - node T_164 = mux(T_91, UInt<5>("h019"), T_163) - node T_165 = mux(T_89, UInt<5>("h01a"), T_164) - node T_166 = mux(T_87, UInt<5>("h01b"), T_165) - node T_167 = mux(T_85, UInt<5>("h01c"), T_166) - node T_168 = mux(T_83, UInt<5>("h01d"), T_167) - node T_169 = mux(T_81, UInt<5>("h01e"), T_168) - node T_170 = mux(T_79, UInt<5>("h01f"), T_169) - node T_171 = mux(T_77, UInt<6>("h020"), T_170) - node T_172 = mux(T_75, UInt<6>("h021"), T_171) - node T_173 = mux(T_73, UInt<6>("h022"), T_172) - node T_174 = mux(T_71, UInt<6>("h023"), T_173) - node T_175 = mux(T_69, UInt<6>("h024"), T_174) - node T_176 = mux(T_67, UInt<6>("h025"), T_175) - node T_177 = mux(T_65, UInt<6>("h026"), T_176) - node T_178 = mux(T_63, UInt<6>("h027"), T_177) - node T_179 = mux(T_61, UInt<6>("h028"), T_178) - node T_180 = mux(T_59, UInt<6>("h029"), T_179) - node T_181 = mux(T_57, UInt<6>("h02a"), T_180) - node T_182 = mux(T_55, UInt<6>("h02b"), T_181) - node T_183 = mux(T_53, UInt<6>("h02c"), T_182) - node T_184 = mux(T_51, UInt<6>("h02d"), T_183) - node T_185 = mux(T_49, UInt<6>("h02e"), T_184) - node T_186 = mux(T_47, UInt<6>("h02f"), T_185) - node T_187 = mux(T_45, UInt<6>("h030"), T_186) - node T_188 = mux(T_43, UInt<6>("h031"), T_187) - node T_189 = mux(T_41, UInt<6>("h032"), T_188) - node T_190 = mux(T_39, UInt<6>("h033"), T_189) - node T_191 = mux(T_37, UInt<6>("h034"), T_190) - node T_192 = mux(T_35, UInt<6>("h035"), T_191) - node T_193 = mux(T_33, UInt<6>("h036"), T_192) - node T_194 = mux(T_31, UInt<6>("h037"), T_193) - node T_195 = mux(T_29, UInt<6>("h038"), T_194) - node T_196 = mux(T_27, UInt<6>("h039"), T_195) - node T_197 = mux(T_25, UInt<6>("h03a"), T_196) - node T_198 = mux(T_23, UInt<6>("h03b"), T_197) - node T_199 = mux(T_21, UInt<6>("h03c"), T_198) - node T_200 = mux(T_19, UInt<6>("h03d"), T_199) - node T_201 = mux(T_17, UInt<6>("h03e"), T_200) - node T_202 = mux(T_15, UInt<6>("h03f"), T_201) - node normCount = not(T_202) - node T_204 = dshl(absIn, normCount) - node normAbsIn = bits(T_204, 63, 0) - node T_207 = bits(normAbsIn, 11, 10) - node T_208 = bits(normAbsIn, 9, 0) - node T_210 = neq(T_208, UInt<1>("h00")) - node roundBits = cat(T_207, T_210) - node T_212 = bits(roundBits, 1, 0) - node roundInexact = neq(T_212, UInt<1>("h00")) - node T_215 = eq(io.roundingMode, UInt<2>("h00")) - node T_216 = bits(roundBits, 2, 1) - node T_217 = not(T_216) - node T_219 = eq(T_217, UInt<1>("h00")) - node T_220 = bits(roundBits, 1, 0) - node T_221 = not(T_220) - node T_223 = eq(T_221, UInt<1>("h00")) - node T_224 = or(T_219, T_223) - node T_226 = mux(T_215, T_224, UInt<1>("h00")) - node T_227 = eq(io.roundingMode, UInt<2>("h02")) - node T_228 = and(sign, roundInexact) - node T_230 = mux(T_227, T_228, UInt<1>("h00")) - node T_231 = or(T_226, T_230) - node T_232 = eq(io.roundingMode, UInt<2>("h03")) - node T_234 = eq(sign, UInt<1>("h00")) - node T_235 = and(T_234, roundInexact) - node T_237 = mux(T_232, T_235, UInt<1>("h00")) - node round = or(T_231, T_237) - node T_240 = bits(normAbsIn, 63, 11) - node unroundedNorm = cat(UInt<1>("h00"), T_240) - node T_244 = addw(unroundedNorm, UInt<1>("h01")) - node roundedNorm = mux(round, T_244, unroundedNorm) - node T_247 = not(normCount) - node unroundedExp = cat(UInt<4>("h00"), T_247) - node T_251 = cat(UInt<1>("h00"), unroundedExp) - node T_252 = bit(roundedNorm, 53) - node roundedExp = addw(T_251, T_252) - node T_255 = bit(normAbsIn, 63) - node T_257 = bits(roundedExp, 10, 0) - node T_258 = mux(UInt<1>("h00"), UInt<11>("h0400"), T_257) - node expOut = cat(T_255, T_258) + node T_12 = sub(UInt<1>("h00"), io.in) + node T_13 = tail(T_12, 1) + node absIn = mux(sign, T_13, io.in) + node T_15 = shl(absIn, 0) + node T_16 = bits(T_15, 63, 63) + node T_18 = bits(T_15, 62, 62) + node T_20 = bits(T_15, 61, 61) + node T_22 = bits(T_15, 60, 60) + node T_24 = bits(T_15, 59, 59) + node T_26 = bits(T_15, 58, 58) + node T_28 = bits(T_15, 57, 57) + node T_30 = bits(T_15, 56, 56) + node T_32 = bits(T_15, 55, 55) + node T_34 = bits(T_15, 54, 54) + node T_36 = bits(T_15, 53, 53) + node T_38 = bits(T_15, 52, 52) + node T_40 = bits(T_15, 51, 51) + node T_42 = bits(T_15, 50, 50) + node T_44 = bits(T_15, 49, 49) + node T_46 = bits(T_15, 48, 48) + node T_48 = bits(T_15, 47, 47) + node T_50 = bits(T_15, 46, 46) + node T_52 = bits(T_15, 45, 45) + node T_54 = bits(T_15, 44, 44) + node T_56 = bits(T_15, 43, 43) + node T_58 = bits(T_15, 42, 42) + node T_60 = bits(T_15, 41, 41) + node T_62 = bits(T_15, 40, 40) + node T_64 = bits(T_15, 39, 39) + node T_66 = bits(T_15, 38, 38) + node T_68 = bits(T_15, 37, 37) + node T_70 = bits(T_15, 36, 36) + node T_72 = bits(T_15, 35, 35) + node T_74 = bits(T_15, 34, 34) + node T_76 = bits(T_15, 33, 33) + node T_78 = bits(T_15, 32, 32) + node T_80 = bits(T_15, 31, 31) + node T_82 = bits(T_15, 30, 30) + node T_84 = bits(T_15, 29, 29) + node T_86 = bits(T_15, 28, 28) + node T_88 = bits(T_15, 27, 27) + node T_90 = bits(T_15, 26, 26) + node T_92 = bits(T_15, 25, 25) + node T_94 = bits(T_15, 24, 24) + node T_96 = bits(T_15, 23, 23) + node T_98 = bits(T_15, 22, 22) + node T_100 = bits(T_15, 21, 21) + node T_102 = bits(T_15, 20, 20) + node T_104 = bits(T_15, 19, 19) + node T_106 = bits(T_15, 18, 18) + node T_108 = bits(T_15, 17, 17) + node T_110 = bits(T_15, 16, 16) + node T_112 = bits(T_15, 15, 15) + node T_114 = bits(T_15, 14, 14) + node T_116 = bits(T_15, 13, 13) + node T_118 = bits(T_15, 12, 12) + node T_120 = bits(T_15, 11, 11) + node T_122 = bits(T_15, 10, 10) + node T_124 = bits(T_15, 9, 9) + node T_126 = bits(T_15, 8, 8) + node T_128 = bits(T_15, 7, 7) + node T_130 = bits(T_15, 6, 6) + node T_132 = bits(T_15, 5, 5) + node T_134 = bits(T_15, 4, 4) + node T_136 = bits(T_15, 3, 3) + node T_138 = bits(T_15, 2, 2) + node T_140 = bits(T_15, 1, 1) + node T_141 = shl(T_140, 0) + node T_142 = mux(T_138, UInt<2>("h02"), T_141) + node T_143 = mux(T_136, UInt<2>("h03"), T_142) + node T_144 = mux(T_134, UInt<3>("h04"), T_143) + node T_145 = mux(T_132, UInt<3>("h05"), T_144) + node T_146 = mux(T_130, UInt<3>("h06"), T_145) + node T_147 = mux(T_128, UInt<3>("h07"), T_146) + node T_148 = mux(T_126, UInt<4>("h08"), T_147) + node T_149 = mux(T_124, UInt<4>("h09"), T_148) + node T_150 = mux(T_122, UInt<4>("h0a"), T_149) + node T_151 = mux(T_120, UInt<4>("h0b"), T_150) + node T_152 = mux(T_118, UInt<4>("h0c"), T_151) + node T_153 = mux(T_116, UInt<4>("h0d"), T_152) + node T_154 = mux(T_114, UInt<4>("h0e"), T_153) + node T_155 = mux(T_112, UInt<4>("h0f"), T_154) + node T_156 = mux(T_110, UInt<5>("h010"), T_155) + node T_157 = mux(T_108, UInt<5>("h011"), T_156) + node T_158 = mux(T_106, UInt<5>("h012"), T_157) + node T_159 = mux(T_104, UInt<5>("h013"), T_158) + node T_160 = mux(T_102, UInt<5>("h014"), T_159) + node T_161 = mux(T_100, UInt<5>("h015"), T_160) + node T_162 = mux(T_98, UInt<5>("h016"), T_161) + node T_163 = mux(T_96, UInt<5>("h017"), T_162) + node T_164 = mux(T_94, UInt<5>("h018"), T_163) + node T_165 = mux(T_92, UInt<5>("h019"), T_164) + node T_166 = mux(T_90, UInt<5>("h01a"), T_165) + node T_167 = mux(T_88, UInt<5>("h01b"), T_166) + node T_168 = mux(T_86, UInt<5>("h01c"), T_167) + node T_169 = mux(T_84, UInt<5>("h01d"), T_168) + node T_170 = mux(T_82, UInt<5>("h01e"), T_169) + node T_171 = mux(T_80, UInt<5>("h01f"), T_170) + node T_172 = mux(T_78, UInt<6>("h020"), T_171) + node T_173 = mux(T_76, UInt<6>("h021"), T_172) + node T_174 = mux(T_74, UInt<6>("h022"), T_173) + node T_175 = mux(T_72, UInt<6>("h023"), T_174) + node T_176 = mux(T_70, UInt<6>("h024"), T_175) + node T_177 = mux(T_68, UInt<6>("h025"), T_176) + node T_178 = mux(T_66, UInt<6>("h026"), T_177) + node T_179 = mux(T_64, UInt<6>("h027"), T_178) + node T_180 = mux(T_62, UInt<6>("h028"), T_179) + node T_181 = mux(T_60, UInt<6>("h029"), T_180) + node T_182 = mux(T_58, UInt<6>("h02a"), T_181) + node T_183 = mux(T_56, UInt<6>("h02b"), T_182) + node T_184 = mux(T_54, UInt<6>("h02c"), T_183) + node T_185 = mux(T_52, UInt<6>("h02d"), T_184) + node T_186 = mux(T_50, UInt<6>("h02e"), T_185) + node T_187 = mux(T_48, UInt<6>("h02f"), T_186) + node T_188 = mux(T_46, UInt<6>("h030"), T_187) + node T_189 = mux(T_44, UInt<6>("h031"), T_188) + node T_190 = mux(T_42, UInt<6>("h032"), T_189) + node T_191 = mux(T_40, UInt<6>("h033"), T_190) + node T_192 = mux(T_38, UInt<6>("h034"), T_191) + node T_193 = mux(T_36, UInt<6>("h035"), T_192) + node T_194 = mux(T_34, UInt<6>("h036"), T_193) + node T_195 = mux(T_32, UInt<6>("h037"), T_194) + node T_196 = mux(T_30, UInt<6>("h038"), T_195) + node T_197 = mux(T_28, UInt<6>("h039"), T_196) + node T_198 = mux(T_26, UInt<6>("h03a"), T_197) + node T_199 = mux(T_24, UInt<6>("h03b"), T_198) + node T_200 = mux(T_22, UInt<6>("h03c"), T_199) + node T_201 = mux(T_20, UInt<6>("h03d"), T_200) + node T_202 = mux(T_18, UInt<6>("h03e"), T_201) + node T_203 = mux(T_16, UInt<6>("h03f"), T_202) + node normCount = not(T_203) + node T_205 = dshl(absIn, normCount) + node normAbsIn = bits(T_205, 63, 0) + node T_208 = bits(normAbsIn, 11, 10) + node T_209 = bits(normAbsIn, 9, 0) + node T_211 = neq(T_209, UInt<1>("h00")) + node roundBits = cat(T_208, T_211) + node T_213 = bits(roundBits, 1, 0) + node roundInexact = neq(T_213, UInt<1>("h00")) + node T_216 = eq(io.roundingMode, UInt<2>("h00")) + node T_217 = bits(roundBits, 2, 1) + node T_218 = not(T_217) + node T_220 = eq(T_218, UInt<1>("h00")) + node T_221 = bits(roundBits, 1, 0) + node T_222 = not(T_221) + node T_224 = eq(T_222, UInt<1>("h00")) + node T_225 = or(T_220, T_224) + node T_227 = mux(T_216, T_225, UInt<1>("h00")) + node T_228 = eq(io.roundingMode, UInt<2>("h02")) + node T_229 = and(sign, roundInexact) + node T_231 = mux(T_228, T_229, UInt<1>("h00")) + node T_232 = or(T_227, T_231) + node T_233 = eq(io.roundingMode, UInt<2>("h03")) + node T_235 = eq(sign, UInt<1>("h00")) + node T_236 = and(T_235, roundInexact) + node T_238 = mux(T_233, T_236, UInt<1>("h00")) + node round = or(T_232, T_238) + node T_241 = bits(normAbsIn, 63, 11) + node unroundedNorm = cat(UInt<1>("h00"), T_241) + node T_245 = add(unroundedNorm, UInt<1>("h01")) + node T_246 = tail(T_245, 1) + node roundedNorm = mux(round, T_246, unroundedNorm) + node T_249 = not(normCount) + node unroundedExp = cat(UInt<4>("h00"), T_249) + node T_253 = cat(UInt<1>("h00"), unroundedExp) + node T_254 = bits(roundedNorm, 53, 53) + node T_255 = add(T_253, T_254) + node roundedExp = tail(T_255, 1) + node T_258 = bits(normAbsIn, 63, 63) + node T_260 = bits(roundedExp, 10, 0) + node T_261 = mux(UInt<1>("h00"), UInt<11>("h0400"), T_260) + node expOut = cat(T_258, T_261) node overflow = or(UInt<1>("h00"), UInt<1>("h00")) node inexact = or(roundInexact, overflow) - node T_262 = bits(roundedNorm, 51, 0) - node T_263 = cat(expOut, T_262) - node T_264 = cat(sign, T_263) - io.out <= T_264 - node T_267 = cat(UInt<2>("h00"), overflow) - node T_268 = cat(UInt<1>("h00"), inexact) - node T_269 = cat(T_267, T_268) - io.exceptionFlags <= T_269 + node T_265 = bits(roundedNorm, 51, 0) + node T_266 = cat(expOut, T_265) + node T_267 = cat(sign, T_266) + io.out <= T_267 + node T_270 = cat(UInt<2>("h00"), overflow) + node T_271 = cat(UInt<1>("h00"), inexact) + node T_272 = cat(T_270, T_271) + io.exceptionFlags <= T_272 module IntToFP : input clk : Clock input reset : UInt<1> output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} - io.out.bits.exc <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - reg T_136 : UInt<1>, clk, reset, UInt<1>("h00") + io is invalid + reg T_136 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) T_136 <= io.in.valid - reg T_137 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk, UInt<1>("h00"), T_137 + reg T_137 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk when io.in.valid : T_137 <- io.in.bits skip wire in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} - in.bits.in3 <= UInt<1>("h00") - in.bits.in2 <= UInt<1>("h00") - in.bits.in1 <= UInt<1>("h00") - in.bits.typ <= UInt<1>("h00") - in.bits.rm <= UInt<1>("h00") - in.bits.wflags <= UInt<1>("h00") - in.bits.round <= UInt<1>("h00") - in.bits.sqrt <= UInt<1>("h00") - in.bits.div <= UInt<1>("h00") - in.bits.fma <= UInt<1>("h00") - in.bits.fastpipe <= UInt<1>("h00") - in.bits.toint <= UInt<1>("h00") - in.bits.fromint <= UInt<1>("h00") - in.bits.single <= UInt<1>("h00") - in.bits.swap23 <= UInt<1>("h00") - in.bits.swap12 <= UInt<1>("h00") - in.bits.ren3 <= UInt<1>("h00") - in.bits.ren2 <= UInt<1>("h00") - in.bits.ren1 <= UInt<1>("h00") - in.bits.wen <= UInt<1>("h00") - in.bits.ldst <= UInt<1>("h00") - in.bits.cmd <= UInt<1>("h00") - in.valid <= UInt<1>("h00") + in is invalid in.valid <= T_136 in.bits <- T_137 wire mux : {data : UInt<65>, exc : UInt<5>} + mux is invalid mux.exc <= UInt<1>("h00") - mux.data <= UInt<1>("h00") - mux.exc <= UInt<1>("h00") - node T_288 = bit(in.bits.in1, 63) - node T_289 = bits(in.bits.in1, 62, 52) - node T_290 = bits(in.bits.in1, 51, 0) - node T_292 = eq(T_289, UInt<1>("h00")) - node T_294 = eq(T_290, UInt<1>("h00")) - node T_295 = and(T_292, T_294) - node T_296 = shl(T_290, 12) - node T_297 = bit(T_296, 63) - node T_299 = bit(T_296, 62) - node T_301 = bit(T_296, 61) - node T_303 = bit(T_296, 60) - node T_305 = bit(T_296, 59) - node T_307 = bit(T_296, 58) - node T_309 = bit(T_296, 57) - node T_311 = bit(T_296, 56) - node T_313 = bit(T_296, 55) - node T_315 = bit(T_296, 54) - node T_317 = bit(T_296, 53) - node T_319 = bit(T_296, 52) - node T_321 = bit(T_296, 51) - node T_323 = bit(T_296, 50) - node T_325 = bit(T_296, 49) - node T_327 = bit(T_296, 48) - node T_329 = bit(T_296, 47) - node T_331 = bit(T_296, 46) - node T_333 = bit(T_296, 45) - node T_335 = bit(T_296, 44) - node T_337 = bit(T_296, 43) - node T_339 = bit(T_296, 42) - node T_341 = bit(T_296, 41) - node T_343 = bit(T_296, 40) - node T_345 = bit(T_296, 39) - node T_347 = bit(T_296, 38) - node T_349 = bit(T_296, 37) - node T_351 = bit(T_296, 36) - node T_353 = bit(T_296, 35) - node T_355 = bit(T_296, 34) - node T_357 = bit(T_296, 33) - node T_359 = bit(T_296, 32) - node T_361 = bit(T_296, 31) - node T_363 = bit(T_296, 30) - node T_365 = bit(T_296, 29) - node T_367 = bit(T_296, 28) - node T_369 = bit(T_296, 27) - node T_371 = bit(T_296, 26) - node T_373 = bit(T_296, 25) - node T_375 = bit(T_296, 24) - node T_377 = bit(T_296, 23) - node T_379 = bit(T_296, 22) - node T_381 = bit(T_296, 21) - node T_383 = bit(T_296, 20) - node T_385 = bit(T_296, 19) - node T_387 = bit(T_296, 18) - node T_389 = bit(T_296, 17) - node T_391 = bit(T_296, 16) - node T_393 = bit(T_296, 15) - node T_395 = bit(T_296, 14) - node T_397 = bit(T_296, 13) - node T_399 = bit(T_296, 12) - node T_401 = bit(T_296, 11) - node T_403 = bit(T_296, 10) - node T_405 = bit(T_296, 9) - node T_407 = bit(T_296, 8) - node T_409 = bit(T_296, 7) - node T_411 = bit(T_296, 6) - node T_413 = bit(T_296, 5) - node T_415 = bit(T_296, 4) - node T_417 = bit(T_296, 3) - node T_419 = bit(T_296, 2) - node T_421 = bit(T_296, 1) - node T_422 = shl(T_421, 0) - node T_423 = mux(T_419, UInt<2>("h02"), T_422) - node T_424 = mux(T_417, UInt<2>("h03"), T_423) - node T_425 = mux(T_415, UInt<3>("h04"), T_424) - node T_426 = mux(T_413, UInt<3>("h05"), T_425) - node T_427 = mux(T_411, UInt<3>("h06"), T_426) - node T_428 = mux(T_409, UInt<3>("h07"), T_427) - node T_429 = mux(T_407, UInt<4>("h08"), T_428) - node T_430 = mux(T_405, UInt<4>("h09"), T_429) - node T_431 = mux(T_403, UInt<4>("h0a"), T_430) - node T_432 = mux(T_401, UInt<4>("h0b"), T_431) - node T_433 = mux(T_399, UInt<4>("h0c"), T_432) - node T_434 = mux(T_397, UInt<4>("h0d"), T_433) - node T_435 = mux(T_395, UInt<4>("h0e"), T_434) - node T_436 = mux(T_393, UInt<4>("h0f"), T_435) - node T_437 = mux(T_391, UInt<5>("h010"), T_436) - node T_438 = mux(T_389, UInt<5>("h011"), T_437) - node T_439 = mux(T_387, UInt<5>("h012"), T_438) - node T_440 = mux(T_385, UInt<5>("h013"), T_439) - node T_441 = mux(T_383, UInt<5>("h014"), T_440) - node T_442 = mux(T_381, UInt<5>("h015"), T_441) - node T_443 = mux(T_379, UInt<5>("h016"), T_442) - node T_444 = mux(T_377, UInt<5>("h017"), T_443) - node T_445 = mux(T_375, UInt<5>("h018"), T_444) - node T_446 = mux(T_373, UInt<5>("h019"), T_445) - node T_447 = mux(T_371, UInt<5>("h01a"), T_446) - node T_448 = mux(T_369, UInt<5>("h01b"), T_447) - node T_449 = mux(T_367, UInt<5>("h01c"), T_448) - node T_450 = mux(T_365, UInt<5>("h01d"), T_449) - node T_451 = mux(T_363, UInt<5>("h01e"), T_450) - node T_452 = mux(T_361, UInt<5>("h01f"), T_451) - node T_453 = mux(T_359, UInt<6>("h020"), T_452) - node T_454 = mux(T_357, UInt<6>("h021"), T_453) - node T_455 = mux(T_355, UInt<6>("h022"), T_454) - node T_456 = mux(T_353, UInt<6>("h023"), T_455) - node T_457 = mux(T_351, UInt<6>("h024"), T_456) - node T_458 = mux(T_349, UInt<6>("h025"), T_457) - node T_459 = mux(T_347, UInt<6>("h026"), T_458) - node T_460 = mux(T_345, UInt<6>("h027"), T_459) - node T_461 = mux(T_343, UInt<6>("h028"), T_460) - node T_462 = mux(T_341, UInt<6>("h029"), T_461) - node T_463 = mux(T_339, UInt<6>("h02a"), T_462) - node T_464 = mux(T_337, UInt<6>("h02b"), T_463) - node T_465 = mux(T_335, UInt<6>("h02c"), T_464) - node T_466 = mux(T_333, UInt<6>("h02d"), T_465) - node T_467 = mux(T_331, UInt<6>("h02e"), T_466) - node T_468 = mux(T_329, UInt<6>("h02f"), T_467) - node T_469 = mux(T_327, UInt<6>("h030"), T_468) - node T_470 = mux(T_325, UInt<6>("h031"), T_469) - node T_471 = mux(T_323, UInt<6>("h032"), T_470) - node T_472 = mux(T_321, UInt<6>("h033"), T_471) - node T_473 = mux(T_319, UInt<6>("h034"), T_472) - node T_474 = mux(T_317, UInt<6>("h035"), T_473) - node T_475 = mux(T_315, UInt<6>("h036"), T_474) - node T_476 = mux(T_313, UInt<6>("h037"), T_475) - node T_477 = mux(T_311, UInt<6>("h038"), T_476) - node T_478 = mux(T_309, UInt<6>("h039"), T_477) - node T_479 = mux(T_307, UInt<6>("h03a"), T_478) - node T_480 = mux(T_305, UInt<6>("h03b"), T_479) - node T_481 = mux(T_303, UInt<6>("h03c"), T_480) - node T_482 = mux(T_301, UInt<6>("h03d"), T_481) - node T_483 = mux(T_299, UInt<6>("h03e"), T_482) - node T_484 = mux(T_297, UInt<6>("h03f"), T_483) - node T_485 = not(T_484) - node T_486 = dshl(T_290, T_485) - node T_487 = bits(T_486, 50, 0) - node T_489 = cat(T_487, UInt<1>("h00")) - node T_492 = subw(UInt<12>("h00"), UInt<1>("h01")) - node T_493 = xor(T_485, T_492) - node T_494 = mux(T_292, T_493, T_289) - node T_498 = mux(T_292, UInt<2>("h02"), UInt<1>("h01")) - node T_499 = or(UInt<11>("h0400"), T_498) - node T_500 = addw(T_494, T_499) - node T_501 = bits(T_500, 11, 10) - node T_503 = eq(T_501, UInt<2>("h03")) - node T_505 = eq(T_294, UInt<1>("h00")) - node T_506 = and(T_503, T_505) - node T_508 = subw(UInt<3>("h00"), T_295) - node T_509 = shl(T_508, 9) - node T_510 = not(T_509) - node T_511 = and(T_500, T_510) - node T_512 = shl(T_506, 9) - node T_513 = or(T_511, T_512) - node T_514 = mux(T_292, T_489, T_290) - node T_515 = cat(T_513, T_514) - node T_516 = cat(T_288, T_515) - mux.data <= T_516 + node T_263 = bits(in.bits.in1, 63, 63) + node T_264 = bits(in.bits.in1, 62, 52) + node T_265 = bits(in.bits.in1, 51, 0) + node T_267 = eq(T_264, UInt<1>("h00")) + node T_269 = eq(T_265, UInt<1>("h00")) + node T_270 = and(T_267, T_269) + node T_271 = shl(T_265, 12) + node T_272 = bits(T_271, 63, 63) + node T_274 = bits(T_271, 62, 62) + node T_276 = bits(T_271, 61, 61) + node T_278 = bits(T_271, 60, 60) + node T_280 = bits(T_271, 59, 59) + node T_282 = bits(T_271, 58, 58) + node T_284 = bits(T_271, 57, 57) + node T_286 = bits(T_271, 56, 56) + node T_288 = bits(T_271, 55, 55) + node T_290 = bits(T_271, 54, 54) + node T_292 = bits(T_271, 53, 53) + node T_294 = bits(T_271, 52, 52) + node T_296 = bits(T_271, 51, 51) + node T_298 = bits(T_271, 50, 50) + node T_300 = bits(T_271, 49, 49) + node T_302 = bits(T_271, 48, 48) + node T_304 = bits(T_271, 47, 47) + node T_306 = bits(T_271, 46, 46) + node T_308 = bits(T_271, 45, 45) + node T_310 = bits(T_271, 44, 44) + node T_312 = bits(T_271, 43, 43) + node T_314 = bits(T_271, 42, 42) + node T_316 = bits(T_271, 41, 41) + node T_318 = bits(T_271, 40, 40) + node T_320 = bits(T_271, 39, 39) + node T_322 = bits(T_271, 38, 38) + node T_324 = bits(T_271, 37, 37) + node T_326 = bits(T_271, 36, 36) + node T_328 = bits(T_271, 35, 35) + node T_330 = bits(T_271, 34, 34) + node T_332 = bits(T_271, 33, 33) + node T_334 = bits(T_271, 32, 32) + node T_336 = bits(T_271, 31, 31) + node T_338 = bits(T_271, 30, 30) + node T_340 = bits(T_271, 29, 29) + node T_342 = bits(T_271, 28, 28) + node T_344 = bits(T_271, 27, 27) + node T_346 = bits(T_271, 26, 26) + node T_348 = bits(T_271, 25, 25) + node T_350 = bits(T_271, 24, 24) + node T_352 = bits(T_271, 23, 23) + node T_354 = bits(T_271, 22, 22) + node T_356 = bits(T_271, 21, 21) + node T_358 = bits(T_271, 20, 20) + node T_360 = bits(T_271, 19, 19) + node T_362 = bits(T_271, 18, 18) + node T_364 = bits(T_271, 17, 17) + node T_366 = bits(T_271, 16, 16) + node T_368 = bits(T_271, 15, 15) + node T_370 = bits(T_271, 14, 14) + node T_372 = bits(T_271, 13, 13) + node T_374 = bits(T_271, 12, 12) + node T_376 = bits(T_271, 11, 11) + node T_378 = bits(T_271, 10, 10) + node T_380 = bits(T_271, 9, 9) + node T_382 = bits(T_271, 8, 8) + node T_384 = bits(T_271, 7, 7) + node T_386 = bits(T_271, 6, 6) + node T_388 = bits(T_271, 5, 5) + node T_390 = bits(T_271, 4, 4) + node T_392 = bits(T_271, 3, 3) + node T_394 = bits(T_271, 2, 2) + node T_396 = bits(T_271, 1, 1) + node T_397 = shl(T_396, 0) + node T_398 = mux(T_394, UInt<2>("h02"), T_397) + node T_399 = mux(T_392, UInt<2>("h03"), T_398) + node T_400 = mux(T_390, UInt<3>("h04"), T_399) + node T_401 = mux(T_388, UInt<3>("h05"), T_400) + node T_402 = mux(T_386, UInt<3>("h06"), T_401) + node T_403 = mux(T_384, UInt<3>("h07"), T_402) + node T_404 = mux(T_382, UInt<4>("h08"), T_403) + node T_405 = mux(T_380, UInt<4>("h09"), T_404) + node T_406 = mux(T_378, UInt<4>("h0a"), T_405) + node T_407 = mux(T_376, UInt<4>("h0b"), T_406) + node T_408 = mux(T_374, UInt<4>("h0c"), T_407) + node T_409 = mux(T_372, UInt<4>("h0d"), T_408) + node T_410 = mux(T_370, UInt<4>("h0e"), T_409) + node T_411 = mux(T_368, UInt<4>("h0f"), T_410) + node T_412 = mux(T_366, UInt<5>("h010"), T_411) + node T_413 = mux(T_364, UInt<5>("h011"), T_412) + node T_414 = mux(T_362, UInt<5>("h012"), T_413) + node T_415 = mux(T_360, UInt<5>("h013"), T_414) + node T_416 = mux(T_358, UInt<5>("h014"), T_415) + node T_417 = mux(T_356, UInt<5>("h015"), T_416) + node T_418 = mux(T_354, UInt<5>("h016"), T_417) + node T_419 = mux(T_352, UInt<5>("h017"), T_418) + node T_420 = mux(T_350, UInt<5>("h018"), T_419) + node T_421 = mux(T_348, UInt<5>("h019"), T_420) + node T_422 = mux(T_346, UInt<5>("h01a"), T_421) + node T_423 = mux(T_344, UInt<5>("h01b"), T_422) + node T_424 = mux(T_342, UInt<5>("h01c"), T_423) + node T_425 = mux(T_340, UInt<5>("h01d"), T_424) + node T_426 = mux(T_338, UInt<5>("h01e"), T_425) + node T_427 = mux(T_336, UInt<5>("h01f"), T_426) + node T_428 = mux(T_334, UInt<6>("h020"), T_427) + node T_429 = mux(T_332, UInt<6>("h021"), T_428) + node T_430 = mux(T_330, UInt<6>("h022"), T_429) + node T_431 = mux(T_328, UInt<6>("h023"), T_430) + node T_432 = mux(T_326, UInt<6>("h024"), T_431) + node T_433 = mux(T_324, UInt<6>("h025"), T_432) + node T_434 = mux(T_322, UInt<6>("h026"), T_433) + node T_435 = mux(T_320, UInt<6>("h027"), T_434) + node T_436 = mux(T_318, UInt<6>("h028"), T_435) + node T_437 = mux(T_316, UInt<6>("h029"), T_436) + node T_438 = mux(T_314, UInt<6>("h02a"), T_437) + node T_439 = mux(T_312, UInt<6>("h02b"), T_438) + node T_440 = mux(T_310, UInt<6>("h02c"), T_439) + node T_441 = mux(T_308, UInt<6>("h02d"), T_440) + node T_442 = mux(T_306, UInt<6>("h02e"), T_441) + node T_443 = mux(T_304, UInt<6>("h02f"), T_442) + node T_444 = mux(T_302, UInt<6>("h030"), T_443) + node T_445 = mux(T_300, UInt<6>("h031"), T_444) + node T_446 = mux(T_298, UInt<6>("h032"), T_445) + node T_447 = mux(T_296, UInt<6>("h033"), T_446) + node T_448 = mux(T_294, UInt<6>("h034"), T_447) + node T_449 = mux(T_292, UInt<6>("h035"), T_448) + node T_450 = mux(T_290, UInt<6>("h036"), T_449) + node T_451 = mux(T_288, UInt<6>("h037"), T_450) + node T_452 = mux(T_286, UInt<6>("h038"), T_451) + node T_453 = mux(T_284, UInt<6>("h039"), T_452) + node T_454 = mux(T_282, UInt<6>("h03a"), T_453) + node T_455 = mux(T_280, UInt<6>("h03b"), T_454) + node T_456 = mux(T_278, UInt<6>("h03c"), T_455) + node T_457 = mux(T_276, UInt<6>("h03d"), T_456) + node T_458 = mux(T_274, UInt<6>("h03e"), T_457) + node T_459 = mux(T_272, UInt<6>("h03f"), T_458) + node T_460 = not(T_459) + node T_461 = dshl(T_265, T_460) + node T_462 = bits(T_461, 50, 0) + node T_464 = cat(T_462, UInt<1>("h00")) + node T_467 = sub(UInt<12>("h00"), UInt<1>("h01")) + node T_468 = tail(T_467, 1) + node T_469 = xor(T_460, T_468) + node T_470 = mux(T_267, T_469, T_264) + node T_474 = mux(T_267, UInt<2>("h02"), UInt<1>("h01")) + node T_475 = or(UInt<11>("h0400"), T_474) + node T_476 = add(T_470, T_475) + node T_477 = tail(T_476, 1) + node T_478 = bits(T_477, 11, 10) + node T_480 = eq(T_478, UInt<2>("h03")) + node T_482 = eq(T_269, UInt<1>("h00")) + node T_483 = and(T_480, T_482) + node T_485 = sub(UInt<3>("h00"), T_270) + node T_486 = tail(T_485, 1) + node T_487 = shl(T_486, 9) + node T_488 = not(T_487) + node T_489 = and(T_477, T_488) + node T_490 = shl(T_483, 9) + node T_491 = or(T_489, T_490) + node T_492 = mux(T_267, T_464, T_265) + node T_493 = cat(T_491, T_492) + node T_494 = cat(T_263, T_493) + mux.data <= T_494 when in.bits.single : - node T_518 = bit(in.bits.in1, 31) - node T_519 = bits(in.bits.in1, 30, 23) - node T_520 = bits(in.bits.in1, 22, 0) - node T_522 = eq(T_519, UInt<1>("h00")) - node T_524 = eq(T_520, UInt<1>("h00")) - node T_525 = and(T_522, T_524) - node T_526 = shl(T_520, 9) - node T_527 = bit(T_526, 31) - node T_529 = bit(T_526, 30) - node T_531 = bit(T_526, 29) - node T_533 = bit(T_526, 28) - node T_535 = bit(T_526, 27) - node T_537 = bit(T_526, 26) - node T_539 = bit(T_526, 25) - node T_541 = bit(T_526, 24) - node T_543 = bit(T_526, 23) - node T_545 = bit(T_526, 22) - node T_547 = bit(T_526, 21) - node T_549 = bit(T_526, 20) - node T_551 = bit(T_526, 19) - node T_553 = bit(T_526, 18) - node T_555 = bit(T_526, 17) - node T_557 = bit(T_526, 16) - node T_559 = bit(T_526, 15) - node T_561 = bit(T_526, 14) - node T_563 = bit(T_526, 13) - node T_565 = bit(T_526, 12) - node T_567 = bit(T_526, 11) - node T_569 = bit(T_526, 10) - node T_571 = bit(T_526, 9) - node T_573 = bit(T_526, 8) - node T_575 = bit(T_526, 7) - node T_577 = bit(T_526, 6) - node T_579 = bit(T_526, 5) - node T_581 = bit(T_526, 4) - node T_583 = bit(T_526, 3) - node T_585 = bit(T_526, 2) - node T_587 = bit(T_526, 1) - node T_588 = shl(T_587, 0) - node T_589 = mux(T_585, UInt<2>("h02"), T_588) - node T_590 = mux(T_583, UInt<2>("h03"), T_589) - node T_591 = mux(T_581, UInt<3>("h04"), T_590) - node T_592 = mux(T_579, UInt<3>("h05"), T_591) - node T_593 = mux(T_577, UInt<3>("h06"), T_592) - node T_594 = mux(T_575, UInt<3>("h07"), T_593) - node T_595 = mux(T_573, UInt<4>("h08"), T_594) - node T_596 = mux(T_571, UInt<4>("h09"), T_595) - node T_597 = mux(T_569, UInt<4>("h0a"), T_596) - node T_598 = mux(T_567, UInt<4>("h0b"), T_597) - node T_599 = mux(T_565, UInt<4>("h0c"), T_598) - node T_600 = mux(T_563, UInt<4>("h0d"), T_599) - node T_601 = mux(T_561, UInt<4>("h0e"), T_600) - node T_602 = mux(T_559, UInt<4>("h0f"), T_601) - node T_603 = mux(T_557, UInt<5>("h010"), T_602) - node T_604 = mux(T_555, UInt<5>("h011"), T_603) - node T_605 = mux(T_553, UInt<5>("h012"), T_604) - node T_606 = mux(T_551, UInt<5>("h013"), T_605) - node T_607 = mux(T_549, UInt<5>("h014"), T_606) - node T_608 = mux(T_547, UInt<5>("h015"), T_607) - node T_609 = mux(T_545, UInt<5>("h016"), T_608) - node T_610 = mux(T_543, UInt<5>("h017"), T_609) - node T_611 = mux(T_541, UInt<5>("h018"), T_610) - node T_612 = mux(T_539, UInt<5>("h019"), T_611) - node T_613 = mux(T_537, UInt<5>("h01a"), T_612) - node T_614 = mux(T_535, UInt<5>("h01b"), T_613) - node T_615 = mux(T_533, UInt<5>("h01c"), T_614) - node T_616 = mux(T_531, UInt<5>("h01d"), T_615) - node T_617 = mux(T_529, UInt<5>("h01e"), T_616) - node T_618 = mux(T_527, UInt<5>("h01f"), T_617) - node T_619 = not(T_618) - node T_620 = dshl(T_520, T_619) - node T_621 = bits(T_620, 21, 0) - node T_623 = cat(T_621, UInt<1>("h00")) - node T_626 = subw(UInt<9>("h00"), UInt<1>("h01")) - node T_627 = xor(T_619, T_626) - node T_628 = mux(T_522, T_627, T_519) - node T_632 = mux(T_522, UInt<2>("h02"), UInt<1>("h01")) - node T_633 = or(UInt<8>("h080"), T_632) - node T_634 = addw(T_628, T_633) - node T_635 = bits(T_634, 8, 7) - node T_637 = eq(T_635, UInt<2>("h03")) - node T_639 = eq(T_524, UInt<1>("h00")) - node T_640 = and(T_637, T_639) - node T_642 = subw(UInt<3>("h00"), T_525) - node T_643 = shl(T_642, 6) - node T_644 = not(T_643) - node T_645 = and(T_634, T_644) - node T_646 = shl(T_640, 6) - node T_647 = or(T_645, T_646) - node T_648 = mux(T_522, T_623, T_520) - node T_649 = cat(T_647, T_648) - node T_650 = cat(T_518, T_649) - node T_651 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_652 = cat(T_651, T_650) - mux.data <= T_652 - skip - node T_653 = bit(in.bits.typ, 1) - node T_654 = asSInt(in.bits.in1) - node T_655 = bit(in.bits.typ, 0) - node T_656 = bits(in.bits.in1, 31, 0) - node T_657 = cvt(T_656) - node T_658 = bits(in.bits.in1, 31, 0) - node T_659 = asSInt(T_658) - node T_660 = mux(T_655, T_657, T_659) - node longValue = mux(T_653, T_654, T_660) + node T_496 = bits(in.bits.in1, 31, 31) + node T_497 = bits(in.bits.in1, 30, 23) + node T_498 = bits(in.bits.in1, 22, 0) + node T_500 = eq(T_497, UInt<1>("h00")) + node T_502 = eq(T_498, UInt<1>("h00")) + node T_503 = and(T_500, T_502) + node T_504 = shl(T_498, 9) + node T_505 = bits(T_504, 31, 31) + node T_507 = bits(T_504, 30, 30) + node T_509 = bits(T_504, 29, 29) + node T_511 = bits(T_504, 28, 28) + node T_513 = bits(T_504, 27, 27) + node T_515 = bits(T_504, 26, 26) + node T_517 = bits(T_504, 25, 25) + node T_519 = bits(T_504, 24, 24) + node T_521 = bits(T_504, 23, 23) + node T_523 = bits(T_504, 22, 22) + node T_525 = bits(T_504, 21, 21) + node T_527 = bits(T_504, 20, 20) + node T_529 = bits(T_504, 19, 19) + node T_531 = bits(T_504, 18, 18) + node T_533 = bits(T_504, 17, 17) + node T_535 = bits(T_504, 16, 16) + node T_537 = bits(T_504, 15, 15) + node T_539 = bits(T_504, 14, 14) + node T_541 = bits(T_504, 13, 13) + node T_543 = bits(T_504, 12, 12) + node T_545 = bits(T_504, 11, 11) + node T_547 = bits(T_504, 10, 10) + node T_549 = bits(T_504, 9, 9) + node T_551 = bits(T_504, 8, 8) + node T_553 = bits(T_504, 7, 7) + node T_555 = bits(T_504, 6, 6) + node T_557 = bits(T_504, 5, 5) + node T_559 = bits(T_504, 4, 4) + node T_561 = bits(T_504, 3, 3) + node T_563 = bits(T_504, 2, 2) + node T_565 = bits(T_504, 1, 1) + node T_566 = shl(T_565, 0) + node T_567 = mux(T_563, UInt<2>("h02"), T_566) + node T_568 = mux(T_561, UInt<2>("h03"), T_567) + node T_569 = mux(T_559, UInt<3>("h04"), T_568) + node T_570 = mux(T_557, UInt<3>("h05"), T_569) + node T_571 = mux(T_555, UInt<3>("h06"), T_570) + node T_572 = mux(T_553, UInt<3>("h07"), T_571) + node T_573 = mux(T_551, UInt<4>("h08"), T_572) + node T_574 = mux(T_549, UInt<4>("h09"), T_573) + node T_575 = mux(T_547, UInt<4>("h0a"), T_574) + node T_576 = mux(T_545, UInt<4>("h0b"), T_575) + node T_577 = mux(T_543, UInt<4>("h0c"), T_576) + node T_578 = mux(T_541, UInt<4>("h0d"), T_577) + node T_579 = mux(T_539, UInt<4>("h0e"), T_578) + node T_580 = mux(T_537, UInt<4>("h0f"), T_579) + node T_581 = mux(T_535, UInt<5>("h010"), T_580) + node T_582 = mux(T_533, UInt<5>("h011"), T_581) + node T_583 = mux(T_531, UInt<5>("h012"), T_582) + node T_584 = mux(T_529, UInt<5>("h013"), T_583) + node T_585 = mux(T_527, UInt<5>("h014"), T_584) + node T_586 = mux(T_525, UInt<5>("h015"), T_585) + node T_587 = mux(T_523, UInt<5>("h016"), T_586) + node T_588 = mux(T_521, UInt<5>("h017"), T_587) + node T_589 = mux(T_519, UInt<5>("h018"), T_588) + node T_590 = mux(T_517, UInt<5>("h019"), T_589) + node T_591 = mux(T_515, UInt<5>("h01a"), T_590) + node T_592 = mux(T_513, UInt<5>("h01b"), T_591) + node T_593 = mux(T_511, UInt<5>("h01c"), T_592) + node T_594 = mux(T_509, UInt<5>("h01d"), T_593) + node T_595 = mux(T_507, UInt<5>("h01e"), T_594) + node T_596 = mux(T_505, UInt<5>("h01f"), T_595) + node T_597 = not(T_596) + node T_598 = dshl(T_498, T_597) + node T_599 = bits(T_598, 21, 0) + node T_601 = cat(T_599, UInt<1>("h00")) + node T_604 = sub(UInt<9>("h00"), UInt<1>("h01")) + node T_605 = tail(T_604, 1) + node T_606 = xor(T_597, T_605) + node T_607 = mux(T_500, T_606, T_497) + node T_611 = mux(T_500, UInt<2>("h02"), UInt<1>("h01")) + node T_612 = or(UInt<8>("h080"), T_611) + node T_613 = add(T_607, T_612) + node T_614 = tail(T_613, 1) + node T_615 = bits(T_614, 8, 7) + node T_617 = eq(T_615, UInt<2>("h03")) + node T_619 = eq(T_502, UInt<1>("h00")) + node T_620 = and(T_617, T_619) + node T_622 = sub(UInt<3>("h00"), T_503) + node T_623 = tail(T_622, 1) + node T_624 = shl(T_623, 6) + node T_625 = not(T_624) + node T_626 = and(T_614, T_625) + node T_627 = shl(T_620, 6) + node T_628 = or(T_626, T_627) + node T_629 = mux(T_500, T_601, T_498) + node T_630 = cat(T_628, T_629) + node T_631 = cat(T_496, T_630) + node T_632 = asUInt(asSInt(UInt<32>("h0ffffffff"))) + node T_633 = cat(T_632, T_631) + mux.data <= T_633 + skip + node T_634 = bits(in.bits.typ, 1, 1) + node T_635 = asSInt(in.bits.in1) + node T_636 = bits(in.bits.typ, 0, 0) + node T_637 = bits(in.bits.in1, 31, 0) + node T_638 = cvt(T_637) + node T_639 = bits(in.bits.in1, 31, 0) + node T_640 = asSInt(T_639) + node T_641 = mux(T_636, T_638, T_640) + node longValue = mux(T_634, T_635, T_641) inst l2s of INToRecFN - l2s.io.roundingMode <= UInt<1>("h00") - l2s.io.in <= UInt<1>("h00") - l2s.io.signedIn <= UInt<1>("h00") + l2s.io is invalid l2s.clk <= clk l2s.reset <= reset - node T_666 = bit(in.bits.typ, 0) - node T_667 = not(T_666) - l2s.io.signedIn <= T_667 - node T_668 = asUInt(longValue) - l2s.io.in <= T_668 + node T_644 = bits(in.bits.typ, 0, 0) + node T_645 = not(T_644) + l2s.io.signedIn <= T_645 + node T_646 = asUInt(longValue) + l2s.io.in <= T_646 l2s.io.roundingMode <= in.bits.rm inst l2d of INToRecFN_119 - l2d.io.roundingMode <= UInt<1>("h00") - l2d.io.in <= UInt<1>("h00") - l2d.io.signedIn <= UInt<1>("h00") + l2d.io is invalid l2d.clk <= clk l2d.reset <= reset - node T_673 = bit(in.bits.typ, 0) - node T_674 = not(T_673) - l2d.io.signedIn <= T_674 - node T_675 = asUInt(longValue) - l2d.io.in <= T_675 + node T_648 = bits(in.bits.typ, 0, 0) + node T_649 = not(T_648) + l2d.io.signedIn <= T_649 + node T_650 = asUInt(longValue) + l2d.io.in <= T_650 l2d.io.roundingMode <= in.bits.rm - node T_678 = and(in.bits.cmd, UInt<3>("h04")) - node T_679 = eq(UInt<1>("h00"), T_678) - when T_679 : + node T_653 = and(in.bits.cmd, UInt<3>("h04")) + node T_654 = eq(UInt<1>("h00"), T_653) + when T_654 : when in.bits.single : - node T_681 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_682 = cat(T_681, l2s.io.out) - mux.data <= T_682 + node T_656 = asUInt(asSInt(UInt<32>("h0ffffffff"))) + node T_657 = cat(T_656, l2s.io.out) + mux.data <= T_657 mux.exc <= l2s.io.exceptionFlags skip - node T_684 = eq(in.bits.single, UInt<1>("h00")) - when T_684 : + node T_659 = eq(in.bits.single, UInt<1>("h00")) + when T_659 : mux.data <= l2d.io.out mux.exc <= l2d.io.exceptionFlags skip skip - reg T_687 : UInt<1>, clk, reset, UInt<1>("h00") - T_687 <= in.valid - reg T_688 : {data : UInt<65>, exc : UInt<5>}, clk, UInt<1>("h00"), T_688 + reg T_662 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + T_662 <= in.valid + reg T_663 : {data : UInt<65>, exc : UInt<5>}, clk when in.valid : - T_688 <- mux - skip - reg T_693 : UInt<1>, clk, reset, UInt<1>("h00") - T_693 <= T_687 - reg T_694 : {data : UInt<65>, exc : UInt<5>}, clk, UInt<1>("h00"), T_694 - when T_687 : - T_694 <- T_688 - skip - wire T_705 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} - T_705.bits.exc <= UInt<1>("h00") - T_705.bits.data <= UInt<1>("h00") - T_705.valid <= UInt<1>("h00") - T_705.valid <= T_693 - T_705.bits <- T_694 - io.out <- T_705 + T_663 <- mux + skip + reg T_668 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + T_668 <= T_662 + reg T_669 : {data : UInt<65>, exc : UInt<5>}, clk + when T_662 : + T_669 <- T_663 + skip + wire T_680 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} + T_680 is invalid + T_680.valid <= T_668 + T_680.bits <- T_669 + io.out <- T_680 module RoundRawFNToRecFN : input clk : Clock input reset : UInt<1> output io : {flip invalidExc : UInt<1>, flip infiniteExc : UInt<1>, flip in : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>}, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} - io.exceptionFlags <= UInt<1>("h00") - io.out <= UInt<1>("h00") + io is invalid node roundingMode_nearest_even = eq(io.roundingMode, UInt<2>("h00")) node roundingMode_minMag = eq(io.roundingMode, UInt<2>("h01")) node roundingMode_min = eq(io.roundingMode, UInt<2>("h02")) @@ -37538,813 +29614,763 @@ circuit Top : node T_28 = not(io.in.sign) node T_29 = and(roundingMode_max, T_28) node roundMagUp = or(T_27, T_29) - node doShiftSigDown1 = bit(io.in.sig, 26) + node doShiftSigDown1 = bits(io.in.sig, 26, 26) node T_33 = lt(io.in.sExp, asSInt(UInt<1>("h00"))) - node T_35 = subw(UInt<25>("h00"), T_33) - node T_36 = bits(io.in.sExp, 8, 0) - node T_37 = not(T_36) - node T_39 = dshr(asSInt(UInt<513>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_37) - node T_40 = bits(T_39, 130, 106) - node T_41 = bits(T_40, 15, 0) - node T_44 = shl(UInt<8>("h0ff"), 8) - node T_45 = xor(UInt<16>("h0ffff"), T_44) - node T_46 = shr(T_41, 8) - node T_47 = and(T_46, T_45) - node T_48 = bits(T_41, 7, 0) - node T_49 = shl(T_48, 8) - node T_50 = not(T_45) - node T_51 = and(T_49, T_50) - node T_52 = or(T_47, T_51) - node T_53 = bits(T_45, 11, 0) - node T_54 = shl(T_53, 4) - node T_55 = xor(T_45, T_54) - node T_56 = shr(T_52, 4) - node T_57 = and(T_56, T_55) - node T_58 = bits(T_52, 11, 0) - node T_59 = shl(T_58, 4) - node T_60 = not(T_55) - node T_61 = and(T_59, T_60) - node T_62 = or(T_57, T_61) - node T_63 = bits(T_55, 13, 0) - node T_64 = shl(T_63, 2) - node T_65 = xor(T_55, T_64) - node T_66 = shr(T_62, 2) - node T_67 = and(T_66, T_65) - node T_68 = bits(T_62, 13, 0) - node T_69 = shl(T_68, 2) - node T_70 = not(T_65) - node T_71 = and(T_69, T_70) - node T_72 = or(T_67, T_71) - node T_73 = bits(T_65, 14, 0) - node T_74 = shl(T_73, 1) - node T_75 = xor(T_65, T_74) - node T_76 = shr(T_72, 1) - node T_77 = and(T_76, T_75) - node T_78 = bits(T_72, 14, 0) - node T_79 = shl(T_78, 1) - node T_80 = not(T_75) - node T_81 = and(T_79, T_80) - node T_82 = or(T_77, T_81) - node T_83 = bits(T_40, 24, 16) - node T_84 = bits(T_83, 7, 0) - node T_87 = shl(UInt<4>("h0f"), 4) - node T_88 = xor(UInt<8>("h0ff"), T_87) - node T_89 = shr(T_84, 4) - node T_90 = and(T_89, T_88) - node T_91 = bits(T_84, 3, 0) - node T_92 = shl(T_91, 4) - node T_93 = not(T_88) - node T_94 = and(T_92, T_93) - node T_95 = or(T_90, T_94) - node T_96 = bits(T_88, 5, 0) - node T_97 = shl(T_96, 2) - node T_98 = xor(T_88, T_97) - node T_99 = shr(T_95, 2) - node T_100 = and(T_99, T_98) - node T_101 = bits(T_95, 5, 0) - node T_102 = shl(T_101, 2) - node T_103 = not(T_98) - node T_104 = and(T_102, T_103) - node T_105 = or(T_100, T_104) - node T_106 = bits(T_98, 6, 0) - node T_107 = shl(T_106, 1) - node T_108 = xor(T_98, T_107) - node T_109 = shr(T_105, 1) - node T_110 = and(T_109, T_108) - node T_111 = bits(T_105, 6, 0) - node T_112 = shl(T_111, 1) - node T_113 = not(T_108) - node T_114 = and(T_112, T_113) - node T_115 = or(T_110, T_114) - node T_116 = bits(T_83, 8, 8) - node T_117 = cat(T_115, T_116) - node T_118 = cat(T_82, T_117) - node T_119 = or(T_35, T_118) - node T_120 = or(T_119, doShiftSigDown1) - node roundMask = cat(T_120, UInt<2>("h03")) - node T_123 = shr(roundMask, 1) - node T_124 = not(T_123) - node roundPosMask = and(T_124, roundMask) - node T_126 = and(io.in.sig, roundPosMask) - node roundPosBit = neq(T_126, UInt<1>("h00")) - node T_129 = shr(roundMask, 1) - node T_130 = and(io.in.sig, T_129) - node anyRoundExtra = neq(T_130, UInt<1>("h00")) + node T_35 = sub(UInt<25>("h00"), T_33) + node T_36 = tail(T_35, 1) + node T_37 = bits(io.in.sExp, 8, 0) + node T_38 = not(T_37) + node T_40 = dshr(asSInt(UInt<513>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_38) + node T_41 = bits(T_40, 130, 106) + node T_42 = bits(T_41, 15, 0) + node T_45 = shl(UInt<8>("h0ff"), 8) + node T_46 = xor(UInt<16>("h0ffff"), T_45) + node T_47 = shr(T_42, 8) + node T_48 = and(T_47, T_46) + node T_49 = bits(T_42, 7, 0) + node T_50 = shl(T_49, 8) + node T_51 = not(T_46) + node T_52 = and(T_50, T_51) + node T_53 = or(T_48, T_52) + node T_54 = bits(T_46, 11, 0) + node T_55 = shl(T_54, 4) + node T_56 = xor(T_46, T_55) + node T_57 = shr(T_53, 4) + node T_58 = and(T_57, T_56) + node T_59 = bits(T_53, 11, 0) + node T_60 = shl(T_59, 4) + node T_61 = not(T_56) + node T_62 = and(T_60, T_61) + node T_63 = or(T_58, T_62) + node T_64 = bits(T_56, 13, 0) + node T_65 = shl(T_64, 2) + node T_66 = xor(T_56, T_65) + node T_67 = shr(T_63, 2) + node T_68 = and(T_67, T_66) + node T_69 = bits(T_63, 13, 0) + node T_70 = shl(T_69, 2) + node T_71 = not(T_66) + node T_72 = and(T_70, T_71) + node T_73 = or(T_68, T_72) + node T_74 = bits(T_66, 14, 0) + node T_75 = shl(T_74, 1) + node T_76 = xor(T_66, T_75) + node T_77 = shr(T_73, 1) + node T_78 = and(T_77, T_76) + node T_79 = bits(T_73, 14, 0) + node T_80 = shl(T_79, 1) + node T_81 = not(T_76) + node T_82 = and(T_80, T_81) + node T_83 = or(T_78, T_82) + node T_84 = bits(T_41, 24, 16) + node T_85 = bits(T_84, 7, 0) + node T_88 = shl(UInt<4>("h0f"), 4) + node T_89 = xor(UInt<8>("h0ff"), T_88) + node T_90 = shr(T_85, 4) + node T_91 = and(T_90, T_89) + node T_92 = bits(T_85, 3, 0) + node T_93 = shl(T_92, 4) + node T_94 = not(T_89) + node T_95 = and(T_93, T_94) + node T_96 = or(T_91, T_95) + node T_97 = bits(T_89, 5, 0) + node T_98 = shl(T_97, 2) + node T_99 = xor(T_89, T_98) + node T_100 = shr(T_96, 2) + node T_101 = and(T_100, T_99) + node T_102 = bits(T_96, 5, 0) + node T_103 = shl(T_102, 2) + node T_104 = not(T_99) + node T_105 = and(T_103, T_104) + node T_106 = or(T_101, T_105) + node T_107 = bits(T_99, 6, 0) + node T_108 = shl(T_107, 1) + node T_109 = xor(T_99, T_108) + node T_110 = shr(T_106, 1) + node T_111 = and(T_110, T_109) + node T_112 = bits(T_106, 6, 0) + node T_113 = shl(T_112, 1) + node T_114 = not(T_109) + node T_115 = and(T_113, T_114) + node T_116 = or(T_111, T_115) + node T_117 = bits(T_84, 8, 8) + node T_118 = cat(T_116, T_117) + node T_119 = cat(T_83, T_118) + node T_120 = or(T_36, T_119) + node T_121 = or(T_120, doShiftSigDown1) + node roundMask = cat(T_121, UInt<2>("h03")) + node T_124 = shr(roundMask, 1) + node T_125 = not(T_124) + node roundPosMask = and(T_125, roundMask) + node T_127 = and(io.in.sig, roundPosMask) + node roundPosBit = neq(T_127, UInt<1>("h00")) + node T_130 = shr(roundMask, 1) + node T_131 = and(io.in.sig, T_130) + node anyRoundExtra = neq(T_131, UInt<1>("h00")) node common_inexact = or(roundPosBit, anyRoundExtra) - node T_134 = and(roundingMode_nearest_even, roundPosBit) - node T_135 = and(roundMagUp, common_inexact) - node T_136 = or(T_134, T_135) - node T_137 = or(io.in.sig, roundMask) - node T_138 = shr(T_137, 2) - node T_140 = addw(T_138, UInt<1>("h01")) - node T_141 = and(roundingMode_nearest_even, roundPosBit) - node T_142 = not(anyRoundExtra) - node T_143 = and(T_141, T_142) - node T_144 = shr(roundMask, 1) - node T_146 = mux(T_143, T_144, UInt<26>("h00")) - node T_147 = not(T_146) - node T_148 = and(T_140, T_147) - node T_149 = not(roundMask) - node T_150 = and(io.in.sig, T_149) - node T_151 = shr(T_150, 2) - node roundedSig = mux(T_136, T_148, T_151) - node T_153 = shr(roundedSig, 24) - node T_154 = cvt(T_153) - node sRoundedExp = addw(io.in.sExp, T_154) + node T_135 = and(roundingMode_nearest_even, roundPosBit) + node T_136 = and(roundMagUp, common_inexact) + node T_137 = or(T_135, T_136) + node T_138 = or(io.in.sig, roundMask) + node T_139 = shr(T_138, 2) + node T_141 = add(T_139, UInt<1>("h01")) + node T_142 = tail(T_141, 1) + node T_143 = and(roundingMode_nearest_even, roundPosBit) + node T_144 = not(anyRoundExtra) + node T_145 = and(T_143, T_144) + node T_146 = shr(roundMask, 1) + node T_148 = mux(T_145, T_146, UInt<26>("h00")) + node T_149 = not(T_148) + node T_150 = and(T_142, T_149) + node T_151 = not(roundMask) + node T_152 = and(io.in.sig, T_151) + node T_153 = shr(T_152, 2) + node roundedSig = mux(T_137, T_150, T_153) + node T_155 = shr(roundedSig, 24) + node T_156 = cvt(T_155) + node T_157 = add(io.in.sExp, T_156) + node T_158 = tail(T_157, 1) + node sRoundedExp = asSInt(T_158) node common_expOut = bits(sRoundedExp, 8, 0) - node T_157 = bits(roundedSig, 23, 1) - node T_158 = bits(roundedSig, 22, 0) - node common_fractOut = mux(doShiftSigDown1, T_157, T_158) - node T_160 = shr(sRoundedExp, 7) - node common_overflow = geq(T_160, asSInt(UInt<3>("h03"))) + node T_161 = bits(roundedSig, 23, 1) + node T_162 = bits(roundedSig, 22, 0) + node common_fractOut = mux(doShiftSigDown1, T_161, T_162) + node T_164 = shr(sRoundedExp, 7) + node common_overflow = geq(T_164, asSInt(UInt<3>("h03"))) node common_totalUnderflow = lt(sRoundedExp, asSInt(UInt<8>("h06b"))) - node T_167 = mux(doShiftSigDown1, asSInt(UInt<9>("h081")), asSInt(UInt<9>("h082"))) - node T_168 = lt(io.in.sExp, T_167) - node common_underflow = and(common_inexact, T_168) + node T_171 = mux(doShiftSigDown1, asSInt(UInt<9>("h081")), asSInt(UInt<9>("h082"))) + node T_172 = lt(io.in.sExp, T_171) + node common_underflow = and(common_inexact, T_172) node isNaNOut = or(io.invalidExc, io.in.isNaN) node notNaN_isSpecialInfOut = or(io.infiniteExc, io.in.isInf) - node T_172 = not(isNaNOut) - node T_173 = not(notNaN_isSpecialInfOut) - node T_174 = and(T_172, T_173) - node T_175 = not(io.in.isZero) - node commonCase = and(T_174, T_175) + node T_176 = not(isNaNOut) + node T_177 = not(notNaN_isSpecialInfOut) + node T_178 = and(T_176, T_177) + node T_179 = not(io.in.isZero) + node commonCase = and(T_178, T_179) node overflow = and(commonCase, common_overflow) node underflow = and(commonCase, common_underflow) - node T_179 = and(commonCase, common_inexact) - node inexact = or(overflow, T_179) + node T_183 = and(commonCase, common_inexact) + node inexact = or(overflow, T_183) node overflow_roundMagUp = or(roundingMode_nearest_even, roundMagUp) - node T_182 = and(commonCase, common_totalUnderflow) - node pegMinNonzeroMagOut = and(T_182, roundMagUp) - node T_184 = and(commonCase, overflow) - node T_185 = not(overflow_roundMagUp) - node pegMaxFiniteMagOut = and(T_184, T_185) - node T_187 = and(overflow, overflow_roundMagUp) - node notNaN_isInfOut = or(notNaN_isSpecialInfOut, T_187) + node T_186 = and(commonCase, common_totalUnderflow) + node pegMinNonzeroMagOut = and(T_186, roundMagUp) + node T_188 = and(commonCase, overflow) + node T_189 = not(overflow_roundMagUp) + node pegMaxFiniteMagOut = and(T_188, T_189) + node T_191 = and(overflow, overflow_roundMagUp) + node notNaN_isInfOut = or(notNaN_isSpecialInfOut, T_191) node signOut = mux(isNaNOut, UInt<1>("h00"), io.in.sign) - node T_191 = or(io.in.isZero, common_totalUnderflow) - node T_194 = mux(T_191, UInt<9>("h01c0"), UInt<1>("h00")) - node T_195 = not(T_194) - node T_196 = and(common_expOut, T_195) - node T_198 = not(UInt<9>("h06b")) - node T_200 = mux(pegMinNonzeroMagOut, T_198, UInt<1>("h00")) - node T_201 = not(T_200) - node T_202 = and(T_196, T_201) - node T_205 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<1>("h00")) - node T_206 = not(T_205) - node T_207 = and(T_202, T_206) - node T_210 = mux(notNaN_isInfOut, UInt<9>("h040"), UInt<1>("h00")) - node T_211 = not(T_210) - node T_212 = and(T_207, T_211) - node T_215 = mux(pegMinNonzeroMagOut, UInt<9>("h06b"), UInt<1>("h00")) - node T_216 = or(T_212, T_215) - node T_219 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<1>("h00")) + node T_195 = or(io.in.isZero, common_totalUnderflow) + node T_198 = mux(T_195, UInt<9>("h01c0"), UInt<1>("h00")) + node T_199 = not(T_198) + node T_200 = and(common_expOut, T_199) + node T_202 = not(UInt<9>("h06b")) + node T_204 = mux(pegMinNonzeroMagOut, T_202, UInt<1>("h00")) + node T_205 = not(T_204) + node T_206 = and(T_200, T_205) + node T_209 = mux(pegMaxFiniteMagOut, UInt<9>("h080"), UInt<1>("h00")) + node T_210 = not(T_209) + node T_211 = and(T_206, T_210) + node T_214 = mux(notNaN_isInfOut, UInt<9>("h040"), UInt<1>("h00")) + node T_215 = not(T_214) + node T_216 = and(T_211, T_215) + node T_219 = mux(pegMinNonzeroMagOut, UInt<9>("h06b"), UInt<1>("h00")) node T_220 = or(T_216, T_219) - node T_223 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<1>("h00")) + node T_223 = mux(pegMaxFiniteMagOut, UInt<9>("h017f"), UInt<1>("h00")) node T_224 = or(T_220, T_223) - node T_227 = mux(isNaNOut, UInt<9>("h01c0"), UInt<1>("h00")) - node expOut = or(T_224, T_227) - node T_229 = and(common_totalUnderflow, roundMagUp) - node T_230 = or(T_229, isNaNOut) - node T_232 = mux(T_230, UInt<1>("h00"), common_fractOut) - node T_234 = subw(UInt<23>("h00"), pegMaxFiniteMagOut) - node T_235 = or(T_232, T_234) - node T_236 = shl(isNaNOut, 22) - node fractOut = or(T_235, T_236) - node T_238 = cat(expOut, fractOut) - node T_239 = cat(signOut, T_238) - io.out <= T_239 - node T_240 = cat(io.invalidExc, io.infiniteExc) - node T_241 = cat(underflow, inexact) - node T_242 = cat(overflow, T_241) - node T_243 = cat(T_240, T_242) - io.exceptionFlags <= T_243 + node T_227 = mux(notNaN_isInfOut, UInt<9>("h0180"), UInt<1>("h00")) + node T_228 = or(T_224, T_227) + node T_231 = mux(isNaNOut, UInt<9>("h01c0"), UInt<1>("h00")) + node expOut = or(T_228, T_231) + node T_233 = and(common_totalUnderflow, roundMagUp) + node T_234 = or(T_233, isNaNOut) + node T_236 = mux(T_234, UInt<1>("h00"), common_fractOut) + node T_238 = sub(UInt<23>("h00"), pegMaxFiniteMagOut) + node T_239 = tail(T_238, 1) + node T_240 = or(T_236, T_239) + node T_241 = shl(isNaNOut, 22) + node fractOut = or(T_240, T_241) + node T_243 = cat(expOut, fractOut) + node T_244 = cat(signOut, T_243) + io.out <= T_244 + node T_245 = cat(io.invalidExc, io.infiniteExc) + node T_246 = cat(underflow, inexact) + node T_247 = cat(overflow, T_246) + node T_248 = cat(T_245, T_247) + io.exceptionFlags <= T_248 module RecFNToRecFN_121 : input clk : Clock input reset : UInt<1> output io : {flip in : UInt<65>, flip roundingMode : UInt<2>, out : UInt<33>, exceptionFlags : UInt<5>} - io.exceptionFlags <= UInt<1>("h00") - io.out <= UInt<1>("h00") + io is invalid node T_8 = bits(io.in, 63, 52) node T_9 = bits(T_8, 11, 10) node T_11 = eq(T_9, UInt<2>("h03")) wire T_19 : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<13>, sig : UInt<56>} - T_19.sig <= UInt<1>("h00") - T_19.sExp <= asSInt(UInt<1>("h00")) - T_19.isZero <= UInt<1>("h00") - T_19.isInf <= UInt<1>("h00") - T_19.isNaN <= UInt<1>("h00") - T_19.sign <= UInt<1>("h00") - node T_32 = bit(io.in, 64) - T_19.sign <= T_32 - node T_33 = bit(T_8, 9) - node T_34 = and(T_11, T_33) - T_19.isNaN <= T_34 - node T_35 = bit(T_8, 9) - node T_37 = eq(T_35, UInt<1>("h00")) - node T_38 = and(T_11, T_37) - T_19.isInf <= T_38 - node T_39 = bits(T_8, 11, 9) - node T_41 = eq(T_39, UInt<1>("h00")) - T_19.isZero <= T_41 - node T_42 = cvt(T_8) - T_19.sExp <= T_42 - node T_44 = bits(io.in, 51, 0) - node T_46 = cat(T_44, UInt<2>("h00")) - node T_47 = cat(UInt<2>("h01"), T_46) - T_19.sig <= T_47 - node T_49 = addw(T_19.sExp, asSInt(UInt<12>("h0900"))) + T_19 is invalid + node T_26 = bits(io.in, 64, 64) + T_19.sign <= T_26 + node T_27 = bits(T_8, 9, 9) + node T_28 = and(T_11, T_27) + T_19.isNaN <= T_28 + node T_29 = bits(T_8, 9, 9) + node T_31 = eq(T_29, UInt<1>("h00")) + node T_32 = and(T_11, T_31) + T_19.isInf <= T_32 + node T_33 = bits(T_8, 11, 9) + node T_35 = eq(T_33, UInt<1>("h00")) + T_19.isZero <= T_35 + node T_36 = cvt(T_8) + T_19.sExp <= T_36 + node T_38 = bits(io.in, 51, 0) + node T_40 = cat(T_38, UInt<2>("h00")) + node T_41 = cat(UInt<2>("h01"), T_40) + T_19.sig <= T_41 + node T_43 = add(T_19.sExp, asSInt(UInt<12>("h0900"))) + node T_44 = tail(T_43, 1) + node T_45 = asSInt(T_44) wire outRawFloat : {sign : UInt<1>, isNaN : UInt<1>, isInf : UInt<1>, isZero : UInt<1>, sExp : SInt<10>, sig : UInt<27>} - outRawFloat.sig <= UInt<1>("h00") - outRawFloat.sExp <= asSInt(UInt<1>("h00")) - outRawFloat.isZero <= UInt<1>("h00") - outRawFloat.isInf <= UInt<1>("h00") - outRawFloat.isNaN <= UInt<1>("h00") - outRawFloat.sign <= UInt<1>("h00") + outRawFloat is invalid outRawFloat.sign <= T_19.sign outRawFloat.isNaN <= T_19.isNaN outRawFloat.isInf <= T_19.isInf outRawFloat.isZero <= T_19.isZero - node T_71 = lt(T_49, asSInt(UInt<1>("h00"))) - node T_72 = bits(T_49, 11, 9) - node T_74 = neq(T_72, UInt<1>("h00")) - node T_76 = cat(UInt<1>("h01"), UInt<1>("h01")) - node T_77 = cat(T_76, T_76) - node T_78 = cat(T_76, T_77) - node T_79 = cat(UInt<1>("h01"), T_78) - node T_81 = cat(T_79, UInt<2>("h00")) - node T_82 = bits(T_49, 8, 0) - node T_83 = mux(T_74, T_81, T_82) - node T_84 = cat(T_71, T_83) - node T_85 = asSInt(T_84) - outRawFloat.sExp <= T_85 - node T_86 = bits(T_19.sig, 55, 30) - node T_87 = bits(T_19.sig, 29, 0) - node T_89 = neq(T_87, UInt<1>("h00")) - node T_90 = cat(T_86, T_89) - outRawFloat.sig <= T_90 - node T_91 = bit(outRawFloat.sig, 24) - node T_93 = eq(T_91, UInt<1>("h00")) - node invalidExc = and(outRawFloat.isNaN, T_93) - inst T_95 of RoundRawFNToRecFN - T_95.io.roundingMode <= UInt<1>("h00") - T_95.io.in.sig <= UInt<1>("h00") - T_95.io.in.sExp <= asSInt(UInt<1>("h00")) - T_95.io.in.isZero <= UInt<1>("h00") - T_95.io.in.isInf <= UInt<1>("h00") - T_95.io.in.isNaN <= UInt<1>("h00") - T_95.io.in.sign <= UInt<1>("h00") - T_95.io.infiniteExc <= UInt<1>("h00") - T_95.io.invalidExc <= UInt<1>("h00") - T_95.clk <= clk - T_95.reset <= reset - T_95.io.invalidExc <= invalidExc - T_95.io.infiniteExc <= UInt<1>("h00") - T_95.io.in <- outRawFloat - T_95.io.roundingMode <= io.roundingMode - io.out <= T_95.io.out - io.exceptionFlags <= T_95.io.exceptionFlags + node T_61 = lt(T_45, asSInt(UInt<1>("h00"))) + node T_62 = bits(T_45, 11, 9) + node T_64 = neq(T_62, UInt<1>("h00")) + node T_66 = cat(UInt<1>("h01"), UInt<1>("h01")) + node T_67 = cat(T_66, T_66) + node T_68 = cat(T_66, T_67) + node T_69 = cat(UInt<1>("h01"), T_68) + node T_71 = cat(T_69, UInt<2>("h00")) + node T_72 = bits(T_45, 8, 0) + node T_73 = mux(T_64, T_71, T_72) + node T_74 = cat(T_61, T_73) + node T_75 = asSInt(T_74) + outRawFloat.sExp <= T_75 + node T_76 = bits(T_19.sig, 55, 30) + node T_77 = bits(T_19.sig, 29, 0) + node T_79 = neq(T_77, UInt<1>("h00")) + node T_80 = cat(T_76, T_79) + outRawFloat.sig <= T_80 + node T_81 = bits(outRawFloat.sig, 24, 24) + node T_83 = eq(T_81, UInt<1>("h00")) + node invalidExc = and(outRawFloat.isNaN, T_83) + inst T_85 of RoundRawFNToRecFN + T_85.io is invalid + T_85.clk <= clk + T_85.reset <= reset + T_85.io.invalidExc <= invalidExc + T_85.io.infiniteExc <= UInt<1>("h00") + T_85.io.in <- outRawFloat + T_85.io.roundingMode <= io.roundingMode + io.out <= T_85.io.out + io.exceptionFlags <= T_85.io.exceptionFlags module FPToFP : input clk : Clock input reset : UInt<1> output io : {flip in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, out : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}, flip lt : UInt<1>} - io.out.bits.exc <= UInt<1>("h00") - io.out.bits.data <= UInt<1>("h00") - io.out.valid <= UInt<1>("h00") - reg T_137 : UInt<1>, clk, reset, UInt<1>("h00") + io is invalid + reg T_137 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) T_137 <= io.in.valid - reg T_138 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk, UInt<1>("h00"), T_138 + reg T_138 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}, clk when io.in.valid : T_138 <- io.in.bits skip wire in : {valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}} - in.bits.in3 <= UInt<1>("h00") - in.bits.in2 <= UInt<1>("h00") - in.bits.in1 <= UInt<1>("h00") - in.bits.typ <= UInt<1>("h00") - in.bits.rm <= UInt<1>("h00") - in.bits.wflags <= UInt<1>("h00") - in.bits.round <= UInt<1>("h00") - in.bits.sqrt <= UInt<1>("h00") - in.bits.div <= UInt<1>("h00") - in.bits.fma <= UInt<1>("h00") - in.bits.fastpipe <= UInt<1>("h00") - in.bits.toint <= UInt<1>("h00") - in.bits.fromint <= UInt<1>("h00") - in.bits.single <= UInt<1>("h00") - in.bits.swap23 <= UInt<1>("h00") - in.bits.swap12 <= UInt<1>("h00") - in.bits.ren3 <= UInt<1>("h00") - in.bits.ren2 <= UInt<1>("h00") - in.bits.ren1 <= UInt<1>("h00") - in.bits.wen <= UInt<1>("h00") - in.bits.ldst <= UInt<1>("h00") - in.bits.cmd <= UInt<1>("h00") - in.valid <= UInt<1>("h00") + in is invalid in.valid <= T_137 in.bits <- T_138 - node T_282 = and(in.bits.cmd, UInt<3>("h05")) - node isSgnj = eq(UInt<3>("h04"), T_282) - node T_284 = and(in.bits.single, isSgnj) - node T_285 = bit(in.bits.rm, 1) - node T_287 = eq(T_284, UInt<1>("h00")) - node T_288 = or(T_285, T_287) - node T_289 = bit(in.bits.in1, 32) - node T_290 = bit(in.bits.rm, 0) - node T_291 = mux(T_288, T_289, T_290) - node T_292 = bit(in.bits.in2, 32) - node T_293 = and(T_284, T_292) - node sign_s = xor(T_291, T_293) - node T_296 = eq(in.bits.single, UInt<1>("h00")) - node T_297 = and(T_296, isSgnj) - node T_298 = bit(in.bits.rm, 1) - node T_300 = eq(T_297, UInt<1>("h00")) - node T_301 = or(T_298, T_300) - node T_302 = bit(in.bits.in1, 64) - node T_303 = bit(in.bits.rm, 0) - node T_304 = mux(T_301, T_302, T_303) - node T_305 = bit(in.bits.in2, 64) - node T_306 = and(T_297, T_305) - node sign_d = xor(T_304, T_306) - node T_308 = bits(in.bits.in1, 63, 33) - node T_309 = bits(in.bits.in1, 31, 0) - node T_310 = cat(sign_d, T_308) - node T_311 = cat(sign_s, T_309) - node fsgnj = cat(T_310, T_311) + node T_259 = and(in.bits.cmd, UInt<3>("h05")) + node isSgnj = eq(UInt<3>("h04"), T_259) + node T_261 = and(in.bits.single, isSgnj) + node T_262 = bits(in.bits.rm, 1, 1) + node T_264 = eq(T_261, UInt<1>("h00")) + node T_265 = or(T_262, T_264) + node T_266 = bits(in.bits.in1, 32, 32) + node T_267 = bits(in.bits.rm, 0, 0) + node T_268 = mux(T_265, T_266, T_267) + node T_269 = bits(in.bits.in2, 32, 32) + node T_270 = and(T_261, T_269) + node sign_s = xor(T_268, T_270) + node T_273 = eq(in.bits.single, UInt<1>("h00")) + node T_274 = and(T_273, isSgnj) + node T_275 = bits(in.bits.rm, 1, 1) + node T_277 = eq(T_274, UInt<1>("h00")) + node T_278 = or(T_275, T_277) + node T_279 = bits(in.bits.in1, 64, 64) + node T_280 = bits(in.bits.rm, 0, 0) + node T_281 = mux(T_278, T_279, T_280) + node T_282 = bits(in.bits.in2, 64, 64) + node T_283 = and(T_274, T_282) + node sign_d = xor(T_281, T_283) + node T_285 = bits(in.bits.in1, 63, 33) + node T_286 = bits(in.bits.in1, 31, 0) + node T_287 = cat(sign_d, T_285) + node T_288 = cat(sign_s, T_286) + node fsgnj = cat(T_287, T_288) inst s2d of RecFNToRecFN - s2d.io.roundingMode <= UInt<1>("h00") - s2d.io.in <= UInt<1>("h00") + s2d.io is invalid s2d.clk <= clk s2d.reset <= reset inst d2s of RecFNToRecFN_121 - d2s.io.roundingMode <= UInt<1>("h00") - d2s.io.in <= UInt<1>("h00") + d2s.io is invalid d2s.clk <= clk d2s.reset <= reset s2d.io.in <= in.bits.in1 s2d.io.roundingMode <= in.bits.rm d2s.io.in <= in.bits.in1 d2s.io.roundingMode <= in.bits.rm - node T_319 = bits(in.bits.in1, 31, 29) - node T_320 = not(T_319) - node T_322 = eq(T_320, UInt<1>("h00")) - node T_323 = bits(in.bits.in1, 63, 61) - node T_324 = not(T_323) - node T_326 = eq(T_324, UInt<1>("h00")) - node isnan1 = mux(in.bits.single, T_322, T_326) - node T_328 = bits(in.bits.in2, 31, 29) - node T_329 = not(T_328) - node T_331 = eq(T_329, UInt<1>("h00")) - node T_332 = bits(in.bits.in2, 63, 61) - node T_333 = not(T_332) - node T_335 = eq(T_333, UInt<1>("h00")) - node isnan2 = mux(in.bits.single, T_331, T_335) - node T_337 = bit(in.bits.in1, 22) - node T_338 = bit(in.bits.in1, 51) - node T_339 = mux(in.bits.single, T_337, T_338) - node T_340 = not(T_339) - node issnan1 = and(isnan1, T_340) - node T_342 = bit(in.bits.in2, 22) - node T_343 = bit(in.bits.in2, 51) - node T_344 = mux(in.bits.single, T_342, T_343) - node T_345 = not(T_344) - node issnan2 = and(isnan2, T_345) - node T_347 = or(issnan1, issnan2) - node minmax_exc = cat(T_347, UInt<4>("h00")) - node isMax = bit(in.bits.rm, 0) - node T_351 = neq(isMax, io.lt) - node T_353 = eq(isnan1, UInt<1>("h00")) - node T_354 = and(T_351, T_353) - node isLHS = or(isnan2, T_354) + node T_292 = bits(in.bits.in1, 31, 29) + node T_293 = not(T_292) + node T_295 = eq(T_293, UInt<1>("h00")) + node T_296 = bits(in.bits.in1, 63, 61) + node T_297 = not(T_296) + node T_299 = eq(T_297, UInt<1>("h00")) + node isnan1 = mux(in.bits.single, T_295, T_299) + node T_301 = bits(in.bits.in2, 31, 29) + node T_302 = not(T_301) + node T_304 = eq(T_302, UInt<1>("h00")) + node T_305 = bits(in.bits.in2, 63, 61) + node T_306 = not(T_305) + node T_308 = eq(T_306, UInt<1>("h00")) + node isnan2 = mux(in.bits.single, T_304, T_308) + node T_310 = bits(in.bits.in1, 22, 22) + node T_311 = bits(in.bits.in1, 51, 51) + node T_312 = mux(in.bits.single, T_310, T_311) + node T_313 = not(T_312) + node issnan1 = and(isnan1, T_313) + node T_315 = bits(in.bits.in2, 22, 22) + node T_316 = bits(in.bits.in2, 51, 51) + node T_317 = mux(in.bits.single, T_315, T_316) + node T_318 = not(T_317) + node issnan2 = and(isnan2, T_318) + node T_320 = or(issnan1, issnan2) + node minmax_exc = cat(T_320, UInt<4>("h00")) + node isMax = bits(in.bits.rm, 0, 0) + node T_324 = neq(isMax, io.lt) + node T_326 = eq(isnan1, UInt<1>("h00")) + node T_327 = and(T_324, T_326) + node isLHS = or(isnan2, T_327) wire mux : {data : UInt<65>, exc : UInt<5>} - mux.exc <= UInt<1>("h00") - mux.data <= UInt<1>("h00") + mux is invalid mux.exc <= minmax_exc mux.data <= in.bits.in2 when isSgnj : mux.exc <= UInt<1>("h00") skip - node T_365 = or(isSgnj, isLHS) - when T_365 : + node T_336 = or(isSgnj, isLHS) + when T_336 : mux.data <= fsgnj skip - node T_368 = and(in.bits.cmd, UInt<3>("h04")) - node T_369 = eq(UInt<1>("h00"), T_368) - when T_369 : + node T_339 = and(in.bits.cmd, UInt<3>("h04")) + node T_340 = eq(UInt<1>("h00"), T_339) + when T_340 : when in.bits.single : - node T_371 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_372 = cat(T_371, d2s.io.out) - mux.data <= T_372 + node T_342 = asUInt(asSInt(UInt<32>("h0ffffffff"))) + node T_343 = cat(T_342, d2s.io.out) + mux.data <= T_343 mux.exc <= d2s.io.exceptionFlags skip - node T_374 = eq(in.bits.single, UInt<1>("h00")) - when T_374 : + node T_345 = eq(in.bits.single, UInt<1>("h00")) + when T_345 : mux.data <= s2d.io.out mux.exc <= s2d.io.exceptionFlags skip skip - reg T_377 : UInt<1>, clk, reset, UInt<1>("h00") - T_377 <= in.valid - reg T_378 : {data : UInt<65>, exc : UInt<5>}, clk, UInt<1>("h00"), T_378 + reg T_348 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + T_348 <= in.valid + reg T_349 : {data : UInt<65>, exc : UInt<5>}, clk when in.valid : - T_378 <- mux + T_349 <- mux skip - wire T_389 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} - T_389.bits.exc <= UInt<1>("h00") - T_389.bits.data <= UInt<1>("h00") - T_389.valid <= UInt<1>("h00") - T_389.valid <= T_377 - T_389.bits <- T_378 - io.out <- T_389 + wire T_360 : {valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}} + T_360 is invalid + T_360.valid <= T_348 + T_360.bits <- T_349 + io.out <- T_360 module DivSqrtRecF64_mulAddZ31 : input clk : Clock input reset : UInt<1> output io : {inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>, usingMulAdd : UInt<4>, latchMulAddA_0 : UInt<1>, mulAddA_0 : UInt<54>, latchMulAddB_0 : UInt<1>, mulAddB_0 : UInt<54>, mulAddC_2 : UInt<105>, flip mulAddResult_3 : UInt<105>} - io.mulAddC_2 <= UInt<1>("h00") - io.mulAddB_0 <= UInt<1>("h00") - io.latchMulAddB_0 <= UInt<1>("h00") - io.mulAddA_0 <= UInt<1>("h00") - io.latchMulAddA_0 <= UInt<1>("h00") - io.usingMulAdd <= UInt<1>("h00") - io.exceptionFlags <= UInt<1>("h00") - io.out <= UInt<1>("h00") - io.outValid_sqrt <= UInt<1>("h00") - io.outValid_div <= UInt<1>("h00") - io.inReady_sqrt <= UInt<1>("h00") - io.inReady_div <= UInt<1>("h00") - reg valid_PA : UInt<1>, clk, reset, UInt<1>("h00") - reg sqrtOp_PA : UInt<1>, clk, UInt<1>("h00"), sqrtOp_PA - reg sign_PA : UInt<1>, clk, UInt<1>("h00"), sign_PA - reg specialCodeB_PA : UInt<3>, clk, UInt<1>("h00"), specialCodeB_PA - reg fractB_51_PA : UInt<1>, clk, UInt<1>("h00"), fractB_51_PA - reg roundingMode_PA : UInt<2>, clk, UInt<1>("h00"), roundingMode_PA - reg specialCodeA_PA : UInt<3>, clk, UInt<1>("h00"), specialCodeA_PA - reg fractA_51_PA : UInt<1>, clk, UInt<1>("h00"), fractA_51_PA - reg exp_PA : UInt<14>, clk, UInt<1>("h00"), exp_PA - reg fractB_other_PA : UInt<51>, clk, UInt<1>("h00"), fractB_other_PA - reg fractA_other_PA : UInt<51>, clk, UInt<1>("h00"), fractA_other_PA - reg valid_PB : UInt<1>, clk, reset, UInt<1>("h00") - reg sqrtOp_PB : UInt<1>, clk, UInt<1>("h00"), sqrtOp_PB - reg sign_PB : UInt<1>, clk, UInt<1>("h00"), sign_PB - reg specialCodeA_PB : UInt<3>, clk, UInt<1>("h00"), specialCodeA_PB - reg fractA_51_PB : UInt<1>, clk, UInt<1>("h00"), fractA_51_PB - reg specialCodeB_PB : UInt<3>, clk, UInt<1>("h00"), specialCodeB_PB - reg fractB_51_PB : UInt<1>, clk, UInt<1>("h00"), fractB_51_PB - reg roundingMode_PB : UInt<2>, clk, UInt<1>("h00"), roundingMode_PB - reg exp_PB : UInt<14>, clk, UInt<1>("h00"), exp_PB - reg fractA_0_PB : UInt<1>, clk, UInt<1>("h00"), fractA_0_PB - reg fractB_other_PB : UInt<51>, clk, UInt<1>("h00"), fractB_other_PB - reg valid_PC : UInt<1>, clk, reset, UInt<1>("h00") - reg sqrtOp_PC : UInt<1>, clk, UInt<1>("h00"), sqrtOp_PC - reg sign_PC : UInt<1>, clk, UInt<1>("h00"), sign_PC - reg specialCodeA_PC : UInt<3>, clk, UInt<1>("h00"), specialCodeA_PC - reg fractA_51_PC : UInt<1>, clk, UInt<1>("h00"), fractA_51_PC - reg specialCodeB_PC : UInt<3>, clk, UInt<1>("h00"), specialCodeB_PC - reg fractB_51_PC : UInt<1>, clk, UInt<1>("h00"), fractB_51_PC - reg roundingMode_PC : UInt<2>, clk, UInt<1>("h00"), roundingMode_PC - reg exp_PC : UInt<14>, clk, UInt<1>("h00"), exp_PC - reg fractA_0_PC : UInt<1>, clk, UInt<1>("h00"), fractA_0_PC - reg fractB_other_PC : UInt<51>, clk, UInt<1>("h00"), fractB_other_PC - reg cycleNum_A : UInt<3>, clk, reset, UInt<3>("h00") - reg cycleNum_B : UInt<4>, clk, reset, UInt<4>("h00") - reg cycleNum_C : UInt<3>, clk, reset, UInt<3>("h00") - reg cycleNum_E : UInt<3>, clk, reset, UInt<3>("h00") - reg fractR0_A : UInt<9>, clk, UInt<1>("h00"), fractR0_A - reg hiSqrR0_A_sqrt : UInt<10>, clk, UInt<1>("h00"), hiSqrR0_A_sqrt - reg partNegSigma0_A : UInt<21>, clk, UInt<1>("h00"), partNegSigma0_A - reg nextMulAdd9A_A : UInt<9>, clk, UInt<1>("h00"), nextMulAdd9A_A - reg nextMulAdd9B_A : UInt<9>, clk, UInt<1>("h00"), nextMulAdd9B_A - reg ER1_B_sqrt : UInt<17>, clk, UInt<1>("h00"), ER1_B_sqrt - reg ESqrR1_B_sqrt : UInt<32>, clk, UInt<1>("h00"), ESqrR1_B_sqrt - reg sigX1_B : UInt<58>, clk, UInt<1>("h00"), sigX1_B - reg sqrSigma1_C : UInt<33>, clk, UInt<1>("h00"), sqrSigma1_C - reg sigXN_C : UInt<58>, clk, UInt<1>("h00"), sigXN_C - reg u_C_sqrt : UInt<31>, clk, UInt<1>("h00"), u_C_sqrt - reg E_E_div : UInt<1>, clk, UInt<1>("h00"), E_E_div - reg sigT_E : UInt<53>, clk, UInt<1>("h00"), sigT_E - reg extraT_E : UInt<1>, clk, UInt<1>("h00"), extraT_E - reg isNegRemT_E : UInt<1>, clk, UInt<1>("h00"), isNegRemT_E - reg trueEqX_E1 : UInt<1>, clk, UInt<1>("h00"), trueEqX_E1 + io is invalid + reg valid_PA : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg sqrtOp_PA : UInt<1>, clk + reg sign_PA : UInt<1>, clk + reg specialCodeB_PA : UInt<3>, clk + reg fractB_51_PA : UInt<1>, clk + reg roundingMode_PA : UInt<2>, clk + reg specialCodeA_PA : UInt<3>, clk + reg fractA_51_PA : UInt<1>, clk + reg exp_PA : UInt<14>, clk + reg fractB_other_PA : UInt<51>, clk + reg fractA_other_PA : UInt<51>, clk + reg valid_PB : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg sqrtOp_PB : UInt<1>, clk + reg sign_PB : UInt<1>, clk + reg specialCodeA_PB : UInt<3>, clk + reg fractA_51_PB : UInt<1>, clk + reg specialCodeB_PB : UInt<3>, clk + reg fractB_51_PB : UInt<1>, clk + reg roundingMode_PB : UInt<2>, clk + reg exp_PB : UInt<14>, clk + reg fractA_0_PB : UInt<1>, clk + reg fractB_other_PB : UInt<51>, clk + reg valid_PC : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg sqrtOp_PC : UInt<1>, clk + reg sign_PC : UInt<1>, clk + reg specialCodeA_PC : UInt<3>, clk + reg fractA_51_PC : UInt<1>, clk + reg specialCodeB_PC : UInt<3>, clk + reg fractB_51_PC : UInt<1>, clk + reg roundingMode_PC : UInt<2>, clk + reg exp_PC : UInt<14>, clk + reg fractA_0_PC : UInt<1>, clk + reg fractB_other_PC : UInt<51>, clk + reg cycleNum_A : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + reg cycleNum_B : UInt<4>, clk with : (reset => (reset, UInt<4>("h00"))) + reg cycleNum_C : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + reg cycleNum_E : UInt<3>, clk with : (reset => (reset, UInt<3>("h00"))) + reg fractR0_A : UInt<9>, clk + reg hiSqrR0_A_sqrt : UInt<10>, clk + reg partNegSigma0_A : UInt<21>, clk + reg nextMulAdd9A_A : UInt<9>, clk + reg nextMulAdd9B_A : UInt<9>, clk + reg ER1_B_sqrt : UInt<17>, clk + reg ESqrR1_B_sqrt : UInt<32>, clk + reg sigX1_B : UInt<58>, clk + reg sqrSigma1_C : UInt<33>, clk + reg sigXN_C : UInt<58>, clk + reg u_C_sqrt : UInt<31>, clk + reg E_E_div : UInt<1>, clk + reg sigT_E : UInt<53>, clk + reg extraT_E : UInt<1>, clk + reg isNegRemT_E : UInt<1>, clk + reg trueEqX_E1 : UInt<1>, clk wire ready_PA : UInt<1> - ready_PA <= UInt<1>("h00") + ready_PA is invalid wire ready_PB : UInt<1> - ready_PB <= UInt<1>("h00") + ready_PB is invalid wire ready_PC : UInt<1> - ready_PC <= UInt<1>("h00") + ready_PC is invalid wire leaving_PA : UInt<1> - leaving_PA <= UInt<1>("h00") + leaving_PA is invalid wire leaving_PB : UInt<1> - leaving_PB <= UInt<1>("h00") + leaving_PB is invalid wire leaving_PC : UInt<1> - leaving_PC <= UInt<1>("h00") + leaving_PC is invalid wire cyc_B10_sqrt : UInt<1> - cyc_B10_sqrt <= UInt<1>("h00") + cyc_B10_sqrt is invalid wire cyc_B9_sqrt : UInt<1> - cyc_B9_sqrt <= UInt<1>("h00") + cyc_B9_sqrt is invalid wire cyc_B8_sqrt : UInt<1> - cyc_B8_sqrt <= UInt<1>("h00") + cyc_B8_sqrt is invalid wire cyc_B7_sqrt : UInt<1> - cyc_B7_sqrt <= UInt<1>("h00") + cyc_B7_sqrt is invalid wire cyc_B6 : UInt<1> - cyc_B6 <= UInt<1>("h00") + cyc_B6 is invalid wire cyc_B5 : UInt<1> - cyc_B5 <= UInt<1>("h00") + cyc_B5 is invalid wire cyc_B4 : UInt<1> - cyc_B4 <= UInt<1>("h00") + cyc_B4 is invalid wire cyc_B3 : UInt<1> - cyc_B3 <= UInt<1>("h00") + cyc_B3 is invalid wire cyc_B2 : UInt<1> - cyc_B2 <= UInt<1>("h00") + cyc_B2 is invalid wire cyc_B1 : UInt<1> - cyc_B1 <= UInt<1>("h00") + cyc_B1 is invalid wire cyc_B6_div : UInt<1> - cyc_B6_div <= UInt<1>("h00") + cyc_B6_div is invalid wire cyc_B5_div : UInt<1> - cyc_B5_div <= UInt<1>("h00") + cyc_B5_div is invalid wire cyc_B4_div : UInt<1> - cyc_B4_div <= UInt<1>("h00") + cyc_B4_div is invalid wire cyc_B3_div : UInt<1> - cyc_B3_div <= UInt<1>("h00") + cyc_B3_div is invalid wire cyc_B2_div : UInt<1> - cyc_B2_div <= UInt<1>("h00") + cyc_B2_div is invalid wire cyc_B1_div : UInt<1> - cyc_B1_div <= UInt<1>("h00") + cyc_B1_div is invalid wire cyc_B6_sqrt : UInt<1> - cyc_B6_sqrt <= UInt<1>("h00") + cyc_B6_sqrt is invalid wire cyc_B5_sqrt : UInt<1> - cyc_B5_sqrt <= UInt<1>("h00") + cyc_B5_sqrt is invalid wire cyc_B4_sqrt : UInt<1> - cyc_B4_sqrt <= UInt<1>("h00") + cyc_B4_sqrt is invalid wire cyc_B3_sqrt : UInt<1> - cyc_B3_sqrt <= UInt<1>("h00") + cyc_B3_sqrt is invalid wire cyc_B2_sqrt : UInt<1> - cyc_B2_sqrt <= UInt<1>("h00") + cyc_B2_sqrt is invalid wire cyc_B1_sqrt : UInt<1> - cyc_B1_sqrt <= UInt<1>("h00") + cyc_B1_sqrt is invalid wire cyc_C5 : UInt<1> - cyc_C5 <= UInt<1>("h00") + cyc_C5 is invalid wire cyc_C4 : UInt<1> - cyc_C4 <= UInt<1>("h00") + cyc_C4 is invalid wire valid_normalCase_leaving_PB : UInt<1> - valid_normalCase_leaving_PB <= UInt<1>("h00") + valid_normalCase_leaving_PB is invalid wire cyc_C2 : UInt<1> - cyc_C2 <= UInt<1>("h00") + cyc_C2 is invalid wire cyc_C1 : UInt<1> - cyc_C1 <= UInt<1>("h00") + cyc_C1 is invalid wire cyc_E4 : UInt<1> - cyc_E4 <= UInt<1>("h00") + cyc_E4 is invalid wire cyc_E3 : UInt<1> - cyc_E3 <= UInt<1>("h00") + cyc_E3 is invalid wire cyc_E2 : UInt<1> - cyc_E2 <= UInt<1>("h00") + cyc_E2 is invalid wire cyc_E1 : UInt<1> - cyc_E1 <= UInt<1>("h00") + cyc_E1 is invalid wire zSigma1_B4 : UInt<?> - zSigma1_B4 <= UInt<1>("h00") + zSigma1_B4 is invalid wire sigXNU_B3_CX : UInt<?> - sigXNU_B3_CX <= UInt<1>("h00") + sigXNU_B3_CX is invalid wire zComplSigT_C1_sqrt : UInt<?> - zComplSigT_C1_sqrt <= UInt<1>("h00") + zComplSigT_C1_sqrt is invalid wire zComplSigT_C1 : UInt<?> - zComplSigT_C1 <= UInt<1>("h00") - node T_251 = not(cyc_B7_sqrt) - node T_252 = and(ready_PA, T_251) - node T_253 = not(cyc_B6_sqrt) - node T_254 = and(T_252, T_253) - node T_255 = not(cyc_B5_sqrt) - node T_256 = and(T_254, T_255) - node T_257 = not(cyc_B4_sqrt) - node T_258 = and(T_256, T_257) - node T_259 = not(cyc_B3) - node T_260 = and(T_258, T_259) - node T_261 = not(cyc_B2) - node T_262 = and(T_260, T_261) - node T_263 = not(cyc_B1_sqrt) - node T_264 = and(T_262, T_263) - node T_265 = not(cyc_C5) - node T_266 = and(T_264, T_265) - node T_267 = not(cyc_C4) - node T_268 = and(T_266, T_267) - io.inReady_div <= T_268 - node T_269 = not(cyc_B6_sqrt) - node T_270 = and(ready_PA, T_269) - node T_271 = not(cyc_B5_sqrt) - node T_272 = and(T_270, T_271) - node T_273 = not(cyc_B4_sqrt) - node T_274 = and(T_272, T_273) - node T_275 = not(cyc_B2_div) - node T_276 = and(T_274, T_275) - node T_277 = not(cyc_B1_sqrt) - node T_278 = and(T_276, T_277) - io.inReady_sqrt <= T_278 - node T_279 = and(io.inReady_div, io.inValid) - node T_280 = not(io.sqrtOp) - node cyc_S_div = and(T_279, T_280) - node T_282 = and(io.inReady_sqrt, io.inValid) - node cyc_S_sqrt = and(T_282, io.sqrtOp) + zComplSigT_C1 is invalid + node T_210 = not(cyc_B7_sqrt) + node T_211 = and(ready_PA, T_210) + node T_212 = not(cyc_B6_sqrt) + node T_213 = and(T_211, T_212) + node T_214 = not(cyc_B5_sqrt) + node T_215 = and(T_213, T_214) + node T_216 = not(cyc_B4_sqrt) + node T_217 = and(T_215, T_216) + node T_218 = not(cyc_B3) + node T_219 = and(T_217, T_218) + node T_220 = not(cyc_B2) + node T_221 = and(T_219, T_220) + node T_222 = not(cyc_B1_sqrt) + node T_223 = and(T_221, T_222) + node T_224 = not(cyc_C5) + node T_225 = and(T_223, T_224) + node T_226 = not(cyc_C4) + node T_227 = and(T_225, T_226) + io.inReady_div <= T_227 + node T_228 = not(cyc_B6_sqrt) + node T_229 = and(ready_PA, T_228) + node T_230 = not(cyc_B5_sqrt) + node T_231 = and(T_229, T_230) + node T_232 = not(cyc_B4_sqrt) + node T_233 = and(T_231, T_232) + node T_234 = not(cyc_B2_div) + node T_235 = and(T_233, T_234) + node T_236 = not(cyc_B1_sqrt) + node T_237 = and(T_235, T_236) + io.inReady_sqrt <= T_237 + node T_238 = and(io.inReady_div, io.inValid) + node T_239 = not(io.sqrtOp) + node cyc_S_div = and(T_238, T_239) + node T_241 = and(io.inReady_sqrt, io.inValid) + node cyc_S_sqrt = and(T_241, io.sqrtOp) node cyc_S = or(cyc_S_div, cyc_S_sqrt) - node signA_S = bit(io.a, 64) + node signA_S = bits(io.a, 64, 64) node expA_S = bits(io.a, 63, 52) node fractA_S = bits(io.a, 51, 0) node specialCodeA_S = bits(expA_S, 11, 9) node isZeroA_S = eq(specialCodeA_S, UInt<3>("h00")) - node T_291 = bits(specialCodeA_S, 2, 1) - node isSpecialA_S = eq(T_291, UInt<2>("h03")) - node signB_S = bit(io.b, 64) + node T_250 = bits(specialCodeA_S, 2, 1) + node isSpecialA_S = eq(T_250, UInt<2>("h03")) + node signB_S = bits(io.b, 64, 64) node expB_S = bits(io.b, 63, 52) node fractB_S = bits(io.b, 51, 0) node specialCodeB_S = bits(expB_S, 11, 9) node isZeroB_S = eq(specialCodeB_S, UInt<3>("h00")) - node T_300 = bits(specialCodeB_S, 2, 1) - node isSpecialB_S = eq(T_300, UInt<2>("h03")) - node T_303 = xor(signA_S, signB_S) - node sign_S = mux(io.sqrtOp, signB_S, T_303) - node T_305 = not(isSpecialA_S) - node T_306 = not(isSpecialB_S) - node T_307 = and(T_305, T_306) - node T_308 = not(isZeroA_S) - node T_309 = and(T_307, T_308) - node T_310 = not(isZeroB_S) - node normalCase_S_div = and(T_309, T_310) - node T_312 = not(isSpecialB_S) - node T_313 = not(isZeroB_S) - node T_314 = and(T_312, T_313) - node T_315 = not(signB_S) - node normalCase_S_sqrt = and(T_314, T_315) + node T_259 = bits(specialCodeB_S, 2, 1) + node isSpecialB_S = eq(T_259, UInt<2>("h03")) + node T_262 = xor(signA_S, signB_S) + node sign_S = mux(io.sqrtOp, signB_S, T_262) + node T_264 = not(isSpecialA_S) + node T_265 = not(isSpecialB_S) + node T_266 = and(T_264, T_265) + node T_267 = not(isZeroA_S) + node T_268 = and(T_266, T_267) + node T_269 = not(isZeroB_S) + node normalCase_S_div = and(T_268, T_269) + node T_271 = not(isSpecialB_S) + node T_272 = not(isZeroB_S) + node T_273 = and(T_271, T_272) + node T_274 = not(signB_S) + node normalCase_S_sqrt = and(T_273, T_274) node normalCase_S = mux(io.sqrtOp, normalCase_S_sqrt, normalCase_S_div) node entering_PA_normalCase_div = and(cyc_S_div, normalCase_S_div) node entering_PA_normalCase_sqrt = and(cyc_S_sqrt, normalCase_S_sqrt) node entering_PA_normalCase = or(entering_PA_normalCase_div, entering_PA_normalCase_sqrt) - node T_321 = not(ready_PB) - node T_322 = or(valid_PA, T_321) - node T_323 = and(cyc_S, T_322) - node entering_PA = or(entering_PA_normalCase, T_323) - node T_325 = not(normalCase_S) - node T_326 = and(cyc_S, T_325) - node T_327 = not(valid_PA) - node T_328 = and(T_326, T_327) - node T_329 = not(valid_PB) - node T_330 = not(ready_PC) - node T_331 = and(T_329, T_330) - node T_332 = or(leaving_PB, T_331) - node entering_PB_S = and(T_328, T_332) - node T_334 = not(normalCase_S) - node T_335 = and(cyc_S, T_334) - node T_336 = not(valid_PA) - node T_337 = and(T_335, T_336) - node T_338 = not(valid_PB) - node T_339 = and(T_337, T_338) - node entering_PC_S = and(T_339, ready_PC) - node T_341 = or(entering_PA, leaving_PA) - when T_341 : + node T_280 = not(ready_PB) + node T_281 = or(valid_PA, T_280) + node T_282 = and(cyc_S, T_281) + node entering_PA = or(entering_PA_normalCase, T_282) + node T_284 = not(normalCase_S) + node T_285 = and(cyc_S, T_284) + node T_286 = not(valid_PA) + node T_287 = and(T_285, T_286) + node T_288 = not(valid_PB) + node T_289 = not(ready_PC) + node T_290 = and(T_288, T_289) + node T_291 = or(leaving_PB, T_290) + node entering_PB_S = and(T_287, T_291) + node T_293 = not(normalCase_S) + node T_294 = and(cyc_S, T_293) + node T_295 = not(valid_PA) + node T_296 = and(T_294, T_295) + node T_297 = not(valid_PB) + node T_298 = and(T_296, T_297) + node entering_PC_S = and(T_298, ready_PC) + node T_300 = or(entering_PA, leaving_PA) + when T_300 : valid_PA <= entering_PA skip when entering_PA : sqrtOp_PA <= io.sqrtOp sign_PA <= sign_S specialCodeB_PA <= specialCodeB_S - node T_342 = bit(fractB_S, 51) - fractB_51_PA <= T_342 + node T_301 = bits(fractB_S, 51, 51) + fractB_51_PA <= T_301 roundingMode_PA <= io.roundingMode skip - node T_343 = not(io.sqrtOp) - node T_344 = and(entering_PA, T_343) - when T_344 : + node T_302 = not(io.sqrtOp) + node T_303 = and(entering_PA, T_302) + when T_303 : specialCodeA_PA <= specialCodeA_S - node T_345 = bit(fractA_S, 51) - fractA_51_PA <= T_345 + node T_304 = bits(fractA_S, 51, 51) + fractA_51_PA <= T_304 skip when entering_PA_normalCase : - node T_346 = bit(expB_S, 11) - node T_348 = subw(UInt<3>("h00"), T_346) - node T_349 = bits(expB_S, 10, 0) - node T_350 = not(T_349) - node T_351 = cat(T_348, T_350) - node T_352 = addw(expA_S, T_351) - node T_353 = mux(io.sqrtOp, expB_S, T_352) - exp_PA <= T_353 - node T_354 = bits(fractB_S, 50, 0) - fractB_other_PA <= T_354 + node T_305 = bits(expB_S, 11, 11) + node T_307 = sub(UInt<3>("h00"), T_305) + node T_308 = tail(T_307, 1) + node T_309 = bits(expB_S, 10, 0) + node T_310 = not(T_309) + node T_311 = cat(T_308, T_310) + node T_312 = add(expA_S, T_311) + node T_313 = tail(T_312, 1) + node T_314 = mux(io.sqrtOp, expB_S, T_313) + exp_PA <= T_314 + node T_315 = bits(fractB_S, 50, 0) + fractB_other_PA <= T_315 skip when entering_PA_normalCase_div : - node T_355 = bits(fractA_S, 50, 0) - fractA_other_PA <= T_355 + node T_316 = bits(fractA_S, 50, 0) + fractA_other_PA <= T_316 skip node isZeroA_PA = eq(specialCodeA_PA, UInt<3>("h00")) - node T_358 = bits(specialCodeA_PA, 2, 1) - node isSpecialA_PA = eq(T_358, UInt<2>("h03")) - node T_362 = cat(fractA_51_PA, fractA_other_PA) - node sigA_PA = cat(UInt<1>("h01"), T_362) + node T_319 = bits(specialCodeA_PA, 2, 1) + node isSpecialA_PA = eq(T_319, UInt<2>("h03")) + node T_323 = cat(fractA_51_PA, fractA_other_PA) + node sigA_PA = cat(UInt<1>("h01"), T_323) node isZeroB_PA = eq(specialCodeB_PA, UInt<3>("h00")) - node T_366 = bits(specialCodeB_PA, 2, 1) - node isSpecialB_PA = eq(T_366, UInt<2>("h03")) - node T_370 = cat(fractB_51_PA, fractB_other_PA) - node sigB_PA = cat(UInt<1>("h01"), T_370) - node T_372 = not(isSpecialB_PA) - node T_373 = not(isZeroB_PA) - node T_374 = and(T_372, T_373) - node T_375 = not(sign_PA) - node T_376 = and(T_374, T_375) - node T_377 = not(isSpecialA_PA) - node T_378 = not(isSpecialB_PA) - node T_379 = and(T_377, T_378) - node T_380 = not(isZeroA_PA) - node T_381 = and(T_379, T_380) - node T_382 = not(isZeroB_PA) - node T_383 = and(T_381, T_382) - node normalCase_PA = mux(sqrtOp_PA, T_376, T_383) + node T_327 = bits(specialCodeB_PA, 2, 1) + node isSpecialB_PA = eq(T_327, UInt<2>("h03")) + node T_331 = cat(fractB_51_PA, fractB_other_PA) + node sigB_PA = cat(UInt<1>("h01"), T_331) + node T_333 = not(isSpecialB_PA) + node T_334 = not(isZeroB_PA) + node T_335 = and(T_333, T_334) + node T_336 = not(sign_PA) + node T_337 = and(T_335, T_336) + node T_338 = not(isSpecialA_PA) + node T_339 = not(isSpecialB_PA) + node T_340 = and(T_338, T_339) + node T_341 = not(isZeroA_PA) + node T_342 = and(T_340, T_341) + node T_343 = not(isZeroB_PA) + node T_344 = and(T_342, T_343) + node normalCase_PA = mux(sqrtOp_PA, T_337, T_344) node valid_normalCase_leaving_PA = or(cyc_B4_div, cyc_B7_sqrt) node valid_leaving_PA = mux(normalCase_PA, valid_normalCase_leaving_PA, ready_PB) - node T_387 = and(valid_PA, valid_leaving_PA) - leaving_PA <= T_387 - node T_388 = not(valid_PA) - node T_389 = or(T_388, valid_leaving_PA) - ready_PA <= T_389 - node T_390 = and(valid_PA, normalCase_PA) - node entering_PB_normalCase = and(T_390, valid_normalCase_leaving_PA) + node T_348 = and(valid_PA, valid_leaving_PA) + leaving_PA <= T_348 + node T_349 = not(valid_PA) + node T_350 = or(T_349, valid_leaving_PA) + ready_PA <= T_350 + node T_351 = and(valid_PA, normalCase_PA) + node entering_PB_normalCase = and(T_351, valid_normalCase_leaving_PA) node entering_PB = or(entering_PB_S, leaving_PA) - node T_393 = or(entering_PB, leaving_PB) - when T_393 : + node T_354 = or(entering_PB, leaving_PB) + when T_354 : valid_PB <= entering_PB skip when entering_PB : - node T_394 = mux(valid_PA, sqrtOp_PA, io.sqrtOp) - sqrtOp_PB <= T_394 - node T_395 = mux(valid_PA, sign_PA, sign_S) - sign_PB <= T_395 - node T_396 = mux(valid_PA, specialCodeA_PA, specialCodeA_S) - specialCodeA_PB <= T_396 - node T_397 = bit(fractA_S, 51) - node T_398 = mux(valid_PA, fractA_51_PA, T_397) - fractA_51_PB <= T_398 - node T_399 = mux(valid_PA, specialCodeB_PA, specialCodeB_S) - specialCodeB_PB <= T_399 - node T_400 = bit(fractB_S, 51) - node T_401 = mux(valid_PA, fractB_51_PA, T_400) - fractB_51_PB <= T_401 - node T_402 = mux(valid_PA, roundingMode_PA, io.roundingMode) - roundingMode_PB <= T_402 + node T_355 = mux(valid_PA, sqrtOp_PA, io.sqrtOp) + sqrtOp_PB <= T_355 + node T_356 = mux(valid_PA, sign_PA, sign_S) + sign_PB <= T_356 + node T_357 = mux(valid_PA, specialCodeA_PA, specialCodeA_S) + specialCodeA_PB <= T_357 + node T_358 = bits(fractA_S, 51, 51) + node T_359 = mux(valid_PA, fractA_51_PA, T_358) + fractA_51_PB <= T_359 + node T_360 = mux(valid_PA, specialCodeB_PA, specialCodeB_S) + specialCodeB_PB <= T_360 + node T_361 = bits(fractB_S, 51, 51) + node T_362 = mux(valid_PA, fractB_51_PA, T_361) + fractB_51_PB <= T_362 + node T_363 = mux(valid_PA, roundingMode_PA, io.roundingMode) + roundingMode_PB <= T_363 skip when entering_PB_normalCase : exp_PB <= exp_PA - node T_403 = bit(fractA_other_PA, 0) - fractA_0_PB <= T_403 + node T_364 = bits(fractA_other_PA, 0, 0) + fractA_0_PB <= T_364 fractB_other_PB <= fractB_other_PA skip node isZeroA_PB = eq(specialCodeA_PB, UInt<3>("h00")) - node T_406 = bits(specialCodeA_PB, 2, 1) - node isSpecialA_PB = eq(T_406, UInt<2>("h03")) + node T_367 = bits(specialCodeA_PB, 2, 1) + node isSpecialA_PB = eq(T_367, UInt<2>("h03")) node isZeroB_PB = eq(specialCodeB_PB, UInt<3>("h00")) - node T_411 = bits(specialCodeB_PB, 2, 1) - node isSpecialB_PB = eq(T_411, UInt<2>("h03")) - node T_414 = not(isSpecialB_PB) - node T_415 = not(isZeroB_PB) - node T_416 = and(T_414, T_415) - node T_417 = not(sign_PB) - node T_418 = and(T_416, T_417) - node T_419 = not(isSpecialA_PB) - node T_420 = not(isSpecialB_PB) - node T_421 = and(T_419, T_420) - node T_422 = not(isZeroA_PB) - node T_423 = and(T_421, T_422) - node T_424 = not(isZeroB_PB) - node T_425 = and(T_423, T_424) - node normalCase_PB = mux(sqrtOp_PB, T_418, T_425) + node T_372 = bits(specialCodeB_PB, 2, 1) + node isSpecialB_PB = eq(T_372, UInt<2>("h03")) + node T_375 = not(isSpecialB_PB) + node T_376 = not(isZeroB_PB) + node T_377 = and(T_375, T_376) + node T_378 = not(sign_PB) + node T_379 = and(T_377, T_378) + node T_380 = not(isSpecialA_PB) + node T_381 = not(isSpecialB_PB) + node T_382 = and(T_380, T_381) + node T_383 = not(isZeroA_PB) + node T_384 = and(T_382, T_383) + node T_385 = not(isZeroB_PB) + node T_386 = and(T_384, T_385) + node normalCase_PB = mux(sqrtOp_PB, T_379, T_386) node valid_leaving_PB = mux(normalCase_PB, valid_normalCase_leaving_PB, ready_PC) - node T_428 = and(valid_PB, valid_leaving_PB) - leaving_PB <= T_428 - node T_429 = not(valid_PB) - node T_430 = or(T_429, valid_leaving_PB) - ready_PB <= T_430 - node T_431 = and(valid_PB, normalCase_PB) - node entering_PC_normalCase = and(T_431, valid_normalCase_leaving_PB) + node T_389 = and(valid_PB, valid_leaving_PB) + leaving_PB <= T_389 + node T_390 = not(valid_PB) + node T_391 = or(T_390, valid_leaving_PB) + ready_PB <= T_391 + node T_392 = and(valid_PB, normalCase_PB) + node entering_PC_normalCase = and(T_392, valid_normalCase_leaving_PB) node entering_PC = or(entering_PC_S, leaving_PB) - node T_434 = or(entering_PC, leaving_PC) - when T_434 : + node T_395 = or(entering_PC, leaving_PC) + when T_395 : valid_PC <= entering_PC skip when entering_PC : - node T_435 = mux(valid_PB, sqrtOp_PB, io.sqrtOp) - sqrtOp_PC <= T_435 - node T_436 = mux(valid_PB, sign_PB, sign_S) - sign_PC <= T_436 - node T_437 = mux(valid_PB, specialCodeA_PB, specialCodeA_S) - specialCodeA_PC <= T_437 - node T_438 = bit(fractA_S, 51) - node T_439 = mux(valid_PB, fractA_51_PB, T_438) - fractA_51_PC <= T_439 - node T_440 = mux(valid_PB, specialCodeB_PB, specialCodeB_S) - specialCodeB_PC <= T_440 - node T_441 = bit(fractB_S, 51) - node T_442 = mux(valid_PB, fractB_51_PB, T_441) - fractB_51_PC <= T_442 - node T_443 = mux(valid_PB, roundingMode_PB, io.roundingMode) - roundingMode_PC <= T_443 + node T_396 = mux(valid_PB, sqrtOp_PB, io.sqrtOp) + sqrtOp_PC <= T_396 + node T_397 = mux(valid_PB, sign_PB, sign_S) + sign_PC <= T_397 + node T_398 = mux(valid_PB, specialCodeA_PB, specialCodeA_S) + specialCodeA_PC <= T_398 + node T_399 = bits(fractA_S, 51, 51) + node T_400 = mux(valid_PB, fractA_51_PB, T_399) + fractA_51_PC <= T_400 + node T_401 = mux(valid_PB, specialCodeB_PB, specialCodeB_S) + specialCodeB_PC <= T_401 + node T_402 = bits(fractB_S, 51, 51) + node T_403 = mux(valid_PB, fractB_51_PB, T_402) + fractB_51_PC <= T_403 + node T_404 = mux(valid_PB, roundingMode_PB, io.roundingMode) + roundingMode_PC <= T_404 skip when entering_PC_normalCase : exp_PC <= exp_PB @@ -38352,79 +30378,81 @@ circuit Top : fractB_other_PC <= fractB_other_PB skip node isZeroA_PC = eq(specialCodeA_PC, UInt<3>("h00")) - node T_446 = bits(specialCodeA_PC, 2, 1) - node isSpecialA_PC = eq(T_446, UInt<2>("h03")) - node T_449 = bit(specialCodeA_PC, 0) - node T_450 = not(T_449) - node isInfA_PC = and(isSpecialA_PC, T_450) - node T_452 = bit(specialCodeA_PC, 0) - node isNaNA_PC = and(isSpecialA_PC, T_452) - node T_454 = not(fractA_51_PC) - node isSigNaNA_PC = and(isNaNA_PC, T_454) + node T_407 = bits(specialCodeA_PC, 2, 1) + node isSpecialA_PC = eq(T_407, UInt<2>("h03")) + node T_410 = bits(specialCodeA_PC, 0, 0) + node T_411 = not(T_410) + node isInfA_PC = and(isSpecialA_PC, T_411) + node T_413 = bits(specialCodeA_PC, 0, 0) + node isNaNA_PC = and(isSpecialA_PC, T_413) + node T_415 = not(fractA_51_PC) + node isSigNaNA_PC = and(isNaNA_PC, T_415) node isZeroB_PC = eq(specialCodeB_PC, UInt<3>("h00")) - node T_458 = bits(specialCodeB_PC, 2, 1) - node isSpecialB_PC = eq(T_458, UInt<2>("h03")) - node T_461 = bit(specialCodeB_PC, 0) - node T_462 = not(T_461) - node isInfB_PC = and(isSpecialB_PC, T_462) - node T_464 = bit(specialCodeB_PC, 0) - node isNaNB_PC = and(isSpecialB_PC, T_464) - node T_466 = not(fractB_51_PC) - node isSigNaNB_PC = and(isNaNB_PC, T_466) - node T_469 = cat(fractB_51_PC, fractB_other_PC) - node sigB_PC = cat(UInt<1>("h01"), T_469) - node T_471 = not(isSpecialB_PC) - node T_472 = not(isZeroB_PC) - node T_473 = and(T_471, T_472) - node T_474 = not(sign_PC) - node T_475 = and(T_473, T_474) - node T_476 = not(isSpecialA_PC) - node T_477 = not(isSpecialB_PC) - node T_478 = and(T_476, T_477) - node T_479 = not(isZeroA_PC) - node T_480 = and(T_478, T_479) - node T_481 = not(isZeroB_PC) - node T_482 = and(T_480, T_481) - node normalCase_PC = mux(sqrtOp_PC, T_475, T_482) - node expP2_PC = addw(exp_PC, UInt<2>("h02")) - node T_486 = bit(exp_PC, 0) - node T_487 = bits(expP2_PC, 13, 1) - node T_489 = cat(T_487, UInt<1>("h00")) - node T_490 = bits(exp_PC, 13, 1) - node T_492 = cat(T_490, UInt<1>("h01")) - node expP1_PC = mux(T_486, T_489, T_492) + node T_419 = bits(specialCodeB_PC, 2, 1) + node isSpecialB_PC = eq(T_419, UInt<2>("h03")) + node T_422 = bits(specialCodeB_PC, 0, 0) + node T_423 = not(T_422) + node isInfB_PC = and(isSpecialB_PC, T_423) + node T_425 = bits(specialCodeB_PC, 0, 0) + node isNaNB_PC = and(isSpecialB_PC, T_425) + node T_427 = not(fractB_51_PC) + node isSigNaNB_PC = and(isNaNB_PC, T_427) + node T_430 = cat(fractB_51_PC, fractB_other_PC) + node sigB_PC = cat(UInt<1>("h01"), T_430) + node T_432 = not(isSpecialB_PC) + node T_433 = not(isZeroB_PC) + node T_434 = and(T_432, T_433) + node T_435 = not(sign_PC) + node T_436 = and(T_434, T_435) + node T_437 = not(isSpecialA_PC) + node T_438 = not(isSpecialB_PC) + node T_439 = and(T_437, T_438) + node T_440 = not(isZeroA_PC) + node T_441 = and(T_439, T_440) + node T_442 = not(isZeroB_PC) + node T_443 = and(T_441, T_442) + node normalCase_PC = mux(sqrtOp_PC, T_436, T_443) + node T_446 = add(exp_PC, UInt<2>("h02")) + node expP2_PC = tail(T_446, 1) + node T_448 = bits(exp_PC, 0, 0) + node T_449 = bits(expP2_PC, 13, 1) + node T_451 = cat(T_449, UInt<1>("h00")) + node T_452 = bits(exp_PC, 13, 1) + node T_454 = cat(T_452, UInt<1>("h01")) + node expP1_PC = mux(T_448, T_451, T_454) node roundingMode_near_even_PC = eq(roundingMode_PC, UInt<2>("h00")) node roundingMode_minMag_PC = eq(roundingMode_PC, UInt<2>("h01")) node roundingMode_min_PC = eq(roundingMode_PC, UInt<2>("h02")) node roundingMode_max_PC = eq(roundingMode_PC, UInt<2>("h03")) node roundMagUp_PC = mux(sign_PC, roundingMode_min_PC, roundingMode_max_PC) node overflowY_roundMagUp_PC = or(roundingMode_near_even_PC, roundMagUp_PC) - node T_500 = not(roundMagUp_PC) - node T_501 = not(roundingMode_near_even_PC) - node roundMagDown_PC = and(T_500, T_501) - node T_503 = not(normalCase_PC) - node valid_leaving_PC = or(T_503, cyc_E1) - node T_505 = and(valid_PC, valid_leaving_PC) - leaving_PC <= T_505 - node T_506 = not(valid_PC) - node T_507 = or(T_506, valid_leaving_PC) - ready_PC <= T_507 - node T_508 = not(sqrtOp_PC) - node T_509 = and(leaving_PC, T_508) - io.outValid_div <= T_509 - node T_510 = and(leaving_PC, sqrtOp_PC) - io.outValid_sqrt <= T_510 - node T_512 = neq(cycleNum_A, UInt<1>("h00")) - node T_513 = or(entering_PA_normalCase, T_512) - when T_513 : - node T_516 = mux(entering_PA_normalCase_div, UInt<2>("h03"), UInt<1>("h00")) - node T_519 = mux(entering_PA_normalCase_sqrt, UInt<3>("h06"), UInt<1>("h00")) - node T_520 = or(T_516, T_519) - node T_521 = not(entering_PA_normalCase) - node T_523 = subw(cycleNum_A, UInt<1>("h01")) - node T_525 = mux(T_521, T_523, UInt<1>("h00")) - node T_526 = or(T_520, T_525) - cycleNum_A <= T_526 + node T_462 = not(roundMagUp_PC) + node T_463 = not(roundingMode_near_even_PC) + node roundMagDown_PC = and(T_462, T_463) + node T_465 = not(normalCase_PC) + node valid_leaving_PC = or(T_465, cyc_E1) + node T_467 = and(valid_PC, valid_leaving_PC) + leaving_PC <= T_467 + node T_468 = not(valid_PC) + node T_469 = or(T_468, valid_leaving_PC) + ready_PC <= T_469 + node T_470 = not(sqrtOp_PC) + node T_471 = and(leaving_PC, T_470) + io.outValid_div <= T_471 + node T_472 = and(leaving_PC, sqrtOp_PC) + io.outValid_sqrt <= T_472 + node T_474 = neq(cycleNum_A, UInt<1>("h00")) + node T_475 = or(entering_PA_normalCase, T_474) + when T_475 : + node T_478 = mux(entering_PA_normalCase_div, UInt<2>("h03"), UInt<1>("h00")) + node T_481 = mux(entering_PA_normalCase_sqrt, UInt<3>("h06"), UInt<1>("h00")) + node T_482 = or(T_478, T_481) + node T_483 = not(entering_PA_normalCase) + node T_485 = sub(cycleNum_A, UInt<1>("h01")) + node T_486 = tail(T_485, 1) + node T_488 = mux(T_483, T_486, UInt<1>("h00")) + node T_489 = or(T_482, T_488) + cycleNum_A <= T_489 skip node cyc_A6_sqrt = eq(cycleNum_A, UInt<3>("h06")) node cyc_A5_sqrt = eq(cycleNum_A, UInt<3>("h05")) @@ -38433,566 +30461,575 @@ circuit Top : node cyc_A3 = eq(cycleNum_A, UInt<2>("h03")) node cyc_A2 = eq(cycleNum_A, UInt<2>("h02")) node cyc_A1 = eq(cycleNum_A, UInt<1>("h01")) - node T_540 = not(sqrtOp_PA) - node cyc_A3_div = and(cyc_A3, T_540) - node T_542 = not(sqrtOp_PA) - node cyc_A2_div = and(cyc_A2, T_542) - node T_544 = not(sqrtOp_PA) - node cyc_A1_div = and(cyc_A1, T_544) + node T_503 = not(sqrtOp_PA) + node cyc_A3_div = and(cyc_A3, T_503) + node T_505 = not(sqrtOp_PA) + node cyc_A2_div = and(cyc_A2, T_505) + node T_507 = not(sqrtOp_PA) + node cyc_A1_div = and(cyc_A1, T_507) node cyc_A3_sqrt = and(cyc_A3, sqrtOp_PA) node cyc_A2_sqrt = and(cyc_A2, sqrtOp_PA) node cyc_A1_sqrt = and(cyc_A1, sqrtOp_PA) - node T_550 = neq(cycleNum_B, UInt<1>("h00")) - node T_551 = or(cyc_A1, T_550) - when T_551 : - node T_554 = mux(sqrtOp_PA, UInt<4>("h0a"), UInt<3>("h06")) - node T_556 = subw(cycleNum_B, UInt<1>("h01")) - node T_557 = mux(cyc_A1, T_554, T_556) - cycleNum_B <= T_557 - skip - node T_559 = eq(cycleNum_B, UInt<4>("h0a")) - cyc_B10_sqrt <= T_559 - node T_561 = eq(cycleNum_B, UInt<4>("h09")) - cyc_B9_sqrt <= T_561 - node T_563 = eq(cycleNum_B, UInt<4>("h08")) - cyc_B8_sqrt <= T_563 - node T_565 = eq(cycleNum_B, UInt<3>("h07")) - cyc_B7_sqrt <= T_565 - node T_567 = eq(cycleNum_B, UInt<3>("h06")) - cyc_B6 <= T_567 - node T_569 = eq(cycleNum_B, UInt<3>("h05")) - cyc_B5 <= T_569 - node T_571 = eq(cycleNum_B, UInt<3>("h04")) - cyc_B4 <= T_571 - node T_573 = eq(cycleNum_B, UInt<2>("h03")) - cyc_B3 <= T_573 - node T_575 = eq(cycleNum_B, UInt<2>("h02")) - cyc_B2 <= T_575 - node T_577 = eq(cycleNum_B, UInt<1>("h01")) - cyc_B1 <= T_577 - node T_578 = and(cyc_B6, valid_PA) - node T_579 = not(sqrtOp_PA) - node T_580 = and(T_578, T_579) - cyc_B6_div <= T_580 - node T_581 = and(cyc_B5, valid_PA) - node T_582 = not(sqrtOp_PA) - node T_583 = and(T_581, T_582) - cyc_B5_div <= T_583 - node T_584 = and(cyc_B4, valid_PA) - node T_585 = not(sqrtOp_PA) - node T_586 = and(T_584, T_585) - cyc_B4_div <= T_586 - node T_587 = not(sqrtOp_PB) - node T_588 = and(cyc_B3, T_587) - cyc_B3_div <= T_588 - node T_589 = not(sqrtOp_PB) - node T_590 = and(cyc_B2, T_589) - cyc_B2_div <= T_590 - node T_591 = not(sqrtOp_PB) - node T_592 = and(cyc_B1, T_591) - cyc_B1_div <= T_592 - node T_593 = and(cyc_B6, valid_PB) - node T_594 = and(T_593, sqrtOp_PB) - cyc_B6_sqrt <= T_594 - node T_595 = and(cyc_B5, valid_PB) - node T_596 = and(T_595, sqrtOp_PB) - cyc_B5_sqrt <= T_596 - node T_597 = and(cyc_B4, valid_PB) - node T_598 = and(T_597, sqrtOp_PB) - cyc_B4_sqrt <= T_598 - node T_599 = and(cyc_B3, sqrtOp_PB) - cyc_B3_sqrt <= T_599 - node T_600 = and(cyc_B2, sqrtOp_PB) - cyc_B2_sqrt <= T_600 - node T_601 = and(cyc_B1, sqrtOp_PB) - cyc_B1_sqrt <= T_601 - node T_603 = neq(cycleNum_C, UInt<1>("h00")) - node T_604 = or(cyc_B1, T_603) - when T_604 : - node T_607 = mux(sqrtOp_PB, UInt<3>("h06"), UInt<3>("h05")) - node T_609 = subw(cycleNum_C, UInt<1>("h01")) - node T_610 = mux(cyc_B1, T_607, T_609) - cycleNum_C <= T_610 + node T_513 = neq(cycleNum_B, UInt<1>("h00")) + node T_514 = or(cyc_A1, T_513) + when T_514 : + node T_517 = mux(sqrtOp_PA, UInt<4>("h0a"), UInt<3>("h06")) + node T_519 = sub(cycleNum_B, UInt<1>("h01")) + node T_520 = tail(T_519, 1) + node T_521 = mux(cyc_A1, T_517, T_520) + cycleNum_B <= T_521 + skip + node T_523 = eq(cycleNum_B, UInt<4>("h0a")) + cyc_B10_sqrt <= T_523 + node T_525 = eq(cycleNum_B, UInt<4>("h09")) + cyc_B9_sqrt <= T_525 + node T_527 = eq(cycleNum_B, UInt<4>("h08")) + cyc_B8_sqrt <= T_527 + node T_529 = eq(cycleNum_B, UInt<3>("h07")) + cyc_B7_sqrt <= T_529 + node T_531 = eq(cycleNum_B, UInt<3>("h06")) + cyc_B6 <= T_531 + node T_533 = eq(cycleNum_B, UInt<3>("h05")) + cyc_B5 <= T_533 + node T_535 = eq(cycleNum_B, UInt<3>("h04")) + cyc_B4 <= T_535 + node T_537 = eq(cycleNum_B, UInt<2>("h03")) + cyc_B3 <= T_537 + node T_539 = eq(cycleNum_B, UInt<2>("h02")) + cyc_B2 <= T_539 + node T_541 = eq(cycleNum_B, UInt<1>("h01")) + cyc_B1 <= T_541 + node T_542 = and(cyc_B6, valid_PA) + node T_543 = not(sqrtOp_PA) + node T_544 = and(T_542, T_543) + cyc_B6_div <= T_544 + node T_545 = and(cyc_B5, valid_PA) + node T_546 = not(sqrtOp_PA) + node T_547 = and(T_545, T_546) + cyc_B5_div <= T_547 + node T_548 = and(cyc_B4, valid_PA) + node T_549 = not(sqrtOp_PA) + node T_550 = and(T_548, T_549) + cyc_B4_div <= T_550 + node T_551 = not(sqrtOp_PB) + node T_552 = and(cyc_B3, T_551) + cyc_B3_div <= T_552 + node T_553 = not(sqrtOp_PB) + node T_554 = and(cyc_B2, T_553) + cyc_B2_div <= T_554 + node T_555 = not(sqrtOp_PB) + node T_556 = and(cyc_B1, T_555) + cyc_B1_div <= T_556 + node T_557 = and(cyc_B6, valid_PB) + node T_558 = and(T_557, sqrtOp_PB) + cyc_B6_sqrt <= T_558 + node T_559 = and(cyc_B5, valid_PB) + node T_560 = and(T_559, sqrtOp_PB) + cyc_B5_sqrt <= T_560 + node T_561 = and(cyc_B4, valid_PB) + node T_562 = and(T_561, sqrtOp_PB) + cyc_B4_sqrt <= T_562 + node T_563 = and(cyc_B3, sqrtOp_PB) + cyc_B3_sqrt <= T_563 + node T_564 = and(cyc_B2, sqrtOp_PB) + cyc_B2_sqrt <= T_564 + node T_565 = and(cyc_B1, sqrtOp_PB) + cyc_B1_sqrt <= T_565 + node T_567 = neq(cycleNum_C, UInt<1>("h00")) + node T_568 = or(cyc_B1, T_567) + when T_568 : + node T_571 = mux(sqrtOp_PB, UInt<3>("h06"), UInt<3>("h05")) + node T_573 = sub(cycleNum_C, UInt<1>("h01")) + node T_574 = tail(T_573, 1) + node T_575 = mux(cyc_B1, T_571, T_574) + cycleNum_C <= T_575 skip node cyc_C6_sqrt = eq(cycleNum_C, UInt<3>("h06")) - node T_614 = eq(cycleNum_C, UInt<3>("h05")) - cyc_C5 <= T_614 - node T_616 = eq(cycleNum_C, UInt<3>("h04")) - cyc_C4 <= T_616 - node T_618 = eq(cycleNum_C, UInt<2>("h03")) - valid_normalCase_leaving_PB <= T_618 - node T_620 = eq(cycleNum_C, UInt<2>("h02")) - cyc_C2 <= T_620 - node T_622 = eq(cycleNum_C, UInt<1>("h01")) - cyc_C1 <= T_622 - node T_623 = not(sqrtOp_PB) - node cyc_C5_div = and(cyc_C5, T_623) - node T_625 = not(sqrtOp_PB) - node cyc_C4_div = and(cyc_C4, T_625) - node T_627 = not(sqrtOp_PB) - node cyc_C3_div = and(valid_normalCase_leaving_PB, T_627) - node T_629 = not(sqrtOp_PC) - node cyc_C2_div = and(cyc_C2, T_629) - node T_631 = not(sqrtOp_PC) - node cyc_C1_div = and(cyc_C1, T_631) + node T_579 = eq(cycleNum_C, UInt<3>("h05")) + cyc_C5 <= T_579 + node T_581 = eq(cycleNum_C, UInt<3>("h04")) + cyc_C4 <= T_581 + node T_583 = eq(cycleNum_C, UInt<2>("h03")) + valid_normalCase_leaving_PB <= T_583 + node T_585 = eq(cycleNum_C, UInt<2>("h02")) + cyc_C2 <= T_585 + node T_587 = eq(cycleNum_C, UInt<1>("h01")) + cyc_C1 <= T_587 + node T_588 = not(sqrtOp_PB) + node cyc_C5_div = and(cyc_C5, T_588) + node T_590 = not(sqrtOp_PB) + node cyc_C4_div = and(cyc_C4, T_590) + node T_592 = not(sqrtOp_PB) + node cyc_C3_div = and(valid_normalCase_leaving_PB, T_592) + node T_594 = not(sqrtOp_PC) + node cyc_C2_div = and(cyc_C2, T_594) + node T_596 = not(sqrtOp_PC) + node cyc_C1_div = and(cyc_C1, T_596) node cyc_C5_sqrt = and(cyc_C5, sqrtOp_PB) node cyc_C4_sqrt = and(cyc_C4, sqrtOp_PB) node cyc_C3_sqrt = and(valid_normalCase_leaving_PB, sqrtOp_PB) node cyc_C2_sqrt = and(cyc_C2, sqrtOp_PC) node cyc_C1_sqrt = and(cyc_C1, sqrtOp_PC) - node T_639 = neq(cycleNum_E, UInt<1>("h00")) - node T_640 = or(cyc_C1, T_639) - when T_640 : - node T_643 = subw(cycleNum_E, UInt<1>("h01")) - node T_644 = mux(cyc_C1, UInt<3>("h04"), T_643) - cycleNum_E <= T_644 - skip - node T_646 = eq(cycleNum_E, UInt<3>("h04")) - cyc_E4 <= T_646 - node T_648 = eq(cycleNum_E, UInt<2>("h03")) - cyc_E3 <= T_648 - node T_650 = eq(cycleNum_E, UInt<2>("h02")) - cyc_E2 <= T_650 - node T_652 = eq(cycleNum_E, UInt<1>("h01")) - cyc_E1 <= T_652 - node T_653 = not(sqrtOp_PC) - node cyc_E4_div = and(cyc_E4, T_653) - node T_655 = not(sqrtOp_PC) - node cyc_E3_div = and(cyc_E3, T_655) - node T_657 = not(sqrtOp_PC) - node cyc_E2_div = and(cyc_E2, T_657) - node T_659 = not(sqrtOp_PC) - node cyc_E1_div = and(cyc_E1, T_659) + node T_604 = neq(cycleNum_E, UInt<1>("h00")) + node T_605 = or(cyc_C1, T_604) + when T_605 : + node T_608 = sub(cycleNum_E, UInt<1>("h01")) + node T_609 = tail(T_608, 1) + node T_610 = mux(cyc_C1, UInt<3>("h04"), T_609) + cycleNum_E <= T_610 + skip + node T_612 = eq(cycleNum_E, UInt<3>("h04")) + cyc_E4 <= T_612 + node T_614 = eq(cycleNum_E, UInt<2>("h03")) + cyc_E3 <= T_614 + node T_616 = eq(cycleNum_E, UInt<2>("h02")) + cyc_E2 <= T_616 + node T_618 = eq(cycleNum_E, UInt<1>("h01")) + cyc_E1 <= T_618 + node T_619 = not(sqrtOp_PC) + node cyc_E4_div = and(cyc_E4, T_619) + node T_621 = not(sqrtOp_PC) + node cyc_E3_div = and(cyc_E3, T_621) + node T_623 = not(sqrtOp_PC) + node cyc_E2_div = and(cyc_E2, T_623) + node T_625 = not(sqrtOp_PC) + node cyc_E1_div = and(cyc_E1, T_625) node cyc_E4_sqrt = and(cyc_E4, sqrtOp_PC) node cyc_E3_sqrt = and(cyc_E3, sqrtOp_PC) node cyc_E2_sqrt = and(cyc_E2, sqrtOp_PC) node cyc_E1_sqrt = and(cyc_E1, sqrtOp_PC) node zFractB_A4_div = mux(entering_PA_normalCase_div, fractB_S, UInt<1>("h00")) - node T_667 = bits(fractB_S, 51, 49) - node T_669 = eq(T_667, UInt<1>("h00")) - node zLinPiece_0_A4_div = and(entering_PA_normalCase_div, T_669) - node T_671 = bits(fractB_S, 51, 49) - node T_673 = eq(T_671, UInt<1>("h01")) - node zLinPiece_1_A4_div = and(entering_PA_normalCase_div, T_673) - node T_675 = bits(fractB_S, 51, 49) - node T_677 = eq(T_675, UInt<2>("h02")) - node zLinPiece_2_A4_div = and(entering_PA_normalCase_div, T_677) - node T_679 = bits(fractB_S, 51, 49) - node T_681 = eq(T_679, UInt<2>("h03")) - node zLinPiece_3_A4_div = and(entering_PA_normalCase_div, T_681) - node T_683 = bits(fractB_S, 51, 49) - node T_685 = eq(T_683, UInt<3>("h04")) - node zLinPiece_4_A4_div = and(entering_PA_normalCase_div, T_685) - node T_687 = bits(fractB_S, 51, 49) - node T_689 = eq(T_687, UInt<3>("h05")) - node zLinPiece_5_A4_div = and(entering_PA_normalCase_div, T_689) - node T_691 = bits(fractB_S, 51, 49) - node T_693 = eq(T_691, UInt<3>("h06")) - node zLinPiece_6_A4_div = and(entering_PA_normalCase_div, T_693) - node T_695 = bits(fractB_S, 51, 49) - node T_697 = eq(T_695, UInt<3>("h07")) - node zLinPiece_7_A4_div = and(entering_PA_normalCase_div, T_697) - node T_701 = mux(zLinPiece_0_A4_div, UInt<9>("h01c7"), UInt<1>("h00")) - node T_704 = mux(zLinPiece_1_A4_div, UInt<9>("h016c"), UInt<1>("h00")) - node T_705 = or(T_701, T_704) - node T_708 = mux(zLinPiece_2_A4_div, UInt<9>("h012a"), UInt<1>("h00")) - node T_709 = or(T_705, T_708) - node T_712 = mux(zLinPiece_3_A4_div, UInt<9>("h0f8"), UInt<1>("h00")) - node T_713 = or(T_709, T_712) - node T_716 = mux(zLinPiece_4_A4_div, UInt<9>("h0d2"), UInt<1>("h00")) - node T_717 = or(T_713, T_716) - node T_720 = mux(zLinPiece_5_A4_div, UInt<9>("h0b4"), UInt<1>("h00")) - node T_721 = or(T_717, T_720) - node T_724 = mux(zLinPiece_6_A4_div, UInt<9>("h09c"), UInt<1>("h00")) - node T_725 = or(T_721, T_724) - node T_728 = mux(zLinPiece_7_A4_div, UInt<9>("h089"), UInt<1>("h00")) - node zK1_A4_div = or(T_725, T_728) - node T_731 = not(UInt<12>("h0fe3")) - node T_733 = mux(zLinPiece_0_A4_div, T_731, UInt<1>("h00")) - node T_735 = not(UInt<12>("h0c5d")) - node T_737 = mux(zLinPiece_1_A4_div, T_735, UInt<1>("h00")) - node T_738 = or(T_733, T_737) - node T_740 = not(UInt<12>("h098a")) - node T_742 = mux(zLinPiece_2_A4_div, T_740, UInt<1>("h00")) - node T_743 = or(T_738, T_742) - node T_745 = not(UInt<12>("h0739")) - node T_747 = mux(zLinPiece_3_A4_div, T_745, UInt<1>("h00")) - node T_748 = or(T_743, T_747) - node T_750 = not(UInt<12>("h054b")) - node T_752 = mux(zLinPiece_4_A4_div, T_750, UInt<1>("h00")) - node T_753 = or(T_748, T_752) - node T_755 = not(UInt<12>("h03a9")) - node T_757 = mux(zLinPiece_5_A4_div, T_755, UInt<1>("h00")) - node T_758 = or(T_753, T_757) - node T_760 = not(UInt<12>("h0242")) - node T_762 = mux(zLinPiece_6_A4_div, T_760, UInt<1>("h00")) - node T_763 = or(T_758, T_762) - node T_765 = not(UInt<12>("h010b")) - node T_767 = mux(zLinPiece_7_A4_div, T_765, UInt<1>("h00")) - node zComplFractK0_A4_div = or(T_763, T_767) + node T_633 = bits(fractB_S, 51, 49) + node T_635 = eq(T_633, UInt<1>("h00")) + node zLinPiece_0_A4_div = and(entering_PA_normalCase_div, T_635) + node T_637 = bits(fractB_S, 51, 49) + node T_639 = eq(T_637, UInt<1>("h01")) + node zLinPiece_1_A4_div = and(entering_PA_normalCase_div, T_639) + node T_641 = bits(fractB_S, 51, 49) + node T_643 = eq(T_641, UInt<2>("h02")) + node zLinPiece_2_A4_div = and(entering_PA_normalCase_div, T_643) + node T_645 = bits(fractB_S, 51, 49) + node T_647 = eq(T_645, UInt<2>("h03")) + node zLinPiece_3_A4_div = and(entering_PA_normalCase_div, T_647) + node T_649 = bits(fractB_S, 51, 49) + node T_651 = eq(T_649, UInt<3>("h04")) + node zLinPiece_4_A4_div = and(entering_PA_normalCase_div, T_651) + node T_653 = bits(fractB_S, 51, 49) + node T_655 = eq(T_653, UInt<3>("h05")) + node zLinPiece_5_A4_div = and(entering_PA_normalCase_div, T_655) + node T_657 = bits(fractB_S, 51, 49) + node T_659 = eq(T_657, UInt<3>("h06")) + node zLinPiece_6_A4_div = and(entering_PA_normalCase_div, T_659) + node T_661 = bits(fractB_S, 51, 49) + node T_663 = eq(T_661, UInt<3>("h07")) + node zLinPiece_7_A4_div = and(entering_PA_normalCase_div, T_663) + node T_667 = mux(zLinPiece_0_A4_div, UInt<9>("h01c7"), UInt<1>("h00")) + node T_670 = mux(zLinPiece_1_A4_div, UInt<9>("h016c"), UInt<1>("h00")) + node T_671 = or(T_667, T_670) + node T_674 = mux(zLinPiece_2_A4_div, UInt<9>("h012a"), UInt<1>("h00")) + node T_675 = or(T_671, T_674) + node T_678 = mux(zLinPiece_3_A4_div, UInt<9>("h0f8"), UInt<1>("h00")) + node T_679 = or(T_675, T_678) + node T_682 = mux(zLinPiece_4_A4_div, UInt<9>("h0d2"), UInt<1>("h00")) + node T_683 = or(T_679, T_682) + node T_686 = mux(zLinPiece_5_A4_div, UInt<9>("h0b4"), UInt<1>("h00")) + node T_687 = or(T_683, T_686) + node T_690 = mux(zLinPiece_6_A4_div, UInt<9>("h09c"), UInt<1>("h00")) + node T_691 = or(T_687, T_690) + node T_694 = mux(zLinPiece_7_A4_div, UInt<9>("h089"), UInt<1>("h00")) + node zK1_A4_div = or(T_691, T_694) + node T_697 = not(UInt<12>("h0fe3")) + node T_699 = mux(zLinPiece_0_A4_div, T_697, UInt<1>("h00")) + node T_701 = not(UInt<12>("h0c5d")) + node T_703 = mux(zLinPiece_1_A4_div, T_701, UInt<1>("h00")) + node T_704 = or(T_699, T_703) + node T_706 = not(UInt<12>("h098a")) + node T_708 = mux(zLinPiece_2_A4_div, T_706, UInt<1>("h00")) + node T_709 = or(T_704, T_708) + node T_711 = not(UInt<12>("h0739")) + node T_713 = mux(zLinPiece_3_A4_div, T_711, UInt<1>("h00")) + node T_714 = or(T_709, T_713) + node T_716 = not(UInt<12>("h054b")) + node T_718 = mux(zLinPiece_4_A4_div, T_716, UInt<1>("h00")) + node T_719 = or(T_714, T_718) + node T_721 = not(UInt<12>("h03a9")) + node T_723 = mux(zLinPiece_5_A4_div, T_721, UInt<1>("h00")) + node T_724 = or(T_719, T_723) + node T_726 = not(UInt<12>("h0242")) + node T_728 = mux(zLinPiece_6_A4_div, T_726, UInt<1>("h00")) + node T_729 = or(T_724, T_728) + node T_731 = not(UInt<12>("h010b")) + node T_733 = mux(zLinPiece_7_A4_div, T_731, UInt<1>("h00")) + node zComplFractK0_A4_div = or(T_729, T_733) node zFractB_A7_sqrt = mux(entering_PA_normalCase_sqrt, fractB_S, UInt<1>("h00")) - node T_771 = bit(expB_S, 0) - node T_772 = not(T_771) - node T_773 = and(entering_PA_normalCase_sqrt, T_772) - node T_774 = bit(fractB_S, 51) - node T_775 = not(T_774) - node zQuadPiece_0_A7_sqrt = and(T_773, T_775) - node T_777 = bit(expB_S, 0) - node T_778 = not(T_777) - node T_779 = and(entering_PA_normalCase_sqrt, T_778) - node T_780 = bit(fractB_S, 51) - node zQuadPiece_1_A7_sqrt = and(T_779, T_780) - node T_782 = bit(expB_S, 0) - node T_783 = and(entering_PA_normalCase_sqrt, T_782) - node T_784 = bit(fractB_S, 51) - node T_785 = not(T_784) - node zQuadPiece_2_A7_sqrt = and(T_783, T_785) - node T_787 = bit(expB_S, 0) - node T_788 = and(entering_PA_normalCase_sqrt, T_787) - node T_789 = bit(fractB_S, 51) - node zQuadPiece_3_A7_sqrt = and(T_788, T_789) - node T_793 = mux(zQuadPiece_0_A7_sqrt, UInt<9>("h01c8"), UInt<1>("h00")) - node T_796 = mux(zQuadPiece_1_A7_sqrt, UInt<9>("h0c1"), UInt<1>("h00")) - node T_797 = or(T_793, T_796) - node T_800 = mux(zQuadPiece_2_A7_sqrt, UInt<9>("h0143"), UInt<1>("h00")) - node T_801 = or(T_797, T_800) - node T_804 = mux(zQuadPiece_3_A7_sqrt, UInt<9>("h089"), UInt<1>("h00")) - node zK2_A7_sqrt = or(T_801, T_804) - node T_807 = not(UInt<10>("h03d0")) - node T_809 = mux(zQuadPiece_0_A7_sqrt, T_807, UInt<1>("h00")) - node T_811 = not(UInt<10>("h0220")) - node T_813 = mux(zQuadPiece_1_A7_sqrt, T_811, UInt<1>("h00")) - node T_814 = or(T_809, T_813) - node T_816 = not(UInt<10>("h02b2")) - node T_818 = mux(zQuadPiece_2_A7_sqrt, T_816, UInt<1>("h00")) + node T_737 = bits(expB_S, 0, 0) + node T_738 = not(T_737) + node T_739 = and(entering_PA_normalCase_sqrt, T_738) + node T_740 = bits(fractB_S, 51, 51) + node T_741 = not(T_740) + node zQuadPiece_0_A7_sqrt = and(T_739, T_741) + node T_743 = bits(expB_S, 0, 0) + node T_744 = not(T_743) + node T_745 = and(entering_PA_normalCase_sqrt, T_744) + node T_746 = bits(fractB_S, 51, 51) + node zQuadPiece_1_A7_sqrt = and(T_745, T_746) + node T_748 = bits(expB_S, 0, 0) + node T_749 = and(entering_PA_normalCase_sqrt, T_748) + node T_750 = bits(fractB_S, 51, 51) + node T_751 = not(T_750) + node zQuadPiece_2_A7_sqrt = and(T_749, T_751) + node T_753 = bits(expB_S, 0, 0) + node T_754 = and(entering_PA_normalCase_sqrt, T_753) + node T_755 = bits(fractB_S, 51, 51) + node zQuadPiece_3_A7_sqrt = and(T_754, T_755) + node T_759 = mux(zQuadPiece_0_A7_sqrt, UInt<9>("h01c8"), UInt<1>("h00")) + node T_762 = mux(zQuadPiece_1_A7_sqrt, UInt<9>("h0c1"), UInt<1>("h00")) + node T_763 = or(T_759, T_762) + node T_766 = mux(zQuadPiece_2_A7_sqrt, UInt<9>("h0143"), UInt<1>("h00")) + node T_767 = or(T_763, T_766) + node T_770 = mux(zQuadPiece_3_A7_sqrt, UInt<9>("h089"), UInt<1>("h00")) + node zK2_A7_sqrt = or(T_767, T_770) + node T_773 = not(UInt<10>("h03d0")) + node T_775 = mux(zQuadPiece_0_A7_sqrt, T_773, UInt<1>("h00")) + node T_777 = not(UInt<10>("h0220")) + node T_779 = mux(zQuadPiece_1_A7_sqrt, T_777, UInt<1>("h00")) + node T_780 = or(T_775, T_779) + node T_782 = not(UInt<10>("h02b2")) + node T_784 = mux(zQuadPiece_2_A7_sqrt, T_782, UInt<1>("h00")) + node T_785 = or(T_780, T_784) + node T_787 = not(UInt<10>("h0181")) + node T_789 = mux(zQuadPiece_3_A7_sqrt, T_787, UInt<1>("h00")) + node zComplK1_A7_sqrt = or(T_785, T_789) + node T_791 = bits(exp_PA, 0, 0) + node T_792 = not(T_791) + node T_793 = and(cyc_A6_sqrt, T_792) + node T_794 = bits(sigB_PA, 51, 51) + node T_795 = not(T_794) + node zQuadPiece_0_A6_sqrt = and(T_793, T_795) + node T_797 = bits(exp_PA, 0, 0) + node T_798 = not(T_797) + node T_799 = and(cyc_A6_sqrt, T_798) + node T_800 = bits(sigB_PA, 51, 51) + node zQuadPiece_1_A6_sqrt = and(T_799, T_800) + node T_802 = bits(exp_PA, 0, 0) + node T_803 = and(cyc_A6_sqrt, T_802) + node T_804 = bits(sigB_PA, 51, 51) + node T_805 = not(T_804) + node zQuadPiece_2_A6_sqrt = and(T_803, T_805) + node T_807 = bits(exp_PA, 0, 0) + node T_808 = and(cyc_A6_sqrt, T_807) + node T_809 = bits(sigB_PA, 51, 51) + node zQuadPiece_3_A6_sqrt = and(T_808, T_809) + node T_812 = not(UInt<13>("h01fe5")) + node T_814 = mux(zQuadPiece_0_A6_sqrt, T_812, UInt<1>("h00")) + node T_816 = not(UInt<13>("h01435")) + node T_818 = mux(zQuadPiece_1_A6_sqrt, T_816, UInt<1>("h00")) node T_819 = or(T_814, T_818) - node T_821 = not(UInt<10>("h0181")) - node T_823 = mux(zQuadPiece_3_A7_sqrt, T_821, UInt<1>("h00")) - node zComplK1_A7_sqrt = or(T_819, T_823) - node T_825 = bit(exp_PA, 0) - node T_826 = not(T_825) - node T_827 = and(cyc_A6_sqrt, T_826) - node T_828 = bit(sigB_PA, 51) - node T_829 = not(T_828) - node zQuadPiece_0_A6_sqrt = and(T_827, T_829) - node T_831 = bit(exp_PA, 0) - node T_832 = not(T_831) - node T_833 = and(cyc_A6_sqrt, T_832) - node T_834 = bit(sigB_PA, 51) - node zQuadPiece_1_A6_sqrt = and(T_833, T_834) - node T_836 = bit(exp_PA, 0) - node T_837 = and(cyc_A6_sqrt, T_836) - node T_838 = bit(sigB_PA, 51) - node T_839 = not(T_838) - node zQuadPiece_2_A6_sqrt = and(T_837, T_839) - node T_841 = bit(exp_PA, 0) - node T_842 = and(cyc_A6_sqrt, T_841) - node T_843 = bit(sigB_PA, 51) - node zQuadPiece_3_A6_sqrt = and(T_842, T_843) - node T_846 = not(UInt<13>("h01fe5")) - node T_848 = mux(zQuadPiece_0_A6_sqrt, T_846, UInt<1>("h00")) - node T_850 = not(UInt<13>("h01435")) - node T_852 = mux(zQuadPiece_1_A6_sqrt, T_850, UInt<1>("h00")) - node T_853 = or(T_848, T_852) - node T_855 = not(UInt<13>("h0d2c")) - node T_857 = mux(zQuadPiece_2_A6_sqrt, T_855, UInt<1>("h00")) - node T_858 = or(T_853, T_857) - node T_860 = not(UInt<13>("h04e8")) - node T_862 = mux(zQuadPiece_3_A6_sqrt, T_860, UInt<1>("h00")) - node zComplFractK0_A6_sqrt = or(T_858, T_862) - node T_864 = bits(zFractB_A4_div, 48, 40) - node T_865 = or(T_864, zK2_A7_sqrt) - node T_866 = not(cyc_S) - node T_868 = mux(T_866, nextMulAdd9A_A, UInt<1>("h00")) - node mulAdd9A_A = or(T_865, T_868) - node T_870 = bits(zFractB_A7_sqrt, 50, 42) - node T_871 = or(zK1_A4_div, T_870) - node T_872 = not(cyc_S) - node T_874 = mux(T_872, nextMulAdd9B_A, UInt<1>("h00")) - node mulAdd9B_A = or(T_871, T_874) - node T_876 = shl(zComplK1_A7_sqrt, 10) - node T_878 = subw(UInt<6>("h00"), cyc_A6_sqrt) - node T_879 = cat(zComplFractK0_A6_sqrt, T_878) - node T_880 = cat(cyc_A6_sqrt, T_879) - node T_881 = or(T_876, T_880) - node T_883 = subw(UInt<8>("h00"), entering_PA_normalCase_div) - node T_884 = cat(zComplFractK0_A4_div, T_883) - node T_885 = cat(entering_PA_normalCase_div, T_884) - node T_886 = or(T_881, T_885) - node T_888 = shl(fractR0_A, 10) - node T_889 = addw(UInt<20>("h040000"), T_888) - node T_891 = mux(cyc_A5_sqrt, T_889, UInt<1>("h00")) - node T_892 = or(T_886, T_891) - node T_893 = bit(hiSqrR0_A_sqrt, 9) - node T_894 = not(T_893) - node T_895 = and(cyc_A4_sqrt, T_894) - node T_898 = mux(T_895, UInt<11>("h0400"), UInt<1>("h00")) - node T_899 = or(T_892, T_898) - node T_900 = bit(hiSqrR0_A_sqrt, 9) - node T_901 = and(cyc_A4_sqrt, T_900) - node T_902 = or(T_901, cyc_A3_div) - node T_903 = bits(sigB_PA, 46, 26) - node T_905 = addw(T_903, UInt<11>("h0400")) - node T_907 = mux(T_902, T_905, UInt<1>("h00")) - node T_908 = or(T_899, T_907) - node T_909 = or(cyc_A3_sqrt, cyc_A2) - node T_911 = mux(T_909, partNegSigma0_A, UInt<1>("h00")) - node T_912 = or(T_908, T_911) - node T_913 = shl(fractR0_A, 16) - node T_915 = mux(cyc_A1_sqrt, T_913, UInt<1>("h00")) - node T_916 = or(T_912, T_915) - node T_917 = shl(fractR0_A, 15) - node T_919 = mux(cyc_A1_div, T_917, UInt<1>("h00")) - node mulAdd9C_A = or(T_916, T_919) - node T_921 = mul(mulAdd9A_A, mulAdd9B_A) - node T_923 = bits(mulAdd9C_A, 17, 0) - node T_924 = cat(UInt<1>("h00"), T_923) - node loMulAdd9Out_A = addw(T_921, T_924) - node T_926 = bit(loMulAdd9Out_A, 18) - node T_927 = bits(mulAdd9C_A, 24, 18) - node T_929 = addw(T_927, UInt<1>("h01")) - node T_930 = bits(mulAdd9C_A, 24, 18) - node T_931 = mux(T_926, T_929, T_930) - node T_932 = bits(loMulAdd9Out_A, 17, 0) - node mulAdd9Out_A = cat(T_931, T_932) - node T_934 = bit(mulAdd9Out_A, 19) - node T_935 = and(cyc_A6_sqrt, T_934) - node T_936 = not(mulAdd9Out_A) - node T_937 = shr(T_936, 10) - node T_939 = mux(T_935, T_937, UInt<1>("h00")) - node zFractR0_A6_sqrt = bits(T_939, 8, 0) - node T_941 = bit(exp_PA, 0) - node T_942 = shl(mulAdd9Out_A, 1) - node sqrR0_A5_sqrt = mux(T_941, T_942, mulAdd9Out_A) - node T_944 = bit(mulAdd9Out_A, 20) - node T_945 = and(entering_PA_normalCase_div, T_944) - node T_946 = not(mulAdd9Out_A) - node T_947 = shr(T_946, 11) - node T_949 = mux(T_945, T_947, UInt<1>("h00")) - node zFractR0_A4_div = bits(T_949, 8, 0) - node T_951 = bit(mulAdd9Out_A, 11) - node T_952 = and(cyc_A2, T_951) - node T_953 = not(mulAdd9Out_A) - node T_954 = shr(T_953, 2) - node T_956 = mux(T_952, T_954, UInt<1>("h00")) - node zSigma0_A2 = bits(T_956, 8, 0) - node T_958 = shr(mulAdd9Out_A, 10) - node T_959 = shr(mulAdd9Out_A, 9) - node T_960 = mux(sqrtOp_PA, T_958, T_959) - node fractR1_A1 = bits(T_960, 14, 0) + node T_821 = not(UInt<13>("h0d2c")) + node T_823 = mux(zQuadPiece_2_A6_sqrt, T_821, UInt<1>("h00")) + node T_824 = or(T_819, T_823) + node T_826 = not(UInt<13>("h04e8")) + node T_828 = mux(zQuadPiece_3_A6_sqrt, T_826, UInt<1>("h00")) + node zComplFractK0_A6_sqrt = or(T_824, T_828) + node T_830 = bits(zFractB_A4_div, 48, 40) + node T_831 = or(T_830, zK2_A7_sqrt) + node T_832 = not(cyc_S) + node T_834 = mux(T_832, nextMulAdd9A_A, UInt<1>("h00")) + node mulAdd9A_A = or(T_831, T_834) + node T_836 = bits(zFractB_A7_sqrt, 50, 42) + node T_837 = or(zK1_A4_div, T_836) + node T_838 = not(cyc_S) + node T_840 = mux(T_838, nextMulAdd9B_A, UInt<1>("h00")) + node mulAdd9B_A = or(T_837, T_840) + node T_842 = shl(zComplK1_A7_sqrt, 10) + node T_844 = sub(UInt<6>("h00"), cyc_A6_sqrt) + node T_845 = tail(T_844, 1) + node T_846 = cat(zComplFractK0_A6_sqrt, T_845) + node T_847 = cat(cyc_A6_sqrt, T_846) + node T_848 = or(T_842, T_847) + node T_850 = sub(UInt<8>("h00"), entering_PA_normalCase_div) + node T_851 = tail(T_850, 1) + node T_852 = cat(zComplFractK0_A4_div, T_851) + node T_853 = cat(entering_PA_normalCase_div, T_852) + node T_854 = or(T_848, T_853) + node T_856 = shl(fractR0_A, 10) + node T_857 = add(UInt<20>("h040000"), T_856) + node T_858 = tail(T_857, 1) + node T_860 = mux(cyc_A5_sqrt, T_858, UInt<1>("h00")) + node T_861 = or(T_854, T_860) + node T_862 = bits(hiSqrR0_A_sqrt, 9, 9) + node T_863 = not(T_862) + node T_864 = and(cyc_A4_sqrt, T_863) + node T_867 = mux(T_864, UInt<11>("h0400"), UInt<1>("h00")) + node T_868 = or(T_861, T_867) + node T_869 = bits(hiSqrR0_A_sqrt, 9, 9) + node T_870 = and(cyc_A4_sqrt, T_869) + node T_871 = or(T_870, cyc_A3_div) + node T_872 = bits(sigB_PA, 46, 26) + node T_874 = add(T_872, UInt<11>("h0400")) + node T_875 = tail(T_874, 1) + node T_877 = mux(T_871, T_875, UInt<1>("h00")) + node T_878 = or(T_868, T_877) + node T_879 = or(cyc_A3_sqrt, cyc_A2) + node T_881 = mux(T_879, partNegSigma0_A, UInt<1>("h00")) + node T_882 = or(T_878, T_881) + node T_883 = shl(fractR0_A, 16) + node T_885 = mux(cyc_A1_sqrt, T_883, UInt<1>("h00")) + node T_886 = or(T_882, T_885) + node T_887 = shl(fractR0_A, 15) + node T_889 = mux(cyc_A1_div, T_887, UInt<1>("h00")) + node mulAdd9C_A = or(T_886, T_889) + node T_891 = mul(mulAdd9A_A, mulAdd9B_A) + node T_893 = bits(mulAdd9C_A, 17, 0) + node T_894 = cat(UInt<1>("h00"), T_893) + node T_895 = add(T_891, T_894) + node loMulAdd9Out_A = tail(T_895, 1) + node T_897 = bits(loMulAdd9Out_A, 18, 18) + node T_898 = bits(mulAdd9C_A, 24, 18) + node T_900 = add(T_898, UInt<1>("h01")) + node T_901 = tail(T_900, 1) + node T_902 = bits(mulAdd9C_A, 24, 18) + node T_903 = mux(T_897, T_901, T_902) + node T_904 = bits(loMulAdd9Out_A, 17, 0) + node mulAdd9Out_A = cat(T_903, T_904) + node T_906 = bits(mulAdd9Out_A, 19, 19) + node T_907 = and(cyc_A6_sqrt, T_906) + node T_908 = not(mulAdd9Out_A) + node T_909 = shr(T_908, 10) + node T_911 = mux(T_907, T_909, UInt<1>("h00")) + node zFractR0_A6_sqrt = bits(T_911, 8, 0) + node T_913 = bits(exp_PA, 0, 0) + node T_914 = shl(mulAdd9Out_A, 1) + node sqrR0_A5_sqrt = mux(T_913, T_914, mulAdd9Out_A) + node T_916 = bits(mulAdd9Out_A, 20, 20) + node T_917 = and(entering_PA_normalCase_div, T_916) + node T_918 = not(mulAdd9Out_A) + node T_919 = shr(T_918, 11) + node T_921 = mux(T_917, T_919, UInt<1>("h00")) + node zFractR0_A4_div = bits(T_921, 8, 0) + node T_923 = bits(mulAdd9Out_A, 11, 11) + node T_924 = and(cyc_A2, T_923) + node T_925 = not(mulAdd9Out_A) + node T_926 = shr(T_925, 2) + node T_928 = mux(T_924, T_926, UInt<1>("h00")) + node zSigma0_A2 = bits(T_928, 8, 0) + node T_930 = shr(mulAdd9Out_A, 10) + node T_931 = shr(mulAdd9Out_A, 9) + node T_932 = mux(sqrtOp_PA, T_930, T_931) + node fractR1_A1 = bits(T_932, 14, 0) node r1_A1 = cat(UInt<1>("h01"), fractR1_A1) - node T_964 = bit(exp_PA, 0) - node T_965 = shl(r1_A1, 1) - node ER1_A1_sqrt = mux(T_964, T_965, r1_A1) - node T_967 = or(cyc_A6_sqrt, entering_PA_normalCase_div) - when T_967 : - node T_968 = or(zFractR0_A6_sqrt, zFractR0_A4_div) - fractR0_A <= T_968 + node T_936 = bits(exp_PA, 0, 0) + node T_937 = shl(r1_A1, 1) + node ER1_A1_sqrt = mux(T_936, T_937, r1_A1) + node T_939 = or(cyc_A6_sqrt, entering_PA_normalCase_div) + when T_939 : + node T_940 = or(zFractR0_A6_sqrt, zFractR0_A4_div) + fractR0_A <= T_940 skip when cyc_A5_sqrt : - node T_969 = shr(sqrR0_A5_sqrt, 10) - hiSqrR0_A_sqrt <= T_969 - skip - node T_970 = or(cyc_A4_sqrt, cyc_A3) - when T_970 : - node T_971 = shr(mulAdd9Out_A, 9) - node T_972 = mux(cyc_A4_sqrt, mulAdd9Out_A, T_971) - node T_973 = bits(T_972, 20, 0) - partNegSigma0_A <= T_973 - skip - node T_974 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) - node T_975 = or(T_974, cyc_A5_sqrt) - node T_976 = or(T_975, cyc_A4) - node T_977 = or(T_976, cyc_A3) - node T_978 = or(T_977, cyc_A2) - when T_978 : - node T_979 = not(mulAdd9Out_A) - node T_980 = shr(T_979, 11) - node T_982 = mux(entering_PA_normalCase_sqrt, T_980, UInt<1>("h00")) - node T_983 = or(T_982, zFractR0_A6_sqrt) - node T_984 = bits(sigB_PA, 43, 35) - node T_986 = mux(cyc_A4_sqrt, T_984, UInt<1>("h00")) - node T_987 = or(T_983, T_986) - node T_988 = bits(zFractB_A4_div, 43, 35) - node T_989 = or(T_987, T_988) - node T_990 = or(cyc_A5_sqrt, cyc_A3) - node T_991 = bits(sigB_PA, 52, 44) - node T_993 = mux(T_990, T_991, UInt<1>("h00")) - node T_994 = or(T_989, T_993) - node T_995 = or(T_994, zSigma0_A2) - nextMulAdd9A_A <= T_995 - skip - node T_996 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) - node T_997 = or(T_996, cyc_A5_sqrt) - node T_998 = or(T_997, cyc_A4) - node T_999 = or(T_998, cyc_A2) - when T_999 : - node T_1000 = bits(zFractB_A7_sqrt, 50, 42) - node T_1001 = or(T_1000, zFractR0_A6_sqrt) - node T_1002 = bits(sqrR0_A5_sqrt, 9, 1) - node T_1004 = mux(cyc_A5_sqrt, T_1002, UInt<1>("h00")) - node T_1005 = or(T_1001, T_1004) - node T_1006 = or(T_1005, zFractR0_A4_div) - node T_1007 = bits(hiSqrR0_A_sqrt, 8, 0) - node T_1009 = mux(cyc_A4_sqrt, T_1007, UInt<1>("h00")) - node T_1010 = or(T_1006, T_1009) - node T_1012 = bits(fractR0_A, 8, 1) - node T_1013 = cat(UInt<1>("h01"), T_1012) - node T_1015 = mux(cyc_A2, T_1013, UInt<1>("h00")) - node T_1016 = or(T_1010, T_1015) - nextMulAdd9B_A <= T_1016 + node T_941 = shr(sqrR0_A5_sqrt, 10) + hiSqrR0_A_sqrt <= T_941 + skip + node T_942 = or(cyc_A4_sqrt, cyc_A3) + when T_942 : + node T_943 = shr(mulAdd9Out_A, 9) + node T_944 = mux(cyc_A4_sqrt, mulAdd9Out_A, T_943) + node T_945 = bits(T_944, 20, 0) + partNegSigma0_A <= T_945 + skip + node T_946 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) + node T_947 = or(T_946, cyc_A5_sqrt) + node T_948 = or(T_947, cyc_A4) + node T_949 = or(T_948, cyc_A3) + node T_950 = or(T_949, cyc_A2) + when T_950 : + node T_951 = not(mulAdd9Out_A) + node T_952 = shr(T_951, 11) + node T_954 = mux(entering_PA_normalCase_sqrt, T_952, UInt<1>("h00")) + node T_955 = or(T_954, zFractR0_A6_sqrt) + node T_956 = bits(sigB_PA, 43, 35) + node T_958 = mux(cyc_A4_sqrt, T_956, UInt<1>("h00")) + node T_959 = or(T_955, T_958) + node T_960 = bits(zFractB_A4_div, 43, 35) + node T_961 = or(T_959, T_960) + node T_962 = or(cyc_A5_sqrt, cyc_A3) + node T_963 = bits(sigB_PA, 52, 44) + node T_965 = mux(T_962, T_963, UInt<1>("h00")) + node T_966 = or(T_961, T_965) + node T_967 = or(T_966, zSigma0_A2) + nextMulAdd9A_A <= T_967 + skip + node T_968 = or(entering_PA_normalCase_sqrt, cyc_A6_sqrt) + node T_969 = or(T_968, cyc_A5_sqrt) + node T_970 = or(T_969, cyc_A4) + node T_971 = or(T_970, cyc_A2) + when T_971 : + node T_972 = bits(zFractB_A7_sqrt, 50, 42) + node T_973 = or(T_972, zFractR0_A6_sqrt) + node T_974 = bits(sqrR0_A5_sqrt, 9, 1) + node T_976 = mux(cyc_A5_sqrt, T_974, UInt<1>("h00")) + node T_977 = or(T_973, T_976) + node T_978 = or(T_977, zFractR0_A4_div) + node T_979 = bits(hiSqrR0_A_sqrt, 8, 0) + node T_981 = mux(cyc_A4_sqrt, T_979, UInt<1>("h00")) + node T_982 = or(T_978, T_981) + node T_984 = bits(fractR0_A, 8, 1) + node T_985 = cat(UInt<1>("h01"), T_984) + node T_987 = mux(cyc_A2, T_985, UInt<1>("h00")) + node T_988 = or(T_982, T_987) + nextMulAdd9B_A <= T_988 skip when cyc_A1_sqrt : ER1_B_sqrt <= ER1_A1_sqrt skip - node T_1017 = or(cyc_A1, cyc_B7_sqrt) - node T_1018 = or(T_1017, cyc_B6_div) - node T_1019 = or(T_1018, cyc_B4) - node T_1020 = or(T_1019, cyc_B3) - node T_1021 = or(T_1020, cyc_C6_sqrt) - node T_1022 = or(T_1021, cyc_C4) - node T_1023 = or(T_1022, cyc_C1) - io.latchMulAddA_0 <= T_1023 - node T_1024 = shl(ER1_A1_sqrt, 36) - node T_1026 = mux(cyc_A1_sqrt, T_1024, UInt<1>("h00")) - node T_1027 = or(cyc_B7_sqrt, cyc_A1_div) - node T_1029 = mux(T_1027, sigB_PA, UInt<1>("h00")) - node T_1030 = or(T_1026, T_1029) - node T_1032 = mux(cyc_B6_div, sigA_PA, UInt<1>("h00")) - node T_1033 = or(T_1030, T_1032) - node T_1034 = bits(zSigma1_B4, 45, 12) - node T_1035 = or(T_1033, T_1034) - node T_1036 = or(cyc_B3, cyc_C6_sqrt) - node T_1037 = bits(sigXNU_B3_CX, 57, 12) - node T_1039 = mux(T_1036, T_1037, UInt<1>("h00")) - node T_1040 = or(T_1035, T_1039) - node T_1041 = bits(sigXN_C, 57, 25) - node T_1042 = shl(T_1041, 13) - node T_1044 = mux(cyc_C4_div, T_1042, UInt<1>("h00")) - node T_1045 = or(T_1040, T_1044) - node T_1046 = shl(u_C_sqrt, 15) - node T_1048 = mux(cyc_C4_sqrt, T_1046, UInt<1>("h00")) - node T_1049 = or(T_1045, T_1048) - node T_1051 = mux(cyc_C1_div, sigB_PC, UInt<1>("h00")) - node T_1052 = or(T_1049, T_1051) - node T_1053 = or(T_1052, zComplSigT_C1_sqrt) - io.mulAddA_0 <= T_1053 - node T_1054 = or(cyc_A1, cyc_B7_sqrt) - node T_1055 = or(T_1054, cyc_B6_sqrt) - node T_1056 = or(T_1055, cyc_B4) - node T_1057 = or(T_1056, cyc_C6_sqrt) - node T_1058 = or(T_1057, cyc_C4) - node T_1059 = or(T_1058, cyc_C1) - io.latchMulAddB_0 <= T_1059 - node T_1060 = shl(r1_A1, 36) - node T_1062 = mux(cyc_A1, T_1060, UInt<1>("h00")) - node T_1063 = shl(ESqrR1_B_sqrt, 19) - node T_1065 = mux(cyc_B7_sqrt, T_1063, UInt<1>("h00")) - node T_1066 = or(T_1062, T_1065) - node T_1067 = shl(ER1_B_sqrt, 36) - node T_1069 = mux(cyc_B6_sqrt, T_1067, UInt<1>("h00")) - node T_1070 = or(T_1066, T_1069) - node T_1071 = or(T_1070, zSigma1_B4) - node T_1072 = bits(sqrSigma1_C, 30, 1) - node T_1074 = mux(cyc_C6_sqrt, T_1072, UInt<1>("h00")) - node T_1075 = or(T_1071, T_1074) - node T_1077 = mux(cyc_C4, sqrSigma1_C, UInt<1>("h00")) - node T_1078 = or(T_1075, T_1077) - node T_1079 = or(T_1078, zComplSigT_C1) - io.mulAddB_0 <= T_1079 - node T_1080 = or(cyc_A4, cyc_A3_div) - node T_1081 = or(T_1080, cyc_A1_div) - node T_1082 = or(T_1081, cyc_B10_sqrt) - node T_1083 = or(T_1082, cyc_B9_sqrt) - node T_1084 = or(T_1083, cyc_B7_sqrt) - node T_1085 = or(T_1084, cyc_B6) - node T_1086 = or(T_1085, cyc_B5_sqrt) - node T_1087 = or(T_1086, cyc_B3_sqrt) - node T_1088 = or(T_1087, cyc_B2_div) - node T_1089 = or(T_1088, cyc_B1_sqrt) - node T_1090 = or(T_1089, cyc_C4) - node T_1091 = or(cyc_A3, cyc_A2_div) - node T_1092 = or(T_1091, cyc_B9_sqrt) - node T_1093 = or(T_1092, cyc_B8_sqrt) - node T_1094 = or(T_1093, cyc_B6) - node T_1095 = or(T_1094, cyc_B5) - node T_1096 = or(T_1095, cyc_B4_sqrt) - node T_1097 = or(T_1096, cyc_B2_sqrt) - node T_1098 = or(T_1097, cyc_B1_div) - node T_1099 = or(T_1098, cyc_C6_sqrt) - node T_1100 = or(T_1099, valid_normalCase_leaving_PB) - node T_1101 = or(cyc_A2, cyc_A1_div) - node T_1102 = or(T_1101, cyc_B8_sqrt) - node T_1103 = or(T_1102, cyc_B7_sqrt) - node T_1104 = or(T_1103, cyc_B5) - node T_1105 = or(T_1104, cyc_B4) - node T_1106 = or(T_1105, cyc_B3_sqrt) - node T_1107 = or(T_1106, cyc_B1_sqrt) - node T_1108 = or(T_1107, cyc_C5) - node T_1109 = or(T_1108, cyc_C2) - node T_1110 = or(io.latchMulAddA_0, cyc_B6) - node T_1111 = or(T_1110, cyc_B2_sqrt) - node T_1112 = cat(T_1090, T_1100) - node T_1113 = cat(T_1109, T_1111) - node T_1114 = cat(T_1112, T_1113) - io.usingMulAdd <= T_1114 - node T_1115 = shl(sigX1_B, 47) - node T_1117 = mux(cyc_B1, T_1115, UInt<1>("h00")) - node T_1118 = shl(sigX1_B, 46) - node T_1120 = mux(cyc_C6_sqrt, T_1118, UInt<1>("h00")) - node T_1121 = or(T_1117, T_1120) - node T_1122 = or(cyc_C4_sqrt, cyc_C2) - node T_1123 = shl(sigXN_C, 47) - node T_1125 = mux(T_1122, T_1123, UInt<1>("h00")) - node T_1126 = or(T_1121, T_1125) - node T_1127 = not(E_E_div) - node T_1128 = and(cyc_E3_div, T_1127) - node T_1129 = shl(fractA_0_PC, 53) - node T_1131 = mux(T_1128, T_1129, UInt<1>("h00")) - node T_1132 = or(T_1126, T_1131) - node T_1133 = bit(exp_PC, 0) - node T_1134 = bit(sigB_PC, 0) - node T_1136 = cat(T_1134, UInt<1>("h00")) - node T_1137 = bit(sigB_PC, 1) - node T_1138 = bit(sigB_PC, 0) - node T_1139 = xor(T_1137, T_1138) - node T_1140 = bit(sigB_PC, 0) - node T_1141 = cat(T_1139, T_1140) - node T_1142 = mux(T_1133, T_1136, T_1141) - node T_1143 = not(extraT_E) - node T_1145 = cat(T_1143, UInt<1>("h00")) - node T_1146 = xor(T_1142, T_1145) - node T_1147 = shl(T_1146, 54) - node T_1149 = mux(cyc_E3_sqrt, T_1147, UInt<1>("h00")) - node T_1150 = or(T_1132, T_1149) - io.mulAddC_2 <= T_1150 + node T_989 = or(cyc_A1, cyc_B7_sqrt) + node T_990 = or(T_989, cyc_B6_div) + node T_991 = or(T_990, cyc_B4) + node T_992 = or(T_991, cyc_B3) + node T_993 = or(T_992, cyc_C6_sqrt) + node T_994 = or(T_993, cyc_C4) + node T_995 = or(T_994, cyc_C1) + io.latchMulAddA_0 <= T_995 + node T_996 = shl(ER1_A1_sqrt, 36) + node T_998 = mux(cyc_A1_sqrt, T_996, UInt<1>("h00")) + node T_999 = or(cyc_B7_sqrt, cyc_A1_div) + node T_1001 = mux(T_999, sigB_PA, UInt<1>("h00")) + node T_1002 = or(T_998, T_1001) + node T_1004 = mux(cyc_B6_div, sigA_PA, UInt<1>("h00")) + node T_1005 = or(T_1002, T_1004) + node T_1006 = bits(zSigma1_B4, 45, 12) + node T_1007 = or(T_1005, T_1006) + node T_1008 = or(cyc_B3, cyc_C6_sqrt) + node T_1009 = bits(sigXNU_B3_CX, 57, 12) + node T_1011 = mux(T_1008, T_1009, UInt<1>("h00")) + node T_1012 = or(T_1007, T_1011) + node T_1013 = bits(sigXN_C, 57, 25) + node T_1014 = shl(T_1013, 13) + node T_1016 = mux(cyc_C4_div, T_1014, UInt<1>("h00")) + node T_1017 = or(T_1012, T_1016) + node T_1018 = shl(u_C_sqrt, 15) + node T_1020 = mux(cyc_C4_sqrt, T_1018, UInt<1>("h00")) + node T_1021 = or(T_1017, T_1020) + node T_1023 = mux(cyc_C1_div, sigB_PC, UInt<1>("h00")) + node T_1024 = or(T_1021, T_1023) + node T_1025 = or(T_1024, zComplSigT_C1_sqrt) + io.mulAddA_0 <= T_1025 + node T_1026 = or(cyc_A1, cyc_B7_sqrt) + node T_1027 = or(T_1026, cyc_B6_sqrt) + node T_1028 = or(T_1027, cyc_B4) + node T_1029 = or(T_1028, cyc_C6_sqrt) + node T_1030 = or(T_1029, cyc_C4) + node T_1031 = or(T_1030, cyc_C1) + io.latchMulAddB_0 <= T_1031 + node T_1032 = shl(r1_A1, 36) + node T_1034 = mux(cyc_A1, T_1032, UInt<1>("h00")) + node T_1035 = shl(ESqrR1_B_sqrt, 19) + node T_1037 = mux(cyc_B7_sqrt, T_1035, UInt<1>("h00")) + node T_1038 = or(T_1034, T_1037) + node T_1039 = shl(ER1_B_sqrt, 36) + node T_1041 = mux(cyc_B6_sqrt, T_1039, UInt<1>("h00")) + node T_1042 = or(T_1038, T_1041) + node T_1043 = or(T_1042, zSigma1_B4) + node T_1044 = bits(sqrSigma1_C, 30, 1) + node T_1046 = mux(cyc_C6_sqrt, T_1044, UInt<1>("h00")) + node T_1047 = or(T_1043, T_1046) + node T_1049 = mux(cyc_C4, sqrSigma1_C, UInt<1>("h00")) + node T_1050 = or(T_1047, T_1049) + node T_1051 = or(T_1050, zComplSigT_C1) + io.mulAddB_0 <= T_1051 + node T_1052 = or(cyc_A4, cyc_A3_div) + node T_1053 = or(T_1052, cyc_A1_div) + node T_1054 = or(T_1053, cyc_B10_sqrt) + node T_1055 = or(T_1054, cyc_B9_sqrt) + node T_1056 = or(T_1055, cyc_B7_sqrt) + node T_1057 = or(T_1056, cyc_B6) + node T_1058 = or(T_1057, cyc_B5_sqrt) + node T_1059 = or(T_1058, cyc_B3_sqrt) + node T_1060 = or(T_1059, cyc_B2_div) + node T_1061 = or(T_1060, cyc_B1_sqrt) + node T_1062 = or(T_1061, cyc_C4) + node T_1063 = or(cyc_A3, cyc_A2_div) + node T_1064 = or(T_1063, cyc_B9_sqrt) + node T_1065 = or(T_1064, cyc_B8_sqrt) + node T_1066 = or(T_1065, cyc_B6) + node T_1067 = or(T_1066, cyc_B5) + node T_1068 = or(T_1067, cyc_B4_sqrt) + node T_1069 = or(T_1068, cyc_B2_sqrt) + node T_1070 = or(T_1069, cyc_B1_div) + node T_1071 = or(T_1070, cyc_C6_sqrt) + node T_1072 = or(T_1071, valid_normalCase_leaving_PB) + node T_1073 = or(cyc_A2, cyc_A1_div) + node T_1074 = or(T_1073, cyc_B8_sqrt) + node T_1075 = or(T_1074, cyc_B7_sqrt) + node T_1076 = or(T_1075, cyc_B5) + node T_1077 = or(T_1076, cyc_B4) + node T_1078 = or(T_1077, cyc_B3_sqrt) + node T_1079 = or(T_1078, cyc_B1_sqrt) + node T_1080 = or(T_1079, cyc_C5) + node T_1081 = or(T_1080, cyc_C2) + node T_1082 = or(io.latchMulAddA_0, cyc_B6) + node T_1083 = or(T_1082, cyc_B2_sqrt) + node T_1084 = cat(T_1062, T_1072) + node T_1085 = cat(T_1081, T_1083) + node T_1086 = cat(T_1084, T_1085) + io.usingMulAdd <= T_1086 + node T_1087 = shl(sigX1_B, 47) + node T_1089 = mux(cyc_B1, T_1087, UInt<1>("h00")) + node T_1090 = shl(sigX1_B, 46) + node T_1092 = mux(cyc_C6_sqrt, T_1090, UInt<1>("h00")) + node T_1093 = or(T_1089, T_1092) + node T_1094 = or(cyc_C4_sqrt, cyc_C2) + node T_1095 = shl(sigXN_C, 47) + node T_1097 = mux(T_1094, T_1095, UInt<1>("h00")) + node T_1098 = or(T_1093, T_1097) + node T_1099 = not(E_E_div) + node T_1100 = and(cyc_E3_div, T_1099) + node T_1101 = shl(fractA_0_PC, 53) + node T_1103 = mux(T_1100, T_1101, UInt<1>("h00")) + node T_1104 = or(T_1098, T_1103) + node T_1105 = bits(exp_PC, 0, 0) + node T_1106 = bits(sigB_PC, 0, 0) + node T_1108 = cat(T_1106, UInt<1>("h00")) + node T_1109 = bits(sigB_PC, 1, 1) + node T_1110 = bits(sigB_PC, 0, 0) + node T_1111 = xor(T_1109, T_1110) + node T_1112 = bits(sigB_PC, 0, 0) + node T_1113 = cat(T_1111, T_1112) + node T_1114 = mux(T_1105, T_1108, T_1113) + node T_1115 = not(extraT_E) + node T_1117 = cat(T_1115, UInt<1>("h00")) + node T_1118 = xor(T_1114, T_1117) + node T_1119 = shl(T_1118, 54) + node T_1121 = mux(cyc_E3_sqrt, T_1119, UInt<1>("h00")) + node T_1122 = or(T_1104, T_1121) + io.mulAddC_2 <= T_1122 node ESqrR1_B8_sqrt = bits(io.mulAddResult_3, 103, 72) - node T_1152 = bits(io.mulAddResult_3, 90, 45) - node T_1153 = not(T_1152) - node T_1155 = mux(cyc_B4, T_1153, UInt<1>("h00")) - zSigma1_B4 <= T_1155 + node T_1124 = bits(io.mulAddResult_3, 90, 45) + node T_1125 = not(T_1124) + node T_1127 = mux(cyc_B4, T_1125, UInt<1>("h00")) + zSigma1_B4 <= T_1127 node sqrSigma1_B1 = bits(io.mulAddResult_3, 79, 47) - node T_1157 = bits(io.mulAddResult_3, 104, 47) - sigXNU_B3_CX <= T_1157 - node T_1158 = bit(io.mulAddResult_3, 104) - node E_C1_div = not(T_1158) - node T_1160 = not(E_C1_div) - node T_1161 = and(cyc_C1_div, T_1160) - node T_1162 = or(T_1161, cyc_C1_sqrt) - node T_1163 = bits(io.mulAddResult_3, 104, 51) - node T_1164 = not(T_1163) - node T_1166 = mux(T_1162, T_1164, UInt<1>("h00")) - node T_1167 = and(cyc_C1_div, E_C1_div) - node T_1169 = bits(io.mulAddResult_3, 102, 50) - node T_1170 = not(T_1169) - node T_1171 = cat(UInt<1>("h00"), T_1170) - node T_1173 = mux(T_1167, T_1171, UInt<1>("h00")) - node T_1174 = or(T_1166, T_1173) - zComplSigT_C1 <= T_1174 - node T_1175 = bits(io.mulAddResult_3, 104, 51) - node T_1176 = not(T_1175) - node T_1178 = mux(cyc_C1_sqrt, T_1176, UInt<1>("h00")) - zComplSigT_C1_sqrt <= T_1178 + node T_1129 = bits(io.mulAddResult_3, 104, 47) + sigXNU_B3_CX <= T_1129 + node T_1130 = bits(io.mulAddResult_3, 104, 104) + node E_C1_div = not(T_1130) + node T_1132 = not(E_C1_div) + node T_1133 = and(cyc_C1_div, T_1132) + node T_1134 = or(T_1133, cyc_C1_sqrt) + node T_1135 = bits(io.mulAddResult_3, 104, 51) + node T_1136 = not(T_1135) + node T_1138 = mux(T_1134, T_1136, UInt<1>("h00")) + node T_1139 = and(cyc_C1_div, E_C1_div) + node T_1141 = bits(io.mulAddResult_3, 102, 50) + node T_1142 = not(T_1141) + node T_1143 = cat(UInt<1>("h00"), T_1142) + node T_1145 = mux(T_1139, T_1143, UInt<1>("h00")) + node T_1146 = or(T_1138, T_1145) + zComplSigT_C1 <= T_1146 + node T_1147 = bits(io.mulAddResult_3, 104, 51) + node T_1148 = not(T_1147) + node T_1150 = mux(cyc_C1_sqrt, T_1148, UInt<1>("h00")) + zComplSigT_C1_sqrt <= T_1150 node sigT_C1 = not(zComplSigT_C1) node remT_E2 = bits(io.mulAddResult_3, 55, 0) when cyc_B8_sqrt : @@ -39004,364 +31041,370 @@ circuit Top : when cyc_B1 : sqrSigma1_C <= sqrSigma1_B1 skip - node T_1181 = or(cyc_C6_sqrt, cyc_C5_div) - node T_1182 = or(T_1181, cyc_C3_sqrt) - when T_1182 : + node T_1153 = or(cyc_C6_sqrt, cyc_C5_div) + node T_1154 = or(T_1153, cyc_C3_sqrt) + when T_1154 : sigXN_C <= sigXNU_B3_CX skip when cyc_C5_sqrt : - node T_1183 = bits(sigXNU_B3_CX, 56, 26) - u_C_sqrt <= T_1183 + node T_1155 = bits(sigXNU_B3_CX, 56, 26) + u_C_sqrt <= T_1155 skip when cyc_C1 : E_E_div <= E_C1_div - node T_1184 = bits(sigT_C1, 53, 1) - sigT_E <= T_1184 - node T_1185 = bit(sigT_C1, 0) - extraT_E <= T_1185 + node T_1156 = bits(sigT_C1, 53, 1) + sigT_E <= T_1156 + node T_1157 = bits(sigT_C1, 0, 0) + extraT_E <= T_1157 skip when cyc_E2 : - node T_1186 = bit(remT_E2, 55) - node T_1187 = bit(remT_E2, 53) - node T_1188 = mux(sqrtOp_PC, T_1186, T_1187) - isNegRemT_E <= T_1188 - node T_1189 = bits(remT_E2, 53, 0) - node T_1191 = eq(T_1189, UInt<1>("h00")) - node T_1192 = not(sqrtOp_PC) - node T_1193 = bits(remT_E2, 55, 54) - node T_1195 = eq(T_1193, UInt<1>("h00")) - node T_1196 = or(T_1192, T_1195) - node T_1197 = and(T_1191, T_1196) - trueEqX_E1 <= T_1197 - skip - node T_1198 = not(sqrtOp_PC) - node T_1199 = and(T_1198, E_E_div) - node T_1201 = mux(T_1199, exp_PC, UInt<1>("h00")) - node T_1202 = not(sqrtOp_PC) - node T_1203 = not(E_E_div) - node T_1204 = and(T_1202, T_1203) - node T_1206 = mux(T_1204, expP1_PC, UInt<1>("h00")) - node T_1207 = or(T_1201, T_1206) - node T_1208 = shr(exp_PC, 1) - node T_1210 = addw(T_1208, UInt<12>("h0400")) - node T_1212 = mux(sqrtOp_PC, T_1210, UInt<1>("h00")) - node sExpX_E = or(T_1207, T_1212) + node T_1158 = bits(remT_E2, 55, 55) + node T_1159 = bits(remT_E2, 53, 53) + node T_1160 = mux(sqrtOp_PC, T_1158, T_1159) + isNegRemT_E <= T_1160 + node T_1161 = bits(remT_E2, 53, 0) + node T_1163 = eq(T_1161, UInt<1>("h00")) + node T_1164 = not(sqrtOp_PC) + node T_1165 = bits(remT_E2, 55, 54) + node T_1167 = eq(T_1165, UInt<1>("h00")) + node T_1168 = or(T_1164, T_1167) + node T_1169 = and(T_1163, T_1168) + trueEqX_E1 <= T_1169 + skip + node T_1170 = not(sqrtOp_PC) + node T_1171 = and(T_1170, E_E_div) + node T_1173 = mux(T_1171, exp_PC, UInt<1>("h00")) + node T_1174 = not(sqrtOp_PC) + node T_1175 = not(E_E_div) + node T_1176 = and(T_1174, T_1175) + node T_1178 = mux(T_1176, expP1_PC, UInt<1>("h00")) + node T_1179 = or(T_1173, T_1178) + node T_1180 = shr(exp_PC, 1) + node T_1182 = add(T_1180, UInt<12>("h0400")) + node T_1183 = tail(T_1182, 1) + node T_1185 = mux(sqrtOp_PC, T_1183, UInt<1>("h00")) + node sExpX_E = or(T_1179, T_1185) node posExpX_E = bits(sExpX_E, 12, 0) - node T_1215 = not(posExpX_E) - node T_1217 = dshr(asSInt(UInt<8193>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_1215) - node T_1218 = bits(T_1217, 1026, 974) - node T_1219 = bits(T_1218, 31, 0) - node T_1222 = shl(UInt<16>("h0ffff"), 16) - node T_1223 = xor(UInt<32>("h0ffffffff"), T_1222) - node T_1224 = shr(T_1219, 16) - node T_1225 = and(T_1224, T_1223) - node T_1226 = bits(T_1219, 15, 0) - node T_1227 = shl(T_1226, 16) - node T_1228 = not(T_1223) - node T_1229 = and(T_1227, T_1228) - node T_1230 = or(T_1225, T_1229) - node T_1231 = bits(T_1223, 23, 0) - node T_1232 = shl(T_1231, 8) - node T_1233 = xor(T_1223, T_1232) - node T_1234 = shr(T_1230, 8) - node T_1235 = and(T_1234, T_1233) - node T_1236 = bits(T_1230, 23, 0) - node T_1237 = shl(T_1236, 8) - node T_1238 = not(T_1233) - node T_1239 = and(T_1237, T_1238) - node T_1240 = or(T_1235, T_1239) - node T_1241 = bits(T_1233, 27, 0) - node T_1242 = shl(T_1241, 4) - node T_1243 = xor(T_1233, T_1242) - node T_1244 = shr(T_1240, 4) - node T_1245 = and(T_1244, T_1243) - node T_1246 = bits(T_1240, 27, 0) - node T_1247 = shl(T_1246, 4) - node T_1248 = not(T_1243) - node T_1249 = and(T_1247, T_1248) - node T_1250 = or(T_1245, T_1249) - node T_1251 = bits(T_1243, 29, 0) - node T_1252 = shl(T_1251, 2) - node T_1253 = xor(T_1243, T_1252) - node T_1254 = shr(T_1250, 2) - node T_1255 = and(T_1254, T_1253) - node T_1256 = bits(T_1250, 29, 0) - node T_1257 = shl(T_1256, 2) - node T_1258 = not(T_1253) - node T_1259 = and(T_1257, T_1258) - node T_1260 = or(T_1255, T_1259) - node T_1261 = bits(T_1253, 30, 0) - node T_1262 = shl(T_1261, 1) - node T_1263 = xor(T_1253, T_1262) - node T_1264 = shr(T_1260, 1) - node T_1265 = and(T_1264, T_1263) - node T_1266 = bits(T_1260, 30, 0) - node T_1267 = shl(T_1266, 1) - node T_1268 = not(T_1263) - node T_1269 = and(T_1267, T_1268) - node T_1270 = or(T_1265, T_1269) - node T_1271 = bits(T_1218, 52, 32) - node T_1272 = bits(T_1271, 15, 0) - node T_1275 = shl(UInt<8>("h0ff"), 8) - node T_1276 = xor(UInt<16>("h0ffff"), T_1275) - node T_1277 = shr(T_1272, 8) - node T_1278 = and(T_1277, T_1276) - node T_1279 = bits(T_1272, 7, 0) - node T_1280 = shl(T_1279, 8) - node T_1281 = not(T_1276) - node T_1282 = and(T_1280, T_1281) - node T_1283 = or(T_1278, T_1282) - node T_1284 = bits(T_1276, 11, 0) - node T_1285 = shl(T_1284, 4) - node T_1286 = xor(T_1276, T_1285) - node T_1287 = shr(T_1283, 4) - node T_1288 = and(T_1287, T_1286) - node T_1289 = bits(T_1283, 11, 0) - node T_1290 = shl(T_1289, 4) - node T_1291 = not(T_1286) - node T_1292 = and(T_1290, T_1291) - node T_1293 = or(T_1288, T_1292) - node T_1294 = bits(T_1286, 13, 0) - node T_1295 = shl(T_1294, 2) - node T_1296 = xor(T_1286, T_1295) - node T_1297 = shr(T_1293, 2) - node T_1298 = and(T_1297, T_1296) - node T_1299 = bits(T_1293, 13, 0) - node T_1300 = shl(T_1299, 2) - node T_1301 = not(T_1296) - node T_1302 = and(T_1300, T_1301) - node T_1303 = or(T_1298, T_1302) - node T_1304 = bits(T_1296, 14, 0) - node T_1305 = shl(T_1304, 1) - node T_1306 = xor(T_1296, T_1305) - node T_1307 = shr(T_1303, 1) - node T_1308 = and(T_1307, T_1306) - node T_1309 = bits(T_1303, 14, 0) - node T_1310 = shl(T_1309, 1) - node T_1311 = not(T_1306) - node T_1312 = and(T_1310, T_1311) - node T_1313 = or(T_1308, T_1312) - node T_1314 = bits(T_1271, 20, 16) - node T_1315 = bits(T_1314, 3, 0) - node T_1316 = bits(T_1315, 1, 0) - node T_1317 = bits(T_1316, 0, 0) - node T_1318 = bits(T_1316, 1, 1) - node T_1319 = cat(T_1317, T_1318) - node T_1320 = bits(T_1315, 3, 2) - node T_1321 = bits(T_1320, 0, 0) - node T_1322 = bits(T_1320, 1, 1) - node T_1323 = cat(T_1321, T_1322) - node T_1324 = cat(T_1319, T_1323) - node T_1325 = bits(T_1314, 4, 4) - node T_1326 = cat(T_1324, T_1325) - node T_1327 = cat(T_1313, T_1326) - node roundMask_E = cat(T_1270, T_1327) - node T_1330 = cat(UInt<1>("h00"), roundMask_E) - node T_1331 = not(T_1330) - node T_1333 = cat(roundMask_E, UInt<1>("h01")) - node incrPosMask_E = and(T_1331, T_1333) - node T_1335 = shr(incrPosMask_E, 1) - node T_1336 = and(sigT_E, T_1335) - node hiRoundPosBitT_E = neq(T_1336, UInt<1>("h00")) - node T_1339 = shr(roundMask_E, 1) - node T_1340 = and(sigT_E, T_1339) - node all0sHiRoundExtraT_E = eq(T_1340, UInt<1>("h00")) - node T_1343 = not(sigT_E) - node T_1344 = shr(roundMask_E, 1) - node T_1345 = and(T_1343, T_1344) - node all1sHiRoundExtraT_E = eq(T_1345, UInt<1>("h00")) - node T_1348 = bit(roundMask_E, 0) - node T_1349 = not(T_1348) - node T_1350 = or(T_1349, hiRoundPosBitT_E) - node all1sHiRoundT_E = and(T_1350, all1sHiRoundExtraT_E) - node T_1353 = addw(UInt<54>("h00"), sigT_E) - node sigAdjT_E = addw(T_1353, roundMagUp_PC) - node T_1356 = not(roundMask_E) - node T_1357 = cat(UInt<1>("h01"), T_1356) - node sigY0_E = and(sigAdjT_E, T_1357) - node T_1360 = cat(UInt<1>("h00"), roundMask_E) - node T_1361 = or(sigAdjT_E, T_1360) - node sigY1_E = addw(T_1361, UInt<1>("h01")) - node T_1364 = not(isNegRemT_E) - node T_1365 = not(trueEqX_E1) - node T_1366 = and(T_1364, T_1365) - node trueLtX_E1 = mux(sqrtOp_PC, T_1366, isNegRemT_E) - node T_1368 = bit(roundMask_E, 0) - node T_1369 = not(trueLtX_E1) - node T_1370 = and(T_1368, T_1369) - node T_1371 = and(T_1370, all1sHiRoundExtraT_E) - node T_1372 = and(T_1371, extraT_E) - node hiRoundPosBit_E1 = xor(hiRoundPosBitT_E, T_1372) - node T_1374 = not(trueEqX_E1) - node T_1375 = not(extraT_E) - node T_1376 = or(T_1374, T_1375) - node T_1377 = not(all1sHiRoundExtraT_E) - node anyRoundExtra_E1 = or(T_1376, T_1377) - node T_1379 = and(roundingMode_near_even_PC, hiRoundPosBit_E1) - node T_1380 = not(anyRoundExtra_E1) - node T_1381 = and(T_1379, T_1380) - node roundEvenMask_E1 = mux(T_1381, incrPosMask_E, UInt<1>("h00")) - node T_1384 = and(roundMagDown_PC, extraT_E) - node T_1385 = not(trueLtX_E1) - node T_1386 = and(T_1384, T_1385) - node T_1387 = and(T_1386, all1sHiRoundT_E) - node T_1388 = not(trueLtX_E1) - node T_1389 = and(extraT_E, T_1388) - node T_1390 = not(trueEqX_E1) - node T_1391 = and(T_1389, T_1390) - node T_1392 = not(all1sHiRoundT_E) - node T_1393 = or(T_1391, T_1392) - node T_1394 = and(roundMagUp_PC, T_1393) - node T_1395 = or(T_1387, T_1394) - node T_1396 = not(trueLtX_E1) - node T_1397 = or(extraT_E, T_1396) - node T_1398 = bit(roundMask_E, 0) - node T_1399 = not(T_1398) - node T_1400 = and(T_1397, T_1399) - node T_1401 = or(hiRoundPosBitT_E, T_1400) - node T_1402 = not(trueLtX_E1) - node T_1403 = and(extraT_E, T_1402) - node T_1404 = and(T_1403, all1sHiRoundExtraT_E) - node T_1405 = or(T_1401, T_1404) - node T_1406 = and(roundingMode_near_even_PC, T_1405) - node T_1407 = or(T_1395, T_1406) - node T_1408 = mux(T_1407, sigY1_E, sigY0_E) - node T_1409 = not(roundEvenMask_E1) - node sigY_E1 = and(T_1408, T_1409) + node T_1188 = not(posExpX_E) + node T_1190 = dshr(asSInt(UInt<8193>("h0100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000")), T_1188) + node T_1191 = bits(T_1190, 1026, 974) + node T_1192 = bits(T_1191, 31, 0) + node T_1195 = shl(UInt<16>("h0ffff"), 16) + node T_1196 = xor(UInt<32>("h0ffffffff"), T_1195) + node T_1197 = shr(T_1192, 16) + node T_1198 = and(T_1197, T_1196) + node T_1199 = bits(T_1192, 15, 0) + node T_1200 = shl(T_1199, 16) + node T_1201 = not(T_1196) + node T_1202 = and(T_1200, T_1201) + node T_1203 = or(T_1198, T_1202) + node T_1204 = bits(T_1196, 23, 0) + node T_1205 = shl(T_1204, 8) + node T_1206 = xor(T_1196, T_1205) + node T_1207 = shr(T_1203, 8) + node T_1208 = and(T_1207, T_1206) + node T_1209 = bits(T_1203, 23, 0) + node T_1210 = shl(T_1209, 8) + node T_1211 = not(T_1206) + node T_1212 = and(T_1210, T_1211) + node T_1213 = or(T_1208, T_1212) + node T_1214 = bits(T_1206, 27, 0) + node T_1215 = shl(T_1214, 4) + node T_1216 = xor(T_1206, T_1215) + node T_1217 = shr(T_1213, 4) + node T_1218 = and(T_1217, T_1216) + node T_1219 = bits(T_1213, 27, 0) + node T_1220 = shl(T_1219, 4) + node T_1221 = not(T_1216) + node T_1222 = and(T_1220, T_1221) + node T_1223 = or(T_1218, T_1222) + node T_1224 = bits(T_1216, 29, 0) + node T_1225 = shl(T_1224, 2) + node T_1226 = xor(T_1216, T_1225) + node T_1227 = shr(T_1223, 2) + node T_1228 = and(T_1227, T_1226) + node T_1229 = bits(T_1223, 29, 0) + node T_1230 = shl(T_1229, 2) + node T_1231 = not(T_1226) + node T_1232 = and(T_1230, T_1231) + node T_1233 = or(T_1228, T_1232) + node T_1234 = bits(T_1226, 30, 0) + node T_1235 = shl(T_1234, 1) + node T_1236 = xor(T_1226, T_1235) + node T_1237 = shr(T_1233, 1) + node T_1238 = and(T_1237, T_1236) + node T_1239 = bits(T_1233, 30, 0) + node T_1240 = shl(T_1239, 1) + node T_1241 = not(T_1236) + node T_1242 = and(T_1240, T_1241) + node T_1243 = or(T_1238, T_1242) + node T_1244 = bits(T_1191, 52, 32) + node T_1245 = bits(T_1244, 15, 0) + node T_1248 = shl(UInt<8>("h0ff"), 8) + node T_1249 = xor(UInt<16>("h0ffff"), T_1248) + node T_1250 = shr(T_1245, 8) + node T_1251 = and(T_1250, T_1249) + node T_1252 = bits(T_1245, 7, 0) + node T_1253 = shl(T_1252, 8) + node T_1254 = not(T_1249) + node T_1255 = and(T_1253, T_1254) + node T_1256 = or(T_1251, T_1255) + node T_1257 = bits(T_1249, 11, 0) + node T_1258 = shl(T_1257, 4) + node T_1259 = xor(T_1249, T_1258) + node T_1260 = shr(T_1256, 4) + node T_1261 = and(T_1260, T_1259) + node T_1262 = bits(T_1256, 11, 0) + node T_1263 = shl(T_1262, 4) + node T_1264 = not(T_1259) + node T_1265 = and(T_1263, T_1264) + node T_1266 = or(T_1261, T_1265) + node T_1267 = bits(T_1259, 13, 0) + node T_1268 = shl(T_1267, 2) + node T_1269 = xor(T_1259, T_1268) + node T_1270 = shr(T_1266, 2) + node T_1271 = and(T_1270, T_1269) + node T_1272 = bits(T_1266, 13, 0) + node T_1273 = shl(T_1272, 2) + node T_1274 = not(T_1269) + node T_1275 = and(T_1273, T_1274) + node T_1276 = or(T_1271, T_1275) + node T_1277 = bits(T_1269, 14, 0) + node T_1278 = shl(T_1277, 1) + node T_1279 = xor(T_1269, T_1278) + node T_1280 = shr(T_1276, 1) + node T_1281 = and(T_1280, T_1279) + node T_1282 = bits(T_1276, 14, 0) + node T_1283 = shl(T_1282, 1) + node T_1284 = not(T_1279) + node T_1285 = and(T_1283, T_1284) + node T_1286 = or(T_1281, T_1285) + node T_1287 = bits(T_1244, 20, 16) + node T_1288 = bits(T_1287, 3, 0) + node T_1289 = bits(T_1288, 1, 0) + node T_1290 = bits(T_1289, 0, 0) + node T_1291 = bits(T_1289, 1, 1) + node T_1292 = cat(T_1290, T_1291) + node T_1293 = bits(T_1288, 3, 2) + node T_1294 = bits(T_1293, 0, 0) + node T_1295 = bits(T_1293, 1, 1) + node T_1296 = cat(T_1294, T_1295) + node T_1297 = cat(T_1292, T_1296) + node T_1298 = bits(T_1287, 4, 4) + node T_1299 = cat(T_1297, T_1298) + node T_1300 = cat(T_1286, T_1299) + node roundMask_E = cat(T_1243, T_1300) + node T_1303 = cat(UInt<1>("h00"), roundMask_E) + node T_1304 = not(T_1303) + node T_1306 = cat(roundMask_E, UInt<1>("h01")) + node incrPosMask_E = and(T_1304, T_1306) + node T_1308 = shr(incrPosMask_E, 1) + node T_1309 = and(sigT_E, T_1308) + node hiRoundPosBitT_E = neq(T_1309, UInt<1>("h00")) + node T_1312 = shr(roundMask_E, 1) + node T_1313 = and(sigT_E, T_1312) + node all0sHiRoundExtraT_E = eq(T_1313, UInt<1>("h00")) + node T_1316 = not(sigT_E) + node T_1317 = shr(roundMask_E, 1) + node T_1318 = and(T_1316, T_1317) + node all1sHiRoundExtraT_E = eq(T_1318, UInt<1>("h00")) + node T_1321 = bits(roundMask_E, 0, 0) + node T_1322 = not(T_1321) + node T_1323 = or(T_1322, hiRoundPosBitT_E) + node all1sHiRoundT_E = and(T_1323, all1sHiRoundExtraT_E) + node T_1326 = add(UInt<54>("h00"), sigT_E) + node T_1327 = tail(T_1326, 1) + node T_1328 = add(T_1327, roundMagUp_PC) + node sigAdjT_E = tail(T_1328, 1) + node T_1331 = not(roundMask_E) + node T_1332 = cat(UInt<1>("h01"), T_1331) + node sigY0_E = and(sigAdjT_E, T_1332) + node T_1335 = cat(UInt<1>("h00"), roundMask_E) + node T_1336 = or(sigAdjT_E, T_1335) + node T_1338 = add(T_1336, UInt<1>("h01")) + node sigY1_E = tail(T_1338, 1) + node T_1340 = not(isNegRemT_E) + node T_1341 = not(trueEqX_E1) + node T_1342 = and(T_1340, T_1341) + node trueLtX_E1 = mux(sqrtOp_PC, T_1342, isNegRemT_E) + node T_1344 = bits(roundMask_E, 0, 0) + node T_1345 = not(trueLtX_E1) + node T_1346 = and(T_1344, T_1345) + node T_1347 = and(T_1346, all1sHiRoundExtraT_E) + node T_1348 = and(T_1347, extraT_E) + node hiRoundPosBit_E1 = xor(hiRoundPosBitT_E, T_1348) + node T_1350 = not(trueEqX_E1) + node T_1351 = not(extraT_E) + node T_1352 = or(T_1350, T_1351) + node T_1353 = not(all1sHiRoundExtraT_E) + node anyRoundExtra_E1 = or(T_1352, T_1353) + node T_1355 = and(roundingMode_near_even_PC, hiRoundPosBit_E1) + node T_1356 = not(anyRoundExtra_E1) + node T_1357 = and(T_1355, T_1356) + node roundEvenMask_E1 = mux(T_1357, incrPosMask_E, UInt<1>("h00")) + node T_1360 = and(roundMagDown_PC, extraT_E) + node T_1361 = not(trueLtX_E1) + node T_1362 = and(T_1360, T_1361) + node T_1363 = and(T_1362, all1sHiRoundT_E) + node T_1364 = not(trueLtX_E1) + node T_1365 = and(extraT_E, T_1364) + node T_1366 = not(trueEqX_E1) + node T_1367 = and(T_1365, T_1366) + node T_1368 = not(all1sHiRoundT_E) + node T_1369 = or(T_1367, T_1368) + node T_1370 = and(roundMagUp_PC, T_1369) + node T_1371 = or(T_1363, T_1370) + node T_1372 = not(trueLtX_E1) + node T_1373 = or(extraT_E, T_1372) + node T_1374 = bits(roundMask_E, 0, 0) + node T_1375 = not(T_1374) + node T_1376 = and(T_1373, T_1375) + node T_1377 = or(hiRoundPosBitT_E, T_1376) + node T_1378 = not(trueLtX_E1) + node T_1379 = and(extraT_E, T_1378) + node T_1380 = and(T_1379, all1sHiRoundExtraT_E) + node T_1381 = or(T_1377, T_1380) + node T_1382 = and(roundingMode_near_even_PC, T_1381) + node T_1383 = or(T_1371, T_1382) + node T_1384 = mux(T_1383, sigY1_E, sigY0_E) + node T_1385 = not(roundEvenMask_E1) + node sigY_E1 = and(T_1384, T_1385) node fractY_E1 = bits(sigY_E1, 51, 0) node inexactY_E1 = or(hiRoundPosBit_E1, anyRoundExtra_E1) - node T_1413 = bit(sigY_E1, 53) - node T_1414 = not(T_1413) - node T_1416 = mux(T_1414, sExpX_E, UInt<1>("h00")) - node T_1417 = bit(sigY_E1, 53) - node T_1418 = not(sqrtOp_PC) - node T_1419 = and(T_1417, T_1418) - node T_1420 = and(T_1419, E_E_div) - node T_1422 = mux(T_1420, expP1_PC, UInt<1>("h00")) - node T_1423 = or(T_1416, T_1422) - node T_1424 = bit(sigY_E1, 53) - node T_1425 = not(sqrtOp_PC) - node T_1426 = and(T_1424, T_1425) - node T_1427 = not(E_E_div) - node T_1428 = and(T_1426, T_1427) - node T_1430 = mux(T_1428, expP2_PC, UInt<1>("h00")) - node T_1431 = or(T_1423, T_1430) - node T_1432 = bit(sigY_E1, 53) - node T_1433 = and(T_1432, sqrtOp_PC) - node T_1434 = shr(expP2_PC, 1) - node T_1436 = addw(T_1434, UInt<12>("h0400")) - node T_1438 = mux(T_1433, T_1436, UInt<1>("h00")) - node sExpY_E1 = or(T_1431, T_1438) + node T_1389 = bits(sigY_E1, 53, 53) + node T_1390 = not(T_1389) + node T_1392 = mux(T_1390, sExpX_E, UInt<1>("h00")) + node T_1393 = bits(sigY_E1, 53, 53) + node T_1394 = not(sqrtOp_PC) + node T_1395 = and(T_1393, T_1394) + node T_1396 = and(T_1395, E_E_div) + node T_1398 = mux(T_1396, expP1_PC, UInt<1>("h00")) + node T_1399 = or(T_1392, T_1398) + node T_1400 = bits(sigY_E1, 53, 53) + node T_1401 = not(sqrtOp_PC) + node T_1402 = and(T_1400, T_1401) + node T_1403 = not(E_E_div) + node T_1404 = and(T_1402, T_1403) + node T_1406 = mux(T_1404, expP2_PC, UInt<1>("h00")) + node T_1407 = or(T_1399, T_1406) + node T_1408 = bits(sigY_E1, 53, 53) + node T_1409 = and(T_1408, sqrtOp_PC) + node T_1410 = shr(expP2_PC, 1) + node T_1412 = add(T_1410, UInt<12>("h0400")) + node T_1413 = tail(T_1412, 1) + node T_1415 = mux(T_1409, T_1413, UInt<1>("h00")) + node sExpY_E1 = or(T_1407, T_1415) node expY_E1 = bits(sExpY_E1, 11, 0) - node T_1441 = bit(sExpY_E1, 13) - node T_1442 = not(T_1441) - node T_1444 = bits(sExpY_E1, 12, 10) - node T_1445 = leq(UInt<3>("h03"), T_1444) - node overflowY_E1 = and(T_1442, T_1445) - node T_1447 = bit(sExpY_E1, 13) - node T_1448 = bits(sExpY_E1, 12, 0) - node T_1450 = lt(T_1448, UInt<13>("h03ce")) - node totalUnderflowY_E1 = or(T_1447, T_1450) - node T_1453 = leq(posExpX_E, UInt<13>("h0401")) - node T_1454 = and(T_1453, inexactY_E1) - node underflowY_E1 = or(totalUnderflowY_E1, T_1454) - node T_1456 = not(isNaNB_PC) - node T_1457 = not(isZeroB_PC) - node T_1458 = and(T_1456, T_1457) - node T_1459 = and(T_1458, sign_PC) - node T_1460 = and(isZeroA_PC, isZeroB_PC) - node T_1461 = and(isInfA_PC, isInfB_PC) - node T_1462 = or(T_1460, T_1461) - node notSigNaN_invalid_PC = mux(sqrtOp_PC, T_1459, T_1462) - node T_1464 = not(sqrtOp_PC) - node T_1465 = and(T_1464, isSigNaNA_PC) - node T_1466 = or(T_1465, isSigNaNB_PC) - node invalid_PC = or(T_1466, notSigNaN_invalid_PC) - node T_1468 = not(sqrtOp_PC) - node T_1469 = not(isSpecialA_PC) - node T_1470 = and(T_1468, T_1469) - node T_1471 = not(isZeroA_PC) - node T_1472 = and(T_1470, T_1471) - node infinity_PC = and(T_1472, isZeroB_PC) + node T_1418 = bits(sExpY_E1, 13, 13) + node T_1419 = not(T_1418) + node T_1421 = bits(sExpY_E1, 12, 10) + node T_1422 = leq(UInt<3>("h03"), T_1421) + node overflowY_E1 = and(T_1419, T_1422) + node T_1424 = bits(sExpY_E1, 13, 13) + node T_1425 = bits(sExpY_E1, 12, 0) + node T_1427 = lt(T_1425, UInt<13>("h03ce")) + node totalUnderflowY_E1 = or(T_1424, T_1427) + node T_1430 = leq(posExpX_E, UInt<13>("h0401")) + node T_1431 = and(T_1430, inexactY_E1) + node underflowY_E1 = or(totalUnderflowY_E1, T_1431) + node T_1433 = not(isNaNB_PC) + node T_1434 = not(isZeroB_PC) + node T_1435 = and(T_1433, T_1434) + node T_1436 = and(T_1435, sign_PC) + node T_1437 = and(isZeroA_PC, isZeroB_PC) + node T_1438 = and(isInfA_PC, isInfB_PC) + node T_1439 = or(T_1437, T_1438) + node notSigNaN_invalid_PC = mux(sqrtOp_PC, T_1436, T_1439) + node T_1441 = not(sqrtOp_PC) + node T_1442 = and(T_1441, isSigNaNA_PC) + node T_1443 = or(T_1442, isSigNaNB_PC) + node invalid_PC = or(T_1443, notSigNaN_invalid_PC) + node T_1445 = not(sqrtOp_PC) + node T_1446 = not(isSpecialA_PC) + node T_1447 = and(T_1445, T_1446) + node T_1448 = not(isZeroA_PC) + node T_1449 = and(T_1447, T_1448) + node infinity_PC = and(T_1449, isZeroB_PC) node overflow_E1 = and(normalCase_PC, overflowY_E1) node underflow_E1 = and(normalCase_PC, underflowY_E1) - node T_1476 = or(overflow_E1, underflow_E1) - node T_1477 = and(normalCase_PC, inexactY_E1) - node inexact_E1 = or(T_1476, T_1477) - node T_1479 = or(isZeroA_PC, isInfB_PC) - node T_1480 = not(roundMagUp_PC) - node T_1481 = and(totalUnderflowY_E1, T_1480) - node T_1482 = or(T_1479, T_1481) - node notSpecial_isZeroOut_E1 = mux(sqrtOp_PC, isZeroB_PC, T_1482) - node T_1484 = and(normalCase_PC, totalUnderflowY_E1) - node pegMinFiniteMagOut_E1 = and(T_1484, roundMagUp_PC) - node T_1486 = not(overflowY_roundMagUp_PC) - node pegMaxFiniteMagOut_E1 = and(overflow_E1, T_1486) - node T_1488 = or(isInfA_PC, isZeroB_PC) - node T_1489 = and(overflow_E1, overflowY_roundMagUp_PC) - node T_1490 = or(T_1488, T_1489) - node notNaN_isInfOut_E1 = mux(sqrtOp_PC, isInfB_PC, T_1490) - node T_1492 = not(sqrtOp_PC) - node T_1493 = and(T_1492, isNaNA_PC) - node T_1494 = or(T_1493, isNaNB_PC) - node isNaNOut_PC = or(T_1494, notSigNaN_invalid_PC) - node T_1496 = not(isNaNOut_PC) - node T_1497 = and(isZeroB_PC, sign_PC) - node T_1498 = mux(sqrtOp_PC, T_1497, sign_PC) - node signOut_PC = and(T_1496, T_1498) - node T_1501 = not(UInt<12>("h01ff")) - node T_1503 = mux(notSpecial_isZeroOut_E1, T_1501, UInt<1>("h00")) - node T_1504 = not(T_1503) - node T_1505 = and(expY_E1, T_1504) - node T_1507 = not(UInt<12>("h03ce")) - node T_1509 = mux(pegMinFiniteMagOut_E1, T_1507, UInt<1>("h00")) - node T_1510 = not(T_1509) - node T_1511 = and(T_1505, T_1510) - node T_1513 = not(UInt<12>("h0bff")) - node T_1515 = mux(pegMaxFiniteMagOut_E1, T_1513, UInt<1>("h00")) - node T_1516 = not(T_1515) - node T_1517 = and(T_1511, T_1516) - node T_1519 = not(UInt<12>("h0dff")) - node T_1521 = mux(notNaN_isInfOut_E1, T_1519, UInt<1>("h00")) - node T_1522 = not(T_1521) - node T_1523 = and(T_1517, T_1522) - node T_1526 = mux(pegMinFiniteMagOut_E1, UInt<12>("h03ce"), UInt<1>("h00")) - node T_1527 = or(T_1523, T_1526) - node T_1530 = mux(pegMaxFiniteMagOut_E1, UInt<12>("h0bff"), UInt<1>("h00")) - node T_1531 = or(T_1527, T_1530) - node T_1534 = mux(notNaN_isInfOut_E1, UInt<12>("h0c00"), UInt<1>("h00")) - node T_1535 = or(T_1531, T_1534) - node T_1538 = mux(isNaNOut_PC, UInt<12>("h0e00"), UInt<1>("h00")) - node expOut_E1 = or(T_1535, T_1538) - node T_1540 = or(notSpecial_isZeroOut_E1, totalUnderflowY_E1) - node T_1541 = or(T_1540, isNaNOut_PC) - node T_1543 = mux(T_1541, UInt<1>("h00"), fractY_E1) - node T_1545 = subw(UInt<52>("h00"), pegMaxFiniteMagOut_E1) - node T_1546 = or(T_1543, T_1545) - node T_1547 = shl(isNaNOut_PC, 51) - node fractOut_E1 = or(T_1546, T_1547) - node T_1549 = cat(expOut_E1, fractOut_E1) - node T_1550 = cat(signOut_PC, T_1549) - io.out <= T_1550 - node T_1551 = cat(invalid_PC, infinity_PC) - node T_1552 = cat(underflow_E1, inexact_E1) - node T_1553 = cat(overflow_E1, T_1552) - node T_1554 = cat(T_1551, T_1553) - io.exceptionFlags <= T_1554 + node T_1453 = or(overflow_E1, underflow_E1) + node T_1454 = and(normalCase_PC, inexactY_E1) + node inexact_E1 = or(T_1453, T_1454) + node T_1456 = or(isZeroA_PC, isInfB_PC) + node T_1457 = not(roundMagUp_PC) + node T_1458 = and(totalUnderflowY_E1, T_1457) + node T_1459 = or(T_1456, T_1458) + node notSpecial_isZeroOut_E1 = mux(sqrtOp_PC, isZeroB_PC, T_1459) + node T_1461 = and(normalCase_PC, totalUnderflowY_E1) + node pegMinFiniteMagOut_E1 = and(T_1461, roundMagUp_PC) + node T_1463 = not(overflowY_roundMagUp_PC) + node pegMaxFiniteMagOut_E1 = and(overflow_E1, T_1463) + node T_1465 = or(isInfA_PC, isZeroB_PC) + node T_1466 = and(overflow_E1, overflowY_roundMagUp_PC) + node T_1467 = or(T_1465, T_1466) + node notNaN_isInfOut_E1 = mux(sqrtOp_PC, isInfB_PC, T_1467) + node T_1469 = not(sqrtOp_PC) + node T_1470 = and(T_1469, isNaNA_PC) + node T_1471 = or(T_1470, isNaNB_PC) + node isNaNOut_PC = or(T_1471, notSigNaN_invalid_PC) + node T_1473 = not(isNaNOut_PC) + node T_1474 = and(isZeroB_PC, sign_PC) + node T_1475 = mux(sqrtOp_PC, T_1474, sign_PC) + node signOut_PC = and(T_1473, T_1475) + node T_1478 = not(UInt<12>("h01ff")) + node T_1480 = mux(notSpecial_isZeroOut_E1, T_1478, UInt<1>("h00")) + node T_1481 = not(T_1480) + node T_1482 = and(expY_E1, T_1481) + node T_1484 = not(UInt<12>("h03ce")) + node T_1486 = mux(pegMinFiniteMagOut_E1, T_1484, UInt<1>("h00")) + node T_1487 = not(T_1486) + node T_1488 = and(T_1482, T_1487) + node T_1490 = not(UInt<12>("h0bff")) + node T_1492 = mux(pegMaxFiniteMagOut_E1, T_1490, UInt<1>("h00")) + node T_1493 = not(T_1492) + node T_1494 = and(T_1488, T_1493) + node T_1496 = not(UInt<12>("h0dff")) + node T_1498 = mux(notNaN_isInfOut_E1, T_1496, UInt<1>("h00")) + node T_1499 = not(T_1498) + node T_1500 = and(T_1494, T_1499) + node T_1503 = mux(pegMinFiniteMagOut_E1, UInt<12>("h03ce"), UInt<1>("h00")) + node T_1504 = or(T_1500, T_1503) + node T_1507 = mux(pegMaxFiniteMagOut_E1, UInt<12>("h0bff"), UInt<1>("h00")) + node T_1508 = or(T_1504, T_1507) + node T_1511 = mux(notNaN_isInfOut_E1, UInt<12>("h0c00"), UInt<1>("h00")) + node T_1512 = or(T_1508, T_1511) + node T_1515 = mux(isNaNOut_PC, UInt<12>("h0e00"), UInt<1>("h00")) + node expOut_E1 = or(T_1512, T_1515) + node T_1517 = or(notSpecial_isZeroOut_E1, totalUnderflowY_E1) + node T_1518 = or(T_1517, isNaNOut_PC) + node T_1520 = mux(T_1518, UInt<1>("h00"), fractY_E1) + node T_1522 = sub(UInt<52>("h00"), pegMaxFiniteMagOut_E1) + node T_1523 = tail(T_1522, 1) + node T_1524 = or(T_1520, T_1523) + node T_1525 = shl(isNaNOut_PC, 51) + node fractOut_E1 = or(T_1524, T_1525) + node T_1527 = cat(expOut_E1, fractOut_E1) + node T_1528 = cat(signOut_PC, T_1527) + io.out <= T_1528 + node T_1529 = cat(invalid_PC, infinity_PC) + node T_1530 = cat(underflow_E1, inexact_E1) + node T_1531 = cat(overflow_E1, T_1530) + node T_1532 = cat(T_1529, T_1531) + io.exceptionFlags <= T_1532 module Mul54 : input clk : Clock input reset : UInt<1> output io : {flip val_s0 : UInt<1>, flip latch_a_s0 : UInt<1>, flip a_s0 : UInt<54>, flip latch_b_s0 : UInt<1>, flip b_s0 : UInt<54>, flip c_s2 : UInt<105>, result_s3 : UInt<105>} - io.result_s3 <= UInt<1>("h00") - reg val_s1 : UInt<1>, clk, UInt<1>("h00"), val_s1 - reg val_s2 : UInt<1>, clk, UInt<1>("h00"), val_s2 - reg reg_a_s1 : UInt<54>, clk, UInt<1>("h00"), reg_a_s1 - reg reg_b_s1 : UInt<54>, clk, UInt<1>("h00"), reg_b_s1 - reg reg_a_s2 : UInt<54>, clk, UInt<1>("h00"), reg_a_s2 - reg reg_b_s2 : UInt<54>, clk, UInt<1>("h00"), reg_b_s2 - reg reg_result_s3 : UInt<105>, clk, UInt<1>("h00"), reg_result_s3 + io is invalid + reg val_s1 : UInt<1>, clk + reg val_s2 : UInt<1>, clk + reg reg_a_s1 : UInt<54>, clk + reg reg_b_s1 : UInt<54>, clk + reg reg_a_s2 : UInt<54>, clk + reg reg_b_s2 : UInt<54>, clk + reg reg_result_s3 : UInt<105>, clk val_s1 <= io.val_s0 val_s2 <= val_s1 when io.val_s0 : @@ -39379,8 +31422,9 @@ circuit Top : when val_s2 : node T_25 = mul(reg_a_s2, reg_b_s2) node T_26 = bits(T_25, 104, 0) - node T_27 = addw(T_26, io.c_s2) - reg_result_s3 <= T_27 + node T_27 = add(T_26, io.c_s2) + node T_28 = tail(T_27, 1) + reg_result_s3 <= T_28 skip io.result_s3 <= reg_result_s3 @@ -39389,19 +31433,9 @@ circuit Top : input reset : UInt<1> output io : {inReady_div : UInt<1>, inReady_sqrt : UInt<1>, flip inValid : UInt<1>, flip sqrtOp : UInt<1>, flip a : UInt<65>, flip b : UInt<65>, flip roundingMode : UInt<2>, outValid_div : UInt<1>, outValid_sqrt : UInt<1>, out : UInt<65>, exceptionFlags : UInt<5>} - io.exceptionFlags <= UInt<1>("h00") - io.out <= UInt<1>("h00") - io.outValid_sqrt <= UInt<1>("h00") - io.outValid_div <= UInt<1>("h00") - io.inReady_sqrt <= UInt<1>("h00") - io.inReady_div <= UInt<1>("h00") + io is invalid inst ds of DivSqrtRecF64_mulAddZ31 - ds.io.mulAddResult_3 <= UInt<1>("h00") - ds.io.roundingMode <= UInt<1>("h00") - ds.io.b <= UInt<1>("h00") - ds.io.a <= UInt<1>("h00") - ds.io.sqrtOp <= UInt<1>("h00") - ds.io.inValid <= UInt<1>("h00") + ds.io is invalid ds.clk <= clk ds.reset <= reset io.inReady_div <= ds.io.inReady_div @@ -39416,16 +31450,11 @@ circuit Top : io.out <= ds.io.out io.exceptionFlags <= ds.io.exceptionFlags inst mul of Mul54 - mul.io.c_s2 <= UInt<1>("h00") - mul.io.b_s0 <= UInt<1>("h00") - mul.io.latch_b_s0 <= UInt<1>("h00") - mul.io.a_s0 <= UInt<1>("h00") - mul.io.latch_a_s0 <= UInt<1>("h00") - mul.io.val_s0 <= UInt<1>("h00") + mul.io is invalid mul.clk <= clk mul.reset <= reset - node T_29 = bit(ds.io.usingMulAdd, 0) - mul.io.val_s0 <= T_29 + node T_17 = bits(ds.io.usingMulAdd, 0, 0) + mul.io.val_s0 <= T_17 mul.io.latch_a_s0 <= ds.io.latchMulAddA_0 mul.io.a_s0 <= ds.io.mulAddA_0 mul.io.latch_b_s0 <= ds.io.latchMulAddB_0 @@ -39438,41 +31467,11 @@ circuit Top : input reset : UInt<1> output io : {flip inst : UInt<32>, flip fromint_data : UInt<64>, flip fcsr_rm : UInt<3>, fcsr_flags : {valid : UInt<1>, bits : UInt<5>}, store_data : UInt<64>, toint_data : UInt<64>, flip dmem_resp_val : UInt<1>, flip dmem_resp_type : UInt<3>, flip dmem_resp_tag : UInt<5>, flip dmem_resp_data : UInt<64>, flip valid : UInt<1>, fcsr_rdy : UInt<1>, nack_mem : UInt<1>, illegal_rm : UInt<1>, flip killx : UInt<1>, flip killm : UInt<1>, dec : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, sboard_set : UInt<1>, sboard_clr : UInt<1>, sboard_clra : UInt<5>, flip cp_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>}}, cp_resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<65>, exc : UInt<5>}}} - io.cp_resp.bits.exc <= UInt<1>("h00") - io.cp_resp.bits.data <= UInt<1>("h00") - io.cp_resp.valid <= UInt<1>("h00") - io.cp_req.ready <= UInt<1>("h00") - io.sboard_clra <= UInt<1>("h00") - io.sboard_clr <= UInt<1>("h00") - io.sboard_set <= UInt<1>("h00") - io.dec.wflags <= UInt<1>("h00") - io.dec.round <= UInt<1>("h00") - io.dec.sqrt <= UInt<1>("h00") - io.dec.div <= UInt<1>("h00") - io.dec.fma <= UInt<1>("h00") - io.dec.fastpipe <= UInt<1>("h00") - io.dec.toint <= UInt<1>("h00") - io.dec.fromint <= UInt<1>("h00") - io.dec.single <= UInt<1>("h00") - io.dec.swap23 <= UInt<1>("h00") - io.dec.swap12 <= UInt<1>("h00") - io.dec.ren3 <= UInt<1>("h00") - io.dec.ren2 <= UInt<1>("h00") - io.dec.ren1 <= UInt<1>("h00") - io.dec.wen <= UInt<1>("h00") - io.dec.ldst <= UInt<1>("h00") - io.dec.cmd <= UInt<1>("h00") - io.illegal_rm <= UInt<1>("h00") - io.nack_mem <= UInt<1>("h00") - io.fcsr_rdy <= UInt<1>("h00") - io.toint_data <= UInt<1>("h00") - io.store_data <= UInt<1>("h00") - io.fcsr_flags.bits <= UInt<1>("h00") - io.fcsr_flags.valid <= UInt<1>("h00") - reg ex_reg_valid : UInt<1>, clk, reset, UInt<1>("h00") + io is invalid + reg ex_reg_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) ex_reg_valid <= io.valid node req_valid = or(ex_reg_valid, io.cp_req.valid) - reg ex_reg_inst : UInt<32>, clk, UInt<1>("h00"), ex_reg_inst + reg ex_reg_inst : UInt<32>, clk when io.valid : ex_reg_inst <= io.inst skip @@ -39481,13 +31480,13 @@ circuit Top : node T_205 = eq(io.killx, UInt<1>("h00")) node T_206 = and(ex_reg_valid, T_205) node T_207 = or(T_206, ex_cp_valid) - reg mem_reg_valid : UInt<1>, clk, reset, UInt<1>("h00") + reg mem_reg_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) mem_reg_valid <= T_207 - reg mem_reg_inst : UInt<32>, clk, UInt<1>("h00"), mem_reg_inst + reg mem_reg_inst : UInt<32>, clk when ex_reg_valid : mem_reg_inst <= ex_reg_inst skip - reg mem_cp_valid : UInt<1>, clk, reset, UInt<1>("h00") + reg mem_cp_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) mem_cp_valid <= ex_cp_valid node T_213 = or(io.killm, io.nack_mem) node T_215 = eq(mem_cp_valid, UInt<1>("h00")) @@ -39495,1215 +31494,682 @@ circuit Top : node T_218 = eq(killm, UInt<1>("h00")) node T_219 = or(T_218, mem_cp_valid) node T_220 = and(mem_reg_valid, T_219) - reg wb_reg_valid : UInt<1>, clk, reset, UInt<1>("h00") + reg wb_reg_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) wb_reg_valid <= T_220 - reg wb_cp_valid : UInt<1>, clk, reset, UInt<1>("h00") + reg wb_cp_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) wb_cp_valid <= mem_cp_valid inst fp_decoder of FPUDecoder - fp_decoder.io.inst <= UInt<1>("h00") + fp_decoder.io is invalid fp_decoder.clk <= clk fp_decoder.reset <= reset fp_decoder.io.inst <= io.inst wire cp_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>} - cp_ctrl.wflags <= UInt<1>("h00") - cp_ctrl.round <= UInt<1>("h00") - cp_ctrl.sqrt <= UInt<1>("h00") - cp_ctrl.div <= UInt<1>("h00") - cp_ctrl.fma <= UInt<1>("h00") - cp_ctrl.fastpipe <= UInt<1>("h00") - cp_ctrl.toint <= UInt<1>("h00") - cp_ctrl.fromint <= UInt<1>("h00") - cp_ctrl.single <= UInt<1>("h00") - cp_ctrl.swap23 <= UInt<1>("h00") - cp_ctrl.swap12 <= UInt<1>("h00") - cp_ctrl.ren3 <= UInt<1>("h00") - cp_ctrl.ren2 <= UInt<1>("h00") - cp_ctrl.ren1 <= UInt<1>("h00") - cp_ctrl.wen <= UInt<1>("h00") - cp_ctrl.ldst <= UInt<1>("h00") - cp_ctrl.cmd <= UInt<1>("h00") + cp_ctrl is invalid cp_ctrl <- io.cp_req.bits io.cp_resp.valid <= UInt<1>("h00") io.cp_resp.bits.data <= UInt<1>("h00") - reg T_282 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk, UInt<1>("h00"), T_282 + reg T_264 : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk when io.valid : - T_282 <- fp_decoder.io.sigs - skip - wire ex_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>} - ex_ctrl <- cp_ctrl - when ex_reg_valid : - ex_ctrl <- T_282 + T_264 <- fp_decoder.io.sigs skip - reg mem_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk, UInt<1>("h00"), mem_ctrl + node ex_ctrl = mux(ex_reg_valid, T_264, cp_ctrl) + reg mem_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk when req_valid : mem_ctrl <- ex_ctrl skip - reg wb_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk, UInt<1>("h00"), wb_ctrl + reg wb_ctrl : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>}, clk when mem_reg_valid : wb_ctrl <- mem_ctrl skip - reg load_wb : UInt<1>, clk, UInt<1>("h00"), load_wb + reg load_wb : UInt<1>, clk load_wb <= io.dmem_resp_val - node T_373 = eq(io.dmem_resp_type, UInt<3>("h02")) - node T_374 = eq(io.dmem_resp_type, UInt<3>("h06")) - node T_375 = or(T_373, T_374) - reg load_wb_single : UInt<1>, clk, UInt<1>("h00"), load_wb_single + node T_337 = eq(io.dmem_resp_type, UInt<3>("h02")) + node T_338 = eq(io.dmem_resp_type, UInt<3>("h06")) + node T_339 = or(T_337, T_338) + reg load_wb_single : UInt<1>, clk when io.dmem_resp_val : - load_wb_single <= T_375 + load_wb_single <= T_339 skip - reg load_wb_data : UInt<64>, clk, UInt<1>("h00"), load_wb_data + reg load_wb_data : UInt<64>, clk when io.dmem_resp_val : load_wb_data <= io.dmem_resp_data skip - reg load_wb_tag : UInt<5>, clk, UInt<1>("h00"), load_wb_tag + reg load_wb_tag : UInt<5>, clk when io.dmem_resp_val : load_wb_tag <= io.dmem_resp_tag skip - node T_379 = bit(load_wb_data, 31) - node T_380 = bits(load_wb_data, 30, 23) - node T_381 = bits(load_wb_data, 22, 0) - node T_383 = eq(T_380, UInt<1>("h00")) - node T_385 = eq(T_381, UInt<1>("h00")) - node T_386 = and(T_383, T_385) - node T_387 = shl(T_381, 9) - node T_388 = bit(T_387, 31) - node T_390 = bit(T_387, 30) - node T_392 = bit(T_387, 29) - node T_394 = bit(T_387, 28) - node T_396 = bit(T_387, 27) - node T_398 = bit(T_387, 26) - node T_400 = bit(T_387, 25) - node T_402 = bit(T_387, 24) - node T_404 = bit(T_387, 23) - node T_406 = bit(T_387, 22) - node T_408 = bit(T_387, 21) - node T_410 = bit(T_387, 20) - node T_412 = bit(T_387, 19) - node T_414 = bit(T_387, 18) - node T_416 = bit(T_387, 17) - node T_418 = bit(T_387, 16) - node T_420 = bit(T_387, 15) - node T_422 = bit(T_387, 14) - node T_424 = bit(T_387, 13) - node T_426 = bit(T_387, 12) - node T_428 = bit(T_387, 11) - node T_430 = bit(T_387, 10) - node T_432 = bit(T_387, 9) - node T_434 = bit(T_387, 8) - node T_436 = bit(T_387, 7) - node T_438 = bit(T_387, 6) - node T_440 = bit(T_387, 5) - node T_442 = bit(T_387, 4) - node T_444 = bit(T_387, 3) - node T_446 = bit(T_387, 2) - node T_448 = bit(T_387, 1) - node T_449 = shl(T_448, 0) - node T_450 = mux(T_446, UInt<2>("h02"), T_449) - node T_451 = mux(T_444, UInt<2>("h03"), T_450) - node T_452 = mux(T_442, UInt<3>("h04"), T_451) - node T_453 = mux(T_440, UInt<3>("h05"), T_452) - node T_454 = mux(T_438, UInt<3>("h06"), T_453) - node T_455 = mux(T_436, UInt<3>("h07"), T_454) - node T_456 = mux(T_434, UInt<4>("h08"), T_455) - node T_457 = mux(T_432, UInt<4>("h09"), T_456) - node T_458 = mux(T_430, UInt<4>("h0a"), T_457) - node T_459 = mux(T_428, UInt<4>("h0b"), T_458) - node T_460 = mux(T_426, UInt<4>("h0c"), T_459) - node T_461 = mux(T_424, UInt<4>("h0d"), T_460) - node T_462 = mux(T_422, UInt<4>("h0e"), T_461) - node T_463 = mux(T_420, UInt<4>("h0f"), T_462) - node T_464 = mux(T_418, UInt<5>("h010"), T_463) - node T_465 = mux(T_416, UInt<5>("h011"), T_464) - node T_466 = mux(T_414, UInt<5>("h012"), T_465) - node T_467 = mux(T_412, UInt<5>("h013"), T_466) - node T_468 = mux(T_410, UInt<5>("h014"), T_467) - node T_469 = mux(T_408, UInt<5>("h015"), T_468) - node T_470 = mux(T_406, UInt<5>("h016"), T_469) - node T_471 = mux(T_404, UInt<5>("h017"), T_470) - node T_472 = mux(T_402, UInt<5>("h018"), T_471) - node T_473 = mux(T_400, UInt<5>("h019"), T_472) - node T_474 = mux(T_398, UInt<5>("h01a"), T_473) - node T_475 = mux(T_396, UInt<5>("h01b"), T_474) - node T_476 = mux(T_394, UInt<5>("h01c"), T_475) - node T_477 = mux(T_392, UInt<5>("h01d"), T_476) - node T_478 = mux(T_390, UInt<5>("h01e"), T_477) - node T_479 = mux(T_388, UInt<5>("h01f"), T_478) - node T_480 = not(T_479) - node T_481 = dshl(T_381, T_480) - node T_482 = bits(T_481, 21, 0) - node T_484 = cat(T_482, UInt<1>("h00")) - node T_487 = subw(UInt<9>("h00"), UInt<1>("h01")) - node T_488 = xor(T_480, T_487) - node T_489 = mux(T_383, T_488, T_380) - node T_493 = mux(T_383, UInt<2>("h02"), UInt<1>("h01")) - node T_494 = or(UInt<8>("h080"), T_493) - node T_495 = addw(T_489, T_494) - node T_496 = bits(T_495, 8, 7) - node T_498 = eq(T_496, UInt<2>("h03")) - node T_500 = eq(T_385, UInt<1>("h00")) - node T_501 = and(T_498, T_500) - node T_503 = subw(UInt<3>("h00"), T_386) - node T_504 = shl(T_503, 6) - node T_505 = not(T_504) - node T_506 = and(T_495, T_505) - node T_507 = shl(T_501, 6) - node T_508 = or(T_506, T_507) - node T_509 = mux(T_383, T_484, T_381) - node T_510 = cat(T_508, T_509) - node rec_s = cat(T_379, T_510) - node T_512 = bit(load_wb_data, 63) - node T_513 = bits(load_wb_data, 62, 52) - node T_514 = bits(load_wb_data, 51, 0) - node T_516 = eq(T_513, UInt<1>("h00")) - node T_518 = eq(T_514, UInt<1>("h00")) - node T_519 = and(T_516, T_518) - node T_520 = shl(T_514, 12) - node T_521 = bit(T_520, 63) - node T_523 = bit(T_520, 62) - node T_525 = bit(T_520, 61) - node T_527 = bit(T_520, 60) - node T_529 = bit(T_520, 59) - node T_531 = bit(T_520, 58) - node T_533 = bit(T_520, 57) - node T_535 = bit(T_520, 56) - node T_537 = bit(T_520, 55) - node T_539 = bit(T_520, 54) - node T_541 = bit(T_520, 53) - node T_543 = bit(T_520, 52) - node T_545 = bit(T_520, 51) - node T_547 = bit(T_520, 50) - node T_549 = bit(T_520, 49) - node T_551 = bit(T_520, 48) - node T_553 = bit(T_520, 47) - node T_555 = bit(T_520, 46) - node T_557 = bit(T_520, 45) - node T_559 = bit(T_520, 44) - node T_561 = bit(T_520, 43) - node T_563 = bit(T_520, 42) - node T_565 = bit(T_520, 41) - node T_567 = bit(T_520, 40) - node T_569 = bit(T_520, 39) - node T_571 = bit(T_520, 38) - node T_573 = bit(T_520, 37) - node T_575 = bit(T_520, 36) - node T_577 = bit(T_520, 35) - node T_579 = bit(T_520, 34) - node T_581 = bit(T_520, 33) - node T_583 = bit(T_520, 32) - node T_585 = bit(T_520, 31) - node T_587 = bit(T_520, 30) - node T_589 = bit(T_520, 29) - node T_591 = bit(T_520, 28) - node T_593 = bit(T_520, 27) - node T_595 = bit(T_520, 26) - node T_597 = bit(T_520, 25) - node T_599 = bit(T_520, 24) - node T_601 = bit(T_520, 23) - node T_603 = bit(T_520, 22) - node T_605 = bit(T_520, 21) - node T_607 = bit(T_520, 20) - node T_609 = bit(T_520, 19) - node T_611 = bit(T_520, 18) - node T_613 = bit(T_520, 17) - node T_615 = bit(T_520, 16) - node T_617 = bit(T_520, 15) - node T_619 = bit(T_520, 14) - node T_621 = bit(T_520, 13) - node T_623 = bit(T_520, 12) - node T_625 = bit(T_520, 11) - node T_627 = bit(T_520, 10) - node T_629 = bit(T_520, 9) - node T_631 = bit(T_520, 8) - node T_633 = bit(T_520, 7) - node T_635 = bit(T_520, 6) - node T_637 = bit(T_520, 5) - node T_639 = bit(T_520, 4) - node T_641 = bit(T_520, 3) - node T_643 = bit(T_520, 2) - node T_645 = bit(T_520, 1) - node T_646 = shl(T_645, 0) - node T_647 = mux(T_643, UInt<2>("h02"), T_646) - node T_648 = mux(T_641, UInt<2>("h03"), T_647) - node T_649 = mux(T_639, UInt<3>("h04"), T_648) - node T_650 = mux(T_637, UInt<3>("h05"), T_649) - node T_651 = mux(T_635, UInt<3>("h06"), T_650) - node T_652 = mux(T_633, UInt<3>("h07"), T_651) - node T_653 = mux(T_631, UInt<4>("h08"), T_652) - node T_654 = mux(T_629, UInt<4>("h09"), T_653) - node T_655 = mux(T_627, UInt<4>("h0a"), T_654) - node T_656 = mux(T_625, UInt<4>("h0b"), T_655) - node T_657 = mux(T_623, UInt<4>("h0c"), T_656) - node T_658 = mux(T_621, UInt<4>("h0d"), T_657) - node T_659 = mux(T_619, UInt<4>("h0e"), T_658) - node T_660 = mux(T_617, UInt<4>("h0f"), T_659) - node T_661 = mux(T_615, UInt<5>("h010"), T_660) - node T_662 = mux(T_613, UInt<5>("h011"), T_661) - node T_663 = mux(T_611, UInt<5>("h012"), T_662) - node T_664 = mux(T_609, UInt<5>("h013"), T_663) - node T_665 = mux(T_607, UInt<5>("h014"), T_664) - node T_666 = mux(T_605, UInt<5>("h015"), T_665) - node T_667 = mux(T_603, UInt<5>("h016"), T_666) - node T_668 = mux(T_601, UInt<5>("h017"), T_667) - node T_669 = mux(T_599, UInt<5>("h018"), T_668) - node T_670 = mux(T_597, UInt<5>("h019"), T_669) - node T_671 = mux(T_595, UInt<5>("h01a"), T_670) - node T_672 = mux(T_593, UInt<5>("h01b"), T_671) - node T_673 = mux(T_591, UInt<5>("h01c"), T_672) - node T_674 = mux(T_589, UInt<5>("h01d"), T_673) - node T_675 = mux(T_587, UInt<5>("h01e"), T_674) - node T_676 = mux(T_585, UInt<5>("h01f"), T_675) - node T_677 = mux(T_583, UInt<6>("h020"), T_676) - node T_678 = mux(T_581, UInt<6>("h021"), T_677) - node T_679 = mux(T_579, UInt<6>("h022"), T_678) - node T_680 = mux(T_577, UInt<6>("h023"), T_679) - node T_681 = mux(T_575, UInt<6>("h024"), T_680) - node T_682 = mux(T_573, UInt<6>("h025"), T_681) - node T_683 = mux(T_571, UInt<6>("h026"), T_682) - node T_684 = mux(T_569, UInt<6>("h027"), T_683) - node T_685 = mux(T_567, UInt<6>("h028"), T_684) - node T_686 = mux(T_565, UInt<6>("h029"), T_685) - node T_687 = mux(T_563, UInt<6>("h02a"), T_686) - node T_688 = mux(T_561, UInt<6>("h02b"), T_687) - node T_689 = mux(T_559, UInt<6>("h02c"), T_688) - node T_690 = mux(T_557, UInt<6>("h02d"), T_689) - node T_691 = mux(T_555, UInt<6>("h02e"), T_690) - node T_692 = mux(T_553, UInt<6>("h02f"), T_691) - node T_693 = mux(T_551, UInt<6>("h030"), T_692) - node T_694 = mux(T_549, UInt<6>("h031"), T_693) - node T_695 = mux(T_547, UInt<6>("h032"), T_694) - node T_696 = mux(T_545, UInt<6>("h033"), T_695) - node T_697 = mux(T_543, UInt<6>("h034"), T_696) - node T_698 = mux(T_541, UInt<6>("h035"), T_697) - node T_699 = mux(T_539, UInt<6>("h036"), T_698) - node T_700 = mux(T_537, UInt<6>("h037"), T_699) - node T_701 = mux(T_535, UInt<6>("h038"), T_700) - node T_702 = mux(T_533, UInt<6>("h039"), T_701) - node T_703 = mux(T_531, UInt<6>("h03a"), T_702) - node T_704 = mux(T_529, UInt<6>("h03b"), T_703) - node T_705 = mux(T_527, UInt<6>("h03c"), T_704) - node T_706 = mux(T_525, UInt<6>("h03d"), T_705) - node T_707 = mux(T_523, UInt<6>("h03e"), T_706) - node T_708 = mux(T_521, UInt<6>("h03f"), T_707) - node T_709 = not(T_708) - node T_710 = dshl(T_514, T_709) - node T_711 = bits(T_710, 50, 0) - node T_713 = cat(T_711, UInt<1>("h00")) - node T_716 = subw(UInt<12>("h00"), UInt<1>("h01")) - node T_717 = xor(T_709, T_716) - node T_718 = mux(T_516, T_717, T_513) - node T_722 = mux(T_516, UInt<2>("h02"), UInt<1>("h01")) - node T_723 = or(UInt<11>("h0400"), T_722) - node T_724 = addw(T_718, T_723) - node T_725 = bits(T_724, 11, 10) - node T_727 = eq(T_725, UInt<2>("h03")) - node T_729 = eq(T_518, UInt<1>("h00")) - node T_730 = and(T_727, T_729) - node T_732 = subw(UInt<3>("h00"), T_519) - node T_733 = shl(T_732, 9) - node T_734 = not(T_733) - node T_735 = and(T_724, T_734) - node T_736 = shl(T_730, 9) - node T_737 = or(T_735, T_736) - node T_738 = mux(T_516, T_713, T_514) - node T_739 = cat(T_737, T_738) - node rec_d = cat(T_512, T_739) - node T_742 = asUInt(asSInt(UInt<32>("h0ffffffff"))) - node T_743 = cat(T_742, rec_s) - node load_wb_data_recoded = mux(load_wb_single, T_743, rec_d) + node T_343 = bits(load_wb_data, 31, 31) + node T_344 = bits(load_wb_data, 30, 23) + node T_345 = bits(load_wb_data, 22, 0) + node T_347 = eq(T_344, UInt<1>("h00")) + node T_349 = eq(T_345, UInt<1>("h00")) + node T_350 = and(T_347, T_349) + node T_351 = shl(T_345, 9) + node T_352 = bits(T_351, 31, 31) + node T_354 = bits(T_351, 30, 30) + node T_356 = bits(T_351, 29, 29) + node T_358 = bits(T_351, 28, 28) + node T_360 = bits(T_351, 27, 27) + node T_362 = bits(T_351, 26, 26) + node T_364 = bits(T_351, 25, 25) + node T_366 = bits(T_351, 24, 24) + node T_368 = bits(T_351, 23, 23) + node T_370 = bits(T_351, 22, 22) + node T_372 = bits(T_351, 21, 21) + node T_374 = bits(T_351, 20, 20) + node T_376 = bits(T_351, 19, 19) + node T_378 = bits(T_351, 18, 18) + node T_380 = bits(T_351, 17, 17) + node T_382 = bits(T_351, 16, 16) + node T_384 = bits(T_351, 15, 15) + node T_386 = bits(T_351, 14, 14) + node T_388 = bits(T_351, 13, 13) + node T_390 = bits(T_351, 12, 12) + node T_392 = bits(T_351, 11, 11) + node T_394 = bits(T_351, 10, 10) + node T_396 = bits(T_351, 9, 9) + node T_398 = bits(T_351, 8, 8) + node T_400 = bits(T_351, 7, 7) + node T_402 = bits(T_351, 6, 6) + node T_404 = bits(T_351, 5, 5) + node T_406 = bits(T_351, 4, 4) + node T_408 = bits(T_351, 3, 3) + node T_410 = bits(T_351, 2, 2) + node T_412 = bits(T_351, 1, 1) + node T_413 = shl(T_412, 0) + node T_414 = mux(T_410, UInt<2>("h02"), T_413) + node T_415 = mux(T_408, UInt<2>("h03"), T_414) + node T_416 = mux(T_406, UInt<3>("h04"), T_415) + node T_417 = mux(T_404, UInt<3>("h05"), T_416) + node T_418 = mux(T_402, UInt<3>("h06"), T_417) + node T_419 = mux(T_400, UInt<3>("h07"), T_418) + node T_420 = mux(T_398, UInt<4>("h08"), T_419) + node T_421 = mux(T_396, UInt<4>("h09"), T_420) + node T_422 = mux(T_394, UInt<4>("h0a"), T_421) + node T_423 = mux(T_392, UInt<4>("h0b"), T_422) + node T_424 = mux(T_390, UInt<4>("h0c"), T_423) + node T_425 = mux(T_388, UInt<4>("h0d"), T_424) + node T_426 = mux(T_386, UInt<4>("h0e"), T_425) + node T_427 = mux(T_384, UInt<4>("h0f"), T_426) + node T_428 = mux(T_382, UInt<5>("h010"), T_427) + node T_429 = mux(T_380, UInt<5>("h011"), T_428) + node T_430 = mux(T_378, UInt<5>("h012"), T_429) + node T_431 = mux(T_376, UInt<5>("h013"), T_430) + node T_432 = mux(T_374, UInt<5>("h014"), T_431) + node T_433 = mux(T_372, UInt<5>("h015"), T_432) + node T_434 = mux(T_370, UInt<5>("h016"), T_433) + node T_435 = mux(T_368, UInt<5>("h017"), T_434) + node T_436 = mux(T_366, UInt<5>("h018"), T_435) + node T_437 = mux(T_364, UInt<5>("h019"), T_436) + node T_438 = mux(T_362, UInt<5>("h01a"), T_437) + node T_439 = mux(T_360, UInt<5>("h01b"), T_438) + node T_440 = mux(T_358, UInt<5>("h01c"), T_439) + node T_441 = mux(T_356, UInt<5>("h01d"), T_440) + node T_442 = mux(T_354, UInt<5>("h01e"), T_441) + node T_443 = mux(T_352, UInt<5>("h01f"), T_442) + node T_444 = not(T_443) + node T_445 = dshl(T_345, T_444) + node T_446 = bits(T_445, 21, 0) + node T_448 = cat(T_446, UInt<1>("h00")) + node T_451 = sub(UInt<9>("h00"), UInt<1>("h01")) + node T_452 = tail(T_451, 1) + node T_453 = xor(T_444, T_452) + node T_454 = mux(T_347, T_453, T_344) + node T_458 = mux(T_347, UInt<2>("h02"), UInt<1>("h01")) + node T_459 = or(UInt<8>("h080"), T_458) + node T_460 = add(T_454, T_459) + node T_461 = tail(T_460, 1) + node T_462 = bits(T_461, 8, 7) + node T_464 = eq(T_462, UInt<2>("h03")) + node T_466 = eq(T_349, UInt<1>("h00")) + node T_467 = and(T_464, T_466) + node T_469 = sub(UInt<3>("h00"), T_350) + node T_470 = tail(T_469, 1) + node T_471 = shl(T_470, 6) + node T_472 = not(T_471) + node T_473 = and(T_461, T_472) + node T_474 = shl(T_467, 6) + node T_475 = or(T_473, T_474) + node T_476 = mux(T_347, T_448, T_345) + node T_477 = cat(T_475, T_476) + node rec_s = cat(T_343, T_477) + node T_479 = bits(load_wb_data, 63, 63) + node T_480 = bits(load_wb_data, 62, 52) + node T_481 = bits(load_wb_data, 51, 0) + node T_483 = eq(T_480, UInt<1>("h00")) + node T_485 = eq(T_481, UInt<1>("h00")) + node T_486 = and(T_483, T_485) + node T_487 = shl(T_481, 12) + node T_488 = bits(T_487, 63, 63) + node T_490 = bits(T_487, 62, 62) + node T_492 = bits(T_487, 61, 61) + node T_494 = bits(T_487, 60, 60) + node T_496 = bits(T_487, 59, 59) + node T_498 = bits(T_487, 58, 58) + node T_500 = bits(T_487, 57, 57) + node T_502 = bits(T_487, 56, 56) + node T_504 = bits(T_487, 55, 55) + node T_506 = bits(T_487, 54, 54) + node T_508 = bits(T_487, 53, 53) + node T_510 = bits(T_487, 52, 52) + node T_512 = bits(T_487, 51, 51) + node T_514 = bits(T_487, 50, 50) + node T_516 = bits(T_487, 49, 49) + node T_518 = bits(T_487, 48, 48) + node T_520 = bits(T_487, 47, 47) + node T_522 = bits(T_487, 46, 46) + node T_524 = bits(T_487, 45, 45) + node T_526 = bits(T_487, 44, 44) + node T_528 = bits(T_487, 43, 43) + node T_530 = bits(T_487, 42, 42) + node T_532 = bits(T_487, 41, 41) + node T_534 = bits(T_487, 40, 40) + node T_536 = bits(T_487, 39, 39) + node T_538 = bits(T_487, 38, 38) + node T_540 = bits(T_487, 37, 37) + node T_542 = bits(T_487, 36, 36) + node T_544 = bits(T_487, 35, 35) + node T_546 = bits(T_487, 34, 34) + node T_548 = bits(T_487, 33, 33) + node T_550 = bits(T_487, 32, 32) + node T_552 = bits(T_487, 31, 31) + node T_554 = bits(T_487, 30, 30) + node T_556 = bits(T_487, 29, 29) + node T_558 = bits(T_487, 28, 28) + node T_560 = bits(T_487, 27, 27) + node T_562 = bits(T_487, 26, 26) + node T_564 = bits(T_487, 25, 25) + node T_566 = bits(T_487, 24, 24) + node T_568 = bits(T_487, 23, 23) + node T_570 = bits(T_487, 22, 22) + node T_572 = bits(T_487, 21, 21) + node T_574 = bits(T_487, 20, 20) + node T_576 = bits(T_487, 19, 19) + node T_578 = bits(T_487, 18, 18) + node T_580 = bits(T_487, 17, 17) + node T_582 = bits(T_487, 16, 16) + node T_584 = bits(T_487, 15, 15) + node T_586 = bits(T_487, 14, 14) + node T_588 = bits(T_487, 13, 13) + node T_590 = bits(T_487, 12, 12) + node T_592 = bits(T_487, 11, 11) + node T_594 = bits(T_487, 10, 10) + node T_596 = bits(T_487, 9, 9) + node T_598 = bits(T_487, 8, 8) + node T_600 = bits(T_487, 7, 7) + node T_602 = bits(T_487, 6, 6) + node T_604 = bits(T_487, 5, 5) + node T_606 = bits(T_487, 4, 4) + node T_608 = bits(T_487, 3, 3) + node T_610 = bits(T_487, 2, 2) + node T_612 = bits(T_487, 1, 1) + node T_613 = shl(T_612, 0) + node T_614 = mux(T_610, UInt<2>("h02"), T_613) + node T_615 = mux(T_608, UInt<2>("h03"), T_614) + node T_616 = mux(T_606, UInt<3>("h04"), T_615) + node T_617 = mux(T_604, UInt<3>("h05"), T_616) + node T_618 = mux(T_602, UInt<3>("h06"), T_617) + node T_619 = mux(T_600, UInt<3>("h07"), T_618) + node T_620 = mux(T_598, UInt<4>("h08"), T_619) + node T_621 = mux(T_596, UInt<4>("h09"), T_620) + node T_622 = mux(T_594, UInt<4>("h0a"), T_621) + node T_623 = mux(T_592, UInt<4>("h0b"), T_622) + node T_624 = mux(T_590, UInt<4>("h0c"), T_623) + node T_625 = mux(T_588, UInt<4>("h0d"), T_624) + node T_626 = mux(T_586, UInt<4>("h0e"), T_625) + node T_627 = mux(T_584, UInt<4>("h0f"), T_626) + node T_628 = mux(T_582, UInt<5>("h010"), T_627) + node T_629 = mux(T_580, UInt<5>("h011"), T_628) + node T_630 = mux(T_578, UInt<5>("h012"), T_629) + node T_631 = mux(T_576, UInt<5>("h013"), T_630) + node T_632 = mux(T_574, UInt<5>("h014"), T_631) + node T_633 = mux(T_572, UInt<5>("h015"), T_632) + node T_634 = mux(T_570, UInt<5>("h016"), T_633) + node T_635 = mux(T_568, UInt<5>("h017"), T_634) + node T_636 = mux(T_566, UInt<5>("h018"), T_635) + node T_637 = mux(T_564, UInt<5>("h019"), T_636) + node T_638 = mux(T_562, UInt<5>("h01a"), T_637) + node T_639 = mux(T_560, UInt<5>("h01b"), T_638) + node T_640 = mux(T_558, UInt<5>("h01c"), T_639) + node T_641 = mux(T_556, UInt<5>("h01d"), T_640) + node T_642 = mux(T_554, UInt<5>("h01e"), T_641) + node T_643 = mux(T_552, UInt<5>("h01f"), T_642) + node T_644 = mux(T_550, UInt<6>("h020"), T_643) + node T_645 = mux(T_548, UInt<6>("h021"), T_644) + node T_646 = mux(T_546, UInt<6>("h022"), T_645) + node T_647 = mux(T_544, UInt<6>("h023"), T_646) + node T_648 = mux(T_542, UInt<6>("h024"), T_647) + node T_649 = mux(T_540, UInt<6>("h025"), T_648) + node T_650 = mux(T_538, UInt<6>("h026"), T_649) + node T_651 = mux(T_536, UInt<6>("h027"), T_650) + node T_652 = mux(T_534, UInt<6>("h028"), T_651) + node T_653 = mux(T_532, UInt<6>("h029"), T_652) + node T_654 = mux(T_530, UInt<6>("h02a"), T_653) + node T_655 = mux(T_528, UInt<6>("h02b"), T_654) + node T_656 = mux(T_526, UInt<6>("h02c"), T_655) + node T_657 = mux(T_524, UInt<6>("h02d"), T_656) + node T_658 = mux(T_522, UInt<6>("h02e"), T_657) + node T_659 = mux(T_520, UInt<6>("h02f"), T_658) + node T_660 = mux(T_518, UInt<6>("h030"), T_659) + node T_661 = mux(T_516, UInt<6>("h031"), T_660) + node T_662 = mux(T_514, UInt<6>("h032"), T_661) + node T_663 = mux(T_512, UInt<6>("h033"), T_662) + node T_664 = mux(T_510, UInt<6>("h034"), T_663) + node T_665 = mux(T_508, UInt<6>("h035"), T_664) + node T_666 = mux(T_506, UInt<6>("h036"), T_665) + node T_667 = mux(T_504, UInt<6>("h037"), T_666) + node T_668 = mux(T_502, UInt<6>("h038"), T_667) + node T_669 = mux(T_500, UInt<6>("h039"), T_668) + node T_670 = mux(T_498, UInt<6>("h03a"), T_669) + node T_671 = mux(T_496, UInt<6>("h03b"), T_670) + node T_672 = mux(T_494, UInt<6>("h03c"), T_671) + node T_673 = mux(T_492, UInt<6>("h03d"), T_672) + node T_674 = mux(T_490, UInt<6>("h03e"), T_673) + node T_675 = mux(T_488, UInt<6>("h03f"), T_674) + node T_676 = not(T_675) + node T_677 = dshl(T_481, T_676) + node T_678 = bits(T_677, 50, 0) + node T_680 = cat(T_678, UInt<1>("h00")) + node T_683 = sub(UInt<12>("h00"), UInt<1>("h01")) + node T_684 = tail(T_683, 1) + node T_685 = xor(T_676, T_684) + node T_686 = mux(T_483, T_685, T_480) + node T_690 = mux(T_483, UInt<2>("h02"), UInt<1>("h01")) + node T_691 = or(UInt<11>("h0400"), T_690) + node T_692 = add(T_686, T_691) + node T_693 = tail(T_692, 1) + node T_694 = bits(T_693, 11, 10) + node T_696 = eq(T_694, UInt<2>("h03")) + node T_698 = eq(T_485, UInt<1>("h00")) + node T_699 = and(T_696, T_698) + node T_701 = sub(UInt<3>("h00"), T_486) + node T_702 = tail(T_701, 1) + node T_703 = shl(T_702, 9) + node T_704 = not(T_703) + node T_705 = and(T_693, T_704) + node T_706 = shl(T_699, 9) + node T_707 = or(T_705, T_706) + node T_708 = mux(T_483, T_680, T_481) + node T_709 = cat(T_707, T_708) + node rec_d = cat(T_479, T_709) + node T_712 = asUInt(asSInt(UInt<32>("h0ffffffff"))) + node T_713 = cat(T_712, rec_s) + node load_wb_data_recoded = mux(load_wb_single, T_713, rec_d) cmem regfile : UInt<65>[32] when load_wb : - infer mport T_748 = regfile[load_wb_tag], clk - T_748 <= load_wb_data_recoded + infer mport T_718 = regfile[load_wb_tag], clk + T_718 <= load_wb_data_recoded skip - reg ex_ra1 : UInt<?>, clk, UInt<1>("h00"), ex_ra1 - reg ex_ra2 : UInt<?>, clk, UInt<1>("h00"), ex_ra2 - reg ex_ra3 : UInt<?>, clk, UInt<1>("h00"), ex_ra3 + reg ex_ra1 : UInt<?>, clk + reg ex_ra2 : UInt<?>, clk + reg ex_ra3 : UInt<?>, clk when io.valid : when fp_decoder.io.sigs.ren1 : - node T_756 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) - when T_756 : - node T_757 = bits(io.inst, 19, 15) - ex_ra1 <= T_757 + node T_726 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) + when T_726 : + node T_727 = bits(io.inst, 19, 15) + ex_ra1 <= T_727 skip when fp_decoder.io.sigs.swap12 : - node T_758 = bits(io.inst, 19, 15) - ex_ra2 <= T_758 + node T_728 = bits(io.inst, 19, 15) + ex_ra2 <= T_728 skip skip when fp_decoder.io.sigs.ren2 : when fp_decoder.io.sigs.swap12 : - node T_759 = bits(io.inst, 24, 20) - ex_ra1 <= T_759 + node T_729 = bits(io.inst, 24, 20) + ex_ra1 <= T_729 skip when fp_decoder.io.sigs.swap23 : - node T_760 = bits(io.inst, 24, 20) - ex_ra3 <= T_760 + node T_730 = bits(io.inst, 24, 20) + ex_ra3 <= T_730 skip - node T_762 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) - node T_764 = eq(fp_decoder.io.sigs.swap23, UInt<1>("h00")) - node T_765 = and(T_762, T_764) - when T_765 : - node T_766 = bits(io.inst, 24, 20) - ex_ra2 <= T_766 + node T_732 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00")) + node T_734 = eq(fp_decoder.io.sigs.swap23, UInt<1>("h00")) + node T_735 = and(T_732, T_734) + when T_735 : + node T_736 = bits(io.inst, 24, 20) + ex_ra2 <= T_736 skip skip when fp_decoder.io.sigs.ren3 : - node T_767 = bits(io.inst, 31, 27) - ex_ra3 <= T_767 + node T_737 = bits(io.inst, 31, 27) + ex_ra3 <= T_737 skip skip infer mport ex_rs1 = regfile[ex_ra1], clk infer mport ex_rs2 = regfile[ex_ra2], clk infer mport ex_rs3 = regfile[ex_ra3], clk - node T_771 = bits(ex_reg_inst, 14, 12) - node T_773 = eq(T_771, UInt<3>("h07")) - node T_774 = bits(ex_reg_inst, 14, 12) - node ex_rm = mux(T_773, io.fcsr_rm, T_774) + node T_741 = bits(ex_reg_inst, 14, 12) + node T_743 = eq(T_741, UInt<3>("h07")) + node T_744 = bits(ex_reg_inst, 14, 12) + node ex_rm = mux(T_743, io.fcsr_rm, T_744) node cp_rs2 = mux(io.cp_req.bits.swap23, io.cp_req.bits.in3, io.cp_req.bits.in2) node cp_rs3 = mux(io.cp_req.bits.swap23, io.cp_req.bits.in2, io.cp_req.bits.in3) wire req : {cmd : UInt<5>, ldst : UInt<1>, wen : UInt<1>, ren1 : UInt<1>, ren2 : UInt<1>, ren3 : UInt<1>, swap12 : UInt<1>, swap23 : UInt<1>, single : UInt<1>, fromint : UInt<1>, toint : UInt<1>, fastpipe : UInt<1>, fma : UInt<1>, div : UInt<1>, sqrt : UInt<1>, round : UInt<1>, wflags : UInt<1>, rm : UInt<3>, typ : UInt<2>, in1 : UInt<65>, in2 : UInt<65>, in3 : UInt<65>} - req.in3 <= UInt<1>("h00") - req.in2 <= UInt<1>("h00") - req.in1 <= UInt<1>("h00") - req.typ <= UInt<1>("h00") - req.rm <= UInt<1>("h00") - req.wflags <= UInt<1>("h00") - req.round <= UInt<1>("h00") - req.sqrt <= UInt<1>("h00") - req.div <= UInt<1>("h00") - req.fma <= UInt<1>("h00") - req.fastpipe <= UInt<1>("h00") - req.toint <= UInt<1>("h00") - req.fromint <= UInt<1>("h00") - req.single <= UInt<1>("h00") - req.swap23 <= UInt<1>("h00") - req.swap12 <= UInt<1>("h00") - req.ren3 <= UInt<1>("h00") - req.ren2 <= UInt<1>("h00") - req.ren1 <= UInt<1>("h00") - req.wen <= UInt<1>("h00") - req.ldst <= UInt<1>("h00") - req.cmd <= UInt<1>("h00") + req is invalid req <- ex_ctrl - node T_846 = mux(ex_reg_valid, ex_rm, io.cp_req.bits.rm) - req.rm <= T_846 - node T_847 = mux(ex_reg_valid, ex_rs1, io.cp_req.bits.in1) - req.in1 <= T_847 - node T_848 = mux(ex_reg_valid, ex_rs2, cp_rs2) - req.in2 <= T_848 - node T_849 = mux(ex_reg_valid, ex_rs3, cp_rs3) - req.in3 <= T_849 - node T_850 = bits(ex_reg_inst, 21, 20) - node T_851 = mux(ex_reg_valid, T_850, io.cp_req.bits.typ) - req.typ <= T_851 + node T_794 = mux(ex_reg_valid, ex_rm, io.cp_req.bits.rm) + req.rm <= T_794 + node T_795 = mux(ex_reg_valid, ex_rs1, io.cp_req.bits.in1) + req.in1 <= T_795 + node T_796 = mux(ex_reg_valid, ex_rs2, cp_rs2) + req.in2 <= T_796 + node T_797 = mux(ex_reg_valid, ex_rs3, cp_rs3) + req.in3 <= T_797 + node T_798 = bits(ex_reg_inst, 21, 20) + node T_799 = mux(ex_reg_valid, T_798, io.cp_req.bits.typ) + req.typ <= T_799 inst sfma of FPUFMAPipe - sfma.io.in.bits.in3 <= UInt<1>("h00") - sfma.io.in.bits.in2 <= UInt<1>("h00") - sfma.io.in.bits.in1 <= UInt<1>("h00") - sfma.io.in.bits.typ <= UInt<1>("h00") - sfma.io.in.bits.rm <= UInt<1>("h00") - sfma.io.in.bits.wflags <= UInt<1>("h00") - sfma.io.in.bits.round <= UInt<1>("h00") - sfma.io.in.bits.sqrt <= UInt<1>("h00") - sfma.io.in.bits.div <= UInt<1>("h00") - sfma.io.in.bits.fma <= UInt<1>("h00") - sfma.io.in.bits.fastpipe <= UInt<1>("h00") - sfma.io.in.bits.toint <= UInt<1>("h00") - sfma.io.in.bits.fromint <= UInt<1>("h00") - sfma.io.in.bits.single <= UInt<1>("h00") - sfma.io.in.bits.swap23 <= UInt<1>("h00") - sfma.io.in.bits.swap12 <= UInt<1>("h00") - sfma.io.in.bits.ren3 <= UInt<1>("h00") - sfma.io.in.bits.ren2 <= UInt<1>("h00") - sfma.io.in.bits.ren1 <= UInt<1>("h00") - sfma.io.in.bits.wen <= UInt<1>("h00") - sfma.io.in.bits.ldst <= UInt<1>("h00") - sfma.io.in.bits.cmd <= UInt<1>("h00") - sfma.io.in.valid <= UInt<1>("h00") + sfma.io is invalid sfma.clk <= clk sfma.reset <= reset - node T_876 = and(req_valid, ex_ctrl.fma) - node T_877 = and(T_876, ex_ctrl.single) - sfma.io.in.valid <= T_877 + node T_801 = and(req_valid, ex_ctrl.fma) + node T_802 = and(T_801, ex_ctrl.single) + sfma.io.in.valid <= T_802 sfma.io.in.bits <- req inst dfma of FPUFMAPipe_113 - dfma.io.in.bits.in3 <= UInt<1>("h00") - dfma.io.in.bits.in2 <= UInt<1>("h00") - dfma.io.in.bits.in1 <= UInt<1>("h00") - dfma.io.in.bits.typ <= UInt<1>("h00") - dfma.io.in.bits.rm <= UInt<1>("h00") - dfma.io.in.bits.wflags <= UInt<1>("h00") - dfma.io.in.bits.round <= UInt<1>("h00") - dfma.io.in.bits.sqrt <= UInt<1>("h00") - dfma.io.in.bits.div <= UInt<1>("h00") - dfma.io.in.bits.fma <= UInt<1>("h00") - dfma.io.in.bits.fastpipe <= UInt<1>("h00") - dfma.io.in.bits.toint <= UInt<1>("h00") - dfma.io.in.bits.fromint <= UInt<1>("h00") - dfma.io.in.bits.single <= UInt<1>("h00") - dfma.io.in.bits.swap23 <= UInt<1>("h00") - dfma.io.in.bits.swap12 <= UInt<1>("h00") - dfma.io.in.bits.ren3 <= UInt<1>("h00") - dfma.io.in.bits.ren2 <= UInt<1>("h00") - dfma.io.in.bits.ren1 <= UInt<1>("h00") - dfma.io.in.bits.wen <= UInt<1>("h00") - dfma.io.in.bits.ldst <= UInt<1>("h00") - dfma.io.in.bits.cmd <= UInt<1>("h00") - dfma.io.in.valid <= UInt<1>("h00") + dfma.io is invalid dfma.clk <= clk dfma.reset <= reset - node T_902 = and(req_valid, ex_ctrl.fma) - node T_904 = eq(ex_ctrl.single, UInt<1>("h00")) - node T_905 = and(T_902, T_904) - dfma.io.in.valid <= T_905 + node T_804 = and(req_valid, ex_ctrl.fma) + node T_806 = eq(ex_ctrl.single, UInt<1>("h00")) + node T_807 = and(T_804, T_806) + dfma.io.in.valid <= T_807 dfma.io.in.bits <- req inst fpiu of FPToInt - fpiu.io.in.bits.in3 <= UInt<1>("h00") - fpiu.io.in.bits.in2 <= UInt<1>("h00") - fpiu.io.in.bits.in1 <= UInt<1>("h00") - fpiu.io.in.bits.typ <= UInt<1>("h00") - fpiu.io.in.bits.rm <= UInt<1>("h00") - fpiu.io.in.bits.wflags <= UInt<1>("h00") - fpiu.io.in.bits.round <= UInt<1>("h00") - fpiu.io.in.bits.sqrt <= UInt<1>("h00") - fpiu.io.in.bits.div <= UInt<1>("h00") - fpiu.io.in.bits.fma <= UInt<1>("h00") - fpiu.io.in.bits.fastpipe <= UInt<1>("h00") - fpiu.io.in.bits.toint <= UInt<1>("h00") - fpiu.io.in.bits.fromint <= UInt<1>("h00") - fpiu.io.in.bits.single <= UInt<1>("h00") - fpiu.io.in.bits.swap23 <= UInt<1>("h00") - fpiu.io.in.bits.swap12 <= UInt<1>("h00") - fpiu.io.in.bits.ren3 <= UInt<1>("h00") - fpiu.io.in.bits.ren2 <= UInt<1>("h00") - fpiu.io.in.bits.ren1 <= UInt<1>("h00") - fpiu.io.in.bits.wen <= UInt<1>("h00") - fpiu.io.in.bits.ldst <= UInt<1>("h00") - fpiu.io.in.bits.cmd <= UInt<1>("h00") - fpiu.io.in.valid <= UInt<1>("h00") + fpiu.io is invalid fpiu.clk <= clk fpiu.reset <= reset - node T_930 = or(ex_ctrl.toint, ex_ctrl.div) - node T_931 = or(T_930, ex_ctrl.sqrt) - node T_934 = and(ex_ctrl.cmd, UInt<4>("h0d")) - node T_935 = eq(UInt<3>("h05"), T_934) - node T_936 = or(T_931, T_935) - node T_937 = and(req_valid, T_936) - fpiu.io.in.valid <= T_937 + node T_809 = or(ex_ctrl.toint, ex_ctrl.div) + node T_810 = or(T_809, ex_ctrl.sqrt) + node T_813 = and(ex_ctrl.cmd, UInt<4>("h0d")) + node T_814 = eq(UInt<3>("h05"), T_813) + node T_815 = or(T_810, T_814) + node T_816 = and(req_valid, T_815) + fpiu.io.in.valid <= T_816 fpiu.io.in.bits <- req io.store_data <= fpiu.io.out.bits.store io.toint_data <= fpiu.io.out.bits.toint - node T_938 = and(fpiu.io.out.valid, mem_cp_valid) - node T_939 = and(T_938, mem_ctrl.toint) - when T_939 : + node T_817 = and(fpiu.io.out.valid, mem_cp_valid) + node T_818 = and(T_817, mem_ctrl.toint) + when T_818 : io.cp_resp.bits.data <= fpiu.io.out.bits.toint io.cp_resp.valid <= UInt<1>("h01") skip inst ifpu of IntToFP - ifpu.io.in.bits.in3 <= UInt<1>("h00") - ifpu.io.in.bits.in2 <= UInt<1>("h00") - ifpu.io.in.bits.in1 <= UInt<1>("h00") - ifpu.io.in.bits.typ <= UInt<1>("h00") - ifpu.io.in.bits.rm <= UInt<1>("h00") - ifpu.io.in.bits.wflags <= UInt<1>("h00") - ifpu.io.in.bits.round <= UInt<1>("h00") - ifpu.io.in.bits.sqrt <= UInt<1>("h00") - ifpu.io.in.bits.div <= UInt<1>("h00") - ifpu.io.in.bits.fma <= UInt<1>("h00") - ifpu.io.in.bits.fastpipe <= UInt<1>("h00") - ifpu.io.in.bits.toint <= UInt<1>("h00") - ifpu.io.in.bits.fromint <= UInt<1>("h00") - ifpu.io.in.bits.single <= UInt<1>("h00") - ifpu.io.in.bits.swap23 <= UInt<1>("h00") - ifpu.io.in.bits.swap12 <= UInt<1>("h00") - ifpu.io.in.bits.ren3 <= UInt<1>("h00") - ifpu.io.in.bits.ren2 <= UInt<1>("h00") - ifpu.io.in.bits.ren1 <= UInt<1>("h00") - ifpu.io.in.bits.wen <= UInt<1>("h00") - ifpu.io.in.bits.ldst <= UInt<1>("h00") - ifpu.io.in.bits.cmd <= UInt<1>("h00") - ifpu.io.in.valid <= UInt<1>("h00") + ifpu.io is invalid ifpu.clk <= clk ifpu.reset <= reset - node T_965 = and(req_valid, ex_ctrl.fromint) - ifpu.io.in.valid <= T_965 + node T_821 = and(req_valid, ex_ctrl.fromint) + ifpu.io.in.valid <= T_821 ifpu.io.in.bits <- req - node T_966 = mux(ex_reg_valid, io.fromint_data, io.cp_req.bits.in1) - ifpu.io.in.bits.in1 <= T_966 + node T_822 = mux(ex_reg_valid, io.fromint_data, io.cp_req.bits.in1) + ifpu.io.in.bits.in1 <= T_822 inst fpmu of FPToFP - fpmu.io.lt <= UInt<1>("h00") - fpmu.io.in.bits.in3 <= UInt<1>("h00") - fpmu.io.in.bits.in2 <= UInt<1>("h00") - fpmu.io.in.bits.in1 <= UInt<1>("h00") - fpmu.io.in.bits.typ <= UInt<1>("h00") - fpmu.io.in.bits.rm <= UInt<1>("h00") - fpmu.io.in.bits.wflags <= UInt<1>("h00") - fpmu.io.in.bits.round <= UInt<1>("h00") - fpmu.io.in.bits.sqrt <= UInt<1>("h00") - fpmu.io.in.bits.div <= UInt<1>("h00") - fpmu.io.in.bits.fma <= UInt<1>("h00") - fpmu.io.in.bits.fastpipe <= UInt<1>("h00") - fpmu.io.in.bits.toint <= UInt<1>("h00") - fpmu.io.in.bits.fromint <= UInt<1>("h00") - fpmu.io.in.bits.single <= UInt<1>("h00") - fpmu.io.in.bits.swap23 <= UInt<1>("h00") - fpmu.io.in.bits.swap12 <= UInt<1>("h00") - fpmu.io.in.bits.ren3 <= UInt<1>("h00") - fpmu.io.in.bits.ren2 <= UInt<1>("h00") - fpmu.io.in.bits.ren1 <= UInt<1>("h00") - fpmu.io.in.bits.wen <= UInt<1>("h00") - fpmu.io.in.bits.ldst <= UInt<1>("h00") - fpmu.io.in.bits.cmd <= UInt<1>("h00") - fpmu.io.in.valid <= UInt<1>("h00") + fpmu.io is invalid fpmu.clk <= clk fpmu.reset <= reset - node T_992 = and(req_valid, ex_ctrl.fastpipe) - fpmu.io.in.valid <= T_992 + node T_824 = and(req_valid, ex_ctrl.fastpipe) + fpmu.io.in.valid <= T_824 fpmu.io.in.bits <- req fpmu.io.lt <= fpiu.io.out.bits.lt - reg divSqrt_wen : UInt<1>, clk, UInt<1>("h00"), divSqrt_wen + reg divSqrt_wen : UInt<1>, clk divSqrt_wen <= UInt<1>("h00") wire divSqrt_inReady : UInt<1> divSqrt_inReady <= UInt<1>("h00") - reg divSqrt_waddr : UInt<?>, clk, UInt<1>("h00"), divSqrt_waddr + reg divSqrt_waddr : UInt<?>, clk wire divSqrt_wdata : UInt<?> - divSqrt_wdata <= UInt<1>("h00") + divSqrt_wdata is invalid wire divSqrt_flags : UInt<?> - divSqrt_flags <= UInt<1>("h00") - reg divSqrt_in_flight : UInt<1>, clk, reset, UInt<1>("h00") - reg divSqrt_killed : UInt<1>, clk, UInt<1>("h00"), divSqrt_killed - node T_1011 = mux(mem_ctrl.fastpipe, UInt<1>("h01"), UInt<1>("h00")) - node T_1014 = mux(mem_ctrl.fromint, UInt<2>("h02"), UInt<1>("h00")) - node T_1015 = and(mem_ctrl.fma, mem_ctrl.single) - node T_1018 = mux(T_1015, UInt<1>("h01"), UInt<1>("h00")) - node T_1020 = eq(mem_ctrl.single, UInt<1>("h00")) - node T_1021 = and(mem_ctrl.fma, T_1020) - node T_1024 = mux(T_1021, UInt<2>("h02"), UInt<1>("h00")) - node T_1025 = or(T_1011, T_1014) - node T_1026 = or(T_1025, T_1018) - node memLatencyMask = or(T_1026, T_1024) - reg wen : UInt<2>, clk, reset, UInt<2>("h00") - reg winfo : UInt<?>[2], clk, UInt<1>("h00"), winfo - node T_1042 = or(mem_ctrl.fma, mem_ctrl.fastpipe) - node T_1043 = or(T_1042, mem_ctrl.fromint) - node mem_wen = and(mem_reg_valid, T_1043) - node T_1047 = mux(ex_ctrl.fastpipe, UInt<2>("h02"), UInt<1>("h00")) - node T_1050 = mux(ex_ctrl.fromint, UInt<3>("h04"), UInt<1>("h00")) - node T_1051 = and(ex_ctrl.fma, ex_ctrl.single) - node T_1054 = mux(T_1051, UInt<2>("h02"), UInt<1>("h00")) - node T_1056 = eq(ex_ctrl.single, UInt<1>("h00")) - node T_1057 = and(ex_ctrl.fma, T_1056) - node T_1060 = mux(T_1057, UInt<3>("h04"), UInt<1>("h00")) - node T_1061 = or(T_1047, T_1050) - node T_1062 = or(T_1061, T_1054) - node T_1063 = or(T_1062, T_1060) - node T_1064 = and(memLatencyMask, T_1063) - node T_1066 = neq(T_1064, UInt<1>("h00")) - node T_1067 = and(mem_wen, T_1066) - node T_1070 = mux(ex_ctrl.fastpipe, UInt<3>("h04"), UInt<1>("h00")) - node T_1073 = mux(ex_ctrl.fromint, UInt<4>("h08"), UInt<1>("h00")) - node T_1074 = and(ex_ctrl.fma, ex_ctrl.single) - node T_1077 = mux(T_1074, UInt<3>("h04"), UInt<1>("h00")) - node T_1079 = eq(ex_ctrl.single, UInt<1>("h00")) - node T_1080 = and(ex_ctrl.fma, T_1079) - node T_1083 = mux(T_1080, UInt<4>("h08"), UInt<1>("h00")) - node T_1084 = or(T_1070, T_1073) - node T_1085 = or(T_1084, T_1077) - node T_1086 = or(T_1085, T_1083) - node T_1087 = and(wen, T_1086) - node T_1089 = neq(T_1087, UInt<1>("h00")) - node T_1090 = or(T_1067, T_1089) - reg write_port_busy : UInt<1>, clk, UInt<1>("h00"), write_port_busy + divSqrt_flags is invalid + reg divSqrt_in_flight : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg divSqrt_killed : UInt<1>, clk + node T_841 = mux(mem_ctrl.fastpipe, UInt<1>("h01"), UInt<1>("h00")) + node T_844 = mux(mem_ctrl.fromint, UInt<2>("h02"), UInt<1>("h00")) + node T_845 = and(mem_ctrl.fma, mem_ctrl.single) + node T_848 = mux(T_845, UInt<1>("h01"), UInt<1>("h00")) + node T_850 = eq(mem_ctrl.single, UInt<1>("h00")) + node T_851 = and(mem_ctrl.fma, T_850) + node T_854 = mux(T_851, UInt<2>("h02"), UInt<1>("h00")) + node T_855 = or(T_841, T_844) + node T_856 = or(T_855, T_848) + node memLatencyMask = or(T_856, T_854) + reg wen : UInt<2>, clk with : (reset => (reset, UInt<2>("h00"))) + reg winfo : UInt<?>[2], clk + node T_872 = or(mem_ctrl.fma, mem_ctrl.fastpipe) + node T_873 = or(T_872, mem_ctrl.fromint) + node mem_wen = and(mem_reg_valid, T_873) + node T_877 = mux(ex_ctrl.fastpipe, UInt<2>("h02"), UInt<1>("h00")) + node T_880 = mux(ex_ctrl.fromint, UInt<3>("h04"), UInt<1>("h00")) + node T_881 = and(ex_ctrl.fma, ex_ctrl.single) + node T_884 = mux(T_881, UInt<2>("h02"), UInt<1>("h00")) + node T_886 = eq(ex_ctrl.single, UInt<1>("h00")) + node T_887 = and(ex_ctrl.fma, T_886) + node T_890 = mux(T_887, UInt<3>("h04"), UInt<1>("h00")) + node T_891 = or(T_877, T_880) + node T_892 = or(T_891, T_884) + node T_893 = or(T_892, T_890) + node T_894 = and(memLatencyMask, T_893) + node T_896 = neq(T_894, UInt<1>("h00")) + node T_897 = and(mem_wen, T_896) + node T_900 = mux(ex_ctrl.fastpipe, UInt<3>("h04"), UInt<1>("h00")) + node T_903 = mux(ex_ctrl.fromint, UInt<4>("h08"), UInt<1>("h00")) + node T_904 = and(ex_ctrl.fma, ex_ctrl.single) + node T_907 = mux(T_904, UInt<3>("h04"), UInt<1>("h00")) + node T_909 = eq(ex_ctrl.single, UInt<1>("h00")) + node T_910 = and(ex_ctrl.fma, T_909) + node T_913 = mux(T_910, UInt<4>("h08"), UInt<1>("h00")) + node T_914 = or(T_900, T_903) + node T_915 = or(T_914, T_907) + node T_916 = or(T_915, T_913) + node T_917 = and(wen, T_916) + node T_919 = neq(T_917, UInt<1>("h00")) + node T_920 = or(T_897, T_919) + reg write_port_busy : UInt<1>, clk when req_valid : - write_port_busy <= T_1090 - skip - node T_1094 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) - node T_1097 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) - node T_1098 = and(mem_ctrl.fma, mem_ctrl.single) - node T_1101 = mux(T_1098, UInt<2>("h02"), UInt<1>("h00")) - node T_1103 = eq(mem_ctrl.single, UInt<1>("h00")) - node T_1104 = and(mem_ctrl.fma, T_1103) - node T_1107 = mux(T_1104, UInt<2>("h03"), UInt<1>("h00")) - node T_1108 = or(T_1094, T_1097) - node T_1109 = or(T_1108, T_1101) - node T_1110 = or(T_1109, T_1107) - node T_1111 = bits(mem_reg_inst, 11, 7) - node T_1112 = cat(mem_cp_valid, T_1110) - node T_1113 = cat(mem_ctrl.single, T_1111) - node mem_winfo = cat(T_1112, T_1113) - node T_1115 = bit(wen, 1) - when T_1115 : + write_port_busy <= T_920 + skip + node T_924 = mux(mem_ctrl.fastpipe, UInt<1>("h00"), UInt<1>("h00")) + node T_927 = mux(mem_ctrl.fromint, UInt<1>("h01"), UInt<1>("h00")) + node T_928 = and(mem_ctrl.fma, mem_ctrl.single) + node T_931 = mux(T_928, UInt<2>("h02"), UInt<1>("h00")) + node T_933 = eq(mem_ctrl.single, UInt<1>("h00")) + node T_934 = and(mem_ctrl.fma, T_933) + node T_937 = mux(T_934, UInt<2>("h03"), UInt<1>("h00")) + node T_938 = or(T_924, T_927) + node T_939 = or(T_938, T_931) + node T_940 = or(T_939, T_937) + node T_941 = bits(mem_reg_inst, 11, 7) + node T_942 = cat(mem_cp_valid, T_940) + node T_943 = cat(mem_ctrl.single, T_941) + node mem_winfo = cat(T_942, T_943) + node T_945 = bits(wen, 1, 1) + when T_945 : winfo[0] <= winfo[1] skip - node T_1116 = shr(wen, 1) - wen <= T_1116 + node T_946 = shr(wen, 1) + wen <= T_946 when mem_wen : - node T_1118 = eq(killm, UInt<1>("h00")) - when T_1118 : - node T_1119 = shr(wen, 1) - node T_1120 = or(T_1119, memLatencyMask) - wen <= T_1120 - skip - node T_1122 = eq(write_port_busy, UInt<1>("h00")) - node T_1123 = bit(memLatencyMask, 0) - node T_1124 = and(T_1122, T_1123) - when T_1124 : + node T_948 = eq(killm, UInt<1>("h00")) + when T_948 : + node T_949 = shr(wen, 1) + node T_950 = or(T_949, memLatencyMask) + wen <= T_950 + skip + node T_952 = eq(write_port_busy, UInt<1>("h00")) + node T_953 = bits(memLatencyMask, 0, 0) + node T_954 = and(T_952, T_953) + when T_954 : winfo[0] <= mem_winfo skip - node T_1126 = eq(write_port_busy, UInt<1>("h00")) - node T_1127 = bit(memLatencyMask, 1) - node T_1128 = and(T_1126, T_1127) - when T_1128 : + node T_956 = eq(write_port_busy, UInt<1>("h00")) + node T_957 = bits(memLatencyMask, 1, 1) + node T_958 = and(T_956, T_957) + when T_958 : winfo[1] <= mem_winfo skip skip - node T_1129 = bits(winfo[0], 4, 0) - node waddr = mux(divSqrt_wen, divSqrt_waddr, T_1129) + node T_959 = bits(winfo[0], 4, 0) + node waddr = mux(divSqrt_wen, divSqrt_waddr, T_959) node wsrc = shr(winfo[0], 6) - node wcp = bit(winfo[0], 8) - wire T_1134 : UInt<65>[4] - T_1134[0] <= fpmu.io.out.bits.data - T_1134[1] <= ifpu.io.out.bits.data - T_1134[2] <= sfma.io.out.bits.data - T_1134[3] <= dfma.io.out.bits.data - node wdata = mux(divSqrt_wen, divSqrt_wdata, T_1134[wsrc]) - wire T_1143 : UInt<5>[4] - T_1143[0] <= fpmu.io.out.bits.exc - T_1143[1] <= ifpu.io.out.bits.exc - T_1143[2] <= sfma.io.out.bits.exc - T_1143[3] <= dfma.io.out.bits.exc - node T_1151 = eq(wcp, UInt<1>("h00")) - node T_1152 = bit(wen, 0) - node T_1153 = and(T_1151, T_1152) - node T_1154 = or(T_1153, divSqrt_wen) - when T_1154 : - infer mport T_1155 = regfile[waddr], clk - T_1155 <= wdata - skip - node T_1156 = bit(wen, 0) - node T_1157 = and(wcp, T_1156) - when T_1157 : + node wcp = bits(winfo[0], 8, 8) + wire T_964 : UInt<65>[4] + T_964[0] <= fpmu.io.out.bits.data + T_964[1] <= ifpu.io.out.bits.data + T_964[2] <= sfma.io.out.bits.data + T_964[3] <= dfma.io.out.bits.data + node wdata = mux(divSqrt_wen, divSqrt_wdata, T_964[wsrc]) + wire T_973 : UInt<5>[4] + T_973[0] <= fpmu.io.out.bits.exc + T_973[1] <= ifpu.io.out.bits.exc + T_973[2] <= sfma.io.out.bits.exc + T_973[3] <= dfma.io.out.bits.exc + node T_981 = eq(wcp, UInt<1>("h00")) + node T_982 = bits(wen, 0, 0) + node T_983 = and(T_981, T_982) + node T_984 = or(T_983, divSqrt_wen) + when T_984 : + infer mport T_985 = regfile[waddr], clk + T_985 <= wdata + skip + node T_986 = bits(wen, 0, 0) + node T_987 = and(wcp, T_986) + when T_987 : io.cp_resp.bits.data <= wdata io.cp_resp.valid <= UInt<1>("h01") skip - node T_1160 = eq(ex_reg_valid, UInt<1>("h00")) - io.cp_req.ready <= T_1160 + node T_990 = eq(ex_reg_valid, UInt<1>("h00")) + io.cp_req.ready <= T_990 node wb_toint_valid = and(wb_reg_valid, wb_ctrl.toint) - reg wb_toint_exc : UInt<5>, clk, UInt<1>("h00"), wb_toint_exc + reg wb_toint_exc : UInt<5>, clk when mem_ctrl.toint : wb_toint_exc <= fpiu.io.out.bits.exc skip - node T_1163 = or(wb_toint_valid, divSqrt_wen) - node T_1164 = bit(wen, 0) - node T_1165 = or(T_1163, T_1164) - io.fcsr_flags.valid <= T_1165 - node T_1167 = mux(wb_toint_valid, wb_toint_exc, UInt<1>("h00")) - node T_1169 = mux(divSqrt_wen, divSqrt_flags, UInt<1>("h00")) - node T_1170 = or(T_1167, T_1169) - node T_1171 = bit(wen, 0) - node T_1173 = mux(T_1171, T_1143[wsrc], UInt<1>("h00")) - node T_1174 = or(T_1170, T_1173) - io.fcsr_flags.bits <= T_1174 - node T_1175 = or(mem_ctrl.div, mem_ctrl.sqrt) - node T_1176 = and(mem_reg_valid, T_1175) - node T_1178 = eq(divSqrt_inReady, UInt<1>("h00")) - node T_1180 = neq(wen, UInt<1>("h00")) - node T_1181 = or(T_1178, T_1180) - node units_busy = and(T_1176, T_1181) - node T_1183 = and(ex_reg_valid, ex_ctrl.wflags) - node T_1184 = and(mem_reg_valid, mem_ctrl.wflags) - node T_1185 = or(T_1183, T_1184) - node T_1186 = and(wb_reg_valid, wb_ctrl.toint) - node T_1187 = or(T_1185, T_1186) - node T_1189 = neq(wen, UInt<1>("h00")) - node T_1190 = or(T_1187, T_1189) - node T_1191 = or(T_1190, divSqrt_in_flight) - node T_1193 = eq(T_1191, UInt<1>("h00")) - io.fcsr_rdy <= T_1193 - node T_1194 = or(units_busy, write_port_busy) - node T_1195 = or(T_1194, divSqrt_in_flight) - io.nack_mem <= T_1195 + node T_993 = or(wb_toint_valid, divSqrt_wen) + node T_994 = bits(wen, 0, 0) + node T_995 = or(T_993, T_994) + io.fcsr_flags.valid <= T_995 + node T_997 = mux(wb_toint_valid, wb_toint_exc, UInt<1>("h00")) + node T_999 = mux(divSqrt_wen, divSqrt_flags, UInt<1>("h00")) + node T_1000 = or(T_997, T_999) + node T_1001 = bits(wen, 0, 0) + node T_1003 = mux(T_1001, T_973[wsrc], UInt<1>("h00")) + node T_1004 = or(T_1000, T_1003) + io.fcsr_flags.bits <= T_1004 + node T_1005 = or(mem_ctrl.div, mem_ctrl.sqrt) + node T_1006 = and(mem_reg_valid, T_1005) + node T_1008 = eq(divSqrt_inReady, UInt<1>("h00")) + node T_1010 = neq(wen, UInt<1>("h00")) + node T_1011 = or(T_1008, T_1010) + node units_busy = and(T_1006, T_1011) + node T_1013 = and(ex_reg_valid, ex_ctrl.wflags) + node T_1014 = and(mem_reg_valid, mem_ctrl.wflags) + node T_1015 = or(T_1013, T_1014) + node T_1016 = and(wb_reg_valid, wb_ctrl.toint) + node T_1017 = or(T_1015, T_1016) + node T_1019 = neq(wen, UInt<1>("h00")) + node T_1020 = or(T_1017, T_1019) + node T_1021 = or(T_1020, divSqrt_in_flight) + node T_1023 = eq(T_1021, UInt<1>("h00")) + io.fcsr_rdy <= T_1023 + node T_1024 = or(units_busy, write_port_busy) + node T_1025 = or(T_1024, divSqrt_in_flight) + io.nack_mem <= T_1025 io.dec <- fp_decoder.io.sigs - node T_1197 = eq(wb_cp_valid, UInt<1>("h00")) - node T_1198 = and(wb_reg_valid, T_1197) - node T_1200 = or(UInt<1>("h00"), mem_ctrl.div) - node T_1201 = or(T_1200, mem_ctrl.sqrt) - reg T_1202 : UInt<1>, clk, UInt<1>("h00"), T_1202 - T_1202 <= T_1201 - node T_1203 = and(T_1198, T_1202) - io.sboard_set <= T_1203 - node T_1205 = eq(wb_cp_valid, UInt<1>("h00")) - node T_1206 = bit(wen, 0) - node T_1208 = and(T_1206, UInt<1>("h00")) - node T_1209 = or(divSqrt_wen, T_1208) - node T_1210 = and(T_1205, T_1209) - io.sboard_clr <= T_1210 + node T_1027 = eq(wb_cp_valid, UInt<1>("h00")) + node T_1028 = and(wb_reg_valid, T_1027) + node T_1030 = or(UInt<1>("h00"), mem_ctrl.div) + node T_1031 = or(T_1030, mem_ctrl.sqrt) + reg T_1032 : UInt<1>, clk + T_1032 <= T_1031 + node T_1033 = and(T_1028, T_1032) + io.sboard_set <= T_1033 + node T_1035 = eq(wb_cp_valid, UInt<1>("h00")) + node T_1036 = bits(wen, 0, 0) + node T_1038 = and(T_1036, UInt<1>("h00")) + node T_1039 = or(divSqrt_wen, T_1038) + node T_1040 = and(T_1035, T_1039) + io.sboard_clr <= T_1040 io.sboard_clra <= waddr - node T_1211 = bit(ex_rm, 2) - node T_1212 = and(T_1211, ex_ctrl.round) - io.illegal_rm <= T_1212 + node T_1041 = bits(ex_rm, 2, 2) + node T_1042 = and(T_1041, ex_ctrl.round) + io.illegal_rm <= T_1042 divSqrt_wdata <= UInt<1>("h00") divSqrt_flags <= UInt<1>("h00") - reg T_1216 : UInt<1>, clk, UInt<1>("h00"), T_1216 - reg T_1218 : UInt<?>, clk, UInt<1>("h00"), T_1218 - reg T_1220 : UInt<?>, clk, UInt<1>("h00"), T_1220 - reg T_1222 : UInt<?>, clk, UInt<1>("h00"), T_1222 - inst T_1223 of DivSqrtRecF64 - T_1223.io.roundingMode <= UInt<1>("h00") - T_1223.io.b <= UInt<1>("h00") - T_1223.io.a <= UInt<1>("h00") - T_1223.io.sqrtOp <= UInt<1>("h00") - T_1223.io.inValid <= UInt<1>("h00") - T_1223.clk <= clk - T_1223.reset <= reset - node T_1229 = mux(T_1223.io.sqrtOp, T_1223.io.inReady_sqrt, T_1223.io.inReady_div) - divSqrt_inReady <= T_1229 - node T_1230 = or(T_1223.io.outValid_div, T_1223.io.outValid_sqrt) - node T_1231 = or(mem_ctrl.div, mem_ctrl.sqrt) - node T_1232 = and(mem_reg_valid, T_1231) - node T_1234 = eq(divSqrt_in_flight, UInt<1>("h00")) - node T_1235 = and(T_1232, T_1234) - T_1223.io.inValid <= T_1235 - T_1223.io.sqrtOp <= mem_ctrl.sqrt - T_1223.io.a <= fpiu.io.as_double.in1 - T_1223.io.b <= fpiu.io.as_double.in2 - T_1223.io.roundingMode <= fpiu.io.as_double.rm - node T_1236 = and(T_1223.io.inValid, divSqrt_inReady) - when T_1236 : + reg T_1046 : UInt<1>, clk + reg T_1048 : UInt<?>, clk + reg T_1050 : UInt<?>, clk + reg T_1052 : UInt<?>, clk + inst T_1053 of DivSqrtRecF64 + T_1053.io is invalid + T_1053.clk <= clk + T_1053.reset <= reset + node T_1054 = mux(T_1053.io.sqrtOp, T_1053.io.inReady_sqrt, T_1053.io.inReady_div) + divSqrt_inReady <= T_1054 + node T_1055 = or(T_1053.io.outValid_div, T_1053.io.outValid_sqrt) + node T_1056 = or(mem_ctrl.div, mem_ctrl.sqrt) + node T_1057 = and(mem_reg_valid, T_1056) + node T_1059 = eq(divSqrt_in_flight, UInt<1>("h00")) + node T_1060 = and(T_1057, T_1059) + T_1053.io.inValid <= T_1060 + T_1053.io.sqrtOp <= mem_ctrl.sqrt + T_1053.io.a <= fpiu.io.as_double.in1 + T_1053.io.b <= fpiu.io.as_double.in2 + T_1053.io.roundingMode <= fpiu.io.as_double.rm + node T_1061 = and(T_1053.io.inValid, divSqrt_inReady) + when T_1061 : divSqrt_in_flight <= UInt<1>("h01") divSqrt_killed <= killm - T_1216 <= mem_ctrl.single - node T_1238 = bits(mem_reg_inst, 11, 7) - divSqrt_waddr <= T_1238 - T_1218 <= T_1223.io.roundingMode - skip - when T_1230 : - node T_1240 = eq(divSqrt_killed, UInt<1>("h00")) - divSqrt_wen <= T_1240 - T_1222 <= T_1223.io.out + T_1046 <= mem_ctrl.single + node T_1063 = bits(mem_reg_inst, 11, 7) + divSqrt_waddr <= T_1063 + T_1048 <= T_1053.io.roundingMode + skip + when T_1055 : + node T_1065 = eq(divSqrt_killed, UInt<1>("h00")) + divSqrt_wen <= T_1065 + T_1052 <= T_1053.io.out divSqrt_in_flight <= UInt<1>("h00") - T_1220 <= T_1223.io.exceptionFlags - skip - inst T_1242 of RecFNToRecFN_121 - T_1242.io.roundingMode <= UInt<1>("h00") - T_1242.io.in <= UInt<1>("h00") - T_1242.clk <= clk - T_1242.reset <= reset - T_1242.io.in <= T_1222 - T_1242.io.roundingMode <= ex_rm - node T_1245 = mux(T_1216, T_1242.io.out, T_1222) - divSqrt_wdata <= T_1245 - node T_1247 = mux(T_1216, T_1242.io.exceptionFlags, UInt<1>("h00")) - node T_1248 = or(T_1220, T_1247) - divSqrt_flags <= T_1248 + T_1050 <= T_1053.io.exceptionFlags + skip + inst T_1067 of RecFNToRecFN_121 + T_1067.io is invalid + T_1067.clk <= clk + T_1067.reset <= reset + T_1067.io.in <= T_1052 + T_1067.io.roundingMode <= ex_rm + node T_1068 = mux(T_1046, T_1067.io.out, T_1052) + divSqrt_wdata <= T_1068 + node T_1070 = mux(T_1046, T_1067.io.exceptionFlags, UInt<1>("h00")) + node T_1071 = or(T_1050, T_1070) + divSqrt_flags <= T_1071 module RocketTile : input clk : Clock input reset : UInt<1> output io : {cached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, flip probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>}}, release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}}[1], uncached : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}[1], host : {flip reset : UInt<1>, flip id : UInt<1>, flip csr : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}, debug_stats_csr : UInt<1>}, dma : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, cmd : UInt<3>, source : UInt<32>, dest : UInt<32>, length : UInt<32>, size : UInt<2>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {client_xact_id : UInt<2>, status : UInt<2>}}}} - io.dma.resp.ready <= UInt<1>("h00") - io.dma.req.bits.size <= UInt<1>("h00") - io.dma.req.bits.length <= UInt<1>("h00") - io.dma.req.bits.dest <= UInt<1>("h00") - io.dma.req.bits.source <= UInt<1>("h00") - io.dma.req.bits.cmd <= UInt<1>("h00") - io.dma.req.bits.client_xact_id <= UInt<1>("h00") - io.dma.req.valid <= UInt<1>("h00") - io.host.debug_stats_csr <= UInt<1>("h00") - io.host.csr.resp.bits <= UInt<1>("h00") - io.host.csr.resp.valid <= UInt<1>("h00") - io.host.csr.req.ready <= UInt<1>("h00") - io.uncached[0].grant.ready <= UInt<1>("h00") - io.uncached[0].acquire.bits.data <= UInt<1>("h00") - io.uncached[0].acquire.bits.union <= UInt<1>("h00") - io.uncached[0].acquire.bits.a_type <= UInt<1>("h00") - io.uncached[0].acquire.bits.is_builtin_type <= UInt<1>("h00") - io.uncached[0].acquire.bits.addr_beat <= UInt<1>("h00") - io.uncached[0].acquire.bits.client_xact_id <= UInt<1>("h00") - io.uncached[0].acquire.bits.addr_block <= UInt<1>("h00") - io.uncached[0].acquire.valid <= UInt<1>("h00") - io.cached[0].release.bits.data <= UInt<1>("h00") - io.cached[0].release.bits.r_type <= UInt<1>("h00") - io.cached[0].release.bits.voluntary <= UInt<1>("h00") - io.cached[0].release.bits.client_xact_id <= UInt<1>("h00") - io.cached[0].release.bits.addr_block <= UInt<1>("h00") - io.cached[0].release.bits.addr_beat <= UInt<1>("h00") - io.cached[0].release.valid <= UInt<1>("h00") - io.cached[0].probe.ready <= UInt<1>("h00") - io.cached[0].grant.ready <= UInt<1>("h00") - io.cached[0].acquire.bits.data <= UInt<1>("h00") - io.cached[0].acquire.bits.union <= UInt<1>("h00") - io.cached[0].acquire.bits.a_type <= UInt<1>("h00") - io.cached[0].acquire.bits.is_builtin_type <= UInt<1>("h00") - io.cached[0].acquire.bits.addr_beat <= UInt<1>("h00") - io.cached[0].acquire.bits.client_xact_id <= UInt<1>("h00") - io.cached[0].acquire.bits.addr_block <= UInt<1>("h00") - io.cached[0].acquire.valid <= UInt<1>("h00") + io is invalid inst core of Rocket - core.io.rocc.dma.resp.ready <= UInt<1>("h00") - core.io.rocc.dma.req.bits.size <= UInt<1>("h00") - core.io.rocc.dma.req.bits.length <= UInt<1>("h00") - core.io.rocc.dma.req.bits.dest <= UInt<1>("h00") - core.io.rocc.dma.req.bits.source <= UInt<1>("h00") - core.io.rocc.dma.req.bits.cmd <= UInt<1>("h00") - core.io.rocc.dma.req.bits.client_xact_id <= UInt<1>("h00") - core.io.rocc.dma.req.valid <= UInt<1>("h00") - core.io.rocc.fpu_resp.ready <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.in3 <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.in2 <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.in1 <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.typ <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.rm <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.wflags <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.round <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.sqrt <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.div <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.fma <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.fastpipe <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.toint <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.fromint <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.single <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.swap23 <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.swap12 <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.ren3 <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.ren2 <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.ren1 <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.wen <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.ldst <= UInt<1>("h00") - core.io.rocc.fpu_req.bits.cmd <= UInt<1>("h00") - core.io.rocc.fpu_req.valid <= UInt<1>("h00") - core.io.rocc.pptw.req.bits.fetch <= UInt<1>("h00") - core.io.rocc.pptw.req.bits.store <= UInt<1>("h00") - core.io.rocc.pptw.req.bits.prv <= UInt<1>("h00") - core.io.rocc.pptw.req.bits.addr <= UInt<1>("h00") - core.io.rocc.pptw.req.valid <= UInt<1>("h00") - core.io.rocc.dptw.req.bits.fetch <= UInt<1>("h00") - core.io.rocc.dptw.req.bits.store <= UInt<1>("h00") - core.io.rocc.dptw.req.bits.prv <= UInt<1>("h00") - core.io.rocc.dptw.req.bits.addr <= UInt<1>("h00") - core.io.rocc.dptw.req.valid <= UInt<1>("h00") - core.io.rocc.iptw.req.bits.fetch <= UInt<1>("h00") - core.io.rocc.iptw.req.bits.store <= UInt<1>("h00") - core.io.rocc.iptw.req.bits.prv <= UInt<1>("h00") - core.io.rocc.iptw.req.bits.addr <= UInt<1>("h00") - core.io.rocc.iptw.req.valid <= UInt<1>("h00") - core.io.rocc.autl.grant.ready <= UInt<1>("h00") - core.io.rocc.autl.acquire.bits.data <= UInt<1>("h00") - core.io.rocc.autl.acquire.bits.union <= UInt<1>("h00") - core.io.rocc.autl.acquire.bits.a_type <= UInt<1>("h00") - core.io.rocc.autl.acquire.bits.is_builtin_type <= UInt<1>("h00") - core.io.rocc.autl.acquire.bits.addr_beat <= UInt<1>("h00") - core.io.rocc.autl.acquire.bits.client_xact_id <= UInt<1>("h00") - core.io.rocc.autl.acquire.bits.addr_block <= UInt<1>("h00") - core.io.rocc.autl.acquire.valid <= UInt<1>("h00") - core.io.rocc.interrupt <= UInt<1>("h00") - core.io.rocc.busy <= UInt<1>("h00") - core.io.rocc.mem.invalidate_lr <= UInt<1>("h00") - core.io.rocc.mem.req.bits.data <= UInt<1>("h00") - core.io.rocc.mem.req.bits.phys <= UInt<1>("h00") - core.io.rocc.mem.req.bits.kill <= UInt<1>("h00") - core.io.rocc.mem.req.bits.typ <= UInt<1>("h00") - core.io.rocc.mem.req.bits.cmd <= UInt<1>("h00") - core.io.rocc.mem.req.bits.tag <= UInt<1>("h00") - core.io.rocc.mem.req.bits.addr <= UInt<1>("h00") - core.io.rocc.mem.req.valid <= UInt<1>("h00") - core.io.rocc.resp.bits.data <= UInt<1>("h00") - core.io.rocc.resp.bits.rd <= UInt<1>("h00") - core.io.rocc.resp.valid <= UInt<1>("h00") - core.io.rocc.cmd.ready <= UInt<1>("h00") - core.io.fpu.cp_resp.bits.exc <= UInt<1>("h00") - core.io.fpu.cp_resp.bits.data <= UInt<1>("h00") - core.io.fpu.cp_resp.valid <= UInt<1>("h00") - core.io.fpu.cp_req.ready <= UInt<1>("h00") - core.io.fpu.sboard_clra <= UInt<1>("h00") - core.io.fpu.sboard_clr <= UInt<1>("h00") - core.io.fpu.sboard_set <= UInt<1>("h00") - core.io.fpu.dec.wflags <= UInt<1>("h00") - core.io.fpu.dec.round <= UInt<1>("h00") - core.io.fpu.dec.sqrt <= UInt<1>("h00") - core.io.fpu.dec.div <= UInt<1>("h00") - core.io.fpu.dec.fma <= UInt<1>("h00") - core.io.fpu.dec.fastpipe <= UInt<1>("h00") - core.io.fpu.dec.toint <= UInt<1>("h00") - core.io.fpu.dec.fromint <= UInt<1>("h00") - core.io.fpu.dec.single <= UInt<1>("h00") - core.io.fpu.dec.swap23 <= UInt<1>("h00") - core.io.fpu.dec.swap12 <= UInt<1>("h00") - core.io.fpu.dec.ren3 <= UInt<1>("h00") - core.io.fpu.dec.ren2 <= UInt<1>("h00") - core.io.fpu.dec.ren1 <= UInt<1>("h00") - core.io.fpu.dec.wen <= UInt<1>("h00") - core.io.fpu.dec.ldst <= UInt<1>("h00") - core.io.fpu.dec.cmd <= UInt<1>("h00") - core.io.fpu.illegal_rm <= UInt<1>("h00") - core.io.fpu.nack_mem <= UInt<1>("h00") - core.io.fpu.fcsr_rdy <= UInt<1>("h00") - core.io.fpu.toint_data <= UInt<1>("h00") - core.io.fpu.store_data <= UInt<1>("h00") - core.io.fpu.fcsr_flags.bits <= UInt<1>("h00") - core.io.fpu.fcsr_flags.valid <= UInt<1>("h00") - core.io.dmem.ordered <= UInt<1>("h00") - core.io.dmem.xcpt.pf.st <= UInt<1>("h00") - core.io.dmem.xcpt.pf.ld <= UInt<1>("h00") - core.io.dmem.xcpt.ma.st <= UInt<1>("h00") - core.io.dmem.xcpt.ma.ld <= UInt<1>("h00") - core.io.dmem.replay_next.bits <= UInt<1>("h00") - core.io.dmem.replay_next.valid <= UInt<1>("h00") - core.io.dmem.resp.bits.store_data <= UInt<1>("h00") - core.io.dmem.resp.bits.data_word_bypass <= UInt<1>("h00") - core.io.dmem.resp.bits.has_data <= UInt<1>("h00") - core.io.dmem.resp.bits.replay <= UInt<1>("h00") - core.io.dmem.resp.bits.nack <= UInt<1>("h00") - core.io.dmem.resp.bits.data <= UInt<1>("h00") - core.io.dmem.resp.bits.typ <= UInt<1>("h00") - core.io.dmem.resp.bits.cmd <= UInt<1>("h00") - core.io.dmem.resp.bits.tag <= UInt<1>("h00") - core.io.dmem.resp.bits.addr <= UInt<1>("h00") - core.io.dmem.resp.valid <= UInt<1>("h00") - core.io.dmem.req.ready <= UInt<1>("h00") - core.io.imem.npc <= UInt<1>("h00") - core.io.imem.btb_resp.bits.bht.value <= UInt<1>("h00") - core.io.imem.btb_resp.bits.bht.history <= UInt<1>("h00") - core.io.imem.btb_resp.bits.entry <= UInt<1>("h00") - core.io.imem.btb_resp.bits.target <= UInt<1>("h00") - core.io.imem.btb_resp.bits.bridx <= UInt<1>("h00") - core.io.imem.btb_resp.bits.mask <= UInt<1>("h00") - core.io.imem.btb_resp.bits.taken <= UInt<1>("h00") - core.io.imem.btb_resp.valid <= UInt<1>("h00") - core.io.imem.resp.bits.xcpt_if <= UInt<1>("h00") - core.io.imem.resp.bits.mask <= UInt<1>("h00") - core.io.imem.resp.bits.data[0] <= UInt<1>("h00") - core.io.imem.resp.bits.pc <= UInt<1>("h00") - core.io.imem.resp.valid <= UInt<1>("h00") - core.io.host.csr.resp.ready <= UInt<1>("h00") - core.io.host.csr.req.bits.data <= UInt<1>("h00") - core.io.host.csr.req.bits.addr <= UInt<1>("h00") - core.io.host.csr.req.bits.rw <= UInt<1>("h00") - core.io.host.csr.req.valid <= UInt<1>("h00") - core.io.host.id <= UInt<1>("h00") - core.io.host.reset <= UInt<1>("h00") + core.io is invalid core.clk <= clk core.reset <= reset inst icache of Frontend - icache.io.mem.grant.bits.data <= UInt<1>("h00") - icache.io.mem.grant.bits.g_type <= UInt<1>("h00") - icache.io.mem.grant.bits.is_builtin_type <= UInt<1>("h00") - icache.io.mem.grant.bits.manager_xact_id <= UInt<1>("h00") - icache.io.mem.grant.bits.client_xact_id <= UInt<1>("h00") - icache.io.mem.grant.bits.addr_beat <= UInt<1>("h00") - icache.io.mem.grant.valid <= UInt<1>("h00") - icache.io.mem.acquire.ready <= UInt<1>("h00") - icache.io.ptw.invalidate <= UInt<1>("h00") - icache.io.ptw.status.ie <= UInt<1>("h00") - icache.io.ptw.status.prv <= UInt<1>("h00") - icache.io.ptw.status.ie1 <= UInt<1>("h00") - icache.io.ptw.status.prv1 <= UInt<1>("h00") - icache.io.ptw.status.ie2 <= UInt<1>("h00") - icache.io.ptw.status.prv2 <= UInt<1>("h00") - icache.io.ptw.status.ie3 <= UInt<1>("h00") - icache.io.ptw.status.prv3 <= UInt<1>("h00") - icache.io.ptw.status.fs <= UInt<1>("h00") - icache.io.ptw.status.xs <= UInt<1>("h00") - icache.io.ptw.status.mprv <= UInt<1>("h00") - icache.io.ptw.status.vm <= UInt<1>("h00") - icache.io.ptw.status.zero1 <= UInt<1>("h00") - icache.io.ptw.status.sd_rv32 <= UInt<1>("h00") - icache.io.ptw.status.zero2 <= UInt<1>("h00") - icache.io.ptw.status.sd <= UInt<1>("h00") - icache.io.ptw.resp.bits.pte.v <= UInt<1>("h00") - icache.io.ptw.resp.bits.pte.typ <= UInt<1>("h00") - icache.io.ptw.resp.bits.pte.r <= UInt<1>("h00") - icache.io.ptw.resp.bits.pte.d <= UInt<1>("h00") - icache.io.ptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") - icache.io.ptw.resp.bits.pte.ppn <= UInt<1>("h00") - icache.io.ptw.resp.bits.error <= UInt<1>("h00") - icache.io.ptw.resp.valid <= UInt<1>("h00") - icache.io.ptw.req.ready <= UInt<1>("h00") - icache.io.cpu.invalidate <= UInt<1>("h00") - icache.io.cpu.ras_update.bits.prediction.bits.bht.value <= UInt<1>("h00") - icache.io.cpu.ras_update.bits.prediction.bits.bht.history <= UInt<1>("h00") - icache.io.cpu.ras_update.bits.prediction.bits.entry <= UInt<1>("h00") - icache.io.cpu.ras_update.bits.prediction.bits.target <= UInt<1>("h00") - icache.io.cpu.ras_update.bits.prediction.bits.bridx <= UInt<1>("h00") - icache.io.cpu.ras_update.bits.prediction.bits.mask <= UInt<1>("h00") - icache.io.cpu.ras_update.bits.prediction.bits.taken <= UInt<1>("h00") - icache.io.cpu.ras_update.bits.prediction.valid <= UInt<1>("h00") - icache.io.cpu.ras_update.bits.returnAddr <= UInt<1>("h00") - icache.io.cpu.ras_update.bits.isReturn <= UInt<1>("h00") - icache.io.cpu.ras_update.bits.isCall <= UInt<1>("h00") - icache.io.cpu.ras_update.valid <= UInt<1>("h00") - icache.io.cpu.bht_update.bits.mispredict <= UInt<1>("h00") - icache.io.cpu.bht_update.bits.taken <= UInt<1>("h00") - icache.io.cpu.bht_update.bits.pc <= UInt<1>("h00") - icache.io.cpu.bht_update.bits.prediction.bits.bht.value <= UInt<1>("h00") - icache.io.cpu.bht_update.bits.prediction.bits.bht.history <= UInt<1>("h00") - icache.io.cpu.bht_update.bits.prediction.bits.entry <= UInt<1>("h00") - icache.io.cpu.bht_update.bits.prediction.bits.target <= UInt<1>("h00") - icache.io.cpu.bht_update.bits.prediction.bits.bridx <= UInt<1>("h00") - icache.io.cpu.bht_update.bits.prediction.bits.mask <= UInt<1>("h00") - icache.io.cpu.bht_update.bits.prediction.bits.taken <= UInt<1>("h00") - icache.io.cpu.bht_update.bits.prediction.valid <= UInt<1>("h00") - icache.io.cpu.bht_update.valid <= UInt<1>("h00") - icache.io.cpu.btb_update.bits.br_pc <= UInt<1>("h00") - icache.io.cpu.btb_update.bits.isReturn <= UInt<1>("h00") - icache.io.cpu.btb_update.bits.isJump <= UInt<1>("h00") - icache.io.cpu.btb_update.bits.taken <= UInt<1>("h00") - icache.io.cpu.btb_update.bits.target <= UInt<1>("h00") - icache.io.cpu.btb_update.bits.pc <= UInt<1>("h00") - icache.io.cpu.btb_update.bits.prediction.bits.bht.value <= UInt<1>("h00") - icache.io.cpu.btb_update.bits.prediction.bits.bht.history <= UInt<1>("h00") - icache.io.cpu.btb_update.bits.prediction.bits.entry <= UInt<1>("h00") - icache.io.cpu.btb_update.bits.prediction.bits.target <= UInt<1>("h00") - icache.io.cpu.btb_update.bits.prediction.bits.bridx <= UInt<1>("h00") - icache.io.cpu.btb_update.bits.prediction.bits.mask <= UInt<1>("h00") - icache.io.cpu.btb_update.bits.prediction.bits.taken <= UInt<1>("h00") - icache.io.cpu.btb_update.bits.prediction.valid <= UInt<1>("h00") - icache.io.cpu.btb_update.valid <= UInt<1>("h00") - icache.io.cpu.resp.ready <= UInt<1>("h00") - icache.io.cpu.req.bits.pc <= UInt<1>("h00") - icache.io.cpu.req.valid <= UInt<1>("h00") + icache.io is invalid icache.clk <= clk icache.reset <= reset inst dcache of HellaCache - dcache.io.mem.release.ready <= UInt<1>("h00") - dcache.io.mem.probe.bits.p_type <= UInt<1>("h00") - dcache.io.mem.probe.bits.addr_block <= UInt<1>("h00") - dcache.io.mem.probe.valid <= UInt<1>("h00") - dcache.io.mem.grant.bits.data <= UInt<1>("h00") - dcache.io.mem.grant.bits.g_type <= UInt<1>("h00") - dcache.io.mem.grant.bits.is_builtin_type <= UInt<1>("h00") - dcache.io.mem.grant.bits.manager_xact_id <= UInt<1>("h00") - dcache.io.mem.grant.bits.client_xact_id <= UInt<1>("h00") - dcache.io.mem.grant.bits.addr_beat <= UInt<1>("h00") - dcache.io.mem.grant.valid <= UInt<1>("h00") - dcache.io.mem.acquire.ready <= UInt<1>("h00") - dcache.io.ptw.invalidate <= UInt<1>("h00") - dcache.io.ptw.status.ie <= UInt<1>("h00") - dcache.io.ptw.status.prv <= UInt<1>("h00") - dcache.io.ptw.status.ie1 <= UInt<1>("h00") - dcache.io.ptw.status.prv1 <= UInt<1>("h00") - dcache.io.ptw.status.ie2 <= UInt<1>("h00") - dcache.io.ptw.status.prv2 <= UInt<1>("h00") - dcache.io.ptw.status.ie3 <= UInt<1>("h00") - dcache.io.ptw.status.prv3 <= UInt<1>("h00") - dcache.io.ptw.status.fs <= UInt<1>("h00") - dcache.io.ptw.status.xs <= UInt<1>("h00") - dcache.io.ptw.status.mprv <= UInt<1>("h00") - dcache.io.ptw.status.vm <= UInt<1>("h00") - dcache.io.ptw.status.zero1 <= UInt<1>("h00") - dcache.io.ptw.status.sd_rv32 <= UInt<1>("h00") - dcache.io.ptw.status.zero2 <= UInt<1>("h00") - dcache.io.ptw.status.sd <= UInt<1>("h00") - dcache.io.ptw.resp.bits.pte.v <= UInt<1>("h00") - dcache.io.ptw.resp.bits.pte.typ <= UInt<1>("h00") - dcache.io.ptw.resp.bits.pte.r <= UInt<1>("h00") - dcache.io.ptw.resp.bits.pte.d <= UInt<1>("h00") - dcache.io.ptw.resp.bits.pte.reserved_for_software <= UInt<1>("h00") - dcache.io.ptw.resp.bits.pte.ppn <= UInt<1>("h00") - dcache.io.ptw.resp.bits.error <= UInt<1>("h00") - dcache.io.ptw.resp.valid <= UInt<1>("h00") - dcache.io.ptw.req.ready <= UInt<1>("h00") - dcache.io.cpu.invalidate_lr <= UInt<1>("h00") - dcache.io.cpu.req.bits.data <= UInt<1>("h00") - dcache.io.cpu.req.bits.phys <= UInt<1>("h00") - dcache.io.cpu.req.bits.kill <= UInt<1>("h00") - dcache.io.cpu.req.bits.typ <= UInt<1>("h00") - dcache.io.cpu.req.bits.cmd <= UInt<1>("h00") - dcache.io.cpu.req.bits.tag <= UInt<1>("h00") - dcache.io.cpu.req.bits.addr <= UInt<1>("h00") - dcache.io.cpu.req.valid <= UInt<1>("h00") + dcache.io is invalid dcache.clk <= clk dcache.reset <= reset inst ptw of PTW - ptw.io.dpath.status.ie <= UInt<1>("h00") - ptw.io.dpath.status.prv <= UInt<1>("h00") - ptw.io.dpath.status.ie1 <= UInt<1>("h00") - ptw.io.dpath.status.prv1 <= UInt<1>("h00") - ptw.io.dpath.status.ie2 <= UInt<1>("h00") - ptw.io.dpath.status.prv2 <= UInt<1>("h00") - ptw.io.dpath.status.ie3 <= UInt<1>("h00") - ptw.io.dpath.status.prv3 <= UInt<1>("h00") - ptw.io.dpath.status.fs <= UInt<1>("h00") - ptw.io.dpath.status.xs <= UInt<1>("h00") - ptw.io.dpath.status.mprv <= UInt<1>("h00") - ptw.io.dpath.status.vm <= UInt<1>("h00") - ptw.io.dpath.status.zero1 <= UInt<1>("h00") - ptw.io.dpath.status.sd_rv32 <= UInt<1>("h00") - ptw.io.dpath.status.zero2 <= UInt<1>("h00") - ptw.io.dpath.status.sd <= UInt<1>("h00") - ptw.io.dpath.invalidate <= UInt<1>("h00") - ptw.io.dpath.ptbr <= UInt<1>("h00") - ptw.io.mem.ordered <= UInt<1>("h00") - ptw.io.mem.xcpt.pf.st <= UInt<1>("h00") - ptw.io.mem.xcpt.pf.ld <= UInt<1>("h00") - ptw.io.mem.xcpt.ma.st <= UInt<1>("h00") - ptw.io.mem.xcpt.ma.ld <= UInt<1>("h00") - ptw.io.mem.replay_next.bits <= UInt<1>("h00") - ptw.io.mem.replay_next.valid <= UInt<1>("h00") - ptw.io.mem.resp.bits.store_data <= UInt<1>("h00") - ptw.io.mem.resp.bits.data_word_bypass <= UInt<1>("h00") - ptw.io.mem.resp.bits.has_data <= UInt<1>("h00") - ptw.io.mem.resp.bits.replay <= UInt<1>("h00") - ptw.io.mem.resp.bits.nack <= UInt<1>("h00") - ptw.io.mem.resp.bits.data <= UInt<1>("h00") - ptw.io.mem.resp.bits.typ <= UInt<1>("h00") - ptw.io.mem.resp.bits.cmd <= UInt<1>("h00") - ptw.io.mem.resp.bits.tag <= UInt<1>("h00") - ptw.io.mem.resp.bits.addr <= UInt<1>("h00") - ptw.io.mem.resp.valid <= UInt<1>("h00") - ptw.io.mem.req.ready <= UInt<1>("h00") - ptw.io.requestor[0].req.bits.fetch <= UInt<1>("h00") - ptw.io.requestor[0].req.bits.store <= UInt<1>("h00") - ptw.io.requestor[0].req.bits.prv <= UInt<1>("h00") - ptw.io.requestor[0].req.bits.addr <= UInt<1>("h00") - ptw.io.requestor[0].req.valid <= UInt<1>("h00") - ptw.io.requestor[1].req.bits.fetch <= UInt<1>("h00") - ptw.io.requestor[1].req.bits.store <= UInt<1>("h00") - ptw.io.requestor[1].req.bits.prv <= UInt<1>("h00") - ptw.io.requestor[1].req.bits.addr <= UInt<1>("h00") - ptw.io.requestor[1].req.valid <= UInt<1>("h00") + ptw.io is invalid ptw.clk <= clk ptw.reset <= reset dcache.io.cpu.invalidate_lr <= core.io.dmem.invalidate_lr inst dcArb of HellaCacheArbiter - dcArb.io.mem.ordered <= UInt<1>("h00") - dcArb.io.mem.xcpt.pf.st <= UInt<1>("h00") - dcArb.io.mem.xcpt.pf.ld <= UInt<1>("h00") - dcArb.io.mem.xcpt.ma.st <= UInt<1>("h00") - dcArb.io.mem.xcpt.ma.ld <= UInt<1>("h00") - dcArb.io.mem.replay_next.bits <= UInt<1>("h00") - dcArb.io.mem.replay_next.valid <= UInt<1>("h00") - dcArb.io.mem.resp.bits.store_data <= UInt<1>("h00") - dcArb.io.mem.resp.bits.data_word_bypass <= UInt<1>("h00") - dcArb.io.mem.resp.bits.has_data <= UInt<1>("h00") - dcArb.io.mem.resp.bits.replay <= UInt<1>("h00") - dcArb.io.mem.resp.bits.nack <= UInt<1>("h00") - dcArb.io.mem.resp.bits.data <= UInt<1>("h00") - dcArb.io.mem.resp.bits.typ <= UInt<1>("h00") - dcArb.io.mem.resp.bits.cmd <= UInt<1>("h00") - dcArb.io.mem.resp.bits.tag <= UInt<1>("h00") - dcArb.io.mem.resp.bits.addr <= UInt<1>("h00") - dcArb.io.mem.resp.valid <= UInt<1>("h00") - dcArb.io.mem.req.ready <= UInt<1>("h00") - dcArb.io.requestor[0].invalidate_lr <= UInt<1>("h00") - dcArb.io.requestor[0].req.bits.data <= UInt<1>("h00") - dcArb.io.requestor[0].req.bits.phys <= UInt<1>("h00") - dcArb.io.requestor[0].req.bits.kill <= UInt<1>("h00") - dcArb.io.requestor[0].req.bits.typ <= UInt<1>("h00") - dcArb.io.requestor[0].req.bits.cmd <= UInt<1>("h00") - dcArb.io.requestor[0].req.bits.tag <= UInt<1>("h00") - dcArb.io.requestor[0].req.bits.addr <= UInt<1>("h00") - dcArb.io.requestor[0].req.valid <= UInt<1>("h00") - dcArb.io.requestor[1].invalidate_lr <= UInt<1>("h00") - dcArb.io.requestor[1].req.bits.data <= UInt<1>("h00") - dcArb.io.requestor[1].req.bits.phys <= UInt<1>("h00") - dcArb.io.requestor[1].req.bits.kill <= UInt<1>("h00") - dcArb.io.requestor[1].req.bits.typ <= UInt<1>("h00") - dcArb.io.requestor[1].req.bits.cmd <= UInt<1>("h00") - dcArb.io.requestor[1].req.bits.tag <= UInt<1>("h00") - dcArb.io.requestor[1].req.bits.addr <= UInt<1>("h00") - dcArb.io.requestor[1].req.valid <= UInt<1>("h00") + dcArb.io is invalid dcArb.clk <= clk dcArb.reset <= reset dcArb.io.requestor[0] <- ptw.io.mem @@ -40714,48 +32180,15 @@ circuit Top : io.host <- core.io.host icache.io.cpu <- core.io.imem core.io.ptw <- ptw.io.dpath - inst T_3634 of FPU - T_3634.io.cp_resp.ready <= UInt<1>("h00") - T_3634.io.cp_req.bits.in3 <= UInt<1>("h00") - T_3634.io.cp_req.bits.in2 <= UInt<1>("h00") - T_3634.io.cp_req.bits.in1 <= UInt<1>("h00") - T_3634.io.cp_req.bits.typ <= UInt<1>("h00") - T_3634.io.cp_req.bits.rm <= UInt<1>("h00") - T_3634.io.cp_req.bits.wflags <= UInt<1>("h00") - T_3634.io.cp_req.bits.round <= UInt<1>("h00") - T_3634.io.cp_req.bits.sqrt <= UInt<1>("h00") - T_3634.io.cp_req.bits.div <= UInt<1>("h00") - T_3634.io.cp_req.bits.fma <= UInt<1>("h00") - T_3634.io.cp_req.bits.fastpipe <= UInt<1>("h00") - T_3634.io.cp_req.bits.toint <= UInt<1>("h00") - T_3634.io.cp_req.bits.fromint <= UInt<1>("h00") - T_3634.io.cp_req.bits.single <= UInt<1>("h00") - T_3634.io.cp_req.bits.swap23 <= UInt<1>("h00") - T_3634.io.cp_req.bits.swap12 <= UInt<1>("h00") - T_3634.io.cp_req.bits.ren3 <= UInt<1>("h00") - T_3634.io.cp_req.bits.ren2 <= UInt<1>("h00") - T_3634.io.cp_req.bits.ren1 <= UInt<1>("h00") - T_3634.io.cp_req.bits.wen <= UInt<1>("h00") - T_3634.io.cp_req.bits.ldst <= UInt<1>("h00") - T_3634.io.cp_req.bits.cmd <= UInt<1>("h00") - T_3634.io.cp_req.valid <= UInt<1>("h00") - T_3634.io.killm <= UInt<1>("h00") - T_3634.io.killx <= UInt<1>("h00") - T_3634.io.valid <= UInt<1>("h00") - T_3634.io.dmem_resp_data <= UInt<1>("h00") - T_3634.io.dmem_resp_tag <= UInt<1>("h00") - T_3634.io.dmem_resp_type <= UInt<1>("h00") - T_3634.io.dmem_resp_val <= UInt<1>("h00") - T_3634.io.fcsr_rm <= UInt<1>("h00") - T_3634.io.fromint_data <= UInt<1>("h00") - T_3634.io.inst <= UInt<1>("h00") - T_3634.clk <= clk - T_3634.reset <= reset - core.io.fpu <- T_3634.io + inst T_3284 of FPU + T_3284.io is invalid + T_3284.clk <= clk + T_3284.reset <= reset + core.io.fpu <- T_3284.io io.cached[0] <- dcache.io.mem io.uncached[0] <- icache.io.mem - T_3634.io.cp_req.valid <= UInt<1>("h00") - T_3634.io.cp_resp.ready <= UInt<1>("h00") + T_3284.io.cp_req.valid <= UInt<1>("h00") + T_3284.io.cp_resp.ready <= UInt<1>("h00") io.dma.req.valid <= UInt<1>("h00") io.dma.resp.ready <= UInt<1>("h00") @@ -40764,16 +32197,11 @@ circuit Top : input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, count : UInt<2>} - io.count <= UInt<1>("h00") - io.deq.bits.data <= UInt<1>("h00") - io.deq.bits.addr <= UInt<1>("h00") - io.deq.bits.rw <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}[2] - reg T_53 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_55 : UInt<1>, clk, reset, UInt<1>("h00") - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg T_53 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_55 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(T_53, T_55) node T_60 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_60) @@ -40791,54 +32219,50 @@ circuit Top : T_74 <- io.enq.bits node T_79 = eq(T_53, UInt<1>("h01")) node T_81 = and(UInt<1>("h00"), T_79) - node T_84 = addw(T_53, UInt<1>("h01")) - node T_85 = mux(T_81, UInt<1>("h00"), T_84) - T_53 <= T_85 + node T_84 = add(T_53, UInt<1>("h01")) + node T_85 = tail(T_84, 1) + node T_86 = mux(T_81, UInt<1>("h00"), T_85) + T_53 <= T_86 skip when do_deq : - node T_87 = eq(T_55, UInt<1>("h01")) - node T_89 = and(UInt<1>("h00"), T_87) - node T_92 = addw(T_55, UInt<1>("h01")) - node T_93 = mux(T_89, UInt<1>("h00"), T_92) - T_55 <= T_93 - skip - node T_94 = neq(do_enq, do_deq) - when T_94 : + node T_88 = eq(T_55, UInt<1>("h01")) + node T_90 = and(UInt<1>("h00"), T_88) + node T_93 = add(T_55, UInt<1>("h01")) + node T_94 = tail(T_93, 1) + node T_95 = mux(T_90, UInt<1>("h00"), T_94) + T_55 <= T_95 + skip + node T_96 = neq(do_enq, do_deq) + when T_96 : maybe_full <= do_enq skip - node T_96 = eq(empty, UInt<1>("h00")) - node T_98 = and(UInt<1>("h00"), io.enq.valid) - node T_99 = or(T_96, T_98) - io.deq.valid <= T_99 - node T_101 = eq(full, UInt<1>("h00")) - node T_103 = and(UInt<1>("h00"), io.deq.ready) - node T_104 = or(T_101, T_103) - io.enq.ready <= T_104 - infer mport T_105 = ram[T_55], clk - wire T_113 : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>} - T_113 <- T_105 - when maybe_flow : - T_113 <- io.enq.bits - skip - io.deq.bits <- T_113 - node ptr_diff = subw(T_53, T_55) - node T_118 = and(maybe_full, ptr_match) - node T_119 = cat(T_118, ptr_diff) - io.count <= T_119 + node T_98 = eq(empty, UInt<1>("h00")) + node T_100 = and(UInt<1>("h00"), io.enq.valid) + node T_101 = or(T_98, T_100) + io.deq.valid <= T_101 + node T_103 = eq(full, UInt<1>("h00")) + node T_105 = and(UInt<1>("h00"), io.deq.ready) + node T_106 = or(T_103, T_105) + io.enq.ready <= T_106 + infer mport T_107 = ram[T_55], clk + node T_111 = mux(maybe_flow, io.enq.bits, T_107) + io.deq.bits <- T_111 + node T_115 = sub(T_53, T_55) + node ptr_diff = tail(T_115, 1) + node T_117 = and(maybe_full, ptr_match) + node T_118 = cat(T_117, ptr_diff) + io.count <= T_118 module Queue_125 : input clk : Clock input reset : UInt<1> output io : {flip enq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, deq : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}, count : UInt<2>} - io.count <= UInt<1>("h00") - io.deq.bits <= UInt<1>("h00") - io.deq.valid <= UInt<1>("h00") - io.enq.ready <= UInt<1>("h00") + io is invalid cmem ram : UInt<64>[2] - reg T_26 : UInt<1>, clk, reset, UInt<1>("h00") - reg T_28 : UInt<1>, clk, reset, UInt<1>("h00") - reg maybe_full : UInt<1>, clk, reset, UInt<1>("h00") + reg T_26 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg T_28 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) + reg maybe_full : UInt<1>, clk with : (reset => (reset, UInt<1>("h00"))) node ptr_match = eq(T_26, T_28) node T_33 = eq(maybe_full, UInt<1>("h00")) node empty = and(ptr_match, T_33) @@ -40856,333 +32280,125 @@ circuit Top : T_47 <= io.enq.bits node T_49 = eq(T_26, UInt<1>("h01")) node T_51 = and(UInt<1>("h00"), T_49) - node T_54 = addw(T_26, UInt<1>("h01")) - node T_55 = mux(T_51, UInt<1>("h00"), T_54) - T_26 <= T_55 + node T_54 = add(T_26, UInt<1>("h01")) + node T_55 = tail(T_54, 1) + node T_56 = mux(T_51, UInt<1>("h00"), T_55) + T_26 <= T_56 skip when do_deq : - node T_57 = eq(T_28, UInt<1>("h01")) - node T_59 = and(UInt<1>("h00"), T_57) - node T_62 = addw(T_28, UInt<1>("h01")) - node T_63 = mux(T_59, UInt<1>("h00"), T_62) - T_28 <= T_63 - skip - node T_64 = neq(do_enq, do_deq) - when T_64 : + node T_58 = eq(T_28, UInt<1>("h01")) + node T_60 = and(UInt<1>("h00"), T_58) + node T_63 = add(T_28, UInt<1>("h01")) + node T_64 = tail(T_63, 1) + node T_65 = mux(T_60, UInt<1>("h00"), T_64) + T_28 <= T_65 + skip + node T_66 = neq(do_enq, do_deq) + when T_66 : maybe_full <= do_enq skip - node T_66 = eq(empty, UInt<1>("h00")) - node T_68 = and(UInt<1>("h00"), io.enq.valid) - node T_69 = or(T_66, T_68) - io.deq.valid <= T_69 - node T_71 = eq(full, UInt<1>("h00")) - node T_73 = and(UInt<1>("h00"), io.deq.ready) - node T_74 = or(T_71, T_73) - io.enq.ready <= T_74 - infer mport T_75 = ram[T_28], clk - node T_76 = mux(maybe_flow, io.enq.bits, T_75) - io.deq.bits <= T_76 - node ptr_diff = subw(T_26, T_28) - node T_78 = and(maybe_full, ptr_match) - node T_79 = cat(T_78, ptr_diff) - io.count <= T_79 + node T_68 = eq(empty, UInt<1>("h00")) + node T_70 = and(UInt<1>("h00"), io.enq.valid) + node T_71 = or(T_68, T_70) + io.deq.valid <= T_71 + node T_73 = eq(full, UInt<1>("h00")) + node T_75 = and(UInt<1>("h00"), io.deq.ready) + node T_76 = or(T_73, T_75) + io.enq.ready <= T_76 + infer mport T_77 = ram[T_28], clk + node T_78 = mux(maybe_flow, io.enq.bits, T_77) + io.deq.bits <= T_78 + node T_79 = sub(T_26, T_28) + node ptr_diff = tail(T_79, 1) + node T_81 = and(maybe_full, ptr_match) + node T_82 = cat(T_81, ptr_diff) + io.count <= T_82 module Top : input clk : Clock input reset : UInt<1> output io : {host : {clk : UInt<1>, clk_edge : UInt<1>, flip in : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, out : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<16>}, debug_stats_csr : UInt<1>}, mem_backup_ctrl : {flip en : UInt<1>, flip in_valid : UInt<1>, flip out_ready : UInt<1>, out_valid : UInt<1>}, mem : {aw : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, w : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, last : UInt<1>, strb : UInt<8>, user : UInt<1>}}, flip b : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, id : UInt<5>, user : UInt<1>}}, ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, flip r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}}[1]} - io.mem[0].r.ready <= UInt<1>("h00") - io.mem[0].ar.bits.user <= UInt<1>("h00") - io.mem[0].ar.bits.id <= UInt<1>("h00") - io.mem[0].ar.bits.region <= UInt<1>("h00") - io.mem[0].ar.bits.qos <= UInt<1>("h00") - io.mem[0].ar.bits.prot <= UInt<1>("h00") - io.mem[0].ar.bits.cache <= UInt<1>("h00") - io.mem[0].ar.bits.lock <= UInt<1>("h00") - io.mem[0].ar.bits.burst <= UInt<1>("h00") - io.mem[0].ar.bits.size <= UInt<1>("h00") - io.mem[0].ar.bits.len <= UInt<1>("h00") - io.mem[0].ar.bits.addr <= UInt<1>("h00") - io.mem[0].ar.valid <= UInt<1>("h00") - io.mem[0].b.ready <= UInt<1>("h00") - io.mem[0].w.bits.user <= UInt<1>("h00") - io.mem[0].w.bits.strb <= UInt<1>("h00") - io.mem[0].w.bits.last <= UInt<1>("h00") - io.mem[0].w.bits.data <= UInt<1>("h00") - io.mem[0].w.valid <= UInt<1>("h00") - io.mem[0].aw.bits.user <= UInt<1>("h00") - io.mem[0].aw.bits.id <= UInt<1>("h00") - io.mem[0].aw.bits.region <= UInt<1>("h00") - io.mem[0].aw.bits.qos <= UInt<1>("h00") - io.mem[0].aw.bits.prot <= UInt<1>("h00") - io.mem[0].aw.bits.cache <= UInt<1>("h00") - io.mem[0].aw.bits.lock <= UInt<1>("h00") - io.mem[0].aw.bits.burst <= UInt<1>("h00") - io.mem[0].aw.bits.size <= UInt<1>("h00") - io.mem[0].aw.bits.len <= UInt<1>("h00") - io.mem[0].aw.bits.addr <= UInt<1>("h00") - io.mem[0].aw.valid <= UInt<1>("h00") - io.mem_backup_ctrl.out_valid <= UInt<1>("h00") - io.host.debug_stats_csr <= UInt<1>("h00") - io.host.out.bits <= UInt<1>("h00") - io.host.out.valid <= UInt<1>("h00") - io.host.in.ready <= UInt<1>("h00") - io.host.clk_edge <= UInt<1>("h00") - io.host.clk <= UInt<1>("h00") + io is invalid inst uncore of Uncore - uncore.io.dma[0].resp.ready <= UInt<1>("h00") - uncore.io.dma[0].req.bits.size <= UInt<1>("h00") - uncore.io.dma[0].req.bits.length <= UInt<1>("h00") - uncore.io.dma[0].req.bits.dest <= UInt<1>("h00") - uncore.io.dma[0].req.bits.source <= UInt<1>("h00") - uncore.io.dma[0].req.bits.cmd <= UInt<1>("h00") - uncore.io.dma[0].req.bits.client_xact_id <= UInt<1>("h00") - uncore.io.dma[0].req.valid <= UInt<1>("h00") - uncore.io.mmio.r.bits.user <= UInt<1>("h00") - uncore.io.mmio.r.bits.id <= UInt<1>("h00") - uncore.io.mmio.r.bits.last <= UInt<1>("h00") - uncore.io.mmio.r.bits.data <= UInt<1>("h00") - uncore.io.mmio.r.bits.resp <= UInt<1>("h00") - uncore.io.mmio.r.valid <= UInt<1>("h00") - uncore.io.mmio.ar.ready <= UInt<1>("h00") - uncore.io.mmio.b.bits.user <= UInt<1>("h00") - uncore.io.mmio.b.bits.id <= UInt<1>("h00") - uncore.io.mmio.b.bits.resp <= UInt<1>("h00") - uncore.io.mmio.b.valid <= UInt<1>("h00") - uncore.io.mmio.w.ready <= UInt<1>("h00") - uncore.io.mmio.aw.ready <= UInt<1>("h00") - uncore.io.mem_backup_ctrl.out_ready <= UInt<1>("h00") - uncore.io.mem_backup_ctrl.in_valid <= UInt<1>("h00") - uncore.io.mem_backup_ctrl.en <= UInt<1>("h00") - uncore.io.htif[0].debug_stats_csr <= UInt<1>("h00") - uncore.io.htif[0].csr.resp.bits <= UInt<1>("h00") - uncore.io.htif[0].csr.resp.valid <= UInt<1>("h00") - uncore.io.htif[0].csr.req.ready <= UInt<1>("h00") - uncore.io.tiles_uncached[0].grant.ready <= UInt<1>("h00") - uncore.io.tiles_uncached[0].acquire.bits.data <= UInt<1>("h00") - uncore.io.tiles_uncached[0].acquire.bits.union <= UInt<1>("h00") - uncore.io.tiles_uncached[0].acquire.bits.a_type <= UInt<1>("h00") - uncore.io.tiles_uncached[0].acquire.bits.is_builtin_type <= UInt<1>("h00") - uncore.io.tiles_uncached[0].acquire.bits.addr_beat <= UInt<1>("h00") - uncore.io.tiles_uncached[0].acquire.bits.client_xact_id <= UInt<1>("h00") - uncore.io.tiles_uncached[0].acquire.bits.addr_block <= UInt<1>("h00") - uncore.io.tiles_uncached[0].acquire.valid <= UInt<1>("h00") - uncore.io.tiles_cached[0].release.bits.data <= UInt<1>("h00") - uncore.io.tiles_cached[0].release.bits.r_type <= UInt<1>("h00") - uncore.io.tiles_cached[0].release.bits.voluntary <= UInt<1>("h00") - uncore.io.tiles_cached[0].release.bits.client_xact_id <= UInt<1>("h00") - uncore.io.tiles_cached[0].release.bits.addr_block <= UInt<1>("h00") - uncore.io.tiles_cached[0].release.bits.addr_beat <= UInt<1>("h00") - uncore.io.tiles_cached[0].release.valid <= UInt<1>("h00") - uncore.io.tiles_cached[0].probe.ready <= UInt<1>("h00") - uncore.io.tiles_cached[0].grant.ready <= UInt<1>("h00") - uncore.io.tiles_cached[0].acquire.bits.data <= UInt<1>("h00") - uncore.io.tiles_cached[0].acquire.bits.union <= UInt<1>("h00") - uncore.io.tiles_cached[0].acquire.bits.a_type <= UInt<1>("h00") - uncore.io.tiles_cached[0].acquire.bits.is_builtin_type <= UInt<1>("h00") - uncore.io.tiles_cached[0].acquire.bits.addr_beat <= UInt<1>("h00") - uncore.io.tiles_cached[0].acquire.bits.client_xact_id <= UInt<1>("h00") - uncore.io.tiles_cached[0].acquire.bits.addr_block <= UInt<1>("h00") - uncore.io.tiles_cached[0].acquire.valid <= UInt<1>("h00") - uncore.io.mem[0].r.bits.user <= UInt<1>("h00") - uncore.io.mem[0].r.bits.id <= UInt<1>("h00") - uncore.io.mem[0].r.bits.last <= UInt<1>("h00") - uncore.io.mem[0].r.bits.data <= UInt<1>("h00") - uncore.io.mem[0].r.bits.resp <= UInt<1>("h00") - uncore.io.mem[0].r.valid <= UInt<1>("h00") - uncore.io.mem[0].ar.ready <= UInt<1>("h00") - uncore.io.mem[0].b.bits.user <= UInt<1>("h00") - uncore.io.mem[0].b.bits.id <= UInt<1>("h00") - uncore.io.mem[0].b.bits.resp <= UInt<1>("h00") - uncore.io.mem[0].b.valid <= UInt<1>("h00") - uncore.io.mem[0].w.ready <= UInt<1>("h00") - uncore.io.mem[0].aw.ready <= UInt<1>("h00") - uncore.io.host.out.ready <= UInt<1>("h00") - uncore.io.host.in.bits <= UInt<1>("h00") - uncore.io.host.in.valid <= UInt<1>("h00") + uncore.io is invalid uncore.clk <= clk uncore.reset <= reset - inst T_739 of RocketTile - T_739.io.dma.resp.bits.status <= UInt<1>("h00") - T_739.io.dma.resp.bits.client_xact_id <= UInt<1>("h00") - T_739.io.dma.resp.valid <= UInt<1>("h00") - T_739.io.dma.req.ready <= UInt<1>("h00") - T_739.io.host.csr.resp.ready <= UInt<1>("h00") - T_739.io.host.csr.req.bits.data <= UInt<1>("h00") - T_739.io.host.csr.req.bits.addr <= UInt<1>("h00") - T_739.io.host.csr.req.bits.rw <= UInt<1>("h00") - T_739.io.host.csr.req.valid <= UInt<1>("h00") - T_739.io.host.id <= UInt<1>("h00") - T_739.io.host.reset <= UInt<1>("h00") - T_739.io.uncached[0].grant.bits.data <= UInt<1>("h00") - T_739.io.uncached[0].grant.bits.g_type <= UInt<1>("h00") - T_739.io.uncached[0].grant.bits.is_builtin_type <= UInt<1>("h00") - T_739.io.uncached[0].grant.bits.manager_xact_id <= UInt<1>("h00") - T_739.io.uncached[0].grant.bits.client_xact_id <= UInt<1>("h00") - T_739.io.uncached[0].grant.bits.addr_beat <= UInt<1>("h00") - T_739.io.uncached[0].grant.valid <= UInt<1>("h00") - T_739.io.uncached[0].acquire.ready <= UInt<1>("h00") - T_739.io.cached[0].release.ready <= UInt<1>("h00") - T_739.io.cached[0].probe.bits.p_type <= UInt<1>("h00") - T_739.io.cached[0].probe.bits.addr_block <= UInt<1>("h00") - T_739.io.cached[0].probe.valid <= UInt<1>("h00") - T_739.io.cached[0].grant.bits.data <= UInt<1>("h00") - T_739.io.cached[0].grant.bits.g_type <= UInt<1>("h00") - T_739.io.cached[0].grant.bits.is_builtin_type <= UInt<1>("h00") - T_739.io.cached[0].grant.bits.manager_xact_id <= UInt<1>("h00") - T_739.io.cached[0].grant.bits.client_xact_id <= UInt<1>("h00") - T_739.io.cached[0].grant.bits.addr_beat <= UInt<1>("h00") - T_739.io.cached[0].grant.valid <= UInt<1>("h00") - T_739.io.cached[0].acquire.ready <= UInt<1>("h00") - T_739.clk <= clk - T_739.reset <= uncore.io.htif[0].reset - T_739.io.host.id <= UInt<1>("h00") - reg T_772 : UInt<1>, clk, UInt<1>("h00"), T_772 - T_772 <= uncore.io.htif[0].reset - reg T_773 : UInt<1>, clk, UInt<1>("h00"), T_773 - T_773 <= T_772 - T_739.io.host.reset <= T_773 - inst T_778 of Queue_124 - T_778.io.deq.ready <= UInt<1>("h00") - T_778.io.enq.bits.data <= UInt<1>("h00") - T_778.io.enq.bits.addr <= UInt<1>("h00") - T_778.io.enq.bits.rw <= UInt<1>("h00") - T_778.io.enq.valid <= UInt<1>("h00") - T_778.clk <= clk - T_778.reset <= reset - T_778.io.enq.valid <= uncore.io.htif[0].csr.req.valid - T_778.io.enq.bits <- uncore.io.htif[0].csr.req.bits - uncore.io.htif[0].csr.req.ready <= T_778.io.enq.ready - T_739.io.host.csr.req <- T_778.io.deq - inst T_785 of Queue_125 - T_785.io.deq.ready <= UInt<1>("h00") - T_785.io.enq.bits <= UInt<1>("h00") - T_785.io.enq.valid <= UInt<1>("h00") - T_785.clk <= clk - T_785.reset <= reset - T_785.io.enq.valid <= T_739.io.host.csr.resp.valid - T_785.io.enq.bits <= T_739.io.host.csr.resp.bits - T_739.io.host.csr.resp.ready <= T_785.io.enq.ready - uncore.io.htif[0].csr.resp <- T_785.io.deq - uncore.io.htif[0].debug_stats_csr <= T_739.io.host.debug_stats_csr - uncore.io.tiles_cached[0] <- T_739.io.cached[0] - uncore.io.tiles_uncached[0] <- T_739.io.uncached[0] + inst T_669 of RocketTile + T_669.io is invalid + T_669.clk <= clk + T_669.reset <= uncore.io.htif[0].reset + T_669.io.host.id <= UInt<1>("h00") + reg T_671 : UInt<1>, clk + T_671 <= uncore.io.htif[0].reset + reg T_672 : UInt<1>, clk + T_672 <= T_671 + T_669.io.host.reset <= T_672 + inst T_677 of Queue_124 + T_677.io is invalid + T_677.clk <= clk + T_677.reset <= reset + T_677.io.enq.valid <= uncore.io.htif[0].csr.req.valid + T_677.io.enq.bits <- uncore.io.htif[0].csr.req.bits + uncore.io.htif[0].csr.req.ready <= T_677.io.enq.ready + T_669.io.host.csr.req <- T_677.io.deq + inst T_679 of Queue_125 + T_679.io is invalid + T_679.clk <= clk + T_679.reset <= reset + T_679.io.enq.valid <= T_669.io.host.csr.resp.valid + T_679.io.enq.bits <= T_669.io.host.csr.resp.bits + T_669.io.host.csr.resp.ready <= T_679.io.enq.ready + uncore.io.htif[0].csr.resp <- T_679.io.deq + uncore.io.htif[0].debug_stats_csr <= T_669.io.host.debug_stats_csr + uncore.io.tiles_cached[0] <- T_669.io.cached[0] + uncore.io.tiles_uncached[0] <- T_669.io.uncached[0] io.host <- uncore.io.host io.mem_backup_ctrl <- uncore.io.mem_backup_ctrl - inst T_801 of Queue_36 - T_801.io.deq.ready <= UInt<1>("h00") - T_801.io.enq.bits.user <= UInt<1>("h00") - T_801.io.enq.bits.id <= UInt<1>("h00") - T_801.io.enq.bits.region <= UInt<1>("h00") - T_801.io.enq.bits.qos <= UInt<1>("h00") - T_801.io.enq.bits.prot <= UInt<1>("h00") - T_801.io.enq.bits.cache <= UInt<1>("h00") - T_801.io.enq.bits.lock <= UInt<1>("h00") - T_801.io.enq.bits.burst <= UInt<1>("h00") - T_801.io.enq.bits.size <= UInt<1>("h00") - T_801.io.enq.bits.len <= UInt<1>("h00") - T_801.io.enq.bits.addr <= UInt<1>("h00") - T_801.io.enq.valid <= UInt<1>("h00") - T_801.clk <= clk - T_801.reset <= reset - T_801.io.enq.valid <= uncore.io.mem[0].ar.valid - T_801.io.enq.bits <- uncore.io.mem[0].ar.bits - uncore.io.mem[0].ar.ready <= T_801.io.enq.ready - io.mem[0].ar <- T_801.io.deq - inst T_827 of Queue_36 - T_827.io.deq.ready <= UInt<1>("h00") - T_827.io.enq.bits.user <= UInt<1>("h00") - T_827.io.enq.bits.id <= UInt<1>("h00") - T_827.io.enq.bits.region <= UInt<1>("h00") - T_827.io.enq.bits.qos <= UInt<1>("h00") - T_827.io.enq.bits.prot <= UInt<1>("h00") - T_827.io.enq.bits.cache <= UInt<1>("h00") - T_827.io.enq.bits.lock <= UInt<1>("h00") - T_827.io.enq.bits.burst <= UInt<1>("h00") - T_827.io.enq.bits.size <= UInt<1>("h00") - T_827.io.enq.bits.len <= UInt<1>("h00") - T_827.io.enq.bits.addr <= UInt<1>("h00") - T_827.io.enq.valid <= UInt<1>("h00") - T_827.clk <= clk - T_827.reset <= reset - T_827.io.enq.valid <= uncore.io.mem[0].aw.valid - T_827.io.enq.bits <- uncore.io.mem[0].aw.bits - uncore.io.mem[0].aw.ready <= T_827.io.enq.ready - io.mem[0].aw <- T_827.io.deq - inst T_846 of Queue_74 - T_846.io.deq.ready <= UInt<1>("h00") - T_846.io.enq.bits.user <= UInt<1>("h00") - T_846.io.enq.bits.strb <= UInt<1>("h00") - T_846.io.enq.bits.last <= UInt<1>("h00") - T_846.io.enq.bits.data <= UInt<1>("h00") - T_846.io.enq.valid <= UInt<1>("h00") - T_846.clk <= clk - T_846.reset <= reset - T_846.io.enq.valid <= uncore.io.mem[0].w.valid - T_846.io.enq.bits <- uncore.io.mem[0].w.bits - uncore.io.mem[0].w.ready <= T_846.io.enq.ready - io.mem[0].w <- T_846.io.deq - inst T_859 of Queue_75 - T_859.io.deq.ready <= UInt<1>("h00") - T_859.io.enq.bits.user <= UInt<1>("h00") - T_859.io.enq.bits.id <= UInt<1>("h00") - T_859.io.enq.bits.last <= UInt<1>("h00") - T_859.io.enq.bits.data <= UInt<1>("h00") - T_859.io.enq.bits.resp <= UInt<1>("h00") - T_859.io.enq.valid <= UInt<1>("h00") - T_859.clk <= clk - T_859.reset <= reset - T_859.io.enq.valid <= io.mem[0].r.valid - T_859.io.enq.bits <- io.mem[0].r.bits - io.mem[0].r.ready <= T_859.io.enq.ready - uncore.io.mem[0].r <- T_859.io.deq - inst T_871 of Queue_76 - T_871.io.deq.ready <= UInt<1>("h00") - T_871.io.enq.bits.user <= UInt<1>("h00") - T_871.io.enq.bits.id <= UInt<1>("h00") - T_871.io.enq.bits.resp <= UInt<1>("h00") - T_871.io.enq.valid <= UInt<1>("h00") - T_871.clk <= clk - T_871.reset <= reset - T_871.io.enq.valid <= io.mem[0].b.valid - T_871.io.enq.bits <- io.mem[0].b.bits - io.mem[0].b.ready <= T_871.io.enq.ready - uncore.io.mem[0].b <- T_871.io.deq + inst T_692 of Queue_36 + T_692.io is invalid + T_692.clk <= clk + T_692.reset <= reset + T_692.io.enq.valid <= uncore.io.mem[0].ar.valid + T_692.io.enq.bits <- uncore.io.mem[0].ar.bits + uncore.io.mem[0].ar.ready <= T_692.io.enq.ready + io.mem[0].ar <- T_692.io.deq + inst T_705 of Queue_36 + T_705.io is invalid + T_705.clk <= clk + T_705.reset <= reset + T_705.io.enq.valid <= uncore.io.mem[0].aw.valid + T_705.io.enq.bits <- uncore.io.mem[0].aw.bits + uncore.io.mem[0].aw.ready <= T_705.io.enq.ready + io.mem[0].aw <- T_705.io.deq + inst T_711 of Queue_74 + T_711.io is invalid + T_711.clk <= clk + T_711.reset <= reset + T_711.io.enq.valid <= uncore.io.mem[0].w.valid + T_711.io.enq.bits <- uncore.io.mem[0].w.bits + uncore.io.mem[0].w.ready <= T_711.io.enq.ready + io.mem[0].w <- T_711.io.deq + inst T_718 of Queue_75 + T_718.io is invalid + T_718.clk <= clk + T_718.reset <= reset + T_718.io.enq.valid <= io.mem[0].r.valid + T_718.io.enq.bits <- io.mem[0].r.bits + io.mem[0].r.ready <= T_718.io.enq.ready + uncore.io.mem[0].r <- T_718.io.deq + inst T_723 of Queue_76 + T_723.io is invalid + T_723.clk <= clk + T_723.reset <= reset + T_723.io.enq.valid <= io.mem[0].b.valid + T_723.io.enq.bits <- io.mem[0].b.bits + io.mem[0].b.ready <= T_723.io.enq.ready + uncore.io.mem[0].b <- T_723.io.deq io.mem[0].ar.bits.cache <= UInt<4>("h03") io.mem[0].aw.bits.cache <= UInt<4>("h03") inst errslave of NastiErrorSlave_40 - errslave.io.r.ready <= UInt<1>("h00") - errslave.io.ar.bits.user <= UInt<1>("h00") - errslave.io.ar.bits.id <= UInt<1>("h00") - errslave.io.ar.bits.region <= UInt<1>("h00") - errslave.io.ar.bits.qos <= UInt<1>("h00") - errslave.io.ar.bits.prot <= UInt<1>("h00") - errslave.io.ar.bits.cache <= UInt<1>("h00") - errslave.io.ar.bits.lock <= UInt<1>("h00") - errslave.io.ar.bits.burst <= UInt<1>("h00") - errslave.io.ar.bits.size <= UInt<1>("h00") - errslave.io.ar.bits.len <= UInt<1>("h00") - errslave.io.ar.bits.addr <= UInt<1>("h00") - errslave.io.ar.valid <= UInt<1>("h00") - errslave.io.b.ready <= UInt<1>("h00") - errslave.io.w.bits.user <= UInt<1>("h00") - errslave.io.w.bits.strb <= UInt<1>("h00") - errslave.io.w.bits.last <= UInt<1>("h00") - errslave.io.w.bits.data <= UInt<1>("h00") - errslave.io.w.valid <= UInt<1>("h00") - errslave.io.aw.bits.user <= UInt<1>("h00") - errslave.io.aw.bits.id <= UInt<1>("h00") - errslave.io.aw.bits.region <= UInt<1>("h00") - errslave.io.aw.bits.qos <= UInt<1>("h00") - errslave.io.aw.bits.prot <= UInt<1>("h00") - errslave.io.aw.bits.cache <= UInt<1>("h00") - errslave.io.aw.bits.lock <= UInt<1>("h00") - errslave.io.aw.bits.burst <= UInt<1>("h00") - errslave.io.aw.bits.size <= UInt<1>("h00") - errslave.io.aw.bits.len <= UInt<1>("h00") - errslave.io.aw.bits.addr <= UInt<1>("h00") - errslave.io.aw.valid <= UInt<1>("h00") + errslave.io is invalid errslave.clk <= clk errslave.reset <= reset errslave.io <- uncore.io.mmio |