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| author | Albert Magyar | 2020-03-13 15:38:53 -0700 |
|---|---|---|
| committer | GitHub | 2020-03-13 15:38:53 -0700 |
| commit | f89f39342f166dc4f2caec4dcb5d2e7dc6e58b70 (patch) | |
| tree | b814ad1d17a8064f2f4a8ebe81f794eb9e141448 | |
| parent | 5c0c0018d812d57270035a9d3bd82e2289acf4ec (diff) | |
[spec] Update Mid FIRRTL spec to reflect removal of subaccesses (#1451)
| -rw-r--r-- | spec/spec.pdf | bin | 275420 -> 275443 bytes | |||
| -rw-r--r-- | spec/spec.tex | 1 |
2 files changed, 1 insertions, 0 deletions
diff --git a/spec/spec.pdf b/spec/spec.pdf Binary files differindex 5b967bbe..89197101 100644 --- a/spec/spec.pdf +++ b/spec/spec.pdf diff --git a/spec/spec.tex b/spec/spec.tex index 70b073c3..45c25d4b 100644 --- a/spec/spec.tex +++ b/spec/spec.tex @@ -1667,6 +1667,7 @@ A FIRRTL circuit is defined to be a valid MidFIRRTL circuit if it obeys the foll \begin{itemize} \item All widths must be explicitly defined. \item The conditional statement is not used. +\item The dynamic subaccess expression is not used. \item All components are connected to exactly once. \end{itemize} |