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| author | azidar | 2015-04-16 10:15:52 -0700 |
|---|---|---|
| committer | azidar | 2015-04-16 10:15:52 -0700 |
| commit | f742fe90ab7f56fb5c7b7022956ba68a2a60a8f5 (patch) | |
| tree | e1dc8292240f8e2e4f13d366e7b46e4aad5f3a62 | |
| parent | 88a9b1721b799275238c7d601643cf030a73f99c (diff) | |
Updated TODO
| -rw-r--r-- | TODO | 15 |
1 files changed, 14 insertions, 1 deletions
@@ -33,6 +33,14 @@ Well-formed low firrtl ======== Other Passes ======== PrimOp lowering +======== Consultations ======== +Patrick: + subword accesses (extractor?) + draft example +Stephen: + width equality + pin stephen on an example + ======== Think About ======== annotation system zero-width wires @@ -70,10 +78,15 @@ Overflow checks for add/add-wrap Check combinational Fast C++ where wires/register/instances are predicated +======== FIRRTL++ ========= +Variable size FIFOs +TruthTable node +Custom types? Parameterized Types? -======== Next layer components ======= +======== Next Layer Components ======= Accelerator with config registers Schedulable Decouple Nack Scheduler + |
