Fixed performance bug in backend. Added renaming

5 files changed, 65 insertions, 46 deletions

diff --git a/Makefile b/Makefile
index 6eda3cc3..b0c200d5 100644
--- a/Makefile
+++ b/Makefile
@@ -52,7 +52,7 @@ units = ALUTop Datapath Control Core
 v     = $(addsuffix .fir.v, $(units))
 
 $(units): % :
-	firrtl -X verilog -i test/chisel3/$*.fir -o test/chisel3/$*.fir.v -p c
+	firrtl -X verilog -i test/chisel3/$*.fir -o test/chisel3/$*.fir.v
 	scp test/chisel3/$*.fir.v adamiz@a5:/scratch/adamiz/firrtl-all/riscv-mini/generated-src/$*.v
 
 done:
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index b87c654e..2402d747 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -82,8 +82,8 @@ public defn run-passes (c:Circuit,ls:List<Pass>) :
       if PRINT-CIRCUITS : println(name(p))
       c* = pass(p)(c*)
       if PRINT-CIRCUITS : print(c*)
-      if PRINT-CIRCUITS : println-all(["Finished " name(p) "\n"])
       val current-time = current-time-us()
+      println-all(["Finished " name(p) "\n"])
       println-all(["Time since start: " current-time - start-time])
       println-all(["Time for this pass: " current-time - t])
       t = current-time
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index 608b47d2..e36ec06d 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -774,7 +774,7 @@ public defn check-low-form (c:Circuit) -> Circuit :
       for p in ports(m) do :
          check-low-form-t(info(p),type(p),name(p))
 
-      val assigned? = Vector<Symbol>()
+      val assigned? = HashTable<Symbol,True>(symbol-hash)
       val insts = Vector<Symbol>()
       val mems = Vector<Symbol>()
       defn check-correct-exp (info:FileInfo,e:Expression) -> False :
@@ -811,8 +811,8 @@ public defn check-low-form (c:Circuit) -> Circuit :
                match(loc(s)) :
                   (e:Ref|Subfield) : 
                      val n* = to-symbol $ to-string $ e
-                     if contains?(assigned?,n*) : add(errors,SingleAssignment(info(s),n*))
-                     else : add(assigned?,to-symbol $ to-string $ e)
+                     if key?(assigned?,n*) : add(errors,SingleAssignment(info(s),n*))
+                     else : assigned?[to-symbol $ to-string $ e] = true
                   (e) : check-correct-exp(info(s),e)
             (s:EmptyStmt) : false
             (s:Begin) : do(check-low-form-s,s)
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index c6973115..c4d6a58f 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -286,9 +286,11 @@ defmethod map (f: Type -> Type, e: WIndex) :
 ;    removed, except _.
 
 public defstruct RemoveSpecialChars <: Pass
-public defmethod pass (b:RemoveSpecialChars) -> (Circuit -> Circuit) : remove-special-chars
+public defmethod pass (b:RemoveSpecialChars) -> (Circuit -> Circuit) : 
+   remove-special-chars
 public defmethod name (b:RemoveSpecialChars) -> String : "Remove Special Characters"
 public defmethod short-name (b:RemoveSpecialChars) -> String : "rem-spec-chars"
+public defmulti 
 
 ;------------ Helper Functions -------------
 
@@ -2077,7 +2079,7 @@ defn split-exp (c:Circuit) :
             do(f,s)
          (s:Connect) : 
             val exp* = map(split-exp-e{_,full-name(loc(s)),info(s)},exp(s))
-            add(v,Connect(info(s),loc(s),exp(s)))
+            add(v,Connect(info(s),loc(s),exp*))
          (s:DefNode) : 
             val exp* = map(split-exp-e{_,name(s),info(s)},value(s))
             add(v,DefNode(info(s),name(s),exp*))
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index 29112271..d4165bb4 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -66,25 +66,27 @@ defn emit (e:Expression) -> String :
       (e:Subfield) : error("Non-supported expression")
       (e:Index) : error("Non-supported expression")
       (e:DoPrim) : 
-         val sargs = map(emit-as-type{_,type(e)},args(e))
-         val xargs = map(emit-signed-if-any{_,args(e)},args(e))
+         ;val sargs = map(emit-as-type{_,type(e)},args(e))
+         ;val xargs = map(emit-signed-if-any{_,args(e)},args(e))
          string-join $ switch {_ == op(e)} :
-            ADD-OP : [sargs[0] " + " sargs[1]]
-            SUB-OP : [sargs[0] " - " sargs[1]]
-            MUL-OP : [sargs[0] " * " sargs[1] ]
-            DIV-OP : [sargs[0] " / " sargs[1] ]
-            MOD-OP : [sargs[0] " % " sargs[1] ]
-            QUO-OP : [sargs[0] " / " sargs[1] ]
-            REM-OP : [sargs[0] " % " sargs[1] ]
-            ADD-WRAP-OP : [sargs[0], " + " sargs[1]]
-            SUB-WRAP-OP : [sargs[0], " - " sargs[1]]
-            LESS-OP : [xargs[0] " < " xargs[1]]
-            LESS-EQ-OP : [xargs[0] " <= " xargs[1]]
-            GREATER-OP : [xargs[0] " > " xargs[1]]
-            GREATER-EQ-OP : [xargs[0] " >= " xargs[1]]
-            NEQUAL-OP : [xargs[0] " != " xargs[1]]
-            EQUAL-OP : [xargs[0] " == " xargs[1]]
-            MUX-OP : [emit(args(e)[0]) " ? " sargs[1] " : " sargs[2]]
+            ADD-OP : [emit-as-type(args(e)[0],type(e)) " + " emit-as-type(args(e)[1],type(e))]
+            SUB-OP : [emit-as-type(args(e)[0],type(e)) " - " emit-as-type(args(e)[1],type(e))]
+            MUL-OP : [emit-as-type(args(e)[0],type(e)) " * " emit-as-type(args(e)[1],type(e)) ]
+            DIV-OP : [emit-as-type(args(e)[0],type(e)) " / " emit-as-type(args(e)[1],type(e)) ]
+            MOD-OP : [emit-as-type(args(e)[0],type(e)) " % " emit-as-type(args(e)[1],type(e)) ]
+            QUO-OP : [emit-as-type(args(e)[0],type(e)) " / " emit-as-type(args(e)[1],type(e)) ]
+            REM-OP : [emit-as-type(args(e)[0],type(e)) " % " emit-as-type(args(e)[1],type(e)) ]
+            ADD-WRAP-OP : [emit-as-type(args(e)[0],type(e)), " + " emit-as-type(args(e)[1],type(e))]
+            SUB-WRAP-OP : [emit-as-type(args(e)[0],type(e)), " - " emit-as-type(args(e)[1],type(e))]
+            LESS-OP : [emit-signed-if-any(args(e)[0],args(e)) " < " emit-signed-if-any(args(e)[1],args(e))]
+            LESS-EQ-OP : [emit-signed-if-any(args(e)[0],args(e)) " <= " emit-signed-if-any(args(e)[1],args(e))]
+            GREATER-OP : [emit-signed-if-any(args(e)[0],args(e)) " > " emit-signed-if-any(args(e)[1],args(e))]
+            GREATER-EQ-OP : [emit-signed-if-any(args(e)[0],args(e)) " >= " emit-signed-if-any(args(e)[1],args(e))]
+            NEQUAL-OP : [emit-signed-if-any(args(e)[0],args(e)) " != " emit-signed-if-any(args(e)[1],args(e))]
+            EQUAL-OP : [emit-signed-if-any(args(e)[0],args(e)) " == " emit-signed-if-any(args(e)[1],args(e))]
+            MUX-OP : 
+               val en = emit(args(e)[0])
+               [en " ? " emit-as-type(args(e)[1],type(e)) " : " emit-as-type(args(e)[2],type(e))]
             PAD-OP : 
                val x = args(e)[0]
                val w = width!(type(x))
@@ -97,43 +99,42 @@ defn emit (e:Expression) -> String :
                ["$unsigned(" emit(args(e)[0]) ")"]
             AS-SINT-OP : 
                ["$signed(" emit(args(e)[0]) ")"]
-            DYN-SHIFT-LEFT-OP : [sargs[0] " << " emit(args(e)[1])]
+            DYN-SHIFT-LEFT-OP : [emit-as-type(args(e)[0],type(e)) " << " emit(args(e)[1])]
             DYN-SHIFT-RIGHT-OP : 
-               if type(e) typeof SIntType : [sargs[0] " >>> " emit(args(e)[1])]
-               else : [sargs[0] " >> " emit(args(e)[1])]
-            SHIFT-LEFT-OP : [sargs[0] " << " consts(e)[0]]
+               if type(e) typeof SIntType : [emit-as-type(args(e)[0],type(e)) " >>> " emit(args(e)[1])]
+               else : [emit-as-type(args(e)[0],type(e)) " >> " emit(args(e)[1])]
+            SHIFT-LEFT-OP : [emit-as-type(args(e)[0],type(e)) " << " consts(e)[0]]
             SHIFT-RIGHT-OP : 
-               if type(e) typeof SIntType : [sargs[0] " >>> " consts(e)[0]]
-               else : [sargs[0] " >> " consts(e)[0]]
-            NEG-OP : ["-{" sargs[0] "}"]
+               if type(e) typeof SIntType : [emit-as-type(args(e)[0],type(e)) " >>> " consts(e)[0]]
+               else : [emit-as-type(args(e)[0],type(e)) " >> " consts(e)[0]]
+            NEG-OP : ["-{" emit-as-type(args(e)[0],type(e)) "}"]
             CONVERT-OP : 
                match(type(args(e)[0])) :
-                  (t:UIntType) : ["{1'b0," sargs[0] "}"]
-                  (t:SIntType) : [sargs[0]]
-            BIT-NOT-OP : ["!" sargs[0]]
-            BIT-AND-OP : [sargs[0] " & " sargs[1]]
-            BIT-OR-OP : [sargs[0] " | " sargs[1]]
-            BIT-XOR-OP : [sargs[0] " ^ " sargs[1]]
-            CONCAT-OP : ["{" sargs[0] "," sargs[1] "}"]
-            BIT-SELECT-OP : [sargs[0] "[" consts(e)[0] "]"]
-            BITS-SELECT-OP : [sargs[0] "[" consts(e)[0] ":" consts(e)[1] "]"]
+                  (t:UIntType) : ["{1'b0," emit-as-type(args(e)[0],type(e)) "}"]
+                  (t:SIntType) : [emit-as-type(args(e)[0],type(e))]
+            BIT-NOT-OP : ["!" emit-as-type(args(e)[0],type(e))]
+            BIT-AND-OP : [emit-as-type(args(e)[0],type(e)) " & " emit-as-type(args(e)[1],type(e))]
+            BIT-OR-OP : [emit-as-type(args(e)[0],type(e)) " | " emit-as-type(args(e)[1],type(e))]
+            BIT-XOR-OP : [emit-as-type(args(e)[0],type(e)) " ^ " emit-as-type(args(e)[1],type(e))]
+            CONCAT-OP : ["{" emit-as-type(args(e)[0],type(e)) "," emit-as-type(args(e)[1],type(e)) "}"]
+            BIT-SELECT-OP : [emit-as-type(args(e)[0],type(e)) "[" consts(e)[0] "]"]
+            BITS-SELECT-OP : [emit-as-type(args(e)[0],type(e)) "[" consts(e)[0] ":" consts(e)[1] "]"]
             BIT-AND-REDUCE-OP : 
-               var v = sargs[0]
+               var v = emit-as-type(args(e)[0],type(e))
                for x in tail(args(e)) do :
                   v = concat(v, [" & " emit(x)])
                v
             BIT-OR-REDUCE-OP : 
-               var v = sargs[0]
+               var v = emit-as-type(args(e)[0],type(e))
                for x in tail(args(e)) do :
                   v = concat(v, [" | " emit(x)])
                v
             BIT-XOR-REDUCE-OP : 
-               var v = sargs[0]
+               var v = emit-as-type(args(e)[0],type(e))
                for x in tail(args(e)) do :
                   v = concat(v, [" ^ " emit(x)])
                v
 
-
 defn get-name (e:Expression) -> Symbol :
    match(e) :
       (e:Ref) : name(e)
@@ -184,20 +185,35 @@ defn emit-module (m:InModule) :
             val my-clk-update = get?(updates,get-name(clock(s)),Vector<Streamable>())
             if key?(ens,sym) :
                add(my-clk-update,["if(" emit(ens[sym]) ") begin"])
-               add(my-clk-update,["  " sym " <= " emit(cons[sym]) ";"])
+               println(STANDARD-ERROR, "In key?, after first update")
+               val x = cons[sym]
+               println(STANDARD-ERROR, "In key?, after cons[sym]")
+               println(STANDARD-ERROR,x)
+               val y = emit(x)
+               println(STANDARD-ERROR, "In key?, after emit")
+               add(my-clk-update,["  " sym " <= " y ";"])
+               println(STANDARD-ERROR, "In key?, after second update")
                add(my-clk-update,["end"])
+               println(STANDARD-ERROR, "In key?, after all updates")
             else :
+               println(STANDARD-ERROR, "In else, before update")
                add(my-clk-update,[sym " <= " emit(cons[sym]) ";"])
+               println(STANDARD-ERROR, "In else, after update")
+            println(STANDARD-ERROR, "After ifelse, befure update")
             updates[get-name(clock(s))] = my-clk-update
+            println(STANDARD-ERROR, "After ifelse, after update")
          (s:DefMemory) :
+            println(STANDARD-ERROR, s)
             val vtype = type(s) as VectorType
             add(regs,["reg  " get-width(type(vtype)) " " sym " [0:" size(vtype) "];"])
             add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"])
             add(inits,["  " sym "[initvar] = {" width!(type(vtype)) "{$random}};"])
          (s:DefNode) :
+            println(STANDARD-ERROR, s)
             add(wires,["wire " get-width(type(value(s))) " " sym ";"])
             add(assigns,["assign " sym " = " emit(value(s)) ";"])
          (s:DefInstance) : 
+            println(STANDARD-ERROR, s)
             inst-ports[sym] = Vector<Streamable>()
             insts[sym] = name(module(s) as Ref)
             for f in fields(type(module(s)) as BundleType) do :
@@ -207,6 +223,7 @@ defn emit-module (m:InModule) :
                if flip(f) == REVERSE :
                   add(assigns,["assign " n* " = " emit(cons[n*]) ";"])
          (s:DefAccessor) : 
+            println(STANDARD-ERROR, s)
             val mem-declaration = decs[name(source(s) as Ref)] as DefMemory
             switch {_ == acc-dir(s)} :
                READ :