Fix dshl zero-width shift behavior (#2339)

* Fix dshl zero-width shift behavior

Add a special case for dshl handling in the ZeroWidths pass.  If one
expression is shifted by a second, zero-width expression, just return
the first expression.  This prevents a bug where the width will
incorrectly expand due to zero-widths introducing a 1-bit zero
expression.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>

* fixup! Fix dshl zero-width shift behavior

2 files changed, 21 insertions, 0 deletions

diff --git a/src/main/scala/firrtl/passes/ZeroWidth.scala b/src/main/scala/firrtl/passes/ZeroWidth.scala
index 003ab3c9..80eeab12 100644
--- a/src/main/scala/firrtl/passes/ZeroWidth.scala
+++ b/src/main/scala/firrtl/passes/ZeroWidth.scala
@@ -132,6 +132,10 @@ object ZeroWidth extends Transform with DependencyAPIMigration {
         case seq    => DoPrim(Cat, seq, consts, tpe).map(onExp)
       }
     case DoPrim(Andr, Seq(x), _, _) if (bitWidth(x.tpe) == 0) => UIntLiteral(1) // nothing false
+    // The width of the result type of dshl is a function of the width of the shift.  This has to be special cased for
+    // the zero-width shift case to prevent increasing the result width.  Canonicalize a dshl by a zero-width element as
+    // just returning the unshifted expression.
+    case DoPrim(Dshl, Seq(x, a), _, _) if (bitWidth(a.tpe) == 0) => x
     case other =>
       other.tpe match {
         case UIntType(IntWidth(ZERO)) => UIntLiteral(ZERO, IntWidth(BigInt(1)))
diff --git a/src/test/scala/firrtlTests/ZeroWidthTests.scala b/src/test/scala/firrtlTests/ZeroWidthTests.scala
index 654c6f42..4e22ff51 100644
--- a/src/test/scala/firrtlTests/ZeroWidthTests.scala
+++ b/src/test/scala/firrtlTests/ZeroWidthTests.scala
@@ -238,6 +238,23 @@ class ZeroWidthTests extends FirrtlFlatSpec {
     (parse(exec(input))) should be(parse(check))
   }
 
+  "dshl with zero-width" should "canonicalize to the un-shifted expression" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    input x : UInt<0>
+        |    input y : SInt<1>
+        |    output z : SInt<1>
+        |    z <= dshl(y, x)""".stripMargin
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    input y : SInt<1>
+        |    output z : SInt<1>
+        |    z <= y""".stripMargin
+    (parse(exec(input))) should be(parse(check))
+  }
+
   "Memories with zero-width data-type" should "be fully removed" in {
     val input =
       """circuit Foo: