Added custom pass. Does not correctly run, stanza just spins. Requires debugging.

6 files changed, 182 insertions, 2 deletions

diff --git a/Makefile b/Makefile
index ea837d89..07184181 100644
--- a/Makefile
+++ b/Makefile
@@ -35,6 +35,9 @@ chisel3:
 features:
 	cd $(test_dir)/features && lit -v . --path=$(root_dir)/utils/bin/
 
+custom:
+	cd $(test_dir)/custom && lit -v . --path=$(root_dir)/utils/bin/ --max-time=10
+
 clean:
 	rm -f $(test_dir)/*/*/*.out
 	rm -f $(test_dir)/*/*.out
diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza
new file mode 100644
index 00000000..1ca29bdd
--- /dev/null
+++ b/src/main/stanza/custom-compiler.stanza
@@ -0,0 +1,38 @@
+defpackage firrtl/custom-compiler :
+   import core
+   import verse
+   import firrtl/ir-utils
+   import firrtl/ir2
+   import firrtl/passes
+   import firrtl/errors
+   import firrtl/verilog
+   import firrtl/custom-passes
+
+public defstruct InstrumentedVerilog <: Compiler :
+   file: String with: (as-method => true)
+   args: List<String>
+public defmethod passes (c:InstrumentedVerilog) -> List<Pass> :
+   to-list $ [
+      WhenCoverage(args(c)[0],args(c)[1])
+      CheckHighForm(expand-delin)
+      TempElimination()
+      ToWorkingIR()
+      MakeExplicitReset()
+      ResolveKinds()
+      CheckKinds()
+      InferTypes()
+      CheckTypes()
+      ResolveGenders()
+      CheckGenders()
+      ExpandAccessors()
+      LowerToGround()
+      ExpandIndexedConnects()
+      ExpandWhens()
+      InferWidths()
+      SplitExp()
+      ToRealIR()
+      SpecialRename(`#,`_)
+      Verilog(file(c))
+   ]
+
+
diff --git a/src/main/stanza/custom-passes.stanza b/src/main/stanza/custom-passes.stanza
new file mode 100644
index 00000000..d47f6661
--- /dev/null
+++ b/src/main/stanza/custom-passes.stanza
@@ -0,0 +1,81 @@
+defpackage firrtl/custom-passes :
+   import core
+   import verse
+   import firrtl/ir-utils
+   import firrtl/ir2
+
+public defstruct WhenCoverage <: Pass :
+   port-name : String
+   reg-name : String
+public defmethod pass (b:WhenCoverage) -> (Circuit -> Circuit) : when-coverage{port-name(b),reg-name(b),_}
+public defmethod name (b:WhenCoverage) -> String : "When Coverage"
+public defmethod short-name (b:WhenCoverage) -> String : "when-coverage"
+
+;============ Utilz =============
+defn concat-all (ls:List<Expression>) -> Expression :
+   if length(ls) == 0 : error("Shouldn't be here")
+   if length(ls) == 1 : head(ls)
+   else : DoPrim( CONCAT-OP,
+                  list(head(ls),concat-all(tail(ls))),
+                  list(),
+                  UIntType(UnknownWidth()))
+
+;============ When Coverage Pass =============
+;port width = 1 bit per scope + portwidths of all instances
+
+defn when-coverage (port-name:Symbol, reg-name:Symbol, m:InModule) -> InModule :
+   val when-bits = Vector<Ref>()
+   val inst-bits = Vector<Ref>()
+   val sym = HashTable<Symbol,Int>(symbol-hash)
+   val w1 = IntWidth(1)
+   val t1 = UIntType(w1)
+   val u1 = UIntValue(1,w1)
+   defn when-coverage (s:Stmt) -> Stmt :
+      map{when-coverage,_} $ match(s) :
+         (s:Conditionally) : 
+            val ref = Ref(firrtl-gensym(reg-name,sym),t1)
+            add(when-bits,ref)
+            val conseq* = Begin(list(Connect(FileInfo()ref,u1),conseq(s)))
+            Conditionally(info(s),pred(s),conseq*,alt(s))
+         (s:DefInstance) : 
+            val ref = Ref(firrtl-gensym(port-name,sym),t1)
+            add(inst-bits,ref)
+            val sfld = Subfield(Ref(name(s),UnknownType()),port-name,UnknownType())
+            Begin(list(s,Connect(FileInfo(),ref,sfld)))
+         (s) : s
+
+   val body* = when-coverage(body(m))
+   val logic = Vector<Stmt>()
+
+   val w-ls = to-list $ when-bits
+   if length(w-ls) != 0 :
+      val reg-ref = Ref(reg-name,UIntType(IntWidth(length(w-ls))))
+      add{logic,_} $ DefRegister(FileInfo(),name(reg-ref),type(reg-ref))
+      add{logic,_} $ OnReset(FileInfo(),reg-ref,UIntValue(0,IntWidth(length(w-ls))))
+      for (x in w-ls, i in 0 to false) do :
+         add{logic,_} $ DefWire(FileInfo(),name(x),type(x))
+         add{logic,_} $ Connect(FileInfo(),x,DoPrim(BIT-SELECT-OP,list(reg-ref),list(i),UIntType(w1)))
+      add{logic,_} $ Connect(FileInfo(),reg-ref,concat-all(w-ls))
+
+   val i-ls = to-list $ inst-bits
+   if length(i-ls) != 0 :
+      val port-ref = Ref(port-name,UIntType(UnknownWidth()))
+      for (x in i-ls, i in 0 to false) do :
+         add{logic,_} $ DefWire(FileInfo(),name(x),type(x))
+         add{logic,_} $ Connect(FileInfo(),x,UIntValue(0,UnknownWidth()))
+      add{logic,_} $ Connect(FileInfo(),port-ref,concat-all(append(w-ls,i-ls)))
+
+   if length(logic) != 0 :
+      val ports* = List(Port(FileInfo(),port-name,OUTPUT,UIntType(UnknownWidth())),ports(m))
+      val body** = Begin(list(Begin(to-list $ logic),body*))
+      InModule(info(m),name(m),ports*,body**)
+   else : m
+
+public defn when-coverage (port-name:String, reg-name:String, c:Circuit) :
+   val modules* = for m in modules(c) map :
+      match(m) :
+         (m:InModule) : 
+            when-coverage(to-symbol $ port-name,to-symbol $ reg-name,m)
+         (m:ExModule) : m
+   Circuit(info(c),modules*,main(c))
+
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index e92f4854..18e069b4 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -134,11 +134,11 @@ public defstruct Conditionally <: Stmt :
    alt: Stmt
 public defstruct Begin <: Stmt : ;LOW
    body: List<Stmt>
-public defstruct OnReset <: Stmt : ;LOW
+public defstruct OnReset <: Stmt : 
    info: FileInfo with: (as-method => true)
    loc: Expression
    exp: Expression
-public defstruct BulkConnect <: Stmt : ;LOW
+public defstruct BulkConnect <: Stmt : 
    info: FileInfo with: (as-method => true)
    loc: Expression
    exp: Expression
diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza
index 5a7e593d..1a8f6780 100644
--- a/src/main/stanza/firrtl-test-main.stanza
+++ b/src/main/stanza/firrtl-test-main.stanza
@@ -13,6 +13,10 @@
 #include("flo.stanza")
 #include("verilog.stanza")
 
+;Custom Packages
+#include("custom-passes.stanza")
+#include("custom-compiler.stanza")
+
 defpackage firrtl-main :
    import core
    import verse
@@ -22,6 +26,9 @@ defpackage firrtl-main :
    import stz/parser
    import firrtl/ir-utils
    import firrtl/compiler
+   ;Custom Packages
+   import firrtl/custom-passes
+   import firrtl/custom-compiler
 
 defn set-printvars! (p:List<Char>) :
    if contains(p,'t') : PRINT-TYPES = true
@@ -42,11 +49,13 @@ defn get-passes (pass-names:List<String>) -> List<Pass> :
       p as Pass
          
 defn main () :
+   println("HERE")
    val args = commandline-arguments()
    var input = false
    var output = false
    var compiler = false
    val pass-names = Vector<String>()
+   val pass-args = Vector<String>()
    var printvars = ""
    for (s in args, i in 0 to false) do :
       if s == "-i" : input = args[i + 1]
@@ -54,7 +63,9 @@ defn main () :
       if s == "-x" : add(pass-names,args[i + 1])
       if s == "-X" : compiler = args[i + 1]
       if s == "-p" : printvars = args[i + 1]
+      if s == "-s" : add(pass-args,args[i + 1])
 
+   println("THERE")
    if input == false : 
       error("No input file provided. Use -i flag.")
    if output == false : 
@@ -66,12 +77,14 @@ defn main () :
    val c = parse-firrtl(lexed)
    set-printvars!(to-list(printvars))
    
+   println("EVERYWHERE")
    if compiler == false :
       run-passes(c,get-passes(to-list(pass-names)))
    else :
       switch {_ == compiler} :
          "flo" : run-passes(c,StandardFlo(output as String))
          "verilog" : run-passes(c,StandardVerilog(output as String))
+         "verilute" : run-passes(c,InstrumentedVerilog(output as String,to-list $ pass-args))
          else : error("Invalid compiler flag")
 
 main()
diff --git a/test/custom/when-coverage/gcd.fir b/test/custom/when-coverage/gcd.fir
new file mode 100644
index 00000000..d3e9d35b
--- /dev/null
+++ b/test/custom/when-coverage/gcd.fir
@@ -0,0 +1,45 @@
+; RUN: firrtl -i %s -o %s.v -X verilute -s coverage -s when-scope -p c | tee %s.out | FileCheck %s
+
+;CHECK: Verilog
+circuit top :
+   module subtracter :
+      input x : UInt
+      input y : UInt
+      output q : UInt
+      q := sub-wrap(x, y)
+   module gcd :
+      input a : UInt<16>
+      input b : UInt<16>
+      input e : UInt<1>
+      output z : UInt<16>
+      output v : UInt<1>
+      reg x : UInt
+      reg y : UInt
+      on-reset x := UInt(0)
+      on-reset y := UInt(42)
+      when gt(x, y) :
+         inst s of subtracter
+         s.x := x
+         s.y := y
+         x := s.q
+      else :
+         inst s2 of subtracter
+         s2.x := x
+         s2.y := y
+         y := s2.q
+      when e :
+         x := a
+         y := b
+      v := eq(v, UInt(0))
+      z := x
+   module top :
+      input a : UInt<16>
+      input b : UInt<16>
+      output z : UInt
+      inst i of gcd
+      i.a := a
+      i.b := b
+      i.e := UInt(1)
+      z := i.z
+;CHECK: Done!
+