Made things go faster. Still in progress. Expand when now removes

non-referenced declarations that are not instances, but it doesn't work
right now.

5 files changed, 131 insertions, 55 deletions

diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index db6781c5..64d4a7c4 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -77,16 +77,25 @@ public defn run-passes (c:Circuit,ls:List<Pass>) :
    println("Compiling!")
    if PRINT-CIRCUITS : println("Original Circuit")
    if PRINT-CIRCUITS : print(c)
-   val start-time = current-time-us()
+   ;val start-time = current-time-us()
+   val start-time = to-int(to-string(current-time-us() / to-long(1000)))
    var t = start-time
-   val tables = Vector<HashTable<Symbol,HashTable<Symbol,Symbol>>>()
+   val time-table = Vector<[String,Int]>()
    for p in ls do : 
+      println-all(STANDARD-ERROR,["Starting " name(p)])
       if PRINT-CIRCUITS : println(name(p))
       c* = pass(p)(c*)
       if PRINT-CIRCUITS : print(c*)
-      val current-time = current-time-us()
-      println-all(["Finished " name(p) "\n"])
-      println-all(["Time since start: " current-time - start-time])
-      println-all(["Time for this pass: " current-time - t])
+      val current-time = to-int(to-string(current-time-us() / to-long(1000)))
+      println-all(STANDARD-ERROR,["Finished " name(p)])
+      println-all(STANDARD-ERROR,["Milliseconds since start: " current-time - start-time])
+      println-all(STANDARD-ERROR,["Milliseconds for this pass: " current-time - t])
+      println-all(STANDARD-ERROR,["\n"])
+      add(time-table,[name(p), current-time - t])
       t = current-time
-   println("Done!")
+
+   println(STANDARD-ERROR,"===== Time Breakdown =====")
+   for x in time-table do :
+      println-all(STANDARD-ERROR,[x[0] " --- " to-float(x[1] as Int) / to-float(t - start-time) "%"])
+   println(STANDARD-ERROR,"==========================")
+   println(STANDARD-ERROR,"Done!")
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index e36d52a4..d8969dd3 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -283,20 +283,26 @@ public defn check-high-form (c:Circuit) -> Circuit :
       map(check-high-form-t{info,_:Type},e)
       e
 
-   defn check-high-form-s (s:Stmt,names:HashTable<Symbol,True>) -> Stmt :
+   defn check-high-form-s (s:Stmt,names:HashTable<Symbol,True>,mnames:HashTable<Symbol,True>) -> Stmt :
       defn check-name (info:FileInfo,name:Symbol) -> False :
          if key?(names,name) : add(errors,NotUnique(info,name))
       map(check-high-form-t{info(s),_:Type},s)
 
-      map{check-high-form-s{_,names},_} $ { 
-         match(map(check-high-form-e{info(s),_,names},s)) :
-            (s:DefWire|DefRegister) :
+      map{check-high-form-s{_,names,mnames},_} $ { 
+         match(s) : ;map(check-high-form-e{info(s),_,names},s)) :
+            (s:DefWire) : 
                check-name(info(s),name(s))
                names[name(s)] = true
+            (s:DefRegister) :
+               check-name(info(s),name(s))
+               names[name(s)] = true
+               check-high-form-e(info(s),reset(s),names)
+               check-high-form-e(info(s),clock(s),names)
             (s:DefMemory) : 
                check-name(info(s),name(s))
                names[name(s)] = true
                if has-flip?(type(s)) : add(errors, MemWithFlip(info(s), name(s)))
+               check-high-form-e(info(s),clock(s),names)
             (s:DefInstance) : 
                if not contains?(name(module(s) as Ref),map(name,modules(c))) : 
                   add(errors, ModuleNotDefined(info(s),name(module(s) as Ref)))
@@ -304,21 +310,34 @@ public defn check-high-form (c:Circuit) -> Circuit :
                names[name(s)] = true
             (s:DefNode) : 
                check-name(info(s),name(s))
+               check-high-form-e(info(s),value(s),names)
                names[name(s)] = true
             (s:DefAccessor) :
                check-name(info(s),name(s))
+               check-high-form-e(info(s),index(s),names)
+               check-high-form-e(info(s),source(s),names)
                names[name(s)] = true
             (s:Connect) : 
                check-valid-loc(info(s),loc(s))
+               check-high-form-e(info(s),loc(s),names)
+               check-high-form-e(info(s),exp(s),names)
             (s:BulkConnect) : 
                check-valid-loc(info(s),loc(s))
+               check-high-form-e(info(s),loc(s),names)
+               check-high-form-e(info(s),exp(s),names)
+            (s:OnReset) : 
+               check-high-form-e(info(s),loc(s),names)
+               check-high-form-e(info(s),exp(s),names)
+            (s:Conditionally) : 
+               check-high-form-e(info(s),pred(s),names)
             (s) : false
          s }()
 
    defn check-high-form-m (m:Module) -> False :
       val names = HashTable<Symbol,True>(symbol-hash)
+      val mnames = HashTable<Symbol,True>(symbol-hash)
       for m in modules(c) do :
-         names[name(m)] = true
+         mnames[name(m)] = true
       for p in ports(m) do :
          names[name(p)] = true
          ;if name(p) == `reset :
@@ -335,7 +354,7 @@ public defn check-high-form (c:Circuit) -> Circuit :
 
       match(m) :
          (m:ExModule) : false
-         (m:InModule) : check-high-form-s(body(m),names)
+         (m:InModule) : check-high-form-s(body(m),names,mnames)
       ;match(any-prefixes?(names,to-string(sym),to-string(sym))) :
          ;(s:False) : false
          ;(s:String) : add(errors,IsPrefix(info,to-symbol(s)))
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index 5b7c1106..7e07eb8b 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -167,7 +167,7 @@ defsyntax firrtl :
          if not empty?(rest) :
             FPE(rest, "Expected a statement here.")
          InModule(first-info(form),name, ps, Begin(cs))
-      module = (exmodule ?name:#id! #:! (?ps:#port ... ?rest ...)) :
+      module = (extmodule ?name:#id! #:! (?ps:#port ... ?rest ...)) :
          if not empty?(rest) :
             FPE(rest, "Expected a port here.")
          ExModule(first-info(form),name, ps)
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 9a983cff..0118c73b 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -252,7 +252,7 @@ defmethod print (o:OutputStream, m:InModule) :
    print(io,body(m))
 
 defmethod print (o:OutputStream, m:ExModule) :
-   print-all(o, ["exmodule " name(m) " :"])
+   print-all(o, ["extmodule " name(m) " :"])
    print-debug(o,m)
    print(o,"\n")
    val io = IndentedStream(o, 3)
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 7002d7aa..cfcbb36b 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -319,25 +319,25 @@ defn remove-special-chars (c:Circuit) :
          add(n*,get-new-string(c))
       symbol-join(n*)
    defn rename-t (t:Type) -> Type :
-      match(map(rename-t,t)) :
+      match(t) :
          (t:BundleType) : BundleType $
             for f in fields(t) map :
-               Field(rename(name(f)),flip(f),type(f))
-         (e) : e
+               Field(rename(name(f)),flip(f),rename-t(type(f)))
+         (e) : map(rename-t,e)
    defn rename-e (e:Expression) -> Expression :
-      map{rename-t,_} $ match(map(rename-e,e)) :
-         (e:Ref) : Ref(rename(name(e)),type(e))
-         (e:Subfield) : Subfield(exp(e),rename(name(e)),type(e))
-         (e) : e
+      match(e) :
+         (e:Ref) : Ref(rename(name(e)),rename-t(type(e)))
+         (e:Subfield) : Subfield(exp(e),rename(name(e)),rename-t(type(e)))
+         (e) : map(rename-t,map(rename-e,e))
    defn rename-s (s:Stmt) -> Stmt :
-      map{rename-t,_} $ match(map(rename-e,s)) :
-         (s:DefWire) : DefWire(info(s),rename(name(s)),type(s))
-         (s:DefRegister) : DefRegister(info(s),rename(name(s)),type(s),clock(s),reset(s))
+      match(map(rename-e,s)) :
+         (s:DefWire) : DefWire(info(s),rename(name(s)),rename-t(type(s)))
+         (s:DefRegister) : DefRegister(info(s),rename(name(s)),rename-t(type(s)),clock(s),reset(s))
          (s:DefInstance) : DefInstance(info(s),rename(name(s)),module(s))
-         (s:DefMemory) : DefMemory(info(s),rename(name(s)),type(s),seq?(s),clock(s))
+         (s:DefMemory) : DefMemory(info(s),rename(name(s)),rename-t(type(s)) as VectorType,seq?(s),clock(s))
          (s:DefNode) : DefNode(info(s),rename(name(s)),value(s))
          (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),source(s),index(s),acc-dir(s))
-         (s) : map(rename-s,s)
+         (s) : map(rename-t,map(rename-s,s))
 
    Circuit(info(c),modules*, main(c)) where :
       val modules* =
@@ -743,16 +743,14 @@ defn resolve-genders (c:Circuit) :
             genders[n] = g
             done? = false
             g
-         val entry = for kv in genders find :
-            key(kv) == n
+         val entry = get?(genders,n,false)
          match(entry) :
-            (e:KeyValue<Symbol,Gender>) :
-               val value = value(e)
-               if      value == UNKNOWN-GENDER and g == UNKNOWN-GENDER : g
-               else if value != UNKNOWN-GENDER and g == UNKNOWN-GENDER : value
-               else if value == UNKNOWN-GENDER and g != UNKNOWN-GENDER : force-gender(n,g)
-               else : value
-            (e:False) : force-gender(n,g)
+            (g*:Gender) :
+               if      g* == UNKNOWN-GENDER and g == UNKNOWN-GENDER : g
+               else if g* != UNKNOWN-GENDER and g == UNKNOWN-GENDER : g*
+               else if g* == UNKNOWN-GENDER and g != UNKNOWN-GENDER : force-gender(n,g)
+               else : g*
+            (g*:False) : force-gender(n,g)
             
       defn resolve-stmt (s:Stmt) -> Stmt :
          match(s) :
@@ -1281,6 +1279,12 @@ defmethod print (o:OutputStream, sv:SymbolicValue) :
       (sv: SVMux) : print-all(o, ["(" pred(sv) " ? " conseq(sv) " : " alt(sv) ")"])
       (sv: SVNul) : print(o, "SVNUL")
 
+defn map (f: Expression -> Expression, sv:SymbolicValue) -> SymbolicValue :
+   match(sv) :
+      (sv:SVMux) : SVMux(f(pred(sv)),conseq(sv),alt(sv))
+      (sv:SVExp) : SVExp(f(exp(sv)))
+      (sv:SVNul) : sv
+
 defmulti map<?T> (f: SymbolicValue -> SymbolicValue, sv:?T&SymbolicValue) -> T 
 defmethod map (f: SymbolicValue -> SymbolicValue, sv:SymbolicValue) -> SymbolicValue :
    match(sv) :
@@ -1288,15 +1292,18 @@ defmethod map (f: SymbolicValue -> SymbolicValue, sv:SymbolicValue) -> SymbolicV
       (sv) : sv
 
 defn do (f:SymbolicValue -> ?, s:SymbolicValue) -> False :
-   for x in s map :
-      f(x)
-      x
+   defn f* (sv:SymbolicValue) -> SymbolicValue : 
+      f(sv)
+      sv
+   map(f*,s)
    false
+
 defn dor (f:SymbolicValue -> ?, e:SymbolicValue) -> False :
    do(f,e)
-   for x in e map :
+   defn f* (x:SymbolicValue) -> SymbolicValue : 
       dor(f,x)
       x
+   map(f*,e)
    false
 
 defmethod equal? (a:SymbolicValue,b:SymbolicValue) -> True|False :
@@ -1328,13 +1335,13 @@ defn deepcopy (t:HashTable<Symbol,SymbolicValue>) -> HashTable<Symbol,SymbolicVa
       val t0 = HashTable<Symbol,SymbolicValue>(symbol-hash)
       for x in t do :
          t0[key(x)] = value(x)
-defn get-unique-keys (ts:List<HashTable<Symbol,SymbolicValue>>) -> Vector<Symbol> :
-   t0 where :
-      val t0 = Vector<Symbol>()
-      for v in ts do : 
-         for t in v do :
-            val duplicate? = for x in t0 any? : x == key(t)
-            if not duplicate? : add(t0,key(t))
+defn get-unique-keys (ts:List<HashTable<Symbol,SymbolicValue>>) -> Streamable<Symbol> :
+   val h = HashTable<Symbol,True>(symbol-hash)
+   for v in ts do : 
+      for t in v do :
+         h[key(t)] = true
+   keys(h)
+
 defn has-nul? (sv:SymbolicValue) -> True|False :
    var has? = false
    if sv typeof SVNul : has? = true
@@ -1484,6 +1491,33 @@ defn build-tables (s:Stmt,
       (s:Begin) : for s* in body(s) do: build-tables(s*,assign,resets,flattn,rsignals)
       (s:DefMemory|DefNode|EmptyStmt) : false
 
+
+defn mark-referenced (referenced?:HashTable<Symbol,True>, s:Stmt) -> False :
+   defn mark-referenced-e (e:Expression) -> Expression :
+      match(map(mark-referenced-e,e)) :
+         (e:Ref) : 
+            referenced?[name(e)] = true
+            e
+         (e) : e
+   do(mark-referenced{referenced?,_:Stmt},s)
+   map(mark-referenced-e,s)
+   false
+
+defn mark-referenced (referenced?:HashTable<Symbol,True>, sv:SymbolicValue) -> False :
+   defn mark-referenced-e (e:Expression) -> Expression :
+      match(map(mark-referenced-e,e)) :
+         (e:Ref) : 
+            referenced?[name(e)] = true
+            e
+         (e) : e
+   map(mark-referenced-e,sv)
+   false
+
+defn is-referenced? (referenced?:HashTable<Symbol,True>, s:Stmt) -> True|False :
+   match(s) :
+      (s:DefWire|DefRegister|DefAccessor|DefMemory|DefNode) : key?(referenced?,name(s))
+      (s:DefInstance) : true
+               
 ;--------------- Expand Whens Pass -------------------
 
 public defn expand-whens (c:Circuit) -> Circuit :
@@ -1497,7 +1531,10 @@ public defn expand-whens (c:Circuit) -> Circuit :
    
    defn expand-whens (s:Stmt, table:HashTable<Symbol,SymbolicValue>,decs:Vector<Stmt>,cons:Vector<Stmt>) -> Stmt :
       match(map(expand-whens{_,table,decs,cons},s)) : 
-         (s:DefNode|DefMemory) : add(decs,s)
+         (s:DefNode) : 
+            add(decs,s)
+         (s:DefMemory) : 
+            add(decs,s)
          (s:DefWire) : 
             add(decs,s)
             val ref = WRef(name(s),type(s),NodeKind(),FEMALE)
@@ -1565,19 +1602,30 @@ public defn expand-whens (c:Circuit) -> Circuit :
             ;val enables = get-enables(assign,kinds)
             ;for x in enables do : enables[key(x)] = optimize(value(x))
                   
-            println-debug("====== Assigns ======")
-            for x in assign do : println-debug(x)
-            println-debug("====== Resets ======")
-            for x in resets do : println-debug(x)
+            ;println-debug("====== Assigns ======")
+            ;for x in assign do : println-debug(x)
+            ;println-debug("====== Resets ======")
+            ;for x in resets do : println-debug(x)
    
             val table = merge-resets(assign,resets,rsignals)
-            println-debug("====== Table ======")
-            for x in table do : println-debug(x)
+            ;println-debug("====== Table ======")
+            ;for x in table do : println-debug(x)
+
             val decs = Vector<Stmt>()
             val cons = Vector<Stmt>()
             expand-whens(ports(m),table,cons)
             expand-whens(body(m),table,decs,cons)
-            InModule(info(m),name(m),ports(m),Begin(append(to-list(decs),to-list(cons))))
+
+            val referenced? = HashTable<Symbol,True>(symbol-hash)
+            for x in table do :
+               mark-referenced(referenced?,value(x))
+            for x in decs do :
+               mark-referenced(referenced?,x)
+            val decs* = Vector<Stmt>()
+            for x in decs do :
+               if is-referenced?(referenced?,x) : add(decs*,x)
+               
+            InModule(info(m),name(m),ports(m),Begin(to-list(append(decs*,to-list(cons)))))
 
    val c* = Circuit(info(c),modules*, main(c)) where :
       val modules* =