Fix bundle type equality

Was not checking for length of bundles, so if the bundles matched but one had more fields, it was not caught.

2 files changed, 31 insertions, 0 deletions

diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala
index 0ab51085..05173f56 100644
--- a/src/main/scala/firrtl/WIR.scala
+++ b/src/main/scala/firrtl/WIR.scala
@@ -125,6 +125,7 @@ class WrappedType (val t:Type) {
                      if (f1.name != f2.name) ret = false
                      if (wt(f1.tpe) != wt(f2.tpe)) ret = false
                   }}
+                  if (t1.fields.size != t2.fields.size) ret = false
                   ret
                }
                case (t1,t2) => false
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
new file mode 100644
index 00000000..eda5d5d2
--- /dev/null
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -0,0 +1,30 @@
+
+package firrtlTests
+
+import java.io._
+import org.scalatest._
+import org.scalatest.prop._
+import firrtl.{Parser,Circuit}
+import firrtl.passes.{Pass,ToWorkingIR,CheckHighForm,ResolveKinds,InferTypes,CheckTypes,PassExceptions}
+
+class UnitTests extends FlatSpec with Matchers {
+  "Connecting bundles of different types" should "throw an exception" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    input y: {a : UInt<1>}
+        |    output x: {a : UInt<1>, b : UInt<1>}
+        |    x <= y""".stripMargin
+    intercept[PassExceptions] {
+      passes.foldLeft(Parser.parse("",input.split("\n").toIterator)) {
+        (c: Circuit, p: Pass) => p.run(c)
+      }
+    }
+  }
+}