diff options
| author | jackkoenig | 2016-02-24 22:37:20 -0800 |
|---|---|---|
| committer | jackkoenig | 2016-02-24 22:40:28 -0800 |
| commit | ae40fe404805dd62dfc04061b7091b1095aa8877 (patch) | |
| tree | 55e886131d690e24b885caf300fc96c6cd819e3e | |
| parent | 7810c394489c72508cf09584fb597278a5b33b09 (diff) | |
Make rocket-golden.v match output of #75
| -rw-r--r-- | regress/rocket-golden.v | 2882 |
1 files changed, 1492 insertions, 1390 deletions
diff --git a/regress/rocket-golden.v b/regress/rocket-golden.v index d754d2f5..7e0bef0d 100644 --- a/regress/rocket-golden.v +++ b/regress/rocket-golden.v @@ -10037,6 +10037,10 @@ module BroadcastAcquireTracker( wire GEN_51; wire GEN_52; wire GEN_53; + wire GEN_54; + wire GEN_55; + wire GEN_56; + wire GEN_57; assign io_inner_acquire_ready = T_1245 ? 1'h1 : collect_iacq_data ? 1'h1 : 1'h0; assign io_inner_grant_valid = T_1418 ? 1'h1 : T_1407 ? io_outer_grant_valid : 1'h0; assign io_inner_grant_bits_addr_beat = T_1129_addr_beat; @@ -10373,9 +10377,9 @@ module BroadcastAcquireTracker( assign T_848 = {T_846,T_847}; assign T_850 = {1'h0,1'h1}; assign T_851 = {3'h7,T_850}; - assign GEN_0 = GEN_45 ? xact_wmask_buffer_3 : GEN_46 ? xact_wmask_buffer_2 : GEN_47 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; + assign GEN_0 = GEN_49 ? xact_wmask_buffer_3 : GEN_50 ? xact_wmask_buffer_2 : GEN_51 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; assign T_853 = {GEN_0,1'h1}; - assign GEN_1 = GEN_48 ? xact_wmask_buffer_3 : GEN_49 ? xact_wmask_buffer_2 : GEN_50 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; + assign GEN_1 = GEN_52 ? xact_wmask_buffer_3 : GEN_53 ? xact_wmask_buffer_2 : GEN_54 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; assign T_855 = {GEN_1,1'h1}; assign T_857 = {1'h0,3'h7}; assign T_858 = {1'h0,1'h1}; @@ -10403,7 +10407,7 @@ module BroadcastAcquireTracker( assign oacq_write_block_a_type = 3'h3; assign oacq_write_block_union = T_877; assign oacq_write_block_data = GEN_2; - assign GEN_2 = GEN_51 ? xact_data_buffer_3 : GEN_52 ? xact_data_buffer_2 : GEN_53 ? xact_data_buffer_1 : xact_data_buffer_0; + assign GEN_2 = GEN_55 ? xact_data_buffer_3 : GEN_56 ? xact_data_buffer_2 : GEN_57 ? xact_data_buffer_1 : xact_data_buffer_0; assign T_895 = xact_union[12:9]; assign T_896 = xact_union[8:6]; assign T_904 = {T_895,T_896}; @@ -10740,50 +10744,54 @@ module BroadcastAcquireTracker( assign T_1429 = T_1428 ? 3'h6 : 1'h0; assign T_1430 = 3'h6 == state; assign GEN_9 = T_325 & T_327; - assign GEN_10 = T_1149 & T_1151; - assign GEN_11 = T_1163 & T_1165; - assign GEN_12 = T_1189 & T_1191; - assign GEN_13 = 1'h0 == 1'h0; - assign GEN_14 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_15 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_16 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_17 = 1'h1 == 1'h0; - assign GEN_18 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_19 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_20 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_21 = 2'h2 == 1'h0; - assign GEN_22 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_23 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_24 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_25 = 2'h3 == 1'h0; - assign GEN_26 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_27 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_28 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_29 = 1'h0 == 1'h0; - assign GEN_30 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_31 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_32 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_33 = 1'h1 == 1'h0; - assign GEN_34 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_35 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_36 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_37 = 2'h2 == 1'h0; - assign GEN_38 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_39 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_40 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_41 = 2'h3 == 1'h0; - assign GEN_42 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_43 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_44 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_45 = 2'h3 == oacq_data_cnt; - assign GEN_46 = 2'h2 == oacq_data_cnt; - assign GEN_47 = 1'h1 == oacq_data_cnt; - assign GEN_48 = 2'h3 == oacq_data_cnt; - assign GEN_49 = 2'h2 == oacq_data_cnt; - assign GEN_50 = 1'h1 == oacq_data_cnt; - assign GEN_51 = 2'h3 == oacq_data_cnt; - assign GEN_52 = 2'h2 == oacq_data_cnt; - assign GEN_53 = 1'h1 == oacq_data_cnt; + assign GEN_10 = GEN_9 & T_329; + assign GEN_11 = T_1149 & T_1151; + assign GEN_12 = GEN_11 & T_1153; + assign GEN_13 = T_1163 & T_1165; + assign GEN_14 = GEN_13 & T_1167; + assign GEN_15 = T_1189 & T_1191; + assign GEN_16 = GEN_15 & T_1193; + assign GEN_17 = 1'h0 == 1'h0; + assign GEN_18 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_19 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_20 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_21 = 1'h1 == 1'h0; + assign GEN_22 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_23 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_24 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_25 = 2'h2 == 1'h0; + assign GEN_26 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_27 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_28 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_29 = 2'h3 == 1'h0; + assign GEN_30 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_31 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_32 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_33 = 1'h0 == 1'h0; + assign GEN_34 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_35 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_36 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_37 = 1'h1 == 1'h0; + assign GEN_38 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_39 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_40 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_41 = 2'h2 == 1'h0; + assign GEN_42 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_43 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_44 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_45 = 2'h3 == 1'h0; + assign GEN_46 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_47 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_48 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_49 = 2'h3 == oacq_data_cnt; + assign GEN_50 = 2'h2 == oacq_data_cnt; + assign GEN_51 = 1'h1 == oacq_data_cnt; + assign GEN_52 = 2'h3 == oacq_data_cnt; + assign GEN_53 = 2'h2 == oacq_data_cnt; + assign GEN_54 = 1'h1 == oacq_data_cnt; + assign GEN_55 = 2'h3 == oacq_data_cnt; + assign GEN_56 = 2'h2 == oacq_data_cnt; + assign GEN_57 = 1'h1 == oacq_data_cnt; `ifndef SYNTHESIS integer initvar; initial begin @@ -15249,12 +15257,12 @@ module BroadcastAcquireTracker( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_13) begin + if(GEN_17) begin xact_data_buffer_0 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_14) begin + if(GEN_18) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -15269,7 +15277,7 @@ module BroadcastAcquireTracker( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_15) begin + if(GEN_19) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -15284,7 +15292,7 @@ module BroadcastAcquireTracker( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_16) begin + if(GEN_20) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -15302,12 +15310,12 @@ module BroadcastAcquireTracker( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_17) begin + if(GEN_21) begin xact_data_buffer_1 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_18) begin + if(GEN_22) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -15322,7 +15330,7 @@ module BroadcastAcquireTracker( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_19) begin + if(GEN_23) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -15337,7 +15345,7 @@ module BroadcastAcquireTracker( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_20) begin + if(GEN_24) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -15355,12 +15363,12 @@ module BroadcastAcquireTracker( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_21) begin + if(GEN_25) begin xact_data_buffer_2 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_22) begin + if(GEN_26) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -15375,7 +15383,7 @@ module BroadcastAcquireTracker( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_23) begin + if(GEN_27) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -15390,7 +15398,7 @@ module BroadcastAcquireTracker( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_24) begin + if(GEN_28) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -15408,12 +15416,12 @@ module BroadcastAcquireTracker( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_25) begin + if(GEN_29) begin xact_data_buffer_3 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_26) begin + if(GEN_30) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -15428,7 +15436,7 @@ module BroadcastAcquireTracker( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_27) begin + if(GEN_31) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -15443,7 +15451,7 @@ module BroadcastAcquireTracker( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_28) begin + if(GEN_32) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -15461,12 +15469,12 @@ module BroadcastAcquireTracker( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_29) begin + if(GEN_33) begin xact_wmask_buffer_0 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_30) begin + if(GEN_34) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -15481,7 +15489,7 @@ module BroadcastAcquireTracker( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_31) begin + if(GEN_35) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -15496,7 +15504,7 @@ module BroadcastAcquireTracker( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_32) begin + if(GEN_36) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -15514,12 +15522,12 @@ module BroadcastAcquireTracker( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_33) begin + if(GEN_37) begin xact_wmask_buffer_1 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_34) begin + if(GEN_38) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -15534,7 +15542,7 @@ module BroadcastAcquireTracker( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_35) begin + if(GEN_39) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -15549,7 +15557,7 @@ module BroadcastAcquireTracker( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_36) begin + if(GEN_40) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -15567,12 +15575,12 @@ module BroadcastAcquireTracker( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_37) begin + if(GEN_41) begin xact_wmask_buffer_2 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_38) begin + if(GEN_42) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -15587,7 +15595,7 @@ module BroadcastAcquireTracker( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_39) begin + if(GEN_43) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -15602,7 +15610,7 @@ module BroadcastAcquireTracker( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_40) begin + if(GEN_44) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -15620,12 +15628,12 @@ module BroadcastAcquireTracker( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_41) begin + if(GEN_45) begin xact_wmask_buffer_3 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_42) begin + if(GEN_46) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -15640,7 +15648,7 @@ module BroadcastAcquireTracker( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_43) begin + if(GEN_47) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -15655,7 +15663,7 @@ module BroadcastAcquireTracker( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_44) begin + if(GEN_48) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -16044,7 +16052,7 @@ module BroadcastAcquireTracker( end end `ifndef SYNTHESIS - if(GEN_9 & T_329) begin + if(GEN_10) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches"); end `endif @@ -16054,7 +16062,7 @@ module BroadcastAcquireTracker( end `endif `ifndef SYNTHESIS - if(GEN_10 & T_1153) begin + if(GEN_12) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request."); end `endif @@ -16064,7 +16072,7 @@ module BroadcastAcquireTracker( end `endif `ifndef SYNTHESIS - if(GEN_11 & T_1167) begin + if(GEN_14) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request."); end `endif @@ -16074,7 +16082,7 @@ module BroadcastAcquireTracker( end `endif `ifndef SYNTHESIS - if(GEN_12 & T_1193) begin + if(GEN_16) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat."); end `endif @@ -16892,6 +16900,10 @@ module BroadcastAcquireTracker_27( wire GEN_51; wire GEN_52; wire GEN_53; + wire GEN_54; + wire GEN_55; + wire GEN_56; + wire GEN_57; assign io_inner_acquire_ready = T_1245 ? 1'h1 : collect_iacq_data ? 1'h1 : 1'h0; assign io_inner_grant_valid = T_1418 ? 1'h1 : T_1407 ? io_outer_grant_valid : 1'h0; assign io_inner_grant_bits_addr_beat = T_1129_addr_beat; @@ -17228,9 +17240,9 @@ module BroadcastAcquireTracker_27( assign T_848 = {T_846,T_847}; assign T_850 = {1'h0,1'h1}; assign T_851 = {3'h7,T_850}; - assign GEN_0 = GEN_45 ? xact_wmask_buffer_3 : GEN_46 ? xact_wmask_buffer_2 : GEN_47 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; + assign GEN_0 = GEN_49 ? xact_wmask_buffer_3 : GEN_50 ? xact_wmask_buffer_2 : GEN_51 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; assign T_853 = {GEN_0,1'h1}; - assign GEN_1 = GEN_48 ? xact_wmask_buffer_3 : GEN_49 ? xact_wmask_buffer_2 : GEN_50 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; + assign GEN_1 = GEN_52 ? xact_wmask_buffer_3 : GEN_53 ? xact_wmask_buffer_2 : GEN_54 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; assign T_855 = {GEN_1,1'h1}; assign T_857 = {1'h0,3'h7}; assign T_858 = {1'h0,1'h1}; @@ -17258,7 +17270,7 @@ module BroadcastAcquireTracker_27( assign oacq_write_block_a_type = 3'h3; assign oacq_write_block_union = T_877; assign oacq_write_block_data = GEN_2; - assign GEN_2 = GEN_51 ? xact_data_buffer_3 : GEN_52 ? xact_data_buffer_2 : GEN_53 ? xact_data_buffer_1 : xact_data_buffer_0; + assign GEN_2 = GEN_55 ? xact_data_buffer_3 : GEN_56 ? xact_data_buffer_2 : GEN_57 ? xact_data_buffer_1 : xact_data_buffer_0; assign T_895 = xact_union[12:9]; assign T_896 = xact_union[8:6]; assign T_904 = {T_895,T_896}; @@ -17595,50 +17607,54 @@ module BroadcastAcquireTracker_27( assign T_1429 = T_1428 ? 3'h6 : 1'h0; assign T_1430 = 3'h6 == state; assign GEN_9 = T_325 & T_327; - assign GEN_10 = T_1149 & T_1151; - assign GEN_11 = T_1163 & T_1165; - assign GEN_12 = T_1189 & T_1191; - assign GEN_13 = 1'h0 == 1'h0; - assign GEN_14 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_15 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_16 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_17 = 1'h1 == 1'h0; - assign GEN_18 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_19 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_20 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_21 = 2'h2 == 1'h0; - assign GEN_22 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_23 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_24 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_25 = 2'h3 == 1'h0; - assign GEN_26 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_27 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_28 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_29 = 1'h0 == 1'h0; - assign GEN_30 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_31 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_32 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_33 = 1'h1 == 1'h0; - assign GEN_34 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_35 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_36 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_37 = 2'h2 == 1'h0; - assign GEN_38 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_39 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_40 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_41 = 2'h3 == 1'h0; - assign GEN_42 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_43 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_44 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_45 = 2'h3 == oacq_data_cnt; - assign GEN_46 = 2'h2 == oacq_data_cnt; - assign GEN_47 = 1'h1 == oacq_data_cnt; - assign GEN_48 = 2'h3 == oacq_data_cnt; - assign GEN_49 = 2'h2 == oacq_data_cnt; - assign GEN_50 = 1'h1 == oacq_data_cnt; - assign GEN_51 = 2'h3 == oacq_data_cnt; - assign GEN_52 = 2'h2 == oacq_data_cnt; - assign GEN_53 = 1'h1 == oacq_data_cnt; + assign GEN_10 = GEN_9 & T_329; + assign GEN_11 = T_1149 & T_1151; + assign GEN_12 = GEN_11 & T_1153; + assign GEN_13 = T_1163 & T_1165; + assign GEN_14 = GEN_13 & T_1167; + assign GEN_15 = T_1189 & T_1191; + assign GEN_16 = GEN_15 & T_1193; + assign GEN_17 = 1'h0 == 1'h0; + assign GEN_18 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_19 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_20 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_21 = 1'h1 == 1'h0; + assign GEN_22 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_23 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_24 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_25 = 2'h2 == 1'h0; + assign GEN_26 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_27 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_28 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_29 = 2'h3 == 1'h0; + assign GEN_30 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_31 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_32 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_33 = 1'h0 == 1'h0; + assign GEN_34 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_35 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_36 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_37 = 1'h1 == 1'h0; + assign GEN_38 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_39 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_40 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_41 = 2'h2 == 1'h0; + assign GEN_42 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_43 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_44 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_45 = 2'h3 == 1'h0; + assign GEN_46 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_47 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_48 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_49 = 2'h3 == oacq_data_cnt; + assign GEN_50 = 2'h2 == oacq_data_cnt; + assign GEN_51 = 1'h1 == oacq_data_cnt; + assign GEN_52 = 2'h3 == oacq_data_cnt; + assign GEN_53 = 2'h2 == oacq_data_cnt; + assign GEN_54 = 1'h1 == oacq_data_cnt; + assign GEN_55 = 2'h3 == oacq_data_cnt; + assign GEN_56 = 2'h2 == oacq_data_cnt; + assign GEN_57 = 1'h1 == oacq_data_cnt; `ifndef SYNTHESIS integer initvar; initial begin @@ -22104,12 +22120,12 @@ module BroadcastAcquireTracker_27( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_13) begin + if(GEN_17) begin xact_data_buffer_0 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_14) begin + if(GEN_18) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -22124,7 +22140,7 @@ module BroadcastAcquireTracker_27( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_15) begin + if(GEN_19) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -22139,7 +22155,7 @@ module BroadcastAcquireTracker_27( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_16) begin + if(GEN_20) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -22157,12 +22173,12 @@ module BroadcastAcquireTracker_27( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_17) begin + if(GEN_21) begin xact_data_buffer_1 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_18) begin + if(GEN_22) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -22177,7 +22193,7 @@ module BroadcastAcquireTracker_27( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_19) begin + if(GEN_23) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -22192,7 +22208,7 @@ module BroadcastAcquireTracker_27( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_20) begin + if(GEN_24) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -22210,12 +22226,12 @@ module BroadcastAcquireTracker_27( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_21) begin + if(GEN_25) begin xact_data_buffer_2 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_22) begin + if(GEN_26) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -22230,7 +22246,7 @@ module BroadcastAcquireTracker_27( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_23) begin + if(GEN_27) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -22245,7 +22261,7 @@ module BroadcastAcquireTracker_27( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_24) begin + if(GEN_28) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -22263,12 +22279,12 @@ module BroadcastAcquireTracker_27( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_25) begin + if(GEN_29) begin xact_data_buffer_3 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_26) begin + if(GEN_30) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -22283,7 +22299,7 @@ module BroadcastAcquireTracker_27( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_27) begin + if(GEN_31) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -22298,7 +22314,7 @@ module BroadcastAcquireTracker_27( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_28) begin + if(GEN_32) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -22316,12 +22332,12 @@ module BroadcastAcquireTracker_27( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_29) begin + if(GEN_33) begin xact_wmask_buffer_0 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_30) begin + if(GEN_34) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -22336,7 +22352,7 @@ module BroadcastAcquireTracker_27( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_31) begin + if(GEN_35) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -22351,7 +22367,7 @@ module BroadcastAcquireTracker_27( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_32) begin + if(GEN_36) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -22369,12 +22385,12 @@ module BroadcastAcquireTracker_27( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_33) begin + if(GEN_37) begin xact_wmask_buffer_1 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_34) begin + if(GEN_38) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -22389,7 +22405,7 @@ module BroadcastAcquireTracker_27( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_35) begin + if(GEN_39) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -22404,7 +22420,7 @@ module BroadcastAcquireTracker_27( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_36) begin + if(GEN_40) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -22422,12 +22438,12 @@ module BroadcastAcquireTracker_27( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_37) begin + if(GEN_41) begin xact_wmask_buffer_2 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_38) begin + if(GEN_42) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -22442,7 +22458,7 @@ module BroadcastAcquireTracker_27( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_39) begin + if(GEN_43) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -22457,7 +22473,7 @@ module BroadcastAcquireTracker_27( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_40) begin + if(GEN_44) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -22475,12 +22491,12 @@ module BroadcastAcquireTracker_27( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_41) begin + if(GEN_45) begin xact_wmask_buffer_3 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_42) begin + if(GEN_46) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -22495,7 +22511,7 @@ module BroadcastAcquireTracker_27( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_43) begin + if(GEN_47) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -22510,7 +22526,7 @@ module BroadcastAcquireTracker_27( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_44) begin + if(GEN_48) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -22899,7 +22915,7 @@ module BroadcastAcquireTracker_27( end end `ifndef SYNTHESIS - if(GEN_9 & T_329) begin + if(GEN_10) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches"); end `endif @@ -22909,7 +22925,7 @@ module BroadcastAcquireTracker_27( end `endif `ifndef SYNTHESIS - if(GEN_10 & T_1153) begin + if(GEN_12) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request."); end `endif @@ -22919,7 +22935,7 @@ module BroadcastAcquireTracker_27( end `endif `ifndef SYNTHESIS - if(GEN_11 & T_1167) begin + if(GEN_14) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request."); end `endif @@ -22929,7 +22945,7 @@ module BroadcastAcquireTracker_27( end `endif `ifndef SYNTHESIS - if(GEN_12 & T_1193) begin + if(GEN_16) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat."); end `endif @@ -23747,6 +23763,10 @@ module BroadcastAcquireTracker_28( wire GEN_51; wire GEN_52; wire GEN_53; + wire GEN_54; + wire GEN_55; + wire GEN_56; + wire GEN_57; assign io_inner_acquire_ready = T_1245 ? 1'h1 : collect_iacq_data ? 1'h1 : 1'h0; assign io_inner_grant_valid = T_1418 ? 1'h1 : T_1407 ? io_outer_grant_valid : 1'h0; assign io_inner_grant_bits_addr_beat = T_1129_addr_beat; @@ -24083,9 +24103,9 @@ module BroadcastAcquireTracker_28( assign T_848 = {T_846,T_847}; assign T_850 = {1'h0,1'h1}; assign T_851 = {3'h7,T_850}; - assign GEN_0 = GEN_45 ? xact_wmask_buffer_3 : GEN_46 ? xact_wmask_buffer_2 : GEN_47 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; + assign GEN_0 = GEN_49 ? xact_wmask_buffer_3 : GEN_50 ? xact_wmask_buffer_2 : GEN_51 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; assign T_853 = {GEN_0,1'h1}; - assign GEN_1 = GEN_48 ? xact_wmask_buffer_3 : GEN_49 ? xact_wmask_buffer_2 : GEN_50 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; + assign GEN_1 = GEN_52 ? xact_wmask_buffer_3 : GEN_53 ? xact_wmask_buffer_2 : GEN_54 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; assign T_855 = {GEN_1,1'h1}; assign T_857 = {1'h0,3'h7}; assign T_858 = {1'h0,1'h1}; @@ -24113,7 +24133,7 @@ module BroadcastAcquireTracker_28( assign oacq_write_block_a_type = 3'h3; assign oacq_write_block_union = T_877; assign oacq_write_block_data = GEN_2; - assign GEN_2 = GEN_51 ? xact_data_buffer_3 : GEN_52 ? xact_data_buffer_2 : GEN_53 ? xact_data_buffer_1 : xact_data_buffer_0; + assign GEN_2 = GEN_55 ? xact_data_buffer_3 : GEN_56 ? xact_data_buffer_2 : GEN_57 ? xact_data_buffer_1 : xact_data_buffer_0; assign T_895 = xact_union[12:9]; assign T_896 = xact_union[8:6]; assign T_904 = {T_895,T_896}; @@ -24450,50 +24470,54 @@ module BroadcastAcquireTracker_28( assign T_1429 = T_1428 ? 3'h6 : 1'h0; assign T_1430 = 3'h6 == state; assign GEN_9 = T_325 & T_327; - assign GEN_10 = T_1149 & T_1151; - assign GEN_11 = T_1163 & T_1165; - assign GEN_12 = T_1189 & T_1191; - assign GEN_13 = 1'h0 == 1'h0; - assign GEN_14 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_15 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_16 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_17 = 1'h1 == 1'h0; - assign GEN_18 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_19 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_20 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_21 = 2'h2 == 1'h0; - assign GEN_22 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_23 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_24 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_25 = 2'h3 == 1'h0; - assign GEN_26 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_27 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_28 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_29 = 1'h0 == 1'h0; - assign GEN_30 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_31 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_32 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_33 = 1'h1 == 1'h0; - assign GEN_34 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_35 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_36 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_37 = 2'h2 == 1'h0; - assign GEN_38 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_39 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_40 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_41 = 2'h3 == 1'h0; - assign GEN_42 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_43 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_44 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_45 = 2'h3 == oacq_data_cnt; - assign GEN_46 = 2'h2 == oacq_data_cnt; - assign GEN_47 = 1'h1 == oacq_data_cnt; - assign GEN_48 = 2'h3 == oacq_data_cnt; - assign GEN_49 = 2'h2 == oacq_data_cnt; - assign GEN_50 = 1'h1 == oacq_data_cnt; - assign GEN_51 = 2'h3 == oacq_data_cnt; - assign GEN_52 = 2'h2 == oacq_data_cnt; - assign GEN_53 = 1'h1 == oacq_data_cnt; + assign GEN_10 = GEN_9 & T_329; + assign GEN_11 = T_1149 & T_1151; + assign GEN_12 = GEN_11 & T_1153; + assign GEN_13 = T_1163 & T_1165; + assign GEN_14 = GEN_13 & T_1167; + assign GEN_15 = T_1189 & T_1191; + assign GEN_16 = GEN_15 & T_1193; + assign GEN_17 = 1'h0 == 1'h0; + assign GEN_18 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_19 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_20 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_21 = 1'h1 == 1'h0; + assign GEN_22 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_23 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_24 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_25 = 2'h2 == 1'h0; + assign GEN_26 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_27 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_28 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_29 = 2'h3 == 1'h0; + assign GEN_30 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_31 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_32 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_33 = 1'h0 == 1'h0; + assign GEN_34 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_35 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_36 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_37 = 1'h1 == 1'h0; + assign GEN_38 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_39 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_40 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_41 = 2'h2 == 1'h0; + assign GEN_42 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_43 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_44 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_45 = 2'h3 == 1'h0; + assign GEN_46 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_47 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_48 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_49 = 2'h3 == oacq_data_cnt; + assign GEN_50 = 2'h2 == oacq_data_cnt; + assign GEN_51 = 1'h1 == oacq_data_cnt; + assign GEN_52 = 2'h3 == oacq_data_cnt; + assign GEN_53 = 2'h2 == oacq_data_cnt; + assign GEN_54 = 1'h1 == oacq_data_cnt; + assign GEN_55 = 2'h3 == oacq_data_cnt; + assign GEN_56 = 2'h2 == oacq_data_cnt; + assign GEN_57 = 1'h1 == oacq_data_cnt; `ifndef SYNTHESIS integer initvar; initial begin @@ -28959,12 +28983,12 @@ module BroadcastAcquireTracker_28( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_13) begin + if(GEN_17) begin xact_data_buffer_0 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_14) begin + if(GEN_18) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -28979,7 +29003,7 @@ module BroadcastAcquireTracker_28( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_15) begin + if(GEN_19) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -28994,7 +29018,7 @@ module BroadcastAcquireTracker_28( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_16) begin + if(GEN_20) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -29012,12 +29036,12 @@ module BroadcastAcquireTracker_28( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_17) begin + if(GEN_21) begin xact_data_buffer_1 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_18) begin + if(GEN_22) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -29032,7 +29056,7 @@ module BroadcastAcquireTracker_28( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_19) begin + if(GEN_23) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -29047,7 +29071,7 @@ module BroadcastAcquireTracker_28( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_20) begin + if(GEN_24) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -29065,12 +29089,12 @@ module BroadcastAcquireTracker_28( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_21) begin + if(GEN_25) begin xact_data_buffer_2 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_22) begin + if(GEN_26) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -29085,7 +29109,7 @@ module BroadcastAcquireTracker_28( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_23) begin + if(GEN_27) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -29100,7 +29124,7 @@ module BroadcastAcquireTracker_28( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_24) begin + if(GEN_28) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -29118,12 +29142,12 @@ module BroadcastAcquireTracker_28( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_25) begin + if(GEN_29) begin xact_data_buffer_3 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_26) begin + if(GEN_30) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -29138,7 +29162,7 @@ module BroadcastAcquireTracker_28( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_27) begin + if(GEN_31) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -29153,7 +29177,7 @@ module BroadcastAcquireTracker_28( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_28) begin + if(GEN_32) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -29171,12 +29195,12 @@ module BroadcastAcquireTracker_28( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_29) begin + if(GEN_33) begin xact_wmask_buffer_0 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_30) begin + if(GEN_34) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -29191,7 +29215,7 @@ module BroadcastAcquireTracker_28( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_31) begin + if(GEN_35) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -29206,7 +29230,7 @@ module BroadcastAcquireTracker_28( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_32) begin + if(GEN_36) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -29224,12 +29248,12 @@ module BroadcastAcquireTracker_28( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_33) begin + if(GEN_37) begin xact_wmask_buffer_1 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_34) begin + if(GEN_38) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -29244,7 +29268,7 @@ module BroadcastAcquireTracker_28( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_35) begin + if(GEN_39) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -29259,7 +29283,7 @@ module BroadcastAcquireTracker_28( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_36) begin + if(GEN_40) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -29277,12 +29301,12 @@ module BroadcastAcquireTracker_28( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_37) begin + if(GEN_41) begin xact_wmask_buffer_2 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_38) begin + if(GEN_42) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -29297,7 +29321,7 @@ module BroadcastAcquireTracker_28( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_39) begin + if(GEN_43) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -29312,7 +29336,7 @@ module BroadcastAcquireTracker_28( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_40) begin + if(GEN_44) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -29330,12 +29354,12 @@ module BroadcastAcquireTracker_28( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_41) begin + if(GEN_45) begin xact_wmask_buffer_3 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_42) begin + if(GEN_46) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -29350,7 +29374,7 @@ module BroadcastAcquireTracker_28( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_43) begin + if(GEN_47) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -29365,7 +29389,7 @@ module BroadcastAcquireTracker_28( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_44) begin + if(GEN_48) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -29754,7 +29778,7 @@ module BroadcastAcquireTracker_28( end end `ifndef SYNTHESIS - if(GEN_9 & T_329) begin + if(GEN_10) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches"); end `endif @@ -29764,7 +29788,7 @@ module BroadcastAcquireTracker_28( end `endif `ifndef SYNTHESIS - if(GEN_10 & T_1153) begin + if(GEN_12) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request."); end `endif @@ -29774,7 +29798,7 @@ module BroadcastAcquireTracker_28( end `endif `ifndef SYNTHESIS - if(GEN_11 & T_1167) begin + if(GEN_14) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request."); end `endif @@ -29784,7 +29808,7 @@ module BroadcastAcquireTracker_28( end `endif `ifndef SYNTHESIS - if(GEN_12 & T_1193) begin + if(GEN_16) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat."); end `endif @@ -30602,6 +30626,10 @@ module BroadcastAcquireTracker_29( wire GEN_51; wire GEN_52; wire GEN_53; + wire GEN_54; + wire GEN_55; + wire GEN_56; + wire GEN_57; assign io_inner_acquire_ready = T_1245 ? 1'h1 : collect_iacq_data ? 1'h1 : 1'h0; assign io_inner_grant_valid = T_1418 ? 1'h1 : T_1407 ? io_outer_grant_valid : 1'h0; assign io_inner_grant_bits_addr_beat = T_1129_addr_beat; @@ -30938,9 +30966,9 @@ module BroadcastAcquireTracker_29( assign T_848 = {T_846,T_847}; assign T_850 = {1'h0,1'h1}; assign T_851 = {3'h7,T_850}; - assign GEN_0 = GEN_45 ? xact_wmask_buffer_3 : GEN_46 ? xact_wmask_buffer_2 : GEN_47 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; + assign GEN_0 = GEN_49 ? xact_wmask_buffer_3 : GEN_50 ? xact_wmask_buffer_2 : GEN_51 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; assign T_853 = {GEN_0,1'h1}; - assign GEN_1 = GEN_48 ? xact_wmask_buffer_3 : GEN_49 ? xact_wmask_buffer_2 : GEN_50 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; + assign GEN_1 = GEN_52 ? xact_wmask_buffer_3 : GEN_53 ? xact_wmask_buffer_2 : GEN_54 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; assign T_855 = {GEN_1,1'h1}; assign T_857 = {1'h0,3'h7}; assign T_858 = {1'h0,1'h1}; @@ -30968,7 +30996,7 @@ module BroadcastAcquireTracker_29( assign oacq_write_block_a_type = 3'h3; assign oacq_write_block_union = T_877; assign oacq_write_block_data = GEN_2; - assign GEN_2 = GEN_51 ? xact_data_buffer_3 : GEN_52 ? xact_data_buffer_2 : GEN_53 ? xact_data_buffer_1 : xact_data_buffer_0; + assign GEN_2 = GEN_55 ? xact_data_buffer_3 : GEN_56 ? xact_data_buffer_2 : GEN_57 ? xact_data_buffer_1 : xact_data_buffer_0; assign T_895 = xact_union[12:9]; assign T_896 = xact_union[8:6]; assign T_904 = {T_895,T_896}; @@ -31305,50 +31333,54 @@ module BroadcastAcquireTracker_29( assign T_1429 = T_1428 ? 3'h6 : 1'h0; assign T_1430 = 3'h6 == state; assign GEN_9 = T_325 & T_327; - assign GEN_10 = T_1149 & T_1151; - assign GEN_11 = T_1163 & T_1165; - assign GEN_12 = T_1189 & T_1191; - assign GEN_13 = 1'h0 == 1'h0; - assign GEN_14 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_15 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_16 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_17 = 1'h1 == 1'h0; - assign GEN_18 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_19 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_20 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_21 = 2'h2 == 1'h0; - assign GEN_22 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_23 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_24 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_25 = 2'h3 == 1'h0; - assign GEN_26 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_27 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_28 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_29 = 1'h0 == 1'h0; - assign GEN_30 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_31 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_32 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_33 = 1'h1 == 1'h0; - assign GEN_34 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_35 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_36 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_37 = 2'h2 == 1'h0; - assign GEN_38 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_39 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_40 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_41 = 2'h3 == 1'h0; - assign GEN_42 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_43 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_44 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_45 = 2'h3 == oacq_data_cnt; - assign GEN_46 = 2'h2 == oacq_data_cnt; - assign GEN_47 = 1'h1 == oacq_data_cnt; - assign GEN_48 = 2'h3 == oacq_data_cnt; - assign GEN_49 = 2'h2 == oacq_data_cnt; - assign GEN_50 = 1'h1 == oacq_data_cnt; - assign GEN_51 = 2'h3 == oacq_data_cnt; - assign GEN_52 = 2'h2 == oacq_data_cnt; - assign GEN_53 = 1'h1 == oacq_data_cnt; + assign GEN_10 = GEN_9 & T_329; + assign GEN_11 = T_1149 & T_1151; + assign GEN_12 = GEN_11 & T_1153; + assign GEN_13 = T_1163 & T_1165; + assign GEN_14 = GEN_13 & T_1167; + assign GEN_15 = T_1189 & T_1191; + assign GEN_16 = GEN_15 & T_1193; + assign GEN_17 = 1'h0 == 1'h0; + assign GEN_18 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_19 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_20 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_21 = 1'h1 == 1'h0; + assign GEN_22 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_23 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_24 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_25 = 2'h2 == 1'h0; + assign GEN_26 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_27 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_28 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_29 = 2'h3 == 1'h0; + assign GEN_30 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_31 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_32 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_33 = 1'h0 == 1'h0; + assign GEN_34 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_35 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_36 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_37 = 1'h1 == 1'h0; + assign GEN_38 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_39 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_40 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_41 = 2'h2 == 1'h0; + assign GEN_42 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_43 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_44 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_45 = 2'h3 == 1'h0; + assign GEN_46 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_47 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_48 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_49 = 2'h3 == oacq_data_cnt; + assign GEN_50 = 2'h2 == oacq_data_cnt; + assign GEN_51 = 1'h1 == oacq_data_cnt; + assign GEN_52 = 2'h3 == oacq_data_cnt; + assign GEN_53 = 2'h2 == oacq_data_cnt; + assign GEN_54 = 1'h1 == oacq_data_cnt; + assign GEN_55 = 2'h3 == oacq_data_cnt; + assign GEN_56 = 2'h2 == oacq_data_cnt; + assign GEN_57 = 1'h1 == oacq_data_cnt; `ifndef SYNTHESIS integer initvar; initial begin @@ -35814,12 +35846,12 @@ module BroadcastAcquireTracker_29( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_13) begin + if(GEN_17) begin xact_data_buffer_0 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_14) begin + if(GEN_18) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -35834,7 +35866,7 @@ module BroadcastAcquireTracker_29( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_15) begin + if(GEN_19) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -35849,7 +35881,7 @@ module BroadcastAcquireTracker_29( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_16) begin + if(GEN_20) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -35867,12 +35899,12 @@ module BroadcastAcquireTracker_29( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_17) begin + if(GEN_21) begin xact_data_buffer_1 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_18) begin + if(GEN_22) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -35887,7 +35919,7 @@ module BroadcastAcquireTracker_29( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_19) begin + if(GEN_23) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -35902,7 +35934,7 @@ module BroadcastAcquireTracker_29( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_20) begin + if(GEN_24) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -35920,12 +35952,12 @@ module BroadcastAcquireTracker_29( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_21) begin + if(GEN_25) begin xact_data_buffer_2 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_22) begin + if(GEN_26) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -35940,7 +35972,7 @@ module BroadcastAcquireTracker_29( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_23) begin + if(GEN_27) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -35955,7 +35987,7 @@ module BroadcastAcquireTracker_29( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_24) begin + if(GEN_28) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -35973,12 +36005,12 @@ module BroadcastAcquireTracker_29( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_25) begin + if(GEN_29) begin xact_data_buffer_3 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_26) begin + if(GEN_30) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -35993,7 +36025,7 @@ module BroadcastAcquireTracker_29( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_27) begin + if(GEN_31) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -36008,7 +36040,7 @@ module BroadcastAcquireTracker_29( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_28) begin + if(GEN_32) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -36026,12 +36058,12 @@ module BroadcastAcquireTracker_29( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_29) begin + if(GEN_33) begin xact_wmask_buffer_0 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_30) begin + if(GEN_34) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -36046,7 +36078,7 @@ module BroadcastAcquireTracker_29( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_31) begin + if(GEN_35) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -36061,7 +36093,7 @@ module BroadcastAcquireTracker_29( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_32) begin + if(GEN_36) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -36079,12 +36111,12 @@ module BroadcastAcquireTracker_29( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_33) begin + if(GEN_37) begin xact_wmask_buffer_1 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_34) begin + if(GEN_38) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -36099,7 +36131,7 @@ module BroadcastAcquireTracker_29( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_35) begin + if(GEN_39) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -36114,7 +36146,7 @@ module BroadcastAcquireTracker_29( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_36) begin + if(GEN_40) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -36132,12 +36164,12 @@ module BroadcastAcquireTracker_29( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_37) begin + if(GEN_41) begin xact_wmask_buffer_2 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_38) begin + if(GEN_42) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -36152,7 +36184,7 @@ module BroadcastAcquireTracker_29( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_39) begin + if(GEN_43) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -36167,7 +36199,7 @@ module BroadcastAcquireTracker_29( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_40) begin + if(GEN_44) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -36185,12 +36217,12 @@ module BroadcastAcquireTracker_29( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_41) begin + if(GEN_45) begin xact_wmask_buffer_3 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_42) begin + if(GEN_46) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -36205,7 +36237,7 @@ module BroadcastAcquireTracker_29( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_43) begin + if(GEN_47) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -36220,7 +36252,7 @@ module BroadcastAcquireTracker_29( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_44) begin + if(GEN_48) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -36609,7 +36641,7 @@ module BroadcastAcquireTracker_29( end end `ifndef SYNTHESIS - if(GEN_9 & T_329) begin + if(GEN_10) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches"); end `endif @@ -36619,7 +36651,7 @@ module BroadcastAcquireTracker_29( end `endif `ifndef SYNTHESIS - if(GEN_10 & T_1153) begin + if(GEN_12) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request."); end `endif @@ -36629,7 +36661,7 @@ module BroadcastAcquireTracker_29( end `endif `ifndef SYNTHESIS - if(GEN_11 & T_1167) begin + if(GEN_14) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request."); end `endif @@ -36639,7 +36671,7 @@ module BroadcastAcquireTracker_29( end `endif `ifndef SYNTHESIS - if(GEN_12 & T_1193) begin + if(GEN_16) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat."); end `endif @@ -37457,6 +37489,10 @@ module BroadcastAcquireTracker_30( wire GEN_51; wire GEN_52; wire GEN_53; + wire GEN_54; + wire GEN_55; + wire GEN_56; + wire GEN_57; assign io_inner_acquire_ready = T_1245 ? 1'h1 : collect_iacq_data ? 1'h1 : 1'h0; assign io_inner_grant_valid = T_1418 ? 1'h1 : T_1407 ? io_outer_grant_valid : 1'h0; assign io_inner_grant_bits_addr_beat = T_1129_addr_beat; @@ -37793,9 +37829,9 @@ module BroadcastAcquireTracker_30( assign T_848 = {T_846,T_847}; assign T_850 = {1'h0,1'h1}; assign T_851 = {3'h7,T_850}; - assign GEN_0 = GEN_45 ? xact_wmask_buffer_3 : GEN_46 ? xact_wmask_buffer_2 : GEN_47 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; + assign GEN_0 = GEN_49 ? xact_wmask_buffer_3 : GEN_50 ? xact_wmask_buffer_2 : GEN_51 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; assign T_853 = {GEN_0,1'h1}; - assign GEN_1 = GEN_48 ? xact_wmask_buffer_3 : GEN_49 ? xact_wmask_buffer_2 : GEN_50 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; + assign GEN_1 = GEN_52 ? xact_wmask_buffer_3 : GEN_53 ? xact_wmask_buffer_2 : GEN_54 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; assign T_855 = {GEN_1,1'h1}; assign T_857 = {1'h0,3'h7}; assign T_858 = {1'h0,1'h1}; @@ -37823,7 +37859,7 @@ module BroadcastAcquireTracker_30( assign oacq_write_block_a_type = 3'h3; assign oacq_write_block_union = T_877; assign oacq_write_block_data = GEN_2; - assign GEN_2 = GEN_51 ? xact_data_buffer_3 : GEN_52 ? xact_data_buffer_2 : GEN_53 ? xact_data_buffer_1 : xact_data_buffer_0; + assign GEN_2 = GEN_55 ? xact_data_buffer_3 : GEN_56 ? xact_data_buffer_2 : GEN_57 ? xact_data_buffer_1 : xact_data_buffer_0; assign T_895 = xact_union[12:9]; assign T_896 = xact_union[8:6]; assign T_904 = {T_895,T_896}; @@ -38160,50 +38196,54 @@ module BroadcastAcquireTracker_30( assign T_1429 = T_1428 ? 3'h6 : 1'h0; assign T_1430 = 3'h6 == state; assign GEN_9 = T_325 & T_327; - assign GEN_10 = T_1149 & T_1151; - assign GEN_11 = T_1163 & T_1165; - assign GEN_12 = T_1189 & T_1191; - assign GEN_13 = 1'h0 == 1'h0; - assign GEN_14 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_15 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_16 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_17 = 1'h1 == 1'h0; - assign GEN_18 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_19 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_20 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_21 = 2'h2 == 1'h0; - assign GEN_22 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_23 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_24 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_25 = 2'h3 == 1'h0; - assign GEN_26 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_27 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_28 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_29 = 1'h0 == 1'h0; - assign GEN_30 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_31 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_32 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_33 = 1'h1 == 1'h0; - assign GEN_34 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_35 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_36 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_37 = 2'h2 == 1'h0; - assign GEN_38 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_39 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_40 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_41 = 2'h3 == 1'h0; - assign GEN_42 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_43 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_44 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_45 = 2'h3 == oacq_data_cnt; - assign GEN_46 = 2'h2 == oacq_data_cnt; - assign GEN_47 = 1'h1 == oacq_data_cnt; - assign GEN_48 = 2'h3 == oacq_data_cnt; - assign GEN_49 = 2'h2 == oacq_data_cnt; - assign GEN_50 = 1'h1 == oacq_data_cnt; - assign GEN_51 = 2'h3 == oacq_data_cnt; - assign GEN_52 = 2'h2 == oacq_data_cnt; - assign GEN_53 = 1'h1 == oacq_data_cnt; + assign GEN_10 = GEN_9 & T_329; + assign GEN_11 = T_1149 & T_1151; + assign GEN_12 = GEN_11 & T_1153; + assign GEN_13 = T_1163 & T_1165; + assign GEN_14 = GEN_13 & T_1167; + assign GEN_15 = T_1189 & T_1191; + assign GEN_16 = GEN_15 & T_1193; + assign GEN_17 = 1'h0 == 1'h0; + assign GEN_18 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_19 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_20 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_21 = 1'h1 == 1'h0; + assign GEN_22 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_23 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_24 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_25 = 2'h2 == 1'h0; + assign GEN_26 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_27 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_28 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_29 = 2'h3 == 1'h0; + assign GEN_30 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_31 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_32 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_33 = 1'h0 == 1'h0; + assign GEN_34 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_35 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_36 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_37 = 1'h1 == 1'h0; + assign GEN_38 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_39 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_40 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_41 = 2'h2 == 1'h0; + assign GEN_42 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_43 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_44 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_45 = 2'h3 == 1'h0; + assign GEN_46 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_47 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_48 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_49 = 2'h3 == oacq_data_cnt; + assign GEN_50 = 2'h2 == oacq_data_cnt; + assign GEN_51 = 1'h1 == oacq_data_cnt; + assign GEN_52 = 2'h3 == oacq_data_cnt; + assign GEN_53 = 2'h2 == oacq_data_cnt; + assign GEN_54 = 1'h1 == oacq_data_cnt; + assign GEN_55 = 2'h3 == oacq_data_cnt; + assign GEN_56 = 2'h2 == oacq_data_cnt; + assign GEN_57 = 1'h1 == oacq_data_cnt; `ifndef SYNTHESIS integer initvar; initial begin @@ -42669,12 +42709,12 @@ module BroadcastAcquireTracker_30( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_13) begin + if(GEN_17) begin xact_data_buffer_0 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_14) begin + if(GEN_18) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -42689,7 +42729,7 @@ module BroadcastAcquireTracker_30( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_15) begin + if(GEN_19) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -42704,7 +42744,7 @@ module BroadcastAcquireTracker_30( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_16) begin + if(GEN_20) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -42722,12 +42762,12 @@ module BroadcastAcquireTracker_30( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_17) begin + if(GEN_21) begin xact_data_buffer_1 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_18) begin + if(GEN_22) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -42742,7 +42782,7 @@ module BroadcastAcquireTracker_30( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_19) begin + if(GEN_23) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -42757,7 +42797,7 @@ module BroadcastAcquireTracker_30( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_20) begin + if(GEN_24) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -42775,12 +42815,12 @@ module BroadcastAcquireTracker_30( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_21) begin + if(GEN_25) begin xact_data_buffer_2 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_22) begin + if(GEN_26) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -42795,7 +42835,7 @@ module BroadcastAcquireTracker_30( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_23) begin + if(GEN_27) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -42810,7 +42850,7 @@ module BroadcastAcquireTracker_30( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_24) begin + if(GEN_28) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -42828,12 +42868,12 @@ module BroadcastAcquireTracker_30( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_25) begin + if(GEN_29) begin xact_data_buffer_3 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_26) begin + if(GEN_30) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -42848,7 +42888,7 @@ module BroadcastAcquireTracker_30( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_27) begin + if(GEN_31) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -42863,7 +42903,7 @@ module BroadcastAcquireTracker_30( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_28) begin + if(GEN_32) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -42881,12 +42921,12 @@ module BroadcastAcquireTracker_30( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_29) begin + if(GEN_33) begin xact_wmask_buffer_0 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_30) begin + if(GEN_34) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -42901,7 +42941,7 @@ module BroadcastAcquireTracker_30( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_31) begin + if(GEN_35) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -42916,7 +42956,7 @@ module BroadcastAcquireTracker_30( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_32) begin + if(GEN_36) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -42934,12 +42974,12 @@ module BroadcastAcquireTracker_30( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_33) begin + if(GEN_37) begin xact_wmask_buffer_1 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_34) begin + if(GEN_38) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -42954,7 +42994,7 @@ module BroadcastAcquireTracker_30( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_35) begin + if(GEN_39) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -42969,7 +43009,7 @@ module BroadcastAcquireTracker_30( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_36) begin + if(GEN_40) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -42987,12 +43027,12 @@ module BroadcastAcquireTracker_30( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_37) begin + if(GEN_41) begin xact_wmask_buffer_2 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_38) begin + if(GEN_42) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -43007,7 +43047,7 @@ module BroadcastAcquireTracker_30( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_39) begin + if(GEN_43) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -43022,7 +43062,7 @@ module BroadcastAcquireTracker_30( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_40) begin + if(GEN_44) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -43040,12 +43080,12 @@ module BroadcastAcquireTracker_30( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_41) begin + if(GEN_45) begin xact_wmask_buffer_3 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_42) begin + if(GEN_46) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -43060,7 +43100,7 @@ module BroadcastAcquireTracker_30( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_43) begin + if(GEN_47) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -43075,7 +43115,7 @@ module BroadcastAcquireTracker_30( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_44) begin + if(GEN_48) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -43464,7 +43504,7 @@ module BroadcastAcquireTracker_30( end end `ifndef SYNTHESIS - if(GEN_9 & T_329) begin + if(GEN_10) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches"); end `endif @@ -43474,7 +43514,7 @@ module BroadcastAcquireTracker_30( end `endif `ifndef SYNTHESIS - if(GEN_10 & T_1153) begin + if(GEN_12) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request."); end `endif @@ -43484,7 +43524,7 @@ module BroadcastAcquireTracker_30( end `endif `ifndef SYNTHESIS - if(GEN_11 & T_1167) begin + if(GEN_14) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request."); end `endif @@ -43494,7 +43534,7 @@ module BroadcastAcquireTracker_30( end `endif `ifndef SYNTHESIS - if(GEN_12 & T_1193) begin + if(GEN_16) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat."); end `endif @@ -44312,6 +44352,10 @@ module BroadcastAcquireTracker_31( wire GEN_51; wire GEN_52; wire GEN_53; + wire GEN_54; + wire GEN_55; + wire GEN_56; + wire GEN_57; assign io_inner_acquire_ready = T_1245 ? 1'h1 : collect_iacq_data ? 1'h1 : 1'h0; assign io_inner_grant_valid = T_1418 ? 1'h1 : T_1407 ? io_outer_grant_valid : 1'h0; assign io_inner_grant_bits_addr_beat = T_1129_addr_beat; @@ -44648,9 +44692,9 @@ module BroadcastAcquireTracker_31( assign T_848 = {T_846,T_847}; assign T_850 = {1'h0,1'h1}; assign T_851 = {3'h7,T_850}; - assign GEN_0 = GEN_45 ? xact_wmask_buffer_3 : GEN_46 ? xact_wmask_buffer_2 : GEN_47 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; + assign GEN_0 = GEN_49 ? xact_wmask_buffer_3 : GEN_50 ? xact_wmask_buffer_2 : GEN_51 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; assign T_853 = {GEN_0,1'h1}; - assign GEN_1 = GEN_48 ? xact_wmask_buffer_3 : GEN_49 ? xact_wmask_buffer_2 : GEN_50 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; + assign GEN_1 = GEN_52 ? xact_wmask_buffer_3 : GEN_53 ? xact_wmask_buffer_2 : GEN_54 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; assign T_855 = {GEN_1,1'h1}; assign T_857 = {1'h0,3'h7}; assign T_858 = {1'h0,1'h1}; @@ -44678,7 +44722,7 @@ module BroadcastAcquireTracker_31( assign oacq_write_block_a_type = 3'h3; assign oacq_write_block_union = T_877; assign oacq_write_block_data = GEN_2; - assign GEN_2 = GEN_51 ? xact_data_buffer_3 : GEN_52 ? xact_data_buffer_2 : GEN_53 ? xact_data_buffer_1 : xact_data_buffer_0; + assign GEN_2 = GEN_55 ? xact_data_buffer_3 : GEN_56 ? xact_data_buffer_2 : GEN_57 ? xact_data_buffer_1 : xact_data_buffer_0; assign T_895 = xact_union[12:9]; assign T_896 = xact_union[8:6]; assign T_904 = {T_895,T_896}; @@ -45015,50 +45059,54 @@ module BroadcastAcquireTracker_31( assign T_1429 = T_1428 ? 3'h6 : 1'h0; assign T_1430 = 3'h6 == state; assign GEN_9 = T_325 & T_327; - assign GEN_10 = T_1149 & T_1151; - assign GEN_11 = T_1163 & T_1165; - assign GEN_12 = T_1189 & T_1191; - assign GEN_13 = 1'h0 == 1'h0; - assign GEN_14 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_15 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_16 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_17 = 1'h1 == 1'h0; - assign GEN_18 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_19 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_20 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_21 = 2'h2 == 1'h0; - assign GEN_22 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_23 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_24 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_25 = 2'h3 == 1'h0; - assign GEN_26 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_27 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_28 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_29 = 1'h0 == 1'h0; - assign GEN_30 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_31 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_32 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_33 = 1'h1 == 1'h0; - assign GEN_34 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_35 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_36 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_37 = 2'h2 == 1'h0; - assign GEN_38 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_39 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_40 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_41 = 2'h3 == 1'h0; - assign GEN_42 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_43 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_44 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_45 = 2'h3 == oacq_data_cnt; - assign GEN_46 = 2'h2 == oacq_data_cnt; - assign GEN_47 = 1'h1 == oacq_data_cnt; - assign GEN_48 = 2'h3 == oacq_data_cnt; - assign GEN_49 = 2'h2 == oacq_data_cnt; - assign GEN_50 = 1'h1 == oacq_data_cnt; - assign GEN_51 = 2'h3 == oacq_data_cnt; - assign GEN_52 = 2'h2 == oacq_data_cnt; - assign GEN_53 = 1'h1 == oacq_data_cnt; + assign GEN_10 = GEN_9 & T_329; + assign GEN_11 = T_1149 & T_1151; + assign GEN_12 = GEN_11 & T_1153; + assign GEN_13 = T_1163 & T_1165; + assign GEN_14 = GEN_13 & T_1167; + assign GEN_15 = T_1189 & T_1191; + assign GEN_16 = GEN_15 & T_1193; + assign GEN_17 = 1'h0 == 1'h0; + assign GEN_18 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_19 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_20 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_21 = 1'h1 == 1'h0; + assign GEN_22 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_23 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_24 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_25 = 2'h2 == 1'h0; + assign GEN_26 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_27 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_28 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_29 = 2'h3 == 1'h0; + assign GEN_30 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_31 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_32 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_33 = 1'h0 == 1'h0; + assign GEN_34 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_35 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_36 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_37 = 1'h1 == 1'h0; + assign GEN_38 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_39 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_40 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_41 = 2'h2 == 1'h0; + assign GEN_42 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_43 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_44 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_45 = 2'h3 == 1'h0; + assign GEN_46 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_47 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_48 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_49 = 2'h3 == oacq_data_cnt; + assign GEN_50 = 2'h2 == oacq_data_cnt; + assign GEN_51 = 1'h1 == oacq_data_cnt; + assign GEN_52 = 2'h3 == oacq_data_cnt; + assign GEN_53 = 2'h2 == oacq_data_cnt; + assign GEN_54 = 1'h1 == oacq_data_cnt; + assign GEN_55 = 2'h3 == oacq_data_cnt; + assign GEN_56 = 2'h2 == oacq_data_cnt; + assign GEN_57 = 1'h1 == oacq_data_cnt; `ifndef SYNTHESIS integer initvar; initial begin @@ -49524,12 +49572,12 @@ module BroadcastAcquireTracker_31( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_13) begin + if(GEN_17) begin xact_data_buffer_0 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_14) begin + if(GEN_18) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -49544,7 +49592,7 @@ module BroadcastAcquireTracker_31( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_15) begin + if(GEN_19) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -49559,7 +49607,7 @@ module BroadcastAcquireTracker_31( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_16) begin + if(GEN_20) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -49577,12 +49625,12 @@ module BroadcastAcquireTracker_31( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_17) begin + if(GEN_21) begin xact_data_buffer_1 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_18) begin + if(GEN_22) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -49597,7 +49645,7 @@ module BroadcastAcquireTracker_31( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_19) begin + if(GEN_23) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -49612,7 +49660,7 @@ module BroadcastAcquireTracker_31( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_20) begin + if(GEN_24) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -49630,12 +49678,12 @@ module BroadcastAcquireTracker_31( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_21) begin + if(GEN_25) begin xact_data_buffer_2 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_22) begin + if(GEN_26) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -49650,7 +49698,7 @@ module BroadcastAcquireTracker_31( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_23) begin + if(GEN_27) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -49665,7 +49713,7 @@ module BroadcastAcquireTracker_31( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_24) begin + if(GEN_28) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -49683,12 +49731,12 @@ module BroadcastAcquireTracker_31( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_25) begin + if(GEN_29) begin xact_data_buffer_3 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_26) begin + if(GEN_30) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -49703,7 +49751,7 @@ module BroadcastAcquireTracker_31( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_27) begin + if(GEN_31) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -49718,7 +49766,7 @@ module BroadcastAcquireTracker_31( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_28) begin + if(GEN_32) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -49736,12 +49784,12 @@ module BroadcastAcquireTracker_31( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_29) begin + if(GEN_33) begin xact_wmask_buffer_0 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_30) begin + if(GEN_34) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -49756,7 +49804,7 @@ module BroadcastAcquireTracker_31( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_31) begin + if(GEN_35) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -49771,7 +49819,7 @@ module BroadcastAcquireTracker_31( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_32) begin + if(GEN_36) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -49789,12 +49837,12 @@ module BroadcastAcquireTracker_31( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_33) begin + if(GEN_37) begin xact_wmask_buffer_1 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_34) begin + if(GEN_38) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -49809,7 +49857,7 @@ module BroadcastAcquireTracker_31( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_35) begin + if(GEN_39) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -49824,7 +49872,7 @@ module BroadcastAcquireTracker_31( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_36) begin + if(GEN_40) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -49842,12 +49890,12 @@ module BroadcastAcquireTracker_31( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_37) begin + if(GEN_41) begin xact_wmask_buffer_2 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_38) begin + if(GEN_42) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -49862,7 +49910,7 @@ module BroadcastAcquireTracker_31( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_39) begin + if(GEN_43) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -49877,7 +49925,7 @@ module BroadcastAcquireTracker_31( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_40) begin + if(GEN_44) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -49895,12 +49943,12 @@ module BroadcastAcquireTracker_31( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_41) begin + if(GEN_45) begin xact_wmask_buffer_3 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_42) begin + if(GEN_46) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -49915,7 +49963,7 @@ module BroadcastAcquireTracker_31( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_43) begin + if(GEN_47) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -49930,7 +49978,7 @@ module BroadcastAcquireTracker_31( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_44) begin + if(GEN_48) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -50319,7 +50367,7 @@ module BroadcastAcquireTracker_31( end end `ifndef SYNTHESIS - if(GEN_9 & T_329) begin + if(GEN_10) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches"); end `endif @@ -50329,7 +50377,7 @@ module BroadcastAcquireTracker_31( end `endif `ifndef SYNTHESIS - if(GEN_10 & T_1153) begin + if(GEN_12) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request."); end `endif @@ -50339,7 +50387,7 @@ module BroadcastAcquireTracker_31( end `endif `ifndef SYNTHESIS - if(GEN_11 & T_1167) begin + if(GEN_14) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request."); end `endif @@ -50349,7 +50397,7 @@ module BroadcastAcquireTracker_31( end `endif `ifndef SYNTHESIS - if(GEN_12 & T_1193) begin + if(GEN_16) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat."); end `endif @@ -51167,6 +51215,10 @@ module BroadcastAcquireTracker_32( wire GEN_51; wire GEN_52; wire GEN_53; + wire GEN_54; + wire GEN_55; + wire GEN_56; + wire GEN_57; assign io_inner_acquire_ready = T_1245 ? 1'h1 : collect_iacq_data ? 1'h1 : 1'h0; assign io_inner_grant_valid = T_1418 ? 1'h1 : T_1407 ? io_outer_grant_valid : 1'h0; assign io_inner_grant_bits_addr_beat = T_1129_addr_beat; @@ -51503,9 +51555,9 @@ module BroadcastAcquireTracker_32( assign T_848 = {T_846,T_847}; assign T_850 = {1'h0,1'h1}; assign T_851 = {3'h7,T_850}; - assign GEN_0 = GEN_45 ? xact_wmask_buffer_3 : GEN_46 ? xact_wmask_buffer_2 : GEN_47 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; + assign GEN_0 = GEN_49 ? xact_wmask_buffer_3 : GEN_50 ? xact_wmask_buffer_2 : GEN_51 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; assign T_853 = {GEN_0,1'h1}; - assign GEN_1 = GEN_48 ? xact_wmask_buffer_3 : GEN_49 ? xact_wmask_buffer_2 : GEN_50 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; + assign GEN_1 = GEN_52 ? xact_wmask_buffer_3 : GEN_53 ? xact_wmask_buffer_2 : GEN_54 ? xact_wmask_buffer_1 : xact_wmask_buffer_0; assign T_855 = {GEN_1,1'h1}; assign T_857 = {1'h0,3'h7}; assign T_858 = {1'h0,1'h1}; @@ -51533,7 +51585,7 @@ module BroadcastAcquireTracker_32( assign oacq_write_block_a_type = 3'h3; assign oacq_write_block_union = T_877; assign oacq_write_block_data = GEN_2; - assign GEN_2 = GEN_51 ? xact_data_buffer_3 : GEN_52 ? xact_data_buffer_2 : GEN_53 ? xact_data_buffer_1 : xact_data_buffer_0; + assign GEN_2 = GEN_55 ? xact_data_buffer_3 : GEN_56 ? xact_data_buffer_2 : GEN_57 ? xact_data_buffer_1 : xact_data_buffer_0; assign T_895 = xact_union[12:9]; assign T_896 = xact_union[8:6]; assign T_904 = {T_895,T_896}; @@ -51870,50 +51922,54 @@ module BroadcastAcquireTracker_32( assign T_1429 = T_1428 ? 3'h6 : 1'h0; assign T_1430 = 3'h6 == state; assign GEN_9 = T_325 & T_327; - assign GEN_10 = T_1149 & T_1151; - assign GEN_11 = T_1163 & T_1165; - assign GEN_12 = T_1189 & T_1191; - assign GEN_13 = 1'h0 == 1'h0; - assign GEN_14 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_15 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_16 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_17 = 1'h1 == 1'h0; - assign GEN_18 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_19 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_20 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_21 = 2'h2 == 1'h0; - assign GEN_22 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_23 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_24 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_25 = 2'h3 == 1'h0; - assign GEN_26 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_27 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_28 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_29 = 1'h0 == 1'h0; - assign GEN_30 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_31 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_32 = 1'h0 == io_inner_acquire_bits_addr_beat; - assign GEN_33 = 1'h1 == 1'h0; - assign GEN_34 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_35 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_36 = 1'h1 == io_inner_acquire_bits_addr_beat; - assign GEN_37 = 2'h2 == 1'h0; - assign GEN_38 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_39 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_40 = 2'h2 == io_inner_acquire_bits_addr_beat; - assign GEN_41 = 2'h3 == 1'h0; - assign GEN_42 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_43 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_44 = 2'h3 == io_inner_acquire_bits_addr_beat; - assign GEN_45 = 2'h3 == oacq_data_cnt; - assign GEN_46 = 2'h2 == oacq_data_cnt; - assign GEN_47 = 1'h1 == oacq_data_cnt; - assign GEN_48 = 2'h3 == oacq_data_cnt; - assign GEN_49 = 2'h2 == oacq_data_cnt; - assign GEN_50 = 1'h1 == oacq_data_cnt; - assign GEN_51 = 2'h3 == oacq_data_cnt; - assign GEN_52 = 2'h2 == oacq_data_cnt; - assign GEN_53 = 1'h1 == oacq_data_cnt; + assign GEN_10 = GEN_9 & T_329; + assign GEN_11 = T_1149 & T_1151; + assign GEN_12 = GEN_11 & T_1153; + assign GEN_13 = T_1163 & T_1165; + assign GEN_14 = GEN_13 & T_1167; + assign GEN_15 = T_1189 & T_1191; + assign GEN_16 = GEN_15 & T_1193; + assign GEN_17 = 1'h0 == 1'h0; + assign GEN_18 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_19 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_20 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_21 = 1'h1 == 1'h0; + assign GEN_22 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_23 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_24 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_25 = 2'h2 == 1'h0; + assign GEN_26 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_27 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_28 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_29 = 2'h3 == 1'h0; + assign GEN_30 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_31 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_32 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_33 = 1'h0 == 1'h0; + assign GEN_34 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_35 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_36 = 1'h0 == io_inner_acquire_bits_addr_beat; + assign GEN_37 = 1'h1 == 1'h0; + assign GEN_38 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_39 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_40 = 1'h1 == io_inner_acquire_bits_addr_beat; + assign GEN_41 = 2'h2 == 1'h0; + assign GEN_42 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_43 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_44 = 2'h2 == io_inner_acquire_bits_addr_beat; + assign GEN_45 = 2'h3 == 1'h0; + assign GEN_46 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_47 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_48 = 2'h3 == io_inner_acquire_bits_addr_beat; + assign GEN_49 = 2'h3 == oacq_data_cnt; + assign GEN_50 = 2'h2 == oacq_data_cnt; + assign GEN_51 = 1'h1 == oacq_data_cnt; + assign GEN_52 = 2'h3 == oacq_data_cnt; + assign GEN_53 = 2'h2 == oacq_data_cnt; + assign GEN_54 = 1'h1 == oacq_data_cnt; + assign GEN_55 = 2'h3 == oacq_data_cnt; + assign GEN_56 = 2'h2 == oacq_data_cnt; + assign GEN_57 = 1'h1 == oacq_data_cnt; `ifndef SYNTHESIS integer initvar; initial begin @@ -56379,12 +56435,12 @@ module BroadcastAcquireTracker_32( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_13) begin + if(GEN_17) begin xact_data_buffer_0 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_14) begin + if(GEN_18) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -56399,7 +56455,7 @@ module BroadcastAcquireTracker_32( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_15) begin + if(GEN_19) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -56414,7 +56470,7 @@ module BroadcastAcquireTracker_32( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_16) begin + if(GEN_20) begin xact_data_buffer_0 <= GEN_3; end else begin ; @@ -56432,12 +56488,12 @@ module BroadcastAcquireTracker_32( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_17) begin + if(GEN_21) begin xact_data_buffer_1 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_18) begin + if(GEN_22) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -56452,7 +56508,7 @@ module BroadcastAcquireTracker_32( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_19) begin + if(GEN_23) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -56467,7 +56523,7 @@ module BroadcastAcquireTracker_32( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_20) begin + if(GEN_24) begin xact_data_buffer_1 <= GEN_3; end else begin ; @@ -56485,12 +56541,12 @@ module BroadcastAcquireTracker_32( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_21) begin + if(GEN_25) begin xact_data_buffer_2 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_22) begin + if(GEN_26) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -56505,7 +56561,7 @@ module BroadcastAcquireTracker_32( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_23) begin + if(GEN_27) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -56520,7 +56576,7 @@ module BroadcastAcquireTracker_32( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_24) begin + if(GEN_28) begin xact_data_buffer_2 <= GEN_3; end else begin ; @@ -56538,12 +56594,12 @@ module BroadcastAcquireTracker_32( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_25) begin + if(GEN_29) begin xact_data_buffer_3 <= GEN_5; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_26) begin + if(GEN_30) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -56558,7 +56614,7 @@ module BroadcastAcquireTracker_32( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_27) begin + if(GEN_31) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -56573,7 +56629,7 @@ module BroadcastAcquireTracker_32( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_28) begin + if(GEN_32) begin xact_data_buffer_3 <= GEN_3; end else begin ; @@ -56591,12 +56647,12 @@ module BroadcastAcquireTracker_32( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_29) begin + if(GEN_33) begin xact_wmask_buffer_0 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_30) begin + if(GEN_34) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -56611,7 +56667,7 @@ module BroadcastAcquireTracker_32( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_31) begin + if(GEN_35) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -56626,7 +56682,7 @@ module BroadcastAcquireTracker_32( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_32) begin + if(GEN_36) begin xact_wmask_buffer_0 <= GEN_4; end else begin ; @@ -56644,12 +56700,12 @@ module BroadcastAcquireTracker_32( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_33) begin + if(GEN_37) begin xact_wmask_buffer_1 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_34) begin + if(GEN_38) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -56664,7 +56720,7 @@ module BroadcastAcquireTracker_32( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_35) begin + if(GEN_39) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -56679,7 +56735,7 @@ module BroadcastAcquireTracker_32( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_36) begin + if(GEN_40) begin xact_wmask_buffer_1 <= GEN_4; end else begin ; @@ -56697,12 +56753,12 @@ module BroadcastAcquireTracker_32( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_37) begin + if(GEN_41) begin xact_wmask_buffer_2 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_38) begin + if(GEN_42) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -56717,7 +56773,7 @@ module BroadcastAcquireTracker_32( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_39) begin + if(GEN_43) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -56732,7 +56788,7 @@ module BroadcastAcquireTracker_32( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_40) begin + if(GEN_44) begin xact_wmask_buffer_2 <= GEN_4; end else begin ; @@ -56750,12 +56806,12 @@ module BroadcastAcquireTracker_32( end else begin if(T_1245) begin if(io_inner_acquire_valid) begin - if(GEN_41) begin + if(GEN_45) begin xact_wmask_buffer_3 <= GEN_6; end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_42) begin + if(GEN_46) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -56770,7 +56826,7 @@ module BroadcastAcquireTracker_32( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_43) begin + if(GEN_47) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -56785,7 +56841,7 @@ module BroadcastAcquireTracker_32( end else begin if(collect_iacq_data) begin if(io_inner_acquire_valid) begin - if(GEN_44) begin + if(GEN_48) begin xact_wmask_buffer_3 <= GEN_4; end else begin ; @@ -57174,7 +57230,7 @@ module BroadcastAcquireTracker_32( end end `ifndef SYNTHESIS - if(GEN_9 & T_329) begin + if(GEN_10) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Broadcast Hub does not support PutAtomics or prefetches"); end `endif @@ -57184,7 +57240,7 @@ module BroadcastAcquireTracker_32( end `endif `ifndef SYNTHESIS - if(GEN_10 & T_1153) begin + if(GEN_12) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different network source than initial request."); end `endif @@ -57194,7 +57250,7 @@ module BroadcastAcquireTracker_32( end `endif `ifndef SYNTHESIS - if(GEN_11 & T_1167) begin + if(GEN_14) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker accepted data beat from different client transaction than initial request."); end `endif @@ -57204,7 +57260,7 @@ module BroadcastAcquireTracker_32( end `endif `ifndef SYNTHESIS - if(GEN_12 & T_1193) begin + if(GEN_16) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): AcquireTracker initialized with a tail data beat."); end `endif @@ -61381,6 +61437,7 @@ module L2BroadcastHub( wire GEN_24; wire GEN_25; wire GEN_26; + wire GEN_27; BroadcastVoluntaryReleaseTracker T_1060 ( .clk(T_1060_clk), .reset(T_1060_reset), @@ -62872,7 +62929,7 @@ module L2BroadcastHub( assign T_2980_5 = T_1065_io_inner_finish_ready; assign T_2980_6 = T_1066_io_inner_finish_ready; assign T_2980_7 = T_1067_io_inner_finish_ready; - assign GEN_2 = GEN_14 ? T_2980_7 : GEN_15 ? T_2980_6 : GEN_16 ? T_2980_5 : GEN_17 ? T_2980_4 : GEN_18 ? T_2980_3 : GEN_19 ? T_2980_2 : GEN_20 ? T_2980_1 : T_2980_0; + assign GEN_2 = GEN_15 ? T_2980_7 : GEN_16 ? T_2980_6 : GEN_17 ? T_2980_5 : GEN_18 ? T_2980_4 : GEN_19 ? T_2980_3 : GEN_20 ? T_2980_2 : GEN_21 ? T_2980_1 : T_2980_0; assign outer_arb_clk = clk; assign outer_arb_reset = reset; assign outer_arb_io_in_0_acquire_valid = T_1060_io_outer_acquire_valid; @@ -62975,10 +63032,10 @@ module L2BroadcastHub( assign T_3152 = outer_data_ptr_loc == 1'h0; assign free_sdq = T_3151 & T_3152; assign T_3156 = 1'h1 == outer_data_ptr_loc; - assign GEN_3 = GEN_21 ? vwbdq_3 : GEN_22 ? vwbdq_2 : GEN_23 ? vwbdq_1 : vwbdq_0; + assign GEN_3 = GEN_22 ? vwbdq_3 : GEN_23 ? vwbdq_2 : GEN_24 ? vwbdq_1 : vwbdq_0; assign T_3157 = T_3156 ? GEN_3 : io_inner_release_bits_data; assign T_3158 = 1'h0 == outer_data_ptr_loc; - assign GEN_4 = GEN_24 ? sdq_3 : GEN_25 ? sdq_2 : GEN_26 ? sdq_1 : sdq_0; + assign GEN_4 = GEN_25 ? sdq_3 : GEN_26 ? sdq_2 : GEN_27 ? sdq_1 : sdq_0; assign T_3159 = T_3158 ? GEN_4 : T_3157; assign T_3160 = io_outer_acquire_valid | sdq_enq; assign T_3162 = 1'h1 << outer_data_ptr_idx; @@ -63006,27 +63063,28 @@ module L2BroadcastHub( assign T_3195 = T_3191 & T_3194; assign T_3196 = T_3168 | T_3195; assign GEN_5 = T_2948 & T_2950; - assign GEN_6 = 1'h0 == sdq_alloc_id; - assign GEN_7 = 1'h1 == sdq_alloc_id; - assign GEN_8 = 2'h2 == sdq_alloc_id; - assign GEN_9 = 2'h3 == sdq_alloc_id; - assign GEN_10 = 1'h0 == rel_data_cnt; - assign GEN_11 = 1'h1 == rel_data_cnt; - assign GEN_12 = 2'h2 == rel_data_cnt; - assign GEN_13 = 2'h3 == rel_data_cnt; - assign GEN_14 = 3'h7 == io_inner_finish_bits_manager_xact_id; - assign GEN_15 = 3'h6 == io_inner_finish_bits_manager_xact_id; - assign GEN_16 = 3'h5 == io_inner_finish_bits_manager_xact_id; - assign GEN_17 = 3'h4 == io_inner_finish_bits_manager_xact_id; - assign GEN_18 = 2'h3 == io_inner_finish_bits_manager_xact_id; - assign GEN_19 = 2'h2 == io_inner_finish_bits_manager_xact_id; - assign GEN_20 = 1'h1 == io_inner_finish_bits_manager_xact_id; - assign GEN_21 = 2'h3 == outer_data_ptr_idx; - assign GEN_22 = 2'h2 == outer_data_ptr_idx; - assign GEN_23 = 1'h1 == outer_data_ptr_idx; - assign GEN_24 = 2'h3 == outer_data_ptr_idx; - assign GEN_25 = 2'h2 == outer_data_ptr_idx; - assign GEN_26 = 1'h1 == outer_data_ptr_idx; + assign GEN_6 = GEN_5 & T_2952; + assign GEN_7 = 1'h0 == sdq_alloc_id; + assign GEN_8 = 1'h1 == sdq_alloc_id; + assign GEN_9 = 2'h2 == sdq_alloc_id; + assign GEN_10 = 2'h3 == sdq_alloc_id; + assign GEN_11 = 1'h0 == rel_data_cnt; + assign GEN_12 = 1'h1 == rel_data_cnt; + assign GEN_13 = 2'h2 == rel_data_cnt; + assign GEN_14 = 2'h3 == rel_data_cnt; + assign GEN_15 = 3'h7 == io_inner_finish_bits_manager_xact_id; + assign GEN_16 = 3'h6 == io_inner_finish_bits_manager_xact_id; + assign GEN_17 = 3'h5 == io_inner_finish_bits_manager_xact_id; + assign GEN_18 = 3'h4 == io_inner_finish_bits_manager_xact_id; + assign GEN_19 = 2'h3 == io_inner_finish_bits_manager_xact_id; + assign GEN_20 = 2'h2 == io_inner_finish_bits_manager_xact_id; + assign GEN_21 = 1'h1 == io_inner_finish_bits_manager_xact_id; + assign GEN_22 = 2'h3 == outer_data_ptr_idx; + assign GEN_23 = 2'h2 == outer_data_ptr_idx; + assign GEN_24 = 1'h1 == outer_data_ptr_idx; + assign GEN_25 = 2'h3 == outer_data_ptr_idx; + assign GEN_26 = 2'h2 == outer_data_ptr_idx; + assign GEN_27 = 1'h1 == outer_data_ptr_idx; `ifndef SYNTHESIS integer initvar; initial begin @@ -63048,7 +63106,7 @@ module L2BroadcastHub( ; end else begin if(sdq_enq) begin - if(GEN_6) begin + if(GEN_7) begin sdq_0 <= GEN_0; end else begin ; @@ -63061,7 +63119,7 @@ module L2BroadcastHub( ; end else begin if(sdq_enq) begin - if(GEN_7) begin + if(GEN_8) begin sdq_1 <= GEN_0; end else begin ; @@ -63074,7 +63132,7 @@ module L2BroadcastHub( ; end else begin if(sdq_enq) begin - if(GEN_8) begin + if(GEN_9) begin sdq_2 <= GEN_0; end else begin ; @@ -63087,7 +63145,7 @@ module L2BroadcastHub( ; end else begin if(sdq_enq) begin - if(GEN_9) begin + if(GEN_10) begin sdq_3 <= GEN_0; end else begin ; @@ -63118,7 +63176,7 @@ module L2BroadcastHub( ; end else begin if(vwbdq_enq) begin - if(GEN_10) begin + if(GEN_11) begin vwbdq_0 <= GEN_1; end else begin ; @@ -63131,7 +63189,7 @@ module L2BroadcastHub( ; end else begin if(vwbdq_enq) begin - if(GEN_11) begin + if(GEN_12) begin vwbdq_1 <= GEN_1; end else begin ; @@ -63144,7 +63202,7 @@ module L2BroadcastHub( ; end else begin if(vwbdq_enq) begin - if(GEN_12) begin + if(GEN_13) begin vwbdq_2 <= GEN_1; end else begin ; @@ -63157,7 +63215,7 @@ module L2BroadcastHub( ; end else begin if(vwbdq_enq) begin - if(GEN_13) begin + if(GEN_14) begin vwbdq_3 <= GEN_1; end else begin ; @@ -63167,7 +63225,7 @@ module L2BroadcastHub( end end `ifndef SYNTHESIS - if(GEN_5 & T_2952) begin + if(GEN_6) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Non-voluntary release should always have a Tracker waiting for it."); end `endif @@ -63905,8 +63963,10 @@ module NastiErrorSlave( wire T_388; wire T_391; wire T_392; - reg GEN_0; - reg GEN_1; + wire GEN_0; + wire GEN_1; + reg GEN_2; + reg GEN_3; Queue_36 r_queue ( .clk(r_queue_clk), .reset(r_queue_reset), @@ -63954,14 +64014,14 @@ module NastiErrorSlave( assign io_b_valid = T_388; assign io_b_bits_resp = 2'h3; assign io_b_bits_id = b_queue_io_deq_bits; - assign io_b_bits_user = GEN_0; + assign io_b_bits_user = GEN_2; assign io_ar_ready = r_queue_io_enq_ready; assign io_r_valid = T_349; assign io_r_bits_resp = 2'h3; assign io_r_bits_data = 1'h0; assign io_r_bits_last = T_359; assign io_r_bits_id = r_queue_io_deq_bits_id; - assign io_r_bits_user = GEN_1; + assign io_r_bits_user = GEN_3; assign T_322 = io_ar_ready & io_ar_valid; assign T_324 = reset == 1'h0; assign T_325 = io_aw_ready & io_aw_valid; @@ -64008,6 +64068,8 @@ module NastiErrorSlave( assign T_388 = b_queue_io_deq_valid & T_387; assign T_391 = draining == 1'h0; assign T_392 = io_b_ready & T_391; + assign GEN_0 = T_322 & T_324; + assign GEN_1 = T_325 & T_327; `ifndef SYNTHESIS integer initvar; initial begin @@ -64015,8 +64077,8 @@ module NastiErrorSlave( responding = {1{$random}}; beats_left = {1{$random}}; draining = {1{$random}}; - GEN_0 = {1{$random}}; - GEN_1 = {1{$random}}; + GEN_2 = {1{$random}}; + GEN_3 = {1{$random}}; end `endif always @(posedge clk) begin @@ -64076,12 +64138,12 @@ module NastiErrorSlave( end end `ifndef SYNTHESIS - if(T_322 & T_324) begin + if(GEN_0) begin $fwrite(32'h80000002,"Invalid read address %h\n",io_ar_bits_addr); end `endif `ifndef SYNTHESIS - if(T_325 & T_327) begin + if(GEN_1) begin $fwrite(32'h80000002,"Invalid write address %h\n",io_aw_bits_addr); end `endif @@ -66096,8 +66158,10 @@ module NastiErrorSlave_40( wire T_381; wire T_384; wire T_385; - reg GEN_0; - reg GEN_1; + wire GEN_0; + wire GEN_1; + reg GEN_2; + reg GEN_3; Queue_36 r_queue ( .clk(r_queue_clk), .reset(r_queue_reset), @@ -66145,14 +66209,14 @@ module NastiErrorSlave_40( assign io_b_valid = T_381; assign io_b_bits_resp = 2'h3; assign io_b_bits_id = b_queue_io_deq_bits; - assign io_b_bits_user = GEN_0; + assign io_b_bits_user = GEN_2; assign io_ar_ready = r_queue_io_enq_ready; assign io_r_valid = T_349; assign io_r_bits_resp = 2'h3; assign io_r_bits_data = 1'h0; assign io_r_bits_last = T_352; assign io_r_bits_id = r_queue_io_deq_bits_id; - assign io_r_bits_user = GEN_1; + assign io_r_bits_user = GEN_3; assign T_322 = io_ar_ready & io_ar_valid; assign T_324 = reset == 1'h0; assign T_325 = io_aw_ready & io_aw_valid; @@ -66199,6 +66263,8 @@ module NastiErrorSlave_40( assign T_381 = b_queue_io_deq_valid & T_380; assign T_384 = draining == 1'h0; assign T_385 = io_b_ready & T_384; + assign GEN_0 = T_322 & T_324; + assign GEN_1 = T_325 & T_327; `ifndef SYNTHESIS integer initvar; initial begin @@ -66206,8 +66272,8 @@ module NastiErrorSlave_40( responding = {1{$random}}; beats_left = {1{$random}}; draining = {1{$random}}; - GEN_0 = {1{$random}}; - GEN_1 = {1{$random}}; + GEN_2 = {1{$random}}; + GEN_3 = {1{$random}}; end `endif always @(posedge clk) begin @@ -66267,12 +66333,12 @@ module NastiErrorSlave_40( end end `ifndef SYNTHESIS - if(T_322 & T_324) begin + if(GEN_0) begin $fwrite(32'h80000002,"Invalid read address %h\n",io_ar_bits_addr); end `endif `ifndef SYNTHESIS - if(T_325 & T_327) begin + if(GEN_1) begin $fwrite(32'h80000002,"Invalid write address %h\n",io_aw_bits_addr); end `endif @@ -80203,6 +80269,8 @@ module TileLinkIONarrower( wire GEN_2; wire GEN_3; wire GEN_4; + wire GEN_5; + wire GEN_6; ReorderQueue T_1415 ( .clk(T_1415_clk), .reset(T_1415_reset), @@ -80659,9 +80727,11 @@ module TileLinkIONarrower( assign T_1897 = T_1896[1:0]; assign T_1898 = T_1893 ? 1'h0 : T_1897; assign GEN_1 = T_980 & T_982; - assign GEN_2 = T_1015 & T_1017; - assign GEN_3 = 1'h0 == T_1660; - assign GEN_4 = 1'h1 == T_1660; + assign GEN_2 = GEN_1 & T_984; + assign GEN_3 = T_1015 & T_1017; + assign GEN_4 = GEN_3 & T_1019; + assign GEN_5 = 1'h0 == T_1660; + assign GEN_6 = 1'h1 == T_1660; `ifndef SYNTHESIS integer initvar; initial begin @@ -80770,7 +80840,7 @@ module TileLinkIONarrower( ; end else begin if(T_1877) begin - if(GEN_3) begin + if(GEN_5) begin T_1651_0 <= GEN_0; end else begin ; @@ -80783,7 +80853,7 @@ module TileLinkIONarrower( ; end else begin if(T_1877) begin - if(GEN_4) begin + if(GEN_6) begin T_1651_1 <= GEN_0; end else begin ; @@ -80854,7 +80924,7 @@ module TileLinkIONarrower( end end `ifndef SYNTHESIS - if(GEN_1 & T_984) begin + if(GEN_2) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Can't perform Put wider than outer width"); end `endif @@ -80864,7 +80934,7 @@ module TileLinkIONarrower( end `endif `ifndef SYNTHESIS - if(GEN_2 & T_1019) begin + if(GEN_4) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Can't perform Get wider than outer width"); end `endif @@ -82447,8 +82517,10 @@ module NastiIOTileLinkIOConverter( wire T_1157; wire GEN_0; wire GEN_1; - reg GEN_2; - reg GEN_3; + wire GEN_2; + wire GEN_3; + reg GEN_4; + reg GEN_5; ReorderQueue_70 roq ( .clk(roq_clk), .reset(roq_reset), @@ -82703,7 +82775,7 @@ module NastiIOTileLinkIOConverter( assign gnt_arb_io_in_0_bits_is_builtin_type = T_1050_is_builtin_type; assign gnt_arb_io_in_0_bits_g_type = T_1050_g_type; assign gnt_arb_io_in_0_bits_data = T_1050_data; - assign gnt_arb_io_in_0_bits_client_id = GEN_2; + assign gnt_arb_io_in_0_bits_client_id = GEN_4; assign gnt_arb_io_in_1_valid = io_nasti_b_valid; assign gnt_arb_io_in_1_bits_addr_beat = T_1109_addr_beat; assign gnt_arb_io_in_1_bits_client_xact_id = T_1109_client_xact_id; @@ -82711,7 +82783,7 @@ module NastiIOTileLinkIOConverter( assign gnt_arb_io_in_1_bits_is_builtin_type = T_1109_is_builtin_type; assign gnt_arb_io_in_1_bits_g_type = T_1109_g_type; assign gnt_arb_io_in_1_bits_data = T_1109_data; - assign gnt_arb_io_in_1_bits_client_id = GEN_3; + assign gnt_arb_io_in_1_bits_client_id = GEN_5; assign gnt_arb_io_out_ready = io_tl_grant_ready; assign T_1014 = {roq_io_deq_data_byteOff,3'h0}; assign T_1015 = io_nasti_r_bits_data << T_1014; @@ -82743,7 +82815,9 @@ module NastiIOTileLinkIOConverter( assign T_1155 = T_1151 == 1'h0; assign T_1157 = reset == 1'h0; assign GEN_0 = T_1142 & T_1144; - assign GEN_1 = T_1153 & T_1155; + assign GEN_1 = GEN_0 & T_1146; + assign GEN_2 = T_1153 & T_1155; + assign GEN_3 = GEN_2 & T_1157; `ifndef SYNTHESIS integer initvar; initial begin @@ -82752,8 +82826,8 @@ module NastiIOTileLinkIOConverter( w_inflight = {1{$random}}; nasti_cnt_out = {1{$random}}; tl_cnt_in = {1{$random}}; - GEN_2 = {1{$random}}; - GEN_3 = {1{$random}}; + GEN_4 = {1{$random}}; + GEN_5 = {1{$random}}; end `endif always @(posedge clk) begin @@ -82806,7 +82880,7 @@ module NastiIOTileLinkIOConverter( end end `ifndef SYNTHESIS - if(GEN_0 & T_1146) begin + if(GEN_1) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): NASTI read error"); end `endif @@ -82816,7 +82890,7 @@ module NastiIOTileLinkIOConverter( end `endif `ifndef SYNTHESIS - if(GEN_1 & T_1157) begin + if(GEN_3) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): NASTI write error"); end `endif @@ -83839,17 +83913,18 @@ module RTC( wire T_321; wire GEN_2; wire GEN_3; - reg [31:0] GEN_4; - reg [7:0] GEN_5; - reg [2:0] GEN_6; - reg [1:0] GEN_7; - reg GEN_8; - reg [3:0] GEN_9; - reg [2:0] GEN_10; - reg [3:0] GEN_11; + wire GEN_4; + reg [31:0] GEN_5; + reg [7:0] GEN_6; + reg [2:0] GEN_7; + reg [1:0] GEN_8; + reg GEN_9; + reg [3:0] GEN_10; + reg [2:0] GEN_11; reg [3:0] GEN_12; - reg [4:0] GEN_13; - reg GEN_14; + reg [3:0] GEN_13; + reg [4:0] GEN_14; + reg GEN_15; assign io_aw_valid = sending_addr; assign io_aw_bits_addr = T_276_addr; assign io_aw_bits_len = T_276_len; @@ -83869,17 +83944,17 @@ module RTC( assign io_w_bits_user = T_300_user; assign io_b_ready = 1'h1; assign io_ar_valid = 1'h0; - assign io_ar_bits_addr = GEN_4; - assign io_ar_bits_len = GEN_5; - assign io_ar_bits_size = GEN_6; - assign io_ar_bits_burst = GEN_7; - assign io_ar_bits_lock = GEN_8; - assign io_ar_bits_cache = GEN_9; - assign io_ar_bits_prot = GEN_10; - assign io_ar_bits_qos = GEN_11; - assign io_ar_bits_region = GEN_12; - assign io_ar_bits_id = GEN_13; - assign io_ar_bits_user = GEN_14; + assign io_ar_bits_addr = GEN_5; + assign io_ar_bits_len = GEN_6; + assign io_ar_bits_size = GEN_7; + assign io_ar_bits_burst = GEN_8; + assign io_ar_bits_lock = GEN_9; + assign io_ar_bits_cache = GEN_10; + assign io_ar_bits_prot = GEN_11; + assign io_ar_bits_qos = GEN_12; + assign io_ar_bits_region = GEN_13; + assign io_ar_bits_id = GEN_14; + assign io_ar_bits_user = GEN_15; assign io_r_ready = 1'h0; assign addrTable_0 = 31'h4000b808; assign rtc_tick = T_217 == 7'h63; @@ -83921,7 +83996,8 @@ module RTC( assign T_319 = T_315 == 1'h0; assign T_321 = reset == 1'h0; assign GEN_2 = T_317 & T_319; - assign GEN_3 = 1'h0 == io_b_bits_id; + assign GEN_3 = GEN_2 & T_321; + assign GEN_4 = 1'h0 == io_b_bits_id; `ifndef SYNTHESIS integer initvar; initial begin @@ -83931,7 +84007,6 @@ module RTC( sending_addr = {1{$random}}; sending_data = {1{$random}}; send_acked_0 = {1{$random}}; - GEN_4 = {1{$random}}; GEN_5 = {1{$random}}; GEN_6 = {1{$random}}; GEN_7 = {1{$random}}; @@ -83942,6 +84017,7 @@ module RTC( GEN_12 = {1{$random}}; GEN_13 = {1{$random}}; GEN_14 = {1{$random}}; + GEN_15 = {1{$random}}; end `endif always @(posedge clk) begin @@ -83989,7 +84065,7 @@ module RTC( send_acked_0 <= T_233_0; end else begin if(T_258) begin - if(GEN_3) begin + if(GEN_4) begin send_acked_0 <= GEN_0; end else begin if(rtc_tick) begin @@ -84007,7 +84083,7 @@ module RTC( end end `ifndef SYNTHESIS - if(GEN_2 & T_321) begin + if(GEN_3) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Not all clocks were updated for rtc tick"); end `endif @@ -84411,6 +84487,7 @@ module SmiIONastiWriteIOConverter( wire T_227; wire T_228; wire GEN_0; + wire GEN_1; assign io_aw_ready = T_173; assign io_w_ready = T_174; assign io_b_valid = T_181; @@ -84465,6 +84542,7 @@ module SmiIONastiWriteIOConverter( assign T_227 = io_smi_resp_ready & io_smi_resp_valid; assign T_228 = io_b_ready & io_b_valid; assign GEN_0 = T_149 & T_151; + assign GEN_1 = GEN_0 & T_153; `ifndef SYNTHESIS integer initvar; initial begin @@ -84611,7 +84689,7 @@ module SmiIONastiWriteIOConverter( end end `ifndef SYNTHESIS - if(GEN_0 & T_153) begin + if(GEN_1) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Nasti size must be >= Smi size"); end `endif @@ -85608,6 +85686,7 @@ module SmiIONastiWriteIOConverter_80( wire T_227; wire T_228; wire GEN_0; + wire GEN_1; assign io_aw_ready = T_173; assign io_w_ready = T_174; assign io_b_valid = T_181; @@ -85662,6 +85741,7 @@ module SmiIONastiWriteIOConverter_80( assign T_227 = io_smi_resp_ready & io_smi_resp_valid; assign T_228 = io_b_ready & io_b_valid; assign GEN_0 = T_149 & T_151; + assign GEN_1 = GEN_0 & T_153; `ifndef SYNTHESIS integer initvar; initial begin @@ -85808,7 +85888,7 @@ module SmiIONastiWriteIOConverter_80( end end `ifndef SYNTHESIS - if(GEN_0 & T_153) begin + if(GEN_1) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Nasti size must be >= Smi size"); end `endif @@ -86677,8 +86757,13 @@ module MemIONastiIOConverter( wire GEN_2; wire GEN_3; wire GEN_4; - reg GEN_5; - reg GEN_6; + wire GEN_5; + wire GEN_6; + wire GEN_7; + wire GEN_8; + wire GEN_9; + reg GEN_10; + reg GEN_11; Queue_37 id_q ( .clk(id_q_clk), .reset(id_q_reset), @@ -86695,14 +86780,14 @@ module MemIONastiIOConverter( assign io_nasti_b_valid = T_446; assign io_nasti_b_bits_resp = 1'h0; assign io_nasti_b_bits_id = id_q_io_deq_bits; - assign io_nasti_b_bits_user = GEN_5; + assign io_nasti_b_bits_user = GEN_10; assign io_nasti_ar_ready = T_444; assign io_nasti_r_valid = io_mem_resp_valid; assign io_nasti_r_bits_resp = 1'h0; assign io_nasti_r_bits_data = io_mem_resp_bits_data; assign io_nasti_r_bits_last = mif_wrap_out; assign io_nasti_r_bits_id = io_mem_resp_bits_tag; - assign io_nasti_r_bits_user = GEN_6; + assign io_nasti_r_bits_user = GEN_11; assign io_mem_req_cmd_valid = T_441; assign io_mem_req_cmd_bits_addr = T_438; assign io_mem_req_cmd_bits_tag = T_439; @@ -86768,18 +86853,23 @@ module MemIONastiIOConverter( assign T_457 = T_453 == 1'h0; assign T_459 = reset == 1'h0; assign GEN_0 = T_387 & T_389; - assign GEN_1 = T_398 & T_400; - assign GEN_2 = T_409 & T_411; - assign GEN_3 = T_420 & T_422; - assign GEN_4 = T_455 & T_457; + assign GEN_1 = GEN_0 & T_391; + assign GEN_2 = T_398 & T_400; + assign GEN_3 = GEN_2 & T_402; + assign GEN_4 = T_409 & T_411; + assign GEN_5 = GEN_4 & T_413; + assign GEN_6 = T_420 & T_422; + assign GEN_7 = GEN_6 & T_424; + assign GEN_8 = T_455 & T_457; + assign GEN_9 = GEN_8 & T_459; `ifndef SYNTHESIS integer initvar; initial begin #0.002; mif_cnt_out = {1{$random}}; b_ok = {1{$random}}; - GEN_5 = {1{$random}}; - GEN_6 = {1{$random}}; + GEN_10 = {1{$random}}; + GEN_11 = {1{$random}}; end `endif always @(posedge clk) begin @@ -86806,7 +86896,7 @@ module MemIONastiIOConverter( end end `ifndef SYNTHESIS - if(GEN_0 & T_391) begin + if(GEN_1) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Nasti data size does not match MemIO data size"); end `endif @@ -86816,7 +86906,7 @@ module MemIONastiIOConverter( end `endif `ifndef SYNTHESIS - if(GEN_1 & T_402) begin + if(GEN_3) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Nasti data size does not match MemIO data size"); end `endif @@ -86826,7 +86916,7 @@ module MemIONastiIOConverter( end `endif `ifndef SYNTHESIS - if(GEN_2 & T_413) begin + if(GEN_5) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Nasti length does not match number of MemIO beats"); end `endif @@ -86836,7 +86926,7 @@ module MemIONastiIOConverter( end `endif `ifndef SYNTHESIS - if(GEN_3 & T_424) begin + if(GEN_7) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Nasti length does not match number of MemIO beats"); end `endif @@ -86846,7 +86936,7 @@ module MemIONastiIOConverter( end `endif `ifndef SYNTHESIS - if(GEN_4 & T_459) begin + if(GEN_9) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): MemIO must write full cache line"); end `endif @@ -91995,9 +92085,11 @@ module NastiROM( wire GEN_203; wire GEN_204; wire GEN_205; - reg [1:0] GEN_206; - reg [4:0] GEN_207; - reg GEN_208; + wire GEN_206; + wire GEN_207; + reg [1:0] GEN_208; + reg [4:0] GEN_209; + reg GEN_210; Queue_89 T_334 ( .clk(T_334_clk), .reset(T_334_reset), @@ -92032,9 +92124,9 @@ module NastiROM( assign io_aw_ready = 1'h0; assign io_w_ready = 1'h0; assign io_b_valid = 1'h0; - assign io_b_bits_resp = GEN_206; - assign io_b_bits_id = GEN_207; - assign io_b_bits_user = GEN_208; + assign io_b_bits_resp = GEN_208; + assign io_b_bits_id = GEN_209; + assign io_b_bits_user = GEN_210; assign io_ar_ready = T_334_io_enq_ready; assign io_r_valid = T_334_io_deq_valid; assign io_r_bits_resp = T_566_resp; @@ -92140,9 +92232,9 @@ module NastiROM( assign GEN_3 = $signed(1'h0); assign T_500 = $signed(T_498) >= $signed(GEN_3); assign T_501 = T_334_io_deq_bits_addr[2]; - assign GEN_0 = GEN_8 ? rom_66 : GEN_9 ? rom_65 : GEN_10 ? rom_64 : GEN_11 ? rom_63 : GEN_12 ? rom_62 : GEN_13 ? rom_61 : GEN_14 ? rom_60 : GEN_15 ? rom_59 : GEN_16 ? rom_58 : GEN_17 ? rom_57 : GEN_18 ? rom_56 : GEN_19 ? rom_55 : GEN_20 ? rom_54 : GEN_21 ? rom_53 : GEN_22 ? rom_52 : GEN_23 ? rom_51 : GEN_24 ? rom_50 : GEN_25 ? rom_49 : GEN_26 ? rom_48 : GEN_27 ? rom_47 : GEN_28 ? rom_46 : GEN_29 ? rom_45 : GEN_30 ? rom_44 : GEN_31 ? rom_43 : GEN_32 ? rom_42 : GEN_33 ? rom_41 : GEN_34 ? rom_40 : GEN_35 ? rom_39 : GEN_36 ? rom_38 : GEN_37 ? rom_37 : GEN_38 ? rom_36 : GEN_39 ? rom_35 : GEN_40 ? rom_34 : GEN_41 ? rom_33 : GEN_42 ? rom_32 : GEN_43 ? rom_31 : GEN_44 ? rom_30 : GEN_45 ? rom_29 : GEN_46 ? rom_28 : GEN_47 ? rom_27 : GEN_48 ? rom_26 : GEN_49 ? rom_25 : GEN_50 ? rom_24 : GEN_51 ? rom_23 : GEN_52 ? rom_22 : GEN_53 ? rom_21 : GEN_54 ? rom_20 : GEN_55 ? rom_19 : GEN_56 ? rom_18 : GEN_57 ? rom_17 : GEN_58 ? rom_16 : GEN_59 ? rom_15 : GEN_60 ? rom_14 : GEN_61 ? rom_13 : GEN_62 ? rom_12 : GEN_63 ? rom_11 : GEN_64 ? rom_10 : GEN_65 ? rom_9 : GEN_66 ? rom_8 : GEN_67 ? rom_7 : GEN_68 ? rom_6 : GEN_69 ? rom_5 : GEN_70 ? rom_4 : GEN_71 ? rom_3 : GEN_72 ? rom_2 : GEN_73 ? rom_1 : rom_0; + assign GEN_0 = GEN_10 ? rom_66 : GEN_11 ? rom_65 : GEN_12 ? rom_64 : GEN_13 ? rom_63 : GEN_14 ? rom_62 : GEN_15 ? rom_61 : GEN_16 ? rom_60 : GEN_17 ? rom_59 : GEN_18 ? rom_58 : GEN_19 ? rom_57 : GEN_20 ? rom_56 : GEN_21 ? rom_55 : GEN_22 ? rom_54 : GEN_23 ? rom_53 : GEN_24 ? rom_52 : GEN_25 ? rom_51 : GEN_26 ? rom_50 : GEN_27 ? rom_49 : GEN_28 ? rom_48 : GEN_29 ? rom_47 : GEN_30 ? rom_46 : GEN_31 ? rom_45 : GEN_32 ? rom_44 : GEN_33 ? rom_43 : GEN_34 ? rom_42 : GEN_35 ? rom_41 : GEN_36 ? rom_40 : GEN_37 ? rom_39 : GEN_38 ? rom_38 : GEN_39 ? rom_37 : GEN_40 ? rom_36 : GEN_41 ? rom_35 : GEN_42 ? rom_34 : GEN_43 ? rom_33 : GEN_44 ? rom_32 : GEN_45 ? rom_31 : GEN_46 ? rom_30 : GEN_47 ? rom_29 : GEN_48 ? rom_28 : GEN_49 ? rom_27 : GEN_50 ? rom_26 : GEN_51 ? rom_25 : GEN_52 ? rom_24 : GEN_53 ? rom_23 : GEN_54 ? rom_22 : GEN_55 ? rom_21 : GEN_56 ? rom_20 : GEN_57 ? rom_19 : GEN_58 ? rom_18 : GEN_59 ? rom_17 : GEN_60 ? rom_16 : GEN_61 ? rom_15 : GEN_62 ? rom_14 : GEN_63 ? rom_13 : GEN_64 ? rom_12 : GEN_65 ? rom_11 : GEN_66 ? rom_10 : GEN_67 ? rom_9 : GEN_68 ? rom_8 : GEN_69 ? rom_7 : GEN_70 ? rom_6 : GEN_71 ? rom_5 : GEN_72 ? rom_4 : GEN_73 ? rom_3 : GEN_74 ? rom_2 : GEN_75 ? rom_1 : rom_0; assign T_502 = GEN_0[63:32]; - assign GEN_1 = GEN_74 ? rom_66 : GEN_75 ? rom_65 : GEN_76 ? rom_64 : GEN_77 ? rom_63 : GEN_78 ? rom_62 : GEN_79 ? rom_61 : GEN_80 ? rom_60 : GEN_81 ? rom_59 : GEN_82 ? rom_58 : GEN_83 ? rom_57 : GEN_84 ? rom_56 : GEN_85 ? rom_55 : GEN_86 ? rom_54 : GEN_87 ? rom_53 : GEN_88 ? rom_52 : GEN_89 ? rom_51 : GEN_90 ? rom_50 : GEN_91 ? rom_49 : GEN_92 ? rom_48 : GEN_93 ? rom_47 : GEN_94 ? rom_46 : GEN_95 ? rom_45 : GEN_96 ? rom_44 : GEN_97 ? rom_43 : GEN_98 ? rom_42 : GEN_99 ? rom_41 : GEN_100 ? rom_40 : GEN_101 ? rom_39 : GEN_102 ? rom_38 : GEN_103 ? rom_37 : GEN_104 ? rom_36 : GEN_105 ? rom_35 : GEN_106 ? rom_34 : GEN_107 ? rom_33 : GEN_108 ? rom_32 : GEN_109 ? rom_31 : GEN_110 ? rom_30 : GEN_111 ? rom_29 : GEN_112 ? rom_28 : GEN_113 ? rom_27 : GEN_114 ? rom_26 : GEN_115 ? rom_25 : GEN_116 ? rom_24 : GEN_117 ? rom_23 : GEN_118 ? rom_22 : GEN_119 ? rom_21 : GEN_120 ? rom_20 : GEN_121 ? rom_19 : GEN_122 ? rom_18 : GEN_123 ? rom_17 : GEN_124 ? rom_16 : GEN_125 ? rom_15 : GEN_126 ? rom_14 : GEN_127 ? rom_13 : GEN_128 ? rom_12 : GEN_129 ? rom_11 : GEN_130 ? rom_10 : GEN_131 ? rom_9 : GEN_132 ? rom_8 : GEN_133 ? rom_7 : GEN_134 ? rom_6 : GEN_135 ? rom_5 : GEN_136 ? rom_4 : GEN_137 ? rom_3 : GEN_138 ? rom_2 : GEN_139 ? rom_1 : rom_0; + assign GEN_1 = GEN_76 ? rom_66 : GEN_77 ? rom_65 : GEN_78 ? rom_64 : GEN_79 ? rom_63 : GEN_80 ? rom_62 : GEN_81 ? rom_61 : GEN_82 ? rom_60 : GEN_83 ? rom_59 : GEN_84 ? rom_58 : GEN_85 ? rom_57 : GEN_86 ? rom_56 : GEN_87 ? rom_55 : GEN_88 ? rom_54 : GEN_89 ? rom_53 : GEN_90 ? rom_52 : GEN_91 ? rom_51 : GEN_92 ? rom_50 : GEN_93 ? rom_49 : GEN_94 ? rom_48 : GEN_95 ? rom_47 : GEN_96 ? rom_46 : GEN_97 ? rom_45 : GEN_98 ? rom_44 : GEN_99 ? rom_43 : GEN_100 ? rom_42 : GEN_101 ? rom_41 : GEN_102 ? rom_40 : GEN_103 ? rom_39 : GEN_104 ? rom_38 : GEN_105 ? rom_37 : GEN_106 ? rom_36 : GEN_107 ? rom_35 : GEN_108 ? rom_34 : GEN_109 ? rom_33 : GEN_110 ? rom_32 : GEN_111 ? rom_31 : GEN_112 ? rom_30 : GEN_113 ? rom_29 : GEN_114 ? rom_28 : GEN_115 ? rom_27 : GEN_116 ? rom_26 : GEN_117 ? rom_25 : GEN_118 ? rom_24 : GEN_119 ? rom_23 : GEN_120 ? rom_22 : GEN_121 ? rom_21 : GEN_122 ? rom_20 : GEN_123 ? rom_19 : GEN_124 ? rom_18 : GEN_125 ? rom_17 : GEN_126 ? rom_16 : GEN_127 ? rom_15 : GEN_128 ? rom_14 : GEN_129 ? rom_13 : GEN_130 ? rom_12 : GEN_131 ? rom_11 : GEN_132 ? rom_10 : GEN_133 ? rom_9 : GEN_134 ? rom_8 : GEN_135 ? rom_7 : GEN_136 ? rom_6 : GEN_137 ? rom_5 : GEN_138 ? rom_4 : GEN_139 ? rom_3 : GEN_140 ? rom_2 : GEN_141 ? rom_1 : rom_0; assign T_503 = GEN_1[31:0]; assign T_504 = T_501 ? T_502 : T_503; assign T_506 = 1'h0 & 1'h0; @@ -92153,7 +92245,7 @@ module NastiROM( assign T_513 = T_500 & T_512; assign T_515 = 32'h0 - T_513; assign T_516 = T_515[31:0]; - assign GEN_2 = GEN_140 ? rom_66 : GEN_141 ? rom_65 : GEN_142 ? rom_64 : GEN_143 ? rom_63 : GEN_144 ? rom_62 : GEN_145 ? rom_61 : GEN_146 ? rom_60 : GEN_147 ? rom_59 : GEN_148 ? rom_58 : GEN_149 ? rom_57 : GEN_150 ? rom_56 : GEN_151 ? rom_55 : GEN_152 ? rom_54 : GEN_153 ? rom_53 : GEN_154 ? rom_52 : GEN_155 ? rom_51 : GEN_156 ? rom_50 : GEN_157 ? rom_49 : GEN_158 ? rom_48 : GEN_159 ? rom_47 : GEN_160 ? rom_46 : GEN_161 ? rom_45 : GEN_162 ? rom_44 : GEN_163 ? rom_43 : GEN_164 ? rom_42 : GEN_165 ? rom_41 : GEN_166 ? rom_40 : GEN_167 ? rom_39 : GEN_168 ? rom_38 : GEN_169 ? rom_37 : GEN_170 ? rom_36 : GEN_171 ? rom_35 : GEN_172 ? rom_34 : GEN_173 ? rom_33 : GEN_174 ? rom_32 : GEN_175 ? rom_31 : GEN_176 ? rom_30 : GEN_177 ? rom_29 : GEN_178 ? rom_28 : GEN_179 ? rom_27 : GEN_180 ? rom_26 : GEN_181 ? rom_25 : GEN_182 ? rom_24 : GEN_183 ? rom_23 : GEN_184 ? rom_22 : GEN_185 ? rom_21 : GEN_186 ? rom_20 : GEN_187 ? rom_19 : GEN_188 ? rom_18 : GEN_189 ? rom_17 : GEN_190 ? rom_16 : GEN_191 ? rom_15 : GEN_192 ? rom_14 : GEN_193 ? rom_13 : GEN_194 ? rom_12 : GEN_195 ? rom_11 : GEN_196 ? rom_10 : GEN_197 ? rom_9 : GEN_198 ? rom_8 : GEN_199 ? rom_7 : GEN_200 ? rom_6 : GEN_201 ? rom_5 : GEN_202 ? rom_4 : GEN_203 ? rom_3 : GEN_204 ? rom_2 : GEN_205 ? rom_1 : rom_0; + assign GEN_2 = GEN_142 ? rom_66 : GEN_143 ? rom_65 : GEN_144 ? rom_64 : GEN_145 ? rom_63 : GEN_146 ? rom_62 : GEN_147 ? rom_61 : GEN_148 ? rom_60 : GEN_149 ? rom_59 : GEN_150 ? rom_58 : GEN_151 ? rom_57 : GEN_152 ? rom_56 : GEN_153 ? rom_55 : GEN_154 ? rom_54 : GEN_155 ? rom_53 : GEN_156 ? rom_52 : GEN_157 ? rom_51 : GEN_158 ? rom_50 : GEN_159 ? rom_49 : GEN_160 ? rom_48 : GEN_161 ? rom_47 : GEN_162 ? rom_46 : GEN_163 ? rom_45 : GEN_164 ? rom_44 : GEN_165 ? rom_43 : GEN_166 ? rom_42 : GEN_167 ? rom_41 : GEN_168 ? rom_40 : GEN_169 ? rom_39 : GEN_170 ? rom_38 : GEN_171 ? rom_37 : GEN_172 ? rom_36 : GEN_173 ? rom_35 : GEN_174 ? rom_34 : GEN_175 ? rom_33 : GEN_176 ? rom_32 : GEN_177 ? rom_31 : GEN_178 ? rom_30 : GEN_179 ? rom_29 : GEN_180 ? rom_28 : GEN_181 ? rom_27 : GEN_182 ? rom_26 : GEN_183 ? rom_25 : GEN_184 ? rom_24 : GEN_185 ? rom_23 : GEN_186 ? rom_22 : GEN_187 ? rom_21 : GEN_188 ? rom_20 : GEN_189 ? rom_19 : GEN_190 ? rom_18 : GEN_191 ? rom_17 : GEN_192 ? rom_16 : GEN_193 ? rom_15 : GEN_194 ? rom_14 : GEN_195 ? rom_13 : GEN_196 ? rom_12 : GEN_197 ? rom_11 : GEN_198 ? rom_10 : GEN_199 ? rom_9 : GEN_200 ? rom_8 : GEN_201 ? rom_7 : GEN_202 ? rom_6 : GEN_203 ? rom_5 : GEN_204 ? rom_4 : GEN_205 ? rom_3 : GEN_206 ? rom_2 : GEN_207 ? rom_1 : rom_0; assign T_517 = GEN_2[63:32]; assign T_518 = T_511 ? T_516 : T_517; assign T_519 = {T_518,T_508}; @@ -92194,228 +92286,230 @@ module NastiROM( assign T_566_user = 1'h0; assign GEN_4 = T_334_io_deq_valid & T_338; assign GEN_5 = GEN_4 & T_340; - assign GEN_6 = T_334_io_deq_valid & T_338; - assign GEN_7 = T_347 & T_349; - assign GEN_8 = 7'h42 == T_492; - assign GEN_9 = 7'h41 == T_492; - assign GEN_10 = 7'h40 == T_492; - assign GEN_11 = 6'h3f == T_492; - assign GEN_12 = 6'h3e == T_492; - assign GEN_13 = 6'h3d == T_492; - assign GEN_14 = 6'h3c == T_492; - assign GEN_15 = 6'h3b == T_492; - assign GEN_16 = 6'h3a == T_492; - assign GEN_17 = 6'h39 == T_492; - assign GEN_18 = 6'h38 == T_492; - assign GEN_19 = 6'h37 == T_492; - assign GEN_20 = 6'h36 == T_492; - assign GEN_21 = 6'h35 == T_492; - assign GEN_22 = 6'h34 == T_492; - assign GEN_23 = 6'h33 == T_492; - assign GEN_24 = 6'h32 == T_492; - assign GEN_25 = 6'h31 == T_492; - assign GEN_26 = 6'h30 == T_492; - assign GEN_27 = 6'h2f == T_492; - assign GEN_28 = 6'h2e == T_492; - assign GEN_29 = 6'h2d == T_492; - assign GEN_30 = 6'h2c == T_492; - assign GEN_31 = 6'h2b == T_492; - assign GEN_32 = 6'h2a == T_492; - assign GEN_33 = 6'h29 == T_492; - assign GEN_34 = 6'h28 == T_492; - assign GEN_35 = 6'h27 == T_492; - assign GEN_36 = 6'h26 == T_492; - assign GEN_37 = 6'h25 == T_492; - assign GEN_38 = 6'h24 == T_492; - assign GEN_39 = 6'h23 == T_492; - assign GEN_40 = 6'h22 == T_492; - assign GEN_41 = 6'h21 == T_492; - assign GEN_42 = 6'h20 == T_492; - assign GEN_43 = 5'h1f == T_492; - assign GEN_44 = 5'h1e == T_492; - assign GEN_45 = 5'h1d == T_492; - assign GEN_46 = 5'h1c == T_492; - assign GEN_47 = 5'h1b == T_492; - assign GEN_48 = 5'h1a == T_492; - assign GEN_49 = 5'h19 == T_492; - assign GEN_50 = 5'h18 == T_492; - assign GEN_51 = 5'h17 == T_492; - assign GEN_52 = 5'h16 == T_492; - assign GEN_53 = 5'h15 == T_492; - assign GEN_54 = 5'h14 == T_492; - assign GEN_55 = 5'h13 == T_492; - assign GEN_56 = 5'h12 == T_492; - assign GEN_57 = 5'h11 == T_492; - assign GEN_58 = 5'h10 == T_492; - assign GEN_59 = 4'hf == T_492; - assign GEN_60 = 4'he == T_492; - assign GEN_61 = 4'hd == T_492; - assign GEN_62 = 4'hc == T_492; - assign GEN_63 = 4'hb == T_492; - assign GEN_64 = 4'ha == T_492; - assign GEN_65 = 4'h9 == T_492; - assign GEN_66 = 4'h8 == T_492; - assign GEN_67 = 3'h7 == T_492; - assign GEN_68 = 3'h6 == T_492; - assign GEN_69 = 3'h5 == T_492; - assign GEN_70 = 3'h4 == T_492; - assign GEN_71 = 2'h3 == T_492; - assign GEN_72 = 2'h2 == T_492; - assign GEN_73 = 1'h1 == T_492; - assign GEN_74 = 7'h42 == T_492; - assign GEN_75 = 7'h41 == T_492; - assign GEN_76 = 7'h40 == T_492; - assign GEN_77 = 6'h3f == T_492; - assign GEN_78 = 6'h3e == T_492; - assign GEN_79 = 6'h3d == T_492; - assign GEN_80 = 6'h3c == T_492; - assign GEN_81 = 6'h3b == T_492; - assign GEN_82 = 6'h3a == T_492; - assign GEN_83 = 6'h39 == T_492; - assign GEN_84 = 6'h38 == T_492; - assign GEN_85 = 6'h37 == T_492; - assign GEN_86 = 6'h36 == T_492; - assign GEN_87 = 6'h35 == T_492; - assign GEN_88 = 6'h34 == T_492; - assign GEN_89 = 6'h33 == T_492; - assign GEN_90 = 6'h32 == T_492; - assign GEN_91 = 6'h31 == T_492; - assign GEN_92 = 6'h30 == T_492; - assign GEN_93 = 6'h2f == T_492; - assign GEN_94 = 6'h2e == T_492; - assign GEN_95 = 6'h2d == T_492; - assign GEN_96 = 6'h2c == T_492; - assign GEN_97 = 6'h2b == T_492; - assign GEN_98 = 6'h2a == T_492; - assign GEN_99 = 6'h29 == T_492; - assign GEN_100 = 6'h28 == T_492; - assign GEN_101 = 6'h27 == T_492; - assign GEN_102 = 6'h26 == T_492; - assign GEN_103 = 6'h25 == T_492; - assign GEN_104 = 6'h24 == T_492; - assign GEN_105 = 6'h23 == T_492; - assign GEN_106 = 6'h22 == T_492; - assign GEN_107 = 6'h21 == T_492; - assign GEN_108 = 6'h20 == T_492; - assign GEN_109 = 5'h1f == T_492; - assign GEN_110 = 5'h1e == T_492; - assign GEN_111 = 5'h1d == T_492; - assign GEN_112 = 5'h1c == T_492; - assign GEN_113 = 5'h1b == T_492; - assign GEN_114 = 5'h1a == T_492; - assign GEN_115 = 5'h19 == T_492; - assign GEN_116 = 5'h18 == T_492; - assign GEN_117 = 5'h17 == T_492; - assign GEN_118 = 5'h16 == T_492; - assign GEN_119 = 5'h15 == T_492; - assign GEN_120 = 5'h14 == T_492; - assign GEN_121 = 5'h13 == T_492; - assign GEN_122 = 5'h12 == T_492; - assign GEN_123 = 5'h11 == T_492; - assign GEN_124 = 5'h10 == T_492; - assign GEN_125 = 4'hf == T_492; - assign GEN_126 = 4'he == T_492; - assign GEN_127 = 4'hd == T_492; - assign GEN_128 = 4'hc == T_492; - assign GEN_129 = 4'hb == T_492; - assign GEN_130 = 4'ha == T_492; - assign GEN_131 = 4'h9 == T_492; - assign GEN_132 = 4'h8 == T_492; - assign GEN_133 = 3'h7 == T_492; - assign GEN_134 = 3'h6 == T_492; - assign GEN_135 = 3'h5 == T_492; - assign GEN_136 = 3'h4 == T_492; - assign GEN_137 = 2'h3 == T_492; - assign GEN_138 = 2'h2 == T_492; - assign GEN_139 = 1'h1 == T_492; - assign GEN_140 = 7'h42 == T_492; - assign GEN_141 = 7'h41 == T_492; - assign GEN_142 = 7'h40 == T_492; - assign GEN_143 = 6'h3f == T_492; - assign GEN_144 = 6'h3e == T_492; - assign GEN_145 = 6'h3d == T_492; - assign GEN_146 = 6'h3c == T_492; - assign GEN_147 = 6'h3b == T_492; - assign GEN_148 = 6'h3a == T_492; - assign GEN_149 = 6'h39 == T_492; - assign GEN_150 = 6'h38 == T_492; - assign GEN_151 = 6'h37 == T_492; - assign GEN_152 = 6'h36 == T_492; - assign GEN_153 = 6'h35 == T_492; - assign GEN_154 = 6'h34 == T_492; - assign GEN_155 = 6'h33 == T_492; - assign GEN_156 = 6'h32 == T_492; - assign GEN_157 = 6'h31 == T_492; - assign GEN_158 = 6'h30 == T_492; - assign GEN_159 = 6'h2f == T_492; - assign GEN_160 = 6'h2e == T_492; - assign GEN_161 = 6'h2d == T_492; - assign GEN_162 = 6'h2c == T_492; - assign GEN_163 = 6'h2b == T_492; - assign GEN_164 = 6'h2a == T_492; - assign GEN_165 = 6'h29 == T_492; - assign GEN_166 = 6'h28 == T_492; - assign GEN_167 = 6'h27 == T_492; - assign GEN_168 = 6'h26 == T_492; - assign GEN_169 = 6'h25 == T_492; - assign GEN_170 = 6'h24 == T_492; - assign GEN_171 = 6'h23 == T_492; - assign GEN_172 = 6'h22 == T_492; - assign GEN_173 = 6'h21 == T_492; - assign GEN_174 = 6'h20 == T_492; - assign GEN_175 = 5'h1f == T_492; - assign GEN_176 = 5'h1e == T_492; - assign GEN_177 = 5'h1d == T_492; - assign GEN_178 = 5'h1c == T_492; - assign GEN_179 = 5'h1b == T_492; - assign GEN_180 = 5'h1a == T_492; - assign GEN_181 = 5'h19 == T_492; - assign GEN_182 = 5'h18 == T_492; - assign GEN_183 = 5'h17 == T_492; - assign GEN_184 = 5'h16 == T_492; - assign GEN_185 = 5'h15 == T_492; - assign GEN_186 = 5'h14 == T_492; - assign GEN_187 = 5'h13 == T_492; - assign GEN_188 = 5'h12 == T_492; - assign GEN_189 = 5'h11 == T_492; - assign GEN_190 = 5'h10 == T_492; - assign GEN_191 = 4'hf == T_492; - assign GEN_192 = 4'he == T_492; - assign GEN_193 = 4'hd == T_492; - assign GEN_194 = 4'hc == T_492; - assign GEN_195 = 4'hb == T_492; - assign GEN_196 = 4'ha == T_492; - assign GEN_197 = 4'h9 == T_492; - assign GEN_198 = 4'h8 == T_492; - assign GEN_199 = 3'h7 == T_492; - assign GEN_200 = 3'h6 == T_492; - assign GEN_201 = 3'h5 == T_492; - assign GEN_202 = 3'h4 == T_492; - assign GEN_203 = 2'h3 == T_492; - assign GEN_204 = 2'h2 == T_492; - assign GEN_205 = 1'h1 == T_492; + assign GEN_6 = GEN_5 & T_342; + assign GEN_7 = T_334_io_deq_valid & T_338; + assign GEN_8 = T_347 & T_349; + assign GEN_9 = GEN_8 & T_351; + assign GEN_10 = 7'h42 == T_492; + assign GEN_11 = 7'h41 == T_492; + assign GEN_12 = 7'h40 == T_492; + assign GEN_13 = 6'h3f == T_492; + assign GEN_14 = 6'h3e == T_492; + assign GEN_15 = 6'h3d == T_492; + assign GEN_16 = 6'h3c == T_492; + assign GEN_17 = 6'h3b == T_492; + assign GEN_18 = 6'h3a == T_492; + assign GEN_19 = 6'h39 == T_492; + assign GEN_20 = 6'h38 == T_492; + assign GEN_21 = 6'h37 == T_492; + assign GEN_22 = 6'h36 == T_492; + assign GEN_23 = 6'h35 == T_492; + assign GEN_24 = 6'h34 == T_492; + assign GEN_25 = 6'h33 == T_492; + assign GEN_26 = 6'h32 == T_492; + assign GEN_27 = 6'h31 == T_492; + assign GEN_28 = 6'h30 == T_492; + assign GEN_29 = 6'h2f == T_492; + assign GEN_30 = 6'h2e == T_492; + assign GEN_31 = 6'h2d == T_492; + assign GEN_32 = 6'h2c == T_492; + assign GEN_33 = 6'h2b == T_492; + assign GEN_34 = 6'h2a == T_492; + assign GEN_35 = 6'h29 == T_492; + assign GEN_36 = 6'h28 == T_492; + assign GEN_37 = 6'h27 == T_492; + assign GEN_38 = 6'h26 == T_492; + assign GEN_39 = 6'h25 == T_492; + assign GEN_40 = 6'h24 == T_492; + assign GEN_41 = 6'h23 == T_492; + assign GEN_42 = 6'h22 == T_492; + assign GEN_43 = 6'h21 == T_492; + assign GEN_44 = 6'h20 == T_492; + assign GEN_45 = 5'h1f == T_492; + assign GEN_46 = 5'h1e == T_492; + assign GEN_47 = 5'h1d == T_492; + assign GEN_48 = 5'h1c == T_492; + assign GEN_49 = 5'h1b == T_492; + assign GEN_50 = 5'h1a == T_492; + assign GEN_51 = 5'h19 == T_492; + assign GEN_52 = 5'h18 == T_492; + assign GEN_53 = 5'h17 == T_492; + assign GEN_54 = 5'h16 == T_492; + assign GEN_55 = 5'h15 == T_492; + assign GEN_56 = 5'h14 == T_492; + assign GEN_57 = 5'h13 == T_492; + assign GEN_58 = 5'h12 == T_492; + assign GEN_59 = 5'h11 == T_492; + assign GEN_60 = 5'h10 == T_492; + assign GEN_61 = 4'hf == T_492; + assign GEN_62 = 4'he == T_492; + assign GEN_63 = 4'hd == T_492; + assign GEN_64 = 4'hc == T_492; + assign GEN_65 = 4'hb == T_492; + assign GEN_66 = 4'ha == T_492; + assign GEN_67 = 4'h9 == T_492; + assign GEN_68 = 4'h8 == T_492; + assign GEN_69 = 3'h7 == T_492; + assign GEN_70 = 3'h6 == T_492; + assign GEN_71 = 3'h5 == T_492; + assign GEN_72 = 3'h4 == T_492; + assign GEN_73 = 2'h3 == T_492; + assign GEN_74 = 2'h2 == T_492; + assign GEN_75 = 1'h1 == T_492; + assign GEN_76 = 7'h42 == T_492; + assign GEN_77 = 7'h41 == T_492; + assign GEN_78 = 7'h40 == T_492; + assign GEN_79 = 6'h3f == T_492; + assign GEN_80 = 6'h3e == T_492; + assign GEN_81 = 6'h3d == T_492; + assign GEN_82 = 6'h3c == T_492; + assign GEN_83 = 6'h3b == T_492; + assign GEN_84 = 6'h3a == T_492; + assign GEN_85 = 6'h39 == T_492; + assign GEN_86 = 6'h38 == T_492; + assign GEN_87 = 6'h37 == T_492; + assign GEN_88 = 6'h36 == T_492; + assign GEN_89 = 6'h35 == T_492; + assign GEN_90 = 6'h34 == T_492; + assign GEN_91 = 6'h33 == T_492; + assign GEN_92 = 6'h32 == T_492; + assign GEN_93 = 6'h31 == T_492; + assign GEN_94 = 6'h30 == T_492; + assign GEN_95 = 6'h2f == T_492; + assign GEN_96 = 6'h2e == T_492; + assign GEN_97 = 6'h2d == T_492; + assign GEN_98 = 6'h2c == T_492; + assign GEN_99 = 6'h2b == T_492; + assign GEN_100 = 6'h2a == T_492; + assign GEN_101 = 6'h29 == T_492; + assign GEN_102 = 6'h28 == T_492; + assign GEN_103 = 6'h27 == T_492; + assign GEN_104 = 6'h26 == T_492; + assign GEN_105 = 6'h25 == T_492; + assign GEN_106 = 6'h24 == T_492; + assign GEN_107 = 6'h23 == T_492; + assign GEN_108 = 6'h22 == T_492; + assign GEN_109 = 6'h21 == T_492; + assign GEN_110 = 6'h20 == T_492; + assign GEN_111 = 5'h1f == T_492; + assign GEN_112 = 5'h1e == T_492; + assign GEN_113 = 5'h1d == T_492; + assign GEN_114 = 5'h1c == T_492; + assign GEN_115 = 5'h1b == T_492; + assign GEN_116 = 5'h1a == T_492; + assign GEN_117 = 5'h19 == T_492; + assign GEN_118 = 5'h18 == T_492; + assign GEN_119 = 5'h17 == T_492; + assign GEN_120 = 5'h16 == T_492; + assign GEN_121 = 5'h15 == T_492; + assign GEN_122 = 5'h14 == T_492; + assign GEN_123 = 5'h13 == T_492; + assign GEN_124 = 5'h12 == T_492; + assign GEN_125 = 5'h11 == T_492; + assign GEN_126 = 5'h10 == T_492; + assign GEN_127 = 4'hf == T_492; + assign GEN_128 = 4'he == T_492; + assign GEN_129 = 4'hd == T_492; + assign GEN_130 = 4'hc == T_492; + assign GEN_131 = 4'hb == T_492; + assign GEN_132 = 4'ha == T_492; + assign GEN_133 = 4'h9 == T_492; + assign GEN_134 = 4'h8 == T_492; + assign GEN_135 = 3'h7 == T_492; + assign GEN_136 = 3'h6 == T_492; + assign GEN_137 = 3'h5 == T_492; + assign GEN_138 = 3'h4 == T_492; + assign GEN_139 = 2'h3 == T_492; + assign GEN_140 = 2'h2 == T_492; + assign GEN_141 = 1'h1 == T_492; + assign GEN_142 = 7'h42 == T_492; + assign GEN_143 = 7'h41 == T_492; + assign GEN_144 = 7'h40 == T_492; + assign GEN_145 = 6'h3f == T_492; + assign GEN_146 = 6'h3e == T_492; + assign GEN_147 = 6'h3d == T_492; + assign GEN_148 = 6'h3c == T_492; + assign GEN_149 = 6'h3b == T_492; + assign GEN_150 = 6'h3a == T_492; + assign GEN_151 = 6'h39 == T_492; + assign GEN_152 = 6'h38 == T_492; + assign GEN_153 = 6'h37 == T_492; + assign GEN_154 = 6'h36 == T_492; + assign GEN_155 = 6'h35 == T_492; + assign GEN_156 = 6'h34 == T_492; + assign GEN_157 = 6'h33 == T_492; + assign GEN_158 = 6'h32 == T_492; + assign GEN_159 = 6'h31 == T_492; + assign GEN_160 = 6'h30 == T_492; + assign GEN_161 = 6'h2f == T_492; + assign GEN_162 = 6'h2e == T_492; + assign GEN_163 = 6'h2d == T_492; + assign GEN_164 = 6'h2c == T_492; + assign GEN_165 = 6'h2b == T_492; + assign GEN_166 = 6'h2a == T_492; + assign GEN_167 = 6'h29 == T_492; + assign GEN_168 = 6'h28 == T_492; + assign GEN_169 = 6'h27 == T_492; + assign GEN_170 = 6'h26 == T_492; + assign GEN_171 = 6'h25 == T_492; + assign GEN_172 = 6'h24 == T_492; + assign GEN_173 = 6'h23 == T_492; + assign GEN_174 = 6'h22 == T_492; + assign GEN_175 = 6'h21 == T_492; + assign GEN_176 = 6'h20 == T_492; + assign GEN_177 = 5'h1f == T_492; + assign GEN_178 = 5'h1e == T_492; + assign GEN_179 = 5'h1d == T_492; + assign GEN_180 = 5'h1c == T_492; + assign GEN_181 = 5'h1b == T_492; + assign GEN_182 = 5'h1a == T_492; + assign GEN_183 = 5'h19 == T_492; + assign GEN_184 = 5'h18 == T_492; + assign GEN_185 = 5'h17 == T_492; + assign GEN_186 = 5'h16 == T_492; + assign GEN_187 = 5'h15 == T_492; + assign GEN_188 = 5'h14 == T_492; + assign GEN_189 = 5'h13 == T_492; + assign GEN_190 = 5'h12 == T_492; + assign GEN_191 = 5'h11 == T_492; + assign GEN_192 = 5'h10 == T_492; + assign GEN_193 = 4'hf == T_492; + assign GEN_194 = 4'he == T_492; + assign GEN_195 = 4'hd == T_492; + assign GEN_196 = 4'hc == T_492; + assign GEN_197 = 4'hb == T_492; + assign GEN_198 = 4'ha == T_492; + assign GEN_199 = 4'h9 == T_492; + assign GEN_200 = 4'h8 == T_492; + assign GEN_201 = 3'h7 == T_492; + assign GEN_202 = 3'h6 == T_492; + assign GEN_203 = 3'h5 == T_492; + assign GEN_204 = 3'h4 == T_492; + assign GEN_205 = 2'h3 == T_492; + assign GEN_206 = 2'h2 == T_492; + assign GEN_207 = 1'h1 == T_492; `ifndef SYNTHESIS integer initvar; initial begin #0.002; - GEN_206 = {1{$random}}; - GEN_207 = {1{$random}}; GEN_208 = {1{$random}}; + GEN_209 = {1{$random}}; + GEN_210 = {1{$random}}; end `endif always @(posedge clk) begin `ifndef SYNTHESIS - if(GEN_5 & T_342) begin + if(GEN_6) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Can't burst-read from NastiROM"); end `endif `ifndef SYNTHESIS - if(GEN_6 & T_340) begin + if(GEN_7 & T_340) begin $fdisplay(32'h80000002,"1");$finish; end `endif `ifndef SYNTHESIS - if(GEN_7 & T_351) begin + if(GEN_9) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): Can't write to NastiROM"); end `endif @@ -95755,33 +95849,33 @@ module CSRFile( wire [63:0] T_6083; wire [63:0] T_6084; wire GEN_1; - reg GEN_2; - reg [6:0] GEN_3; - reg [4:0] GEN_4; + wire GEN_2; + reg GEN_3; + reg [6:0] GEN_4; reg [4:0] GEN_5; - reg GEN_6; + reg [4:0] GEN_6; reg GEN_7; reg GEN_8; - reg [4:0] GEN_9; - reg [6:0] GEN_10; - reg [63:0] GEN_11; + reg GEN_9; + reg [4:0] GEN_10; + reg [6:0] GEN_11; reg [63:0] GEN_12; - reg GEN_13; + reg [63:0] GEN_13; reg GEN_14; reg GEN_15; - reg [39:0] GEN_16; - reg [8:0] GEN_17; - reg [4:0] GEN_18; - reg [2:0] GEN_19; - reg [63:0] GEN_20; - reg GEN_21; + reg GEN_16; + reg [39:0] GEN_17; + reg [8:0] GEN_18; + reg [4:0] GEN_19; + reg [2:0] GEN_20; + reg [63:0] GEN_21; reg GEN_22; reg GEN_23; - reg [63:0] GEN_24; + reg GEN_24; reg [63:0] GEN_25; - reg GEN_26; - reg [8:0] GEN_27; - reg GEN_28; + reg [63:0] GEN_26; + reg GEN_27; + reg [8:0] GEN_28; reg GEN_29; reg GEN_30; reg GEN_31; @@ -95789,99 +95883,100 @@ module CSRFile( reg GEN_33; reg GEN_34; reg GEN_35; - reg [1:0] GEN_36; + reg GEN_36; reg [1:0] GEN_37; - reg [3:0] GEN_38; - reg GEN_39; - reg [3:0] GEN_40; - reg [127:0] GEN_41; - reg GEN_42; + reg [1:0] GEN_38; + reg [3:0] GEN_39; + reg GEN_40; + reg [3:0] GEN_41; + reg [127:0] GEN_42; reg GEN_43; reg GEN_44; - reg [19:0] GEN_45; - reg [2:0] GEN_46; - reg GEN_47; + reg GEN_45; + reg [19:0] GEN_46; + reg [2:0] GEN_47; reg GEN_48; - reg [3:0] GEN_49; - reg GEN_50; + reg GEN_49; + reg [3:0] GEN_50; reg GEN_51; - reg [30:0] GEN_52; - reg GEN_53; - reg [8:0] GEN_54; - reg [4:0] GEN_55; - reg GEN_56; - reg [1:0] GEN_57; + reg GEN_52; + reg [30:0] GEN_53; + reg GEN_54; + reg [8:0] GEN_55; + reg [4:0] GEN_56; + reg GEN_57; reg [1:0] GEN_58; reg [1:0] GEN_59; - reg GEN_60; - reg [1:0] GEN_61; - reg GEN_62; - reg [1:0] GEN_63; - reg GEN_64; - reg [1:0] GEN_65; - reg GEN_66; + reg [1:0] GEN_60; + reg GEN_61; + reg [1:0] GEN_62; + reg GEN_63; + reg [1:0] GEN_64; + reg GEN_65; + reg [1:0] GEN_66; reg GEN_67; reg GEN_68; reg GEN_69; reg GEN_70; - reg [19:0] GEN_71; - reg [2:0] GEN_72; - reg GEN_73; + reg GEN_71; + reg [19:0] GEN_72; + reg [2:0] GEN_73; reg GEN_74; - reg [3:0] GEN_75; - reg GEN_76; + reg GEN_75; + reg [3:0] GEN_76; reg GEN_77; - reg [30:0] GEN_78; - reg GEN_79; - reg [8:0] GEN_80; - reg [4:0] GEN_81; - reg GEN_82; - reg [1:0] GEN_83; + reg GEN_78; + reg [30:0] GEN_79; + reg GEN_80; + reg [8:0] GEN_81; + reg [4:0] GEN_82; + reg GEN_83; reg [1:0] GEN_84; reg [1:0] GEN_85; - reg GEN_86; - reg [1:0] GEN_87; - reg GEN_88; - reg [1:0] GEN_89; - reg GEN_90; - reg [1:0] GEN_91; - reg GEN_92; + reg [1:0] GEN_86; + reg GEN_87; + reg [1:0] GEN_88; + reg GEN_89; + reg [1:0] GEN_90; + reg GEN_91; + reg [1:0] GEN_92; reg GEN_93; reg GEN_94; reg GEN_95; reg GEN_96; - reg [19:0] GEN_97; - reg [2:0] GEN_98; - reg GEN_99; + reg GEN_97; + reg [19:0] GEN_98; + reg [2:0] GEN_99; reg GEN_100; - reg [3:0] GEN_101; - reg GEN_102; + reg GEN_101; + reg [3:0] GEN_102; reg GEN_103; - reg [30:0] GEN_104; - reg GEN_105; - reg [8:0] GEN_106; - reg [4:0] GEN_107; - reg GEN_108; - reg [1:0] GEN_109; + reg GEN_104; + reg [30:0] GEN_105; + reg GEN_106; + reg [8:0] GEN_107; + reg [4:0] GEN_108; + reg GEN_109; reg [1:0] GEN_110; reg [1:0] GEN_111; - reg GEN_112; - reg [1:0] GEN_113; - reg GEN_114; - reg [1:0] GEN_115; - reg GEN_116; - reg [1:0] GEN_117; - reg GEN_118; + reg [1:0] GEN_112; + reg GEN_113; + reg [1:0] GEN_114; + reg GEN_115; + reg [1:0] GEN_116; + reg GEN_117; + reg [1:0] GEN_118; reg GEN_119; reg GEN_120; reg GEN_121; - reg [64:0] GEN_122; - reg [4:0] GEN_123; - reg GEN_124; + reg GEN_122; + reg [64:0] GEN_123; + reg [4:0] GEN_124; reg GEN_125; reg GEN_126; - reg [1:0] GEN_127; + reg GEN_127; reg [1:0] GEN_128; + reg [1:0] GEN_129; assign io_host_csr_req_ready = T_4968; assign io_host_csr_resp_valid = host_csr_rep_valid; assign io_host_csr_resp_bits = host_csr_bits_data; @@ -95911,133 +96006,133 @@ module CSRFile( assign io_fatc = insn_sfence_vm; assign io_time = T_4615; assign io_fcsr_rm = reg_frm; - assign io_rocc_cmd_valid = GEN_2; - assign io_rocc_cmd_bits_inst_funct = GEN_3; - assign io_rocc_cmd_bits_inst_rs2 = GEN_4; - assign io_rocc_cmd_bits_inst_rs1 = GEN_5; - assign io_rocc_cmd_bits_inst_xd = GEN_6; - assign io_rocc_cmd_bits_inst_xs1 = GEN_7; - assign io_rocc_cmd_bits_inst_xs2 = GEN_8; - assign io_rocc_cmd_bits_inst_rd = GEN_9; - assign io_rocc_cmd_bits_inst_opcode = GEN_10; - assign io_rocc_cmd_bits_rs1 = GEN_11; - assign io_rocc_cmd_bits_rs2 = GEN_12; - assign io_rocc_resp_ready = GEN_13; - assign io_rocc_mem_req_ready = GEN_14; - assign io_rocc_mem_resp_valid = GEN_15; - assign io_rocc_mem_resp_bits_addr = GEN_16; - assign io_rocc_mem_resp_bits_tag = GEN_17; - assign io_rocc_mem_resp_bits_cmd = GEN_18; - assign io_rocc_mem_resp_bits_typ = GEN_19; - assign io_rocc_mem_resp_bits_data = GEN_20; - assign io_rocc_mem_resp_bits_nack = GEN_21; - assign io_rocc_mem_resp_bits_replay = GEN_22; - assign io_rocc_mem_resp_bits_has_data = GEN_23; - assign io_rocc_mem_resp_bits_data_word_bypass = GEN_24; - assign io_rocc_mem_resp_bits_store_data = GEN_25; - assign io_rocc_mem_replay_next_valid = GEN_26; - assign io_rocc_mem_replay_next_bits = GEN_27; - assign io_rocc_mem_xcpt_ma_ld = GEN_28; - assign io_rocc_mem_xcpt_ma_st = GEN_29; - assign io_rocc_mem_xcpt_pf_ld = GEN_30; - assign io_rocc_mem_xcpt_pf_st = GEN_31; - assign io_rocc_mem_ordered = GEN_32; - assign io_rocc_s = GEN_33; - assign io_rocc_autl_acquire_ready = GEN_34; - assign io_rocc_autl_grant_valid = GEN_35; - assign io_rocc_autl_grant_bits_addr_beat = GEN_36; - assign io_rocc_autl_grant_bits_client_xact_id = GEN_37; - assign io_rocc_autl_grant_bits_manager_xact_id = GEN_38; - assign io_rocc_autl_grant_bits_is_builtin_type = GEN_39; - assign io_rocc_autl_grant_bits_g_type = GEN_40; - assign io_rocc_autl_grant_bits_data = GEN_41; - assign io_rocc_iptw_req_ready = GEN_42; - assign io_rocc_iptw_resp_valid = GEN_43; - assign io_rocc_iptw_resp_bits_error = GEN_44; - assign io_rocc_iptw_resp_bits_pte_ppn = GEN_45; - assign io_rocc_iptw_resp_bits_pte_reserved_for_software = GEN_46; - assign io_rocc_iptw_resp_bits_pte_d = GEN_47; - assign io_rocc_iptw_resp_bits_pte_r = GEN_48; - assign io_rocc_iptw_resp_bits_pte_typ = GEN_49; - assign io_rocc_iptw_resp_bits_pte_v = GEN_50; - assign io_rocc_iptw_status_sd = GEN_51; - assign io_rocc_iptw_status_zero2 = GEN_52; - assign io_rocc_iptw_status_sd_rv32 = GEN_53; - assign io_rocc_iptw_status_zero1 = GEN_54; - assign io_rocc_iptw_status_vm = GEN_55; - assign io_rocc_iptw_status_mprv = GEN_56; - assign io_rocc_iptw_status_xs = GEN_57; - assign io_rocc_iptw_status_fs = GEN_58; - assign io_rocc_iptw_status_prv3 = GEN_59; - assign io_rocc_iptw_status_ie3 = GEN_60; - assign io_rocc_iptw_status_prv2 = GEN_61; - assign io_rocc_iptw_status_ie2 = GEN_62; - assign io_rocc_iptw_status_prv1 = GEN_63; - assign io_rocc_iptw_status_ie1 = GEN_64; - assign io_rocc_iptw_status_prv = GEN_65; - assign io_rocc_iptw_status_ie = GEN_66; - assign io_rocc_iptw_invalidate = GEN_67; - assign io_rocc_dptw_req_ready = GEN_68; - assign io_rocc_dptw_resp_valid = GEN_69; - assign io_rocc_dptw_resp_bits_error = GEN_70; - assign io_rocc_dptw_resp_bits_pte_ppn = GEN_71; - assign io_rocc_dptw_resp_bits_pte_reserved_for_software = GEN_72; - assign io_rocc_dptw_resp_bits_pte_d = GEN_73; - assign io_rocc_dptw_resp_bits_pte_r = GEN_74; - assign io_rocc_dptw_resp_bits_pte_typ = GEN_75; - assign io_rocc_dptw_resp_bits_pte_v = GEN_76; - assign io_rocc_dptw_status_sd = GEN_77; - assign io_rocc_dptw_status_zero2 = GEN_78; - assign io_rocc_dptw_status_sd_rv32 = GEN_79; - assign io_rocc_dptw_status_zero1 = GEN_80; - assign io_rocc_dptw_status_vm = GEN_81; - assign io_rocc_dptw_status_mprv = GEN_82; - assign io_rocc_dptw_status_xs = GEN_83; - assign io_rocc_dptw_status_fs = GEN_84; - assign io_rocc_dptw_status_prv3 = GEN_85; - assign io_rocc_dptw_status_ie3 = GEN_86; - assign io_rocc_dptw_status_prv2 = GEN_87; - assign io_rocc_dptw_status_ie2 = GEN_88; - assign io_rocc_dptw_status_prv1 = GEN_89; - assign io_rocc_dptw_status_ie1 = GEN_90; - assign io_rocc_dptw_status_prv = GEN_91; - assign io_rocc_dptw_status_ie = GEN_92; - assign io_rocc_dptw_invalidate = GEN_93; - assign io_rocc_pptw_req_ready = GEN_94; - assign io_rocc_pptw_resp_valid = GEN_95; - assign io_rocc_pptw_resp_bits_error = GEN_96; - assign io_rocc_pptw_resp_bits_pte_ppn = GEN_97; - assign io_rocc_pptw_resp_bits_pte_reserved_for_software = GEN_98; - assign io_rocc_pptw_resp_bits_pte_d = GEN_99; - assign io_rocc_pptw_resp_bits_pte_r = GEN_100; - assign io_rocc_pptw_resp_bits_pte_typ = GEN_101; - assign io_rocc_pptw_resp_bits_pte_v = GEN_102; - assign io_rocc_pptw_status_sd = GEN_103; - assign io_rocc_pptw_status_zero2 = GEN_104; - assign io_rocc_pptw_status_sd_rv32 = GEN_105; - assign io_rocc_pptw_status_zero1 = GEN_106; - assign io_rocc_pptw_status_vm = GEN_107; - assign io_rocc_pptw_status_mprv = GEN_108; - assign io_rocc_pptw_status_xs = GEN_109; - assign io_rocc_pptw_status_fs = GEN_110; - assign io_rocc_pptw_status_prv3 = GEN_111; - assign io_rocc_pptw_status_ie3 = GEN_112; - assign io_rocc_pptw_status_prv2 = GEN_113; - assign io_rocc_pptw_status_ie2 = GEN_114; - assign io_rocc_pptw_status_prv1 = GEN_115; - assign io_rocc_pptw_status_ie1 = GEN_116; - assign io_rocc_pptw_status_prv = GEN_117; - assign io_rocc_pptw_status_ie = GEN_118; - assign io_rocc_pptw_invalidate = GEN_119; - assign io_rocc_fpu_req_ready = GEN_120; - assign io_rocc_fpu_resp_valid = GEN_121; - assign io_rocc_fpu_resp_bits_data = GEN_122; - assign io_rocc_fpu_resp_bits_exc = GEN_123; - assign io_rocc_exception = GEN_124; - assign io_rocc_dma_req_ready = GEN_125; - assign io_rocc_dma_resp_valid = GEN_126; - assign io_rocc_dma_resp_bits_client_xact_id = GEN_127; - assign io_rocc_dma_resp_bits_status = GEN_128; + assign io_rocc_cmd_valid = GEN_3; + assign io_rocc_cmd_bits_inst_funct = GEN_4; + assign io_rocc_cmd_bits_inst_rs2 = GEN_5; + assign io_rocc_cmd_bits_inst_rs1 = GEN_6; + assign io_rocc_cmd_bits_inst_xd = GEN_7; + assign io_rocc_cmd_bits_inst_xs1 = GEN_8; + assign io_rocc_cmd_bits_inst_xs2 = GEN_9; + assign io_rocc_cmd_bits_inst_rd = GEN_10; + assign io_rocc_cmd_bits_inst_opcode = GEN_11; + assign io_rocc_cmd_bits_rs1 = GEN_12; + assign io_rocc_cmd_bits_rs2 = GEN_13; + assign io_rocc_resp_ready = GEN_14; + assign io_rocc_mem_req_ready = GEN_15; + assign io_rocc_mem_resp_valid = GEN_16; + assign io_rocc_mem_resp_bits_addr = GEN_17; + assign io_rocc_mem_resp_bits_tag = GEN_18; + assign io_rocc_mem_resp_bits_cmd = GEN_19; + assign io_rocc_mem_resp_bits_typ = GEN_20; + assign io_rocc_mem_resp_bits_data = GEN_21; + assign io_rocc_mem_resp_bits_nack = GEN_22; + assign io_rocc_mem_resp_bits_replay = GEN_23; + assign io_rocc_mem_resp_bits_has_data = GEN_24; + assign io_rocc_mem_resp_bits_data_word_bypass = GEN_25; + assign io_rocc_mem_resp_bits_store_data = GEN_26; + assign io_rocc_mem_replay_next_valid = GEN_27; + assign io_rocc_mem_replay_next_bits = GEN_28; + assign io_rocc_mem_xcpt_ma_ld = GEN_29; + assign io_rocc_mem_xcpt_ma_st = GEN_30; + assign io_rocc_mem_xcpt_pf_ld = GEN_31; + assign io_rocc_mem_xcpt_pf_st = GEN_32; + assign io_rocc_mem_ordered = GEN_33; + assign io_rocc_s = GEN_34; + assign io_rocc_autl_acquire_ready = GEN_35; + assign io_rocc_autl_grant_valid = GEN_36; + assign io_rocc_autl_grant_bits_addr_beat = GEN_37; + assign io_rocc_autl_grant_bits_client_xact_id = GEN_38; + assign io_rocc_autl_grant_bits_manager_xact_id = GEN_39; + assign io_rocc_autl_grant_bits_is_builtin_type = GEN_40; + assign io_rocc_autl_grant_bits_g_type = GEN_41; + assign io_rocc_autl_grant_bits_data = GEN_42; + assign io_rocc_iptw_req_ready = GEN_43; + assign io_rocc_iptw_resp_valid = GEN_44; + assign io_rocc_iptw_resp_bits_error = GEN_45; + assign io_rocc_iptw_resp_bits_pte_ppn = GEN_46; + assign io_rocc_iptw_resp_bits_pte_reserved_for_software = GEN_47; + assign io_rocc_iptw_resp_bits_pte_d = GEN_48; + assign io_rocc_iptw_resp_bits_pte_r = GEN_49; + assign io_rocc_iptw_resp_bits_pte_typ = GEN_50; + assign io_rocc_iptw_resp_bits_pte_v = GEN_51; + assign io_rocc_iptw_status_sd = GEN_52; + assign io_rocc_iptw_status_zero2 = GEN_53; + assign io_rocc_iptw_status_sd_rv32 = GEN_54; + assign io_rocc_iptw_status_zero1 = GEN_55; + assign io_rocc_iptw_status_vm = GEN_56; + assign io_rocc_iptw_status_mprv = GEN_57; + assign io_rocc_iptw_status_xs = GEN_58; + assign io_rocc_iptw_status_fs = GEN_59; + assign io_rocc_iptw_status_prv3 = GEN_60; + assign io_rocc_iptw_status_ie3 = GEN_61; + assign io_rocc_iptw_status_prv2 = GEN_62; + assign io_rocc_iptw_status_ie2 = GEN_63; + assign io_rocc_iptw_status_prv1 = GEN_64; + assign io_rocc_iptw_status_ie1 = GEN_65; + assign io_rocc_iptw_status_prv = GEN_66; + assign io_rocc_iptw_status_ie = GEN_67; + assign io_rocc_iptw_invalidate = GEN_68; + assign io_rocc_dptw_req_ready = GEN_69; + assign io_rocc_dptw_resp_valid = GEN_70; + assign io_rocc_dptw_resp_bits_error = GEN_71; + assign io_rocc_dptw_resp_bits_pte_ppn = GEN_72; + assign io_rocc_dptw_resp_bits_pte_reserved_for_software = GEN_73; + assign io_rocc_dptw_resp_bits_pte_d = GEN_74; + assign io_rocc_dptw_resp_bits_pte_r = GEN_75; + assign io_rocc_dptw_resp_bits_pte_typ = GEN_76; + assign io_rocc_dptw_resp_bits_pte_v = GEN_77; + assign io_rocc_dptw_status_sd = GEN_78; + assign io_rocc_dptw_status_zero2 = GEN_79; + assign io_rocc_dptw_status_sd_rv32 = GEN_80; + assign io_rocc_dptw_status_zero1 = GEN_81; + assign io_rocc_dptw_status_vm = GEN_82; + assign io_rocc_dptw_status_mprv = GEN_83; + assign io_rocc_dptw_status_xs = GEN_84; + assign io_rocc_dptw_status_fs = GEN_85; + assign io_rocc_dptw_status_prv3 = GEN_86; + assign io_rocc_dptw_status_ie3 = GEN_87; + assign io_rocc_dptw_status_prv2 = GEN_88; + assign io_rocc_dptw_status_ie2 = GEN_89; + assign io_rocc_dptw_status_prv1 = GEN_90; + assign io_rocc_dptw_status_ie1 = GEN_91; + assign io_rocc_dptw_status_prv = GEN_92; + assign io_rocc_dptw_status_ie = GEN_93; + assign io_rocc_dptw_invalidate = GEN_94; + assign io_rocc_pptw_req_ready = GEN_95; + assign io_rocc_pptw_resp_valid = GEN_96; + assign io_rocc_pptw_resp_bits_error = GEN_97; + assign io_rocc_pptw_resp_bits_pte_ppn = GEN_98; + assign io_rocc_pptw_resp_bits_pte_reserved_for_software = GEN_99; + assign io_rocc_pptw_resp_bits_pte_d = GEN_100; + assign io_rocc_pptw_resp_bits_pte_r = GEN_101; + assign io_rocc_pptw_resp_bits_pte_typ = GEN_102; + assign io_rocc_pptw_resp_bits_pte_v = GEN_103; + assign io_rocc_pptw_status_sd = GEN_104; + assign io_rocc_pptw_status_zero2 = GEN_105; + assign io_rocc_pptw_status_sd_rv32 = GEN_106; + assign io_rocc_pptw_status_zero1 = GEN_107; + assign io_rocc_pptw_status_vm = GEN_108; + assign io_rocc_pptw_status_mprv = GEN_109; + assign io_rocc_pptw_status_xs = GEN_110; + assign io_rocc_pptw_status_fs = GEN_111; + assign io_rocc_pptw_status_prv3 = GEN_112; + assign io_rocc_pptw_status_ie3 = GEN_113; + assign io_rocc_pptw_status_prv2 = GEN_114; + assign io_rocc_pptw_status_ie2 = GEN_115; + assign io_rocc_pptw_status_prv1 = GEN_116; + assign io_rocc_pptw_status_ie1 = GEN_117; + assign io_rocc_pptw_status_prv = GEN_118; + assign io_rocc_pptw_status_ie = GEN_119; + assign io_rocc_pptw_invalidate = GEN_120; + assign io_rocc_fpu_req_ready = GEN_121; + assign io_rocc_fpu_resp_valid = GEN_122; + assign io_rocc_fpu_resp_bits_data = GEN_123; + assign io_rocc_fpu_resp_bits_exc = GEN_124; + assign io_rocc_exception = GEN_125; + assign io_rocc_dma_req_ready = GEN_126; + assign io_rocc_dma_resp_valid = GEN_127; + assign io_rocc_dma_resp_bits_client_xact_id = GEN_128; + assign io_rocc_dma_resp_bits_status = GEN_129; assign io_interrupt = T_4879; assign io_interrupt_cause = T_4943 ? 64'h8000000000000003 : T_4933 ? 64'h8000000000000002 : T_4921 ? 64'h8000000000000001 : T_4910 ? 64'h8000000000000001 : T_4899 ? 64'h8000000000000000 : T_4888 ? 64'h8000000000000000 : 1'h0; assign T_4480_mtip = 1'h0; @@ -96960,6 +97055,7 @@ module CSRFile( assign T_6083 = T_6081 | 2'h3; assign T_6084 = ~ T_6083; assign GEN_1 = T_5570 & T_5572; + assign GEN_2 = GEN_1 & T_5574; `ifndef SYNTHESIS integer initvar; initial begin @@ -97055,7 +97151,6 @@ module CSRFile( host_csr_bits_rw = {1{$random}}; host_csr_bits_addr = {1{$random}}; host_csr_bits_data = {2{$random}}; - GEN_2 = {1{$random}}; GEN_3 = {1{$random}}; GEN_4 = {1{$random}}; GEN_5 = {1{$random}}; @@ -97064,22 +97159,22 @@ module CSRFile( GEN_8 = {1{$random}}; GEN_9 = {1{$random}}; GEN_10 = {1{$random}}; - GEN_11 = {2{$random}}; + GEN_11 = {1{$random}}; GEN_12 = {2{$random}}; - GEN_13 = {1{$random}}; + GEN_13 = {2{$random}}; GEN_14 = {1{$random}}; GEN_15 = {1{$random}}; - GEN_16 = {2{$random}}; - GEN_17 = {1{$random}}; + GEN_16 = {1{$random}}; + GEN_17 = {2{$random}}; GEN_18 = {1{$random}}; GEN_19 = {1{$random}}; - GEN_20 = {2{$random}}; - GEN_21 = {1{$random}}; + GEN_20 = {1{$random}}; + GEN_21 = {2{$random}}; GEN_22 = {1{$random}}; GEN_23 = {1{$random}}; - GEN_24 = {2{$random}}; + GEN_24 = {1{$random}}; GEN_25 = {2{$random}}; - GEN_26 = {1{$random}}; + GEN_26 = {2{$random}}; GEN_27 = {1{$random}}; GEN_28 = {1{$random}}; GEN_29 = {1{$random}}; @@ -97094,8 +97189,8 @@ module CSRFile( GEN_38 = {1{$random}}; GEN_39 = {1{$random}}; GEN_40 = {1{$random}}; - GEN_41 = {4{$random}}; - GEN_42 = {1{$random}}; + GEN_41 = {1{$random}}; + GEN_42 = {4{$random}}; GEN_43 = {1{$random}}; GEN_44 = {1{$random}}; GEN_45 = {1{$random}}; @@ -97175,13 +97270,14 @@ module CSRFile( GEN_119 = {1{$random}}; GEN_120 = {1{$random}}; GEN_121 = {1{$random}}; - GEN_122 = {3{$random}}; - GEN_123 = {1{$random}}; + GEN_122 = {1{$random}}; + GEN_123 = {3{$random}}; GEN_124 = {1{$random}}; GEN_125 = {1{$random}}; GEN_126 = {1{$random}}; GEN_127 = {1{$random}}; GEN_128 = {1{$random}}; + GEN_129 = {1{$random}}; end `endif always @(posedge clk) begin @@ -98481,7 +98577,7 @@ module CSRFile( end end `ifndef SYNTHESIS - if(GEN_1 & T_5574) begin + if(GEN_2) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): these conditions must be mutually exclusive"); end `endif @@ -109743,6 +109839,7 @@ module BTB( wire GEN_131; wire GEN_132; wire GEN_133; + wire GEN_134; assign io_resp_valid = T_3520; assign io_resp_bits_taken = T_4564 ? 1'h0 : io_resp_valid; assign io_resp_bits_mask = 1'h1; @@ -113661,7 +113758,7 @@ module BTB( assign T_4894 = T_4567 == 1'h0; assign T_4896 = T_4894 == 1'h0; assign T_4897 = T_4896 & T_4892; - assign GEN_2 = GEN_133 ? T_4578_1 : T_4578_0; + assign GEN_2 = GEN_134 ? T_4578_1 : T_4578_0; assign T_4900 = T_4567 < 2'h2; assign T_4902 = T_4567 + 1'h1; assign T_4903 = T_4902[1:0]; @@ -113685,134 +113782,135 @@ module BTB( assign T_4933 = T_4928 ? T_4931 : 1'h1; assign GEN_4 = r_btb_update_valid & T_3085; assign GEN_5 = GEN_4 & T_3087; - assign GEN_6 = r_btb_update_valid & T_3085; - assign GEN_7 = 1'h0 == T_3090; - assign GEN_8 = 1'h1 == T_3090; - assign GEN_9 = 2'h2 == T_3090; - assign GEN_10 = 2'h3 == T_3090; - assign GEN_11 = 3'h4 == T_3090; - assign GEN_12 = 3'h5 == T_3090; - assign GEN_13 = 3'h6 == T_3090; - assign GEN_14 = 3'h7 == T_3090; - assign GEN_15 = 4'h8 == T_3090; - assign GEN_16 = 4'h9 == T_3090; - assign GEN_17 = 4'ha == T_3090; - assign GEN_18 = 4'hb == T_3090; - assign GEN_19 = 4'hc == T_3090; - assign GEN_20 = 4'hd == T_3090; - assign GEN_21 = 4'he == T_3090; - assign GEN_22 = 4'hf == T_3090; - assign GEN_23 = 5'h10 == T_3090; - assign GEN_24 = 5'h11 == T_3090; - assign GEN_25 = 5'h12 == T_3090; - assign GEN_26 = 5'h13 == T_3090; - assign GEN_27 = 5'h14 == T_3090; - assign GEN_28 = 5'h15 == T_3090; - assign GEN_29 = 5'h16 == T_3090; - assign GEN_30 = 5'h17 == T_3090; - assign GEN_31 = 5'h18 == T_3090; - assign GEN_32 = 5'h19 == T_3090; - assign GEN_33 = 5'h1a == T_3090; - assign GEN_34 = 5'h1b == T_3090; - assign GEN_35 = 5'h1c == T_3090; - assign GEN_36 = 5'h1d == T_3090; - assign GEN_37 = 5'h1e == T_3090; - assign GEN_38 = 5'h1f == T_3090; - assign GEN_39 = 6'h20 == T_3090; - assign GEN_40 = 6'h21 == T_3090; - assign GEN_41 = 6'h22 == T_3090; - assign GEN_42 = 6'h23 == T_3090; - assign GEN_43 = 6'h24 == T_3090; - assign GEN_44 = 6'h25 == T_3090; - assign GEN_45 = 6'h26 == T_3090; - assign GEN_46 = 6'h27 == T_3090; - assign GEN_47 = 6'h28 == T_3090; - assign GEN_48 = 6'h29 == T_3090; - assign GEN_49 = 6'h2a == T_3090; - assign GEN_50 = 6'h2b == T_3090; - assign GEN_51 = 6'h2c == T_3090; - assign GEN_52 = 6'h2d == T_3090; - assign GEN_53 = 6'h2e == T_3090; - assign GEN_54 = 6'h2f == T_3090; - assign GEN_55 = 6'h30 == T_3090; - assign GEN_56 = 6'h31 == T_3090; - assign GEN_57 = 6'h32 == T_3090; - assign GEN_58 = 6'h33 == T_3090; - assign GEN_59 = 6'h34 == T_3090; - assign GEN_60 = 6'h35 == T_3090; - assign GEN_61 = 6'h36 == T_3090; - assign GEN_62 = 6'h37 == T_3090; - assign GEN_63 = 6'h38 == T_3090; - assign GEN_64 = 6'h39 == T_3090; - assign GEN_65 = 6'h3a == T_3090; - assign GEN_66 = 6'h3b == T_3090; - assign GEN_67 = 6'h3c == T_3090; - assign GEN_68 = 6'h3d == T_3090; - assign GEN_69 = 1'h0 == T_3090; - assign GEN_70 = 1'h1 == T_3090; - assign GEN_71 = 2'h2 == T_3090; - assign GEN_72 = 2'h3 == T_3090; - assign GEN_73 = 3'h4 == T_3090; - assign GEN_74 = 3'h5 == T_3090; - assign GEN_75 = 3'h6 == T_3090; - assign GEN_76 = 3'h7 == T_3090; - assign GEN_77 = 4'h8 == T_3090; - assign GEN_78 = 4'h9 == T_3090; - assign GEN_79 = 4'ha == T_3090; - assign GEN_80 = 4'hb == T_3090; - assign GEN_81 = 4'hc == T_3090; - assign GEN_82 = 4'hd == T_3090; - assign GEN_83 = 4'he == T_3090; - assign GEN_84 = 4'hf == T_3090; - assign GEN_85 = 5'h10 == T_3090; - assign GEN_86 = 5'h11 == T_3090; - assign GEN_87 = 5'h12 == T_3090; - assign GEN_88 = 5'h13 == T_3090; - assign GEN_89 = 5'h14 == T_3090; - assign GEN_90 = 5'h15 == T_3090; - assign GEN_91 = 5'h16 == T_3090; - assign GEN_92 = 5'h17 == T_3090; - assign GEN_93 = 5'h18 == T_3090; - assign GEN_94 = 5'h19 == T_3090; - assign GEN_95 = 5'h1a == T_3090; - assign GEN_96 = 5'h1b == T_3090; - assign GEN_97 = 5'h1c == T_3090; - assign GEN_98 = 5'h1d == T_3090; - assign GEN_99 = 5'h1e == T_3090; - assign GEN_100 = 5'h1f == T_3090; - assign GEN_101 = 6'h20 == T_3090; - assign GEN_102 = 6'h21 == T_3090; - assign GEN_103 = 6'h22 == T_3090; - assign GEN_104 = 6'h23 == T_3090; - assign GEN_105 = 6'h24 == T_3090; - assign GEN_106 = 6'h25 == T_3090; - assign GEN_107 = 6'h26 == T_3090; - assign GEN_108 = 6'h27 == T_3090; - assign GEN_109 = 6'h28 == T_3090; - assign GEN_110 = 6'h29 == T_3090; - assign GEN_111 = 6'h2a == T_3090; - assign GEN_112 = 6'h2b == T_3090; - assign GEN_113 = 6'h2c == T_3090; - assign GEN_114 = 6'h2d == T_3090; - assign GEN_115 = 6'h2e == T_3090; - assign GEN_116 = 6'h2f == T_3090; - assign GEN_117 = 6'h30 == T_3090; - assign GEN_118 = 6'h31 == T_3090; - assign GEN_119 = 6'h32 == T_3090; - assign GEN_120 = 6'h33 == T_3090; - assign GEN_121 = 6'h34 == T_3090; - assign GEN_122 = 6'h35 == T_3090; - assign GEN_123 = 6'h36 == T_3090; - assign GEN_124 = 6'h37 == T_3090; - assign GEN_125 = 6'h38 == T_3090; - assign GEN_126 = 6'h39 == T_3090; - assign GEN_127 = 6'h3a == T_3090; - assign GEN_128 = 6'h3b == T_3090; - assign GEN_129 = 6'h3c == T_3090; - assign GEN_130 = 6'h3d == T_3090; - assign GEN_131 = 1'h0 == T_4912; - assign GEN_132 = 1'h1 == T_4912; - assign GEN_133 = 1'h1 == T_4569; + assign GEN_6 = GEN_5 & T_3089; + assign GEN_7 = r_btb_update_valid & T_3085; + assign GEN_8 = 1'h0 == T_3090; + assign GEN_9 = 1'h1 == T_3090; + assign GEN_10 = 2'h2 == T_3090; + assign GEN_11 = 2'h3 == T_3090; + assign GEN_12 = 3'h4 == T_3090; + assign GEN_13 = 3'h5 == T_3090; + assign GEN_14 = 3'h6 == T_3090; + assign GEN_15 = 3'h7 == T_3090; + assign GEN_16 = 4'h8 == T_3090; + assign GEN_17 = 4'h9 == T_3090; + assign GEN_18 = 4'ha == T_3090; + assign GEN_19 = 4'hb == T_3090; + assign GEN_20 = 4'hc == T_3090; + assign GEN_21 = 4'hd == T_3090; + assign GEN_22 = 4'he == T_3090; + assign GEN_23 = 4'hf == T_3090; + assign GEN_24 = 5'h10 == T_3090; + assign GEN_25 = 5'h11 == T_3090; + assign GEN_26 = 5'h12 == T_3090; + assign GEN_27 = 5'h13 == T_3090; + assign GEN_28 = 5'h14 == T_3090; + assign GEN_29 = 5'h15 == T_3090; + assign GEN_30 = 5'h16 == T_3090; + assign GEN_31 = 5'h17 == T_3090; + assign GEN_32 = 5'h18 == T_3090; + assign GEN_33 = 5'h19 == T_3090; + assign GEN_34 = 5'h1a == T_3090; + assign GEN_35 = 5'h1b == T_3090; + assign GEN_36 = 5'h1c == T_3090; + assign GEN_37 = 5'h1d == T_3090; + assign GEN_38 = 5'h1e == T_3090; + assign GEN_39 = 5'h1f == T_3090; + assign GEN_40 = 6'h20 == T_3090; + assign GEN_41 = 6'h21 == T_3090; + assign GEN_42 = 6'h22 == T_3090; + assign GEN_43 = 6'h23 == T_3090; + assign GEN_44 = 6'h24 == T_3090; + assign GEN_45 = 6'h25 == T_3090; + assign GEN_46 = 6'h26 == T_3090; + assign GEN_47 = 6'h27 == T_3090; + assign GEN_48 = 6'h28 == T_3090; + assign GEN_49 = 6'h29 == T_3090; + assign GEN_50 = 6'h2a == T_3090; + assign GEN_51 = 6'h2b == T_3090; + assign GEN_52 = 6'h2c == T_3090; + assign GEN_53 = 6'h2d == T_3090; + assign GEN_54 = 6'h2e == T_3090; + assign GEN_55 = 6'h2f == T_3090; + assign GEN_56 = 6'h30 == T_3090; + assign GEN_57 = 6'h31 == T_3090; + assign GEN_58 = 6'h32 == T_3090; + assign GEN_59 = 6'h33 == T_3090; + assign GEN_60 = 6'h34 == T_3090; + assign GEN_61 = 6'h35 == T_3090; + assign GEN_62 = 6'h36 == T_3090; + assign GEN_63 = 6'h37 == T_3090; + assign GEN_64 = 6'h38 == T_3090; + assign GEN_65 = 6'h39 == T_3090; + assign GEN_66 = 6'h3a == T_3090; + assign GEN_67 = 6'h3b == T_3090; + assign GEN_68 = 6'h3c == T_3090; + assign GEN_69 = 6'h3d == T_3090; + assign GEN_70 = 1'h0 == T_3090; + assign GEN_71 = 1'h1 == T_3090; + assign GEN_72 = 2'h2 == T_3090; + assign GEN_73 = 2'h3 == T_3090; + assign GEN_74 = 3'h4 == T_3090; + assign GEN_75 = 3'h5 == T_3090; + assign GEN_76 = 3'h6 == T_3090; + assign GEN_77 = 3'h7 == T_3090; + assign GEN_78 = 4'h8 == T_3090; + assign GEN_79 = 4'h9 == T_3090; + assign GEN_80 = 4'ha == T_3090; + assign GEN_81 = 4'hb == T_3090; + assign GEN_82 = 4'hc == T_3090; + assign GEN_83 = 4'hd == T_3090; + assign GEN_84 = 4'he == T_3090; + assign GEN_85 = 4'hf == T_3090; + assign GEN_86 = 5'h10 == T_3090; + assign GEN_87 = 5'h11 == T_3090; + assign GEN_88 = 5'h12 == T_3090; + assign GEN_89 = 5'h13 == T_3090; + assign GEN_90 = 5'h14 == T_3090; + assign GEN_91 = 5'h15 == T_3090; + assign GEN_92 = 5'h16 == T_3090; + assign GEN_93 = 5'h17 == T_3090; + assign GEN_94 = 5'h18 == T_3090; + assign GEN_95 = 5'h19 == T_3090; + assign GEN_96 = 5'h1a == T_3090; + assign GEN_97 = 5'h1b == T_3090; + assign GEN_98 = 5'h1c == T_3090; + assign GEN_99 = 5'h1d == T_3090; + assign GEN_100 = 5'h1e == T_3090; + assign GEN_101 = 5'h1f == T_3090; + assign GEN_102 = 6'h20 == T_3090; + assign GEN_103 = 6'h21 == T_3090; + assign GEN_104 = 6'h22 == T_3090; + assign GEN_105 = 6'h23 == T_3090; + assign GEN_106 = 6'h24 == T_3090; + assign GEN_107 = 6'h25 == T_3090; + assign GEN_108 = 6'h26 == T_3090; + assign GEN_109 = 6'h27 == T_3090; + assign GEN_110 = 6'h28 == T_3090; + assign GEN_111 = 6'h29 == T_3090; + assign GEN_112 = 6'h2a == T_3090; + assign GEN_113 = 6'h2b == T_3090; + assign GEN_114 = 6'h2c == T_3090; + assign GEN_115 = 6'h2d == T_3090; + assign GEN_116 = 6'h2e == T_3090; + assign GEN_117 = 6'h2f == T_3090; + assign GEN_118 = 6'h30 == T_3090; + assign GEN_119 = 6'h31 == T_3090; + assign GEN_120 = 6'h32 == T_3090; + assign GEN_121 = 6'h33 == T_3090; + assign GEN_122 = 6'h34 == T_3090; + assign GEN_123 = 6'h35 == T_3090; + assign GEN_124 = 6'h36 == T_3090; + assign GEN_125 = 6'h37 == T_3090; + assign GEN_126 = 6'h38 == T_3090; + assign GEN_127 = 6'h39 == T_3090; + assign GEN_128 = 6'h3a == T_3090; + assign GEN_129 = 6'h3b == T_3090; + assign GEN_130 = 6'h3c == T_3090; + assign GEN_131 = 6'h3d == T_3090; + assign GEN_132 = 1'h0 == T_4912; + assign GEN_133 = 1'h1 == T_4912; + assign GEN_134 = 1'h1 == T_4569; `ifndef SYNTHESIS integer initvar; initial begin @@ -114017,7 +114115,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_7) begin + if(GEN_8) begin useRAS_0 <= GEN_0; end else begin ; @@ -114030,7 +114128,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_8) begin + if(GEN_9) begin useRAS_1 <= GEN_0; end else begin ; @@ -114043,7 +114141,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_9) begin + if(GEN_10) begin useRAS_2 <= GEN_0; end else begin ; @@ -114056,7 +114154,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_10) begin + if(GEN_11) begin useRAS_3 <= GEN_0; end else begin ; @@ -114069,7 +114167,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_11) begin + if(GEN_12) begin useRAS_4 <= GEN_0; end else begin ; @@ -114082,7 +114180,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_12) begin + if(GEN_13) begin useRAS_5 <= GEN_0; end else begin ; @@ -114095,7 +114193,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_13) begin + if(GEN_14) begin useRAS_6 <= GEN_0; end else begin ; @@ -114108,7 +114206,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_14) begin + if(GEN_15) begin useRAS_7 <= GEN_0; end else begin ; @@ -114121,7 +114219,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_15) begin + if(GEN_16) begin useRAS_8 <= GEN_0; end else begin ; @@ -114134,7 +114232,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_16) begin + if(GEN_17) begin useRAS_9 <= GEN_0; end else begin ; @@ -114147,7 +114245,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_17) begin + if(GEN_18) begin useRAS_10 <= GEN_0; end else begin ; @@ -114160,7 +114258,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_18) begin + if(GEN_19) begin useRAS_11 <= GEN_0; end else begin ; @@ -114173,7 +114271,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_19) begin + if(GEN_20) begin useRAS_12 <= GEN_0; end else begin ; @@ -114186,7 +114284,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_20) begin + if(GEN_21) begin useRAS_13 <= GEN_0; end else begin ; @@ -114199,7 +114297,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_21) begin + if(GEN_22) begin useRAS_14 <= GEN_0; end else begin ; @@ -114212,7 +114310,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_22) begin + if(GEN_23) begin useRAS_15 <= GEN_0; end else begin ; @@ -114225,7 +114323,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_23) begin + if(GEN_24) begin useRAS_16 <= GEN_0; end else begin ; @@ -114238,7 +114336,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_24) begin + if(GEN_25) begin useRAS_17 <= GEN_0; end else begin ; @@ -114251,7 +114349,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_25) begin + if(GEN_26) begin useRAS_18 <= GEN_0; end else begin ; @@ -114264,7 +114362,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_26) begin + if(GEN_27) begin useRAS_19 <= GEN_0; end else begin ; @@ -114277,7 +114375,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_27) begin + if(GEN_28) begin useRAS_20 <= GEN_0; end else begin ; @@ -114290,7 +114388,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_28) begin + if(GEN_29) begin useRAS_21 <= GEN_0; end else begin ; @@ -114303,7 +114401,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_29) begin + if(GEN_30) begin useRAS_22 <= GEN_0; end else begin ; @@ -114316,7 +114414,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_30) begin + if(GEN_31) begin useRAS_23 <= GEN_0; end else begin ; @@ -114329,7 +114427,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_31) begin + if(GEN_32) begin useRAS_24 <= GEN_0; end else begin ; @@ -114342,7 +114440,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_32) begin + if(GEN_33) begin useRAS_25 <= GEN_0; end else begin ; @@ -114355,7 +114453,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_33) begin + if(GEN_34) begin useRAS_26 <= GEN_0; end else begin ; @@ -114368,7 +114466,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_34) begin + if(GEN_35) begin useRAS_27 <= GEN_0; end else begin ; @@ -114381,7 +114479,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_35) begin + if(GEN_36) begin useRAS_28 <= GEN_0; end else begin ; @@ -114394,7 +114492,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_36) begin + if(GEN_37) begin useRAS_29 <= GEN_0; end else begin ; @@ -114407,7 +114505,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_37) begin + if(GEN_38) begin useRAS_30 <= GEN_0; end else begin ; @@ -114420,7 +114518,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_38) begin + if(GEN_39) begin useRAS_31 <= GEN_0; end else begin ; @@ -114433,7 +114531,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_39) begin + if(GEN_40) begin useRAS_32 <= GEN_0; end else begin ; @@ -114446,7 +114544,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_40) begin + if(GEN_41) begin useRAS_33 <= GEN_0; end else begin ; @@ -114459,7 +114557,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_41) begin + if(GEN_42) begin useRAS_34 <= GEN_0; end else begin ; @@ -114472,7 +114570,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_42) begin + if(GEN_43) begin useRAS_35 <= GEN_0; end else begin ; @@ -114485,7 +114583,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_43) begin + if(GEN_44) begin useRAS_36 <= GEN_0; end else begin ; @@ -114498,7 +114596,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_44) begin + if(GEN_45) begin useRAS_37 <= GEN_0; end else begin ; @@ -114511,7 +114609,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_45) begin + if(GEN_46) begin useRAS_38 <= GEN_0; end else begin ; @@ -114524,7 +114622,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_46) begin + if(GEN_47) begin useRAS_39 <= GEN_0; end else begin ; @@ -114537,7 +114635,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_47) begin + if(GEN_48) begin useRAS_40 <= GEN_0; end else begin ; @@ -114550,7 +114648,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_48) begin + if(GEN_49) begin useRAS_41 <= GEN_0; end else begin ; @@ -114563,7 +114661,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_49) begin + if(GEN_50) begin useRAS_42 <= GEN_0; end else begin ; @@ -114576,7 +114674,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_50) begin + if(GEN_51) begin useRAS_43 <= GEN_0; end else begin ; @@ -114589,7 +114687,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_51) begin + if(GEN_52) begin useRAS_44 <= GEN_0; end else begin ; @@ -114602,7 +114700,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_52) begin + if(GEN_53) begin useRAS_45 <= GEN_0; end else begin ; @@ -114615,7 +114713,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_53) begin + if(GEN_54) begin useRAS_46 <= GEN_0; end else begin ; @@ -114628,7 +114726,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_54) begin + if(GEN_55) begin useRAS_47 <= GEN_0; end else begin ; @@ -114641,7 +114739,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_55) begin + if(GEN_56) begin useRAS_48 <= GEN_0; end else begin ; @@ -114654,7 +114752,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_56) begin + if(GEN_57) begin useRAS_49 <= GEN_0; end else begin ; @@ -114667,7 +114765,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_57) begin + if(GEN_58) begin useRAS_50 <= GEN_0; end else begin ; @@ -114680,7 +114778,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_58) begin + if(GEN_59) begin useRAS_51 <= GEN_0; end else begin ; @@ -114693,7 +114791,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_59) begin + if(GEN_60) begin useRAS_52 <= GEN_0; end else begin ; @@ -114706,7 +114804,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_60) begin + if(GEN_61) begin useRAS_53 <= GEN_0; end else begin ; @@ -114719,7 +114817,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_61) begin + if(GEN_62) begin useRAS_54 <= GEN_0; end else begin ; @@ -114732,7 +114830,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_62) begin + if(GEN_63) begin useRAS_55 <= GEN_0; end else begin ; @@ -114745,7 +114843,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_63) begin + if(GEN_64) begin useRAS_56 <= GEN_0; end else begin ; @@ -114758,7 +114856,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_64) begin + if(GEN_65) begin useRAS_57 <= GEN_0; end else begin ; @@ -114771,7 +114869,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_65) begin + if(GEN_66) begin useRAS_58 <= GEN_0; end else begin ; @@ -114784,7 +114882,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_66) begin + if(GEN_67) begin useRAS_59 <= GEN_0; end else begin ; @@ -114797,7 +114895,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_67) begin + if(GEN_68) begin useRAS_60 <= GEN_0; end else begin ; @@ -114810,7 +114908,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_68) begin + if(GEN_69) begin useRAS_61 <= GEN_0; end else begin ; @@ -114823,7 +114921,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_69) begin + if(GEN_70) begin isJump_0 <= GEN_1; end else begin ; @@ -114836,7 +114934,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_70) begin + if(GEN_71) begin isJump_1 <= GEN_1; end else begin ; @@ -114849,7 +114947,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_71) begin + if(GEN_72) begin isJump_2 <= GEN_1; end else begin ; @@ -114862,7 +114960,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_72) begin + if(GEN_73) begin isJump_3 <= GEN_1; end else begin ; @@ -114875,7 +114973,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_73) begin + if(GEN_74) begin isJump_4 <= GEN_1; end else begin ; @@ -114888,7 +114986,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_74) begin + if(GEN_75) begin isJump_5 <= GEN_1; end else begin ; @@ -114901,7 +114999,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_75) begin + if(GEN_76) begin isJump_6 <= GEN_1; end else begin ; @@ -114914,7 +115012,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_76) begin + if(GEN_77) begin isJump_7 <= GEN_1; end else begin ; @@ -114927,7 +115025,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_77) begin + if(GEN_78) begin isJump_8 <= GEN_1; end else begin ; @@ -114940,7 +115038,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_78) begin + if(GEN_79) begin isJump_9 <= GEN_1; end else begin ; @@ -114953,7 +115051,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_79) begin + if(GEN_80) begin isJump_10 <= GEN_1; end else begin ; @@ -114966,7 +115064,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_80) begin + if(GEN_81) begin isJump_11 <= GEN_1; end else begin ; @@ -114979,7 +115077,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_81) begin + if(GEN_82) begin isJump_12 <= GEN_1; end else begin ; @@ -114992,7 +115090,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_82) begin + if(GEN_83) begin isJump_13 <= GEN_1; end else begin ; @@ -115005,7 +115103,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_83) begin + if(GEN_84) begin isJump_14 <= GEN_1; end else begin ; @@ -115018,7 +115116,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_84) begin + if(GEN_85) begin isJump_15 <= GEN_1; end else begin ; @@ -115031,7 +115129,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_85) begin + if(GEN_86) begin isJump_16 <= GEN_1; end else begin ; @@ -115044,7 +115142,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_86) begin + if(GEN_87) begin isJump_17 <= GEN_1; end else begin ; @@ -115057,7 +115155,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_87) begin + if(GEN_88) begin isJump_18 <= GEN_1; end else begin ; @@ -115070,7 +115168,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_88) begin + if(GEN_89) begin isJump_19 <= GEN_1; end else begin ; @@ -115083,7 +115181,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_89) begin + if(GEN_90) begin isJump_20 <= GEN_1; end else begin ; @@ -115096,7 +115194,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_90) begin + if(GEN_91) begin isJump_21 <= GEN_1; end else begin ; @@ -115109,7 +115207,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_91) begin + if(GEN_92) begin isJump_22 <= GEN_1; end else begin ; @@ -115122,7 +115220,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_92) begin + if(GEN_93) begin isJump_23 <= GEN_1; end else begin ; @@ -115135,7 +115233,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_93) begin + if(GEN_94) begin isJump_24 <= GEN_1; end else begin ; @@ -115148,7 +115246,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_94) begin + if(GEN_95) begin isJump_25 <= GEN_1; end else begin ; @@ -115161,7 +115259,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_95) begin + if(GEN_96) begin isJump_26 <= GEN_1; end else begin ; @@ -115174,7 +115272,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_96) begin + if(GEN_97) begin isJump_27 <= GEN_1; end else begin ; @@ -115187,7 +115285,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_97) begin + if(GEN_98) begin isJump_28 <= GEN_1; end else begin ; @@ -115200,7 +115298,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_98) begin + if(GEN_99) begin isJump_29 <= GEN_1; end else begin ; @@ -115213,7 +115311,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_99) begin + if(GEN_100) begin isJump_30 <= GEN_1; end else begin ; @@ -115226,7 +115324,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_100) begin + if(GEN_101) begin isJump_31 <= GEN_1; end else begin ; @@ -115239,7 +115337,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_101) begin + if(GEN_102) begin isJump_32 <= GEN_1; end else begin ; @@ -115252,7 +115350,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_102) begin + if(GEN_103) begin isJump_33 <= GEN_1; end else begin ; @@ -115265,7 +115363,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_103) begin + if(GEN_104) begin isJump_34 <= GEN_1; end else begin ; @@ -115278,7 +115376,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_104) begin + if(GEN_105) begin isJump_35 <= GEN_1; end else begin ; @@ -115291,7 +115389,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_105) begin + if(GEN_106) begin isJump_36 <= GEN_1; end else begin ; @@ -115304,7 +115402,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_106) begin + if(GEN_107) begin isJump_37 <= GEN_1; end else begin ; @@ -115317,7 +115415,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_107) begin + if(GEN_108) begin isJump_38 <= GEN_1; end else begin ; @@ -115330,7 +115428,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_108) begin + if(GEN_109) begin isJump_39 <= GEN_1; end else begin ; @@ -115343,7 +115441,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_109) begin + if(GEN_110) begin isJump_40 <= GEN_1; end else begin ; @@ -115356,7 +115454,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_110) begin + if(GEN_111) begin isJump_41 <= GEN_1; end else begin ; @@ -115369,7 +115467,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_111) begin + if(GEN_112) begin isJump_42 <= GEN_1; end else begin ; @@ -115382,7 +115480,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_112) begin + if(GEN_113) begin isJump_43 <= GEN_1; end else begin ; @@ -115395,7 +115493,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_113) begin + if(GEN_114) begin isJump_44 <= GEN_1; end else begin ; @@ -115408,7 +115506,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_114) begin + if(GEN_115) begin isJump_45 <= GEN_1; end else begin ; @@ -115421,7 +115519,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_115) begin + if(GEN_116) begin isJump_46 <= GEN_1; end else begin ; @@ -115434,7 +115532,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_116) begin + if(GEN_117) begin isJump_47 <= GEN_1; end else begin ; @@ -115447,7 +115545,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_117) begin + if(GEN_118) begin isJump_48 <= GEN_1; end else begin ; @@ -115460,7 +115558,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_118) begin + if(GEN_119) begin isJump_49 <= GEN_1; end else begin ; @@ -115473,7 +115571,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_119) begin + if(GEN_120) begin isJump_50 <= GEN_1; end else begin ; @@ -115486,7 +115584,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_120) begin + if(GEN_121) begin isJump_51 <= GEN_1; end else begin ; @@ -115499,7 +115597,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_121) begin + if(GEN_122) begin isJump_52 <= GEN_1; end else begin ; @@ -115512,7 +115610,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_122) begin + if(GEN_123) begin isJump_53 <= GEN_1; end else begin ; @@ -115525,7 +115623,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_123) begin + if(GEN_124) begin isJump_54 <= GEN_1; end else begin ; @@ -115538,7 +115636,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_124) begin + if(GEN_125) begin isJump_55 <= GEN_1; end else begin ; @@ -115551,7 +115649,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_125) begin + if(GEN_126) begin isJump_56 <= GEN_1; end else begin ; @@ -115564,7 +115662,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_126) begin + if(GEN_127) begin isJump_57 <= GEN_1; end else begin ; @@ -115577,7 +115675,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_127) begin + if(GEN_128) begin isJump_58 <= GEN_1; end else begin ; @@ -115590,7 +115688,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_128) begin + if(GEN_129) begin isJump_59 <= GEN_1; end else begin ; @@ -115603,7 +115701,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_129) begin + if(GEN_130) begin isJump_60 <= GEN_1; end else begin ; @@ -115616,7 +115714,7 @@ module BTB( ; end else begin if(r_btb_update_valid) begin - if(GEN_130) begin + if(GEN_131) begin isJump_61 <= GEN_1; end else begin ; @@ -115871,7 +115969,7 @@ module BTB( end else begin if(io_ras_update_valid) begin if(io_ras_update_bits_isCall) begin - if(GEN_131) begin + if(GEN_132) begin T_4578_0 <= GEN_3; end else begin ; @@ -115888,7 +115986,7 @@ module BTB( end else begin if(io_ras_update_valid) begin if(io_ras_update_bits_isCall) begin - if(GEN_132) begin + if(GEN_133) begin T_4578_1 <= GEN_3; end else begin ; @@ -115901,12 +115999,12 @@ module BTB( end end `ifndef SYNTHESIS - if(GEN_5 & T_3089) begin + if(GEN_6) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): BTB request != I$ target"); end `endif `ifndef SYNTHESIS - if(GEN_6 & T_3087) begin + if(GEN_7 & T_3087) begin $fdisplay(32'h80000002,"1");$finish; end `endif @@ -120966,6 +121064,7 @@ module ProbeUnit( wire T_1169; wire T_1170; wire GEN_0; + wire GEN_1; assign io_req_ready = T_1061; assign io_rep_valid = T_1062; assign io_rep_bits_addr_beat = reply_addr_beat; @@ -121089,6 +121188,7 @@ module ProbeUnit( assign T_1169 = T_1168 & io_wb_req_ready; assign T_1170 = io_meta_write_ready & io_meta_write_valid; assign GEN_0 = T_1082 & T_1084; + assign GEN_1 = GEN_0 & T_1086; `ifndef SYNTHESIS integer initvar; initial begin @@ -121193,7 +121293,7 @@ module ProbeUnit( end end `ifndef SYNTHESIS - if(GEN_0 & T_1086) begin + if(GEN_1) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): ProbeUnit should not send releases with data"); end `endif @@ -129281,8 +129381,9 @@ module HellaCache( wire T_5207; wire T_5208; wire GEN_1; - reg [1:0] GEN_2; - reg [63:0] GEN_3; + wire GEN_2; + reg [1:0] GEN_3; + reg [63:0] GEN_4; WritebackUnit wb ( .clk(wb_clk), .reset(wb_reset), @@ -129764,7 +129865,7 @@ module HellaCache( assign prober_io_req_valid = T_4167; assign prober_io_req_bits_addr_block = io_mem_probe_bits_addr_block; assign prober_io_req_bits_p_type = io_mem_probe_bits_p_type; - assign prober_io_req_bits_client_xact_id = GEN_2; + assign prober_io_req_bits_client_xact_id = GEN_3; assign prober_io_rep_ready = releaseArb_io_in_1_ready; assign prober_io_meta_read_ready = metaReadArb_io_in_2_ready; assign prober_io_meta_write_ready = metaWriteArb_io_in_1_ready; @@ -130451,7 +130552,7 @@ module HellaCache( assign cache_resp_bits_nack = T_4773; assign cache_resp_bits_replay = s2_replay; assign cache_resp_bits_has_data = T_4714; - assign cache_resp_bits_data_word_bypass = GEN_3; + assign cache_resp_bits_data_word_bypass = GEN_4; assign cache_resp_bits_store_data = s2_req_data; assign T_4701 = s2_valid_masked & s2_hit; assign T_4702 = s2_replay | T_4701; @@ -130559,6 +130660,7 @@ module HellaCache( assign T_5207 = T_5204 & T_5206; assign T_5208 = s1_replay & s1_read; assign GEN_1 = T_1879 & T_1881; + assign GEN_2 = GEN_1 & T_1883; `ifndef SYNTHESIS integer initvar; initial begin @@ -130632,8 +130734,8 @@ module HellaCache( s2_nack_hit = {1{$random}}; s2_recycle_next = {1{$random}}; block_miss = {1{$random}}; - GEN_2 = {1{$random}}; - GEN_3 = {2{$random}}; + GEN_3 = {1{$random}}; + GEN_4 = {2{$random}}; end `endif always @(posedge clk) begin @@ -131339,7 +131441,7 @@ module HellaCache( block_miss <= T_4410; end `ifndef SYNTHESIS - if(GEN_1 & T_1883) begin + if(GEN_2) begin $fwrite(32'h80000002,"Assertion failed: (TODO: code / lineno): DCache exception occurred - cache response not killed."); end `endif |