Changed DefMemory to be a non-vector type with a size member. Necessary for ASIC backend.

8 files changed, 58 insertions, 32 deletions

diff --git a/Makefile b/Makefile
index 3085bfaa..881f2745 100644
--- a/Makefile
+++ b/Makefile
@@ -28,7 +28,7 @@ build:
 build-fast: 
 	cd $(firrtl_dir) && stanza -i firrtl-test-main.stanza -o $(root_dir)/utils/bin/firrtl -flags OPTIMIZE
 
-check:
+check: 
 	cd $(test_dir) && lit -v . --path=$(root_dir)/utils/bin/
 
 regress: 
@@ -60,7 +60,7 @@ $(units): % :
 	firrtl -X verilog -i test/chisel3/$*.fir -o test/chisel3/$*.fir.v -p c > test/chisel3/$*.fir.out 
 	#scp test/chisel3/$*.fir.v adamiz@a5:/scratch/adamiz/firrtl-all/riscv-mini/generated-src/$*.v
 
-done: build check
+done: build-fast check regress
 	say "done"
 
 fail:
diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza
index 8b8c86fb..ad289ea0 100644
--- a/src/main/stanza/errors.stanza
+++ b/src/main/stanza/errors.stanza
@@ -101,6 +101,10 @@ defn NegVecSize (info:FileInfo) :
    PassException $ string-join $
    [info ": [module " mname "]  Vector type size cannot be negative."]
 
+defn NegMemSize (info:FileInfo) :
+   PassException $ string-join $
+   [info ": [module " mname "]  Memory size cannot be negative or zero."]
+
 defn IllegalUnknownWidth (info:FileInfo) :
    PassException $ string-join $
    [info ": [module " mname "]  Widths must be defined for memories and poison nodes."]
@@ -312,6 +316,7 @@ public defn check-high-form (c:Circuit) -> Circuit :
                check-name(info(s),name(s))
                names[name(s)] = true
                if has-flip?(type(s)) : add(errors, MemWithFlip(info(s), name(s)))
+               if size(s) <= 0 : add(errors,NegMemSize(info(s)))
                check-high-form-t(info(s),type(s),false)
                check-high-form-e(info(s),clock(s),names)
             (s:DefInstance) : 
@@ -394,11 +399,20 @@ defn OnResetNotReg (info:FileInfo, name:Symbol) :
    PassException $ string-join $
    [info ": [module " mname "]  Illegal on-reset to non-reg reference " name "."]
 
+defn AccessVecOrMem (info:FileInfo) :
+   PassException $ string-join $
+   [info ": [module " mname "]  Accessors can only access vector-typed components or memories."]
+
 ;----------------- Check Kinds Pass ---------------------
 ; I may have been overeager in looking for places where mems can't be, as mems are guaranteed to have a vector
 ;   type, and this will get caught in the type check pass
 public defn check-kinds (c:Circuit) -> Circuit : 
    val errors = Vector<PassException>()
+   defn get-kind (e:Expression) -> Kind :
+      match(e) :
+         (e:WRef) : kind(e)
+         (e:WSubfield) : get-kind(exp(e))
+         (e:WIndex) : get-kind(exp(e))
    defn check-not-mem (info:FileInfo,e:Expression) -> False :
       do(check-not-mem{info,_},e) 
       match(e) :
@@ -424,7 +438,12 @@ public defn check-kinds (c:Circuit) -> Circuit :
    defn check-kinds-s (s:Stmt) -> False :
       match(s) : 
          (s:DefNode) : check-not-mem(info(s),value(s))
-         (s:DefAccessor) : check-not-mem(info(s),index(s))
+         (s:DefAccessor) : 
+            check-not-mem(info(s),index(s))
+            if (get-kind(source(s)) != MemKind()) and (not type(source(s)) typeof VectorType) :
+               println(get-kind(source(s)))
+               println(type(source(s)))
+               add(errors,AccessVecOrMem(info(s)))
          (s:Conditionally) : check-not-mem(info(s),pred(s))
          (s:Connect) : 
             check-not-mem(info(s),loc(s))
@@ -519,7 +538,6 @@ defn OnResetIllegalFlips (info:FileInfo) :
    PassException $ string-join $
    [info ": [module " mname "]  The register in onreset cannot be a bundle type with flips."]
 
-
 ;---------------- Helper Functions --------------
 defmethod equal? (t1:Type,t2:Type) -> True|False :
    match(t1,t2) : 
@@ -1030,7 +1048,7 @@ public defn check-low-form (c:Circuit) -> Circuit :
             (s:DefPoison) :
                check-low-form-t(info(s),type(s),name(s))
             (s:DefMemory) : 
-               check-low-form-t(info(s),type(type(s)),name(s))
+               check-low-form-t(info(s),type(s),name(s))
                add(mems,name(s))
             (s:DefInstance) : 
                for f in fields(type(module(s)) as BundleType) do :
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index b0db73b2..0ed785c7 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -118,9 +118,10 @@ public defstruct DefInstance <: Stmt : ;LOW
 public defstruct DefMemory <: Stmt : ;LOW
    info: FileInfo with: (as-method => true)
    name: Symbol
-   type: VectorType
+   type: Type
    seq?: True|False
    clock: Expression
+   size: Int
 public defstruct DefNode <: Stmt : ;LOW
    info: FileInfo with: (as-method => true)
    name: Symbol
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index f81777f5..c2c7cfa5 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -236,8 +236,8 @@ defsyntax firrtl :
       stmt = (skip) : EmptyStmt()
       stmt = (wire ?name:#id! #:! ?t:#type!) : DefWire(first-info(form),name, t)
       stmt = (reg ?name:#id! #:! ?t:#type! ?clk:#exp! ?reset:#exp!) : DefRegister(first-info(form),name, t,clk,reset)
-      stmt = (cmem ?name:#id! #:! ?t:#vectype! ?clk:#exp!) : DefMemory(first-info(form),name, t, false, clk)
-      stmt = (smem ?name:#id! #:! ?t:#vectype! ?clk:#exp!) : DefMemory(first-info(form),name, t, true, clk)
+      stmt = (cmem ?name:#id! #:! ?t:#vectype! ?clk:#exp!) : DefMemory(first-info(form),name, type(t), false, clk, size(t))
+      stmt = (smem ?name:#id! #:! ?t:#vectype! ?clk:#exp!) : DefMemory(first-info(form),name, type(t), true, clk, size(t))
       stmt = (inst ?name:#id! #of! ?m:#ref!) : DefInstance(first-info(form),name,m)
       stmt = (node ?name:#id! #=! ?e:#exp!) : DefNode(first-info(form),name,e)
       stmt = (poison ?name:#id! #:! ?t:#type!) : DefPoison(first-info(form),name, t)
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index a234ff81..355f67a4 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -226,8 +226,8 @@ defmethod print (o:OutputStream, c:Stmt) :
       (c:DefRegister) : 
          print-all(o,["reg " name(c) " : " type(c) ", " clock(c) ", " reset(c)])
       (c:DefMemory) :
-         if seq?(c) : print-all(o,["smem " name(c) " : " type(c) ", " clock(c)])
-         else       : print-all(o,["cmem " name(c) " : " type(c) ", " clock(c)])
+         if seq?(c) : print-all(o,["smem " name(c) " : " VectorType(type(c),size(c)) ", " clock(c)])
+         else       : print-all(o,["cmem " name(c) " : " VectorType(type(c),size(c)) ", " clock(c)])
       (c:DefInstance) :
          print-all(o,["inst " name(c) " of " module(c)])
       (c:DefNode) :
@@ -341,7 +341,7 @@ defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt :
    match(c) :
       (c:DefAccessor) : DefAccessor(info(c),name(c), f(source(c)), f(index(c)),acc-dir(c))
       (c:DefRegister) : DefRegister(info(c),name(c), type(c), f(clock(c)), f(reset(c)))
-      (c:DefMemory) : DefMemory(info(c),name(c), type(c), seq?(c), f(clock(c)))
+      (c:DefMemory) : DefMemory(info(c),name(c), type(c), seq?(c), f(clock(c)), size(c))
       (c:DefNode) : DefNode(info(c),name(c), f(value(c)))
       (c:DefInstance) : DefInstance(info(c),name(c), f(module(c)))
       (c:Conditionally) : Conditionally(info(c),f(pred(c)), conseq(c), alt(c))
@@ -386,7 +386,7 @@ defmethod map (f: Type -> Type, c:Stmt) -> Stmt :
       (c:DefPoison) : DefPoison(info(c),name(c),f(type(c)))
       (c:DefWire) : DefWire(info(c),name(c),f(type(c)))
       (c:DefRegister) : DefRegister(info(c),name(c),f(type(c)),clock(c),reset(c))
-      (c:DefMemory) : DefMemory(info(c),name(c),f(type(c)) as VectorType,seq?(c),clock(c))
+      (c:DefMemory) : DefMemory(info(c),name(c),f(type(c)),seq?(c),clock(c),size(c))
       (c) : c
 
 public defmulti mapr<?T> (f: Width -> Width, t:?T&Type) -> T
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 99fb8172..b1d523bd 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -346,7 +346,7 @@ defn remove-special-chars (c:Circuit) :
          (s:DefPoison) : DefPoison(info(s),rename(name(s)),rename-t(type(s)))
          (s:DefRegister) : DefRegister(info(s),rename(name(s)),rename-t(type(s)),rename-e(clock(s)),rename-e(reset(s)))
          (s:DefInstance) : DefInstance(info(s),rename(name(s)),rename-e(module(s)))
-         (s:DefMemory) : DefMemory(info(s),rename(name(s)),rename-t(type(s)) as VectorType,seq?(s),rename-e(clock(s)))
+         (s:DefMemory) : DefMemory(info(s),rename(name(s)),rename-t(type(s)),seq?(s),rename-e(clock(s)),size(s))
          (s:DefNode) : DefNode(info(s),rename(name(s)),rename-e(value(s)))
          (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),rename-e(source(s)),rename-e(index(s)),acc-dir(s))
          (s:Conditionally) : Conditionally(info(s),rename-e(pred(s)),rename-s(conseq(s)),rename-s(alt(s)))
@@ -412,7 +412,7 @@ defn remove-scopes (c:Circuit) :
             (s:DefPoison) : DefPoison(info(s),rename(name(s),env),type(s))
             (s:DefRegister) : DefRegister(info(s),rename(name(s),env),type(s),clock(s),reset(s))
             (s:DefInstance) : DefInstance(info(s),rename(name(s),env),module(s))
-            (s:DefMemory) : DefMemory(info(s),rename(name(s),env),type(s),seq?(s),clock(s))
+            (s:DefMemory) : DefMemory(info(s),rename(name(s),env),type(s),seq?(s),clock(s),size(s))
             (s:DefNode) : DefNode(info(s),rename(name(s),env),value(s))
             (s:DefAccessor) : DefAccessor(info(s),rename(name(s),env),source(s),index(s),acc-dir(s))
             (s:Conditionally) :
@@ -685,7 +685,7 @@ defn infer-types (s:Stmt, l:List<KeyValue<Symbol,Type>>) -> [Stmt List<KeyValue<
       (s:DefMemory) : [s,List(name(s) => type(s),l)]
       (s:DefInstance) : [s, List(name(s) => type(module(s)),l)]
       (s:DefNode) : [s, List(name(s) => type(value(s)),l)]
-      (s:DefAccessor) : [s, List(name(s) => get-vector-subtype(type(source(s))),l)]
+      (s:DefAccessor) : [s, List(name(s) => type(s),l)]
       (s:Conditionally) : 
         val [s*,l*] = infer-types(conseq(s),l)
         val [s**,l**] = infer-types(alt(s),l)
@@ -1004,9 +1004,16 @@ defn lower-ports (ports:List<Port>) -> List<Port> :
       for x in generate-entry(name(p),type(p)) map :
          Port(info(p),name(x),direction(p) * flip(x),type(x))
 
-defn type (s:DefAccessor) -> Type : type(type(source(s)) as VectorType)
-defn size (s:DefMemory) -> Int : size(type(s))
-defn size (s:DefAccessor) -> Int : size(type(source(s)) as VectorType)
+defn get-kind (e:Expression) -> Kind :
+   match(e) :
+      (e:WRef) : kind(e)
+      (e:WSubfield) : get-kind(exp(e))
+      (e:WIndex) : get-kind(exp(e))
+
+defn type (s:DefAccessor) -> Type : 
+   if get-kind(source(s)) == MemKind() : type(source(s))
+   else : type(type(source(s)) as VectorType)
+
 defn base-name (e:Expression) -> Symbol :
    match(e) : 
       (e:WRef) : name(e)
@@ -1044,15 +1051,15 @@ defn lower (body:Stmt) -> Stmt :
             for x in expand-expr(value(s)) map : 
                DefNode(info(s),name(s),exp(x))
          (s:DefMemory) : Begin $ 
-            for x in generate-entry(name(s),type(type(s))) map :
-               DefMemory(info(s),name(x),VectorType(type(x),size(s)),seq?(s),clock(s))
+            for x in generate-entry(name(s),type(s)) map :
+               DefMemory(info(s),name(x),type(x),seq?(s),clock(s),size(s))
          (s:DefAccessor) : 
             val ls = generate-entry(name(s),type(s))
             val rs = generate-entry(name(source(s) as WRef),type(s))
             val index* = exp(head $ expand-expr(index(s)))
             Begin $ for (l in ls, r in rs) map:
                if flip(r) == REVERSE : error("Shouldn't be here")
-               val memref = WRef(name(r),VectorType(type(r),size(s)),MemKind(),gender(s))
+               val memref = WRef(name(r),type(r),MemKind(),gender(s))
                DefAccessor(info(s),name(l),memref,index*,to-acc-dir(gender(s)))
          (s:OnReset|Connect) : Begin $
             for (l in expand-expr(loc(s)), r in expand-expr(exp(s))) map :
@@ -1587,7 +1594,7 @@ public defn expand-whens (c:Circuit) -> Circuit :
                (e:False) : false
          (s:DefAccessor) : 
             add(decs,s)
-            val t = type(type(source(s)) as VectorType)
+            val t = type(s)
             val n = name(s)
             if gender(s) == FEMALE :
                val ref = WRef(n,t,WriteAccessorKind(),FEMALE)
@@ -1954,7 +1961,7 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod
          (s:DefRegister) : DefRegister(info(s),name(s),h[name(s)],gen-constraints(clock(s)),gen-constraints(reset(s)))
          (s:DefAccessor) : DefAccessor(info(s),name(s),gen-constraints(source(s)),gen-constraints(index(s)), acc-dir(s))
          (s:DefInstance) : DefInstance(info(s),name(s),gen-constraints(module(s)))
-         (s:DefMemory) : DefMemory(info(s),name(s),h[name(s)] as VectorType,seq?(s),gen-constraints(clock(s)))
+         (s:DefMemory) : DefMemory(info(s),name(s),h[name(s)],seq?(s),gen-constraints(clock(s)),size(s))
          (s:DefNode) : 
             val l = h[name(s)]
             val r = gen-constraints(value(s))
@@ -2009,7 +2016,7 @@ defn build-environment (c:Circuit,m:Module,h:HashTable<Symbol,Type>) -> HashTabl
          (s:DefRegister) : h[name(s)] = remove-unknowns(type(s))
          (s:DefInstance) : h[name(s)] = h[name(module(s) as WRef)]
          (s:DefMemory) : h[name(s)] = remove-unknowns(type(s))
-         (s:DefAccessor) : h[name(s)] = remove-unknowns(type(type(source(s)) as VectorType))
+         (s:DefAccessor) : h[name(s)] = remove-unknowns(type(s))
          (s:DefNode) : h[name(s)] = remove-unknowns(type(value(s)))
          (s) : false
       do(build-environment,s)
@@ -2161,7 +2168,7 @@ defn inline-instances (c:Circuit) :
          (s:DefPoison) : DefPoison(info(s),rename(name(s),n),type(s))
          (s:DefRegister) : DefRegister(info(s),rename(name(s),n),type(s),clock(s),reset(s))
          (s:DefInstance) : error("Shouldn't be here")
-         (s:DefMemory) : DefMemory(info(s),rename(name(s),n),type(s),seq?(s),clock(s))
+         (s:DefMemory) : DefMemory(info(s),rename(name(s),n),type(s),seq?(s),clock(s),size(s))
          (s:DefNode) : DefNode(info(s),rename(name(s),n),value(s))
          (s) : s
    for m in modules(c) do :
@@ -2315,7 +2322,7 @@ public defn special-rename (original-sym:Symbol,new-sym:Symbol,c:Circuit) :
         (s:DefPoison) : DefPoison(info(s),rename(name(s)),type(s))
         (s:DefRegister) : DefRegister(info(s),rename(name(s)),type(s),clock(s),reset(s))
         (s:DefInstance) : DefInstance(info(s),rename(name(s)),module(s))
-        (s:DefMemory) : DefMemory(info(s),rename(name(s)),type(s),seq?(s),clock(s))
+        (s:DefMemory) : DefMemory(info(s),rename(name(s)),type(s),seq?(s),clock(s),size(s))
         (s:DefNode) : DefNode(info(s),rename(name(s)),value(s))
         (s:DefAccessor) : DefAccessor(info(s),rename(name(s)),source(s),index(s),acc-dir(s))
         (s) : map(to-stmt,s)
diff --git a/src/main/stanza/verilog.stanza b/src/main/stanza/verilog.stanza
index c4a52d5e..fd0407b9 100644
--- a/src/main/stanza/verilog.stanza
+++ b/src/main/stanza/verilog.stanza
@@ -217,10 +217,9 @@ defn emit-module (m:InModule) :
             val w = width!(type(s))
             add(inits,[sym " = " rand-string(w)])
          (s:DefMemory) :
-            val vtype = type(s) as VectorType
-            add(regs,["reg  " get-width(type(vtype)) " " sym " [0:" size(vtype) - 1 "];"])
-            add(inits,["for (initvar = 0; initvar < " size(vtype) "; initvar = initvar+1)"])
-            add(inits,["  " sym "[initvar] = " rand-string(width!(type(vtype))) ])
+            add(regs,["reg  " get-width(type(s)) " " sym " [0:" size(s) - 1 "];"])
+            add(inits,["for (initvar = 0; initvar < " size(s) "; initvar = initvar+1)"])
+            add(inits,["  " sym "[initvar] = " rand-string(width!(type(s))) ])
          (s:DefNode) :
             add(wires,["wire " get-width(type(value(s))) " " sym ";"])
             add(assigns,["assign " sym " = " emit(value(s)) ";"])
@@ -248,11 +247,11 @@ defn emit-module (m:InModule) :
                      updates[get-name(clock(mem-declaration))] = my-clk-update
 
                      ; emit read accessor
-                     add(wires,["wire " get-width(type(type(source(s)) as VectorType)) " " sym ";"])
+                     add(wires,["wire " get-width(type(source(s))) " " sym ";"])
                      add(assigns,["assign " sym " = " emit(source(s)) "[" emit(index*) "];"])
                   else :
                      ; emit read accessor
-                     add(wires,["wire " get-width(type(type(source(s)) as VectorType)) " " sym ";"])
+                     add(wires,["wire " get-width(type(source(s))) " " sym ";"])
                      add(assigns,["assign " sym " = " emit(source(s)) "[" emit(index(s)) "];"])
                WRITE : 
                   val my-clk-update = get?(updates,get-name(clock(mem-declaration)),Vector<Streamable>())
diff --git a/test/passes/expand-accessors/accessor-mem.fir b/test/passes/expand-accessors/accessor-mem.fir
index 1c055b48..c0ce6475 100644
--- a/test/passes/expand-accessors/accessor-mem.fir
+++ b/test/passes/expand-accessors/accessor-mem.fir
@@ -21,3 +21,4 @@ circuit top :
       z := j
 
 ; CHECK: Finished Expand Accessors
+; CHECK: Done!