Updated flo backend

5 files changed, 83 insertions, 60 deletions

diff --git a/TODO b/TODO
index c881509d..edc3fe17 100644
--- a/TODO
+++ b/TODO
@@ -6,13 +6,15 @@
 Add/Update Unit Tests for each pass
    Check after each pass
    write test that checks instance types are correctly lowered
-error on uninitialized wires
+fix expand-whens to have correct semantics
 ensure module names are unique
 add check that limits size of width of dshl
 add efficient prefix checker 
-Change to new low firrtl
+update high/low firrtl checks
 add clock type
 add clock, reset to reg, mem etc
+need a multi-clock domain example
+need an annotation example
 change parser to accept subword, but error
 
 move width inference earlier
diff --git a/src/main/stanza/compilers.stanza b/src/main/stanza/compilers.stanza
index a3b04a94..2f6329dc 100644
--- a/src/main/stanza/compilers.stanza
+++ b/src/main/stanza/compilers.stanza
@@ -3,40 +3,40 @@ defpackage firrtl/compiler :
   import verse
   import firrtl/passes
   import firrtl/errors
-;  import firrtl/flo
+  import firrtl/flo
   import firrtl/verilog
   import firrtl/ir2
   import firrtl/ir-utils
 
-;public defstruct StandardFlo <: Compiler :
-;   file: String with: (as-method => true)
-;public defmethod passes (c:StandardFlo) -> List<Pass> :
-;   to-list $ [
-;      CheckHighForm(expand-delin)
-;      ;; TempElimination()
-;      ToWorkingIR()
-;      MakeExplicitReset()
-;      ResolveKinds()
-;      CheckKinds()
-;      InferTypes()
-;      CheckTypes()
-;      ResolveGenders()
-;      CheckGenders()
-;      ExpandAccessors()
-;      LowerToGround()
-;      ExpandIndexedConnects()
-;      ExpandWhens()
-;      InferWidths()
-;      Pad()
-;      Inline()
-;      SplitExp()
-;      ToRealIR()
-;      SpecialRename(`#,`_)
-;      SpecialRename(`$,`::)
-;      CheckHighForm(`::)
-;      CheckLowForm()
-;      Flo(file(c))
-;   ]
+public defstruct StandardFlo <: Compiler :
+   file: String with: (as-method => true)
+public defmethod passes (c:StandardFlo) -> List<Pass> :
+   to-list $ [
+      CheckHighForm(expand-delin)
+      ;; TempElimination()
+      ToWorkingIR()
+      MakeExplicitReset()
+      ResolveKinds()
+      CheckKinds()
+      InferTypes()
+      CheckTypes()
+      ResolveGenders()
+      CheckGenders()
+      ExpandAccessors()
+      LowerToGround()
+      ExpandIndexedConnects()
+      ExpandWhens()
+      InferWidths()
+      Pad()
+      Inline()
+      SplitExp()
+      ToRealIR()
+      SpecialRename(`#,`_)
+      SpecialRename(`$,`::)
+      CheckHighForm(`::)
+      CheckLowForm()
+      Flo(file(c))
+   ]
 
 public defstruct StandardVerilog <: Compiler :
    file: String with: (as-method => true)
diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza
index 374fe438..beb288b1 100644
--- a/src/main/stanza/firrtl-test-main.stanza
+++ b/src/main/stanza/firrtl-test-main.stanza
@@ -11,7 +11,7 @@
 #include("primop.stanza")
 #include("errors.stanza")
 #include("compilers.stanza")
-;#include("flo.stanza")
+#include("flo.stanza")
 #include("verilog.stanza")
 
 ;Custom Packages
@@ -80,8 +80,7 @@ defn main () :
       run-passes(c,get-passes(to-list(pass-names)))
    else :
       switch {_ == compiler} :
-         ;"flo" : run-passes(c,StandardFlo(output as String))
-         "flo" : run-passes(c,StandardVerilog(output as String))
+         "flo" : run-passes(c,StandardFlo(output as String))
          "verilog" : run-passes(c,StandardVerilog(output as String))
          "verilute" : run-passes(c,InstrumentedVerilog(output as String,to-list $ pass-args))
          else : error("Invalid compiler flag")
diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza
index cf15638d..9f4cdc8c 100644
--- a/src/main/stanza/flo.stanza
+++ b/src/main/stanza/flo.stanza
@@ -11,8 +11,16 @@ public defstruct Flo <: Pass :
    file : String
 public defmethod pass (b:Flo) -> (Circuit -> Circuit) : emit-flo{file(b),_}
 public defmethod name (b:Flo) -> String : "To Flo"
+
+definterface FloKind
+defstruct FRegKind <: FloKind
+defstruct FWritePortKind <: FloKind :
+   mem: Expression
+   index: Expression
+defstruct FOutputPortKind <: FloKind 
   
 defn is-sint? (arg:Expression) -> True|False : type(arg) typeof SIntType
+defn type (s:DefAccessor) -> Type : type(type(source(s)) as VectorType)
 
 defn flo-op-name (op:PrimOp, args:List<Expression>) -> String :
    switch {op == _ } :
@@ -94,12 +102,6 @@ defn emit! (e:Expression,top:Symbol) :
       (e:SIntValue) : emit-all([value(e) "'" sane-width(width(e))], top)
       (e:Subfield) :  emit-all([exp(e) "/" name(e)], top)
       (e:Index) :     emit-all([exp(e) "/" value(e)], top)
-      ;(e:Pad) : 
-         ;emit-all(["rsh'" prim-width(type(e)) " " value(e) " 0"], top)
-      (e:Register) : 
-         emit-all(["reg'" prim-width(type(e)) " " enable(e) " " value(e)], top) 
-      (e:ReadPort) : 
-         emit-all(["rd'" prim-width(type(e)) " " "1" " " mem(e) " " index(e)], top) ;; enable(e)
       (e:DoPrim) : 
          if cmp-op?(op(e)) :
            emit-all([flo-op-name(op(e), args(e)) "'" prim-width(type(args(e)[0]))], top)
@@ -137,41 +139,60 @@ defn maybe-mov (e:Expression) -> String :
       (e) :           false
    if need-mov?: "mov " else: ""
 
-defn emit-s (s:Stmt, v:List<Symbol>, top:Symbol,sh:HashTable<Symbol,Int>) :
+defn emit-s (s:Stmt, flokinds:HashTable<Symbol,FloKind>, top:Symbol,sh:HashTable<Symbol,Int>) :
+   defn emit-connect (s:Connect, en:Expression) :
+      match(loc(s)) :
+        (r:Ref) :
+           val n = name(r)
+           if key?(flokinds,n) :
+              match(flokinds[n]) :
+                 (k:FRegKind) : 
+                    emit-all(["reg'" prim-width(type(r)) " " en " " exp(s)], top) 
+                 (k:FWritePortKind) :
+                    emit-all([top "::" n " = wr'" prim-width(type(r)) " " en " " mem(k) " " index(k) " " exp(s) "\n"], top)
+                 (k:FOutputPortKind) : 
+                    emit-all([top "::" n " = out'" prim-width(type(r)) " " exp(s) "\n"], top)
+                 (k) : error("Shouldn't be here")
+           else :
+              emit-all([top "::" n " = " maybe-mov(exp(s)) exp(s) "\n"], top)
+        (o) :
+           println-all(["CONNEcT LOC " loc(s)])
+           error("Unknown Connect")
    match(s) :
       (s:DefWire) : ""
       (s:DefInstance) : error("Shouldn't be here")
+      (e:DefAccessor) : 
+         if acc-dir == READ :
+            emit-all(["rd'" prim-width(type(e)) " " "1" " " source(e) " " index(e)], top)
       (s:DefMemory) :
          val vtype = type(s) as VectorType
          emit-all([top "::" name(s) " = mem'" prim-width(type(vtype)) " " size(vtype) "\n"], top)
       (s:DefNode) :
          emit-all([top "::" name(s) " = " maybe-mov(value(s)) value(s) "\n"], top)
-      (s:Begin) : do(emit-s{_, v, top,sh}, body(s))
-      (s:Connect) : 
-         match(loc(s)) :
-           (r:Ref) :
-             val n = name(r)
-             if contains?(v,n) :
-                emit-all([top "::" n " = out'" prim-width(type(r)) " " exp(s) "\n"], top)
-             else :
-                emit-all([top "::" n " = " maybe-mov(exp(s)) exp(s) "\n"], top)
-           (w:WritePort) :
-             val n = firrtl-gensym(`F,sh)
-             emit-all([top "::" n " = wr'" prim-width(type(w)) " " enable(w) " " mem(w) " " index(w) " " exp(s) "\n"], top)
-           (o) :
-             println-all(["CONNEcT LOC " loc(s)])
-             error("Unknown Connect")
+      (s:Begin) : do(emit-s{_, flokinds, top,sh}, body(s))
+      (s:Connect) : emit-connect(s,UIntValue(to-long(1),IntWidth(1)))
+      (s:Conditionally) : emit-connect(conseq(s) as Connect,pred(s))
       (s) : s 
 
 defn emit-module (m:InModule,sh:HashTable<Symbol,Int>) :
-   val v = Vector<Symbol>()
+   val flokinds = HashTable<Symbol,FloKind>(symbol-hash)
+   defn build-table (s:Stmt) -> False :
+      do(build-table,s)
+      match(s) : 
+         (s:DefRegister) : flokinds[name(s)] = FRegKind()
+         (s:DefAccessor) : 
+            switch {_ == acc-dir(s)} :
+               WRITE : flokinds[name(s)] = FWritePortKind(source(s),index(s))
+               else : false
+         (s) : false
+      
    for port in ports(m) do :
       if name(port) ==`reset :
          emit-all([name(m) "::" name(port) " = rst'1\n"], name(m))
       else : switch {_ == direction(port)} :
          INPUT : print-all([name(m) "::" name(port) " = " "in'" prim-width(type(port)) "\n"])
-         OUTPUT : add(v,name(port))
-   emit-s(body(m), to-list(v), name(m),sh)
+         OUTPUT : flokinds[name(port)] = FOutputPortKind()
+   emit-s(body(m), flokinds, name(m),sh)
 
 public defn emit-flo (file:String, c:Circuit) :
    with-output-file{file, _} $ fn () :
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index ed3f0079..43cc06a4 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1867,6 +1867,7 @@ defn inline-instances (c:Circuit) :
    defn rename-s (s:Stmt,n:Symbol) -> Stmt :
       map{rename-e{_,n},_} $ match(map(rename-s{_,n},s)) :
          (s:DefWire) : DefWire(info(s),rename(name(s),n),type(s))
+         (s:DefRegister) : DefRegister(info(s),rename(name(s),n),type(s))
          (s:DefInstance) : error("Shouldn't be here")
          (s:DefMemory) : DefMemory(info(s),rename(name(s),n),type(s),seq?(s))
          (s:DefNode) : DefNode(info(s),rename(name(s),n),value(s))