diff options
| author | sinofp | 2021-07-11 15:13:06 +0800 |
|---|---|---|
| committer | GitHub | 2021-07-11 07:13:06 +0000 |
| commit | 92e8bf46117920adbe9679f4c52da58af3416131 (patch) | |
| tree | 3c75fde406735dd9b4c01b738c7711deb5e886ee | |
| parent | df9245e76020f8f7b6e19df2f71721ea1d98bd9d (diff) | |
Rm java.io in WriteEmitted (#2275)
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
| -rw-r--r-- | src/main/scala/firrtl/stage/phases/WriteEmitted.scala | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/src/main/scala/firrtl/stage/phases/WriteEmitted.scala b/src/main/scala/firrtl/stage/phases/WriteEmitted.scala index 010e85c3..90b0e123 100644 --- a/src/main/scala/firrtl/stage/phases/WriteEmitted.scala +++ b/src/main/scala/firrtl/stage/phases/WriteEmitted.scala @@ -2,7 +2,7 @@ package firrtl.stage.phases -import firrtl.{AnnotationSeq, EmittedCircuitAnnotation, EmittedModuleAnnotation} +import firrtl.{AnnotationSeq, EmittedCircuitAnnotation, EmittedModuleAnnotation, FileUtils} import firrtl.options.{Phase, StageOptions, Viewer} import firrtl.stage.FirrtlOptions @@ -44,16 +44,14 @@ class WriteEmitted extends Phase { annotations.flatMap { case a: EmittedModuleAnnotation[_] => - val pw = new PrintWriter(sopts.getBuildFileName(a.value.name, Some(a.value.outputSuffix))) - pw.write(a.value.value) - pw.close() + val target = FileUtils.getPath(sopts.getBuildFileName(a.value.name, Some(a.value.outputSuffix))) + os.write(target, a.value.value) None case a: EmittedCircuitAnnotation[_] => - val pw = new PrintWriter( + val target = FileUtils.getPath( sopts.getBuildFileName(fopts.outputFileName.getOrElse(a.value.name), Some(a.value.outputSuffix)) ) - pw.write(a.value.value) - pw.close() + os.write(target, a.value.value) None case a => Some(a) } |
