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authorazidar2015-04-23 11:43:11 -0700
committerazidar2015-04-23 11:43:11 -0700
commit7f8758420a2a46d7cf19441e9fbd1dba82cae612 (patch)
tree1508e1676f56c202f2021971241529b73db19bae
parenta4f7aa2b81a021f21a49bd4059d051bc0f949880 (diff)
Fixed Pad inference bug
-rw-r--r--TODO8
-rw-r--r--src/main/stanza/passes.stanza2
-rw-r--r--test/passes/jacktest/gcd2.fir26
3 files changed, 33 insertions, 3 deletions
diff --git a/TODO b/TODO
index 4a099d94..818b78c3 100644
--- a/TODO
+++ b/TODO
@@ -7,8 +7,6 @@ on-reset
Parser
Error if incorrectly assign stuff, like use = instead of :=
Update parser and update tests
-Change all primops to be strict on data widths
-Add pad!
Make instances always male, flip the bundles on declaration
dlsh,drsh
move Infer-Widths to before vec expansion?
@@ -32,6 +30,12 @@ Well-formed high firrtl
After adding dynamic assertions, insert bounds check with accessor expansion
Well-formed low firrtl
All things only assigned to once
+Width inference
+ No names
+ No Unknowns
+ All widths are positive
+ Pad's width is greater than value's width
+ pad's width is greater than value's width
======== Other Passes ========
constant folding (partial eval) pass
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 588b4b73..50d2831a 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -1584,7 +1584,7 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod
(e:Pad) :
val value-w = width!(value(e))
val pad-w = remove-unknowns-w(width(e))
- ;add(v,WGeq(pad-w, IntWidth(0)))
+ add(v,WGeq(pad-w, value-w))
val pad-t = match(type(e)) :
(t:UIntType) : UIntType(pad-w)
(t:SIntType) : SIntType(pad-w)
diff --git a/test/passes/jacktest/gcd2.fir b/test/passes/jacktest/gcd2.fir
new file mode 100644
index 00000000..e6700122
--- /dev/null
+++ b/test/passes/jacktest/gcd2.fir
@@ -0,0 +1,26 @@
+; RUN: firrtl -i %s -o %s.flo -x X -p cTwd | tee %s.out | FileCheck %s
+;CHECK: To Flo
+circuit GCD :
+ module GCD :
+ input b : UInt(16)
+ input a : UInt(16)
+ input e : UInt(1)
+ output z : UInt(16)
+ output v : UInt(1)
+
+ reg x : UInt(16)
+ reg y : UInt(16)
+ node T_17 = gt(Pad(x,?), Pad(y,?))
+ when T_17 :
+ node T_18 = sub-wrap(Pad(x,?), Pad(y,?))
+ x := T_18
+ else :
+ node T_19 = sub-wrap(Pad(y,?), Pad(x,?))
+ y := T_19
+ when e :
+ x := a
+ y := b
+ z := x
+ node T_20 = UInt(0, 1)
+ node T_21 = eq(Pad(y,?), Pad(T_20,?))
+ v := T_21