Fixed bug in lowering of subfields. Fixed ModuleVec.fir to be correct

2 files changed, 27 insertions, 30 deletions

diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 0b586080..453a8181 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -712,12 +712,17 @@ defn expand-expr (e:Expression) -> List<EF> :
             for x in generate-entry(name(f),type(f)) map :
                EF(WSubfield(i,name(x),type(x),gender(e)),flip(x))
          else :
-            val b = exp(e)
-            val exps = for x in generate-entry(name(b as WRef),type(b)) map :
-               EF(WRef(name(x),type(x),NodeKind(),gender(e)),DEFAULT)
-            val begin = index-of-elem(type(b) as BundleType,name(e))
+            val exps = expand-expr(exp(e))
+            val begin = index-of-elem(type(exp(e)) as BundleType,name(e))
             val len = num-elems(type(e))
-            headn(tailn(exps,begin),len)
+            val ret = headn(tailn(exps,begin),len)
+            for r in ret map : EF(exp(r),DEFAULT)
+            ;val b =  exp(e)
+            ;val exps = for x in generate-entry(name(b as WRef),type(b)) map :
+               ;EF(WRef(name(x),type(x),NodeKind(),gender(e)),DEFAULT)
+            ;val begin = index-of-elem(type(b) as BundleType,name(e))
+            ;val len = num-elems(type(e))
+            ;headn(tailn(exps,begin),len)
       (e:WIndex) :
          val exps = expand-expr(exp(e))
          val len = num-elems(type(e))
@@ -740,6 +745,11 @@ defn size (s:DefMemory) -> Int : size(type(s))
 defn size (s:WDefAccessor) -> Int : size(type(source(s)) as VectorType)
 defn kind (e:WSubfield) -> Kind : kind(exp(e) as WRef|WSubfield|WIndex)
 defn kind (e:WIndex) -> Kind : kind(exp(e) as WRef|WSubfield|WIndex)
+defn base-name (e:Expression) -> Symbol :
+   match(e) : 
+      (e:WRef) : name(e)
+      (e:WSubfield) : base-name(exp(e))
+      (e:WIndex) : base-name(exp(e))
 
 defn set-gender (e:Expression,g:Gender,f:Flip) -> Expression :
    match(e) : 
@@ -749,18 +759,6 @@ defn set-gender (e:Expression,g:Gender,f:Flip) -> Expression :
 
 defn lower (body:Stmt) -> Stmt :
    defn lower-stmt (s:Stmt) -> Stmt :
-      defn calc-gender (g:Gender, e:Expression) -> Gender :
-         match(e) :
-            (e:WRef) : gender(e)
-            (e:WSubfield) : 
-               println-all-debug(["Calc gender. " g " with " e])
-               println-all-debug(["Exp: " exp(e)])
-               val flip = bundle-field-flip(name(e),type(exp(e)))
-               println-all-debug(["Flip: " flip])
-               calc-gender(flip * g,exp(e))
-            (e:WIndex) : gender(e)
-            (e) : g
-
       println(s)
       match(s) :
          (s:DefWire) : Begin $
@@ -1974,5 +1972,4 @@ public defn run-passes (c: Circuit, p: List<Char>,file:String) :
    if contains(p,'X') or contains(p,'n') : do-stage("Split Expressions", split-exp)
    if contains(p,'X') or contains(p,'o') : do-stage("Real IR", to-real-ir)
    if contains(p,'X') or contains(p,'F') : do-stage("To Flo", emit-flo{file,_})
-
    println("Done!")
diff --git a/test/chisel3/ModuleVec.fir b/test/chisel3/ModuleVec.fir
index 7379024b..a4617267 100644
--- a/test/chisel3/ModuleVec.fir
+++ b/test/chisel3/ModuleVec.fir
@@ -6,25 +6,25 @@ circuit ModuleVec :
     output out : UInt<32>
     
     node T_33 = UInt<1>(1)
-    node T_34 = add(in, T_33)
-    out := T_34
+    node T_34 = add-wrap(Pad(in,?), Pad(T_33,?))
+    out := Pad(T_34,?)
   module PlusOne_25 : 
     input in : UInt<32>
     output out : UInt<32>
     
     node T_35 = UInt<1>(1)
-    node T_36 = add(in, T_35)
-    out := T_36
+    node T_36 = add-wrap(Pad(in,?), Pad(T_35,?))
+    out := Pad(T_36,?)
   module ModuleVec : 
-    output ins : UInt<32>[2]
+    input ins : UInt<32>[2]
     output outs : UInt<32>[2]
     
     inst T_37 of PlusOne
     inst T_38 of PlusOne_25
-    wire pluses : {flip in : UInt<32>, out : UInt<32>}[2]
-    pluses[0] := T_37
-    pluses[1] := T_38
-    pluses.s.in := ins.s
-    outs[0] := pluses.s.out
-    pluses.s.in := ins[1]
-    outs[1] := pluses[1].out
+    wire pluses : { in : UInt<32>, flip out : UInt<32>}[2]
+    pluses[0] := Pad(T_37,?)
+    pluses[1] := Pad(T_38,?)
+    pluses[0].in := Pad(ins[0],?)
+    outs[0] := Pad(pluses[0].out,?)
+    pluses[1].in := Pad(ins[1],?)
+    outs[1] := Pad(pluses[1].out,?)