Fix Serializer for single indented DefModule emission (#2332)

2 files changed, 64 insertions, 6 deletions

diff --git a/src/main/scala/firrtl/ir/Serializer.scala b/src/main/scala/firrtl/ir/Serializer.scala
index 1c2bfc82..f5457dea 100644
--- a/src/main/scala/firrtl/ir/Serializer.scala
+++ b/src/main/scala/firrtl/ir/Serializer.scala
@@ -240,24 +240,24 @@ object Serializer {
 
   private def s(node: DefModule)(implicit b: StringBuilder, indent: Int): Unit = node match {
     case Module(info, name, ports, body) =>
-      b ++= "module "; b ++= name; b ++= " :"; s(info)
+      doIndent(0); b ++= "module "; b ++= name; b ++= " :"; s(info)
       ports.foreach { p => newLineAndIndent(1); s(p) }
       newLineNoIndent() // add a new line between port declaration and body
       newLineAndIndent(1); s(body)(b, indent + 1)
     case ExtModule(info, name, ports, defname, params) =>
-      b ++= "extmodule "; b ++= name; b ++= " :"; s(info)
+      doIndent(0); b ++= "extmodule "; b ++= name; b ++= " :"; s(info)
       ports.foreach { p => newLineAndIndent(1); s(p) }
       newLineAndIndent(1); b ++= "defname = "; b ++= defname
       params.foreach { p => newLineAndIndent(1); s(p) }
-    case other => b ++= other.serialize // Handle user-defined nodes
+    case other => doIndent(0); b ++= other.serialize // Handle user-defined nodes
   }
 
   private def s(node: Circuit)(implicit b: StringBuilder, indent: Int): Unit = node match {
     case Circuit(info, modules, main) =>
       b ++= "circuit "; b ++= main; b ++= " :"; s(info)
       if (modules.nonEmpty) {
-        newLineAndIndent(1); s(modules.head)(b, indent + 1)
-        modules.drop(1).foreach { m => newLineNoIndent(); newLineAndIndent(1); s(m)(b, indent + 1) }
+        newLineNoIndent(); s(modules.head)(b, indent + 1)
+        modules.drop(1).foreach { m => newLineNoIndent(); newLineNoIndent(); s(m)(b, indent + 1) }
       }
       newLineNoIndent()
   }
diff --git a/src/test/scala/firrtlTests/SerializerSpec.scala b/src/test/scala/firrtlTests/SerializerSpec.scala
index e8245872..aae0ff1f 100644
--- a/src/test/scala/firrtlTests/SerializerSpec.scala
+++ b/src/test/scala/firrtlTests/SerializerSpec.scala
@@ -4,7 +4,7 @@ package firrtlTests
 
 import org.scalatest._
 import firrtl.ir._
-import firrtl.Utils
+import firrtl.{Parser, Utils}
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 
@@ -33,6 +33,37 @@ object SerializerSpec {
     def mapType(f:      Type => Type):             Expression = this.copy(expr.mapType(f))
     def mapWidth(f:     Width => Width):           Expression = this.copy(expr.mapWidth(f))
   }
+
+  private def tab(s: String): String = {
+    // Careful to only tab non-empty lines
+    s.split("\n")
+      .map { line =>
+        if (line.nonEmpty) Serializer.Indent + line else line
+      }
+      .mkString("\n")
+  }
+
+  val testModule: String =
+    """module test :
+      |  input in : UInt<8>
+      |  output out : UInt<8>
+      |
+      |  inst c of child
+      |  c.in <= in
+      |  out <= c.out""".stripMargin
+
+  val testModuleTabbed: String = tab(testModule)
+
+  val childModule: String =
+    """extmodule child :
+      |  input in : UInt<8>
+      |  output out : UInt<8>
+      |  defname = child""".stripMargin
+
+  val childModuleTabbed: String = tab(childModule)
+
+  val simpleCircuit: String =
+    "circuit test :\n" + childModuleTabbed + "\n\n" + testModuleTabbed + "\n"
 }
 
 class SerializerSpec extends AnyFlatSpec with Matchers {
@@ -58,4 +89,31 @@ class SerializerSpec extends AnyFlatSpec with Matchers {
     Serializer.serialize(stmts) should be(ser)
   }
 
+  it should "support emitting circuits" in {
+    val parsed = Parser.parse(simpleCircuit)
+    val serialized = Serializer.serialize(parsed)
+    serialized should be(simpleCircuit)
+  }
+
+  it should "support emitting individual modules" in {
+    val parsed = Parser.parse(simpleCircuit)
+    val m = parsed.modules.find(_.name == "test").get
+    val serialized = Serializer.serialize(m)
+    serialized should be(testModule)
+  }
+
+  it should "support emitting indented individual modules" in {
+    val parsed = Parser.parse(simpleCircuit)
+    val m = parsed.modules.find(_.name == "test").get
+    val serialized = Serializer.serialize(m, 1)
+    serialized should be(testModuleTabbed)
+  }
+
+  it should "support emitting indented individual extmodules" in {
+    val parsed = Parser.parse(simpleCircuit)
+    val m = parsed.modules.find(_.name == "child").get
+    val serialized = Serializer.serialize(m, 1)
+    serialized should be(childModuleTabbed)
+  }
+
 }