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authorjackkoenig2016-05-11 23:38:37 -0700
committerjackkoenig2016-05-11 23:38:37 -0700
commit6d72dfbb50a9ccd7944b90d509d9796704aa69a9 (patch)
treeb7161ca42cc23fd9fb2e5868de313ebdbd75b75b
parenta73efa2f67428101cf0984a8fb8ac3ebf32b914b (diff)
Remove trait StanzaPass and related dead code
-rw-r--r--src/main/scala/firrtl/passes/Checks.scala2
-rw-r--r--src/main/scala/firrtl/passes/Passes.scala41
2 files changed, 1 insertions, 42 deletions
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 4b799f41..618c0e99 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -677,7 +677,7 @@ object CheckGenders extends Pass {
}
}
-object CheckWidths extends Pass with StanzaPass {
+object CheckWidths extends Pass {
def name = "Width Check"
var mname = ""
class UninferredWidth (info:Info) extends PassException(s"${info} : [module ${mname}] Uninferred width.")
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index 5401d0b2..8ccfb0b0 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -30,10 +30,6 @@ package firrtl.passes
import com.typesafe.scalalogging.LazyLogging
import java.nio.file.{Paths, Files}
-// For calling Stanza
-import scala.sys.process._
-import scala.io.Source
-
// Datastructures
import scala.collection.mutable.LinkedHashMap
import scala.collection.mutable.HashMap
@@ -55,28 +51,6 @@ trait Pass extends LazyLogging {
class PassException(message: String) extends Exception(message)
class PassExceptions(exceptions: Seq[PassException]) extends Exception("\n" + exceptions.mkString("\n"))
-// Trait for migration, trap to Stanza implementation for passes not yet implemented in Scala
-trait StanzaPass extends LazyLogging {
- def stanzaPass(c: Circuit, n: String): Circuit = {
- // For migration from Stanza, handle unimplemented Passes
- logger.debug(s"Pass ${n} is not yet implemented in Scala")
- val stanzaPasses = Seq("resolve", n)
- val toStanza = Files.createTempFile(Paths.get(""), n, ".fir")
- val fromStanza = Files.createTempFile(Paths.get(""), n, ".fir")
- Files.write(toStanza, c.serialize.getBytes)
-
- val cmd = Seq("firrtl-stanza", "-i", toStanza.toString, "-o", fromStanza.toString, "-b", "firrtl", "-p", "c") ++
- stanzaPasses.flatMap(x=>Seq("-x", x))
- logger.debug(cmd.mkString(" "))
- val ret = cmd.!
- //println(ret)
- val newC = Parser.parse(fromStanza.toString, Source.fromFile(fromStanza.toString).getLines)
- Files.delete(toStanza)
- Files.delete(fromStanza)
- newC
- }
-}
-
object PassUtils extends LazyLogging {
val listOfPasses: Seq[Pass] = Seq(ToWorkingIR,ResolveKinds,InferTypes,ResolveGenders,InferWidths,PullMuxes,ExpandConnects,RemoveAccesses,ExpandWhens,LowerTypes)
lazy val mapNameToPass: Map[String, Pass] = listOfPasses.map(p => p.name -> p).toMap
@@ -122,11 +96,6 @@ object ToWorkingIR extends Pass {
}
}
-object Resolve extends Pass with StanzaPass {
- def name = "Resolve"
- def run (c:Circuit): Circuit = stanzaPass(c, "resolve")
-}
-
object ResolveKinds extends Pass {
private var mname = ""
def name = "Resolve Kinds"
@@ -985,16 +954,6 @@ object Legalize extends Pass {
}
}
-object LoToVerilog extends Pass with StanzaPass {
- def name = "Lo To Verilog"
- def run (c:Circuit): Circuit = stanzaPass(c, "lo-to-verilog")
-}
-
-object FromCHIRRTL extends Pass with StanzaPass {
- def name = "From CHIRRTL"
- def run (c:Circuit): Circuit = stanzaPass(c, "from-chirrtl")
-}
-
object VerilogWrap extends Pass {
def name = "Verilog Wrap"
var mname = ""