Fixed bug in lowering where the arguments to DoPrim and Pad weren't lowered

3 files changed, 44 insertions, 1 deletions

diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index a80c2d7e..91e49123 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -300,7 +300,7 @@ defmethod map (f: Type -> Type, c:Stmt) -> Stmt :
    match(c) :
       (c:DefWire) : DefWire(name(c),f(type(c)))
       (c:DefRegister) : DefRegister(name(c),f(type(c)))
-      (c:DefMemory) : DefMemory(name(c),f(type(c)))
+      (c:DefMemory) : DefMemory(name(c),f(type(c)) as VectorType)
       (c) : c
 
 public defmulti mapr<?T> (f: Width -> Width, t:?T&Type) -> T
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 50d2831a..6c347dff 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -789,6 +789,12 @@ defn lower (body:Stmt, table:HashTable<Symbol,List<KeyValue<Expression,Flip>>>)
             val exps = expand-expr(exp(e))
             val len = num-elems(type(e))
             headn(tailn(exps,len * value(e)),len)
+         (e:Pad) : 
+            val v = key(expand-expr(value(e))[0])
+            list(KeyValue(Pad(v,width(e),type(e)),DEFAULT))
+         (e:DoPrim) :
+            val args = for x in args(e) map : key(expand-expr(x)[0])
+            list(KeyValue(DoPrim(op(e),args,consts(e),type(e)),DEFAULT))
          (e) : list(KeyValue(e, DEFAULT))
 
    ;println-debug(table)
diff --git a/test/passes/jacktest/RegisterVecShift.fir b/test/passes/jacktest/RegisterVecShift.fir
new file mode 100644
index 00000000..733e2036
--- /dev/null
+++ b/test/passes/jacktest/RegisterVecShift.fir
@@ -0,0 +1,37 @@
+; RUN: firrtl -i %s -o %s.flo -x X -p cd | tee %s.out | FileCheck %s
+; CHECK: Done!
+
+circuit RegisterVecShift : 
+  module RegisterVecShift : 
+    input load : UInt(1)
+    output out : UInt(4)
+    input shift : UInt(1)
+    input ins : UInt(4)[4]
+    
+    reg delays : UInt(4)[4]
+    when reset : 
+      node T_38 = UInt(0, 4)
+      node T_39 = UInt(0, 4)
+      node T_40 = UInt(0, 4)
+      node T_41 = UInt(0, 4)
+      wire T_42 : UInt(4)[4]
+      T_42.0 := T_38
+      T_42.1 := T_39
+      T_42.2 := T_40
+      T_42.3 := T_41
+      delays := T_42
+    node T_43 = UInt(5, 3)
+    node T_44 = bit-and(Pad(T_43,?), Pad(load,?))
+    node T_45 = UInt(4, 3)
+    node T_46 = eq(Pad(T_44,?), Pad(T_45,?))
+    when T_46 : 
+      delays.0 := Pad(ins.0,?)
+      delays.1 := Pad(ins.1,?)
+      delays.2 := Pad(ins.2,?)
+      delays.3 := Pad(ins.3,?)
+    else : when shift : 
+        delays.0 := Pad(ins.0,?)
+        delays.1 := Pad(delays.0,?)
+        delays.2 := Pad(delays.1,?)
+        delays.3 := Pad(delays.2,?)
+    out := Pad(delays.3,?)