Changed reg syntax to new "with" semantics in Scala FIRRTL

3 files changed, 7 insertions, 4 deletions

diff --git a/src/main/antlr4/FIRRTL.g4 b/src/main/antlr4/FIRRTL.g4
index 9d186762..2faef4e0 100644
--- a/src/main/antlr4/FIRRTL.g4
+++ b/src/main/antlr4/FIRRTL.g4
@@ -46,7 +46,7 @@ block
 
 stmt
   : 'wire' id ':' type
-  | 'reg' id ':' type exp (exp exp)?
+  | 'reg' id ':' type exp ('with' ':' '{' 'reset' '=>' '(' exp exp ')' '}')?
   | 'mem' id ':' '{' ( 'data-type' '=>' type 
                      | 'depth' '=>' IntLit
                      | 'read-latency' '=>' IntLit
@@ -97,6 +97,8 @@ id
 keyword
   : dir
   | 'inst'  
+  | 'mem'
+  | 'reset'
   ;
 
 // Parentheses are added as part of name because semantics require no space between primop and open parentheses
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index fdd71f8f..1a6a7725 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -135,7 +135,8 @@ object Utils {
       var ret = stmt match {
         case w: DefWire => s"wire ${w.name} : ${w.tpe.serialize}"
         case r: DefRegister => 
-          s"reg ${r.name} : ${r.tpe.serialize}, ${r.clock.serialize}, ${r.reset.serialize}, ${r.init.serialize}"
+          s"reg ${r.name} : ${r.tpe.serialize}, ${r.clock.serialize} with : " + 
+          s"(reset => (${r.reset.serialize}, ${r.init.serialize}))"
         case i: DefInstance => s"inst ${i.name} of ${i.module}"
         case m: DefMemory => {
           val str = new StringBuilder(s"mem ${m.name} : " + newline)
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index a026a495..ad8d24f2 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -122,8 +122,8 @@ class Visitor(val fullFilename: String) extends FIRRTLBaseVisitor[AST]
       case "reg"  => {
         val name = ctx.id(0).getText
         val tpe = visitType(ctx.`type`(0))
-        val (reset, init) = if (ctx.getChildCount > 5) (visitExp(ctx.exp(1)), visitExp(ctx.exp(2))) 
-                            else (UIntValue(0, IntWidth(1)), Ref(name, tpe))
+        val reset = if (ctx.exp(1) != null) visitExp(ctx.exp(1)) else UIntValue(0, IntWidth(1))
+        val init  = if (ctx.exp(2) != null) visitExp(ctx.exp(2)) else Ref(name, tpe)
         DefRegister(info, name, tpe, visitExp(ctx.exp(0)), reset, init)
       }
       case "mem" => visitMem(ctx)