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| author | Felix Yan | 2021-06-26 01:33:37 +0800 |
|---|---|---|
| committer | GitHub | 2021-06-25 10:33:37 -0700 |
| commit | 5f8ec8b6459d5116e13a832ee3bad8a2fd0eb5ae (patch) | |
| tree | 12e0bb02f8bb891869876308197005a356acae34 | |
| parent | 11128d93ea5412508b2616fda862abf05a59b435 (diff) | |
Correct a typo in src/main/scala/firrtl/WIR.scala (#2283)
| -rw-r--r-- | src/main/scala/firrtl/WIR.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala index e9dd95bc..6198c29d 100644 --- a/src/main/scala/firrtl/WIR.scala +++ b/src/main/scala/firrtl/WIR.scala @@ -271,7 +271,7 @@ object WrappedType { case (_: IntervalType, _: IntervalType) => true // Analog totally skips out of the Firrtl type system. // The only way Analog can play with another Analog component is through Attach. - // Ohterwise, we'd need to special case it during ExpandWhens, Lowering, + // Otherwise, we'd need to special case it during ExpandWhens, Lowering, // ExpandConnects, etc. case (_: AnalogType, _: AnalogType) => false case (sink: VectorType, source: VectorType) => |