Updated TODO and spec

3 files changed, 21 insertions, 5 deletions

diff --git a/README.md b/README.md
index 939e9790..fd5be0dc 100644
--- a/README.md
+++ b/README.md
@@ -1,7 +1,7 @@
 # firrtl
 #### Flexible Internal Representation for RTL
 
- This repository contains the compiler for .firrtl files.
+ This repository contains the compiler for .fir files.
  It is currently being developed in stanza, with the end-goal to translate into scala for ease of other people to use.
  This decision was made for multiple reasons:  
        1.   Previous development had already been done in stanza   
diff --git a/TODO b/TODO
index aea5144c..332b127d 100644
--- a/TODO
+++ b/TODO
@@ -2,6 +2,7 @@
 TODO 
    Figure out how types and widths propogate for all updated primops
    Write infer-types pass
+   Remove letrec. Add to expressions: Register(input,en), ReadPort(mem,index,enable), WritePort(mem,index,enable)
    Update spec
       change concrete syntactical names of structural elements
       change direction names for bundle fields
@@ -23,6 +24,7 @@ TODO
       What is lowered form? What is it for?
 
 
+
 Tests:
    Error if declare anything other than module in circuit
    Error if incorrectly assign stuff, like use = instead of :=
diff --git a/spec/spec.tex b/spec/spec.tex
index 41838f70..489dce23 100644
--- a/spec/spec.tex
+++ b/spec/spec.tex
@@ -575,9 +575,9 @@ The resultant value of a divide operation has width equal to the width of the di
 \kws{primop} & \kws{Resultant Type} & \kws{Resultant Width} \\
 \kws{mod}(   \pds{op1}, \pds{op2}) & UInt|SInt & width(op1)|width(op2) - 1  \\
 \kws{mod-uu}(\pds{op1}, \pds{op2}) &   UInt & width(op2)     \\
-\kws{mod-us}(\pds{op1}, \pds{op2}) &   SInt & width(op2) - 1?  \\
+\kws{mod-us}(\pds{op1}, \pds{op2}) &   UInt & width(op2) - 1?  \\
 \kws{mod-su}(\pds{op1}, \pds{op2}) &   UInt & width(op2)     \\
-\kws{mod-ss}(\pds{op1}, \pds{op2}) &   SInt & width(op2) - 1?  \\
+\kws{mod-ss}(\pds{op1}, \pds{op2}) &   UInt & width(op2) - 1?  \\
 \end{array}
 \]
 
@@ -671,9 +671,9 @@ The resultant value is a single-bit unsigned integer.
 \[
 \begin{array}{rll}
 \kws{primop} & \kws{Resultant Type} & \kws{Resultant Width} \\
-\kws{equal}  (\pds{op1}, \pds{op2})     & UInt|SInt & 1 \\
+\kws{equal}  (\pds{op1}, \pds{op2})     & UInt & 1 \\
 \kws{equal-u}(\pds{op1}, \pds{op2})     & UInt & 1 \\
-\kws{equal-s}(\pds{op1}, \pds{op2})     & SInt & 1 \\
+\kws{equal-s}(\pds{op1}, \pds{op2})     & UInt & 1 \\
 \end{array}
 \]
 The equality comparison operator accepts either two unsigned or two signed integers and checks whether they are bitwise equivalent.
@@ -761,6 +761,20 @@ The resultant value has the same type as the operand.
 The shift amount must be less than or equal to the width of the operand.
 The output of a shift right operation is equal to the original signal with the least significant $num$ bits truncated, where $num$ is the shift amount.
 
+\subsection{Convert to Signed}
+\[
+\begin{array}{rll}
+\kws{primop} & \kws{Resultant Type} & \kws{Resultant Width} \\
+\pd{convert}        & SInt & width(op)|width(op) + 1 \\
+\pd{convert-u}      & SInt & width(op) + 1 \\
+\pd{convert-s}      & SInt & width(op) \\
+\end{array}
+\]
+The convert operation accepts either an unsigned or a signed integer.
+The resultant value is always a signed integer.
+The output of a convert operation will be the same arithmetic value as the input value.
+The output width is the same as the input width if the input is signed, and increased by one if the input is unsigned.
+
 \subsection{Bitwise Operations}
 \[
 \begin{array}{rll}