CHIRRTL passes work, parser is updated

8 files changed, 655 insertions, 137 deletions

diff --git a/regress/rocket.fir b/regress/rocket.fir
index 0089cd03..debd6af4 100644
--- a/regress/rocket.fir
+++ b/regress/rocket.fir
@@ -11,11 +11,11 @@ circuit Top :
     node T_1212 = bits(rx_shifter, 63, 16)
     node rx_shifter_in = cat(io.host.in.bits, T_1212)
     node next_cmd = bits(rx_shifter_in, 3, 0)
-    reg cmd : UInt<?>, clk
-    reg size : UInt<?>, clk
-    reg pos : UInt<?>, clk
-    reg seqno : UInt<?>, clk
-    reg addr : UInt<?>, clk
+    reg cmd : UInt, clk
+    reg size : UInt, clk
+    reg pos : UInt, clk
+    reg seqno : UInt, clk
+    reg addr : UInt, clk
     node T_1225 = and(io.host.in.valid, io.host.in.ready)
     when T_1225 :
       rx_shifter <= rx_shifter_in
@@ -106,7 +106,7 @@ circuit Top :
     node T_1323 = and(T_1319, T_1322)
     node T_1324 = or(T_1317, T_1323)
     node tx_done = and(T_1316, T_1324)
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     node T_1336 = eq(state, UInt<3>("h04"))
     node T_1337 = and(T_1336, io.mem.acquire.ready)
     node T_1338 = eq(state, UInt<3>("h05"))
@@ -1309,7 +1309,7 @@ circuit Top :
     
     io is invalid
     reg T_3348 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
-    reg T_3350 : UInt<?>, clk with : (reset => (reset, UInt<2>("h02")))
+    reg T_3350 : UInt, clk with : (reset => (reset, UInt<2>("h02")))
     wire T_3352 : UInt<2>
     T_3352 is invalid
     io.out.valid <= io.in[T_3352].valid
@@ -1419,7 +1419,7 @@ circuit Top :
     
     io is invalid
     reg T_3322 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
-    reg T_3324 : UInt<?>, clk with : (reset => (reset, UInt<2>("h02")))
+    reg T_3324 : UInt, clk with : (reset => (reset, UInt<2>("h02")))
     wire T_3326 : UInt<2>
     T_3326 is invalid
     io.out.valid <= io.in[T_3326].valid
@@ -1741,7 +1741,7 @@ circuit Top :
     output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     reg xact : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk
     wire coh : {sharers : UInt<1>}
     coh is invalid
@@ -1952,7 +1952,7 @@ circuit Top :
     output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk
     wire coh : {sharers : UInt<1>}
     coh is invalid
@@ -2809,7 +2809,7 @@ circuit Top :
     output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk
     wire coh : {sharers : UInt<1>}
     coh is invalid
@@ -3666,7 +3666,7 @@ circuit Top :
     output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk
     wire coh : {sharers : UInt<1>}
     coh is invalid
@@ -4523,7 +4523,7 @@ circuit Top :
     output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk
     wire coh : {sharers : UInt<1>}
     coh is invalid
@@ -5380,7 +5380,7 @@ circuit Top :
     output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk
     wire coh : {sharers : UInt<1>}
     coh is invalid
@@ -6237,7 +6237,7 @@ circuit Top :
     output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk
     wire coh : {sharers : UInt<1>}
     coh is invalid
@@ -7094,7 +7094,7 @@ circuit Top :
     output io : {inner : {flip acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>, client_id : UInt<2>}}, grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>, client_id : UInt<2>}}, flip finish : {flip ready : UInt<1>, valid : UInt<1>, bits : {manager_xact_id : UInt<4>}}, probe : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_id : UInt<2>}}, flip release : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<4>, client_id : UInt<2>}}}, flip incoherent : UInt<1>[1], outer : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<4>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<4>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<4>, manager_xact_id : UInt<1>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<4>}}}, has_acquire_conflict : UInt<1>, has_acquire_match : UInt<1>, has_release_match : UInt<1>}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     reg xact : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data_buffer : UInt<4>[4], wmask_buffer : UInt<16>[4], client_id : UInt<2>}, clk
     wire coh : {sharers : UInt<1>}
     coh is invalid
@@ -7952,7 +7952,7 @@ circuit Top :
     
     io is invalid
     reg T_1502 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
-    reg T_1504 : UInt<?>, clk with : (reset => (reset, UInt<3>("h07")))
+    reg T_1504 : UInt, clk with : (reset => (reset, UInt<3>("h07")))
     wire T_1506 : UInt<3>
     T_1506 is invalid
     io.out.valid <= io.in[T_1506].valid
@@ -8264,7 +8264,7 @@ circuit Top :
     
     io is invalid
     reg T_1318 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
-    reg T_1320 : UInt<?>, clk with : (reset => (reset, UInt<3>("h07")))
+    reg T_1320 : UInt, clk with : (reset => (reset, UInt<3>("h07")))
     wire T_1322 : UInt<3>
     T_1322 is invalid
     io.out.valid <= io.in[T_1322].valid
@@ -8563,7 +8563,7 @@ circuit Top :
     
     io is invalid
     reg T_444 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
-    reg T_446 : UInt<?>, clk with : (reset => (reset, UInt<3>("h07")))
+    reg T_446 : UInt, clk with : (reset => (reset, UInt<3>("h07")))
     wire T_448 : UInt<3>
     T_448 is invalid
     io.out.valid <= io.in[T_448].valid
@@ -9728,16 +9728,14 @@ circuit Top :
     when T_322 :
       node T_324 = eq(reset, UInt<1>("h00"))
       when T_324 :
-        printf(clk, UInt<1>(1), "Invalid read address %x
-", io.ar.bits.addr)
+        printf(clk, UInt<1>(1), "Invalid read address %x\n", io.ar.bits.addr)
         skip
       skip
     node T_325 = and(io.aw.ready, io.aw.valid)
     when T_325 :
       node T_327 = eq(reset, UInt<1>("h00"))
       when T_327 :
-        printf(clk, UInt<1>(1), "Invalid write address %x
-", io.aw.bits.addr)
+        printf(clk, UInt<1>(1), "Invalid write address %x\n", io.aw.bits.addr)
         skip
       skip
     inst r_queue of Queue_36
@@ -10290,16 +10288,14 @@ circuit Top :
     when T_322 :
       node T_324 = eq(reset, UInt<1>("h00"))
       when T_324 :
-        printf(clk, UInt<1>(1), "Invalid read address %x
-", io.ar.bits.addr)
+        printf(clk, UInt<1>(1), "Invalid read address %x\n", io.ar.bits.addr)
         skip
       skip
     node T_325 = and(io.aw.ready, io.aw.valid)
     when T_325 :
       node T_327 = eq(reset, UInt<1>("h00"))
       when T_327 :
-        printf(clk, UInt<1>(1), "Invalid write address %x
-", io.aw.bits.addr)
+        printf(clk, UInt<1>(1), "Invalid write address %x\n", io.aw.bits.addr)
         skip
       skip
     inst r_queue of Queue_36
@@ -11217,7 +11213,7 @@ circuit Top :
     
     io is invalid
     reg T_656 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
-    reg T_658 : UInt<?>, clk with : (reset => (reset, UInt<1>("h01")))
+    reg T_658 : UInt, clk with : (reset => (reset, UInt<1>("h01")))
     wire T_660 : UInt<1>
     T_660 is invalid
     io.out.valid <= io.in[T_660].valid
@@ -12725,7 +12721,7 @@ circuit Top :
     output io : {flip ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<12>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     reg nWords : UInt<1>, clk
     reg nBeats : UInt<8>, clk
     reg addr : UInt<12>, clk
@@ -12845,7 +12841,7 @@ circuit Top :
     reg strb : UInt<1>, clk
     reg data : UInt<64>, clk
     reg last : UInt<1>, clk
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     node T_173 = eq(state, UInt<1>("h00"))
     io.aw.ready <= T_173
     node T_174 = eq(state, UInt<1>("h01"))
@@ -13048,7 +13044,7 @@ circuit Top :
     output io : {flip ar : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<32>, len : UInt<8>, size : UInt<3>, burst : UInt<2>, lock : UInt<1>, cache : UInt<4>, prot : UInt<3>, qos : UInt<4>, region : UInt<4>, id : UInt<5>, user : UInt<1>}}, r : {flip ready : UInt<1>, valid : UInt<1>, bits : {resp : UInt<2>, data : UInt<64>, last : UInt<1>, id : UInt<5>, user : UInt<1>}}, smi : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {rw : UInt<1>, addr : UInt<6>, data : UInt<64>}}, flip resp : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<64>}}}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     reg nWords : UInt<1>, clk
     reg nBeats : UInt<8>, clk
     reg addr : UInt<6>, clk
@@ -13168,7 +13164,7 @@ circuit Top :
     reg strb : UInt<1>, clk
     reg data : UInt<64>, clk
     reg last : UInt<1>, clk
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     node T_173 = eq(state, UInt<1>("h00"))
     io.aw.ready <= T_173
     node T_174 = eq(state, UInt<1>("h01"))
@@ -13516,9 +13512,9 @@ circuit Top :
     io is invalid
     node T_112 = cat(io.wide.req_cmd.bits.tag, io.wide.req_cmd.bits.rw)
     node T_113 = cat(io.wide.req_cmd.bits.addr, T_112)
-    reg out_buf : UInt<?>, clk
-    reg in_buf : UInt<?>, clk
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg out_buf : UInt, clk
+    reg in_buf : UInt, clk
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     reg send_cnt : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
     reg data_send_cnt : UInt<3>, clk with : (reset => (reset, UInt<3>("h00")))
     node T_130 = eq(send_cnt, UInt<1>("h01"))
@@ -14161,10 +14157,10 @@ circuit Top :
     output io : {flip out_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, out_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, in_fast : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, flip in_slow : {flip ready : UInt<1>, valid : UInt<1>, bits : UInt<17>}, clk_slow : UInt<1>, flip set_divisor : {valid : UInt<1>, bits : UInt<32>}, divisor : UInt<32>}
     
     io is invalid
-    reg divisor : UInt<?>, clk with : (reset => (reset, UInt<9>("h01ff")))
-    reg d_shadow : UInt<?>, clk with : (reset => (reset, UInt<9>("h01ff")))
-    reg hold : UInt<?>, clk with : (reset => (reset, UInt<7>("h07f")))
-    reg h_shadow : UInt<?>, clk with : (reset => (reset, UInt<7>("h07f")))
+    reg divisor : UInt, clk with : (reset => (reset, UInt<9>("h01ff")))
+    reg d_shadow : UInt, clk with : (reset => (reset, UInt<9>("h01ff")))
+    reg hold : UInt, clk with : (reset => (reset, UInt<7>("h07f")))
+    reg h_shadow : UInt, clk with : (reset => (reset, UInt<7>("h07f")))
     when io.set_divisor.valid :
       node T_57 = bits(io.set_divisor.bits, 8, 0)
       d_shadow <= T_57
@@ -15917,7 +15913,7 @@ circuit Top :
     output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}}, flip kill : UInt<1>, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<64>, tag : UInt<5>}}}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     reg req : {fn : UInt<4>, dw : UInt<1>, in1 : UInt<64>, in2 : UInt<64>, tag : UInt<5>}, clk
     reg count : UInt<7>, clk
     reg neg_out : UInt<1>, clk
@@ -16429,9 +16425,9 @@ circuit Top :
     reg ex_reg_xcpt : UInt<1>, clk
     reg ex_reg_flush_pipe : UInt<1>, clk
     reg ex_reg_load_use : UInt<1>, clk
-    reg ex_reg_cause : UInt<?>, clk
-    reg ex_reg_pc : UInt<?>, clk
-    reg ex_reg_inst : UInt<?>, clk
+    reg ex_reg_cause : UInt, clk
+    reg ex_reg_pc : UInt, clk
+    reg ex_reg_inst : UInt, clk
     reg mem_reg_xcpt_interrupt : UInt<1>, clk
     reg mem_reg_valid : UInt<1>, clk
     reg mem_reg_btb_hit : UInt<1>, clk
@@ -16439,23 +16435,23 @@ circuit Top :
     reg mem_reg_xcpt : UInt<1>, clk
     reg mem_reg_replay : UInt<1>, clk
     reg mem_reg_flush_pipe : UInt<1>, clk
-    reg mem_reg_cause : UInt<?>, clk
+    reg mem_reg_cause : UInt, clk
     reg mem_reg_slow_bypass : UInt<1>, clk
-    reg mem_reg_pc : UInt<?>, clk
-    reg mem_reg_inst : UInt<?>, clk
-    reg mem_reg_wdata : UInt<?>, clk
-    reg mem_reg_rs2 : UInt<?>, clk
+    reg mem_reg_pc : UInt, clk
+    reg mem_reg_inst : UInt, clk
+    reg mem_reg_wdata : UInt, clk
+    reg mem_reg_rs2 : UInt, clk
     wire take_pc_mem : UInt<1>
     take_pc_mem is invalid
     reg wb_reg_valid : UInt<1>, clk
     reg wb_reg_xcpt : UInt<1>, clk
     reg wb_reg_replay : UInt<1>, clk
-    reg wb_reg_cause : UInt<?>, clk
+    reg wb_reg_cause : UInt, clk
     reg wb_reg_rocc_pending : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
-    reg wb_reg_pc : UInt<?>, clk
-    reg wb_reg_inst : UInt<?>, clk
-    reg wb_reg_wdata : UInt<?>, clk
-    reg wb_reg_rs2 : UInt<?>, clk
+    reg wb_reg_pc : UInt, clk
+    reg wb_reg_inst : UInt, clk
+    reg wb_reg_wdata : UInt, clk
+    reg wb_reg_rs2 : UInt, clk
     wire take_pc_wb : UInt<1>
     take_pc_wb is invalid
     node take_pc_mem_wb = or(take_pc_wb, take_pc_mem)
@@ -16895,7 +16891,7 @@ circuit Top :
     id_load_use is invalid
     reg id_reg_fence : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
     cmem T_6766 : UInt<64>[31]
-    wire T_6768 : UInt<?>
+    wire T_6768 : UInt
     T_6768 is invalid
     node T_6771 = eq(id_raddr1, UInt<1>("h00"))
     node T_6772 = and(UInt<1>("h00"), T_6771)
@@ -16904,7 +16900,7 @@ circuit Top :
     infer mport T_6776 = T_6766[T_6775], clk
     node T_6777 = mux(T_6772, UInt<1>("h00"), T_6776)
     T_6768 <= T_6777
-    wire T_6779 : UInt<?>
+    wire T_6779 : UInt
     T_6779 is invalid
     node T_6782 = eq(id_raddr2, UInt<1>("h00"))
     node T_6783 = and(UInt<1>("h00"), T_6782)
@@ -16999,14 +16995,14 @@ circuit Top :
     node T_6944 = and(T_6929, T_6943)
     node T_6945 = eq(mem_waddr, id_raddr2)
     node T_6946 = and(T_6930, T_6945)
-    wire bypass_mux : UInt<?>[4]
+    wire bypass_mux : UInt[4]
     bypass_mux[0] <= UInt<1>("h00")
     bypass_mux[1] <= mem_reg_wdata
     bypass_mux[2] <= wb_reg_wdata
     bypass_mux[3] <= io.dmem.resp.bits.data_word_bypass
     reg ex_reg_rs_bypass : UInt<1>[2], clk
-    reg ex_reg_rs_lsb : UInt<?>[2], clk
-    reg ex_reg_rs_msb : UInt<?>[2], clk
+    reg ex_reg_rs_lsb : UInt[2], clk
+    reg ex_reg_rs_msb : UInt[2], clk
     node T_6991 = cat(ex_reg_rs_msb[0], ex_reg_rs_lsb[0])
     node T_6992 = mux(ex_reg_rs_bypass[0], bypass_mux[ex_reg_rs_lsb[0]], T_6991)
     node T_6994 = cat(ex_reg_rs_msb[1], ex_reg_rs_lsb[1])
@@ -17506,9 +17502,9 @@ circuit Top :
     node T_7462 = and(wb_reg_valid, wb_ctrl.wxd)
     node T_7464 = eq(T_7462, UInt<1>("h00"))
     div.io.resp.ready <= T_7464
-    wire ll_wdata : UInt<?>
+    wire ll_wdata : UInt
     ll_wdata <= div.io.resp.bits.data
-    wire ll_waddr : UInt<?>
+    wire ll_waddr : UInt
     ll_waddr <= div.io.resp.bits.tag
     node T_7467 = and(div.io.resp.ready, div.io.resp.valid)
     wire ll_wen : UInt<1>
@@ -17893,19 +17889,18 @@ circuit Top :
     node T_7816 = bits(csr.io.time, 32, 0)
     node T_7818 = mux(rf_wen, rf_waddr, UInt<1>("h00"))
     node T_7819 = bits(wb_reg_inst, 19, 15)
-    reg T_7820 : UInt<?>, clk
+    reg T_7820 : UInt, clk
     T_7820 <= T_6992
-    reg T_7821 : UInt<?>, clk
+    reg T_7821 : UInt, clk
     T_7821 <= T_7820
     node T_7822 = bits(wb_reg_inst, 24, 20)
-    reg T_7823 : UInt<?>, clk
+    reg T_7823 : UInt, clk
     T_7823 <= T_6995
-    reg T_7824 : UInt<?>, clk
+    reg T_7824 : UInt, clk
     T_7824 <= T_7823
     node T_7826 = eq(reset, UInt<1>("h00"))
     when T_7826 :
-      printf(clk, UInt<1>(1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)
-", io.host.id, T_7816, wb_valid, wb_reg_pc, T_7818, rf_wdata, rf_wen, T_7819, T_7821, T_7822, T_7824, wb_reg_inst, wb_reg_inst)
+      printf(clk, UInt<1>(1), "C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n ", io.host.id, T_7816, wb_valid, wb_reg_pc, T_7818, rf_wdata, rf_wen, T_7819, T_7821, T_7822, T_7824, wb_reg_inst, wb_reg_inst)
       skip
     
   module BTB : 
@@ -20635,7 +20630,7 @@ circuit Top :
     io.resp.bits.bht <- T_4537
     reg T_4567 : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
     reg T_4569 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
-    reg T_4578 : UInt<?>[2], clk
+    reg T_4578 : UInt[2], clk
     node T_4582 = bits(hits, 0, 0)
     node T_4583 = bits(hits, 1, 1)
     node T_4584 = bits(hits, 2, 2)
@@ -20950,7 +20945,7 @@ circuit Top :
     output io : {flip req : {valid : UInt<1>, bits : {idx : UInt<12>, ppn : UInt<20>, kill : UInt<1>}}, resp : {flip ready : UInt<1>, valid : UInt<1>, bits : {data : UInt<32>, datablock : UInt<128>}}, flip invalidate : UInt<1>, mem : {acquire : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, flip grant : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}}}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     reg invalidated : UInt<1>, clk
     node stall = eq(io.resp.ready, UInt<1>("h00"))
     wire rdy : UInt<1>
@@ -21035,7 +21030,7 @@ circuit Top :
     node T_599 = bits(s0_pgoff, 11, 6)
     node T_601 = eq(refill_done, UInt<1>("h00"))
     node T_602 = and(T_601, s0_valid)
-    wire T_604 : UInt<?>
+    wire T_604 : UInt
     T_604 is invalid
     when T_602 :
       T_604 <= T_599
@@ -21247,7 +21242,7 @@ circuit Top :
     node T_880 = bits(s0_pgoff, 11, 4)
     node T_882 = eq(T_877, UInt<1>("h00"))
     node T_883 = and(T_882, s0_valid)
-    wire T_885 : UInt<?>
+    wire T_885 : UInt
     T_885 is invalid
     when T_883 :
       T_885 <= T_880
@@ -21265,7 +21260,7 @@ circuit Top :
     node T_895 = bits(s0_pgoff, 11, 4)
     node T_897 = eq(T_892, UInt<1>("h00"))
     node T_898 = and(T_897, s0_valid)
-    wire T_900 : UInt<?>
+    wire T_900 : UInt
     T_900 is invalid
     when T_898 :
       T_900 <= T_895
@@ -21283,7 +21278,7 @@ circuit Top :
     node T_910 = bits(s0_pgoff, 11, 4)
     node T_912 = eq(T_907, UInt<1>("h00"))
     node T_913 = and(T_912, s0_valid)
-    wire T_915 : UInt<?>
+    wire T_915 : UInt
     T_915 is invalid
     when T_913 :
       T_915 <= T_910
@@ -21301,7 +21296,7 @@ circuit Top :
     node T_925 = bits(s0_pgoff, 11, 4)
     node T_927 = eq(T_922, UInt<1>("h00"))
     node T_928 = and(T_927, s0_valid)
-    wire T_930 : UInt<?>
+    wire T_930 : UInt
     T_930 is invalid
     when T_928 :
       T_930 <= T_925
@@ -21468,9 +21463,9 @@ circuit Top :
     output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}}, resp : {miss : UInt<1>, ppn : UInt<20>, xcpt_ld : UInt<1>, xcpt_st : UInt<1>, xcpt_if : UInt<1>, hit_idx : UInt<8>}, ptw : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
-    reg r_refill_tag : UInt<?>, clk
-    reg r_refill_waddr : UInt<?>, clk
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
+    reg r_refill_tag : UInt, clk
+    reg r_refill_waddr : UInt, clk
     reg r_req : {asid : UInt<7>, vpn : UInt<28>, passthrough : UInt<1>, instruction : UInt<1>, store : UInt<1>}, clk
     inst tag_cam of RocketCAM
     tag_cam.io is invalid
@@ -21989,13 +21984,13 @@ circuit Top :
     tlb.io is invalid
     tlb.clk <= clk
     tlb.reset <= reset
-    reg s1_pc_ : UInt<?>, clk
+    reg s1_pc_ : UInt, clk
     node T_1280 = not(s1_pc_)
     node T_1282 = or(T_1280, UInt<2>("h03"))
     node s1_pc = not(T_1282)
     reg s1_same_block : UInt<1>, clk
     reg s2_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h01")))
-    reg s2_pc : UInt<?>, clk with : (reset => (reset, UInt<10>("h0200")))
+    reg s2_pc : UInt, clk with : (reset => (reset, UInt<10>("h0200")))
     reg s2_btb_resp_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
     reg s2_btb_resp_bits : {taken : UInt<1>, mask : UInt<1>, bridx : UInt<1>, target : UInt<39>, entry : UInt<6>, bht : {history : UInt<7>, value : UInt<2>}}, clk
     reg s2_xcpt_if : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
@@ -22208,9 +22203,9 @@ circuit Top :
     output io : {flip req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<2>}}, rep : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>}}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, flip way_en : UInt<4>, flip mshr_rdy : UInt<1>, flip block_state : {state : UInt<2>}}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     reg old_coh : {state : UInt<2>}, clk
-    reg way_en : UInt<?>, clk
+    reg way_en : UInt, clk
     reg req : {addr_block : UInt<26>, p_type : UInt<2>, client_xact_id : UInt<2>}, clk
     node tag_matches = neq(way_en, UInt<1>("h00"))
     wire miss_coh : {state : UInt<2>}
@@ -22436,7 +22431,7 @@ circuit Top :
     
     io is invalid
     reg T_852 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
-    reg T_854 : UInt<?>, clk with : (reset => (reset, UInt<2>("h02")))
+    reg T_854 : UInt, clk with : (reset => (reset, UInt<2>("h02")))
     wire T_856 : UInt<2>
     T_856 is invalid
     io.out.valid <= io.in[T_856].valid
@@ -22643,7 +22638,7 @@ circuit Top :
     output io : {flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, idx_match : UInt<1>, tag : UInt<20>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     wire T_1277 : {state : UInt<2>}
     T_1277 is invalid
     T_1277.state <= UInt<1>("h00")
@@ -23016,7 +23011,7 @@ circuit Top :
     output io : {flip req_pri_val : UInt<1>, req_pri_rdy : UInt<1>, flip req_sec_val : UInt<1>, req_sec_rdy : UInt<1>, flip req_bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>, tag_match : UInt<1>, old_meta : {tag : UInt<20>, coh : {state : UInt<2>}}, way_en : UInt<4>}, idx_match : UInt<1>, tag : UInt<20>, mem_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_block : UInt<26>, client_xact_id : UInt<2>, addr_beat : UInt<2>, is_builtin_type : UInt<1>, a_type : UInt<3>, union : UInt<17>, data : UInt<128>}}, refill : {way_en : UInt<4>, addr : UInt<12>}, meta_read : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, tag : UInt<20>}}, meta_write : {flip ready : UInt<1>, valid : UInt<1>, bits : {idx : UInt<6>, way_en : UInt<4>, data : {tag : UInt<20>, coh : {state : UInt<2>}}}}, replay : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, sdq_id : UInt<5>}}, flip mem_grant : {valid : UInt<1>, bits : {addr_beat : UInt<2>, client_xact_id : UInt<2>, manager_xact_id : UInt<4>, is_builtin_type : UInt<1>, g_type : UInt<4>, data : UInt<128>}}, wb_req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr_beat : UInt<2>, addr_block : UInt<26>, client_xact_id : UInt<2>, voluntary : UInt<1>, r_type : UInt<3>, data : UInt<128>, way_en : UInt<4>}}, probe_rdy : UInt<1>}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     wire T_1277 : {state : UInt<2>}
     T_1277 is invalid
     T_1277.state <= UInt<1>("h00")
@@ -23477,7 +23472,7 @@ circuit Top :
     node T_926 = mux(T_917, T_920, T_925)
     node T_927 = mux(T_911, T_915, T_926)
     node beat_data = cat(T_927, T_927)
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     node T_935 = eq(state, UInt<1>("h00"))
     io.req.ready <= T_935
     node addr_block = bits(req.addr, 31, 6)
@@ -23759,7 +23754,7 @@ circuit Top :
     T_1927 <= T_1926
     node T_1928 = shr(io.req.bits.addr, 12)
     node tag_match = eq(T_1927, T_1928)
-    wire wbTagList : UInt<?>[2]
+    wire wbTagList : UInt[2]
     wbTagList is invalid
     wire refillMux : {way_en : UInt<4>, addr : UInt<12>}[2]
     refillMux is invalid
@@ -24049,7 +24044,7 @@ circuit Top :
         T_1751[3] <= T_1743[3]
         skip
       skip
-    wire T_1758 : UInt<?>
+    wire T_1758 : UInt
     T_1758 is invalid
     when io.read.valid :
       T_1758 <= io.read.bits.idx
@@ -24179,7 +24174,7 @@ circuit Top :
       skip
     node T_626 = neq(T_573, UInt<1>("h00"))
     node T_627 = and(T_626, io.read.valid)
-    wire T_629 : UInt<?>
+    wire T_629 : UInt
     T_629 is invalid
     when T_627 :
       T_629 <= raddr
@@ -24213,7 +24208,7 @@ circuit Top :
       skip
     node T_676 = neq(T_573, UInt<1>("h00"))
     node T_677 = and(T_676, io.read.valid)
-    wire T_679 : UInt<?>
+    wire T_679 : UInt
     T_679 is invalid
     when T_677 :
       T_679 <= raddr
@@ -24277,7 +24272,7 @@ circuit Top :
       skip
     node T_771 = neq(T_718, UInt<1>("h00"))
     node T_772 = and(T_771, io.read.valid)
-    wire T_774 : UInt<?>
+    wire T_774 : UInt
     T_774 is invalid
     when T_772 :
       T_774 <= raddr
@@ -24311,7 +24306,7 @@ circuit Top :
       skip
     node T_821 = neq(T_718, UInt<1>("h00"))
     node T_822 = and(T_821, io.read.valid)
-    wire T_824 : UInt<?>
+    wire T_824 : UInt
     T_824 is invalid
     when T_822 :
       T_824 <= raddr
@@ -24591,7 +24586,7 @@ circuit Top :
     
     io is invalid
     reg T_700 : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
-    reg T_702 : UInt<?>, clk with : (reset => (reset, UInt<1>("h01")))
+    reg T_702 : UInt, clk with : (reset => (reset, UInt<1>("h01")))
     wire T_704 : UInt<1>
     T_704 is invalid
     io.out.valid <= io.in[T_704].valid
@@ -24690,7 +24685,7 @@ circuit Top :
     s2_valid_masked is invalid
     reg s3_valid : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
     reg s3_req : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}, clk
-    reg s3_way : UInt<?>, clk
+    reg s3_way : UInt, clk
     reg s1_recycled : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
     when s1_clk_en :
       s1_recycled <= s2_recycle
@@ -24991,9 +24986,9 @@ circuit Top :
     T_2621.state <= T_2595
     node T_2646 = eq(s2_hit_state.state, T_2621.state)
     node s2_hit = and(T_2587, T_2646)
-    reg lrsc_count : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg lrsc_count : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     node lrsc_valid = neq(lrsc_count, UInt<1>("h00"))
-    reg lrsc_addr : UInt<?>, clk
+    reg lrsc_addr : UInt, clk
     node s2_lr = eq(s2_req.cmd, UInt<5>("h06"))
     node s2_sc = eq(s2_req.cmd, UInt<5>("h07"))
     node T_2656 = shr(s2_req.addr, 6)
@@ -25662,10 +25657,10 @@ circuit Top :
     output io : {flip requestor : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}}, flip resp : {valid : UInt<1>, bits : {error : UInt<1>, pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}}}, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}, flip invalidate : UInt<1>}[2], mem : {req : {flip ready : UInt<1>, valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, kill : UInt<1>, phys : UInt<1>, data : UInt<64>}}, flip resp : {valid : UInt<1>, bits : {addr : UInt<40>, tag : UInt<9>, cmd : UInt<5>, typ : UInt<3>, data : UInt<64>, nack : UInt<1>, replay : UInt<1>, has_data : UInt<1>, data_word_bypass : UInt<64>, store_data : UInt<64>}}, flip replay_next : {valid : UInt<1>, bits : UInt<9>}, flip xcpt : {ma : {ld : UInt<1>, st : UInt<1>}, pf : {ld : UInt<1>, st : UInt<1>}}, invalidate_lr : UInt<1>, flip ordered : UInt<1>}, dpath : {flip ptbr : UInt<32>, flip invalidate : UInt<1>, flip status : {sd : UInt<1>, zero2 : UInt<31>, sd_rv32 : UInt<1>, zero1 : UInt<9>, vm : UInt<5>, mprv : UInt<1>, xs : UInt<2>, fs : UInt<2>, prv3 : UInt<2>, ie3 : UInt<1>, prv2 : UInt<2>, ie2 : UInt<1>, prv1 : UInt<2>, ie1 : UInt<1>, prv : UInt<2>, ie : UInt<1>}}}
     
     io is invalid
-    reg state : UInt<?>, clk with : (reset => (reset, UInt<1>("h00")))
+    reg state : UInt, clk with : (reset => (reset, UInt<1>("h00")))
     reg count : UInt<2>, clk
     reg r_req : {addr : UInt<27>, prv : UInt<2>, store : UInt<1>, fetch : UInt<1>}, clk
-    reg r_req_dest : UInt<?>, clk
+    reg r_req_dest : UInt, clk
     reg r_pte : {ppn : UInt<20>, reserved_for_software : UInt<3>, d : UInt<1>, r : UInt<1>, typ : UInt<4>, v : UInt<1>}, clk
     node T_1590 = shr(r_req.addr, 18)
     node T_1591 = bits(T_1590, 8, 0)
@@ -30128,13 +30123,13 @@ circuit Top :
     cyc_E2 is invalid
     wire cyc_E1 : UInt<1>
     cyc_E1 is invalid
-    wire zSigma1_B4 : UInt<?>
+    wire zSigma1_B4 : UInt
     zSigma1_B4 is invalid
-    wire sigXNU_B3_CX : UInt<?>
+    wire sigXNU_B3_CX : UInt
     sigXNU_B3_CX is invalid
-    wire zComplSigT_C1_sqrt : UInt<?>
+    wire zComplSigT_C1_sqrt : UInt
     zComplSigT_C1_sqrt is invalid
-    wire zComplSigT_C1 : UInt<?>
+    wire zComplSigT_C1 : UInt
     zComplSigT_C1 is invalid
     node T_210 = not(cyc_B7_sqrt)
     node T_211 = and(ready_PA, T_210)
@@ -31800,9 +31795,9 @@ circuit Top :
       infer mport T_718 = regfile[load_wb_tag], clk
       T_718 <= load_wb_data_recoded
       skip
-    reg ex_ra1 : UInt<?>, clk
-    reg ex_ra2 : UInt<?>, clk
-    reg ex_ra3 : UInt<?>, clk
+    reg ex_ra1 : UInt, clk
+    reg ex_ra2 : UInt, clk
+    reg ex_ra3 : UInt, clk
     when io.valid :
       when fp_decoder.io.sigs.ren1 :
         node T_726 = eq(fp_decoder.io.sigs.swap12, UInt<1>("h00"))
@@ -31918,10 +31913,10 @@ circuit Top :
     divSqrt_wen <= UInt<1>("h00")
     wire divSqrt_inReady : UInt<1>
     divSqrt_inReady <= UInt<1>("h00")
-    reg divSqrt_waddr : UInt<?>, clk
-    wire divSqrt_wdata : UInt<?>
+    reg divSqrt_waddr : UInt, clk
+    wire divSqrt_wdata : UInt
     divSqrt_wdata is invalid
-    wire divSqrt_flags : UInt<?>
+    wire divSqrt_flags : UInt
     divSqrt_flags is invalid
     reg divSqrt_in_flight : UInt<1>, clk with : (reset => (reset, UInt<1>("h00")))
     reg divSqrt_killed : UInt<1>, clk
@@ -31936,7 +31931,7 @@ circuit Top :
     node T_856 = or(T_855, T_848)
     node memLatencyMask = or(T_856, T_854)
     reg wen : UInt<2>, clk with : (reset => (reset, UInt<2>("h00")))
-    reg winfo : UInt<?>[2], clk
+    reg winfo : UInt[2], clk
     node T_872 = or(mem_ctrl.fma, mem_ctrl.fastpipe)
     node T_873 = or(T_872, mem_ctrl.fromint)
     node mem_wen = and(mem_reg_valid, T_873)
@@ -32098,9 +32093,9 @@ circuit Top :
     divSqrt_wdata <= UInt<1>("h00")
     divSqrt_flags <= UInt<1>("h00")
     reg T_1046 : UInt<1>, clk
-    reg T_1048 : UInt<?>, clk
-    reg T_1050 : UInt<?>, clk
-    reg T_1052 : UInt<?>, clk
+    reg T_1048 : UInt, clk
+    reg T_1050 : UInt, clk
+    reg T_1052 : UInt, clk
     inst T_1053 of DivSqrtRecF64
     T_1053.io is invalid
     T_1053.clk <= clk
diff --git a/src/main/antlr4/FIRRTL.g4 b/src/main/antlr4/FIRRTL.g4
index 6e6b972f..59de36dd 100644
--- a/src/main/antlr4/FIRRTL.g4
+++ b/src/main/antlr4/FIRRTL.g4
@@ -57,6 +57,9 @@ stmt
                      | 'readwriter' '=>' id 
                      )*
                  '}'
+  | 'cmem' id ':' type
+  | 'smem' id ':' type
+  | mdir 'mport' id '=' id '[' exp ']' exp
   | 'inst' id 'of' id 
   | 'node' id '=' exp
   | exp '<=' exp 
@@ -68,6 +71,13 @@ stmt
   | 'skip'
   ;
 
+mdir
+  : 'infer'
+  | 'read'
+  | 'write'
+  | 'rdwr'
+  ;
+
 ruw
   : 'old'
   | 'new'
@@ -129,6 +139,10 @@ keyword
   | 'undefined'
   | 'mux'
   | 'validif'
+  | 'write'
+  | 'read'
+  | 'rdwr'
+  | 'infer'
   ;
 
 // Parentheses are added as part of name because semantics require no space between primop and open parentheses
diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 499ab6db..a3b42695 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -38,6 +38,7 @@ object VerilogEmitter extends Emitter {
       var percent:Boolean = false
       for (c <- s) {
          if (c == '\n') sx += "\\n"
+         else if (c == '"') sx += '\\'.toString + '"'.toString
          else {
             if((c == 'x') && percent) sx += "h" else sx += c.toString
          }
@@ -335,7 +336,8 @@ object VerilogEmitter extends Emitter {
          Seq("$fdisplay(32'h80000002,\"",ret,"\");$finish;")
       }
       def printf (str:String,args:Seq[Expression]) : Seq[Any] = {
-         val strx = (Seq(escape(str)) ++ args).reduce(Seq(_, ",", _))
+         val q = '"'.toString
+         val strx = (Seq(q + escape(str) + q) ++ args.map(x => escape(x.serialize()))).reduce(_ + "," + _)
          Seq("$fwrite(32'h80000002,",strx,");")
       }
       def delay (e:Expression, n:Int, clk:Expression) : Expression = {
diff --git a/src/main/scala/firrtl/Utils.scala b/src/main/scala/firrtl/Utils.scala
index e4525560..546ba17b 100644
--- a/src/main/scala/firrtl/Utils.scala
+++ b/src/main/scala/firrtl/Utils.scala
@@ -875,8 +875,11 @@ object Utils {
          } 
          case i: IsInvalid => s"${i.exp.serialize} is invalid"
          case s: Stop => s"stop(${s.clk.serialize}, ${s.en.serialize}, ${s.ret})"
-         case p: Print => s"printf(${p.clk.serialize}, ${p.en.serialize}, ${p.string}" + 
+         case p: Print => {
+            val q = '"'.toString
+            s"printf(${p.clk.serialize}, ${p.en.serialize}, ${q}${p.string}${q}" + 
                           (if (p.args.nonEmpty) p.args.map(_.serialize).mkString(", ", ", ", "") else "") + ")"
+         }
          case s:Empty => "skip"
          case s:CDefMemory => {
             if (s.seq) s"smem ${s.name} : ${s.tpe} [${s.size}]"
diff --git a/src/main/scala/firrtl/Visitor.scala b/src/main/scala/firrtl/Visitor.scala
index f77a3f58..76759687 100644
--- a/src/main/scala/firrtl/Visitor.scala
+++ b/src/main/scala/firrtl/Visitor.scala
@@ -59,17 +59,23 @@ class Visitor(val fullFilename: String) extends FIRRTLBaseVisitor[AST]
   private def visitModule[AST](ctx: FIRRTLParser.ModuleContext): Module = 
     InModule(getInfo(ctx), (ctx.id.getText), ctx.port.map(visitPort), visitBlock(ctx.block))
 
-	private def visitPort[AST](ctx: FIRRTLParser.PortContext): Port = 
+  private def visitPort[AST](ctx: FIRRTLParser.PortContext): Port = 
     Port(getInfo(ctx), (ctx.id.getText), visitDir(ctx.dir), visitType(ctx.`type`))
-
-	private def visitDir[AST](ctx: FIRRTLParser.DirContext): Direction =
+  private def visitDir[AST](ctx: FIRRTLParser.DirContext): Direction =
     ctx.getText match {
       case "input" => INPUT
       case "output" => OUTPUT
     }
+  private def visitMdir[AST](ctx: FIRRTLParser.MdirContext): MPortDir =
+    ctx.getText match {
+      case "infer" => MInfer
+      case "read" => MRead
+      case "write" => MWrite
+      case "rdwr" => MReadWrite
+    }
 
   // Match on a type instead of on strings?
-	private def visitType[AST](ctx: FIRRTLParser.TypeContext): Type = {
+  private def visitType[AST](ctx: FIRRTLParser.TypeContext): Type = {
     ctx.getChild(0) match {
       case term: TerminalNode => 
         term.getText match {
@@ -145,6 +151,20 @@ class Visitor(val fullFilename: String) extends FIRRTLBaseVisitor[AST]
         DefRegister(info, name, tpe, visitExp(ctx.exp(0)), reset, init)
       }
       case "mem" => visitMem(ctx)
+      case "cmem" => {
+         val t = visitType(ctx.`type`(0))
+         t match {
+            case (t:VectorType) => CDefMemory(info,ctx.id(0).getText,t.tpe,t.size,false)
+            case _ => throw new ParserException(s"${info}: Must provide cmem with vector type")
+         }
+      }
+      case "smem" => {
+         val t = visitType(ctx.`type`(0))
+         t match {
+            case (t:VectorType) => CDefMemory(info,ctx.id(0).getText,t.tpe,t.size,true)
+            case _ => throw new ParserException(s"${info}: Must provide cmem with vector type")
+         }
+      }
       case "inst"  => DefInstance(info, (ctx.id(0).getText), (ctx.id(1).getText))
       case "node" =>  DefNode(info, (ctx.id(0).getText), visitExp(ctx.exp(0)))
       case "when" => { 
@@ -162,6 +182,7 @@ class Visitor(val fullFilename: String) extends FIRRTLBaseVisitor[AST]
           case "<=" => Connect(info, visitExp(ctx.exp(0)), visitExp(ctx.exp(1)) )
           case "<-" => BulkConnect(info, visitExp(ctx.exp(0)), visitExp(ctx.exp(1)) )
           case "is" => IsInvalid(info, visitExp(ctx.exp(0)))
+          case "mport" => CDefMPort(info, ctx.id(0).getText, UnknownType(),ctx.id(1).getText,Seq(visitExp(ctx.exp(0)),visitExp(ctx.exp(1))),visitMdir(ctx.mdir))
         }
       }
     }
diff --git a/src/main/scala/firrtl/WIR.scala b/src/main/scala/firrtl/WIR.scala
index eaa4166b..61657879 100644
--- a/src/main/scala/firrtl/WIR.scala
+++ b/src/main/scala/firrtl/WIR.scala
@@ -190,6 +190,6 @@ case object MRead extends MPortDir
 case object MWrite extends MPortDir
 case object MReadWrite extends MPortDir
 
-case class CDefMemory (val info: FileInfo, val name: String, val tpe: Type, val size: Int, val seq: Boolean) extends Stmt
-case class CDefMPort (val info: FileInfo, val name: String, val tpe: Type, val mem: String, val exps: Seq[Expression], val direction: MPortDir) extends Stmt
+case class CDefMemory (val info: Info, val name: String, val tpe: Type, val size: Int, val seq: Boolean) extends Stmt
+case class CDefMPort (val info: Info, val name: String, val tpe: Type, val mem: String, val exps: Seq[Expression], val direction: MPortDir) extends Stmt
 
diff --git a/src/main/scala/firrtl/passes/Checks.scala b/src/main/scala/firrtl/passes/Checks.scala
index 50ede528..e8d8b112 100644
--- a/src/main/scala/firrtl/passes/Checks.scala
+++ b/src/main/scala/firrtl/passes/Checks.scala
@@ -10,6 +10,7 @@ import scala.collection.mutable.ArrayBuffer
 import firrtl._
 import firrtl.Utils._
 import firrtl.PrimOps._
+import firrtl.WrappedType._
 
 object CheckHighForm extends Pass with LazyLogging {
   def name = "High Form Check"
@@ -266,3 +267,504 @@ object CheckHighForm extends Pass with LazyLogging {
   }
 }
 
+object CheckTypes extends Pass with LazyLogging {
+   def name = "Check Types"
+   var mname = ""
+
+  // Custom Exceptions
+   class SubfieldNotInBundle(info:Info, name:String) extends PassException(s"${info}: [module ${mname} ]  Subfield ${name} is not in bundle.")
+   class SubfieldOnNonBundle(info:Info, name:String) extends PassException(s"${info}: [module ${mname}]  Subfield ${name} is accessed on a non-bundle.")
+   class IndexTooLarge(info:Info, value:Int) extends PassException(s"${info}: [module ${mname}]  Index with value ${value} is too large.")
+   class IndexOnNonVector(info:Info) extends PassException(s"${info}: [module ${mname}]  Index illegal on non-vector type.")
+   class AccessIndexNotUInt(info:Info) extends PassException(s"${info}: [module ${mname}]  Access index must be a UInt type.")
+   class IndexNotUInt(info:Info) extends PassException(s"${info}: [module ${mname}]  Index is not of UIntType.")
+   class EnableNotUInt(info:Info) extends PassException(s"${info}: [module ${mname}]  Enable is not of UIntType.")
+   class InvalidConnect(info:Info) extends PassException(s"${info}: [module ${mname}]  Type mismatch.")
+   class PrintfArgNotGround(info:Info) extends PassException(s"${info}: [module ${mname}]  Printf arguments must be either UIntType or SIntType.")
+   class ReqClk(info:Info) extends PassException(s"${info}: [module ${mname}]  Requires a clock typed signal.")
+   class EnNotUInt(info:Info) extends PassException(s"${info}: [module ${mname}]  Enable must be a UIntType typed signal.")
+   class PredNotUInt(info:Info) extends PassException(s"${info}: [module ${mname}]  Predicate not a UIntType.")
+   class OpNotGround(info:Info, op:String) extends PassException(s"${info}: [module ${mname}]  Primop ${op} cannot operate on non-ground types.")
+   class OpNotUInt(info:Info, op:String,e:String) extends PassException(s"${info}: [module ${mname}]  Primop ${op} requires argument ${e} to be a UInt type.")
+   class OpNotAllUInt(info:Info, op:String) extends PassException(s"${info}: [module ${mname}]  Primop ${op} requires all arguments to be UInt type.")
+   class OpNotAllSameType(info:Info, op:String) extends PassException(s"${info}: [module ${mname}]  Primop ${op} requires all operands to have the same type.")
+   class NodePassiveType(info:Info) extends PassException(s"${info}: [module ${mname}]  Node must be a passive type.")
+   class MuxSameType(info:Info) extends PassException(s"${info}: [module ${mname}]  Must mux between equivalent types.")
+   class MuxPassiveTypes(info:Info) extends PassException(s"${info}: [module ${mname}]  Must mux between passive types.")
+   class MuxCondUInt(info:Info) extends PassException(s"${info}: [module ${mname}]  A mux condition must be of type UInt.")
+   class ValidIfPassiveTypes(info:Info) extends PassException(s"${info}: [module ${mname}]  Must validif a passive type.")
+   class ValidIfCondUInt(info:Info) extends PassException(s"${info}: [module ${mname}]  A validif condition must be of type UInt.")
+   //;---------------- Helper Functions --------------
+   def ut () : UIntType = UIntType(UnknownWidth())
+   def st () : SIntType = SIntType(UnknownWidth())
+   
+   def check_types_primop (e:DoPrim, errors:ArrayBuffer[PassException],info:Info) : Unit = {
+      def all_same_type (ls:Seq[Expression]) : Unit = {
+         var error = false
+         for (x <- ls) {
+            if (wt(tpe(ls.head)) != wt(tpe(x))) error = true
+         }
+         if (error) errors += new OpNotAllSameType(info,e.op.serialize()) 
+      }
+      def all_ground (ls:Seq[Expression]) : Unit = {
+         var error = false
+         for (x <- ls ) {
+            if (!(tpe(x).typeof[UIntType] || tpe(x).typeof[SIntType])) error = true
+         }
+         if (error) errors += new OpNotGround(info,e.op.serialize()) 
+      }
+      def all_uint (ls:Seq[Expression]) : Unit = {
+         var error = false
+         for (x <- ls ) {
+            if (!(tpe(x).typeof[UIntType])) error = true
+         }
+         if (error) errors += new OpNotAllUInt(info,e.op.serialize()) 
+      }
+      def is_uint (x:Expression) : Unit = {
+         var error = false
+         if (!(tpe(x).typeof[UIntType])) error = true
+         if (error) errors += new OpNotUInt(info,e.op.serialize(),x.serialize()) 
+      }
+      
+      e.op match {
+         case AS_UINT_OP =>  {}
+         case AS_SINT_OP =>  {}
+         case AS_CLOCK_OP =>  {}
+         case DYN_SHIFT_LEFT_OP =>  is_uint(e.args(1)); all_ground(e.args)
+         case DYN_SHIFT_RIGHT_OP => is_uint(e.args(1)); all_ground(e.args)
+         case ADD_OP =>  all_ground(e.args)
+         case SUB_OP =>  all_ground(e.args)
+         case MUL_OP =>  all_ground(e.args)
+         case DIV_OP =>  all_ground(e.args)
+         case REM_OP =>  all_ground(e.args)
+         case LESS_OP =>  all_ground(e.args)
+         case LESS_EQ_OP =>  all_ground(e.args)
+         case GREATER_OP =>  all_ground(e.args)
+         case GREATER_EQ_OP =>  all_ground(e.args)
+         case EQUAL_OP =>  all_ground(e.args)
+         case NEQUAL_OP =>  all_ground(e.args)
+         case PAD_OP =>  all_ground(e.args)
+         case SHIFT_LEFT_OP =>  all_ground(e.args)
+         case SHIFT_RIGHT_OP =>  all_ground(e.args)
+         case CONVERT_OP =>  all_ground(e.args)
+         case NEG_OP =>  all_ground(e.args)
+         case NOT_OP =>  all_ground(e.args)
+         case AND_OP =>  all_ground(e.args)
+         case OR_OP =>  all_ground(e.args)
+         case XOR_OP =>  all_ground(e.args)
+         case AND_REDUCE_OP =>  all_ground(e.args)
+         case OR_REDUCE_OP =>  all_ground(e.args)
+         case XOR_REDUCE_OP =>  all_ground(e.args)
+         case CONCAT_OP =>  all_ground(e.args)
+         case BITS_SELECT_OP =>  all_ground(e.args)
+         case HEAD_OP =>  all_ground(e.args)
+         case TAIL_OP =>  all_ground(e.args)
+      }
+   }
+      
+   def run (c:Circuit) : Circuit = {
+      val errors = ArrayBuffer[PassException]()
+      def passive (t:Type) : Boolean = {
+         (t) match { 
+            case (_:UIntType|_:SIntType) => true
+            case (t:VectorType) => passive(t.tpe)
+            case (t:BundleType) => {
+               var p = true
+               for (x <- t.fields ) {
+                  if (x.flip == REVERSE) p = false
+                  if (!passive(x.tpe)) p = false
+               }
+               p
+            }
+            case (t) => true
+         }
+      }
+      def check_types_e (info:Info)(e:Expression) : Expression = {
+         (eMap(check_types_e(info) _,e)) match { 
+            case (e:WRef) => e
+            case (e:WSubField) => {
+               (tpe(e.exp)) match  { 
+                  case (t:BundleType) => {
+                     val ft = t.fields.find(p => p.name == e.name)
+                     if (ft == None) errors += new SubfieldNotInBundle(info,e.name)
+                  }
+                  case (t) => errors += new SubfieldOnNonBundle(info,e.name)
+               }
+            }
+            case (e:WSubIndex) => {
+               (tpe(e.exp)) match { 
+                  case (t:VectorType) => {
+                     if (e.value >= t.size) errors += new IndexTooLarge(info,e.value)
+                  }
+                  case (t) => errors += new IndexOnNonVector(info)
+               }
+            }
+            case (e:WSubAccess) => {
+               (tpe(e.exp)) match { 
+                  case (t:VectorType) => false
+                  case (t) => errors += new IndexOnNonVector(info)
+               }
+               (tpe(e.index)) match { 
+                  case (t:UIntType) => false
+                  case (t) => errors += new AccessIndexNotUInt(info)
+               }
+            }
+            case (e:DoPrim) => check_types_primop(e,errors,info)
+            case (e:Mux) => {
+               if (wt(tpe(e.tval)) != wt(tpe(e.fval))) errors += new MuxSameType(info)
+               if (!passive(tpe(e))) errors += new MuxPassiveTypes(info)
+               if (!passive(tpe(e))) errors += new MuxPassiveTypes(info)
+               if (!(tpe(e.cond).typeof[UIntType])) errors += new MuxCondUInt(info)
+            }
+            case (e:ValidIf) => {
+               if (!passive(tpe(e))) errors += new ValidIfPassiveTypes(info)
+               if (!(tpe(e.cond).typeof[UIntType])) errors += new ValidIfCondUInt(info)
+            }
+            case (_:UIntValue|_:SIntValue) => false
+         }
+         e
+      }
+   
+      def bulk_equals (t1:Type,t2:Type) : Boolean = {
+         (t1,t2) match { 
+            case (t1:BundleType,t2:BundleType) => {
+               var same = true
+               (t1.fields, t2.fields).zipped.map{ (f1,f2) => {
+                  if (f1.name == f2.name) {
+                     if (f1.flip != f2.flip) same = false
+                     if (!bulk_equals(f1.tpe,f2.tpe)) same = false
+                  }
+               }}
+               same
+            }
+            case (t1:ClockType,t2:ClockType) => true
+            case (t1:UIntType,t2:UIntType) => true
+            case (t1:SIntType,t2:SIntType) => true
+            case (t1:VectorType,t2:VectorType) => {
+               if (bulk_equals(t1.tpe,t2.tpe)) true
+               else false
+            }
+            case (t1,t2) => false
+         }
+      }
+           
+      def check_types_s (s:Stmt) : Stmt = {
+         eMap(check_types_e(get_info(s)) _,s) match { 
+            case (s:Connect) => if (wt(tpe(s.loc)) != wt(tpe(s.exp))) errors += new InvalidConnect(s.info)
+            case (s:BulkConnect) => if (!bulk_equals(tpe(s.loc),tpe(s.exp)) ) errors += new InvalidConnect(s.info)
+            case (s:Stop) => {
+               if (wt(tpe(s.clk)) != wt(ClockType()) ) errors += new ReqClk(s.info)
+               if (wt(tpe(s.en)) != wt(ut()) ) errors += new EnNotUInt(s.info)
+            }
+            case (s:Print)=> {
+               for (x <- s.args ) {
+                  if (wt(tpe(x)) != wt(ut()) && wt(tpe(x)) != wt(st()) ) errors += new PrintfArgNotGround(s.info)
+               }
+               if (wt(tpe(s.clk)) != wt(ClockType()) ) errors += new ReqClk(s.info)
+               if (wt(tpe(s.en)) != wt(ut()) ) errors += new EnNotUInt(s.info)
+            }
+            case (s:Conditionally) => if (wt(tpe(s.pred)) != wt(ut()) ) errors += new PredNotUInt(s.info)
+            case (s:DefNode) => if (!passive(tpe(s.value)) ) errors += new NodePassiveType(s.info)
+            case (s) => false
+         }
+         sMap(check_types_s,s)
+      }
+      
+      for (m <- c.modules ) {
+         mname = m.name
+         (m) match { 
+            case (m:ExModule) => false
+            case (m:InModule) => check_types_s(m.body)
+         }
+      }
+      if (errors.nonEmpty) throw new PassExceptions(errors)
+      c
+   }
+}
+
+/*
+object CheckGenders extends Pass {
+   def name = "Check Genders"
+   class WrongGender (info:Info,expr:String,wrong:String,right:String) extends PassException(s"${info}: [module ${mname}  Expression ${expr} is used as a ${wrong} but can only be used as a ${right}.")
+   
+   def dir-to-gender (d:Direction) : Gender = {
+      d match {
+         case INPUT => MALE
+         case OUTPUT => FEMALE //BI-GENDER
+      }
+   }
+   
+   def as-srcsnk (g:Gender) : String = {
+      g match {
+         case MALE => "source"
+         case FEMALE => "sink"
+         case UNKNOWNGENDER => "unknown"
+         case BIGENDER => "sourceOrSink"
+      }
+   }
+   
+   def run (c:Circuit): Circuit = {
+      val errors = ArrayBuffer[PassException]()
+      def get-kind (e:Expression) : Kind = {
+         (e) match { 
+            case (e:WRef) => e.kind
+            case (e:WSubField) => get-kind(e.exp)
+            case (e:WSubIndex) => get-kind(e.exp)
+            case (e:WSubAccess) => get-kind(e.exp)
+            case (e) => NodeKind()
+         }
+      }
+   
+      def check-gender (info:Info,genders:HashMap[String,Gender],desired:Gender)(e:Expression) : Unit = {
+         val gender = get-gender(e,genders)
+         val kindx = get-kind(e)
+         def flipQ (t:Type) : Boolean = {
+            var fQ = false
+            def flip-rec (t:Type,f:Flip) : Type =
+               (t) match { 
+                  case (t:BundleType) => {
+                     for (field <- t.fields) {
+                        flip-rec(field.tpe,times(f, field.flip))
+                     }
+                  }
+                  case (t:VectorType) => flip-rec(t.tpe,f)
+                  case (t) => if (f == REVERSE) fQ = true
+               }
+               t
+            }
+            flip-rec(t,DEFAULT)
+            fQ
+         }
+            
+         val has-flipQ = flipQ(tpe(e))
+         //println(e)
+         //println(gender)
+         //println(desired)
+         //println(kindx)
+         //println(desired == gender)
+         //if gender != desired and gender != BI-GENDER:
+         (gender,desired) match {
+            case (MALE, FEMALE) => errors += WrongGender(info,e.serialize(),as-srcsnk(desired),as-srcsnk(gender))
+            case (FEMALE, MALE) =>
+               if ((kindx == PortKind() or kindx == InstanceKind()) && has-flipQ == false) {
+                  //; OK!
+                  false
+               } else {
+                  //; Not Ok!
+                  add(errors,WrongGender(info,to-symbol(e),as-srcsnk(desired),as-srcsnk(gender)))
+               }
+            case _ => false
+         }
+      }
+   
+      def get-gender (e:Expression,genders:HashMap[String,Gender]) : Gender = {
+         (e) match { 
+            case (e:WRef) => genders(e.name)
+            case (e:WSubField) => 
+               val f = tpe(e.exp).as[BundleType].get.fields.find(f => f.name == e.name)
+               times(get-gender(e.exp,genders),f.flip)
+            case (e:WSubIndex) => get-gender(e.exp,genders)
+            case (e:WSubAccess) => get-gender(e.exp,genders)
+            case (e:DoPrim) => MALE
+            case (e:UIntValue) => MALE
+            case (e:SIntValue) => MALE
+            case (e:Mux) => MALE
+            case (e:ValidIf) => MALE
+         }
+      }
+   
+      def check-genders-e (info:Info,genders:HashMap[String,Gender])(e:Expression) : Expression = {
+         eMap(check-genders-e(info,genders) _,e)
+         (e) match { 
+            case (e:WRef) => false
+            case (e:WSubField) => false
+            case (e:WSubIndex) => false
+            case (e:WSubAccess) => false
+            case (e:DoPrim) => 
+               for e in args(e) do :
+                  check-gender(info,genders,MALE)(e)
+            case (e:Mux) => eMap(check-gender(info,genders,MALE) _,e)
+            case (e:ValidIf) => eMap(check-gender(info,genders,MALE) _,e)
+            case (e:UIntValue) => false
+            case (e:SIntValue) => false
+         }
+         e
+      }
+        
+      def check-genders-s (genders:HashMap[String,Gender])(s:Stmt) : Stmt = {
+         eMap(check-genders-e(get_info(s),genders) _,s)
+         sMap(check-genders-s(genders) _,s)
+         (s) match { 
+            case (s:DefWire) => genders(s.name) = BIGENDER
+            case (s:DefPoison) => genders(s.name) = MALE
+            case (s:DefRegister) => genders(s.name) = BIGENDER
+            case (s:DefNode) => {
+               check-gender(s.info,genders,MALE)(s.value)
+               genders(s.name) = MALE
+            }
+            case (s:DefMemory) => genders(s.name) = MALE
+            case (s:WDefInstance) => genders(s.name) = MALE
+            case (s:Connect) => {
+               check-gender(s.info,genders,FEMALE)(s.loc)
+               check-gender(s.info,genders,MALE)(s.exp)
+            }
+            case (s:Print) => {
+               for (x <- s.args ) {
+                  check-gender(s.info,genders,MALE)(x)
+               }
+               check-gender(s.info,genders,MALE)(s.en)
+               check-gender(s.info,genders,MALE)(s.clk)
+            }
+            case (s:BulkConnect) => {
+               check-gender(s.info,genders,FEMALE)(s.loc)
+               check-gender(s.info,genders,MALE)(s.exp)
+            }
+            case (s:Conditionally) => {
+               check-gender(s.info,genders,MALE)(s.pred)
+            }
+            case (s:Empty) => false
+            case (s:Stop) => {
+               check-gender(s.info,genders,MALE)(s.en)
+               check-gender(s.info,genders,MALE)(s.clk)
+            }
+            case (_:Begin|_:IsInvalid) => false
+         }
+         s
+      }
+   
+      for (m <- c.modules ) {
+         mname = m.name
+         val genders = HashMap[String,Gender]()
+         for (p <- m.ports) {
+            genders(p.name) = dir-to-gender(p.direction)
+         }
+         (m) match { 
+            case (m:ExModule) => false
+            case (m:InModule) => check-genders-s(genders)(m.body)
+         }
+      }
+      if (errors.nonEmpty) throw new PassExceptions(errors)
+      c
+   }
+}
+
+object CheckWidths extends Pass with StanzaPass {
+   def name = "Width Check"
+   def run (c:Circuit): Circuit = stanzaPass(c, "width-check")
+   defn UninferredWidth (info:Info) :
+      PassException $ string-join $
+      [info ": [module " mname "]  Uninferred width."]
+   
+   defn WidthTooSmall (info:Info,v:String) :
+      PassException $ string-join $
+      [info ": [module " mname "]  Width too small for constant " v "."]
+   
+   ;---------------- Helper Functions --------------
+   
+   ;--------------- Check Width Pass -------------------
+   public def check-width (c:Circuit) : Circuit = 
+      val errors = ArrayBuffer[PassException]()
+   
+      def check-width-m (m:Module) : Unit =
+         def check-width-w (info:Info,w:Width) : Width =
+            (w) match { 
+               (w:IntWidth) :
+                  if width(w) <= to-long(0) : add(errors,NegWidth())
+               (w) : 
+                  add(errors,UninferredWidth(info))
+            w
+   
+         def check-width-e (info:Info,e:Expression) : Expression =
+            (map(check-width-e{info,_},e)) match { 
+               (e:UIntValue) : 
+                  (width(e)) match { 
+                     (w:IntWidth) : 
+                        if max(to-long(1),to-long(req-num-bits(value(e)) - 1)) > width(w) : 
+                           add(errors,WidthTooSmall(info,to-string(value(e))))
+                     (w) : add(errors,UninferredWidth(info))
+                  check-width-w(info,width(e))
+               (e:SIntValue) : 
+                  (width(e)) match { 
+                     (w:IntWidth) : 
+                        if to-long(req-num-bits(value(e))) > width(w) : 
+                           add(errors,WidthTooSmall(info,to-string(value(e))))
+                     (w) : add(errors,UninferredWidth(info))
+                  check-width-w(info,width(e))
+               (e:DoPrim) : false
+               (e) : false
+   
+            ;mapr(check-width-w{info,_},type(map(check-width-e{info,_},e)))
+            e
+            
+         def check-width-s (s:Stmt) : Stmt =
+            sinfo! = info(s)
+            map(check-width-e{info(s),_},map(check-width-s,s))
+            map(mapr{check-width-w{info(s),_},_:Type},s)
+      
+         for p in ports(m) do :
+            mapr(check-width-w{info(p),_},type(p))
+   
+         (m) match { 
+            (m:ExModule) : false
+            (m:InModule) : check-width-s(body(m))
+         false
+      
+      for m in modules(c) do :
+         mname = name(m)
+         check-width-m(m)
+      throw(PassExceptions(errors)) when not empty?(errors)
+      c
+   }
+}
+
+object CheckInitialization extends Pass with StanzaPass {
+   def name = "Check Initialization"
+   def run (c:Circuit): Circuit = {
+   defn RefNotInitialized (info:Info, name:String) :
+      PassException $ string-join $
+      [info ": [module " mname "]  Reference " name " is not fully initialized."]
+   
+   ;------------ Helper Functions -------------
+   
+   ;------------ Pass ------------------
+   
+   public def check-init (c:Circuit) : 
+      val errors = ArrayBuffer[PassException]()
+      
+      def check-init-m (m:InModule) : 
+         def get-name (e:Expression) : String =
+            (e) match { 
+               (e:WRef) : name(e)
+               (e:WSubField) : symbol-join([get-name(exp(e)) `. name(e)])
+               (e:WSubIndex) : symbol-join([get-name(exp(e)) to-symbol("[") value(e) to-symbol("]")])
+               (e) : error("Shouldn't be here")
+         def has-void? (e:Expression) : Boolean =
+            var void? = false
+            def has-void (e:Expression) : Expression =
+               (e) match { 
+                  (e:WVoid) : 
+                     void? = true
+                     e
+                  (e) : map(has-void,e)
+            has-void(e)
+            void?
+         def check-init-s (s:Stmt) : Stmt =
+            (s) match { 
+               (s:Connect) : 
+                  if has-void?(exp(s)) : add(errors,RefNotInitialized(info(s),get-name(loc(s))))
+                  s
+               (s) : map(check-init-s,s)
+   
+         check-init-s(body(m))
+         
+      for m in modules(c) do :
+         mname = name(m)
+         (m) match  { 
+            (m:InModule) : check-init-m(m)
+            (m) : false
+   
+      throw(PassExceptions(errors)) when not empty?(errors)
+      c
+   }
+}
+*/
diff --git a/src/main/scala/firrtl/passes/Passes.scala b/src/main/scala/firrtl/passes/Passes.scala
index de07aaab..452b994f 100644
--- a/src/main/scala/firrtl/passes/Passes.scala
+++ b/src/main/scala/firrtl/passes/Passes.scala
@@ -252,10 +252,6 @@ object InferTypes extends Pass {
       Circuit(c.info,modulesx.map({m => mname = m.name; infer_types(m)}) , c.main )
    }
 }
-object CheckTypes extends Pass with StanzaPass {
-  def name = "Check Types"
-  def run (c:Circuit): Circuit = stanzaPass(c, "check-types")
-}
 
 object ResolveGenders extends Pass {
    private var mname = ""
@@ -320,11 +316,6 @@ object ResolveGenders extends Pass {
    }
 }
 
-object CheckGenders extends Pass with StanzaPass {
-   def name = "Check Genders"
-   def run (c:Circuit): Circuit = stanzaPass(c, "check-genders")
-}
-
 object InferWidths extends Pass {
    def name = "Infer Widths"
    var mname = ""
@@ -623,11 +614,6 @@ object InferWidths extends Pass {
    }
 }
 
-object CheckWidths extends Pass with StanzaPass {
-   def name = "Width Check"
-   def run (c:Circuit): Circuit = stanzaPass(c, "width-check")
-}
-
 object PullMuxes extends Pass {
    private var mname = ""
    def name = "Pull Muxes"
@@ -1114,11 +1100,6 @@ object ExpandWhens extends Pass {
    }
 }
 
-object CheckInitialization extends Pass with StanzaPass {
-   def name = "Check Initialization"
-   def run (c:Circuit): Circuit = stanzaPass(c, "check-init")
-}
-
 object ConstProp extends Pass {
    def name = "Constant Propogation"
    var mname = ""