Wrapped delay in ifndef verilator, as it is not supported by verilator

1 files changed, 3 insertions, 1 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 82b307ba..5be17cd1 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -554,7 +554,9 @@ class VerilogEmitter extends Emitter {
             emit(Seq("`ifndef SYNTHESIS"))
             emit(Seq("  integer initvar;"))
             emit(Seq("  initial begin"))
-            emit(Seq("    #0.002;"))
+            emit(Seq("    `ifndef verilator"))
+            emit(Seq("      #0.002;"))
+            emit(Seq("    `endif"))
             for (x <- initials) {
                emit(Seq(tab,x))
             }