Add guard to emission of simulation constructs

1 files changed, 9 insertions, 3 deletions

diff --git a/src/main/scala/firrtl/Emitter.scala b/src/main/scala/firrtl/Emitter.scala
index 79b1847d..82b307ba 100644
--- a/src/main/scala/firrtl/Emitter.scala
+++ b/src/main/scala/firrtl/Emitter.scala
@@ -55,7 +55,7 @@ object FIRRTLEmitter extends Emitter {
 case class VIndent()
 case class VRandom()
 class VerilogEmitter extends Emitter {
-   val tab = "   "
+   val tab = "  "
    val ran = VRandom()
    var w:Option[Writer] = None
    var mname = ""
@@ -344,10 +344,16 @@ class VerilogEmitter extends Emitter {
       def simulate (clk:Expression,en:Expression,s:Seq[Any]) = {
          if (!at_clock.contains(clk)) at_clock(clk) = ArrayBuffer[Seq[Any]]()
          at_clock(clk) += Seq("`ifndef SYNTHESIS")
-         at_clock(clk) += Seq(tab,"if(",en,") begin")
-         at_clock(clk) += Seq(tab,tab,s)
+         at_clock(clk) += Seq("`ifdef PRINTF_COND")
+         at_clock(clk) += Seq(tab,"if (`PRINTF_COND) begin")
+         at_clock(clk) += Seq("`endif")
+         at_clock(clk) += Seq(tab,tab,"if (",en,") begin")
+         at_clock(clk) += Seq(tab,tab,tab,s)
+         at_clock(clk) += Seq(tab,tab,"end")
+         at_clock(clk) += Seq("`ifdef PRINTF_COND")
          at_clock(clk) += Seq(tab,"end")
          at_clock(clk) += Seq("`endif")
+         at_clock(clk) += Seq("`endif")
       }
       def stop (ret:Int) : Seq[Any] = {
          Seq("$fdisplay(32'h80000002,\"",ret,"\");$finish;")