diff options
| author | azidar | 2015-05-18 16:04:58 -0700 |
|---|---|---|
| committer | azidar | 2015-05-18 16:04:58 -0700 |
| commit | 3336e6beb23e1ba883097eac0c0000269bf8ebfa (patch) | |
| tree | c97d9ba8d0e50476e2d32a150fe401cc7413cff8 | |
| parent | 2702e571040e7a07317b79f9c5cfdbd61b9ab2bf (diff) | |
Big API Change. Pad is no longer supported. Widths of primops can be flexible, and the output is usually the max of the inputs. Removed all u/s variants, which need to be dealt with in backends where it matters
37 files changed, 438 insertions, 958 deletions
@@ -3,6 +3,7 @@ ================================================ ======== Current Tasks ======== +Temp elimination needs to count # uses Declared references needs to understand scope <= check in high form check Size of vector type must be non-negative Check for recursively defined instances @@ -69,6 +70,7 @@ Width inference All widths are positive Pad's width is greater than value's width pad's width is greater than value's width + connect can connect from big to small?? Check Gender ======== Other Passes ======== diff --git a/spec/spec.tex b/spec/spec.tex index 3d4611e2..2930e3c8 100644 --- a/spec/spec.tex +++ b/spec/spec.tex @@ -754,15 +754,15 @@ The output width of a dynamic shift left operation is the width of the original \[ \begin{array}{rll} \kws{primop} & \kws{Resultant Type} & \kws{Resultant Width} \\ -\kws{dshr}(\pds{op}:UInt, \pds{op2}:UInt) & UInt & width(op) - pow(2,width(op2)) \\ -\kws{dshr}(\pds{op}:SInt, \pds{op2}:UInt) & SInt & width(op) - pow(2,width(op2)) \\ +\kws{dshr}(\pds{op}:UInt, \pds{op2}:UInt) & UInt & width(op) \\ +\kws{dshr}(\pds{op}:SInt, \pds{op2}:UInt) & SInt & width(op) \\ \end{array} \] The shift right operation accepts either an unsigned or a signed integer, plus a non-negative integer literal specifying the number of bits to shift. The resultant value has the same type as the operand. The shift amount must be less than or equal to the width of the operand. The output of a shift right operation is equal to the original signal with the least significant $n$ bits truncated, where $n$ is the dynamic shift amount. -The output width of a dynamic shift right operation is the width of the original signal minus 2 raised to the width of the dynamic shift amount. +The output width of a dynamic shift right operation is the width of the original signal. \subsection{Convert to Signed} \[ @@ -792,7 +792,7 @@ If the input type is SInt, primop returns -1 * input value, as an SInt with the \[ \begin{array}{rll} \kws{primop} & \kws{Resultant Type} & \kws{Resultant Width} \\ -\kws{bit-not} (\pds{op1:UInt}, \pds{op2:UInt}) & UInt & max(width(op1),width(op2)) \\ +\kws{bit-not} (\pds{op1:UInt}) & UInt & width(op1) \\ \kws{bit-and} (\pds{op1:UInt}, \pds{op2:UInt}) & UInt & max(width(op1),width(op2)) \\ \kws{bit-or} (\pds{op1:UInt}, \pds{op2:UInt}) & UInt & max(width(op1),width(op2)) \\ \kws{bit-xor} (\pds{op1:UInt}, \pds{op2:UInt}) & UInt & max(width(op1),width(op2)) \\ @@ -805,7 +805,6 @@ The operands must be unsigned integers, and the resultant width is equal to the \[ \begin{array}{rll} \kws{primop} & \kws{Resultant Type} & \kws{Resultant Width} \\ -\kws{bit-not-reduce} (\pds{op:UInt}*) & UInt & max(width(op)*) \\ \kws{bit-and-reduce} (\pds{op:UInt}*) & UInt & max(width(op)*) \\ \kws{bit-or-reduce} (\pds{op:UInt}*) & UInt & max(width(op)*) \\ \kws{bit-xor-reduce} (\pds{op:UInt}*) & UInt & max(width(op)*) \\ diff --git a/src/main/stanza/errors.stanza b/src/main/stanza/errors.stanza index 06c09522..a1d230c9 100644 --- a/src/main/stanza/errors.stanza +++ b/src/main/stanza/errors.stanza @@ -47,6 +47,7 @@ defpackage firrtl/errors : public defstruct CheckHighForm <: Pass public defmethod pass (b:CheckHighForm) -> (Circuit -> Circuit) : check-high-form public defmethod name (b:CheckHighForm) -> String : "High Form Check" +public defmethod short-name (b:CheckHighForm) -> String : "high-form-check" ;----------------- Errors ------------------------ defn NotUnique (info:FileInfo, name:Symbol) : @@ -139,7 +140,7 @@ public defn check-high-form (c:Circuit) -> Circuit : defn check-valid-loc (info:FileInfo,e:Expression) -> False : match(e) : - (e:UIntValue|SIntValue|DoPrim|ReadPort|Register|Pad) : + (e:UIntValue|SIntValue|DoPrim|ReadPort|Register) : add(errors,InvalidLOC(info)) (e) : false @@ -180,10 +181,13 @@ public defn check-high-form (c:Circuit) -> Circuit : (s:DefInstance) : if not contains?(name(module(s) as Ref),map(name,modules(c))) : add(errors, ModuleNotDefined(info(s),name(module(s) as Ref))) + check-name(info(s),name(s)) add(names,name(s)) (s:DefNode) : + check-name(info(s),name(s)) add(names,name(s)) (s:DefAccessor) : + check-name(info(s),name(s)) add(names,name(s)) (s:Connect) : check-valid-loc(info(s),loc(s)) @@ -227,6 +231,7 @@ public defn check-high-form (c:Circuit) -> Circuit : public defstruct CheckKinds <: Pass public defmethod pass (b:CheckKinds) -> (Circuit -> Circuit) : check-kinds public defmethod name (b:CheckKinds) -> String : "Check Kinds" +public defmethod short-name (b:CheckKinds) -> String : "check-kinds" ;----------------- Errors --------------------- defn NotMem (info:FileInfo, name:Symbol) : @@ -279,8 +284,8 @@ public defn check-kinds (c:Circuit) -> Circuit : check-is-mem(info,mem(e)) check-not-mem(info,index(e)) check-not-mem(info,enable(e)) - (e:Pad) : - check-not-mem(info,value(e)) + ;(e:Pad) : + ;check-not-mem(info,value(e)) (e) : do(check-not-mem{info,_},e) defn check-kinds-s (s:Stmt) -> False : do(check-kinds-e{info(s),_:Expression},s) @@ -316,6 +321,7 @@ public defn check-kinds (c:Circuit) -> Circuit : public defstruct CheckTypes <: Pass public defmethod pass (b:CheckTypes) -> (Circuit -> Circuit) : check-types public defmethod name (b:CheckTypes) -> String : "Check Types" +public defmethod short-name (b:CheckTypes) -> String : "check-types" ;----------------- Errors --------------------- defn SubfieldNotInBundle (info:FileInfo, name:Symbol) : @@ -342,9 +348,9 @@ defn EnableNotUInt (info:FileInfo) : PassException $ string-join $ [info ": Enable is not of UIntType."] -defn PadNotGround (info:FileInfo) : - PassException $ string-join $ - [info ": Illegal Pad on non-ground type."] +;defn PadNotGround (info:FileInfo) : + ;PassException $ string-join $ + ;[info ": Illegal Pad on non-ground type."] defn InvalidConnect (info:FileInfo) : PassException $ string-join $ @@ -397,9 +403,9 @@ public defn check-types (c:Circuit) -> Circuit : if type(enable(e)) != u() : add(errors,EnableNotUInt(info)) (e:Register) : if type(enable(e)) != u() : add(errors,EnableNotUInt(info)) - (e:Pad) : - val t = type(value(e)) - if not (t == u() or t == s()) : add(errors,PadNotGround(info)) + ;(e:Pad) : + ;val t = type(value(e)) + ;if not (t == u() or t == s()) : add(errors,PadNotGround(info)) (e:UIntValue|SIntValue) : false e defn check-types-s (s:Stmt) -> Stmt : @@ -430,6 +436,7 @@ public defn check-types (c:Circuit) -> Circuit : public defstruct CheckGenders <: Pass public defmethod pass (b:CheckGenders) -> (Circuit -> Circuit) : check-genders public defmethod name (b:CheckGenders) -> String : "Check Genders" +public defmethod short-name (b:CheckGenders) -> String : "check-genders" ;----------------- Errors --------------------- defn WrongGender (info:FileInfo,expr:Symbol,wrong:Symbol,right:Symbol) : @@ -462,7 +469,7 @@ public defn check-genders (c:Circuit) -> Circuit : val f = {_ as Field} $ for f in fields(type(exp(e)) as BundleType) find : name(f) == name(e) get-gender(exp(e),genders) * flip(f) (e:WIndex) : get-gender(exp(e),genders) - (e:Pad) : MALE + ;(e:Pad) : MALE (e:DoPrim) : MALE (e:UIntValue) : MALE (e:SIntValue) : MALE @@ -476,7 +483,7 @@ public defn check-genders (c:Circuit) -> Circuit : (e:WRef) : false (e:WSubfield) : false (e:WIndex) : false - (e:Pad) : check-gender(info,genders,value(e),MALE) + ;(e:Pad) : check-gender(info,genders,value(e),MALE) (e:DoPrim) : for e in args(e) do : check-gender(info,genders,e,MALE) diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza index 02145678..39538498 100644 --- a/src/main/stanza/firrtl-ir.stanza +++ b/src/main/stanza/firrtl-ir.stanza @@ -20,106 +20,30 @@ public defstruct IntWidth <: Width : public definterface PrimOp public val ADD-OP = new PrimOp -public val ADD-UU-OP = new PrimOp -public val ADD-US-OP = new PrimOp -public val ADD-SU-OP = new PrimOp -public val ADD-SS-OP = new PrimOp public val SUB-OP = new PrimOp -public val SUB-UU-OP = new PrimOp -public val SUB-US-OP = new PrimOp -public val SUB-SU-OP = new PrimOp -public val SUB-SS-OP = new PrimOp public val MUL-OP = new PrimOp -public val MUL-UU-OP = new PrimOp -public val MUL-US-OP = new PrimOp -public val MUL-SU-OP = new PrimOp -public val MUL-SS-OP = new PrimOp public val DIV-OP = new PrimOp -public val DIV-UU-OP = new PrimOp -public val DIV-US-OP = new PrimOp -public val DIV-SU-OP = new PrimOp -public val DIV-SS-OP = new PrimOp public val MOD-OP = new PrimOp -public val MOD-UU-OP = new PrimOp -public val MOD-US-OP = new PrimOp -public val MOD-SU-OP = new PrimOp -public val MOD-SS-OP = new PrimOp public val QUO-OP = new PrimOp -public val QUO-UU-OP = new PrimOp -public val QUO-US-OP = new PrimOp -public val QUO-SU-OP = new PrimOp -public val QUO-SS-OP = new PrimOp public val REM-OP = new PrimOp -public val REM-UU-OP = new PrimOp -public val REM-US-OP = new PrimOp -public val REM-SU-OP = new PrimOp -public val REM-SS-OP = new PrimOp public val ADD-WRAP-OP = new PrimOp -public val ADD-WRAP-UU-OP = new PrimOp -public val ADD-WRAP-US-OP = new PrimOp -public val ADD-WRAP-SU-OP = new PrimOp -public val ADD-WRAP-SS-OP = new PrimOp public val SUB-WRAP-OP = new PrimOp -public val SUB-WRAP-UU-OP = new PrimOp -public val SUB-WRAP-US-OP = new PrimOp -public val SUB-WRAP-SU-OP = new PrimOp -public val SUB-WRAP-SS-OP = new PrimOp public val LESS-OP = new PrimOp -public val LESS-UU-OP = new PrimOp -public val LESS-US-OP = new PrimOp -public val LESS-SU-OP = new PrimOp -public val LESS-SS-OP = new PrimOp public val LESS-EQ-OP = new PrimOp -public val LESS-EQ-UU-OP = new PrimOp -public val LESS-EQ-US-OP = new PrimOp -public val LESS-EQ-SU-OP = new PrimOp -public val LESS-EQ-SS-OP = new PrimOp public val GREATER-OP = new PrimOp -public val GREATER-UU-OP = new PrimOp -public val GREATER-US-OP = new PrimOp -public val GREATER-SU-OP = new PrimOp -public val GREATER-SS-OP = new PrimOp public val GREATER-EQ-OP = new PrimOp -public val GREATER-EQ-UU-OP = new PrimOp -public val GREATER-EQ-US-OP = new PrimOp -public val GREATER-EQ-SU-OP = new PrimOp -public val GREATER-EQ-SS-OP = new PrimOp public val NEQUAL-OP = new PrimOp -public val NEQUAL-UU-OP = new PrimOp -public val NEQUAL-SS-OP = new PrimOp public val EQUAL-OP = new PrimOp -public val EQUAL-UU-OP = new PrimOp -public val EQUAL-SS-OP = new PrimOp public val MUX-OP = new PrimOp -public val MUX-UU-OP = new PrimOp -public val MUX-SS-OP = new PrimOp public val PAD-OP = new PrimOp -public val PAD-U-OP = new PrimOp -public val PAD-S-OP = new PrimOp public val AS-UINT-OP = new PrimOp -public val AS-UINT-U-OP = new PrimOp -public val AS-UINT-S-OP = new PrimOp public val AS-SINT-OP = new PrimOp -public val AS-SINT-U-OP = new PrimOp -public val AS-SINT-S-OP = new PrimOp public val DYN-SHIFT-LEFT-OP = new PrimOp -public val DYN-SHIFT-LEFT-U-OP = new PrimOp -public val DYN-SHIFT-LEFT-S-OP = new PrimOp public val DYN-SHIFT-RIGHT-OP = new PrimOp -public val DYN-SHIFT-RIGHT-U-OP = new PrimOp -public val DYN-SHIFT-RIGHT-S-OP = new PrimOp public val SHIFT-LEFT-OP = new PrimOp -public val SHIFT-LEFT-U-OP = new PrimOp -public val SHIFT-LEFT-S-OP = new PrimOp public val SHIFT-RIGHT-OP = new PrimOp -public val SHIFT-RIGHT-U-OP = new PrimOp -public val SHIFT-RIGHT-S-OP = new PrimOp public val NEG-OP = new PrimOp -public val NEG-U-OP = new PrimOp -public val NEG-S-OP = new PrimOp public val CONVERT-OP = new PrimOp -public val CONVERT-U-OP = new PrimOp -public val CONVERT-S-OP = new PrimOp public val BIT-NOT-OP = new PrimOp public val BIT-AND-OP = new PrimOp public val BIT-OR-OP = new PrimOp @@ -170,10 +94,6 @@ public defstruct Register <: Expression : type: Type with: (as-method => true) value: Expression enable: Expression -public defstruct Pad <: Expression : - value: Expression - width: Width - type: Type with: (as-method => true) public definterface Stmt public defmulti info (s:Stmt) -> FileInfo diff --git a/src/main/stanza/firrtl-test-main.stanza b/src/main/stanza/firrtl-test-main.stanza index 7f578772..1b15c6b1 100644 --- a/src/main/stanza/firrtl-test-main.stanza +++ b/src/main/stanza/firrtl-test-main.stanza @@ -34,7 +34,8 @@ defn set-printvars! (p:List<Char>) : defn get-passes (pass-names:List<String>) -> List<Pass> : for n in pass-names map : - val p = for p in standard-passes find : n == short-name(p) + val p = for p in standard-passes find : + n == short-name(p) if p == false : error(to-string $ ["Unrecognized pass flag: " n]) p as Pass diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza index d98ed0ce..47f8b29d 100644 --- a/src/main/stanza/flo.stanza +++ b/src/main/stanza/flo.stanza @@ -14,78 +14,33 @@ public defmethod name (b:Flo) -> String : "To Flo" defn flo-op-name (op:PrimOp) -> String : switch {op == _ } : - ;NEG-OP : "neg" - ;NEG-OP : "neg" - ;NEG-OP : "neg" - ;NEG-OP : "neg" - ADD-UU-OP : "add" - ADD-US-OP : "add" - ADD-SU-OP : "add" - ADD-SS-OP : "add" - ADD-WRAP-UU-OP : "add" - ADD-WRAP-US-OP : "add" - ADD-WRAP-SU-OP : "add" - ADD-WRAP-SS-OP : "add" - SUB-UU-OP : "sub" - SUB-US-OP : "sub" - SUB-SU-OP : "sub" - SUB-SS-OP : "sub" - SUB-WRAP-UU-OP : "sub" - SUB-WRAP-US-OP : "sub" - SUB-WRAP-SU-OP : "sub" - SUB-WRAP-SS-OP : "sub" - MUL-UU-OP : "mul" ;; todo: signed version - MUL-US-OP : "mul" ;; todo: signed version - MUL-SU-OP : "mul" ;; todo: signed version - MUL-SS-OP : "mul" ;; todo: signed version - DIV-UU-OP : "div" ;; todo: signed version - DIV-US-OP : "div" ;; todo: signed version - DIV-SU-OP : "div" ;; todo: signed version - DIV-SS-OP : "div" ;; todo: signed version - MOD-UU-OP : "mod" ;; todo: signed version - MOD-US-OP : "mod" ;; todo: signed version - MOD-SU-OP : "mod" ;; todo: signed version - MOD-SS-OP : "mod" ;; todo: signed version - LESS-UU-OP : "lt" ;; todo: signed version - LESS-US-OP : "lt" ;; todo: signed version - LESS-SU-OP : "lt" ;; todo: signed version - LESS-SS-OP : "lt" ;; todo: signed version - LESS-EQ-UU-OP : "lte" ;; todo: swap args - LESS-EQ-US-OP : "lte" ;; todo: swap args - LESS-EQ-SU-OP : "lte" ;; todo: swap args - LESS-EQ-SS-OP : "lte" ;; todo: swap args - GREATER-UU-OP : "lt" ;; todo: swap args - GREATER-US-OP : "lt" ;; todo: swap args - GREATER-SU-OP : "lt" ;; todo: swap args - GREATER-SS-OP : "lt" ;; todo: swap args - GREATER-EQ-UU-OP : "lte" ;; todo: signed version - GREATER-EQ-US-OP : "lte" ;; todo: signed version - GREATER-EQ-SU-OP : "lte" ;; todo: signed version - GREATER-EQ-SS-OP : "lte" ;; todo: signed version - NEQUAL-UU-OP : "neq" - NEQUAL-SS-OP : "neq" - EQUAL-UU-OP : "eq" - EQUAL-SS-OP : "eq" - MUX-UU-OP : "mux" - MUX-SS-OP : "mux" - PAD-U-OP : "rsh" ;; todo: signed version - PAD-S-OP : "rsh" ;; todo: signed version - NEG-U-OP : "neg" - NEG-S-OP : "neg" + ADD-OP : "add" + ADD-WRAP-OP : "add" + SUB-OP : "sub" + SUB-WRAP-OP : "sub" + MUL-OP : "mul" ;; todo: signed version + DIV-OP : "div" ;; todo: signed version + MOD-OP : "mod" ;; todo: signed version + QUO-OP : "div" ;; todo: signed version + REM-OP : "mod" ;; todo: signed version + LESS-OP : "lt" ;; todo: signed version + LESS-EQ-OP : "lte" ;; todo: swap args + GREATER-OP : "lt" ;; todo: swap args + GREATER-EQ-OP : "lte" ;; todo: signed version + NEQUAL-OP : "neq" + EQUAL-OP : "eq" + MUX-OP : "mux" + PAD-OP : "rsh" ;; todo: signed version + NEG-OP : "neg" ;AS-UINT-U-OP : ;AS-UINT-S-OP : ;AS-SINT-U-OP : ;AS-SINT-S-OP : - SHIFT-LEFT-U-OP : "lsh" - SHIFT-LEFT-S-OP : "lsh" - SHIFT-RIGHT-U-OP : "rsh" - SHIFT-RIGHT-S-OP : "arsh" - DYN-SHIFT-LEFT-U-OP : "lsh" - DYN-SHIFT-LEFT-S-OP : "lsh" - DYN-SHIFT-RIGHT-U-OP : "rsh" - DYN-SHIFT-RIGHT-S-OP : "arsh" + SHIFT-LEFT-OP : "lsh" + SHIFT-RIGHT-OP : "rsh" + DYN-SHIFT-LEFT-OP : "lsh" + DYN-SHIFT-RIGHT-OP : "rsh" ;CONVERT-U-OP : - ;CONVERT-S-OP : BIT-AND-OP : "and" BIT-NOT-OP : "not" BIT-OR-OP : "or" @@ -121,24 +76,24 @@ defn emit-all (es:Streamable, top:Symbol) : defn emit! (e:Expression,top:Symbol) : defn greater-op? (op: PrimOp) -> True|False : - contains?([GREATER-OP, GREATER-UU-OP, GREATER-US-OP, GREATER-SU-OP, GREATER-SS-OP], op) + contains?([GREATER-OP], op) defn greater-eq-op? (op: PrimOp) -> True|False : - contains?([GREATER-EQ-OP, GREATER-EQ-UU-OP, GREATER-EQ-US-OP, GREATER-EQ-SU-OP, GREATER-EQ-SS-OP], op) + contains?([GREATER-EQ-OP], op) defn less-eq-op? (op: PrimOp) -> True|False : - contains?([LESS-EQ-OP, LESS-EQ-UU-OP, LESS-EQ-US-OP, LESS-EQ-SS-OP, LESS-EQ-SS-OP], op) + contains?([LESS-EQ-OP], op) defn less-op? (op: PrimOp) -> True|False : - contains?([LESS-OP, LESS-UU-OP, LESS-US-OP, LESS-SS-OP, LESS-SS-OP], op) + contains?([LESS-OP], op) defn cmp-op? (op: PrimOp) -> True|False : greater-op?(op) or greater-eq-op?(op) or less-op?(op) or less-eq-op?(op) or - contains?([EQUAL-OP, EQUAL-UU-OP, EQUAL-SS-OP, NEQUAL-OP, NEQUAL-UU-OP, NEQUAL-SS-OP], op) + contains?([EQUAL-OP NEQUAL-OP] op) match(e) : (e:Ref) : emit-all([top "::" name(e)], top) (e:UIntValue) : emit-all([value(e) "'" sane-width(width(e))], top) (e:SIntValue) : emit-all([value(e) "'" sane-width(width(e))], top) (e:Subfield) : emit-all([exp(e) "/" name(e)], top) (e:Index) : emit-all([exp(e) "/" value(e)], top) - (e:Pad) : - emit-all(["rsh'" prim-width(type(e)) " " value(e) " 0"], top) + ;(e:Pad) : + ;emit-all(["rsh'" prim-width(type(e)) " " value(e) " 0"], top) (e:Register) : emit-all(["reg'" prim-width(type(e)) " " enable(e) " " value(e)], top) (e:ReadPort) : @@ -160,14 +115,14 @@ defn emit! (e:Expression,top:Symbol) : ;; emit-all([flo-op-name(op(e)) "'" w " " args(e)[0] " " consts(e)[1]], top) else : emit-all([flo-op-name(op(e)) "'" prim-width(type(e))], top) - if (op(e) == PAD-U-OP) or (op(e) == PAD-S-OP) : - emit-all([" " args(e)[0] " " consts(e)[0]], top) - else : - for arg in args(e) do : - print(" ") - emit!(arg, top) - for const in consts(e) do : - print-all([" " const "'" sizeof(const)]) + ;if (op(e) == PAD-U-OP) or (op(e) == PAD-S-OP) : + ;emit-all([" " args(e)[0] " " consts(e)[0]], top) + ;else : + for arg in args(e) do : + print(" ") + emit!(arg, top) + for const in consts(e) do : + print-all([" " const "'" sizeof(const)]) (e) : error("SHOULDN'T EMIT THIS") ;; print-all(["EMIT(" e ")"]) ;(e) : emit-all(["mov'" prim-width(type(e)) " " e], top) ;TODO, not sure which one is right diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza index 15cc497a..0833543f 100644 --- a/src/main/stanza/ir-parser.stanza +++ b/src/main/stanza/ir-parser.stanza @@ -32,106 +32,30 @@ defn atom? (x) : unwrap-token(x) not-typeof List defn primop (x:Symbol) : get?(OPERATORS, x, false) val OPERATORS = HashTable<Symbol, PrimOp>(symbol-hash) OPERATORS[`add] = ADD-OP -OPERATORS[`add-uu] = ADD-UU-OP -OPERATORS[`add-us] = ADD-US-OP -OPERATORS[`add-su] = ADD-SU-OP -OPERATORS[`add-ss] = ADD-SS-OP OPERATORS[`sub] = SUB-OP -OPERATORS[`sub-uu] = SUB-UU-OP -OPERATORS[`sub-us] = SUB-US-OP -OPERATORS[`sub-su] = SUB-SU-OP -OPERATORS[`sub-ss] = SUB-SS-OP OPERATORS[`mul] = MUL-OP -OPERATORS[`mul-uu] = MUL-UU-OP -OPERATORS[`mul-us] = MUL-US-OP -OPERATORS[`mul-su] = MUL-SU-OP -OPERATORS[`mul-ss] = MUL-SS-OP OPERATORS[`div] = DIV-OP -OPERATORS[`div-uu] = DIV-UU-OP -OPERATORS[`div-us] = DIV-US-OP -OPERATORS[`div-su] = DIV-SU-OP -OPERATORS[`div-ss] = DIV-SS-OP OPERATORS[`mod] = MOD-OP -OPERATORS[`mod-uu] = MOD-UU-OP -OPERATORS[`mod-us] = MOD-US-OP -OPERATORS[`mod-su] = MOD-SU-OP -OPERATORS[`mod-ss] = MOD-SS-OP OPERATORS[`quo] = QUO-OP -OPERATORS[`quo-uu] = QUO-UU-OP -OPERATORS[`quo-us] = QUO-US-OP -OPERATORS[`quo-su] = QUO-SU-OP -OPERATORS[`quo-ss] = QUO-SS-OP OPERATORS[`rem] = REM-OP -OPERATORS[`rem-uu] = REM-UU-OP -OPERATORS[`rem-us] = REM-US-OP -OPERATORS[`rem-su] = REM-SU-OP -OPERATORS[`rem-ss] = REM-SS-OP OPERATORS[`add-wrap] = ADD-WRAP-OP -OPERATORS[`add-wrap-uu] = ADD-WRAP-UU-OP -OPERATORS[`add-wrap-us] = ADD-WRAP-US-OP -OPERATORS[`add-wrap-su] = ADD-WRAP-SU-OP -OPERATORS[`add-wrap-ss] = ADD-WRAP-SS-OP OPERATORS[`sub-wrap] = SUB-WRAP-OP -OPERATORS[`sub-wrap-uu] = SUB-WRAP-UU-OP -OPERATORS[`sub-wrap-us] = SUB-WRAP-US-OP -OPERATORS[`sub-wrap-su] = SUB-WRAP-SU-OP -OPERATORS[`sub-wrap-ss] = SUB-WRAP-SS-OP OPERATORS[`lt] = LESS-OP -OPERATORS[`lt-uu] = LESS-UU-OP -OPERATORS[`lt-us] = LESS-US-OP -OPERATORS[`lt-su] = LESS-SU-OP -OPERATORS[`lt-ss] = LESS-SS-OP OPERATORS[`leq] = LESS-EQ-OP -OPERATORS[`leq-uu] = LESS-EQ-UU-OP -OPERATORS[`leq-us] = LESS-EQ-US-OP -OPERATORS[`leq-su] = LESS-EQ-SU-OP -OPERATORS[`leq-ss] = LESS-EQ-SS-OP OPERATORS[`gt] = GREATER-OP -OPERATORS[`gt-uu] = GREATER-UU-OP -OPERATORS[`gt-us] = GREATER-US-OP -OPERATORS[`gt-su] = GREATER-SU-OP -OPERATORS[`gt-ss] = GREATER-SS-OP OPERATORS[`geq] = GREATER-EQ-OP -OPERATORS[`geq-uu] = GREATER-EQ-UU-OP -OPERATORS[`geq-us] = GREATER-EQ-US-OP -OPERATORS[`geq-su] = GREATER-EQ-SU-OP -OPERATORS[`geq-ss] = GREATER-EQ-SS-OP OPERATORS[`eq] = EQUAL-OP -OPERATORS[`eq-uu] = EQUAL-UU-OP -OPERATORS[`eq-ss] = EQUAL-SS-OP OPERATORS[`neq] = NEQUAL-OP -OPERATORS[`neq-uu] = NEQUAL-UU-OP -OPERATORS[`neq-ss] = NEQUAL-SS-OP OPERATORS[`mux] = MUX-OP -OPERATORS[`mux-uu] = MUX-UU-OP -OPERATORS[`mux-ss] = MUX-SS-OP OPERATORS[`pad] = PAD-OP -OPERATORS[`pad-u] = PAD-U-OP -OPERATORS[`pad-s] = PAD-S-OP OPERATORS[`neg] = NEG-OP -OPERATORS[`neg-u] = NEG-U-OP -OPERATORS[`neg-s] = NEG-S-OP OPERATORS[`as-UInt] = AS-UINT-OP -OPERATORS[`as-UInt-u] = AS-UINT-U-OP -OPERATORS[`as-UInt-s] = AS-UINT-S-OP OPERATORS[`as-SInt] = AS-SINT-OP -OPERATORS[`as-SInt-u] = AS-SINT-U-OP -OPERATORS[`as-SInt-s] = AS-SINT-S-OP OPERATORS[`dshl] = DYN-SHIFT-LEFT-OP -OPERATORS[`dshl-u] = DYN-SHIFT-LEFT-U-OP -OPERATORS[`dshl-s] = DYN-SHIFT-LEFT-S-OP OPERATORS[`dshr] = DYN-SHIFT-RIGHT-OP -OPERATORS[`dshr-u] = DYN-SHIFT-RIGHT-U-OP -OPERATORS[`dshr-s] = DYN-SHIFT-RIGHT-S-OP OPERATORS[`shl] = SHIFT-LEFT-OP -OPERATORS[`shl-u] = SHIFT-LEFT-U-OP -OPERATORS[`shl-s] = SHIFT-LEFT-S-OP OPERATORS[`shr] = SHIFT-RIGHT-OP -OPERATORS[`shr-u] = SHIFT-RIGHT-U-OP -OPERATORS[`shr-s] = SHIFT-RIGHT-S-OP OPERATORS[`convert] = CONVERT-OP -OPERATORS[`convert-u] = CONVERT-U-OP -OPERATORS[`convert-s] = CONVERT-S-OP OPERATORS[`bit-and-reduce] = BIT-AND-REDUCE-OP OPERATORS[`bit-or-reduce] = BIT-OR-REDUCE-OP OPERATORS[`bit-xor-reduce] = BIT-XOR-REDUCE-OP @@ -309,9 +233,6 @@ defsyntax firrtl : expterm = (Register(?v:#exp, ?e:#exp)) : Register(UnknownType(), v, e) expterm != (Register) : FPE(form, "Invalid syntax for Register expression.") - expterm = (Pad(?e:#exp, ?w:#width$)) : Pad(e,w,UnknownType()) - expterm != (Pad) : FPE(form, "Invalid syntax for Pad expression.") - expterm = (?op:#sym(?es:#exp ... ?ints:#int ... ?rest ...)) : if not empty?(rest) : FPE(rest, "Illegal operands to primitive operator.") diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza index 2f049203..d2afca05 100644 --- a/src/main/stanza/ir-utils.stanza +++ b/src/main/stanza/ir-utils.stanza @@ -40,6 +40,9 @@ public definterface Pass public defmulti pass (p:Pass) -> (Circuit -> Circuit) public defmulti name (p:Pass) -> String public defmulti short-name (p:Pass) -> String +public defmethod print (o:OutputStream, p:Pass) : + print(o,name(p)) + ;============== PRINTERS =================================== @@ -65,106 +68,30 @@ defmethod print (o:OutputStream, op:PrimOp) : print{o, _} $ switch {op == _} : ADD-OP : "add" - ADD-UU-OP : "add-uu" - ADD-US-OP : "add-us" - ADD-SU-OP : "add-su" - ADD-SS-OP : "add-ss" SUB-OP : "sub" - SUB-UU-OP : "sub-uu" - SUB-US-OP : "sub-us" - SUB-SU-OP : "sub-su" - SUB-SS-OP : "sub-ss" MUL-OP : "mul" - MUL-UU-OP : "mul-uu" - MUL-US-OP : "mul-us" - MUL-SU-OP : "mul-su" - MUL-SS-OP : "mul-ss" DIV-OP : "div" - DIV-UU-OP : "div-uu" - DIV-US-OP : "div-us" - DIV-SU-OP : "div-su" - DIV-SS-OP : "div-ss" MOD-OP : "mod" - MOD-UU-OP : "mod-uu" - MOD-US-OP : "mod-us" - MOD-SU-OP : "mod-su" - MOD-SS-OP : "mod-ss" QUO-OP : "quo" - QUO-UU-OP : "quo-uu" - QUO-US-OP : "quo-us" - QUO-SU-OP : "quo-su" - QUO-SS-OP : "quo-ss" REM-OP : "rem" - REM-UU-OP : "rem-uu" - REM-US-OP : "rem-us" - REM-SU-OP : "rem-su" - REM-SS-OP : "rem-ss" ADD-WRAP-OP : "add-wrap" - ADD-WRAP-UU-OP : "add-wrap-uu" - ADD-WRAP-US-OP : "add-wrap-us" - ADD-WRAP-SU-OP : "add-wrap-su" - ADD-WRAP-SS-OP : "add-wrap-ss" SUB-WRAP-OP : "sub-wrap" - SUB-WRAP-UU-OP : "sub-wrap-uu" - SUB-WRAP-US-OP : "sub-wrap-us" - SUB-WRAP-SU-OP : "sub-wrap-su" - SUB-WRAP-SS-OP : "sub-wrap-ss" LESS-OP : "lt" - LESS-UU-OP : "lt-uu" - LESS-US-OP : "lt-us" - LESS-SU-OP : "lt-su" - LESS-SS-OP : "lt-ss" LESS-EQ-OP : "leq" - LESS-EQ-UU-OP : "leq-uu" - LESS-EQ-US-OP : "leq-us" - LESS-EQ-SU-OP : "leq-su" - LESS-EQ-SS-OP : "leq-ss" GREATER-OP : "gt" - GREATER-UU-OP : "gt-uu" - GREATER-US-OP : "gt-us" - GREATER-SU-OP : "gt-su" - GREATER-SS-OP : "gt-ss" GREATER-EQ-OP : "geq" - GREATER-EQ-UU-OP : "geq-uu" - GREATER-EQ-US-OP : "geq-us" - GREATER-EQ-SU-OP : "geq-su" - GREATER-EQ-SS-OP : "geq-ss" EQUAL-OP : "eq" - EQUAL-UU-OP : "eq-uu" - EQUAL-SS-OP : "eq-ss" NEQUAL-OP : "neq" - NEQUAL-UU-OP : "neq-uu" - NEQUAL-SS-OP : "neq-ss" MUX-OP : "mux" - MUX-UU-OP : "mux-uu" - MUX-SS-OP : "mux-ss" PAD-OP : "pad" - PAD-U-OP : "pad-u" - PAD-S-OP : "pad-s" AS-UINT-OP : "as-UInt" - AS-UINT-U-OP : "as-UInt-u" - AS-UINT-S-OP : "as-UInt-s" AS-SINT-OP : "as-SInt" - AS-SINT-U-OP : "as-SInt-u" - AS-SINT-S-OP : "as-SInt-s" DYN-SHIFT-LEFT-OP : "dshl" - DYN-SHIFT-LEFT-U-OP : "dshl-u" - DYN-SHIFT-LEFT-S-OP : "dshl-s" DYN-SHIFT-RIGHT-OP : "dshr" - DYN-SHIFT-RIGHT-U-OP : "dshr-u" - DYN-SHIFT-RIGHT-S-OP : "dshr-s" SHIFT-LEFT-OP : "shl" - SHIFT-LEFT-U-OP : "shl-u" - SHIFT-LEFT-S-OP : "shl-s" SHIFT-RIGHT-OP : "shr" - SHIFT-RIGHT-U-OP : "shr-u" - SHIFT-RIGHT-S-OP : "shr-s" CONVERT-OP : "convert" - CONVERT-U-OP : "convert-u" - CONVERT-S-OP : "convert-s" NEG-OP : "neg" - NEG-U-OP : "neg-u" - NEG-S-OP : "neg-s" BIT-NOT-OP : "bit-not" BIT-AND-OP : "bit-and" BIT-OR-OP : "bit-or" @@ -190,7 +117,6 @@ defmethod print (o:OutputStream, e:Expression) : (e:ReadPort) : print-all(o, ["ReadPort(" mem(e) ", " index(e) ", " enable(e) ")"]) (e:WritePort) : print-all(o, ["WritePort(" mem(e) ", " index(e) ", " enable(e) ")"]) (e:Register) : print-all(o, ["Register(" value(e) ", " enable(e) ")"]) - (e:Pad) : print-all(o, ["Pad(" value(e) ", " width(e) ")"]) print-debug(o,e) defmethod print (o:OutputStream, c:Stmt) : @@ -295,7 +221,6 @@ defmethod map (f: Expression -> Expression, e:Expression) -> Expression : (e:ReadPort) : ReadPort(f(mem(e)), f(index(e)), type(e), f(enable(e))) (e:WritePort) : WritePort(f(mem(e)), f(index(e)), type(e), f(enable(e))) (e:Register) : Register(type(e),f(value(e)),f(enable(e))) - (e:Pad) : Pad(f(value(e)),width(e),type(e)) (e) : e public defmulti map<?T> (f: Expression -> Expression, c:?T&Stmt) -> T @@ -321,7 +246,6 @@ defmethod map (f: Width -> Width, c:Expression) -> Expression : match(c) : (c:UIntValue) : UIntValue(value(c),f(width(c))) (c:SIntValue) : SIntValue(value(c),f(width(c))) - (c:Pad) : Pad(value(c),f(width(c)),type(c)) (c) : c public defmulti map<?T> (f: Width -> Width, c:?T&Type) -> T @@ -341,7 +265,6 @@ defmethod map (f: Type -> Type, c:Expression) -> Expression : (c:ReadPort) : ReadPort(mem(c),index(c),f(type(c)),enable(c)) (c:WritePort) : WritePort(mem(c),index(c),f(type(c)),enable(c)) (c:Register) : Register(f(type(c)),value(c),enable(c)) - (c:Pad) : Pad(value(c),width(c),f(type(c))) (c) : c public defmulti map<?T> (f: Type -> Type, c:?T&Stmt) -> T diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza index 0e20cd4c..236addce 100644 --- a/src/main/stanza/passes.stanza +++ b/src/main/stanza/passes.stanza @@ -196,12 +196,12 @@ defn hasGender (e:?) : e typeof WRef|WSubfield|WIndex|WDefAccessor defn hasWidth (e:?) : - e typeof UIntType|SIntType|UIntValue|SIntValue|Pad + e typeof UIntType|SIntType|UIntValue|SIntValue defn hasType (e:?) : e typeof Ref|Subfield|Index|DoPrim|WritePort|ReadPort|WRef|WSubfield |WIndex|DefWire|DefRegister|DefMemory|Register - |VectorType|Port|Field|Pad + |VectorType|Port|Field defn hasKind (e:?) : e typeof WRef @@ -244,15 +244,15 @@ defmethod print (o:OutputStream, e:WIndex) : print-debug(o,e as ?) defmethod print (o:OutputStream, s:WDefAccessor) : - print-all(o,["accessor " name(s) " = " source(s) "[" index(s) "] @[" info(s) "]"]) + print-all(o,["accessor " name(s) " = " source(s) "[" index(s) "]"]) print-debug(o,s) defmethod print (o:OutputStream, c:ConnectToIndexed) : - print-all(o, [locs(c) "[" index(c) "] := " exp(c) " @[" info(c) "]"]) + print-all(o, [locs(c) "[" index(c) "] := " exp(c)]) print-debug(o,c as ?) defmethod print (o:OutputStream, c:ConnectFromIndexed) : - print-all(o, [loc(c) " := " exps(c) "[" index(c) "] @[" info(c) "]"]) + print-all(o, [loc(c) " := " exps(c) "[" index(c) "]" ]) print-debug(o,c as ?) defmethod map (f: Expression -> Expression, e: WSubfield) : @@ -482,7 +482,6 @@ defn infer-exp-types (e:Expression, l:List<KeyValue<Symbol,Type>>) -> Expression (e:ReadPort) : ReadPort(mem(e),index(e),get-vector-subtype(type(mem(e))),enable(e)) (e:WritePort) : WritePort(mem(e),index(e),get-vector-subtype(type(mem(e))),enable(e)) (e:Register) : Register(type(value(e)),value(e),enable(e)) - (e:Pad) : Pad(value(e),width(e),type(value(e))) (e:UIntValue|SIntValue) : e defn infer-types (s:Stmt, l:List<KeyValue<Symbol,Type>>) -> [Stmt List<KeyValue<Symbol,Type>>] : @@ -790,9 +789,9 @@ defn expand-expr (e:Expression) -> List<EF> : val exps = expand-expr(exp(e)) val len = num-elems(type(e)) headn(tailn(exps,len * value(e)),len) - (e:Pad) : - val v = exp(head(expand-expr(value(e)))) - list(EF(Pad(v,width(e),type(e)),DEFAULT)) + ;(e:Pad) : + ;val v = exp(head(expand-expr(value(e)))) + ;list(EF(Pad(v,width(e),type(e)),DEFAULT)) (e:DoPrim) : val args = for x in args(e) map : exp(head(expand-expr(x))) list(EF(DoPrim(op(e),args,consts(e),type(e)),DEFAULT)) @@ -931,7 +930,7 @@ public defmethod short-name (b:ExpandIndexedConnects) -> String : "expand-indexe defn expand-connect-indexed-stmt (s: Stmt) -> Stmt : defn equality (e1:Expression,e2:Expression) -> Expression : - DoPrim(EQUAL-UU-OP,list(e1,e2),List(),UIntType(UnknownWidth())) + DoPrim(EQUAL-OP,list(e1,e2),List(),UIntType(UnknownWidth())) defn get-name (e:Expression) -> Symbol : match(e) : (e:WRef) : symbol-join([name(e) `#]) @@ -1018,7 +1017,7 @@ defmethod equal? (e1:Expression,e2:Expression) -> True|False : (e1:WRef,e2:WRef) : name(e1) == name(e2) ;(e1:DoPrim,e2:DoPrim) : TODO (e1:WSubfield,e2:WSubfield) : name(e1) == name(e2) - (e1:Pad,e2:Pad) : width(e1) == width(e2) and value(e1) == value(e2) + ;(e1:Pad,e2:Pad) : width(e1) == width(e2) and value(e1) == value(e2) (e1:DoPrim,e2:DoPrim) : var are-equal? = op(e1) == op(e2) for (x in args(e1),y in args(e2)) do : @@ -1047,7 +1046,7 @@ defn OR (e1:Expression,e2:Expression) -> Expression : defn NOT (e1:Expression) -> Expression : if e1 == one : zero else if e1 == zero : one - else : DoPrim(EQUAL-UU-OP,list(e1,zero),list(),UIntType(IntWidth(1))) + else : DoPrim(EQUAL-OP,list(e1,zero),list(),UIntType(IntWidth(1))) defn children (e:Expression) -> List<Expression> : val es = Vector<Expression>() @@ -1144,7 +1143,7 @@ defn remove-nul (sv:SymbolicValue) -> SymbolicValue : defn to-exp (sv:SymbolicValue) -> Expression|False : match(remove-nul(sv)) : (sv:SVMux) : - DoPrim(MUX-UU-OP, + DoPrim(MUX-OP, list(pred(sv),to-exp(conseq(sv)) as Expression,to-exp(alt(sv)) as Expression), list(), UIntType(IntWidth(1))) @@ -1453,10 +1452,8 @@ defn apply (a:Int|False,b:Int|False, f: (Int,Int) -> Int) -> Int|False : if a typeof Int and b typeof Int : f(a as Int, b as Int) else : false -; TODO: I should make MaxWidth take a variable list of arguments, which would make it easier to write the simplify function. It looks like there isn't a bug in the algorithm, but simplification reallllly speeds it up. - -defn solve-constraints (l:List<WGeq>) -> HashTable<Symbol,Int> : +defn solve-constraints (l:List<WGeq>) -> HashTable<Symbol,Width> : defn contains? (n:Symbol,h:HashTable<Symbol,?>) -> True|False : key?(h,n) defn make-unique (ls:List<WGeq>) -> HashTable<Symbol,Width> : val h = HashTable<Symbol,Width>(symbol-hash) @@ -1533,34 +1530,6 @@ defn solve-constraints (l:List<WGeq>) -> HashTable<Symbol,Int> : w look(w) has? - defn evaluate (h:HashTable<Symbol,Width>) -> HashTable<Symbol,Int> : - defn apply (a:Int|False,f:(Int) -> Int) -> Int|False : - if a typeof Int : f(a as Int) - else : false - defn apply (a:Int|False,b:Int|False, f: (Int,Int) -> Int) -> Int|False : - if a typeof Int and b typeof Int : f(a as Int, b as Int) - else : false - defn apply-l (l:List<Int|False>,f:(Int,Int) -> Int) -> Int|False : - if length(l) == 0 : 0 - else : apply(head(l),apply-l(tail(l),f),f) - defn max (a:Int,b:Int) -> Int : - if a >= b : a - else : b - defn solve (w:Width) -> Int|False : - match(w) : - (w:VarWidth) : false - (w:MaxWidth) : apply-l(map(solve,args(w)),max) - (w:PlusWidth) : apply(solve(arg1(w)),solve(arg2(w)),{_ + _}) - (w:MinusWidth) : apply(solve(arg1(w)),solve(arg2(w)),{_ - _}) - (w:ExpWidth) : apply(2,solve(arg1(w)),{pow(_,_) - 1}) - (w:IntWidth) : width(w) - (w) : error("Shouldn't be here") - - val i = HashTable<Symbol,Int>(symbol-hash) - for x in h do : - val s = solve(value(x)) - if s typeof Int : i[key(x)] = s as Int - i ; Forward solve ; Returns a solved list where each constraint undergoes: @@ -1613,11 +1582,7 @@ defn solve-constraints (l:List<WGeq>) -> HashTable<Symbol,Int> : for x in b do : println-debug(x) println-debug("=========================") - ; Evaluate - val e = evaluate(b) - println-debug("Evaluated Constraints") - for x in e do : println-debug(x) - e + b public defn width! (t:Type) -> Width : match(t) : @@ -1652,15 +1617,15 @@ defn gen-constraints (m:Module, h:HashTable<Symbol,Type>, v:Vector<WGeq>) -> Mod (e:WSubfield) : WSubfield(exp(e),name(e),bundle-field-type(type(exp(e)),name(e)),gender(e)) (e:WIndex) : error("Shouldn't be here") (e:DoPrim) : DoPrim(op(e),args(e),consts(e),primop-gen-constraints(e,v)) - (e:Pad) : - val value-w = width!(value(e)) - val pad-w = remove-unknowns-w(width(e)) - add(v,WGeq(pad-w, value-w)) - val pad-t = match(type(e)) : - (t:UIntType) : UIntType(pad-w) - (t:SIntType) : SIntType(pad-w) - (t) : error("Shouldn't be here") - Pad(value(e),pad-w,pad-t) + ;(e:Pad) : + ; val value-w = width!(value(e)) + ; val pad-w = remove-unknowns-w(width(e)) + ; add(v,WGeq(pad-w, value-w)) + ; val pad-t = match(type(e)) : + ; (t:UIntType) : UIntType(pad-w) + ; (t:SIntType) : SIntType(pad-w) + ; (t) : error("Shouldn't be here") + ; Pad(value(e),pad-w,pad-t) (e:ReadPort) : ReadPort(mem(e),index(e),type(type(mem(e)) as VectorType),enable(e)) (e:WritePort) : WritePort(mem(e),index(e),type(type(mem(e)) as VectorType),enable(e)) (e:Register) : Register(type(value(e)),value(e),enable(e)) @@ -1699,21 +1664,47 @@ defn build-environment (c:Circuit,m:Module,h:HashTable<Symbol,Type>) -> HashTabl build-environment(body(m)) h -defn replace-var-widths (c:Circuit,h:HashTable<Symbol,Int>) -> Circuit : - defn replace-var-widths-w (w:Width) -> Width : +defn reduce-var-widths (c:Circuit,h:HashTable<Symbol,Width>) -> Circuit : + defn evaluate (w:Width) -> Width : + defn apply (a:Int|False,f:(Int) -> Int) -> Int|False : + if a typeof Int : f(a as Int) + else : false + defn apply (a:Int|False,b:Int|False, f: (Int,Int) -> Int) -> Int|False : + if a typeof Int and b typeof Int : f(a as Int, b as Int) + else : false + defn apply-l (l:List<Int|False>,f:(Int,Int) -> Int) -> Int|False : + if length(l) == 0 : 0 + else : apply(head(l),apply-l(tail(l),f),f) + defn max (a:Int,b:Int) -> Int : + if a >= b : a + else : b + defn solve (w:Width) -> Int|False : + match(w) : + (w:VarWidth) : + val w* = h[name(w)] + if w* typeof VarWidth : false + else : solve(w*) + (w:MaxWidth) : apply-l(map(solve,args(w)),max) + (w:PlusWidth) : apply(solve(arg1(w)),solve(arg2(w)),{_ + _}) + (w:MinusWidth) : apply(solve(arg1(w)),solve(arg2(w)),{_ - _}) + (w:ExpWidth) : apply(2,solve(arg1(w)),{pow(_,_) - 1}) + (w:IntWidth) : width(w) + (w) : error("Shouldn't be here") + + val s = solve(w) + if s typeof Int : IntWidth(s as Int) + else : w + + defn reduce-var-widths-w (w:Width) -> Width : println-all-debug(["REPLACE: " w]) - val w* = match(w) : - (w:VarWidth) : - if key?(h,name(w)) : IntWidth(h[name(w)]) - else: w - (w) : w + val w* = evaluate(w) println-all-debug(["WITH: " w*]) w* val modules* = for m in modules(c) map : - Module{info(m),name(m),_,mapr(replace-var-widths-w,body(m))} $ + Module{info(m),name(m),_,mapr(reduce-var-widths-w,body(m))} $ for p in ports(m) map : - Port(info(p),name(p),direction(p),mapr(replace-var-widths-w,type(p))) + Port(info(p),name(p),direction(p),mapr(reduce-var-widths-w,type(p))) Circuit(info(c),modules*,main(c)) @@ -1751,7 +1742,7 @@ defn infer-widths (c:Circuit) -> Circuit : println-debug("======== SOLVED CONSTRAINTS ========") for x in h do : println-debug(x) println-debug("====================================") - replace-var-widths(Circuit(info(c),modules*,main(c)),h) + reduce-var-widths(Circuit(info(c),modules*,main(c)),h) ;================= Inline Instances ======================== @@ -1835,7 +1826,7 @@ defn split-exp (c:Circuit) : false defn split-exp-e (e:Expression,v:Vector<Stmt>,n:Symbol|False,info:FileInfo) -> Expression : match(map(split-exp-e{_,v,n,info},e)): - (e:Subfield|DoPrim|Pad|ReadPort|Register|WritePort) : + (e:Subfield|DoPrim|ReadPort|Register|WritePort) : val n* = if n typeof False : firrtl-gensym(`T) else : firrtl-gensym(symbol-join([n as Symbol `#])) diff --git a/src/main/stanza/primop.stanza b/src/main/stanza/primop.stanza index a06c9b3f..023723b8 100644 --- a/src/main/stanza/primop.stanza +++ b/src/main/stanza/primop.stanza @@ -23,348 +23,109 @@ public defn lower-and-type-primop (e:DoPrim) -> DoPrim : ;println-all(["Inferencing primop type: " e]) switch {op(e) == _} : - ADD-OP : - DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType, t2:UIntType) : ADD-UU-OP - (t1:UIntType, t2:SIntType) : ADD-US-OP - (t1:SIntType, t2:UIntType) : ADD-SU-OP - (t1:SIntType, t2:SIntType) : ADD-SS-OP - ADD-UU-OP : DoPrim(op(e),args(e),consts(e),u()) - ADD-US-OP : DoPrim(op(e),args(e),consts(e),s()) - ADD-SU-OP : DoPrim(op(e),args(e),consts(e),s()) - ADD-SS-OP : DoPrim(op(e),args(e),consts(e),s()) - SUB-OP : - DoPrim{_,args(e),consts(e),s()} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType, t2:UIntType) : SUB-UU-OP - (t1:UIntType, t2:SIntType) : SUB-US-OP - (t1:SIntType, t2:UIntType) : SUB-SU-OP - (t1:SIntType, t2:SIntType) : SUB-SS-OP - SUB-UU-OP : DoPrim(op(e),args(e),consts(e),s()) - SUB-US-OP : DoPrim(op(e),args(e),consts(e),s()) - SUB-SU-OP : DoPrim(op(e),args(e),consts(e),s()) - SUB-SS-OP : DoPrim(op(e),args(e),consts(e),s()) - MUL-OP : - DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType, t2:UIntType) : MUL-UU-OP - (t1:UIntType, t2:SIntType) : MUL-US-OP - (t1:SIntType, t2:UIntType) : MUL-SU-OP - (t1:SIntType, t2:SIntType) : MUL-SS-OP - MUL-UU-OP : DoPrim(op(e),args(e),consts(e),u()) - MUL-US-OP : DoPrim(op(e),args(e),consts(e),s()) - MUL-SU-OP : DoPrim(op(e),args(e),consts(e),s()) - MUL-SS-OP : DoPrim(op(e),args(e),consts(e),s()) - DIV-OP : - DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType, t2:UIntType) : DIV-UU-OP - (t1:UIntType, t2:SIntType) : DIV-US-OP - (t1:SIntType, t2:UIntType) : DIV-SU-OP - (t1:SIntType, t2:SIntType) : DIV-SS-OP - DIV-UU-OP : DoPrim(op(e),args(e),consts(e),u()) - DIV-US-OP : DoPrim(op(e),args(e),consts(e),s()) - DIV-SU-OP : DoPrim(op(e),args(e),consts(e),s()) - DIV-SS-OP : DoPrim(op(e),args(e),consts(e),s()) - MOD-OP : - DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType, t2:UIntType) : MOD-UU-OP - (t1:UIntType, t2:SIntType) : MOD-US-OP - (t1:SIntType, t2:UIntType) : MOD-SU-OP - (t1:SIntType, t2:SIntType) : MOD-SS-OP - MOD-UU-OP : DoPrim(op(e),args(e),consts(e),u()) - MOD-US-OP : DoPrim(op(e),args(e),consts(e),u()) - MOD-SU-OP : DoPrim(op(e),args(e),consts(e),s()) - MOD-SS-OP : DoPrim(op(e),args(e),consts(e),s()) - QUO-OP : - DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType, t2:UIntType) : QUO-UU-OP - (t1:UIntType, t2:SIntType) : QUO-US-OP - (t1:SIntType, t2:UIntType) : QUO-SU-OP - (t1:SIntType, t2:SIntType) : QUO-SS-OP - QUO-UU-OP : DoPrim(op(e),args(e),consts(e),u()) - QUO-US-OP : DoPrim(op(e),args(e),consts(e),s()) - QUO-SU-OP : DoPrim(op(e),args(e),consts(e),s()) - QUO-SS-OP : DoPrim(op(e),args(e),consts(e),s()) - REM-OP : - DoPrim{_,args(e),consts(e),of-type(args(e)[1])} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType, t2:UIntType) : REM-UU-OP - (t1:UIntType, t2:SIntType) : REM-US-OP - (t1:SIntType, t2:UIntType) : REM-SU-OP - (t1:SIntType, t2:SIntType) : REM-SS-OP - REM-UU-OP : DoPrim(op(e),args(e),consts(e),u()) - REM-US-OP : DoPrim(op(e),args(e),consts(e),s()) - REM-SU-OP : DoPrim(op(e),args(e),consts(e),u()) - REM-SS-OP : DoPrim(op(e),args(e),consts(e),s()) - ADD-WRAP-OP : - DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType, t2:UIntType) : ADD-WRAP-UU-OP - (t1:UIntType, t2:SIntType) : ADD-WRAP-US-OP - (t1:SIntType, t2:UIntType) : ADD-WRAP-SU-OP - (t1:SIntType, t2:SIntType) : ADD-WRAP-SS-OP - ADD-WRAP-UU-OP : DoPrim(op(e),args(e),consts(e),u()) - ADD-WRAP-US-OP : DoPrim(op(e),args(e),consts(e),s()) - ADD-WRAP-SU-OP : DoPrim(op(e),args(e),consts(e),s()) - ADD-WRAP-SS-OP : DoPrim(op(e),args(e),consts(e),s()) - SUB-WRAP-OP : - DoPrim{_,args(e),consts(e),u-and(args(e)[0],args(e)[1])} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType, t2:UIntType) : SUB-WRAP-UU-OP - (t1:UIntType, t2:SIntType) : SUB-WRAP-US-OP - (t1:SIntType, t2:UIntType) : SUB-WRAP-SU-OP - (t1:SIntType, t2:SIntType) : SUB-WRAP-SS-OP - SUB-WRAP-UU-OP : DoPrim(op(e),args(e),consts(e),u()) - SUB-WRAP-US-OP : DoPrim(op(e),args(e),consts(e),s()) - SUB-WRAP-SU-OP : DoPrim(op(e),args(e),consts(e),s()) - SUB-WRAP-SS-OP : DoPrim(op(e),args(e),consts(e),s()) - LESS-OP : - DoPrim{_,args(e),consts(e),u()} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType, t2:UIntType) : LESS-UU-OP - (t1:UIntType, t2:SIntType) : LESS-US-OP - (t1:SIntType, t2:UIntType) : LESS-SU-OP - (t1:SIntType, t2:SIntType) : LESS-SS-OP - LESS-UU-OP : DoPrim(op(e),args(e),consts(e),u()) - LESS-US-OP : DoPrim(op(e),args(e),consts(e),u()) - LESS-SU-OP : DoPrim(op(e),args(e),consts(e),u()) - LESS-SS-OP : DoPrim(op(e),args(e),consts(e),u()) - LESS-EQ-OP : - DoPrim{_,args(e),consts(e),u()} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType, t2:UIntType) : LESS-EQ-UU-OP - (t1:UIntType, t2:SIntType) : LESS-EQ-US-OP - (t1:SIntType, t2:UIntType) : LESS-EQ-SU-OP - (t1:SIntType, t2:SIntType) : LESS-EQ-SS-OP - LESS-EQ-UU-OP : DoPrim(op(e),args(e),consts(e),u()) - LESS-EQ-US-OP : DoPrim(op(e),args(e),consts(e),u()) - LESS-EQ-SU-OP : DoPrim(op(e),args(e),consts(e),u()) - LESS-EQ-SS-OP : DoPrim(op(e),args(e),consts(e),u()) - GREATER-OP : - DoPrim{_,args(e),consts(e),u()} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType, t2:UIntType) : GREATER-UU-OP - (t1:UIntType, t2:SIntType) : GREATER-US-OP - (t1:SIntType, t2:UIntType) : GREATER-SU-OP - (t1:SIntType, t2:SIntType) : GREATER-SS-OP - GREATER-UU-OP : DoPrim(op(e),args(e),consts(e),u()) - GREATER-US-OP : DoPrim(op(e),args(e),consts(e),u()) - GREATER-SU-OP : DoPrim(op(e),args(e),consts(e),u()) - GREATER-SS-OP : DoPrim(op(e),args(e),consts(e),u()) - GREATER-EQ-OP : - DoPrim{_,args(e),consts(e),u()} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType, t2:UIntType) : GREATER-EQ-UU-OP - (t1:UIntType, t2:SIntType) : GREATER-EQ-US-OP - (t1:SIntType, t2:UIntType) : GREATER-EQ-SU-OP - (t1:SIntType, t2:SIntType) : GREATER-EQ-SS-OP - GREATER-EQ-UU-OP : DoPrim(op(e),args(e),consts(e),u()) - GREATER-EQ-US-OP : DoPrim(op(e),args(e),consts(e),u()) - GREATER-EQ-SU-OP : DoPrim(op(e),args(e),consts(e),u()) - GREATER-EQ-SS-OP : DoPrim(op(e),args(e),consts(e),u()) - EQUAL-OP : - DoPrim{_,args(e),consts(e),u()} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType, t2:UIntType) : EQUAL-UU-OP - (t1:SIntType, t2:SIntType) : EQUAL-SS-OP - EQUAL-UU-OP : DoPrim(op(e),args(e),consts(e),u()) - EQUAL-SS-OP : DoPrim(op(e),args(e),consts(e),u()) - NEQUAL-OP : - DoPrim{_,args(e),consts(e),u()} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType, t2:UIntType) : NEQUAL-UU-OP - (t1:SIntType, t2:SIntType) : NEQUAL-SS-OP - NEQUAL-UU-OP : DoPrim(op(e),args(e),consts(e),u()) - NEQUAL-SS-OP : DoPrim(op(e),args(e),consts(e),u()) - MUX-OP : - DoPrim{_,args(e),consts(e),of-type(args(e)[1])} $ - match(type(args(e)[1]),type(args(e)[2])) : - (t1:UIntType, t2:UIntType) : MUX-UU-OP - (t1:SIntType, t2:SIntType) : MUX-SS-OP - (t1,t2) : error(to-string(args(e))) - MUX-UU-OP : DoPrim(op(e),args(e),consts(e),u()) - MUX-SS-OP : DoPrim(op(e),args(e),consts(e),s()) - PAD-OP : - DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $ - match(type(args(e)[0])) : - (t1:UIntType) : PAD-U-OP - (t1:SIntType) : PAD-S-OP - PAD-U-OP : DoPrim(op(e),args(e),consts(e),u()) - PAD-S-OP : DoPrim(op(e),args(e),consts(e),s()) - AS-UINT-OP : - DoPrim{_,args(e),consts(e),u()} $ - match(type(args(e)[0])) : - (t1:UIntType) : AS-UINT-U-OP - (t1:SIntType) : AS-UINT-S-OP - AS-UINT-U-OP : DoPrim(op(e),args(e),consts(e),u()) - AS-UINT-S-OP : DoPrim(op(e),args(e),consts(e),u()) - AS-SINT-OP : - DoPrim{_,args(e),consts(e),s()} $ - match(type(args(e)[0])) : - (t1:UIntType) : AS-SINT-U-OP - (t1:SIntType) : AS-SINT-S-OP - AS-SINT-U-OP : DoPrim(op(e),args(e),consts(e),s()) - AS-SINT-S-OP : DoPrim(op(e),args(e),consts(e),s()) - DYN-SHIFT-LEFT-OP : - DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType,t2:UIntType) : DYN-SHIFT-LEFT-U-OP - (t1:SIntType,t2:UIntType) : DYN-SHIFT-LEFT-S-OP - DYN-SHIFT-LEFT-U-OP : DoPrim(op(e),args(e),consts(e),u()) - DYN-SHIFT-LEFT-S-OP : DoPrim(op(e),args(e),consts(e),s()) - DYN-SHIFT-RIGHT-OP : - DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $ - match(type(args(e)[0]),type(args(e)[1])) : - (t1:UIntType,t2:UIntType) : DYN-SHIFT-RIGHT-U-OP - (t1:SIntType,t2:UIntType) : DYN-SHIFT-RIGHT-S-OP - DYN-SHIFT-RIGHT-U-OP : DoPrim(op(e),args(e),consts(e),u()) - DYN-SHIFT-RIGHT-S-OP : DoPrim(op(e),args(e),consts(e),s()) - SHIFT-LEFT-OP : - DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $ - match(type(args(e)[0])) : - (t1:UIntType) : SHIFT-LEFT-U-OP - (t1:SIntType) : SHIFT-LEFT-S-OP - SHIFT-LEFT-U-OP : DoPrim(op(e),args(e),consts(e),u()) - SHIFT-LEFT-S-OP : DoPrim(op(e),args(e),consts(e),s()) - SHIFT-RIGHT-OP : - DoPrim{_,args(e),consts(e),of-type(args(e)[0])} $ - match(type(args(e)[0])) : - (t1:UIntType) : SHIFT-RIGHT-U-OP - (t1:SIntType) : SHIFT-RIGHT-S-OP - SHIFT-RIGHT-U-OP : DoPrim(op(e),args(e),consts(e),u()) - SHIFT-RIGHT-S-OP : DoPrim(op(e),args(e),consts(e),s()) - CONVERT-OP : - DoPrim{_,args(e),consts(e),s()} $ - match(type(args(e)[0])) : - (t1:UIntType) : CONVERT-U-OP - (t1:SIntType) : CONVERT-S-OP - CONVERT-U-OP : DoPrim(op(e),args(e),consts(e),s()) - CONVERT-S-OP : DoPrim(op(e),args(e),consts(e),s()) - NEG-OP : - DoPrim{_,args(e),consts(e),u()} $ - match(type(args(e)[0])) : - (t1:UIntType) : NEG-U-OP - (t1:SIntType) : NEG-S-OP - NEG-U-OP : DoPrim(op(e),args(e),consts(e),u()) - NEG-S-OP : DoPrim(op(e),args(e),consts(e),u()) - BIT-NOT-OP : DoPrim(op(e),args(e),consts(e),u()) - BIT-AND-OP : DoPrim(op(e),args(e),consts(e),u()) - BIT-OR-OP : DoPrim(op(e),args(e),consts(e),u()) - BIT-XOR-OP : DoPrim(op(e),args(e),consts(e),u()) - CONCAT-OP : DoPrim(op(e),args(e),consts(e),u()) - BIT-SELECT-OP : DoPrim(op(e),args(e),consts(e),u()) - BITS-SELECT-OP : DoPrim(op(e),args(e),consts(e),u()) - BIT-AND-REDUCE-OP: DoPrim(op(e),args(e),consts(e),u()) - BIT-OR-REDUCE-OP : DoPrim(op(e),args(e),consts(e),u()) - BIT-XOR-REDUCE-OP: DoPrim(op(e),args(e),consts(e),u()) + ADD-OP : DoPrim(ADD-OP,args(e),consts(e),u-and(args(e)[0],args(e)[1])) + SUB-OP : DoPrim(SUB-OP,args(e),consts(e),s()) + MUL-OP : DoPrim(MUL-OP,args(e),consts(e),u-and(args(e)[0],args(e)[1])) + DIV-OP : DoPrim(DIV-OP,args(e),consts(e),u-and(args(e)[0],args(e)[1])) + MOD-OP : DoPrim(MOD-OP,args(e),consts(e),of-type(args(e)[0])) + QUO-OP : DoPrim(QUO-OP,args(e),consts(e),u-and(args(e)[0],args(e)[1])) + REM-OP : DoPrim(REM-OP,args(e),consts(e),of-type(args(e)[1])) + ADD-WRAP-OP : DoPrim(ADD-WRAP-OP,args(e),consts(e),u-and(args(e)[0],args(e)[1])) + SUB-WRAP-OP : DoPrim(SUB-WRAP-OP,args(e),consts(e),u-and(args(e)[0],args(e)[1])) + LESS-OP : DoPrim(LESS-OP,args(e),consts(e),u()) + LESS-EQ-OP : DoPrim(LESS-EQ-OP,args(e),consts(e),u()) + GREATER-OP : DoPrim(GREATER-OP,args(e),consts(e),u()) + GREATER-EQ-OP : DoPrim(GREATER-EQ-OP,args(e),consts(e),u()) + EQUAL-OP : DoPrim(EQUAL-OP,args(e),consts(e),u()) + NEQUAL-OP : DoPrim(NEQUAL-OP,args(e),consts(e),u()) + MUX-OP : DoPrim(MUX-OP,args(e),consts(e),of-type(args(e)[1])) + PAD-OP : DoPrim(PAD-OP,args(e),consts(e),of-type(args(e)[0])) + AS-UINT-OP : DoPrim(AS-UINT-OP,args(e),consts(e),u()) + AS-SINT-OP : DoPrim(AS-SINT-OP,args(e),consts(e),s()) + DYN-SHIFT-LEFT-OP : DoPrim(DYN-SHIFT-LEFT-OP,args(e),consts(e),of-type(args(e)[0])) + DYN-SHIFT-RIGHT-OP : DoPrim(DYN-SHIFT-RIGHT-OP,args(e),consts(e),of-type(args(e)[0])) + SHIFT-LEFT-OP : DoPrim(SHIFT-LEFT-OP,args(e),consts(e),of-type(args(e)[0])) + SHIFT-RIGHT-OP : DoPrim(SHIFT-RIGHT-OP,args(e),consts(e),of-type(args(e)[0])) + CONVERT-OP : DoPrim(CONVERT-OP,args(e),consts(e),s()) + NEG-OP : DoPrim(NEG-OP,args(e),consts(e),u()) + BIT-NOT-OP : DoPrim(op(e),args(e),consts(e),u()) + BIT-AND-OP : DoPrim(op(e),args(e),consts(e),u()) + BIT-OR-OP : DoPrim(op(e),args(e),consts(e),u()) + BIT-XOR-OP : DoPrim(op(e),args(e),consts(e),u()) + CONCAT-OP : DoPrim(op(e),args(e),consts(e),u()) + BIT-SELECT-OP : DoPrim(op(e),args(e),consts(e),u()) + BITS-SELECT-OP : DoPrim(op(e),args(e),consts(e),u()) + BIT-AND-REDUCE-OP : DoPrim(op(e),args(e),consts(e),u()) + BIT-OR-REDUCE-OP : DoPrim(op(e),args(e),consts(e),u()) + BIT-XOR-REDUCE-OP : DoPrim(op(e),args(e),consts(e),u()) public defn primop-gen-constraints (e:DoPrim,v:Vector<WGeq>) -> Type : - defn all-equal (ls:List<Width>) -> Width : - if length(ls) == 1 : (ls[0]) - else : - val m = MaxWidth(ls) - for (l in ls) do : - add(v,WGeq(l,m)) - m + defn get-max (i0:Int,i1:Int) -> Width : get-max(list(i0,i1)) + defn get-max (ls:List<Int>) -> Width : + MaxWidth $ for i in ls map : width!(args(e)[i]) + defn all-max () -> Width : + MaxWidth $ for x in args(e) map : width!(x) + println-all-debug(["Looking at " op(e) " with inputs " args(e)]) - val all-args-not-equal = to-list([MUX-UU-OP,MUX-SS-OP,CONCAT-OP,BIT-AND-OP,BIT-NOT-OP,BIT-OR-OP,BIT-XOR-OP,BIT-AND-REDUCE-OP,BIT-OR-REDUCE-OP,BIT-XOR-REDUCE-OP,AS-UINT-U-OP,AS-UINT-S-OP,AS-SINT-U-OP,AS-SINT-S-OP,DYN-SHIFT-LEFT-U-OP,DYN-SHIFT-LEFT-S-OP,DYN-SHIFT-RIGHT-U-OP,DYN-SHIFT-RIGHT-S-OP]) - - val w-var = VarWidth(gensym(`w)) - val w* = - if not contains?(all-args-not-equal,op(e)) : - val max-args-w = all-equal(map(width!,args(e))) - switch {op(e) == _} : - ADD-UU-OP : PlusWidth(max-args-w,IntWidth(1)) - ADD-US-OP : PlusWidth(max-args-w,IntWidth(1)) - ADD-SU-OP : PlusWidth(max-args-w,IntWidth(1)) - ADD-SS-OP : PlusWidth(max-args-w,IntWidth(1)) - SUB-UU-OP : PlusWidth(max-args-w,IntWidth(1)) - SUB-US-OP : PlusWidth(max-args-w,IntWidth(1)) - SUB-SU-OP : PlusWidth(max-args-w,IntWidth(1)) - SUB-SS-OP : PlusWidth(max-args-w,IntWidth(1)) - MUL-UU-OP : PlusWidth(max-args-w,max-args-w) - MUL-US-OP : PlusWidth(max-args-w,max-args-w) - MUL-SU-OP : PlusWidth(max-args-w,max-args-w) - MUL-SS-OP : PlusWidth(max-args-w,max-args-w) - DIV-UU-OP : max-args-w - DIV-US-OP : PlusWidth(max-args-w,IntWidth(1)) - DIV-SU-OP : max-args-w - DIV-SS-OP : PlusWidth(max-args-w,IntWidth(1)) - ADD-WRAP-UU-OP : max-args-w - ADD-WRAP-US-OP : max-args-w - ADD-WRAP-SU-OP : max-args-w - ADD-WRAP-SS-OP : max-args-w - SUB-WRAP-UU-OP : max-args-w - SUB-WRAP-US-OP : max-args-w - SUB-WRAP-SU-OP : max-args-w - SUB-WRAP-SS-OP : max-args-w - LESS-UU-OP : IntWidth(1) - LESS-US-OP : IntWidth(1) - LESS-SU-OP : IntWidth(1) - LESS-SS-OP : IntWidth(1) - LESS-EQ-UU-OP : IntWidth(1) - LESS-EQ-US-OP : IntWidth(1) - LESS-EQ-SU-OP : IntWidth(1) - LESS-EQ-SS-OP : IntWidth(1) - GREATER-UU-OP : IntWidth(1) - GREATER-US-OP : IntWidth(1) - GREATER-SU-OP : IntWidth(1) - GREATER-SS-OP : IntWidth(1) - GREATER-EQ-UU-OP : IntWidth(1) - GREATER-EQ-US-OP : IntWidth(1) - GREATER-EQ-SU-OP : IntWidth(1) - GREATER-EQ-SS-OP : IntWidth(1) - EQUAL-UU-OP : IntWidth(1) - EQUAL-SS-OP : IntWidth(1) - NEQUAL-UU-OP : IntWidth(1) - NEQUAL-SS-OP : IntWidth(1) - PAD-U-OP : IntWidth(consts(e)[0]) - PAD-S-OP : IntWidth(consts(e)[0]) - NEG-U-OP : PlusWidth(max-args-w,IntWidth(1)) - NEG-S-OP : PlusWidth(max-args-w,IntWidth(1)) - SHIFT-LEFT-U-OP : PlusWidth(max-args-w,IntWidth(consts(e)[0])) - SHIFT-LEFT-S-OP : PlusWidth(max-args-w,IntWidth(consts(e)[0])) - SHIFT-RIGHT-U-OP : MinusWidth(max-args-w,IntWidth(consts(e)[0])) - SHIFT-RIGHT-S-OP : MinusWidth(max-args-w,IntWidth(consts(e)[0])) - CONVERT-U-OP : PlusWidth(max-args-w,IntWidth(1)) - CONVERT-S-OP : max-args-w - BIT-SELECT-OP : IntWidth(1) - BITS-SELECT-OP : IntWidth(consts(e)[0] - consts(e)[1]) - else : - switch {op(e) == _} : - MUX-UU-OP : - add(v,WGeq(width!(args(e)[0]),IntWidth(1))) - all-equal(List(w-var,tail(map(width!,args(e))))) - MUX-SS-OP : - add(v,WGeq(width!(args(e)[0]),IntWidth(1))) - all-equal(List(w-var,tail(map(width!,args(e))))) - CONCAT-OP : - PlusWidth(width!(args(e)[0]),width!(args(e)[1])) - BIT-NOT-OP : all-equal(List(w-var,map(width!,args(e)))) - BIT-AND-OP : all-equal(List(w-var,map(width!,args(e)))) - BIT-OR-OP : all-equal(List(w-var,map(width!,args(e)))) - BIT-XOR-OP : all-equal(List(w-var,map(width!,args(e)))) - BIT-AND-REDUCE-OP : all-equal(List(w-var,map(width!,args(e)))) - BIT-OR-REDUCE-OP : all-equal(List(w-var,map(width!,args(e)))) - BIT-XOR-REDUCE-OP : all-equal(List(w-var,map(width!,args(e)))) - AS-UINT-U-OP : all-equal(List(w-var,map(width!,args(e)))) - AS-UINT-S-OP : all-equal(List(w-var,map(width!,args(e)))) - AS-SINT-U-OP : all-equal(List(w-var,map(width!,args(e)))) - AS-SINT-S-OP : all-equal(List(w-var,map(width!,args(e)))) - DYN-SHIFT-LEFT-U-OP : - PlusWidth(width!(args(e)[0]),ExpWidth(width!(args(e)[1]))) - DYN-SHIFT-LEFT-S-OP : - PlusWidth(width!(args(e)[0]),ExpWidth(width!(args(e)[1]))) - DYN-SHIFT-RIGHT-U-OP : width!(args(e)[0]) - DYN-SHIFT-RIGHT-S-OP : width!(args(e)[0]) + val w* = switch {op(e) == _} : + ADD-OP : PlusWidth(get-max(0,1),IntWidth(1)) + SUB-OP : PlusWidth(get-max(0,1),IntWidth(1)) + MUL-OP : PlusWidth(get-max(0,1),get-max(0,1)) + DIV-OP : + match(type(args(e)[0]),type(args(e)[1])) : + (t0:UIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) + (t0:SIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) + (t0,t1) : width!(args(e)[0]) + MOD-OP : + match(type(args(e)[0]),type(args(e)[1])) : + (t0:SIntType,t1:UIntType) : PlusWidth(width!(args(e)[1]),IntWidth(1)) + (t0,t1) : width!(args(e)[1]) + QUO-OP : + match(type(args(e)[0]),type(args(e)[1])) : + (t0:UIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) + (t0:SIntType,t1:SIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) + (t0,t1) : width!(args(e)[0]) + REM-OP : + match(type(args(e)[0]),type(args(e)[1])) : + (t0:SIntType,t1:UIntType) : PlusWidth(width!(args(e)[1]),IntWidth(1)) + (t0,t1) : width!(args(e)[1]) + ADD-WRAP-OP : get-max(0,1) + SUB-WRAP-OP : get-max(0,1) + LESS-OP : IntWidth(1) + LESS-EQ-OP : IntWidth(1) + GREATER-OP : IntWidth(1) + GREATER-EQ-OP : IntWidth(1) + EQUAL-OP : IntWidth(1) + NEQUAL-OP : IntWidth(1) + MUX-OP : + add(v,WGeq(IntWidth(1),width!(args(e)[0]))) + add(v,WGeq(width!(args(e)[0]),IntWidth(1))) + get-max(1,2) + PAD-OP : IntWidth(consts(e)[0]) + AS-UINT-OP : width!(args(e)[0]) + AS-SINT-OP : width!(args(e)[0]) + SHIFT-LEFT-OP : PlusWidth(width!(args(e)[0]),IntWidth(consts(e)[0])) + SHIFT-RIGHT-OP : MinusWidth(width!(args(e)[0]),IntWidth(consts(e)[0])) + DYN-SHIFT-LEFT-OP : PlusWidth(width!(args(e)[0]),ExpWidth(width!(args(e)[1]))) + DYN-SHIFT-RIGHT-OP : width!(args(e)[0]) + CONVERT-OP : + match(type(args(e)[0])) : + (t0:UIntType) : PlusWidth(width!(args(e)[0]),IntWidth(1)) + (t0:SIntType) : width!(args(e)[0]) + NEG-OP : PlusWidth(width!(args(e)[0]),IntWidth(1)) + BIT-NOT-OP : width!(args(e)[0]) + BIT-AND-OP : get-max(0,1) + BIT-OR-OP : get-max(0,1) + BIT-XOR-OP : get-max(0,1) + BIT-AND-REDUCE-OP : all-max() + BIT-OR-REDUCE-OP : all-max() + BIT-XOR-REDUCE-OP : all-max() + CONCAT-OP : PlusWidth(width!(args(e)[0]),width!(args(e)[1])) + BIT-SELECT-OP : IntWidth(1) + BITS-SELECT-OP : IntWidth(consts(e)[0] - consts(e)[1]) - add(v,WGeq(w-var,w*)) match(type(e)) : - (t:UIntType) : UIntType(w-var) - (t:SIntType) : SIntType(w-var) + (t:UIntType) : UIntType(w*) + (t:SIntType) : SIntType(w*) (t) : error("Shouldn't be here") diff --git a/test/passes/expand-connect-indexed/bundle-vecs.fir b/test/passes/expand-connect-indexed/bundle-vecs.fir index cb63cacf..7922c278 100644 --- a/test/passes/expand-connect-indexed/bundle-vecs.fir +++ b/test/passes/expand-connect-indexed/bundle-vecs.fir @@ -17,12 +17,12 @@ circuit top : ; CHECK: wire b$y : UInt<32> ; CHECK: b$x := a$0$x ; CHECK: node b$x#0 = i - ; CHECK: when eq-uu(b$x#0, UInt(1)) : + ; CHECK: when eq(b$x#0, UInt(1)) : ; CHECK: b$x := a$1$x ; CHECK: node b$y#0 = i - ; CHECK: when eq-uu(b$y#0, UInt(0)) : + ; CHECK: when eq(b$y#0, UInt(0)) : ; CHECK: a$0$y := b$y - ; CHECK: when eq-uu(b$y#0, UInt(1)) : + ; CHECK: when eq(b$y#0, UInt(1)) : ; CHECK: a$1$y := b$y j := b.x diff --git a/test/passes/expand-whens/bundle-init.fir b/test/passes/expand-whens/bundle-init.fir index c359d871..4f8c31e2 100644 --- a/test/passes/expand-whens/bundle-init.fir +++ b/test/passes/expand-whens/bundle-init.fir @@ -15,11 +15,11 @@ circuit top : r.y := b on-reset r := w -; CHECK: r$x := Register(mux-uu(reset, w$x, a), UInt(1)) +; CHECK: r$x := Register(mux(reset, w$x, a), UInt(1)) ; CHECK: r$y := Register(b, UInt(1)) ; CHECK: a := UInt(1) ; CHECK: b := UInt(2) ; CHECK: w$x := b -; CHECK: w$y := mux-uu(reset, r$y, a) +; CHECK: w$y := mux(reset, r$y, a) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/nested-whens.fir b/test/passes/expand-whens/nested-whens.fir index 2e8cc82a..f7ac8337 100644 --- a/test/passes/expand-whens/nested-whens.fir +++ b/test/passes/expand-whens/nested-whens.fir @@ -20,5 +20,5 @@ circuit top : on-reset r := y r := b r := z -; CHECK: r := Register(mux-uu(reset, mux-uu(q, y, mux-uu(p, x, w)), z), UInt(1)) +; CHECK: r := Register(mux(reset, mux(q, y, mux(p, x, w)), z), UInt(1)) ; CHECK: Finished Expand Whens diff --git a/test/passes/expand-whens/scoped-reg.fir b/test/passes/expand-whens/scoped-reg.fir index e209d94f..b71a5d50 100644 --- a/test/passes/expand-whens/scoped-reg.fir +++ b/test/passes/expand-whens/scoped-reg.fir @@ -7,6 +7,6 @@ circuit top : reg r : UInt on-reset r := UInt(10) r := UInt(20) -; CHECK: r := Register(mux-uu(reset, UInt(10), UInt(20)), mux-uu(reset, UInt(1), p)) +; CHECK: r := Register(mux(reset, UInt(10), UInt(20)), mux(reset, UInt(1), p)) ; CHECK: Finished Expand Whens diff --git a/test/passes/infer-types/gcd.fir b/test/passes/infer-types/gcd.fir index 23d92b4f..6bceda5c 100644 --- a/test/passes/infer-types/gcd.fir +++ b/test/passes/infer-types/gcd.fir @@ -7,7 +7,7 @@ circuit top : input y : UInt output z : UInt z := sub-wrap(x, y) - ;CHECK: z@<t:UInt> := sub-wrap-uu(x@<t:UInt>, y@<t:UInt>)@<t:UInt> + ;CHECK: z@<t:UInt> := sub-wrap(x@<t:UInt>, y@<t:UInt>)@<t:UInt> module gcd : input a : UInt<16> input b : UInt<16> @@ -20,7 +20,7 @@ circuit top : on-reset x := UInt(0) on-reset y := UInt(42) when gt(x, y) : - ;CHECK: when gt-uu(x@<t:UInt>, y@<t:UInt>)@<t:UInt> : + ;CHECK: when gt(x@<t:UInt>, y@<t:UInt>)@<t:UInt> : inst s of subtracter ;CHECK: inst s of subtracter@<t:{flip x : UInt@<t:UInt>, flip y : UInt@<t:UInt>, z : UInt@<t:UInt>, flip reset : UInt<1>@<t:UInt>}> s.x := x @@ -39,7 +39,7 @@ circuit top : x := a y := b v := eq(v, UInt(0)) - ;CHECK: v@<t:UInt> := eq-uu(v@<t:UInt>, UInt(0))@<t:UInt> + ;CHECK: v@<t:UInt> := eq(v@<t:UInt>, UInt(0))@<t:UInt> z := x module top : input a : UInt<16> diff --git a/test/passes/infer-types/primops.fir b/test/passes/infer-types/primops.fir index e0022cfb..05e9adf8 100644 --- a/test/passes/infer-types/primops.fir +++ b/test/passes/infer-types/primops.fir @@ -9,131 +9,131 @@ circuit top : wire d : SInt<8> wire e : UInt<1> - node vadd = add(a, c) ;CHECK: node vadd = add-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wadd-uu = add-uu(a, b) ;CHECK: node wadd-uu = add-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xadd-us = add-us(a, d) ;CHECK: node xadd-us = add-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node yadd-su = add-su(c, b) ;CHECK: node yadd-su = add-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zadd-ss = add-ss(c, d) ;CHECK: node zadd-ss = add-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vsub = sub(a, c) ;CHECK: node vsub = sub-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wsub-uu = sub-uu(a, b) ;CHECK: node wsub-uu = sub-uu(a@<t:UInt>, b@<t:UInt>)@<t:SInt> - node xsub-us = sub-us(a, d) ;CHECK: node xsub-us = sub-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node ysub-su = sub-su(c, b) ;CHECK: node ysub-su = sub-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zsub-ss = sub-ss(c, d) ;CHECK: node zsub-ss = sub-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vmul = mul(a, c) ;CHECK: node vmul = mul-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wmul-uu = mul-uu(a, b) ;CHECK: node wmul-uu = mul-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xmul-us = mul-us(a, d) ;CHECK: node xmul-us = mul-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node ymul-su = mul-su(c, b) ;CHECK: node ymul-su = mul-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zmul-ss = mul-ss(c, d) ;CHECK: node zmul-ss = mul-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vdiv = div(a, c) ;CHECK: node vdiv = div-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wdiv-uu = div-uu(a, b) ;CHECK: node wdiv-uu = div-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xdiv-us = div-us(a, d) ;CHECK: node xdiv-us = div-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node ydiv-su = div-su(c, b) ;CHECK: node ydiv-su = div-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zdiv-ss = div-ss(c, d) ;CHECK: node zdiv-ss = div-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vmod = mod(a, c) ;CHECK: node vmod = mod-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wmod-uu = mod-uu(a, b) ;CHECK: node wmod-uu = mod-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xmod-us = mod-us(a, d) ;CHECK: node xmod-us = mod-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node ymod-su = mod-su(c, b) ;CHECK: node ymod-su = mod-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zmod-ss = mod-ss(c, d) ;CHECK: node zmod-ss = mod-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vquo = quo(a, c) ;CHECK: node vquo = quo-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wquo-uu = quo-uu(a, b) ;CHECK: node wquo-uu = quo-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xquo-us = quo-us(a, d) ;CHECK: node xquo-us = quo-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node yquo-su = quo-su(c, b) ;CHECK: node yquo-su = quo-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zquo-ss = quo-ss(c, d) ;CHECK: node zquo-ss = quo-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vrem = rem(a, c) ;CHECK: node vrem = rem-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wrem-uu = rem-uu(a, b) ;CHECK: node wrem-uu = rem-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xrem-us = rem-us(a, d) ;CHECK: node xrem-us = rem-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node yrem-su = rem-su(c, b) ;CHECK: node yrem-su = rem-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zrem-ss = rem-ss(c, d) ;CHECK: node zrem-ss = rem-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vadd-wrap = add-wrap(a, c) ;CHECK: node vadd-wrap = add-wrap-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wadd-wrap-uu = add-wrap-uu(a, b) ;CHECK: node wadd-wrap-uu = add-wrap-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xadd-wrap-us = add-wrap-us(a, d) ;CHECK: node xadd-wrap-us = add-wrap-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node yadd-wrap-su = add-wrap-su(c, b) ;CHECK: node yadd-wrap-su = add-wrap-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zadd-wrap-ss = add-wrap-ss(c, d) ;CHECK: node zadd-wrap-ss = add-wrap-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vsub-wrap = sub-wrap(a, c) ;CHECK: node vsub-wrap = sub-wrap-us(a@<t:UInt>, c@<t:SInt>)@<t:SInt> - node wsub-wrap-uu = sub-wrap-uu(a, b) ;CHECK: node wsub-wrap-uu = sub-wrap-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xsub-wrap-us = sub-wrap-us(a, d) ;CHECK: node xsub-wrap-us = sub-wrap-us(a@<t:UInt>, d@<t:SInt>)@<t:SInt> - node ysub-wrap-su = sub-wrap-su(c, b) ;CHECK: node ysub-wrap-su = sub-wrap-su(c@<t:SInt>, b@<t:UInt>)@<t:SInt> - node zsub-wrap-ss = sub-wrap-ss(c, d) ;CHECK: node zsub-wrap-ss = sub-wrap-ss(c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vlt = lt(a, c) ;CHECK: node vlt = lt-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wlt-uu = lt-uu(a, b) ;CHECK: node wlt-uu = lt-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xlt-us = lt-us(a, d) ;CHECK: node xlt-us = lt-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node ylt-su = lt-su(c, b) ;CHECK: node ylt-su = lt-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zlt-ss = lt-ss(c, d) ;CHECK: node zlt-ss = lt-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vleq = leq(a, c) ;CHECK: node vleq = leq-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wleq-uu = leq-uu(a, b) ;CHECK: node wleq-uu = leq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xleq-us = leq-us(a, d) ;CHECK: node xleq-us = leq-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node yleq-su = leq-su(c, b) ;CHECK: node yleq-su = leq-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zleq-ss = leq-ss(c, d) ;CHECK: node zleq-ss = leq-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vgt = gt(a, c) ;CHECK: node vgt = gt-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wgt-uu = gt-uu(a, b) ;CHECK: node wgt-uu = gt-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xgt-us = gt-us(a, d) ;CHECK: node xgt-us = gt-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node ygt-su = gt-su(c, b) ;CHECK: node ygt-su = gt-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zgt-ss = gt-ss(c, d) ;CHECK: node zgt-ss = gt-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vgeq = geq(a, c) ;CHECK: node vgeq = geq-us(a@<t:UInt>, c@<t:SInt>)@<t:UInt> - node wgeq-uu = geq-uu(a, b) ;CHECK: node wgeq-uu = geq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node xgeq-us = geq-us(a, d) ;CHECK: node xgeq-us = geq-us(a@<t:UInt>, d@<t:SInt>)@<t:UInt> - node ygeq-su = geq-su(c, b) ;CHECK: node ygeq-su = geq-su(c@<t:SInt>, b@<t:UInt>)@<t:UInt> - node zgeq-ss = geq-ss(c, d) ;CHECK: node zgeq-ss = geq-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vneq = neq(a, b) ;CHECK: node vneq = neq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node wneq-uu = neq-uu(a, b) ;CHECK: node wneq-uu = neq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node zneq-ss = neq-ss(c, d) ;CHECK: node zneq-ss = neq-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node veq = eq(a, b) ;CHECK: node veq = eq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node weq-uu = eq-uu(a, b) ;CHECK: node weq-uu = eq-uu(a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node zeq-ss = eq-ss(c, d) ;CHECK: node zeq-ss = eq-ss(c@<t:SInt>, d@<t:SInt>)@<t:UInt> - - node vmux = mux(e, a, b) ;CHECK: node vmux = mux-uu(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node wmux-uu = mux-uu(e, a, b) ;CHECK: node wmux-uu = mux-uu(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt> - node zmux-ss = mux-ss(e, c, d) ;CHECK: node zmux-ss = mux-ss(e@<t:UInt>, c@<t:SInt>, d@<t:SInt>)@<t:SInt> - - node vpad = pad(a, 10) ;CHECK: node vpad = pad-u(a@<t:UInt>, 10)@<t:UInt> - node wpad-u = pad-u(a, 10) ;CHECK: node wpad-u = pad-u(a@<t:UInt>, 10)@<t:UInt> - node zpad-s = pad-s(c, 10) ;CHECK: node zpad-s = pad-s(c@<t:SInt>, 10)@<t:SInt> - - node vas-UInt = as-UInt(d) ;CHECK: node vas-UInt = as-UInt-s(d@<t:SInt>)@<t:UInt> - node was-UInt-u = as-UInt-u(a) ;CHECK: node was-UInt-u = as-UInt-u(a@<t:UInt>)@<t:UInt> - node zas-UInt-s = as-UInt-s(c) ;CHECK: node zas-UInt-s = as-UInt-s(c@<t:SInt>)@<t:UInt> - - node vas-SInt = as-SInt(a) ;CHECK: node vas-SInt = as-SInt-u(a@<t:UInt>)@<t:SInt> - node was-SInt-u = as-SInt-u(a) ;CHECK: node was-SInt-u = as-SInt-u(a@<t:UInt>)@<t:SInt> - node zas-SInt-s = as-SInt-s(c) ;CHECK: node zas-SInt-s = as-SInt-s(c@<t:SInt>)@<t:SInt> - - node vshl = shl(a, 10) ;CHECK: node vshl = shl-u(a@<t:UInt>, 10)@<t:UInt> - node wshl-u = shl-u(a, 10) ;CHECK: node wshl-u = shl-u(a@<t:UInt>, 10)@<t:UInt> - node zshl-s = shl-s(c, 10) ;CHECK: node zshl-s = shl-s(c@<t:SInt>, 10)@<t:SInt> - - node vdshl = dshl(a, a) ;CHECK: node vdshl = dshl-u(a@<t:UInt>, a@<t:UInt>)@<t:UInt> - node wdshl-u = dshl-u(a, a) ;CHECK: node wdshl-u = dshl-u(a@<t:UInt>, a@<t:UInt>)@<t:UInt> - node zdshl-s = dshl-s(c, a) ;CHECK: node zdshl-s = dshl-s(c@<t:SInt>, a@<t:UInt>)@<t:SInt> - - node vdshr = dshr(a, a) ;CHECK: node vdshr = dshr-u(a@<t:UInt>, a@<t:UInt>)@<t:UInt> - node wdshr-u = dshr-u(a, a) ;CHECK: node wdshr-u = dshr-u(a@<t:UInt>, a@<t:UInt>)@<t:UInt> - node zdshr-s = dshr-s(c, a) ;CHECK: node zdshr-s = dshr-s(c@<t:SInt>, a@<t:UInt>)@<t:SInt> - - node vshr = shr(a, 10) ;CHECK: node vshr = shr-u(a@<t:UInt>, 10)@<t:UInt> - node wshr-u = shr-u(a, 10) ;CHECK: node wshr-u = shr-u(a@<t:UInt>, 10)@<t:UInt> - node zshr-s = shr-s(c, 10) ;CHECK: node zshr-s = shr-s(c@<t:SInt>, 10)@<t:SInt> - - node vconvert = convert(a) ;CHECK: node vconvert = convert-u(a@<t:UInt>)@<t:SInt> - node wconvert-u = convert-u(a) ;CHECK: node wconvert-u = convert-u(a@<t:UInt>)@<t:SInt> - node zconvert-s = convert-s(c) ;CHECK: node zconvert-s = convert-s(c@<t:SInt>)@<t:SInt> - - node vneg = neg(a) ;CHECK: node vneg = neg-u(a@<t:UInt>)@<t:UInt> - node wneg-u = neg-u(a) ;CHECK: node wneg-u = neg-u(a@<t:UInt>)@<t:UInt> - node zneg-s = neg-s(c) ;CHECK: node zneg-s = neg-s(c@<t:SInt>)@<t:UInt> + node vadd = add(a, c) ;CHECK: node vadd = add(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node wadd = add(a, b) ;CHECK: node wadd = add(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xadd = add(a, d) ;CHECK: node xadd = add(a@<t:UInt>, d@<t:SInt>)@<t:SInt> + node yadd = add(c, b) ;CHECK: node yadd = add(c@<t:SInt>, b@<t:UInt>)@<t:SInt> + node zadd = add(c, d) ;CHECK: node zadd = add(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vsub = sub(a, c) ;CHECK: node vsub = sub(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node wsub = sub(a, b) ;CHECK: node wsub = sub(a@<t:UInt>, b@<t:UInt>)@<t:SInt> + node xsub = sub(a, d) ;CHECK: node xsub = sub(a@<t:UInt>, d@<t:SInt>)@<t:SInt> + node ysub = sub(c, b) ;CHECK: node ysub = sub(c@<t:SInt>, b@<t:UInt>)@<t:SInt> + node zsub = sub(c, d) ;CHECK: node zsub = sub(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vmul = mul(a, c) ;CHECK: node vmul = mul(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node wmul = mul(a, b) ;CHECK: node wmul = mul(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xmul = mul(a, d) ;CHECK: node xmul = mul(a@<t:UInt>, d@<t:SInt>)@<t:SInt> + node ymul = mul(c, b) ;CHECK: node ymul = mul(c@<t:SInt>, b@<t:UInt>)@<t:SInt> + node zmul = mul(c, d) ;CHECK: node zmul = mul(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vdiv = div(a, c) ;CHECK: node vdiv = div(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node wdiv = div(a, b) ;CHECK: node wdiv = div(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xdiv = div(a, d) ;CHECK: node xdiv = div(a@<t:UInt>, d@<t:SInt>)@<t:SInt> + node ydiv = div(c, b) ;CHECK: node ydiv = div(c@<t:SInt>, b@<t:UInt>)@<t:SInt> + node zdiv = div(c, d) ;CHECK: node zdiv = div(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vmod = mod(a, c) ;CHECK: node vmod = mod(a@<t:UInt>, c@<t:SInt>)@<t:UInt> + node wmod = mod(a, b) ;CHECK: node wmod = mod(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xmod = mod(a, d) ;CHECK: node xmod = mod(a@<t:UInt>, d@<t:SInt>)@<t:UInt> + node ymod = mod(c, b) ;CHECK: node ymod = mod(c@<t:SInt>, b@<t:UInt>)@<t:SInt> + node zmod = mod(c, d) ;CHECK: node zmod = mod(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vquo = quo(a, c) ;CHECK: node vquo = quo(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node wquo = quo(a, b) ;CHECK: node wquo = quo(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xquo = quo(a, d) ;CHECK: node xquo = quo(a@<t:UInt>, d@<t:SInt>)@<t:SInt> + node yquo = quo(c, b) ;CHECK: node yquo = quo(c@<t:SInt>, b@<t:UInt>)@<t:SInt> + node zquo = quo(c, d) ;CHECK: node zquo = quo(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vrem = rem(a, c) ;CHECK: node vrem = rem(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node wrem = rem(a, b) ;CHECK: node wrem = rem(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xrem = rem(a, d) ;CHECK: node xrem = rem(a@<t:UInt>, d@<t:SInt>)@<t:SInt> + node yrem = rem(c, b) ;CHECK: node yrem = rem(c@<t:SInt>, b@<t:UInt>)@<t:UInt> + node zrem = rem(c, d) ;CHECK: node zrem = rem(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vadd-wrap = add-wrap(a, c) ;CHECK: node vadd-wrap = add-wrap(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node wadd-wrap = add-wrap(a, b) ;CHECK: node wadd-wrap = add-wrap(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xadd-wrap = add-wrap(a, d) ;CHECK: node xadd-wrap = add-wrap(a@<t:UInt>, d@<t:SInt>)@<t:SInt> + node yadd-wrap = add-wrap(c, b) ;CHECK: node yadd-wrap = add-wrap(c@<t:SInt>, b@<t:UInt>)@<t:SInt> + node zadd-wrap = add-wrap(c, d) ;CHECK: node zadd-wrap = add-wrap(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vsub-wrap = sub-wrap(a, c) ;CHECK: node vsub-wrap = sub-wrap(a@<t:UInt>, c@<t:SInt>)@<t:SInt> + node wsub-wrap = sub-wrap(a, b) ;CHECK: node wsub-wrap = sub-wrap(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xsub-wrap = sub-wrap(a, d) ;CHECK: node xsub-wrap = sub-wrap(a@<t:UInt>, d@<t:SInt>)@<t:SInt> + node ysub-wrap = sub-wrap(c, b) ;CHECK: node ysub-wrap = sub-wrap(c@<t:SInt>, b@<t:UInt>)@<t:SInt> + node zsub-wrap = sub-wrap(c, d) ;CHECK: node zsub-wrap = sub-wrap(c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vlt = lt(a, c) ;CHECK: node vlt = lt(a@<t:UInt>, c@<t:SInt>)@<t:UInt> + node wlt = lt(a, b) ;CHECK: node wlt = lt(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xlt = lt(a, d) ;CHECK: node xlt = lt(a@<t:UInt>, d@<t:SInt>)@<t:UInt> + node ylt = lt(c, b) ;CHECK: node ylt = lt(c@<t:SInt>, b@<t:UInt>)@<t:UInt> + node zlt = lt(c, d) ;CHECK: node zlt = lt(c@<t:SInt>, d@<t:SInt>)@<t:UInt> + + node vleq = leq(a, c) ;CHECK: node vleq = leq(a@<t:UInt>, c@<t:SInt>)@<t:UInt> + node wleq = leq(a, b) ;CHECK: node wleq = leq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xleq = leq(a, d) ;CHECK: node xleq = leq(a@<t:UInt>, d@<t:SInt>)@<t:UInt> + node yleq = leq(c, b) ;CHECK: node yleq = leq(c@<t:SInt>, b@<t:UInt>)@<t:UInt> + node zleq = leq(c, d) ;CHECK: node zleq = leq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> + + node vgt = gt(a, c) ;CHECK: node vgt = gt(a@<t:UInt>, c@<t:SInt>)@<t:UInt> + node wgt = gt(a, b) ;CHECK: node wgt = gt(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xgt = gt(a, d) ;CHECK: node xgt = gt(a@<t:UInt>, d@<t:SInt>)@<t:UInt> + node ygt = gt(c, b) ;CHECK: node ygt = gt(c@<t:SInt>, b@<t:UInt>)@<t:UInt> + node zgt = gt(c, d) ;CHECK: node zgt = gt(c@<t:SInt>, d@<t:SInt>)@<t:UInt> + + node vgeq = geq(a, c) ;CHECK: node vgeq = geq(a@<t:UInt>, c@<t:SInt>)@<t:UInt> + node wgeq = geq(a, b) ;CHECK: node wgeq = geq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node xgeq = geq(a, d) ;CHECK: node xgeq = geq(a@<t:UInt>, d@<t:SInt>)@<t:UInt> + node ygeq = geq(c, b) ;CHECK: node ygeq = geq(c@<t:SInt>, b@<t:UInt>)@<t:UInt> + node zgeq = geq(c, d) ;CHECK: node zgeq = geq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> + + node vneq = neq(a, b) ;CHECK: node vneq = neq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node wneq = neq(a, b) ;CHECK: node wneq = neq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node zneq = neq(c, d) ;CHECK: node zneq = neq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> + + node veq = eq(a, b) ;CHECK: node veq = eq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node weq = eq(a, b) ;CHECK: node weq = eq(a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node zeq = eq(c, d) ;CHECK: node zeq = eq(c@<t:SInt>, d@<t:SInt>)@<t:UInt> + + node vmux = mux(e, a, b) ;CHECK: node vmux = mux(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node wmux = mux(e, a, b) ;CHECK: node wmux = mux(e@<t:UInt>, a@<t:UInt>, b@<t:UInt>)@<t:UInt> + node zmux = mux(e, c, d) ;CHECK: node zmux = mux(e@<t:UInt>, c@<t:SInt>, d@<t:SInt>)@<t:SInt> + + node vpad = pad(a, 10) ;CHECK: node vpad = pad(a@<t:UInt>, 10)@<t:UInt> + node wpad = pad(a, 10) ;CHECK: node wpad = pad(a@<t:UInt>, 10)@<t:UInt> + node zpad = pad(c, 10) ;CHECK: node zpad = pad(c@<t:SInt>, 10)@<t:SInt> + + node vas-UInt = as-UInt(d) ;CHECK: node vas-UInt = as-UInt(d@<t:SInt>)@<t:UInt> + node was-UInt = as-UInt(a) ;CHECK: node was-UInt = as-UInt(a@<t:UInt>)@<t:UInt> + node zas-UInt = as-UInt(c) ;CHECK: node zas-UInt = as-UInt(c@<t:SInt>)@<t:UInt> + + node vas-SInt = as-SInt(a) ;CHECK: node vas-SInt = as-SInt(a@<t:UInt>)@<t:SInt> + node was-SInt = as-SInt(a) ;CHECK: node was-SInt = as-SInt(a@<t:UInt>)@<t:SInt> + node zas-SInt = as-SInt(c) ;CHECK: node zas-SInt = as-SInt(c@<t:SInt>)@<t:SInt> + + node vshl = shl(a, 10) ;CHECK: node vshl = shl(a@<t:UInt>, 10)@<t:UInt> + node wshl = shl(a, 10) ;CHECK: node wshl = shl(a@<t:UInt>, 10)@<t:UInt> + node zshl = shl(c, 10) ;CHECK: node zshl = shl(c@<t:SInt>, 10)@<t:SInt> + + node vdshl = dshl(a, a) ;CHECK: node vdshl = dshl(a@<t:UInt>, a@<t:UInt>)@<t:UInt> + node wdshl = dshl(a, a) ;CHECK: node wdshl = dshl(a@<t:UInt>, a@<t:UInt>)@<t:UInt> + node zdshl = dshl(c, a) ;CHECK: node zdshl = dshl(c@<t:SInt>, a@<t:UInt>)@<t:SInt> + + node vdshr = dshr(a, a) ;CHECK: node vdshr = dshr(a@<t:UInt>, a@<t:UInt>)@<t:UInt> + node wdshr = dshr(a, a) ;CHECK: node wdshr = dshr(a@<t:UInt>, a@<t:UInt>)@<t:UInt> + node zdshr = dshr(c, a) ;CHECK: node zdshr = dshr(c@<t:SInt>, a@<t:UInt>)@<t:SInt> + + node vshr = shr(a, 10) ;CHECK: node vshr = shr(a@<t:UInt>, 10)@<t:UInt> + node wshr = shr(a, 10) ;CHECK: node wshr = shr(a@<t:UInt>, 10)@<t:UInt> + node zshr = shr(c, 10) ;CHECK: node zshr = shr(c@<t:SInt>, 10)@<t:SInt> + + node vconvert = convert(a) ;CHECK: node vconvert = convert(a@<t:UInt>)@<t:SInt> + node wconvert = convert(a) ;CHECK: node wconvert = convert(a@<t:UInt>)@<t:SInt> + node zconvert = convert(c) ;CHECK: node zconvert = convert(c@<t:SInt>)@<t:SInt> + + node vneg = neg(a) ;CHECK: node vneg = neg(a@<t:UInt>)@<t:UInt> + node wneg = neg(a) ;CHECK: node wneg = neg(a@<t:UInt>)@<t:UInt> + node zneg = neg(c) ;CHECK: node zneg = neg(c@<t:SInt>)@<t:UInt> node uand = bit-and(a, b) ;CHECK: node uand = bit-and(a@<t:UInt>, b@<t:UInt>)@<t:UInt> node vor = bit-or(a, b) ;CHECK: node vor = bit-or(a@<t:UInt>, b@<t:UInt>)@<t:UInt> diff --git a/test/passes/infer-widths/dsh.fir b/test/passes/infer-widths/dsh.fir index 871e7e8b..6b683e56 100644 --- a/test/passes/infer-widths/dsh.fir +++ b/test/passes/infer-widths/dsh.fir @@ -12,10 +12,10 @@ circuit top : wire c : UInt wire d : SInt - a := dshl-u(x,y) - b := dshl-s(z,y) - c := dshr-u(x,y) - d := dshr-s(z,y) + a := dshl(x,y) + b := dshl(z,y) + c := dshr(x,y) + d := dshr(z,y) ; CHECK: wire a : UInt<23> diff --git a/test/passes/infer-widths/gcd.fir b/test/passes/infer-widths/gcd.fir index 4d4c3575..9e4bf0f5 100644 --- a/test/passes/infer-widths/gcd.fir +++ b/test/passes/infer-widths/gcd.fir @@ -6,7 +6,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := sub-wrap-uu(x, y) + q := sub-wrap(x, y) module gcd : input a : UInt<16> input b : UInt<16> @@ -17,7 +17,7 @@ circuit top : reg y : UInt on-reset x := UInt(0) on-reset y := UInt(42) - when gt-uu(x, y) : + when gt(x, y) : inst s of subtracter s.x := x s.y := y @@ -30,7 +30,7 @@ circuit top : when e : x := a y := b - v := eq-uu(v, UInt(0)) + v := eq(v, UInt(0)) z := x module top : input a : UInt<16> diff --git a/test/passes/infer-widths/simple.fir b/test/passes/infer-widths/simple.fir index 6f3b51c9..590515e7 100644 --- a/test/passes/infer-widths/simple.fir +++ b/test/passes/infer-widths/simple.fir @@ -12,7 +12,7 @@ circuit top : wire c : UInt wire z : UInt - z := mux(c,Pad(a,?),Pad(b,?)) + z := mux(c,a,b) diff --git a/test/passes/inline/gcd.fir b/test/passes/inline/gcd.fir index 418f784b..2c76bc82 100644 --- a/test/passes/inline/gcd.fir +++ b/test/passes/inline/gcd.fir @@ -6,7 +6,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := sub-wrap-uu(x, y) + q := sub-wrap(x, y) module gcd : input a : UInt<16> input b : UInt<16> @@ -17,7 +17,7 @@ circuit top : reg y : UInt on-reset x := UInt(0) on-reset y := UInt(42) - when gt-uu(x, y) : + when gt(x, y) : inst s of subtracter s.x := x s.y := y @@ -30,7 +30,7 @@ circuit top : when e : x := a y := b - v := eq-uu(v, UInt(0)) + v := eq(v, UInt(0)) z := x module top : input a : UInt<16> diff --git a/test/passes/lower-to-ground/accessor.fir b/test/passes/lower-to-ground/accessor.fir index f15980b3..29663234 100644 --- a/test/passes/lower-to-ground/accessor.fir +++ b/test/passes/lower-to-ground/accessor.fir @@ -1,8 +1,8 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cd | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s ; CHECK: Lower To Ground circuit top : - module m : + module top : wire i : UInt<2> wire j : UInt<32> diff --git a/test/passes/lower-to-ground/bundle-vecs.fir b/test/passes/lower-to-ground/bundle-vecs.fir index a4ba1eab..0b9d9799 100644 --- a/test/passes/lower-to-ground/bundle-vecs.fir +++ b/test/passes/lower-to-ground/bundle-vecs.fir @@ -1,10 +1,10 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ; CHECK: Lower To Ground circuit top : - module q : + module top : wire i : UInt - wire j : UInt + wire j : { x : UInt<32>, flip y : UInt<32> } wire a : { x : UInt<32>, flip y : UInt<32> }[2] ; CHECK: wire a$0$x : UInt<32> diff --git a/test/passes/lower-to-ground/bundle.fir b/test/passes/lower-to-ground/bundle.fir index 722d569c..c0acfecd 100644 --- a/test/passes/lower-to-ground/bundle.fir +++ b/test/passes/lower-to-ground/bundle.fir @@ -1,42 +1,42 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cd | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s circuit top : module m : - input a : { x : UInt, flip y: SInt} - output b : { x : UInt, flip y: SInt} - module subtracter : - input c : { x : UInt[5], flip y : { x : UInt[3], flip y : SInt } } - wire a : { x : UInt, flip y : SInt} - wire b : { x : UInt, flip y : SInt} + input a : { x : UInt<5>, flip y: SInt<5>} + output b : { x : UInt<5>, flip y: SInt<5>} + module top : + input c : { x : UInt<5>[5], flip y : { x : UInt<5>[3], flip y : SInt<5> } } + wire a : { x : UInt<5>, flip y : SInt<5>} + wire b : { x : UInt<5>, flip y : SInt<5>} a := b inst i of m i.a := a b := i.b - wire d : UInt[5] + wire d : UInt<5>[5] ;CHECK: Lower To Ground ;CHECK: circuit top : ;CHECK: module m : -;CHECK: input a$x : UInt -;CHECK: output a$y : SInt -;CHECK: output b$x : UInt -;CHECK: input b$y : SInt +;CHECK: input a$x : UInt<5> +;CHECK: output a$y : SInt<5> +;CHECK: output b$x : UInt<5> +;CHECK: input b$y : SInt<5> ;CHECK: input reset : UInt<1> -;CHECK: module subtracter : -;CHECK: input c$x$0 : UInt -;CHECK: input c$x$1 : UInt -;CHECK: input c$x$2 : UInt -;CHECK: input c$x$3 : UInt -;CHECK: input c$x$4 : UInt -;CHECK: output c$y$x$0 : UInt -;CHECK: output c$y$x$1 : UInt -;CHECK: output c$y$x$2 : UInt -;CHECK: input c$y$y : SInt +;CHECK: module top : +;CHECK: input c$x$0 : UInt<5> +;CHECK: input c$x$1 : UInt<5> +;CHECK: input c$x$2 : UInt<5> +;CHECK: input c$x$3 : UInt<5> +;CHECK: input c$x$4 : UInt<5> +;CHECK: output c$y$x$0 : UInt<5> +;CHECK: output c$y$x$1 : UInt<5> +;CHECK: output c$y$x$2 : UInt<5> +;CHECK: input c$y$y : SInt<5> ;CHECK: input reset : UInt<1> -;CHECK: wire a$x : UInt -;CHECK: wire a$y : SInt -;CHECK: wire b$x : UInt -;CHECK: wire b$y : SInt +;CHECK: wire a$x : UInt<5> +;CHECK: wire a$y : SInt<5> +;CHECK: wire b$x : UInt<5> +;CHECK: wire b$y : SInt<5> ;CHECK: a$x := b$x ;CHECK: b$y := a$y ;CHECK: inst i of m @@ -45,9 +45,9 @@ circuit top : ;CHECK: a$y := i.a$y ;CHECK: b$x := i.b$x ;CHECK: i.b$y := b$y -;CHECK: wire d$0 : UInt -;CHECK: wire d$1 : UInt -;CHECK: wire d$2 : UInt -;CHECK: wire d$3 : UInt -;CHECK: wire d$4 : UInt +;CHECK: wire d$0 : UInt<5> +;CHECK: wire d$1 : UInt<5> +;CHECK: wire d$2 : UInt<5> +;CHECK: wire d$3 : UInt<5> +;CHECK: wire d$4 : UInt<5> ;CHECK: Finished Lower To Ground diff --git a/test/passes/lower-to-ground/instance.fir b/test/passes/lower-to-ground/instance.fir index 4cd9f0cc..420c3c7c 100644 --- a/test/passes/lower-to-ground/instance.fir +++ b/test/passes/lower-to-ground/instance.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p cdg | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cdg | tee %s.out | FileCheck %s circuit top : module source : diff --git a/test/passes/lower-to-ground/nested-vec.fir b/test/passes/lower-to-ground/nested-vec.fir index 95b125f6..b7915c5d 100644 --- a/test/passes/lower-to-ground/nested-vec.fir +++ b/test/passes/lower-to-ground/nested-vec.fir @@ -1,8 +1,8 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ; CHECK: Lower To Ground circuit top : - module q : + module top : wire i : UInt wire j : { x : UInt<32>, flip y : UInt<32> } wire k : { x : UInt<32>, y : UInt<32> } diff --git a/test/passes/lower-to-ground/register.fir b/test/passes/lower-to-ground/register.fir index 918710a5..a3c4f0ae 100644 --- a/test/passes/lower-to-ground/register.fir +++ b/test/passes/lower-to-ground/register.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ; CHECK: Lower To Ground circuit top : diff --git a/test/passes/lower-to-ground/test.fir b/test/passes/lower-to-ground/test.fir index 5f5f37fb..7fcf0013 100644 --- a/test/passes/lower-to-ground/test.fir +++ b/test/passes/lower-to-ground/test.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x X -p cdt | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cdt | tee %s.out | FileCheck %s ; CHECK: Done! circuit Top : @@ -8,6 +8,6 @@ circuit Top : output this : {out : {valid : UInt<1>, flip ready : UInt<1>}} inst queue of Queue this.out := queue.out - wire w : { x : UInt, flip y : UInt} - wire a : UInt + wire w : { x : UInt<5>, flip y : UInt<5>} + wire a : UInt<5> w.y := a diff --git a/test/passes/make-explicit-reset/mix-reset.fir b/test/passes/make-explicit-reset/mix-reset.fir index a255dc33..97d32397 100644 --- a/test/passes/make-explicit-reset/mix-reset.fir +++ b/test/passes/make-explicit-reset/mix-reset.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abc -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cd | tee %s.out | FileCheck %s ; CHECK: Make Explicit Reset circuit top : @@ -23,7 +23,7 @@ circuit top : ;CHECK: input reset : UInt<1> input a : UInt<16> input b : UInt<16> - output z : UInt - inst a of A - ;CHECK: a.reset := reset + output z : UInt<1> + inst x of A + ;CHECK: x.reset := reset ;CHECK: Finished Make Explicit Reset diff --git a/test/passes/resolve-genders/accessor.fir b/test/passes/resolve-genders/accessor.fir index caf7d4b3..31314148 100644 --- a/test/passes/resolve-genders/accessor.fir +++ b/test/passes/resolve-genders/accessor.fir @@ -1,9 +1,9 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdef -p cg | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cg | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : module top : - wire m : UInt<32>[10][10][10] + wire m : UInt<32>[5][5][5] wire i : UInt accessor a = m[i] ;CHECK: accessor a = m@<g:m>[i@<g:m>]@<g:m> accessor b = a[i] ;CHECK: accessor b = a@<g:m>[i@<g:m>]@<g:m> diff --git a/test/passes/resolve-genders/bigenders.fir b/test/passes/resolve-genders/bigenders.fir index 56029969..9ca5d16d 100644 --- a/test/passes/resolve-genders/bigenders.fir +++ b/test/passes/resolve-genders/bigenders.fir @@ -1,8 +1,8 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : - module M : + module top : input i : UInt<10> output o : UInt<10> wire w : {x : UInt<10>, flip y : UInt<10>} diff --git a/test/passes/resolve-genders/bulk.fir b/test/passes/resolve-genders/bulk.fir index 9688a71b..1f6b82a5 100644 --- a/test/passes/resolve-genders/bulk.fir +++ b/test/passes/resolve-genders/bulk.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : diff --git a/test/passes/resolve-genders/gcd.fir b/test/passes/resolve-genders/gcd.fir index 2f7aae73..6fbaad85 100644 --- a/test/passes/resolve-genders/gcd.fir +++ b/test/passes/resolve-genders/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdef -p cg | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cg | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : @@ -7,7 +7,7 @@ circuit top : input y : UInt output z : UInt z := sub-wrap(x, y) - ;CHECK: z@<g:f> := sub-wrap-uu(x@<g:m>, y@<g:m>) + ;CHECK: z@<g:f> := sub-wrap(x@<g:m>, y@<g:m>) module gcd : input a : UInt<16> input b : UInt<16> @@ -20,7 +20,7 @@ circuit top : on-reset x := UInt(0) on-reset y := UInt(42) when gt(x, y) : - ;CHECK: when gt-uu(x@<g:m>, y@<g:m>) : + ;CHECK: when gt(x@<g:m>, y@<g:m>) : inst s of subtracter ;CHECK: inst s of subtracter@<g:m> s.x := x diff --git a/test/passes/resolve-genders/ports.fir b/test/passes/resolve-genders/ports.fir index 9bc67c21..993b7cf2 100644 --- a/test/passes/resolve-genders/ports.fir +++ b/test/passes/resolve-genders/ports.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdef -p cg | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p cg | tee %s.out | FileCheck %s ;CHECK: Resolve Genders circuit top : diff --git a/test/passes/resolve-genders/subbundle.fir b/test/passes/resolve-genders/subbundle.fir index 6abc411a..383c2a31 100644 --- a/test/passes/resolve-genders/subbundle.fir +++ b/test/passes/resolve-genders/subbundle.fir @@ -1,8 +1,8 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefgh -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ;CHECK: Lower To Ground circuit top : - module M : + module top : wire w : { flip x : UInt<10>} reg r : { flip x : UInt<10>} w := r ; CHECK r$x := w$x diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir index 10278fdb..341910d4 100644 --- a/test/passes/resolve-kinds/gcd.fir +++ b/test/passes/resolve-kinds/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcd -p ck | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p ck | tee %s.out | FileCheck %s ; CHECK: Resolve Kinds circuit top : diff --git a/test/passes/split-exp/gcd.fir b/test/passes/split-exp/gcd.fir index 71835204..5af83202 100644 --- a/test/passes/split-exp/gcd.fir +++ b/test/passes/split-exp/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x abcdefghijklmn -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ;CHECK: Split Expressions circuit top : @@ -6,7 +6,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := sub-wrap-uu(x, y) + q := sub-wrap(x, y) module gcd : input a : UInt<16> input b : UInt<16> @@ -17,7 +17,7 @@ circuit top : reg y : UInt on-reset x := UInt(0) on-reset y := UInt(42) - when gt-uu(x, y) : + when gt(x, y) : inst s of subtracter s.x := x s.y := y @@ -30,7 +30,7 @@ circuit top : when e : x := a y := b - v := eq-uu(v, UInt(0)) + v := eq(v, UInt(0)) z := x module top : input a : UInt<16> diff --git a/test/passes/to-flo/gcd.fir b/test/passes/to-flo/gcd.fir index c8f2b268..3d5ea30f 100644 --- a/test/passes/to-flo/gcd.fir +++ b/test/passes/to-flo/gcd.fir @@ -1,4 +1,4 @@ -; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s +; RUN: firrtl -i %s -o %s.flo -X flo -p c | tee %s.out | FileCheck %s ;CHECK: Flo circuit top : @@ -6,7 +6,7 @@ circuit top : input x : UInt input y : UInt output q : UInt - q := sub-wrap-uu(x, y) + q := sub-wrap(x, y) module gcd : input a : UInt<16> input b : UInt<16> @@ -17,7 +17,7 @@ circuit top : reg y : UInt on-reset x := UInt(0) on-reset y := UInt(42) - when gt-uu(x, y) : + when gt(x, y) : inst s of subtracter s.x := x s.y := y @@ -30,7 +30,7 @@ circuit top : when e : x := a y := b - v := eq-uu(v, UInt(0)) + v := eq(v, UInt(0)) z := x module top : input a : UInt<16> |