Not finished commmit

7 files changed, 80 insertions, 21 deletions

diff --git a/TODO b/TODO
index c2a8180d..92dee2b7 100644
--- a/TODO
+++ b/TODO
@@ -24,6 +24,7 @@ Well-formed high firrtl
    UInt only has positive ints
    No combinational loops
    cannot connect to a pad, or a register. only connct to a reference
+   onreset can only handle a register
 After adding dynamic assertions, insert bounds check with accessor expansion
 Well-formed low firrtl
    All things only assigned to once
diff --git a/src/main/stanza/firrtl-ir.stanza b/src/main/stanza/firrtl-ir.stanza
index 6a0b193c..0e5400b2 100644
--- a/src/main/stanza/firrtl-ir.stanza
+++ b/src/main/stanza/firrtl-ir.stanza
@@ -193,7 +193,7 @@ public defstruct Conditionally <: Stmt :
 public defstruct Begin <: Stmt : ;LOW
    body: List<Stmt>
 public defstruct OnReset <: Stmt : ;LOW
-   reg: Expression
+   loc: Expression
    exp: Expression
 public defstruct Connect <: Stmt : ;LOW
    loc: Expression
diff --git a/src/main/stanza/ir-parser.stanza b/src/main/stanza/ir-parser.stanza
index c5296dc0..57a10f0a 100644
--- a/src/main/stanza/ir-parser.stanza
+++ b/src/main/stanza/ir-parser.stanza
@@ -263,7 +263,7 @@ defsyntax firrtl :
       stmt = (?s:#stmt/when) : s
 
       stmt = (?x:#exp := ?y:#exp!) : Connect(x, y)
-      stmt = (on-reset ?x:#exp := ?y:#exp!) : Connect(x, y);TODO
+      stmt = (on-reset ?x:#exp := ?y:#exp!) : OnReset(x, y)
 
       stmt = ((?s:#stmt ?ss:#stmt ... ?rest ...)) :
          if not empty?(rest) :
diff --git a/src/main/stanza/ir-utils.stanza b/src/main/stanza/ir-utils.stanza
index 283fe9ea..507ccf94 100644
--- a/src/main/stanza/ir-utils.stanza
+++ b/src/main/stanza/ir-utils.stanza
@@ -180,7 +180,7 @@ defmethod print (o:OutputStream, c:Stmt) :
       (c:Connect) :
          print-all(o, [loc(c) " := " exp(c)])
       (c:OnReset) :
-         print-all(o, ["on-reset " reg(c) " := " exp(c)])
+         print-all(o, ["on-reset " loc(c) " := " exp(c)])
       (c:EmptyStmt) :
          print(o, "skip")
    print-debug(o,c)
@@ -260,7 +260,7 @@ defmethod map (f: Expression -> Expression, c:Stmt) -> Stmt :
       (c:DefInstance) : DefInstance(name(c), f(module(c)))
       (c:Conditionally) : Conditionally(f(pred(c)), conseq(c), alt(c))
       (c:Connect) : Connect(f(loc(c)), f(exp(c)))
-      (c:OnReset) : OnReset(f(reg(c)),f(exp(c)))
+      (c:OnReset) : OnReset(f(loc(c)),f(exp(c)))
       (c) : c
 
 public defmulti map<?T> (f: Stmt -> Stmt, c:?T&Stmt) -> T
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 497f294d..495184e5 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -40,18 +40,27 @@ defstruct WRef <: Expression :
    kind: Kind
    gender: Gender  with: (as-method => true)
 
+defstruct WSubfield <: Expression :
+   exp: Expression
+   name: Symbol
+   type: Type with: (as-method => true)
+   gender: Gender with: (as-method => true)
+
 defstruct WRegInit <: Expression :
    reg: Expression
    name: Symbol
    type: Type with: (as-method => true)
    gender: Gender  with: (as-method => true)
 
-defstruct WSubfield <: Expression :
-   exp: Expression
-   name: Symbol
-   type: Type with: (as-method => true)
-   gender: Gender with: (as-method => true)
+defmethod map (f: Expression -> Expression, e: WRegInit) :
+   WRegInit(f(reg(e)), name(e), type(e), gender(e))
+defmethod map (f: Type -> Type, e: WRegInit) :
+   WRegInit(reg(e), name(e), f(type(e)), gender(e))   
 
+defmethod print (o:OutputStream, e:WRegInit) :
+   print-all(o,[name(e)])
+      print-debug(o,e as ?)
+   
 defstruct WIndex <: Expression :
    exp: Expression
    value: Int
@@ -219,10 +228,6 @@ defmethod print (o:OutputStream, e:WRef) :
    print(o,name(e))
    print-debug(o,e as ?)
 
-defmethod print (o:OutputStream, e:WRegInit) :
-   print-all(o,[name(e)])
-   print-debug(o,e as ?)
-
 defmethod print (o:OutputStream, e:WSubfield) :
    print-all(o,[exp(e) "." name(e)])
    print-debug(o,e as ?)
@@ -243,8 +248,6 @@ defmethod print (o:OutputStream, c:ConnectFromIndexed) :
    print-all(o, [loc(c) " := " exps(c) "[" index(c) "]"])
    print-debug(o,c as ?)
 
-defmethod map (f: Expression -> Expression, e: WRegInit) :
-   WRegInit(f(reg(e)), name(e), type(e), gender(e))
 defmethod map (f: Expression -> Expression, e: WSubfield) :
    WSubfield(f(exp(e)), name(e), type(e), gender(e))
 defmethod map (f: Expression -> Expression, e: WIndex) :
@@ -259,8 +262,6 @@ defmethod map (f: Expression -> Expression, c:ConnectFromIndexed) :
 
 defmethod map (f: Type -> Type, e: WRef) :
    WRef(name(e), f(type(e)), kind(e), gender(e))
-defmethod map (f: Type -> Type, e: WRegInit) :
-   WRegInit(reg(e), name(e), f(type(e)), gender(e))
 defmethod map (f: Type -> Type, e: WSubfield) :
    WSubfield(exp(e), name(e), f(type(e)), gender(e))
 defmethod map (f: Type -> Type, e: WIndex) :
@@ -303,9 +304,7 @@ defn to-working-ir (c:Circuit) :
    defn to-exp (e:Expression) :
       match(map(to-exp,e)) :
          (e:Ref) : WRef(name(e), type(e), NodeKind(), UNKNOWN-GENDER)
-         (e:Subfield) : 
-            if name(e) == `init : WRegInit(exp(e), to-symbol("~.init" % [name(exp(e) as WRef)]), type(e), UNKNOWN-GENDER)
-            else : WSubfield(exp(e), name(e), type(e), UNKNOWN-GENDER)
+         (e:Subfield) : WSubfield(exp(e), name(e), type(e), UNKNOWN-GENDER)
          (e:Index) : WIndex(exp(e), value(e), type(e), UNKNOWN-GENDER)
          (e) : e
    defn to-stmt (s:Stmt) :
@@ -480,7 +479,7 @@ defn infer-types (s:Stmt, l:List<KeyValue<Symbol,Type>>) -> [Stmt List<KeyValue<
         val [s*,l*] = infer-types(conseq(s),l)
         val [s**,l**] = infer-types(alt(s),l)
         [Conditionally(pred(s),s*,s**),l]
-      (s:Connect|EmptyStmt) : [s,l]
+      (s:Connect|OnReset|EmptyStmt) : [s,l]
 
 defn infer-types (m:Module, l:List<KeyValue<Symbol,Type>>) -> Module :
    val ptypes = 
@@ -568,6 +567,8 @@ defn resolve-genders (c:Circuit) :
                WDefAccessor(name(s),source*,index*,gender*)
             (s:Connect) : 
                Connect(resolve-expr(loc(s),FEMALE),resolve-expr(exp(s),MALE))
+            (s:OnReset) : 
+               OnReset(resolve-expr(loc(s),FEMALE),resolve-expr(exp(s),MALE))
             (s:Conditionally) :
                val pred* = resolve-expr(pred(s),MALE)
                val conseq* = resolve-stmt(conseq(s))
@@ -725,6 +726,16 @@ defn lower (body:Stmt, table:HashTable<Symbol,List<KeyValue<Expression,Flip>>>)
                DefWire(name(s),type(value(s))),
                Connect(WRef(name(s),type(value(s)),NodeKind(),FEMALE),value(s)))
             lower-stmt(s*)
+         (s:OnReset) : Begin{_} $
+            for (l in expand-expr(loc(s)), r in expand-expr(exp(s))) map :
+               println-debug(s)
+               val lgender = calc-gender(FEMALE,loc(s)) * value(l)
+               val rgender = calc-gender(MALE,exp(s)) * value(r)
+               println-debug(loc(s))
+               println-debug(exp(s))
+               switch fn ([x,y]) : lgender == x and rgender == y :
+                  [FEMALE,MALE]   : OnReset(key(l),key(r))
+                  [MALE,FEMALE]   : OnReset(key(r),key(l))
          (s:Connect) : Begin{_} $
             for (l in expand-expr(loc(s)), r in expand-expr(exp(s))) map :
                println-debug(s)
diff --git a/test/passes/initialize-regs/bundle-init.fir b/test/passes/initialize-regs/bundle-init.fir
new file mode 100644
index 00000000..7e9af8df
--- /dev/null
+++ b/test/passes/initialize-regs/bundle-init.fir
@@ -0,0 +1,21 @@
+; RUN: firrtl -i %s -o %s.flo -x abcdefghij -p c | tee %s.out | FileCheck %s
+; CHECK: Done!
+circuit top :
+   module A :
+      reg r : { x : UInt, flip y : UInt}
+      wire a : UInt
+      wire b : UInt
+      wire w : { x : UInt, flip y : UInt}
+
+      r.x := a
+      r.y := b
+      on-reset r := w
+      
+; CHECK: reg r : { x, flip y}
+; CHECK: r.x := a
+; CHECK: r.y := b
+; CHECK: when reset :
+; CHECK:    r.x := w.x
+; CHECK:    w.y := r.y
+
+
diff --git a/test/passes/initialize-regs/nested-whens.fir b/test/passes/initialize-regs/nested-whens.fir
new file mode 100644
index 00000000..28cbc53d
--- /dev/null
+++ b/test/passes/initialize-regs/nested-whens.fir
@@ -0,0 +1,26 @@
+; RUN: firrtl -i %s -o %s.flo -x abcdefghij -p c | tee %s.out | FileCheck %s
+; CHECK: Done!
+circuit top :
+   module A :
+      wire p : UInt
+      wire q : UInt
+      reg r : UInt
+      wire a : UInt
+      wire b : UInt
+      wire x : UInt
+      wire y : UInt
+      wire z : UInt
+
+      on-reset r := w
+      when p
+        on-reset r := x
+        r := a
+      when q
+        on-reset r := y
+        r := b
+      r := z
+      
+; CHECK: r := z
+; CHECK: when reset
+; CHECK:    r := q?b:(p?a:w)
+