tests: Decrease Dependency on Deprecated APIs (#1839)

* test: add LeanTransformSpec to replace the old SimpleTransformSpec

SimpleTransformSpec isn't simple anymore!

* AnnotationTests: remove deprecated Compiler code

* LeanTransformSpec: implicitly add right EmitCircuitAnnotation

* AsyncResetSpec: move to new lean spec

* CheckCombLoopsSpec: remove deprecated Compiler code

* ChirrtlMemSpec: remove deprecated compiler code

* CompilerTest: remove use of deprecated Compiler API

6 files changed, 114 insertions, 128 deletions

diff --git a/src/test/scala/firrtl/testutils/LeanTransformSpec.scala b/src/test/scala/firrtl/testutils/LeanTransformSpec.scala
new file mode 100644
index 00000000..c1f0943a
--- /dev/null
+++ b/src/test/scala/firrtl/testutils/LeanTransformSpec.scala
@@ -0,0 +1,50 @@
+package firrtl.testutils
+
+import firrtl.{AnnotationSeq, CircuitState, EmitCircuitAnnotation, ir}
+import firrtl.options.Dependency
+import firrtl.passes.RemoveEmpty
+import firrtl.stage.TransformManager.TransformDependency
+import logger.LazyLogging
+import org.scalatest.flatspec.AnyFlatSpec
+
+class VerilogTransformSpec extends LeanTransformSpec(Seq(Dependency[firrtl.VerilogEmitter]))
+class LowFirrtlTransformSpec extends LeanTransformSpec(Seq(Dependency[firrtl.LowFirrtlEmitter]))
+
+/** The new cool kid on the block, creates a custom compiler for your transform. */
+class LeanTransformSpec(protected val transforms: Seq[TransformDependency]) extends AnyFlatSpec with FirrtlMatchers with LazyLogging {
+  private val compiler = new firrtl.stage.transforms.Compiler(transforms)
+  private val emitterAnnos = LeanTransformSpec.deriveEmitCircuitAnnotations(transforms)
+
+  protected def compile(src: String): CircuitState = compile(src, Seq())
+  protected def compile(src: String, annos: AnnotationSeq): CircuitState = compile(firrtl.Parser.parse(src), annos)
+  protected def compile(c: ir.Circuit): CircuitState = compile(c, Seq())
+  protected def compile(c: ir.Circuit, annos: AnnotationSeq): CircuitState =
+    compiler.transform(CircuitState(c, emitterAnnos ++ annos))
+  protected def execute(input: String, check: String): CircuitState = execute(input, check ,Seq())
+  protected def execute(input: String, check: String, inAnnos: AnnotationSeq): CircuitState = {
+    val finalState = compiler.transform(CircuitState(parse(input), inAnnos))
+    val actual = RemoveEmpty.run(parse(finalState.getEmittedCircuit.value)).serialize
+    val expected = parse(check).serialize
+    logger.debug(actual)
+    logger.debug(expected)
+    actual should be (expected)
+    finalState
+  }
+}
+
+private object LeanTransformSpec {
+  private def deriveEmitCircuitAnnotations(transforms: Iterable[TransformDependency]): AnnotationSeq = {
+    val emitters = transforms.map(_.getObject()).collect{ case e: firrtl.Emitter => e }
+    emitters.map(e => EmitCircuitAnnotation(e.getClass)).toSeq
+  }
+}
+
+/** Use this if you just need to create a standard compiler and want to save some typing. */
+trait MakeCompiler {
+  protected def makeVerilogCompiler(transforms: Seq[TransformDependency] = Seq()) =
+    new firrtl.stage.transforms.Compiler(Seq(Dependency[firrtl.VerilogEmitter]) ++ transforms)
+  protected def makeMinimumVerilogCompiler(transforms: Seq[TransformDependency] = Seq()) =
+    new firrtl.stage.transforms.Compiler(Seq(Dependency[firrtl.MinimumVerilogEmitter]) ++ transforms)
+  protected def makeLowFirrtlCompiler(transforms: Seq[TransformDependency] = Seq()) =
+    new firrtl.stage.transforms.Compiler(Seq(Dependency[firrtl.LowFirrtlEmitter]) ++ transforms)
+}
\ No newline at end of file
diff --git a/src/test/scala/firrtlTests/AnnotationTests.scala b/src/test/scala/firrtlTests/AnnotationTests.scala
index 03131165..4017503e 100644
--- a/src/test/scala/firrtlTests/AnnotationTests.scala
+++ b/src/test/scala/firrtlTests/AnnotationTests.scala
@@ -7,6 +7,7 @@ import java.io.{File, FileWriter}
 import firrtl.annotations._
 import firrtl._
 import firrtl.FileUtils
+import firrtl.options.Dependency
 import firrtl.transforms.OptimizableExtModuleAnnotation
 import firrtl.passes.InlineAnnotation
 import firrtl.passes.memlib.PinAnnotation
@@ -14,24 +15,6 @@ import firrtl.util.BackendCompilationUtilities
 import firrtl.testutils._
 import org.scalatest.matchers.should.Matchers
 
-/**
- * An example methodology for testing Firrtl annotations.
- */
-trait AnnotationSpec extends LowTransformSpec {
-  // Dummy transform
-  def transform = new ResolveAndCheck
-
-  // Check if Annotation Exception is thrown
-  override def failingexecute(input: String, annotations: Seq[Annotation]): Exception = {
-    intercept[AnnotationException] {
-      compile(CircuitState(parse(input), ChirrtlForm, annotations), Seq.empty)
-    }
-  }
-  def execute(input: String, check: Annotation, annotations: Seq[Annotation]): Unit = {
-    val cr = compile(CircuitState(parse(input), ChirrtlForm, annotations), Seq.empty)
-    cr.annotations.toSeq should contain (check)
-  }
-}
 
 object AnnotationTests {
 
@@ -45,7 +28,7 @@ object AnnotationTests {
 
 // Abstract but with lots of tests defined so that we can use the same tests
 // for Legacy and newer Annotations
-abstract class AnnotationTests extends AnnotationSpec with Matchers {
+abstract class AnnotationTests extends LowFirrtlTransformSpec with Matchers with MakeCompiler {
   import AnnotationTests._
 
   def anno(s: String, value: String ="this is a value", mod: String = "Top"): Annotation
@@ -59,20 +42,22 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
          |    input b : UInt<1>
          |    node c = b""".stripMargin
     val ta = anno("c", "")
-    execute(input, ta, Seq(ta))
+    val r = compile(input, Seq(ta))
+    r.annotations.toSeq should contain (ta)
   }
 
   "Deleting annotations" should "create a DeletedAnnotation" in {
-    val compiler = new VerilogCompiler
+    val transform = Dependency[DeletingTransform]
+    val compiler = makeVerilogCompiler(Seq(transform))
     val input =
      """circuit Top :
         |  module Top :
         |    input in: UInt<3>
         |""".stripMargin
-    val transform = new DeletingTransform
-    val tname = transform.name
+
+    val tname = transform.getName
     val inlineAnn = InlineAnnotation(CircuitName("Top"))
-    val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, Seq(inlineAnn)), Seq(transform))
+    val result = compiler.transform(CircuitState(parse(input), Seq(inlineAnn)))
     result.annotations.last should matchPattern {
       case DeletedAnnotation(`tname`, `inlineAnn`) =>
     }
@@ -84,7 +69,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
   }
 
   "Renaming" should "propagate in Lowering of memories" in {
-    val compiler = new VerilogCompiler
+    val compiler = makeVerilogCompiler()
     // Uncomment to help debugging failing tests
     // Logger.setClassLogLevels(Map(compiler.getClass.getName -> LogLevel.Debug))
     val input =
@@ -104,7 +89,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
         |""".stripMargin
     val annos = Seq(anno("m.r.data.b", "sub"), anno("m.r.data", "all"), anno("m", "mem"),
                     dontTouch("Top.m"))
-    val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+    val result = compiler.transform(CircuitState(parse(input), annos))
     val resultAnno = result.annotations.toSeq
     resultAnno should contain (anno("m_a", "mem"))
     resultAnno should contain (anno("m_b_0", "mem"))
@@ -118,7 +103,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
     resultAnno should not contain (anno("r"))
   }
   "Renaming" should "propagate in RemoveChirrtl and Lowering of memories" in {
-    val compiler = new VerilogCompiler
+    val compiler = makeVerilogCompiler()
     val input =
      """circuit Top :
         |  module Top :
@@ -128,7 +113,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
         |    read mport r = m[in], clk
         |""".stripMargin
     val annos = Seq(anno("r.b", "sub"), anno("r", "all"), anno("m", "mem"), dontTouch("Top.m"))
-    val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+    val result = compiler.transform(CircuitState(parse(input), annos))
     val resultAnno = result.annotations.toSeq
     resultAnno should contain (anno("m_a", "mem"))
     resultAnno should contain (anno("m_b_0", "mem"))
@@ -143,7 +128,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
   }
 
   "Renaming" should "propagate in ZeroWidth" in {
-    val compiler = new VerilogCompiler
+    val compiler = makeVerilogCompiler()
     val input =
      """circuit Top :
         |  module Top :
@@ -158,7 +143,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
         |""".stripMargin
     val annos = Seq(anno("zero"), anno("x.a"), anno("x.b"), anno("y[0]"), anno("y[1]"),
                     anno("y[2]"), dontTouch("Top.x"))
-    val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+    val result = compiler.transform(CircuitState(parse(input), annos))
     val resultAnno = result.annotations.toSeq
     resultAnno should contain (anno("x_a"))
     resultAnno should not contain (anno("zero"))
@@ -174,7 +159,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
   }
 
   "Renaming subcomponents" should "propagate in Lowering" in {
-    val compiler = new VerilogCompiler
+    val compiler = makeVerilogCompiler()
     val input =
      """circuit Top :
         |  module Top :
@@ -198,7 +183,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
       anno("write.a"), anno("write.b[0]"), anno("write.b[1]"),
       dontTouch("Top.r"), dontTouch("Top.w"), dontTouch("Top.mem")
     )
-    val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+    val result = compiler.transform(CircuitState(parse(input), annos))
     val resultAnno = result.annotations.toSeq
     resultAnno should not contain (anno("in.a"))
     resultAnno should not contain (anno("in.b[0]"))
@@ -233,7 +218,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
   }
 
   "Renaming components" should "expand in Lowering" in {
-    val compiler = new VerilogCompiler
+    val compiler = makeVerilogCompiler()
     val input =
      """circuit Top :
         |  module Top :
@@ -248,7 +233,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
         |""".stripMargin
     val annos = Seq(anno("in"), anno("out"), anno("w"), anno("r"), dontTouch("Top.r"),
                     dontTouch("Top.w"))
-    val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+    val result = compiler.transform(CircuitState(parse(input), annos))
     val resultAnno = result.annotations.toSeq
     resultAnno should contain (anno("in_a"))
     resultAnno should contain (anno("in_b_0"))
@@ -265,7 +250,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
   }
 
   "Renaming subcomponents that aren't leaves" should "expand in Lowering" in {
-    val compiler = new VerilogCompiler
+    val compiler = makeVerilogCompiler()
     val input =
      """circuit Top :
         |  module Top :
@@ -281,7 +266,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
         |""".stripMargin
     val annos = Seq(anno("in.b"), anno("out.b"), anno("w.b"), anno("r.b"),
                     dontTouch("Top.r"), dontTouch("Top.w"))
-    val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+    val result = compiler.transform(CircuitState(parse(input), annos))
     val resultAnno = result.annotations.toSeq
     resultAnno should contain (anno("in_b_0"))
     resultAnno should contain (anno("in_b_1"))
@@ -294,7 +279,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
   }
 
   "Renaming" should "track constprop + dce" in {
-    val compiler = new VerilogCompiler
+    val compiler = makeVerilogCompiler()
     val input =
      """circuit Top :
         |  module Top :
@@ -310,7 +295,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
       anno("out.a"), anno("out.b[0]"), anno("out.b[1]"),
       anno("n.a"), anno("n.b[0]"), anno("n.b[1]")
     )
-    val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+    val result = compiler.transform(CircuitState(parse(input), annos))
     val resultAnno = result.annotations.toSeq
     resultAnno should not contain (anno("in.a"))
     resultAnno should not contain (anno("in.b[0]"))
@@ -333,7 +318,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
   }
 
   "Renaming" should "track deleted modules AND instances in dce" in {
-    val compiler = new VerilogCompiler
+    val compiler = makeVerilogCompiler()
     val input =
      """circuit Top :
         |  module Dead :
@@ -360,7 +345,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
       anno("foo", mod = "Dead"), anno("bar", mod = "Dead"),
       anno("foo", mod = "DeadExt"), anno("bar", mod = "DeadExt")
     )
-    val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+    val result = compiler.transform(CircuitState(parse(input), annos))
     /* Uncomment to help debug
     println(result.circuit.serialize)
     result.annotations.foreach{ a =>
@@ -387,7 +372,6 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
   }
 
   "Renaming" should "track deduplication" in {
-    val compiler = new VerilogCompiler
     val input =
      """circuit Top :
         |  module Child :
@@ -410,7 +394,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
     val annos = Seq(
       anno("x", mod = "Child"), anno("y", mod = "Child_1"), manno("Child"), manno("Child_1")
     )
-    val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+    val result = compile(input, annos)
     val resultAnno = result.annotations.toSeq
     resultAnno should contain (anno("x", mod = "Child"))
     resultAnno should contain (anno("y", mod = "Child"))
@@ -426,7 +410,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
   }
 
   "Annotations on empty aggregates" should "be deleted" in {
-    val compiler = new VerilogCompiler
+    val compiler = makeVerilogCompiler()
     val input =
      """circuit Top :
         |  module Top :
@@ -442,7 +426,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
       anno("x"), anno("y.bar"), anno("y.fizz"), anno("y.buzz"), anno("a"), anno("b"), anno("c"),
       anno("c[0].d"), anno("c[1].d")
     )
-    val result = compiler.compile(CircuitState(parse(input), ChirrtlForm, annos), Nil)
+    val result = compiler.transform(CircuitState(parse(input), annos))
     val resultAnno = result.annotations.toSeq
     resultAnno should contain (anno("x_foo"))
     resultAnno should not contain (anno("a"))
@@ -470,7 +454,7 @@ abstract class AnnotationTests extends AnnotationSpec with Matchers {
   }
 }
 
-class JsonAnnotationTests extends AnnotationTests with BackendCompilationUtilities {
+class JsonAnnotationTests extends AnnotationTests {
   // Helper annotations
   case class SimpleAnno(target: ComponentName, value: String) extends
       SingleTargetAnnotation[ComponentName] {
@@ -514,7 +498,7 @@ class JsonAnnotationTests extends AnnotationTests with BackendCompilationUtiliti
       |    output z : UInt<1>
       |    z <= x
       |    node y = x""".stripMargin
-    val testDir = createTestDirectory(this.getClass.getSimpleName)
+    val testDir = BackendCompilationUtilities.createTestDirectory(this.getClass.getSimpleName)
     val annoFile = new File(testDir, "anno.json")
 
     annoFileText.foreach { text =>
diff --git a/src/test/scala/firrtlTests/AsyncResetSpec.scala b/src/test/scala/firrtlTests/AsyncResetSpec.scala
index 65c68b27..70b28585 100644
--- a/src/test/scala/firrtlTests/AsyncResetSpec.scala
+++ b/src/test/scala/firrtlTests/AsyncResetSpec.scala
@@ -6,9 +6,7 @@ import firrtl._
 import firrtl.testutils._
 import FirrtlCheckers._
 
-class AsyncResetSpec extends FirrtlFlatSpec {
-  def compile(input: String): CircuitState =
-    (new VerilogCompiler).compileAndEmit(CircuitState(parse(input), ChirrtlForm), List.empty)
+class AsyncResetSpec extends VerilogTransformSpec {
   def compileBody(body: String) = {
     val str = """
       |circuit Test :
diff --git a/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala b/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala
index 6f34ceba..2016e160 100644
--- a/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala
+++ b/src/test/scala/firrtlTests/CheckCombLoopsSpec.scala
@@ -9,18 +9,10 @@ import annotations._
 import java.io.File
 import java.nio.file.Paths
 
-class CheckCombLoopsSpec extends SimpleTransformSpec {
-
-  def emitter = new LowFirrtlEmitter
-
-  def transforms = Seq(
-    new ChirrtlToHighFirrtl,
-    new IRToWorkingIR,
-    new ResolveAndCheck,
-    new HighFirrtlToMiddleFirrtl,
-    new MiddleFirrtlToLowFirrtl
-  )
+import firrtl.options.Dependency
+import firrtl.stage.FirrtlStage
 
+class CheckCombLoopsSpec extends LeanTransformSpec(Seq(Dependency[CheckCombLoops]) ){
   "Loop-free circuit" should "not throw an exception" in {
     val input = """circuit hasnoloops :
                    |  module thru :
@@ -42,8 +34,7 @@ class CheckCombLoopsSpec extends SimpleTransformSpec {
                    |    b <= inner.out2
                    |""".stripMargin
 
-    val writer = new java.io.StringWriter
-    compile(CircuitState(parse(input), ChirrtlForm), writer)
+    compile(parse(input))
   }
 
   "Simple combinational loop" should "throw an exception" in {
@@ -62,9 +53,8 @@ class CheckCombLoopsSpec extends SimpleTransformSpec {
                    |    d <= z
                    |""".stripMargin
 
-    val writer = new java.io.StringWriter
     intercept[CheckCombLoops.CombLoopException] {
-      compile(CircuitState(parse(input), ChirrtlForm), writer)
+      compile(parse(input))
     }
   }
 
@@ -77,9 +67,8 @@ class CheckCombLoopsSpec extends SimpleTransformSpec {
                    |    y <= w
                    |""".stripMargin
 
-    val writer = new java.io.StringWriter
     intercept[CheckCombLoops.CombLoopException] {
-      compile(CircuitState(parse(input), ChirrtlForm), writer)
+      compile(parse(input))
     }
   }
 
@@ -98,9 +87,8 @@ class CheckCombLoopsSpec extends SimpleTransformSpec {
                    |    d <= z
                    |""".stripMargin
 
-    val writer = new java.io.StringWriter
     intercept[CheckCombLoops.CombLoopException] {
-      compile(CircuitState(parse(input), ChirrtlForm), writer)
+      compile(parse(input))
     }
   }
 
@@ -130,9 +118,8 @@ class CheckCombLoopsSpec extends SimpleTransformSpec {
                    |    d <= z
                    |""".stripMargin
 
-    val writer = new java.io.StringWriter
     intercept[CheckCombLoops.CombLoopException] {
-      compile(CircuitState(parse(input), ChirrtlForm), writer)
+      compile(parse(input))
     }
   }
 
@@ -158,9 +145,8 @@ class CheckCombLoopsSpec extends SimpleTransformSpec {
                    |    d <= z
                    |""".stripMargin
 
-    val writer = new java.io.StringWriter
     intercept[CheckCombLoops.CombLoopException] {
-      compile(CircuitState(parse(input), ChirrtlForm), writer)
+      compile(parse(input))
     }
   }
 
@@ -187,9 +173,8 @@ class CheckCombLoopsSpec extends SimpleTransformSpec {
 
     val mt = ModuleTarget("hasloops", "blackbox")
     val annos = AnnotationSeq(Seq(ExtModulePathAnnotation(mt.ref("in"), mt.ref("out"))))
-    val writer = new java.io.StringWriter
     intercept[CheckCombLoops.CombLoopException] {
-      compile(CircuitState(parse(input), ChirrtlForm, annos), writer)
+      compile(parse(input), annos)
     }
   }
 
@@ -216,8 +201,7 @@ class CheckCombLoopsSpec extends SimpleTransformSpec {
     val annos = AnnotationSeq(Seq(
       ExtModulePathAnnotation(mt.ref("in1"), mt.ref("out1")),
       ExtModulePathAnnotation(mt.ref("in2"), mt.ref("out2"))))
-    val writer = new java.io.StringWriter
-    compile(CircuitState(parse(input), ChirrtlForm, annos), writer)
+    compile(parse(input), annos)
   }
 
   "Combinational loop through an output RHS reference" should "throw an exception" in {
@@ -244,9 +228,8 @@ class CheckCombLoopsSpec extends SimpleTransformSpec {
                    |    d <= z
                    |""".stripMargin
 
-    val writer = new java.io.StringWriter
     intercept[CheckCombLoops.CombLoopException] {
-      compile(CircuitState(parse(input), ChirrtlForm), writer)
+      compile(parse(input))
     }
   }
 
@@ -268,9 +251,8 @@ class CheckCombLoopsSpec extends SimpleTransformSpec {
                    |    o <= e
                    |""".stripMargin
 
-    val writer = new java.io.StringWriter
     intercept[CheckCombLoops.CombLoopException] {
-      compile(CircuitState(parse(input), ChirrtlForm), writer)
+      compile(parse(input))
     }
   }
 
@@ -295,8 +277,7 @@ class CheckCombLoopsSpec extends SimpleTransformSpec {
                   |    b <= inner.out2
                   |""".stripMargin
 
-    val writer = new java.io.StringWriter
-    val cs = compile(CircuitState(parse(input), ChirrtlForm), writer)
+    val cs = compile(parse(input))
     val mt = ModuleTarget("hasnoloops", "hasnoloops")
     val anno = CombinationalPath(mt.ref("b"), Seq(mt.ref("a")))
     cs.annotations.contains(anno) should be (true)
@@ -312,11 +293,11 @@ class CheckCombLoopsCommandLineSpec extends FirrtlFlatSpec {
 
   "Combinational loops detection" should "run by default" in {
     a [CheckCombLoops.CombLoopException] should be thrownBy {
-      firrtl.Driver.execute(args)
+      (new FirrtlStage).execute(args, Seq())
     }
   }
 
   it should "not run when given --no-check-comb-loops option" in {
-    firrtl.Driver.execute(args :+ "--no-check-comb-loops")
+    (new FirrtlStage).execute(args :+ "--no-check-comb-loops", Seq())
   }
 }
diff --git a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
index b22283a7..372ba53b 100644
--- a/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlMemSpec.scala
@@ -11,7 +11,7 @@ import firrtl.PrimOps.AsClock
 import firrtl.testutils._
 import firrtl.testutils.FirrtlCheckers._
 
-class ChirrtlMemSpec extends LowTransformSpec {
+class ChirrtlMemSpec extends LowFirrtlTransformSpec {
   object MemEnableCheckPass extends Pass {
     type Netlist = collection.mutable.HashMap[String, Expression]
     def buildNetlist(netlist: Netlist)(s: Statement): Statement = {
@@ -53,12 +53,6 @@ class ChirrtlMemSpec extends LowTransformSpec {
     }
   }
 
-  def transform = new SeqTransform {
-    def inputForm = LowForm
-    def outputForm = LowForm
-    def transforms = Seq(new ConstantPropagation, MemEnableCheckPass)
-  }
-
   "Sequential Memory" should "have correct enable signals" in {
     val input = """
 circuit foo :
@@ -78,7 +72,7 @@ circuit foo :
     io.out <= bar
 """.stripMargin
 
-    val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm))
+    val res = compile(parse(input))
     // Check correctness of firrtl
     parse(res.getEmittedCircuit.value)
   }
@@ -103,7 +97,7 @@ circuit foo :
     io.out <= bar
 """.stripMargin
 
-    val res = compileAndEmit(CircuitState(parse(input), ChirrtlForm))
+    val res = compile(parse(input))
     // Check correctness of firrtl
     parse(res.getEmittedCircuit.value)
   }
@@ -121,7 +115,7 @@ circuit foo :
          |    io.out <= _T_11""".stripMargin
 
     intercept[PassException]{
-      (new LowFirrtlCompiler).compile(CircuitState(parse(input), ChirrtlForm), Seq()).circuit
+      compile(parse(input))
     }.getMessage should startWith ("Undefined memory m referenced by mport _T_11")
   }
 
@@ -172,7 +166,7 @@ circuit foo :
         |      skip @[Stack.scala 19:16]
         |    io.dataOut <= out @[Stack.scala 31:14]
         """.stripMargin
-    val res = (new LowFirrtlCompiler).compile(CircuitState(parse(input), ChirrtlForm), Seq()).circuit
+    val res = compile(parse(input))
     assert(res search {
       case Connect(_, WSubField(WSubField(WRef("stack_mem", _, _, _), "_T_35",_, _), "clk", _, _), WRef("clock", _, _, _)) => true
       case Connect(_, WSubField(WSubField(WRef("stack_mem", _, _, _), "_T_17",_, _), "clk", _, _), WRef("clock", _, _, _)) => true
@@ -193,7 +187,7 @@ circuit foo :
         |      read mport bar = mem[addr], clock
         |      out <= bar
         |""".stripMargin
-    val res = (new LowFirrtlCompiler).compile(CircuitState(parse(input), ChirrtlForm), Seq()).circuit
+    val res = compile(parse(input))
     assert(res search {
       case Connect(_, WSubField(WSubField(WRef("mem", _, _, _), "bar",_, _), "clk", _, _), WRef("clock", _, _, _)) => true
     })
@@ -214,7 +208,7 @@ circuit foo :
         |      read mport bar = mem[addr], local
         |      out <= bar
         |""".stripMargin
-    val res = new LowFirrtlCompiler().compile(CircuitState(parse(input), ChirrtlForm), Seq()).circuit
+    val res = compile(parse(input))
     assert(res search {
       case Connect(_, WSubField(WSubField(WRef("mem", _, _, _), "bar",_, _), "clk", _, _), WRef("clock", _, _, _)) => true
     })
diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala
index 1f793dd2..dfa796c4 100644
--- a/src/test/scala/firrtlTests/CompilerTests.scala
+++ b/src/test/scala/firrtlTests/CompilerTests.scala
@@ -2,21 +2,12 @@
 
 package firrtlTests
 
+import firrtl.CircuitState
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
-
 import firrtl.ir.Circuit
-import firrtl.{
-  ChirrtlForm,
-  CircuitState,
-  Compiler,
-  HighFirrtlCompiler,
-  MiddleFirrtlCompiler,
-  MinimumVerilogCompiler,
-  LowFirrtlCompiler,
-  Parser,
-  VerilogCompiler
-}
+import firrtl.options.Dependency
+import firrtl.testutils.LeanTransformSpec
 import org.scalatest.flatspec.AnyFlatSpec
 import org.scalatest.matchers.should.Matchers
 
@@ -27,15 +18,9 @@ import org.scalatest.matchers.should.Matchers
  * the compiler is executed. The output of the compiler
  * should be compared against the check string.
  */
-abstract class CompilerSpec extends AnyFlatSpec {
-   def parse (s: String): Circuit = Parser.parse(s.split("\n").toIterator)
-   def compiler: Compiler
+abstract class CompilerSpec(emitter: Dependency[firrtl.Emitter]) extends LeanTransformSpec(Seq(emitter)) {
    def input: String
-   def check: String
-   def getOutput: String = {
-     val res = compiler.compileAndEmit(CircuitState(parse(input), ChirrtlForm))
-     res.getEmittedCircuit.value
-   }
+   def getOutput: String = compile(input).getEmittedCircuit.value
 }
 
 /**
@@ -46,8 +31,7 @@ abstract class CompilerSpec extends AnyFlatSpec {
  * is parsed again and compared (in-memory) to the parsed
  * input.
  */
-class HighFirrtlCompilerSpec extends CompilerSpec with Matchers {
-   val compiler = new HighFirrtlCompiler()
+class HighFirrtlCompilerSpec extends CompilerSpec(Dependency[firrtl.HighFirrtlEmitter]) with Matchers {
    val input =
 """circuit Top :
   module Top :
@@ -68,8 +52,7 @@ class HighFirrtlCompilerSpec extends CompilerSpec with Matchers {
   * a lowered (to MidForm) version of the input circuit. The output is
   * string compared to the correct lowered circuit.
   */
-class MiddleFirrtlCompilerSpec extends CompilerSpec with Matchers {
-   val compiler = new MiddleFirrtlCompiler()
+class MiddleFirrtlCompilerSpec extends CompilerSpec(Dependency[firrtl.MiddleFirrtlEmitter]) with Matchers {
    val input =
       """
 circuit Top :
@@ -104,8 +87,7 @@ circuit Top :
  * a lowered version of the input circuit. The output is
  * string compared to the correct lowered circuit.
  */
-class LowFirrtlCompilerSpec extends CompilerSpec with Matchers {
-   val compiler = new LowFirrtlCompiler()
+class LowFirrtlCompilerSpec extends CompilerSpec(Dependency[firrtl.LowFirrtlEmitter]) with Matchers {
    val input =
 """
 circuit Top :
@@ -134,7 +116,7 @@ circuit Top :
  * the corresponding Verilog. The output is string compared
  * to the correct Verilog.
  */
-class VerilogCompilerSpec extends CompilerSpec with Matchers {
+class VerilogCompilerSpec extends CompilerSpec(Dependency[firrtl.VerilogEmitter]) with Matchers {
    val input = """circuit Top :
                  |  module Top :
                  |    input a : UInt<1>[2]
@@ -150,13 +132,12 @@ class VerilogCompilerSpec extends CompilerSpec with Matchers {
                  |  assign b_1 = a_1;
                  |endmodule
                  |""".stripMargin
-   def compiler = new VerilogCompiler()
    "A circuit's verilog output" should "match the given string and not have RANDOMIZE if no invalids" in {
       getOutput should be (check)
    }
 }
 
-class MinimumVerilogCompilerSpec extends CompilerSpec with Matchers {
+class MinimumVerilogCompilerSpec extends CompilerSpec(Dependency[firrtl.MinimumVerilogEmitter]) with Matchers {
   val input = """|circuit Top:
                  |  module Top:
                  |    output b: UInt<1>[3]
@@ -184,8 +165,6 @@ class MinimumVerilogCompilerSpec extends CompilerSpec with Matchers {
                  |  assign o = {{2{i[2]}},i};
                  |endmodule
                  |""".stripMargin
-  def compiler = new MinimumVerilogCompiler()
-
   "A circuit's minimum Verilog output" should "pad signed RHSes but not reflect any const-prop or DCE" in {
     getOutput should be (check)
   }