merge

5 files changed, 95 insertions, 52 deletions

diff --git a/TODO b/TODO
index 46ee3536..1f95a8ad 100644
--- a/TODO
+++ b/TODO
@@ -2,12 +2,15 @@
 ========== ADAM's BIG ASS TODO LIST ============
 ================================================
 
-Important things:
+======== Current Tasks ========
+on-reset
+Parser
+   Error if incorrectly assign stuff, like use = instead of :=
+   Update parser and update tests
    
 ======== Update Core ==========
-Change all primops to be strict on data widths
-Update parser and update tests
 on-reset
+Change all primops to be strict on data widths
 Add source locaters
 Add Unit Tests for each pass
 
@@ -28,6 +31,8 @@ Well-formed low firrtl
    All things only assigned to once
 
 ======== Other Passes ========
+constant folding (partial eval) pass
+common subexpression elimination pass
 
 ======== Consultations ========
 Stephen:
@@ -35,11 +40,11 @@ Stephen:
       pin stephen on an example
 
 ======== Think About ========
+dlsh,drsh
 naming for split nodes
 subword accesses
 annotation system
 zero-width wires
-on-reset
 expanding mems (consider changing defmem to be size, and element type)
 Make instances always male, flip the bundles on declaration
 Multi-streams for print statements/asserts (Jack)
@@ -72,6 +77,9 @@ Bounds checks for accessors
 Overflow checks for add/add-wrap
 Check combinational
 Fast C++ where wires/register/instances are predicated
+Verilog backend - put stuff in posedge clock, not assign statements, for speedup
+Annotate mems with location stuff
+Coverage tests, such as statespace or specific instances (like asserts, sort of)
 
 ======== FIRRTL++ =========
 Variable size FIFOs
diff --git a/src/main/stanza/passes.stanza b/src/main/stanza/passes.stanza
index 42045531..e05dfe39 100644
--- a/src/main/stanza/passes.stanza
+++ b/src/main/stanza/passes.stanza
@@ -308,6 +308,49 @@ defn to-working-ir (c:Circuit) :
          for m in modules(c) map :
             Module(name(m), ports(m), to-stmt(body(m)))
 
+;=============== MAKE EXPLICIT RESET =======================
+; All modules have an implicit reset signal - however, the 
+;   programmer can explicitly reference this signal if desired.
+;   This pass makes all implicit resets explicit while
+;   preserving any previously explicit resets
+; If reset is not explicitly passed to instantiations, then this
+;   pass autmatically connects the parent module's reset to the
+;   instantiation's reset
+
+defn make-explicit-reset (c:Circuit) :
+   defn find-explicit (c:Circuit) -> List<Symbol> :
+      defn explicit? (m:Module) -> True|False :
+         for p in ports(m) any? :
+            name(p) == `reset
+      val explicit-reset = Vector<Symbol>()
+      for m in modules(c) do:
+         if explicit?(m) : add(explicit-reset,name(m))
+      to-list(explicit-reset)
+
+   defn make-explicit (m:Module, explicit-reset:List<Symbol>) -> Module :
+      defn route-reset (s:Stmt) -> Stmt :
+         match(s) :
+            (s:DefInstance) : 
+               val iref = WSubfield(WRef(name(s), UnknownType(), InstanceKind(), UNKNOWN-GENDER),`reset,UnknownType(),UNKNOWN-GENDER)
+               val pref = WRef(`reset, UnknownType(), PortKind(), MALE)
+               Begin(to-list([s,Connect(iref,pref)]))
+            (s) : map(route-reset,s)
+
+      var ports! = ports(m)
+      if not contains?(explicit-reset,name(m)) :
+         ports! = append(ports(m),list(Port(`reset,INPUT,UIntType(IntWidth(1)))))
+      val body! = route-reset(body(m))
+      Module(name(m),ports!,body!)
+      
+   defn make-explicit-reset (m:Module, c:Circuit) -> Module :
+      val explicit-reset = find-explicit(c)
+      make-explicit(m,explicit-reset)
+
+   Circuit(modules*, main(c)) where :
+      val modules* = 
+         for m in modules(c) map :
+            make-explicit-reset(m,c)
+
 ;=============== Resolve Kinds =============================
 ; It is useful for the compiler to know information about 
 ;   objects referenced. This information is stored in the kind
@@ -357,50 +400,6 @@ defn resolve-kinds (c:Circuit) :
          for m in modules(c) map :
             resolve-kinds(m,c)
 
-;=============== MAKE EXPLICIT RESET =======================
-; All modules have an implicit reset signal - however, the 
-;   programmer can explicitly reference this signal if desired.
-;   This pass makes all implicit resets explicit while
-;   preserving any previously explicit resets
-; If reset is not explicitly passed to instantiations, then this
-;   pass autmatically connects the parent module's reset to the
-;   instantiation's reset
-
-defn make-explicit-reset (c:Circuit) :
-   defn find-explicit (c:Circuit) -> List<Symbol> :
-      defn explicit? (m:Module) -> True|False :
-         for p in ports(m) any? :
-            name(p) == `reset
-      val explicit-reset = Vector<Symbol>()
-      for m in modules(c) do:
-         if explicit?(m) : add(explicit-reset,name(m))
-      to-list(explicit-reset)
-
-   defn make-explicit (m:Module, explicit-reset:List<Symbol>) -> Module :
-      defn route-reset (s:Stmt) -> Stmt :
-         match(s) :
-            (s:DefInstance) : 
-               val iref = WSubfield(WRef(name(s), UnknownType(), InstanceKind(), UNKNOWN-GENDER),`reset,UnknownType(),UNKNOWN-GENDER)
-               val pref = WRef(`reset, UnknownType(), PortKind(), MALE)
-               Begin(to-list([s,Connect(iref,pref)]))
-            (s) : map(route-reset,s)
-
-      var ports! = ports(m)
-      if not contains?(explicit-reset,name(m)) :
-         ports! = append(ports(m),list(Port(`reset,INPUT,UIntType(IntWidth(1)))))
-      val body! = route-reset(body(m))
-      Module(name(m),ports!,body!)
-      
-   defn make-explicit-reset (m:Module, c:Circuit) -> Module :
-      val explicit-reset = find-explicit(c)
-      make-explicit(m,explicit-reset)
-
-   Circuit(modules*, main(c)) where :
-      val modules* = 
-         for m in modules(c) map :
-            make-explicit-reset(m,c)
-
-
 ;============== INFER TYPES ================================
 ; This pass infers the type field in all IR nodes by updating
 ;   and passing an environment to all statements in pre-order
@@ -1977,8 +1976,8 @@ public defn run-passes (c: Circuit, p: List<Char>,file:String) :
   ;  If modules have a reset defined, must be an INPUT and UInt(1)
    if contains(p,'X') or contains(p,'a') : do-stage("Temp Elimination", temp-elimination)
    if contains(p,'X') or contains(p,'b') : do-stage("Working IR", to-working-ir)
-   if contains(p,'X') or contains(p,'c') : do-stage("Resolve Kinds", resolve-kinds)
-   if contains(p,'X') or contains(p,'d') : do-stage("Make Explicit Reset", make-explicit-reset)
+   if contains(p,'X') or contains(p,'c') : do-stage("Make Explicit Reset", make-explicit-reset)
+   if contains(p,'X') or contains(p,'d') : do-stage("Resolve Kinds", resolve-kinds)
    if contains(p,'X') or contains(p,'e') : do-stage("Infer Types", infer-types)
    if contains(p,'X') or contains(p,'f') : do-stage("Resolve Genders", resolve-genders)
    if contains(p,'X') or contains(p,'g') : do-stage("Expand Accessors", expand-accessors)
diff --git a/test/chisel3/RegisterVecShift.fir b/test/chisel3/RegisterVecShift.fir
new file mode 100644
index 00000000..7fae4c49
--- /dev/null
+++ b/test/chisel3/RegisterVecShift.fir
@@ -0,0 +1,36 @@
+; RUN: firrtl -i %s -o %s.flo -x X -p c | tee %s.out | FileCheck %s
+; CHECK: Done!
+circuit RegisterVecShift : 
+  module RegisterVecShift : 
+    input load : UInt(1)
+    output out : UInt(4)
+    input shift : UInt(1)
+    input ins : UInt(4)[4]
+    
+    reg delays : UInt(4)[4]
+    when reset : 
+      node T_39 = UInt(0, 4)
+      node T_40 = UInt(0, 4)
+      node T_41 = UInt(0, 4)
+      node T_42 = UInt(0, 4)
+      wire T_43 : UInt(4)[4]
+      T_43.0 := T_39
+      T_43.1 := T_40
+      T_43.2 := T_41
+      T_43.3 := T_42
+      delays := T_43
+    node T_44 = UInt(5, 3)
+    node T_45 = bit-and(T_44, load)
+    node T_46 = UInt(4, 3)
+    node T_47 = eq(T_45, T_46)
+    when T_47 : 
+      delays.0 := ins.0
+      delays.1 := ins.1
+      delays.2 := ins.2
+      delays.3 := ins.3
+     else : when shift : 
+        delays.0 := ins.0
+        delays.1 := delays.0
+        delays.2 := delays.1
+        delays.3 := delays.2
+    out := delays.3
diff --git a/test/passes/make-explicit-reset/mix-reset.fir b/test/passes/make-explicit-reset/mix-reset.fir
index 2f740fa2..720663c1 100644
--- a/test/passes/make-explicit-reset/mix-reset.fir
+++ b/test/passes/make-explicit-reset/mix-reset.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abcd -p c | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x abc -p c | tee %s.out | FileCheck %s
 
 ; CHECK: Make Explicit Reset
 circuit top :
diff --git a/test/passes/resolve-kinds/gcd.fir b/test/passes/resolve-kinds/gcd.fir
index e1a05236..4ad23a6a 100644
--- a/test/passes/resolve-kinds/gcd.fir
+++ b/test/passes/resolve-kinds/gcd.fir
@@ -1,4 +1,4 @@
-; RUN: firrtl -i %s -o %s.flo -x abc -p ck | tee %s.out | FileCheck %s
+; RUN: firrtl -i %s -o %s.flo -x abcd -p ck | tee %s.out | FileCheck %s
 
 ; CHECK: Resolve Kinds
 circuit top :