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| author | Kevin Laeufer | 2020-06-24 10:30:37 -0700 |
|---|---|---|
| committer | GitHub | 2020-06-24 17:30:37 +0000 |
| commit | 04f60431454f030c03dd196e276d97fccc7e6c64 (patch) | |
| tree | 3e0f224651547f1a257535afb870a57fdfba3c42 | |
| parent | e0e685685074c493ea077bccacbbec9b5b2d33ee (diff) | |
verification: clarify the meaning of verification statement in warning message (#1717)
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
| -rw-r--r-- | src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala b/src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala index 9bf4f779..40626765 100644 --- a/src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala +++ b/src/main/scala/firrtl/transforms/formal/RemoveVerificationStatements.scala @@ -44,6 +44,7 @@ class RemoveVerificationStatements extends Transform val newState = state.copy(circuit = run(state.circuit)) if (removedCounter > 0) { StageUtils.dramaticWarning(s"$removedCounter verification statements " + + "(assert, assume or cover) " + "were removed when compiling to Verilog because the basic Verilog " + "standard does not support them. If this was not intended, compile " + "to System Verilog instead using the `-X sverilog` compiler flag.") |