diff options
| author | Schuyler Eldridge | 2020-07-14 16:34:45 -0400 |
|---|---|---|
| committer | GitHub | 2020-07-14 20:34:45 +0000 |
| commit | 005a3d1644742029e744a64c2d9c452969bc64ff (patch) | |
| tree | 12aff2feeb7a456e84369966041adfcaa3d2947b | |
| parent | 63bfb32c72e4db52bd376b3fd96bb0247ee167fb (diff) | |
Make TopWiringTransform run before LowerTypes (#1750)
Add an optionalPrerequisiteOf to TopWiringTransform pointing at
LowerTypes.
This fixes a bug where top-wired wire bundles with flips could result
in the top-wired, flattened bundle having every field with an "output"
direction if the TopWiringTransform is moved around in the transform
order (see FIRRTL issue #1744).
Why did this happen?
Fundamentally, this stems from the fact that LowerTypes preserves
bundle direction for ports, but destroys it for wires.
Specifically, The TopWiringTransform creates ports of the "output"
direction that are copies of the underlying type of the component
being top-wired. Before LowerTypes, the type of a bundle has direction
information via flips. After LowerTypes, the lowered ground type does
not have this information. Therefore, all the ports are ground type
outputs. Simply ensuring that TopWiringTransform must run before
LowerTypes avoids this problem.
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>
| -rw-r--r-- | src/main/scala/firrtl/transforms/TopWiring.scala | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/main/scala/firrtl/transforms/TopWiring.scala b/src/main/scala/firrtl/transforms/TopWiring.scala index 2e123803..59c494c7 100644 --- a/src/main/scala/firrtl/transforms/TopWiring.scala +++ b/src/main/scala/firrtl/transforms/TopWiring.scala @@ -4,10 +4,11 @@ package TopWiring import firrtl._ import firrtl.ir._ -import firrtl.passes.{InferTypes, ResolveKinds, ResolveFlows, ExpandConnects} +import firrtl.passes.{InferTypes, LowerTypes, ResolveKinds, ResolveFlows, ExpandConnects} import firrtl.annotations._ import firrtl.Mappers._ import firrtl.stage.Forms +import firrtl.options.Dependency import collection.mutable @@ -33,7 +34,7 @@ class TopWiringTransform extends Transform with DependencyAPIMigration { override def prerequisites = Forms.MidForm override def optionalPrerequisites = Seq.empty - override def optionalPrerequisiteOf = Forms.MidEmitters + override def optionalPrerequisiteOf = Dependency(LowerTypes) +: Forms.MidEmitters override def invalidates(a: Transform): Boolean = a match { case InferTypes | ResolveKinds | ResolveFlows | ExpandConnects => true |
