Fix issue where inlined cvt could cause crash (#2124)

Due to inlining of Boolean expressions, the following circuit is handled
directly by the VerilogEmitter:

input a: UInt<4>
input b: SInt<1>
output o: UInt<5>
o <= dshl(a, asUInt(cvt(b)))

Priot to this change, this could crash due to mishandling of cvt in the
logic to inject parentheses based on Verilog precedence rules.

This is a corner case, but similar bugs would drop up if we open up the
VerilogEmitter to more expression inlining.

0 files changed, 0 insertions, 0 deletions