sail - Formal specification language for ISAs

Age	Commit message (Expand)	Author
2018-12-20	RISVC model is now at https://github.com/rems-project/sail-riscv . Remove it ...	Robert Norton
2018-11-29	RISC-V: more tidying up of the Spike interface.	Prashanth Mundkur
2018-11-29	RISC-V: factor the execution trace.	Prashanth Mundkur
2018-11-29	RISC-V: minor cleanup of the spike interface.	Prashanth Mundkur
2018-11-29	Merge branch 'rvfi-dii' into sail2	Brian Campbell
2018-11-27	Fix memory leak in string_of_bits	Alasdair Armstrong
2018-11-21	RISC-V: allow platform ram size to be configurable.	Prashanth Mundkur
2018-11-14	Add option to turn off RISC-V compressed instruction support	Brian Campbell
2018-11-14	Fix memory map in RVFI-DII mode	Brian Campbell
2018-11-12	rvfi_dii: take port number with option	Brian Campbell
2018-11-12	Add RVFI DII version of the RISC-V simulator for TestRIG	Brian Campbell
2018-11-07	RISC-V: add some consistency checks when run with spike.	Prashanth Mundkur
2018-10-23	RISC-V: Allow the C platform to get the DTB from a file, so that OS boot is p...	Prashanth Mundkur
2018-10-23	RISC-V: add cli option to dump the platform device-tree.	Prashanth Mundkur
2018-10-23	RISC-V: Add a platform knob to control mtval contents on illegal instruction ...	Prashanth Mundkur
2018-10-23	RISC-V: various fixes	Prashanth Mundkur
2018-10-23	RISC-V: adjust main loop for the non-spike case.	Prashanth Mundkur
2018-10-23	RISC-V: implement terminal output for C platform.	Prashanth Mundkur
2018-10-23	RISC-V: tick the clock in the C platform.	Prashanth Mundkur
2018-10-23	RISC-V: Add device tree blob into rom, currently only when linked against spike.	Prashanth Mundkur
2018-10-23	RISC-V: add default reset vector.	Prashanth Mundkur
2018-10-23	RISC-V: set htif tohost port address using ELF symbol.	Prashanth Mundkur
2018-10-23	RISC-V: Allow Spike linkage to be conditionally enabled.	Prashanth Mundkur
2018-10-23	RISC-V: flush logs at each step.	Prashanth Mundkur
2018-10-23	RISC-V: Flesh out more of the tandem checks in the C platform simulator.	Prashanth Mundkur
2018-10-23	RISC-V: An initial C Sail model linked against Spike for testing.	Prashanth Mundkur