sail - Formal specification language for ISAs

Age	Commit message (Expand)	Author
2018-12-20	RISVC model is now at https://github.com/rems-project/sail-riscv . Remove it ...	Robert Norton
2018-10-23	RISC-V: Add a platform knob to control mtval contents on illegal instruction ...	Prashanth Mundkur
2018-07-11	RISC-V model fixes for RMEM	Jon French
2018-07-10	RISCV load-acquire in Lem (-> rmem)	Jon French
2018-07-10	disable printing when compiling to Lem to keep rmem happy	Jon French
2018-07-07	An initial fix to riscv lr/sc, needs a review.	Prashanth Mundkur
2018-07-05	print to stdout not stderr to stop upsetting rmem regression tests	Jon French
2018-07-05	restore missing RISC-V fence types in sail2; ignore io bits in fences more cl...	Jon French
2018-06-26	Fix duplicate riscv mem-ea, spotted by Jon French.	Prashanth Mundkur
2018-06-25	Add a riscv platform parameter to control trapping to M-mode on misaligned ac...	Prashanth Mundkur
2018-06-22	Make riscv pte dirty-bit update handling configurable via a platform cli option.	Prashanth Mundkur
2018-06-14	rename all lem support files to sail2_foo to avoid conflict with sail1 in rmem	Jon French
2018-06-11	Use riscv platform insns_per_tick to tick the clock.	Prashanth Mundkur
2018-06-07	More definitions for the physical memory map.	Prashanth Mundkur
2018-06-07	Add terminal output to riscv platform, with incomplete handling of input.	Prashanth Mundkur
2018-06-07	Fix Lem build of RISC-V	Thomas Bauereiss
2018-05-22	Fix Lem build for RISC-V	Thomas Bauereiss
2018-04-20	Have sign_extend in common Sail Lem library, use it and zero_extend in	Brian Campbell
2018-04-18	Move a few printing functions to sail_values.lem	Thomas Bauereiss
2018-03-14	Make partiality more explicit in library functions of Lem shallow embedding	Thomas Bauereiss
2018-02-15	Rebase state monad onto prompt monad	Thomas Bauereiss