| Age | Commit message (Expand) | Author |
| 2018-05-10 | more mapping | Jon French |
| 2018-05-10 | load-type riscv assembly | Jon French |
| 2018-05-10 | rtype mapping clauses | Jon French |
| 2018-05-10 | move common mappings to riscv_types.sail | Jon French |
| 2018-05-10 | hacky monomorphic bits-string-parser for now | Jon French |
| 2018-05-10 | Merge branch 'sail2' into mappings | Jon French |
| 2018-05-10 | refining spaces mappings | Jon French |
| 2018-05-09 | Remove unused definitions. | Prashanth Mundkur |
| 2018-05-09 | start of riscv assembly mappings | Jon French |
| 2018-05-07 | Add a register indicating no trigger/breakpoint support, which allows the bre... | Prashanth Mundkur |
| 2018-05-07 | Fix a missed csr read. | Prashanth Mundkur |
| 2018-05-04 | Fix printing of ld. | Prashanth Mundkur |
| 2018-05-03 | Fix a typo in sret decode and privilege checks in xret. | Prashanth Mundkur |
| 2018-05-03 | Add implementation of sfence with a fixme note. | Prashanth Mundkur |
| 2018-05-03 | Implement wfi, and cleanup handling illegal operations. | Prashanth Mundkur |
| 2018-05-03 | Fix interrupt dispatch, improve execution logs, cleanup unused bits. | Prashanth Mundkur |
| 2018-05-03 | Fix up interrupt and exception dispatch. | Prashanth Mundkur |
| 2018-05-03 | Hook in address translation for stores and atomics. | Prashanth Mundkur |
| 2018-05-03 | Log csr writes in the execution log. | Prashanth Mundkur |
| 2018-05-02 | Hook in address translation for loads. | Prashanth Mundkur |
| 2018-05-02 | Fix printing of csr immediates. | Prashanth Mundkur |
| 2018-04-26 | Initial support for faults of writes to physical addresses. | Prashanth Mundkur |
| 2018-04-26 | Initial support for faults of reads to physical addresses. | Prashanth Mundkur |
| 2018-04-20 | Fix a typo. | Prashanth Mundkur |
| 2018-04-20 | Add a riscv instruction printer for the execution log. | Prashanth Mundkur |
| 2018-04-20 | Some cleanup and comments. | Prashanth Mundkur |
| 2018-04-17 | Implement sret. | Prashanth Mundkur |
| 2018-04-16 | Implement the s-mode views of mie/mip, and their legalizers. | Prashanth Mundkur |
| 2018-04-16 | Add the satp legalizer. | Prashanth Mundkur |
| 2018-04-13 | Add some checks of current state, and use for the xepc write legalizer. | Prashanth Mundkur |
| 2018-04-13 | Some initial legalizers for writes to S-mode CSRs. | Prashanth Mundkur |
| 2018-04-13 | Define legalizers for writes to M-mode CSRs, and hook these writes to use them. | Prashanth Mundkur |
| 2018-04-13 | Fix access checks to riscv CSRs. | Prashanth Mundkur |
| 2018-04-11 | Initial bits of supervisor state. | Prashanth Mundkur |
| 2018-04-11 | Add some misc informational m-mode registers that are used in a test. | Prashanth Mundkur |
| 2018-04-11 | More structured riscv trap vector handling. | Prashanth Mundkur |
| 2018-04-09 | Update riscv to use the new system definitions, remove duplicates. | Prashanth Mundkur |
| 2018-03-07 | Make union types consistent in the AST | Alasdair Armstrong |
| 2018-02-06 | Fixed some bugs in the RVC spec; the rvc test now passes. | Prashanth Mundkur |
| 2018-02-06 | some prettyfying of riscv: replace regbits/bits(64) with xlenbits and use ove... | Robert Norton |
| 2018-02-06 | Add remaining RVC instructions. | Prashanth Mundkur |
| 2018-02-02 | Added remaining compressed instructions in Quadrant 0 and 1, Quadrant 2 remains. | Prashanth Mundkur |
| 2018-02-02 | Add M extension to RISCV. Slightly inelegant implementation for now but passi... | Robert Norton |
| 2018-02-02 | Add some more compressed instruction specs, and slightly clean up previous ones. | Prashanth Mundkur |
| 2018-02-01 | Use the recursive execute for c.addi4spn. | Prashanth Mundkur |
| 2018-02-01 | badaddr is a misleading name, since it could contain what the PC points to fo... | Prashanth Mundkur |
| 2018-02-01 | riscv: avoid name clash with global function 'unsigned'. | Robert Norton |
| 2018-02-01 | Add c.addi4spn. | Prashanth Mundkur |
| 2018-02-01 | Fix encoding for compressed ILLEGAL. | Prashanth Mundkur |
| 2018-02-01 | Initial top-level support for compression instructions. | Prashanth Mundkur |