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AgeCommit message (Expand)Author
2018-12-20RISVC model is now at https://github.com/rems-project/sail-riscv . Remove it ...Robert Norton
2018-11-29RISC-V: implement WFI in the platform model.Prashanth Mundkur
2018-11-29RISC-V: factor the execution trace.Prashanth Mundkur
2018-11-29RISC-V: no ldu for rv64iBrian Campbell
2018-11-29RISC-V: add some missing constraints on compressed instruction encodingsBrian Campbell
2018-11-29RISC-V: add checks for misaligned targets to jumps and branchesBrian Campbell
2018-11-09RISC-V: add missed c.ebreak instructionPrashanth Mundkur
2018-11-07RISC-V: fix assembly mappings for lr/sc.Prashanth Mundkur
2018-10-23RISC-V: separate jalr execute clause for seq model and rmem.Prashanth Mundkur
2018-10-23RISC-V: Initial splitting of instructions across multiple files.Prashanth Mundkur
2018-10-23RISC-V: various fixesPrashanth Mundkur
2018-10-05RISC-V: encode/decode and assembly mappings for compressed instructionsJon French
2018-08-28fix bug in RISCV assembly mapping, incorrect order of FENCE pred/succ bitsJon French
2018-07-27Add some missing rv64i instructions, discovered when annotating the riscv isa...Prashanth Mundkur
2018-07-20Add assorted comments, consistency fixes and cleanup.Prashanth Mundkur
2018-07-12Fixed a nested comment issueShaked Flur
2018-07-11Add fixme note about riscv jalr.Prashanth Mundkur
2018-07-11Update the exception code for riscv LR after clarification on isa-dev.Prashanth Mundkur
2018-07-11RISC-V model fixes for RMEMJon French
2018-07-10correct pretty-printing using mappingsJon French
2018-07-09Support writes to misa.C in riscv.Prashanth Mundkur
2018-07-08Move the riscv analysis function into its own file for coverage purposes.Prashanth Mundkur
2018-07-07Cancel riscv reservation before i/o scheduling, tweak reservation tracing.Prashanth Mundkur
2018-07-07An initial fix to riscv lr/sc, needs a review.Prashanth Mundkur
2018-07-05Fix printing of aq/rl flags in risc-v lr/sc.Prashanth Mundkur
2018-07-05support acquire/release loads/stores in RISCV initial_analysisJon French
2018-07-05restore missing RISC-V fence types in sail2; ignore io bits in fences more cl...Jon French
2018-06-28further changes to support rmemJon French
2018-06-25Add a riscv platform parameter to control trapping to M-mode on misaligned ac...Prashanth Mundkur
2018-06-25Hook in the missed misa legalizer.Prashanth Mundkur
2018-06-25Fix a missed fixme for the sstatus view of mstatus.Prashanth Mundkur
2018-06-22More trace log tweaks.Prashanth Mundkur
2018-06-21add PMP registers to CSR, fix buildJon French
2018-06-21changes to riscv model to support rmemJon French
2018-06-11Update retire semantics for riscv WFI.Prashanth Mundkur
2018-06-11Merge branch 'sail2' into mappingsJon French
2018-06-11change double-caret for string-append-pattern to single caret, since that wou...Jon French
2018-06-11drop now-unnecessary type annotation clutter from riscv decode mappingsJon French
2018-06-09Increment minstret on instruction retires, and handle the case when the minst...Prashanth Mundkur
2018-06-09Some fixes to counteren handling.Prashanth Mundkur
2018-06-08Add counteren registers.Prashanth Mundkur
2018-06-08type checking mappings: allow inferring based on the other side's id inferencesJon French
2018-05-23riscv decode now uses mapping-decode and passes testsJon French
2018-05-21further RISCV mapping: all extant non-compressed instructions doneJon French
2018-05-18more riscv mappingJon French
2018-05-18more riscv mappings; riscv now builds successfully to lem which builds to isa...Jon French
2018-05-15Merge branch 'sail2' into mappingsJon French
2018-05-15Fix the ebreak instruction to trap, and remove the now obsolete internal exce...Prashanth Mundkur
2018-05-11...and actually workingJon French
2018-05-11further riscv mappingJon French
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