sail - Formal specification language for ISAs

Age	Commit message (Expand)	Author
2018-04-16	Implement the s-mode views of mie/mip, and their legalizers.	Prashanth Mundkur
2018-04-16	Add the satp legalizer.	Prashanth Mundkur
2018-04-13	Add some checks of current state, and use for the xepc write legalizer.	Prashanth Mundkur
2018-04-13	Some initial legalizers for writes to S-mode CSRs.	Prashanth Mundkur
2018-04-13	Define legalizers for writes to M-mode CSRs, and hook these writes to use them.	Prashanth Mundkur
2018-04-13	Fix access checks to riscv CSRs.	Prashanth Mundkur
2018-04-11	Initial bits of supervisor state.	Prashanth Mundkur
2018-04-11	Add some misc informational m-mode registers that are used in a test.	Prashanth Mundkur
2018-04-11	More structured riscv trap vector handling.	Prashanth Mundkur
2018-04-09	Update riscv to use the new system definitions, remove duplicates.	Prashanth Mundkur
2018-03-07	Make union types consistent in the AST	Alasdair Armstrong
2018-02-06	Fixed some bugs in the RVC spec; the rvc test now passes.	Prashanth Mundkur
2018-02-06	some prettyfying of riscv: replace regbits/bits(64) with xlenbits and use ove...	Robert Norton
2018-02-06	Add remaining RVC instructions.	Prashanth Mundkur
2018-02-02	Added remaining compressed instructions in Quadrant 0 and 1, Quadrant 2 remains.	Prashanth Mundkur
2018-02-02	Add M extension to RISCV. Slightly inelegant implementation for now but passi...	Robert Norton
2018-02-02	Add some more compressed instruction specs, and slightly clean up previous ones.	Prashanth Mundkur
2018-02-01	Use the recursive execute for c.addi4spn.	Prashanth Mundkur
2018-02-01	badaddr is a misleading name, since it could contain what the PC points to fo...	Prashanth Mundkur
2018-02-01	riscv: avoid name clash with global function 'unsigned'.	Robert Norton
2018-02-01	Add c.addi4spn.	Prashanth Mundkur
2018-02-01	Fix encoding for compressed ILLEGAL.	Prashanth Mundkur
2018-02-01	Initial top-level support for compression instructions.	Prashanth Mundkur
2018-01-29	Add a fixme for unhandled fences but allow them to execute.	Prashanth Mundkur
2018-01-29	Initial handling of CSR reads/writes.	Prashanth Mundkur
2018-01-29	Add satp to CSR dummy implemented predicate. Also direct the illegal instruc...	Prashanth Mundkur
2018-01-29	riscv: fix warnings about incomplete patterns. Add a check target in Makefile...	Robert Norton
2018-01-29	Merge branch 'sail2' of https://bitbucket.org/Peter_Sewell/sail into sail2	Robert Norton
2018-01-29	Added ecall/mret and exception support.	Prashanth Mundkur
2018-01-29	Fix error in RISCV: SLLI and SRLI were swapped...	Robert Norton
2018-01-25	riscv: remove case for non-existent constructor in match that was being treat...	Robert Norton
2018-01-25	work in progress riscv CSR implementation.	Robert Norton
2018-01-19	Got riscv spec to typecheck with sail2	Alasdair Armstrong
2018-01-19	riscv sail2 wip.	Robert Norton