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AgeCommit message (Expand)Author
2018-06-11drop now-unnecessary type annotation clutter from riscv decode mappingsJon French
2018-06-08type checking mappings: allow inferring based on the other side's id inferencesJon French
2018-05-23riscv decode now uses mapping-decode and passes testsJon French
2018-05-21further RISCV mapping: all extant non-compressed instructions doneJon French
2018-05-18more riscv mappingJon French
2018-05-18more riscv mappings; riscv now builds successfully to lem which builds to isa...Jon French
2018-05-15Merge branch 'sail2' into mappingsJon French
2018-05-15Fix the ebreak instruction to trap, and remove the now obsolete internal exce...Prashanth Mundkur
2018-05-11...and actually workingJon French
2018-05-11further riscv mappingJon French
2018-05-10more mappingJon French
2018-05-10load-type riscv assemblyJon French
2018-05-10rtype mapping clausesJon French
2018-05-10move common mappings to riscv_types.sailJon French
2018-05-10hacky monomorphic bits-string-parser for nowJon French
2018-05-10Merge branch 'sail2' into mappingsJon French
2018-05-10refining spaces mappingsJon French
2018-05-09Remove unused definitions.Prashanth Mundkur
2018-05-09start of riscv assembly mappingsJon French
2018-05-07Add a register indicating no trigger/breakpoint support, which allows the bre...Prashanth Mundkur
2018-05-07Fix a missed csr read.Prashanth Mundkur
2018-05-04Fix printing of ld.Prashanth Mundkur
2018-05-03Fix a typo in sret decode and privilege checks in xret.Prashanth Mundkur
2018-05-03Add implementation of sfence with a fixme note.Prashanth Mundkur
2018-05-03Implement wfi, and cleanup handling illegal operations.Prashanth Mundkur
2018-05-03Fix interrupt dispatch, improve execution logs, cleanup unused bits.Prashanth Mundkur
2018-05-03Fix up interrupt and exception dispatch.Prashanth Mundkur
2018-05-03Hook in address translation for stores and atomics.Prashanth Mundkur
2018-05-03Log csr writes in the execution log.Prashanth Mundkur
2018-05-02Hook in address translation for loads.Prashanth Mundkur
2018-05-02Fix printing of csr immediates.Prashanth Mundkur
2018-04-26Initial support for faults of writes to physical addresses.Prashanth Mundkur
2018-04-26Initial support for faults of reads to physical addresses.Prashanth Mundkur
2018-04-20Fix a typo.Prashanth Mundkur
2018-04-20Add a riscv instruction printer for the execution log.Prashanth Mundkur
2018-04-20Some cleanup and comments.Prashanth Mundkur
2018-04-17Implement sret.Prashanth Mundkur
2018-04-16Implement the s-mode views of mie/mip, and their legalizers.Prashanth Mundkur
2018-04-16Add the satp legalizer.Prashanth Mundkur
2018-04-13Add some checks of current state, and use for the xepc write legalizer.Prashanth Mundkur
2018-04-13Some initial legalizers for writes to S-mode CSRs.Prashanth Mundkur
2018-04-13Define legalizers for writes to M-mode CSRs, and hook these writes to use them.Prashanth Mundkur
2018-04-13Fix access checks to riscv CSRs.Prashanth Mundkur
2018-04-11Initial bits of supervisor state.Prashanth Mundkur
2018-04-11Add some misc informational m-mode registers that are used in a test.Prashanth Mundkur
2018-04-11More structured riscv trap vector handling.Prashanth Mundkur
2018-04-09Update riscv to use the new system definitions, remove duplicates.Prashanth Mundkur
2018-03-07Make union types consistent in the ASTAlasdair Armstrong
2018-02-06Fixed some bugs in the RVC spec; the rvc test now passes.Prashanth Mundkur
2018-02-06some prettyfying of riscv: replace regbits/bits(64) with xlenbits and use ove...Robert Norton
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