| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2018-09-21 | Remove cheri and mips specs -- they now have their own repository. | Robert Norton | |
| 2018-07-24 | Merge remote-tracking branch 'origin/sail2' into c_fixes | Alasdair Armstrong | |
| 2018-07-03 | cheri: refine lwl/lwr cap length checks to be exact. They were previously a ↵ | Robert Norton | |
| bit loose, but conservative. | |||
| 2018-06-29 | Try to fix some tricky C compilation bugs, break everything instead | Alasdair Armstrong | |
| 2018-06-25 | mips: add optional tracing of register writes (commented out). | Robert Norton | |
| 2018-06-22 | Add bitvector size constraints in MIPS | Brian Campbell | |
| 2018-05-18 | mips: add support for CP0 Config0.K0 field because a test has appeared for ↵ | Robert Norton | |
| it. This concerns cache behaviour of kernel segment k0 but since we dont have a cache we just store the value. It could be relevant to RMEM if we ever want to support kernel mode there. | |||
| 2018-05-17 | changes to for testing FreeBSD boot on MIPS: allowing loading raw file in ↵ | Robert Norton | |
| ocaml main so that we can have simboot + kernel. Support UART output only. | |||
| 2018-05-09 | Use latex support for generating cheri documentation and remove sed based ↵ | Robert Norton | |
| hack. Also some minor code cleanups and comments. | |||
| 2018-04-12 | Add implementations of CReadHwr and CWriteHwr | Robert Norton | |
| 2018-03-14 | Add and use execute_branch and execute_branch_pcc functions to align code ↵ | Robert Norton | |
| with existing MIPS and CHERI specs. | |||
| 2018-03-14 | rename EXTS and EXTZ to sign_extend and zero_extend because it is more ↵ | Robert Norton | |
| obviosu and to more closely match existing cheri pseudocode. | |||
| 2018-03-08 | rename mips_new_tc to mips | Robert Norton | |
| 2018-03-08 | Remove files in mips directory prior to copying in files from mips_new_tc. ↵ | Robert Norton | |
| Hopefully thiis will help git to spot the rename and hence preserve history. | |||
| 2018-03-01 | Add support for read_tag and write_tag in sail_lib.ml. and support for ↵ | Robert Norton | |
| intialising and dumping CHERI state. Somewhat working cheri sail2 model. | |||
| 2017-10-12 | Work around warning in ocaml shallow embedding of mips caused by buggy code ↵ | Robert Norton | |
| generation for dubious casting enumeration to int. | |||
| 2017-04-25 | Add support for uart terminal. Also add read_bit_reg function for faster and ↵ | Robert Norton | |
| neater access to registers of single bit. | |||
| 2017-04-21 | remove unnecessary cast in incrementCP0Count (run every instruction) for ↵ | Robert Norton | |
| potential speedup. | |||
| 2017-03-29 | change reqiured to work with little endian interpreter. | Robert Norton | |
| 2017-03-24 | Checkpoint work-in-progress mips sequential interpreter using ocaml shallow ↵ | Robert Norton | |
| embedding. | |||
| 2017-02-03 | Now that 128-bit capabilities are supported we must be stricter about MIPS ↵ | Robert Norton | |
| alignment | |||
| 2017-02-03 | fix headers | Peter Sewell | |
| 2017-01-24 | first pass at cheri128 sail. | Robert Norton | |
| 2016-10-20 | changes to support get_model for ppcmem. | Robert Norton | |
| 2016-09-14 | Switch mips/cheri over to using memory ea/val for writes. Tag is now first ↵ | Robert Norton | |
| byte of value for capability writes. Still need TAGw for now but should kill eventually. | |||
| 2016-07-28 | Banish exit from the mips/cheri sail except at end of SignalException ↵ | Robert Norton | |
| function. There is a plan to replace this syntax with something more understandable. Should make no functional difference using sequential interpretor but will need to do some work on exception functions when integrating with ppcmem so that it know register writes are exceptional etc. | |||
| 2016-07-26 | Increase size of TLB to 64 entries. In theory this should improve FreeBSD ↵ | Robert Norton | |
| boot time by reducing TLB misses but an apparent reduction in IPS counteracts this. Makes use of foreach and return to implement tlbSearch. | |||
| 2016-07-26 | Add support for BERI specific behaviour which permits some unaligned ↵ | Robert Norton | |
| accesses, for compatibility with clang. | |||
| 2016-07-26 | Add minimal support for emulated Altera JTAG UART. | Robert Norton | |
| 2016-07-13 | fix | Christopher | |
| 2016-06-28 | Munge exception destination PC so we hit the correct address even when ↵ | Robert Norton | |
| kcc.base is non-zero. | |||
| 2016-06-07 | remove workarounds for sail unable to read fields during PC fetch. Should be ↵ | Robert Norton | |
| no functional change. | |||
| 2016-06-07 | Fix issue in accessing fields and slices of registers during translate address | Kathy Gray | |
| 2016-06-06 | Add explicit type cast required because of the way sail does slicing (we ↵ | Robert Norton | |
| want indexing of pfn to be reset to 23..0). Kathy to investigate why this was not caught by type checker. | |||
| 2016-06-03 | Improve formatting of latex export of mips spec: wrap lines, remove dollars ↵ | Robert Norton | |
| in comments. No functional change. | |||
| 2016-06-03 | Mips file: removed some unnecessary parenthesis | Kathy Gray | |
| Interp: trying to add some debugging to isolate bug | |||
| 2016-06-03 | Reduce fill width of header to align closing comments nicely. | Robert Norton | |
| 2016-06-02 | Get widening right now that it matters | Kathy Gray | |
| 2016-06-02 | Apply headache to mips/cheri model. | Robert Norton | |
| 2016-05-25 | add support for capability load/store bits in TLB | Robert Norton | |
| 2016-05-24 | restrict virtual and physical address sizes to 40 and 36 bits respectively ↵ | Robert Norton | |
| -- this could be varied but useful for compatibility with BERI test suite. | |||
| 2016-05-19 | workaround unable to read fields in PC translation bug. | Robert Norton | |
| 2016-05-18 | Make TLB address error exception save BadVAddr. | Robert Norton | |
| 2016-05-18 | Implement 8-entry software-managed TLB. | Robert Norton | |
| 2016-05-13 | fixes to make counter interrupt work: don't attempt to read register fields ↵ | Robert Norton | |
| during instruction fetch as this is apparently broken, writing to fields also a bit dodgy. Finally only raise exception if exl and erl are not set. | |||
| 2016-05-12 | Implement count/compare registers for timer interrupts and rdhwr instruction. | Robert Norton | |
| 2016-05-12 | update/add some comments | Robert Norton | |
| 2016-05-12 | remove redundant wrapper function 'TranslateOrExit' and rename uses. | Robert Norton | |
| 2016-05-12 | Enforce kernel only access to kernel address space. Doesn't really make any ↵ | Robert Norton | |
| difference as without TLB we cannot run any non-kernel mode code anyway. | |||
| 2016-05-03 | fix cheri and mips sail following change to type of TranslateAddress -- can ↵ | Robert Norton | |
| now write registers hence call SignalException instead of returning option<err> . | |||
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index : sail | |
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