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Formal specification language for ISAs
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mips_prelude.sail
Age
Commit message (
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Author
2016-05-25
add support for capability load/store bits in TLB
Robert Norton
2016-05-24
restrict virtual and physical address sizes to 40 and 36 bits respectively --...
Robert Norton
2016-05-19
workaround unable to read fields in PC translation bug.
Robert Norton
2016-05-18
Make TLB address error exception save BadVAddr.
Robert Norton
2016-05-18
Implement 8-entry software-managed TLB.
Robert Norton
2016-05-13
fixes to make counter interrupt work: don't attempt to read register fields d...
Robert Norton
2016-05-12
Implement count/compare registers for timer interrupts and rdhwr instruction.
Robert Norton
2016-05-12
update/add some comments
Robert Norton
2016-05-12
remove redundant wrapper function 'TranslateOrExit' and rename uses.
Robert Norton
2016-05-12
Enforce kernel only access to kernel address space. Doesn't really make any d...
Robert Norton
2016-05-03
fix cheri and mips sail following change to type of TranslateAddress -- can n...
Robert Norton
2016-04-29
use the correct exception vector for ccall/creturn.
Robert Norton
2016-04-28
implement (hopefully) correct exception behaviour wrt PCC/EPCC. Required shuf...
Robert Norton
2016-04-27
cheri: add translation and bounds checking of PC via PCC. Slightly clunky imp...
Robert Norton
2016-03-07
Split mips.sail into three file and make use of the new -o option in preparat...
Robert Norton
