diff options
Diffstat (limited to 'riscv/riscv.sail')
| -rw-r--r-- | riscv/riscv.sail | 18 |
1 files changed, 2 insertions, 16 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index c0c1d6e2..47d714f5 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -61,25 +61,11 @@ union clause ast = RISCV_JALR : (bits(12), regbits, regbits) mapping clause encdec = RISCV_JALR(imm, rs1, rd) <-> imm @ rs1 @ 0b000 @ rd @ 0b1100111 -function clause execute (RISCV_JALR(imm, rs1, rd)) = { - /* write rd before anything else to prevent unintended strength */ - X(rd) = nextPC; /* compatible with JALR, C.JR and C.JALR */ - let newPC : xlenbits = X(rs1) + EXTS(imm); -/* RMEM FIXME: For the sequential model, the above definition doesn't work directly - if rs1 = rd. We would effectively have to keep a regfile for reads and another for - writes, and swap on instruction fetch. This could perhaps be optimized in - some manner, but for now, we just reorder the previous two lines to improve simulator - performance in the sequential model, as below: - let newPC : xlenbits = X(rs1) + EXTS(imm); - X(rd) = nextPC; /* compatible with JALR, C.JR and C.JALR */ -*/ - nextPC = newPC[63..1] @ 0b0; - true -} - mapping clause assembly = RISCV_JALR(imm, rs1, rd) <-> "jalr" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_12(imm) +/* see riscv_jalr_seq.sail or riscv_jalr_rmem.sail for the execute clause. */ + /* ****************************************************************** */ union clause ast = BTYPE : (bits(13), regbits, regbits, bop) |