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Diffstat (limited to 'riscv/riscv.sail')
| -rw-r--r-- | riscv/riscv.sail | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail index fb8d1c08..8d0f40f8 100644 --- a/riscv/riscv.sail +++ b/riscv/riscv.sail @@ -852,6 +852,9 @@ function readCSR csr : csreg -> xlenbits = 0xC01 => mtime, 0xC02 => minstret, + /* trigger/debug */ + 0x7a0 => ~(tselect), /* this indicates we don't have any trigger support */ + _ => { print_bits("unhandled read to CSR ", csr); 0x0000_0000_0000_0000 } } @@ -884,6 +887,9 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit = 0x144 => { mip = legalize_sip(mip, mideleg, value); Some(mip.bits()) }, 0x180 => { satp = legalize_satp(cur_Architecture(), satp, value); Some(satp) }, + /* trigger/debug */ + 0x7a0 => { tselect = value; Some(tselect) }, + _ => None() } in match res { |