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-rw-r--r--riscv/riscv.sail3
1 files changed, 0 insertions, 3 deletions
diff --git a/riscv/riscv.sail b/riscv/riscv.sail
index 8d0f40f8..374ea4a9 100644
--- a/riscv/riscv.sail
+++ b/riscv/riscv.sail
@@ -897,9 +897,6 @@ function writeCSR (csr : csreg, value : xlenbits) -> unit =
None() => print_bits("unhandled write to CSR ", csr)
}
-val signalIllegalInstruction : unit -> unit effect {escape}
-function signalIllegalInstruction () = not_implemented ("illegal instruction")
-
function clause execute CSR(csr, rs1, rd, is_imm, op) =
let rs1_val : xlenbits = if is_imm then EXTZ(rs1) else X(rs1) in
let isWrite : bool = match op {