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authorKathy Gray2014-11-23 16:17:50 +0000
committerKathy Gray2014-11-23 16:18:00 +0000
commitd3beb2f151d762aaac64a6db92d0949cd7acb557 (patch)
tree490ed1aaad31b72011baee570938cb76cfcaca24 /src
parent64e79400a4bf8489038e958e95a952668daecefc (diff)
get bits right coming out of coercion from integer
Diffstat (limited to 'src')
-rw-r--r--src/lem_interp/interp_interface.lem3
1 files changed, 1 insertions, 2 deletions
diff --git a/src/lem_interp/interp_interface.lem b/src/lem_interp/interp_interface.lem
index f28c1c02..b77e8131 100644
--- a/src/lem_interp/interp_interface.lem
+++ b/src/lem_interp/interp_interface.lem
@@ -526,8 +526,7 @@ let integer_of_bit_list b =
val bit_list_of_integer : int -> integer -> list bit
let bit_list_of_integer len b =
List.map (fun b -> if b then Bitc_one else Bitc_zero)
- (boolListFrombitSeq (natFromInt len) (bitSeqFromInteger Nothing b))
-
+ (reverse (boolListFrombitSeq (natFromInt len) (bitSeqFromInteger Nothing b))
val integer_of_byte_list : list byte -> integer
let integer_of_byte_list bytes = integer_of_bit_list (List.concatMap (fun (Byte bs) -> bs) bytes)