From d3beb2f151d762aaac64a6db92d0949cd7acb557 Mon Sep 17 00:00:00 2001
From: Kathy Gray
Date: Sun, 23 Nov 2014 16:17:50 +0000
Subject: get bits right coming out of coercion from integer

---
 src/lem_interp/interp_interface.lem | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/lem_interp/interp_interface.lem b/src/lem_interp/interp_interface.lem
index f28c1c02..b77e8131 100644
--- a/src/lem_interp/interp_interface.lem
+++ b/src/lem_interp/interp_interface.lem
@@ -526,8 +526,7 @@ let integer_of_bit_list b =
 val bit_list_of_integer : int -> integer -> list bit 
 let bit_list_of_integer len b = 
   List.map (fun b -> if b then Bitc_one else Bitc_zero) 
-    (boolListFrombitSeq (natFromInt len) (bitSeqFromInteger Nothing b))
-
+    (reverse (boolListFrombitSeq (natFromInt len) (bitSeqFromInteger Nothing b))
 
 val integer_of_byte_list : list byte -> integer 
 let integer_of_byte_list bytes = integer_of_bit_list (List.concatMap (fun (Byte bs) -> bs) bytes)
-- 
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