diff options
| author | Shaked Flur | 2017-11-01 14:17:08 +0000 |
|---|---|---|
| committer | Shaked Flur | 2017-11-01 14:17:08 +0000 |
| commit | 8e5d44d17c71cf946e65e15de8df42de2af4c652 (patch) | |
| tree | b3611980594a34c65475887377e4afb55a983526 /src/lem_interp | |
| parent | 701d572adda905e6b2098a73c9af56f98212b4a3 (diff) | |
added RISC-V "fence r,r"
Diffstat (limited to 'src/lem_interp')
| -rw-r--r-- | src/lem_interp/sail_impl_base.lem | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/src/lem_interp/sail_impl_base.lem b/src/lem_interp/sail_impl_base.lem index 4f07f574..c0ec8548 100644 --- a/src/lem_interp/sail_impl_base.lem +++ b/src/lem_interp/sail_impl_base.lem @@ -501,6 +501,7 @@ type barrier_kind = (* RISC-V barriers *) | Barrier_RISCV_rw_rw | Barrier_RISCV_r_rw + | Barrier_RISCV_r_r | Barrier_RISCV_rw_w | Barrier_RISCV_w_w | Barrier_RISCV_i @@ -525,6 +526,7 @@ instance (Show barrier_kind) | Barrier_MIPS_SYNC -> "Barrier_MIPS_SYNC" | Barrier_RISCV_rw_rw -> "Barrier_RISCV_rw_rw" | Barrier_RISCV_r_rw -> "Barrier_RISCV_r_rw" + | Barrier_RISCV_r_r -> "Barrier_RISCV_r_r" | Barrier_RISCV_rw_w -> "Barrier_RISCV_rw_w" | Barrier_RISCV_w_w -> "Barrier_RISCV_w_w" | Barrier_RISCV_i -> "Barrier_RISCV_i" @@ -621,10 +623,11 @@ instance (EnumerationType barrier_kind) | Barrier_MIPS_SYNC -> 12 | Barrier_RISCV_rw_rw -> 13 | Barrier_RISCV_r_rw -> 14 - | Barrier_RISCV_rw_w -> 15 - | Barrier_RISCV_w_w -> 16 - | Barrier_RISCV_i -> 17 - | Barrier_x86_MFENCE -> 18 + | Barrier_RISCV_r_r -> 15 + | Barrier_RISCV_rw_w -> 16 + | Barrier_RISCV_w_w -> 17 + | Barrier_RISCV_i -> 18 + | Barrier_x86_MFENCE -> 19 end end |