From 8e5d44d17c71cf946e65e15de8df42de2af4c652 Mon Sep 17 00:00:00 2001
From: Shaked Flur
Date: Wed, 1 Nov 2017 14:17:08 +0000
Subject: added RISC-V "fence r,r"

---
 src/lem_interp/sail_impl_base.lem | 11 +++++++----
 1 file changed, 7 insertions(+), 4 deletions(-)

(limited to 'src/lem_interp')

diff --git a/src/lem_interp/sail_impl_base.lem b/src/lem_interp/sail_impl_base.lem
index 4f07f574..c0ec8548 100644
--- a/src/lem_interp/sail_impl_base.lem
+++ b/src/lem_interp/sail_impl_base.lem
@@ -501,6 +501,7 @@ type barrier_kind =
   (* RISC-V barriers *)
   | Barrier_RISCV_rw_rw
   | Barrier_RISCV_r_rw
+  | Barrier_RISCV_r_r
   | Barrier_RISCV_rw_w
   | Barrier_RISCV_w_w
   | Barrier_RISCV_i
@@ -525,6 +526,7 @@ instance (Show barrier_kind)
     | Barrier_MIPS_SYNC -> "Barrier_MIPS_SYNC"
     | Barrier_RISCV_rw_rw -> "Barrier_RISCV_rw_rw"
     | Barrier_RISCV_r_rw  -> "Barrier_RISCV_r_rw"
+    | Barrier_RISCV_r_r   -> "Barrier_RISCV_r_r"
     | Barrier_RISCV_rw_w  -> "Barrier_RISCV_rw_w"
     | Barrier_RISCV_w_w   -> "Barrier_RISCV_w_w"
     | Barrier_RISCV_i     -> "Barrier_RISCV_i"
@@ -621,10 +623,11 @@ instance (EnumerationType barrier_kind)
     | Barrier_MIPS_SYNC -> 12
     | Barrier_RISCV_rw_rw -> 13
     | Barrier_RISCV_r_rw -> 14
-    | Barrier_RISCV_rw_w -> 15
-    | Barrier_RISCV_w_w -> 16
-    | Barrier_RISCV_i -> 17
-    | Barrier_x86_MFENCE -> 18
+    | Barrier_RISCV_r_r -> 15
+    | Barrier_RISCV_rw_w -> 16
+    | Barrier_RISCV_w_w -> 17
+    | Barrier_RISCV_i -> 18
+    | Barrier_x86_MFENCE -> 19
   end
 end
 
-- 
cgit v1.2.3