diff options
| author | Prashanth Mundkur | 2018-10-08 08:43:31 -0700 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-10-23 15:32:15 -0700 |
| commit | e3490924e6bce23d3d4b236fdc61c7345a17e814 (patch) | |
| tree | 20b74c110f3c30875a188c671c9e078645c9e516 /riscv/riscv_sim.c | |
| parent | 666128be44e51d6b781aedb6fdc97cd90fa59c3c (diff) | |
RISC-V: various fixes
- add mstatus to cross-check
- fix typo in assembly mapping for lr/sc
Diffstat (limited to 'riscv/riscv_sim.c')
| -rw-r--r-- | riscv/riscv_sim.c | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/riscv/riscv_sim.c b/riscv/riscv_sim.c index 17e426eb..79c353f9 100644 --- a/riscv/riscv_sim.c +++ b/riscv/riscv_sim.c @@ -247,6 +247,7 @@ int compare_states(struct tv_spike_t *s) passed &= tv_check_csr(s, CSR_MCAUSE, zmcause.zMcause_chunk_0); passed &= tv_check_csr(s, CSR_MEPC, zmepc); passed &= tv_check_csr(s, CSR_MTVAL, zmtval); + passed &= tv_check_csr(s, CSR_MSTATUS, zmstatus); passed &= tv_check_csr(s, CSR_SCAUSE, zscause.zMcause_chunk_0); passed &= tv_check_csr(s, CSR_SEPC, zsepc); |