diff options
| author | Prashanth Mundkur | 2018-11-28 15:56:08 -0800 |
|---|---|---|
| committer | Prashanth Mundkur | 2018-11-29 09:52:36 -0800 |
| commit | 35eff0805dffe8d006d390bdaebac1b8d4b0a61d (patch) | |
| tree | 500ed7eec04c75b885ca2cccafd1c7484bbb298f /riscv/riscv_sim.c | |
| parent | d4ace417655622268e5af471d8d13dd2422054f7 (diff) | |
RISC-V: factor the execution trace.
This is now split into instructions, regs, memory and platform, each
controlled individually. Currently all are enabled and not connected to
any command-line options, so a recompile is needed for trace tuning.
Diffstat (limited to 'riscv/riscv_sim.c')
| -rw-r--r-- | riscv/riscv_sim.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/riscv/riscv_sim.c b/riscv/riscv_sim.c index f632a399..038c44b6 100644 --- a/riscv/riscv_sim.c +++ b/riscv/riscv_sim.c @@ -57,6 +57,11 @@ static int rvfi_dii_sock; unsigned char *spike_dtb = NULL; size_t spike_dtb_len = 0; +bool config_print_instr = true; +bool config_print_reg = true; +bool config_print_mem_access = true; +bool config_print_platform = true; + static struct option options[] = { {"enable-dirty", no_argument, 0, 'd'}, {"enable-misaligned", no_argument, 0, 'm'}, |